diff options
Diffstat (limited to 'test/CodeGen')
54 files changed, 2310 insertions, 40 deletions
diff --git a/test/CodeGen/ARM/2009-06-30-RegScavengerAssert.ll b/test/CodeGen/ARM/2009-06-30-RegScavengerAssert.ll new file mode 100644 index 0000000..27cad7c --- /dev/null +++ b/test/CodeGen/ARM/2009-06-30-RegScavengerAssert.ll @@ -0,0 +1,122 @@ +; RUN: llvm-as < %s | llc -march=arm -mtriple=armv6-apple-darwin9 + +@nn = external global i32 ; <i32*> [#uses=1] +@al_len = external global i32 ; <i32*> [#uses=2] +@no_mat = external global i32 ; <i32*> [#uses=2] +@no_mis = external global i32 ; <i32*> [#uses=2] +@"\01LC12" = external constant [29 x i8], align 1 ; <[29 x i8]*> [#uses=1] +@"\01LC16" = external constant [33 x i8], align 1 ; <[33 x i8]*> [#uses=1] +@"\01LC17" = external constant [47 x i8], align 1 ; <[47 x i8]*> [#uses=1] + +declare arm_apcscc i32 @printf(i8* nocapture, ...) nounwind + +declare arm_apcscc void @diff(i8*, i8*, i32, i32, i32, i32) nounwind + +define arm_apcscc void @SIM(i8* %A, i8* %B, i32 %M, i32 %N, i32 %K, [256 x i32]* %V, i32 %Q, i32 %R, i32 %nseq) nounwind { +entry: + br i1 undef, label %bb5, label %bb + +bb: ; preds = %bb, %entry + br label %bb + +bb5: ; preds = %entry + br i1 undef, label %bb6, label %bb8 + +bb6: ; preds = %bb6, %bb5 + br i1 undef, label %bb8, label %bb6 + +bb8: ; preds = %bb6, %bb5 + br label %bb15 + +bb9: ; preds = %bb15 + br i1 undef, label %bb10, label %bb11 + +bb10: ; preds = %bb9 + unreachable + +bb11: ; preds = %bb9 + %0 = load i32* undef, align 4 ; <i32> [#uses=2] + %1 = add i32 %0, 1 ; <i32> [#uses=2] + store i32 %1, i32* undef, align 4 + %2 = load i32* undef, align 4 ; <i32> [#uses=1] + store i32 %2, i32* @nn, align 4 + store i32 0, i32* @al_len, align 4 + store i32 0, i32* @no_mat, align 4 + store i32 0, i32* @no_mis, align 4 + %3 = getelementptr i8* %B, i32 %0 ; <i8*> [#uses=1] + tail call arm_apcscc void @diff(i8* undef, i8* %3, i32 undef, i32 undef, i32 undef, i32 undef) nounwind + %4 = sitofp i32 undef to double ; <double> [#uses=1] + %5 = fdiv double %4, 1.000000e+01 ; <double> [#uses=1] + %6 = tail call arm_apcscc i32 (i8*, ...)* @printf(i8* getelementptr ([29 x i8]* @"\01LC12", i32 0, i32 0), double %5) nounwind ; <i32> [#uses=0] + %7 = load i32* @al_len, align 4 ; <i32> [#uses=1] + %8 = load i32* @no_mat, align 4 ; <i32> [#uses=1] + %9 = load i32* @no_mis, align 4 ; <i32> [#uses=1] + %10 = sub i32 %7, %8 ; <i32> [#uses=1] + %11 = sub i32 %10, %9 ; <i32> [#uses=1] + %12 = tail call arm_apcscc i32 (i8*, ...)* @printf(i8* getelementptr ([33 x i8]* @"\01LC16", i32 0, i32 0), i32 %11) nounwind ; <i32> [#uses=0] + %13 = tail call arm_apcscc i32 (i8*, ...)* @printf(i8* getelementptr ([47 x i8]* @"\01LC17", i32 0, i32 0), i32 undef, i32 %1, i32 undef, i32 undef) nounwind ; <i32> [#uses=0] + br i1 undef, label %bb15, label %bb12 + +bb12: ; preds = %bb11 + br label %bb228.i + +bb74.i: ; preds = %bb228.i + br i1 undef, label %bb138.i, label %bb145.i + +bb138.i: ; preds = %bb74.i + br label %bb145.i + +bb145.i: ; preds = %bb228.i, %bb138.i, %bb74.i + br i1 undef, label %bb146.i, label %bb151.i + +bb146.i: ; preds = %bb145.i + br i1 undef, label %bb228.i, label %bb151.i + +bb151.i: ; preds = %bb146.i, %bb145.i + br i1 undef, label %bb153.i, label %bb228.i + +bb153.i: ; preds = %bb151.i + br i1 undef, label %bb220.i, label %bb.nph.i98 + +bb.nph.i98: ; preds = %bb153.i + br label %bb158.i + +bb158.i: ; preds = %bb218.i, %bb.nph.i98 + br i1 undef, label %bb168.i, label %bb160.i + +bb160.i: ; preds = %bb158.i + br i1 undef, label %bb161.i, label %bb168.i + +bb161.i: ; preds = %bb160.i + br i1 undef, label %bb168.i, label %bb163.i + +bb163.i: ; preds = %bb161.i + br i1 undef, label %bb167.i, label %bb168.i + +bb167.i: ; preds = %bb163.i + br label %bb168.i + +bb168.i: ; preds = %bb167.i, %bb163.i, %bb161.i, %bb160.i, %bb158.i + br i1 undef, label %bb211.i, label %bb218.i + +bb211.i: ; preds = %bb168.i + br label %bb218.i + +bb218.i: ; preds = %bb211.i, %bb168.i + br i1 undef, label %bb220.i, label %bb158.i + +bb220.i: ; preds = %bb218.i, %bb153.i + br i1 undef, label %bb221.i, label %bb228.i + +bb221.i: ; preds = %bb220.i + br label %bb228.i + +bb228.i: ; preds = %bb221.i, %bb220.i, %bb151.i, %bb146.i, %bb12 + br i1 undef, label %bb74.i, label %bb145.i + +bb15: ; preds = %bb11, %bb8 + br i1 undef, label %return, label %bb9 + +return: ; preds = %bb15 + ret void +} diff --git a/test/CodeGen/ARM/2009-06-30-RegScavengerAssert2.ll b/test/CodeGen/ARM/2009-06-30-RegScavengerAssert2.ll new file mode 100644 index 0000000..3a14d67 --- /dev/null +++ b/test/CodeGen/ARM/2009-06-30-RegScavengerAssert2.ll @@ -0,0 +1,116 @@ +; RUN: llvm-as < %s | llc -march=arm -mtriple=armv6-apple-darwin9 + +@no_mat = external global i32 ; <i32*> [#uses=1] +@no_mis = external global i32 ; <i32*> [#uses=2] +@"\01LC11" = external constant [33 x i8], align 1 ; <[33 x i8]*> [#uses=1] +@"\01LC15" = external constant [33 x i8], align 1 ; <[33 x i8]*> [#uses=1] +@"\01LC17" = external constant [47 x i8], align 1 ; <[47 x i8]*> [#uses=1] + +declare arm_apcscc i32 @printf(i8* nocapture, ...) nounwind + +declare arm_apcscc void @diff(i8*, i8*, i32, i32, i32, i32) nounwind + +define arm_apcscc void @SIM(i8* %A, i8* %B, i32 %M, i32 %N, i32 %K, [256 x i32]* %V, i32 %Q, i32 %R, i32 %nseq) nounwind { +entry: + br i1 undef, label %bb5, label %bb + +bb: ; preds = %bb, %entry + br label %bb + +bb5: ; preds = %entry + br i1 undef, label %bb6, label %bb8 + +bb6: ; preds = %bb6, %bb5 + br i1 undef, label %bb8, label %bb6 + +bb8: ; preds = %bb6, %bb5 + br label %bb15 + +bb9: ; preds = %bb15 + br i1 undef, label %bb10, label %bb11 + +bb10: ; preds = %bb9 + unreachable + +bb11: ; preds = %bb9 + %0 = load i32* undef, align 4 ; <i32> [#uses=3] + %1 = add i32 %0, 1 ; <i32> [#uses=2] + store i32 %1, i32* undef, align 4 + %2 = load i32* undef, align 4 ; <i32> [#uses=2] + %3 = sub i32 %2, %0 ; <i32> [#uses=1] + store i32 0, i32* @no_mat, align 4 + store i32 0, i32* @no_mis, align 4 + %4 = getelementptr i8* %B, i32 %0 ; <i8*> [#uses=1] + tail call arm_apcscc void @diff(i8* undef, i8* %4, i32 undef, i32 %3, i32 undef, i32 undef) nounwind + %5 = tail call arm_apcscc i32 (i8*, ...)* @printf(i8* getelementptr ([33 x i8]* @"\01LC11", i32 0, i32 0), i32 %tmp13) nounwind ; <i32> [#uses=0] + %6 = load i32* @no_mis, align 4 ; <i32> [#uses=1] + %7 = tail call arm_apcscc i32 (i8*, ...)* @printf(i8* getelementptr ([33 x i8]* @"\01LC15", i32 0, i32 0), i32 %6) nounwind ; <i32> [#uses=0] + %8 = tail call arm_apcscc i32 (i8*, ...)* @printf(i8* getelementptr ([47 x i8]* @"\01LC17", i32 0, i32 0), i32 undef, i32 %1, i32 undef, i32 %2) nounwind ; <i32> [#uses=0] + br i1 undef, label %bb15, label %bb12 + +bb12: ; preds = %bb11 + br label %bb228.i + +bb74.i: ; preds = %bb228.i + br i1 undef, label %bb138.i, label %bb145.i + +bb138.i: ; preds = %bb74.i + br label %bb145.i + +bb145.i: ; preds = %bb228.i, %bb138.i, %bb74.i + br i1 undef, label %bb146.i, label %bb151.i + +bb146.i: ; preds = %bb145.i + br i1 undef, label %bb228.i, label %bb151.i + +bb151.i: ; preds = %bb146.i, %bb145.i + br i1 undef, label %bb153.i, label %bb228.i + +bb153.i: ; preds = %bb151.i + br i1 undef, label %bb220.i, label %bb.nph.i98 + +bb.nph.i98: ; preds = %bb153.i + br label %bb158.i + +bb158.i: ; preds = %bb218.i, %bb.nph.i98 + br i1 undef, label %bb168.i, label %bb160.i + +bb160.i: ; preds = %bb158.i + br i1 undef, label %bb161.i, label %bb168.i + +bb161.i: ; preds = %bb160.i + br i1 undef, label %bb168.i, label %bb163.i + +bb163.i: ; preds = %bb161.i + br i1 undef, label %bb167.i, label %bb168.i + +bb167.i: ; preds = %bb163.i + br label %bb168.i + +bb168.i: ; preds = %bb167.i, %bb163.i, %bb161.i, %bb160.i, %bb158.i + br i1 undef, label %bb211.i, label %bb218.i + +bb211.i: ; preds = %bb168.i + br label %bb218.i + +bb218.i: ; preds = %bb211.i, %bb168.i + br i1 undef, label %bb220.i, label %bb158.i + +bb220.i: ; preds = %bb218.i, %bb153.i + br i1 undef, label %bb221.i, label %bb228.i + +bb221.i: ; preds = %bb220.i + br label %bb228.i + +bb228.i: ; preds = %bb221.i, %bb220.i, %bb151.i, %bb146.i, %bb12 + br i1 undef, label %bb74.i, label %bb145.i + +bb15: ; preds = %bb11, %bb8 + %indvar11 = phi i32 [ 0, %bb8 ], [ %tmp13, %bb11 ] ; <i32> [#uses=2] + %tmp13 = add i32 %indvar11, 1 ; <i32> [#uses=2] + %count.0 = sub i32 undef, %indvar11 ; <i32> [#uses=0] + br i1 undef, label %return, label %bb9 + +return: ; preds = %bb15 + ret void +} diff --git a/test/CodeGen/ARM/2009-06-30-RegScavengerAssert3.ll b/test/CodeGen/ARM/2009-06-30-RegScavengerAssert3.ll new file mode 100644 index 0000000..f94b59d --- /dev/null +++ b/test/CodeGen/ARM/2009-06-30-RegScavengerAssert3.ll @@ -0,0 +1,128 @@ +; RUN: llvm-as < %s | llc -march=arm -mtriple=armv6-apple-darwin9 + +@JJ = external global i32* ; <i32**> [#uses=1] + +define arm_apcscc void @SIM(i8* %A, i8* %B, i32 %M, i32 %N, i32 %K, [256 x i32]* %V, i32 %Q, i32 %R, i32 %nseq) nounwind { +entry: + br i1 undef, label %bb5, label %bb + +bb: ; preds = %bb, %entry + br label %bb + +bb5: ; preds = %entry + br i1 undef, label %bb6, label %bb8 + +bb6: ; preds = %bb6, %bb5 + br i1 undef, label %bb8, label %bb6 + +bb8: ; preds = %bb6, %bb5 + br label %bb15 + +bb9: ; preds = %bb15 + br i1 undef, label %bb10, label %bb11 + +bb10: ; preds = %bb9 + unreachable + +bb11: ; preds = %bb9 + br i1 undef, label %bb15, label %bb12 + +bb12: ; preds = %bb11 + %0 = load i32** @JJ, align 4 ; <i32*> [#uses=1] + br label %bb228.i + +bb74.i: ; preds = %bb228.i + br i1 undef, label %bb138.i, label %bb145.i + +bb138.i: ; preds = %bb74.i + br label %bb145.i + +bb145.i: ; preds = %bb228.i, %bb138.i, %bb74.i + %cflag.0.i = phi i16 [ 0, %bb228.i ], [ 0, %bb74.i ], [ 1, %bb138.i ] ; <i16> [#uses=1] + br i1 undef, label %bb146.i, label %bb151.i + +bb146.i: ; preds = %bb145.i + br i1 undef, label %bb228.i, label %bb151.i + +bb151.i: ; preds = %bb146.i, %bb145.i + %.not297 = icmp ne i16 %cflag.0.i, 0 ; <i1> [#uses=1] + %or.cond298 = and i1 undef, %.not297 ; <i1> [#uses=1] + br i1 %or.cond298, label %bb153.i, label %bb228.i + +bb153.i: ; preds = %bb151.i + br i1 undef, label %bb220.i, label %bb.nph.i98 + +bb.nph.i98: ; preds = %bb153.i + br label %bb158.i + +bb158.i: ; preds = %bb218.i, %bb.nph.i98 + %c.1020.i = phi i32 [ 0, %bb.nph.i98 ], [ %c.14.i, %bb218.i ] ; <i32> [#uses=1] + %cflag.418.i = phi i16 [ 0, %bb.nph.i98 ], [ %cflag.3.i, %bb218.i ] ; <i16> [#uses=1] + %pj.317.i = phi i32 [ undef, %bb.nph.i98 ], [ %8, %bb218.i ] ; <i32> [#uses=1] + %pi.316.i = phi i32 [ undef, %bb.nph.i98 ], [ %7, %bb218.i ] ; <i32> [#uses=1] + %fj.515.i = phi i32 [ undef, %bb.nph.i98 ], [ %fj.4.i, %bb218.i ] ; <i32> [#uses=3] + %ci.910.i = phi i32 [ undef, %bb.nph.i98 ], [ %ci.12.i, %bb218.i ] ; <i32> [#uses=2] + %i.121.i = sub i32 undef, undef ; <i32> [#uses=3] + %tmp105.i = sub i32 undef, undef ; <i32> [#uses=1] + %1 = sub i32 %c.1020.i, undef ; <i32> [#uses=0] + br i1 undef, label %bb168.i, label %bb160.i + +bb160.i: ; preds = %bb158.i + br i1 undef, label %bb161.i, label %bb168.i + +bb161.i: ; preds = %bb160.i + br i1 undef, label %bb168.i, label %bb163.i + +bb163.i: ; preds = %bb161.i + %2 = icmp slt i32 %fj.515.i, undef ; <i1> [#uses=1] + %3 = and i1 %2, undef ; <i1> [#uses=1] + br i1 %3, label %bb167.i, label %bb168.i + +bb167.i: ; preds = %bb163.i + br label %bb168.i + +bb168.i: ; preds = %bb167.i, %bb163.i, %bb161.i, %bb160.i, %bb158.i + %fi.5.i = phi i32 [ undef, %bb167.i ], [ %ci.910.i, %bb158.i ], [ undef, %bb160.i ], [ %ci.910.i, %bb161.i ], [ undef, %bb163.i ] ; <i32> [#uses=1] + %fj.4.i = phi i32 [ undef, %bb167.i ], [ undef, %bb158.i ], [ %fj.515.i, %bb160.i ], [ undef, %bb161.i ], [ %fj.515.i, %bb163.i ] ; <i32> [#uses=2] + %scevgep88.i = getelementptr i32* null, i32 %i.121.i ; <i32*> [#uses=3] + %4 = load i32* %scevgep88.i, align 4 ; <i32> [#uses=2] + %scevgep89.i = getelementptr i32* %0, i32 %i.121.i ; <i32*> [#uses=3] + %5 = load i32* %scevgep89.i, align 4 ; <i32> [#uses=1] + %ci.10.i = select i1 undef, i32 %pi.316.i, i32 %i.121.i ; <i32> [#uses=0] + %cj.9.i = select i1 undef, i32 %pj.317.i, i32 undef ; <i32> [#uses=0] + %6 = icmp slt i32 undef, 0 ; <i1> [#uses=3] + %ci.12.i = select i1 %6, i32 %fi.5.i, i32 %4 ; <i32> [#uses=2] + %cj.11.i100 = select i1 %6, i32 %fj.4.i, i32 %5 ; <i32> [#uses=1] + %c.14.i = select i1 %6, i32 0, i32 undef ; <i32> [#uses=2] + store i32 %c.14.i, i32* undef, align 4 + %7 = load i32* %scevgep88.i, align 4 ; <i32> [#uses=1] + %8 = load i32* %scevgep89.i, align 4 ; <i32> [#uses=1] + store i32 %ci.12.i, i32* %scevgep88.i, align 4 + store i32 %cj.11.i100, i32* %scevgep89.i, align 4 + store i32 %4, i32* undef, align 4 + br i1 undef, label %bb211.i, label %bb218.i + +bb211.i: ; preds = %bb168.i + br label %bb218.i + +bb218.i: ; preds = %bb211.i, %bb168.i + %cflag.3.i = phi i16 [ %cflag.418.i, %bb168.i ], [ 1, %bb211.i ] ; <i16> [#uses=2] + %9 = icmp slt i32 %tmp105.i, undef ; <i1> [#uses=1] + br i1 %9, label %bb220.i, label %bb158.i + +bb220.i: ; preds = %bb218.i, %bb153.i + %cflag.4.lcssa.i = phi i16 [ 0, %bb153.i ], [ %cflag.3.i, %bb218.i ] ; <i16> [#uses=0] + br i1 undef, label %bb221.i, label %bb228.i + +bb221.i: ; preds = %bb220.i + br label %bb228.i + +bb228.i: ; preds = %bb221.i, %bb220.i, %bb151.i, %bb146.i, %bb12 + br i1 undef, label %bb74.i, label %bb145.i + +bb15: ; preds = %bb11, %bb8 + br i1 undef, label %return, label %bb9 + +return: ; preds = %bb15 + ret void +} diff --git a/test/CodeGen/ARM/2009-06-30-RegScavengerAssert4.ll b/test/CodeGen/ARM/2009-06-30-RegScavengerAssert4.ll new file mode 100644 index 0000000..bca7f79 --- /dev/null +++ b/test/CodeGen/ARM/2009-06-30-RegScavengerAssert4.ll @@ -0,0 +1,128 @@ +; RUN: llvm-as < %s | llc -march=arm -mtriple=armv6-apple-darwin9 + +@r = external global i32 ; <i32*> [#uses=1] +@qr = external global i32 ; <i32*> [#uses=1] +@II = external global i32* ; <i32**> [#uses=1] +@no_mis = external global i32 ; <i32*> [#uses=1] +@name1 = external global i8* ; <i8**> [#uses=1] + +declare arm_apcscc void @diff(i8*, i8*, i32, i32, i32, i32) nounwind + +define arm_apcscc void @SIM(i8* %A, i8* %B, i32 %M, i32 %N, i32 %K, [256 x i32]* %V, i32 %Q, i32 %R, i32 %nseq) nounwind { +entry: + br i1 undef, label %bb5, label %bb + +bb: ; preds = %bb, %entry + br label %bb + +bb5: ; preds = %entry + br i1 undef, label %bb6, label %bb8 + +bb6: ; preds = %bb6, %bb5 + br i1 undef, label %bb8, label %bb6 + +bb8: ; preds = %bb6, %bb5 + %0 = load i8** @name1, align 4 ; <i8*> [#uses=0] + br label %bb15 + +bb9: ; preds = %bb15 + br i1 undef, label %bb10, label %bb11 + +bb10: ; preds = %bb9 + unreachable + +bb11: ; preds = %bb9 + store i32 0, i32* @no_mis, align 4 + %1 = getelementptr i8* %A, i32 0 ; <i8*> [#uses=1] + %2 = getelementptr i8* %B, i32 0 ; <i8*> [#uses=1] + tail call arm_apcscc void @diff(i8* %1, i8* %2, i32 undef, i32 undef, i32 undef, i32 undef) nounwind + br i1 undef, label %bb15, label %bb12 + +bb12: ; preds = %bb11 + %3 = load i32** @II, align 4 ; <i32*> [#uses=1] + %4 = load i32* @r, align 4 ; <i32> [#uses=1] + %5 = load i32* @qr, align 4 ; <i32> [#uses=1] + br label %bb228.i + +bb74.i: ; preds = %bb228.i + br i1 undef, label %bb138.i, label %bb145.i + +bb138.i: ; preds = %bb74.i + br label %bb145.i + +bb145.i: ; preds = %bb228.i, %bb138.i, %bb74.i + br i1 undef, label %bb146.i, label %bb151.i + +bb146.i: ; preds = %bb145.i + br i1 undef, label %bb228.i, label %bb151.i + +bb151.i: ; preds = %bb146.i, %bb145.i + br i1 undef, label %bb153.i, label %bb228.i + +bb153.i: ; preds = %bb151.i + %6 = add i32 undef, -1 ; <i32> [#uses=3] + br i1 undef, label %bb220.i, label %bb.nph.i98 + +bb.nph.i98: ; preds = %bb153.i + br label %bb158.i + +bb158.i: ; preds = %bb218.i, %bb.nph.i98 + %c.1020.i = phi i32 [ 0, %bb.nph.i98 ], [ %c.14.i, %bb218.i ] ; <i32> [#uses=1] + %f.419.i = phi i32 [ undef, %bb.nph.i98 ], [ %f.5.i, %bb218.i ] ; <i32> [#uses=1] + %pi.316.i = phi i32 [ undef, %bb.nph.i98 ], [ %10, %bb218.i ] ; <i32> [#uses=1] + %fj.515.i = phi i32 [ %6, %bb.nph.i98 ], [ %fj.4.i, %bb218.i ] ; <i32> [#uses=2] + %fi.614.i = phi i32 [ undef, %bb.nph.i98 ], [ %fi.5.i, %bb218.i ] ; <i32> [#uses=3] + %cj.811.i = phi i32 [ %6, %bb.nph.i98 ], [ %cj.11.i100, %bb218.i ] ; <i32> [#uses=3] + %ci.910.i = phi i32 [ undef, %bb.nph.i98 ], [ %ci.12.i, %bb218.i ] ; <i32> [#uses=2] + %7 = sub i32 %f.419.i, %4 ; <i32> [#uses=5] + %8 = sub i32 %c.1020.i, %5 ; <i32> [#uses=2] + %9 = icmp slt i32 %7, %8 ; <i1> [#uses=1] + br i1 %9, label %bb168.i, label %bb160.i + +bb160.i: ; preds = %bb158.i + br i1 undef, label %bb161.i, label %bb168.i + +bb161.i: ; preds = %bb160.i + br i1 undef, label %bb168.i, label %bb163.i + +bb163.i: ; preds = %bb161.i + br i1 undef, label %bb167.i, label %bb168.i + +bb167.i: ; preds = %bb163.i + br label %bb168.i + +bb168.i: ; preds = %bb167.i, %bb163.i, %bb161.i, %bb160.i, %bb158.i + %fi.5.i = phi i32 [ %fi.614.i, %bb167.i ], [ %ci.910.i, %bb158.i ], [ %fi.614.i, %bb160.i ], [ %ci.910.i, %bb161.i ], [ %fi.614.i, %bb163.i ] ; <i32> [#uses=2] + %fj.4.i = phi i32 [ %cj.811.i, %bb167.i ], [ %cj.811.i, %bb158.i ], [ %fj.515.i, %bb160.i ], [ %cj.811.i, %bb161.i ], [ %fj.515.i, %bb163.i ] ; <i32> [#uses=2] + %f.5.i = phi i32 [ %7, %bb167.i ], [ %8, %bb158.i ], [ %7, %bb160.i ], [ %7, %bb161.i ], [ %7, %bb163.i ] ; <i32> [#uses=2] + %scevgep88.i = getelementptr i32* %3, i32 undef ; <i32*> [#uses=1] + %ci.10.i = select i1 undef, i32 %pi.316.i, i32 undef ; <i32> [#uses=0] + %ci.12.i = select i1 undef, i32 %fi.5.i, i32 undef ; <i32> [#uses=1] + %cj.11.i100 = select i1 undef, i32 %fj.4.i, i32 undef ; <i32> [#uses=1] + %c.14.i = select i1 undef, i32 %f.5.i, i32 undef ; <i32> [#uses=1] + %10 = load i32* %scevgep88.i, align 4 ; <i32> [#uses=1] + br i1 undef, label %bb211.i, label %bb218.i + +bb211.i: ; preds = %bb168.i + br label %bb218.i + +bb218.i: ; preds = %bb211.i, %bb168.i + br i1 undef, label %bb220.i, label %bb158.i + +bb220.i: ; preds = %bb218.i, %bb153.i + %11 = getelementptr i32* null, i32 %6 ; <i32*> [#uses=1] + store i32 undef, i32* %11, align 4 + br i1 undef, label %bb221.i, label %bb228.i + +bb221.i: ; preds = %bb220.i + br label %bb228.i + +bb228.i: ; preds = %bb221.i, %bb220.i, %bb151.i, %bb146.i, %bb12 + br i1 undef, label %bb74.i, label %bb145.i + +bb15: ; preds = %bb11, %bb8 + br i1 undef, label %return, label %bb9 + +return: ; preds = %bb15 + ret void +} diff --git a/test/CodeGen/ARM/2009-06-30-RegScavengerAssert5.ll b/test/CodeGen/ARM/2009-06-30-RegScavengerAssert5.ll new file mode 100644 index 0000000..0c90592 --- /dev/null +++ b/test/CodeGen/ARM/2009-06-30-RegScavengerAssert5.ll @@ -0,0 +1,99 @@ +; RUN: llvm-as < %s | llc -march=arm -mtriple=armv6-apple-darwin9 + +@XX = external global i32* ; <i32**> [#uses=1] + +define arm_apcscc void @SIM(i8* %A, i8* %B, i32 %M, i32 %N, i32 %K, [256 x i32]* %V, i32 %Q, i32 %R, i32 %nseq) nounwind { +entry: + br i1 undef, label %bb5, label %bb + +bb: ; preds = %bb, %entry + br label %bb + +bb5: ; preds = %entry + br i1 undef, label %bb6, label %bb8 + +bb6: ; preds = %bb6, %bb5 + br i1 undef, label %bb8, label %bb6 + +bb8: ; preds = %bb6, %bb5 + br label %bb15 + +bb9: ; preds = %bb15 + br i1 undef, label %bb10, label %bb11 + +bb10: ; preds = %bb9 + unreachable + +bb11: ; preds = %bb9 + br i1 undef, label %bb15, label %bb12 + +bb12: ; preds = %bb11 + %0 = load i32** @XX, align 4 ; <i32*> [#uses=0] + br label %bb228.i + +bb74.i: ; preds = %bb228.i + br i1 undef, label %bb138.i, label %bb145.i + +bb138.i: ; preds = %bb74.i + br label %bb145.i + +bb145.i: ; preds = %bb228.i, %bb138.i, %bb74.i + br i1 undef, label %bb146.i, label %bb151.i + +bb146.i: ; preds = %bb145.i + br i1 undef, label %bb228.i, label %bb151.i + +bb151.i: ; preds = %bb146.i, %bb145.i + br i1 undef, label %bb153.i, label %bb228.i + +bb153.i: ; preds = %bb151.i + br i1 undef, label %bb220.i, label %bb.nph.i98 + +bb.nph.i98: ; preds = %bb153.i + br label %bb158.i + +bb158.i: ; preds = %bb218.i, %bb.nph.i98 + %1 = sub i32 undef, undef ; <i32> [#uses=4] + %2 = sub i32 undef, undef ; <i32> [#uses=1] + br i1 undef, label %bb168.i, label %bb160.i + +bb160.i: ; preds = %bb158.i + br i1 undef, label %bb161.i, label %bb168.i + +bb161.i: ; preds = %bb160.i + br i1 undef, label %bb168.i, label %bb163.i + +bb163.i: ; preds = %bb161.i + br i1 undef, label %bb167.i, label %bb168.i + +bb167.i: ; preds = %bb163.i + br label %bb168.i + +bb168.i: ; preds = %bb167.i, %bb163.i, %bb161.i, %bb160.i, %bb158.i + %f.5.i = phi i32 [ %1, %bb167.i ], [ %2, %bb158.i ], [ %1, %bb160.i ], [ %1, %bb161.i ], [ %1, %bb163.i ] ; <i32> [#uses=1] + %c.14.i = select i1 undef, i32 %f.5.i, i32 undef ; <i32> [#uses=1] + store i32 %c.14.i, i32* undef, align 4 + store i32 undef, i32* null, align 4 + br i1 undef, label %bb211.i, label %bb218.i + +bb211.i: ; preds = %bb168.i + br label %bb218.i + +bb218.i: ; preds = %bb211.i, %bb168.i + br i1 undef, label %bb220.i, label %bb158.i + +bb220.i: ; preds = %bb218.i, %bb153.i + br i1 undef, label %bb221.i, label %bb228.i + +bb221.i: ; preds = %bb220.i + br label %bb228.i + +bb228.i: ; preds = %bb221.i, %bb220.i, %bb151.i, %bb146.i, %bb12 + br i1 undef, label %bb74.i, label %bb145.i + +bb15: ; preds = %bb11, %bb8 + br i1 undef, label %return, label %bb9 + +return: ; preds = %bb15 + ret void +} diff --git a/test/CodeGen/ARM/2009-07-01-CommuteBug.ll b/test/CodeGen/ARM/2009-07-01-CommuteBug.ll new file mode 100644 index 0000000..dfccefc --- /dev/null +++ b/test/CodeGen/ARM/2009-07-01-CommuteBug.ll @@ -0,0 +1,130 @@ +; RUN: llvm-as < %s | llc -march=arm -mtriple=armv6-apple-darwin9 + +@qr = external global i32 ; <i32*> [#uses=1] +@II = external global i32* ; <i32**> [#uses=1] +@JJ = external global i32* ; <i32**> [#uses=1] + +define arm_apcscc void @SIM(i8* %A, i8* %B, i32 %M, i32 %N, i32 %K, [256 x i32]* %V, i32 %Q, i32 %R, i32 %nseq) nounwind { +entry: + br i1 undef, label %bb5, label %bb + +bb: ; preds = %bb, %entry + br label %bb + +bb5: ; preds = %entry + br i1 undef, label %bb6, label %bb8 + +bb6: ; preds = %bb6, %bb5 + br i1 undef, label %bb8, label %bb6 + +bb8: ; preds = %bb6, %bb5 + br label %bb15 + +bb9: ; preds = %bb15 + br i1 undef, label %bb10, label %bb11 + +bb10: ; preds = %bb9 + unreachable + +bb11: ; preds = %bb9 + br i1 undef, label %bb15, label %bb12 + +bb12: ; preds = %bb11 + %0 = load i32** @II, align 4 ; <i32*> [#uses=1] + %1 = load i32** @JJ, align 4 ; <i32*> [#uses=1] + %2 = load i32* @qr, align 4 ; <i32> [#uses=1] + br label %bb228.i + +bb74.i: ; preds = %bb228.i + br i1 undef, label %bb138.i, label %bb145.i + +bb138.i: ; preds = %bb74.i + br label %bb145.i + +bb145.i: ; preds = %bb228.i, %bb138.i, %bb74.i + %cflag.0.i = phi i16 [ %cflag.1.i, %bb228.i ], [ %cflag.1.i, %bb74.i ], [ 1, %bb138.i ] ; <i16> [#uses=2] + br i1 undef, label %bb146.i, label %bb151.i + +bb146.i: ; preds = %bb145.i + br i1 undef, label %bb228.i, label %bb151.i + +bb151.i: ; preds = %bb146.i, %bb145.i + %.not297 = icmp ne i16 %cflag.0.i, 0 ; <i1> [#uses=1] + %or.cond298 = and i1 undef, %.not297 ; <i1> [#uses=1] + br i1 %or.cond298, label %bb153.i, label %bb228.i + +bb153.i: ; preds = %bb151.i + br i1 undef, label %bb220.i, label %bb.nph.i98 + +bb.nph.i98: ; preds = %bb153.i + br label %bb158.i + +bb158.i: ; preds = %bb218.i, %bb.nph.i98 + %c.1020.i = phi i32 [ 0, %bb.nph.i98 ], [ %c.14.i, %bb218.i ] ; <i32> [#uses=1] + %f.419.i = phi i32 [ undef, %bb.nph.i98 ], [ %f.5.i, %bb218.i ] ; <i32> [#uses=1] + %cflag.418.i = phi i16 [ 0, %bb.nph.i98 ], [ %cflag.3.i, %bb218.i ] ; <i16> [#uses=1] + %pj.317.i = phi i32 [ undef, %bb.nph.i98 ], [ %7, %bb218.i ] ; <i32> [#uses=1] + %pi.316.i = phi i32 [ undef, %bb.nph.i98 ], [ %6, %bb218.i ] ; <i32> [#uses=1] + %fj.515.i = phi i32 [ undef, %bb.nph.i98 ], [ %fj.4.i, %bb218.i ] ; <i32> [#uses=2] + %fi.614.i = phi i32 [ undef, %bb.nph.i98 ], [ %fi.5.i, %bb218.i ] ; <i32> [#uses=3] + %cj.811.i = phi i32 [ undef, %bb.nph.i98 ], [ %cj.11.i100, %bb218.i ] ; <i32> [#uses=3] + %ci.910.i = phi i32 [ undef, %bb.nph.i98 ], [ %ci.12.i, %bb218.i ] ; <i32> [#uses=2] + %3 = sub i32 %f.419.i, 0 ; <i32> [#uses=5] + %4 = sub i32 %c.1020.i, %2 ; <i32> [#uses=2] + %5 = icmp slt i32 %3, %4 ; <i1> [#uses=1] + br i1 %5, label %bb168.i, label %bb160.i + +bb160.i: ; preds = %bb158.i + br i1 undef, label %bb161.i, label %bb168.i + +bb161.i: ; preds = %bb160.i + br i1 undef, label %bb168.i, label %bb163.i + +bb163.i: ; preds = %bb161.i + br i1 undef, label %bb167.i, label %bb168.i + +bb167.i: ; preds = %bb163.i + br label %bb168.i + +bb168.i: ; preds = %bb167.i, %bb163.i, %bb161.i, %bb160.i, %bb158.i + %fi.5.i = phi i32 [ %fi.614.i, %bb167.i ], [ %ci.910.i, %bb158.i ], [ %fi.614.i, %bb160.i ], [ %ci.910.i, %bb161.i ], [ %fi.614.i, %bb163.i ] ; <i32> [#uses=2] + %fj.4.i = phi i32 [ %cj.811.i, %bb167.i ], [ %cj.811.i, %bb158.i ], [ %fj.515.i, %bb160.i ], [ %cj.811.i, %bb161.i ], [ %fj.515.i, %bb163.i ] ; <i32> [#uses=2] + %f.5.i = phi i32 [ %3, %bb167.i ], [ %4, %bb158.i ], [ %3, %bb160.i ], [ %3, %bb161.i ], [ %3, %bb163.i ] ; <i32> [#uses=2] + %scevgep88.i = getelementptr i32* %0, i32 undef ; <i32*> [#uses=2] + %scevgep89.i = getelementptr i32* %1, i32 undef ; <i32*> [#uses=2] + %ci.10.i = select i1 undef, i32 %pi.316.i, i32 undef ; <i32> [#uses=0] + %cj.9.i = select i1 undef, i32 %pj.317.i, i32 undef ; <i32> [#uses=0] + %ci.12.i = select i1 undef, i32 %fi.5.i, i32 undef ; <i32> [#uses=2] + %cj.11.i100 = select i1 undef, i32 %fj.4.i, i32 undef ; <i32> [#uses=2] + %c.14.i = select i1 undef, i32 %f.5.i, i32 undef ; <i32> [#uses=1] + %6 = load i32* %scevgep88.i, align 4 ; <i32> [#uses=1] + %7 = load i32* %scevgep89.i, align 4 ; <i32> [#uses=1] + store i32 %ci.12.i, i32* %scevgep88.i, align 4 + store i32 %cj.11.i100, i32* %scevgep89.i, align 4 + br i1 undef, label %bb211.i, label %bb218.i + +bb211.i: ; preds = %bb168.i + br label %bb218.i + +bb218.i: ; preds = %bb211.i, %bb168.i + %cflag.3.i = phi i16 [ %cflag.418.i, %bb168.i ], [ 1, %bb211.i ] ; <i16> [#uses=2] + %8 = icmp slt i32 undef, undef ; <i1> [#uses=1] + br i1 %8, label %bb220.i, label %bb158.i + +bb220.i: ; preds = %bb218.i, %bb153.i + %cflag.4.lcssa.i = phi i16 [ 0, %bb153.i ], [ %cflag.3.i, %bb218.i ] ; <i16> [#uses=2] + br i1 undef, label %bb221.i, label %bb228.i + +bb221.i: ; preds = %bb220.i + br label %bb228.i + +bb228.i: ; preds = %bb221.i, %bb220.i, %bb151.i, %bb146.i, %bb12 + %cflag.1.i = phi i16 [ 0, %bb146.i ], [ %cflag.0.i, %bb151.i ], [ %cflag.4.lcssa.i, %bb220.i ], [ 1, %bb12 ], [ %cflag.4.lcssa.i, %bb221.i ] ; <i16> [#uses=2] + br i1 false, label %bb74.i, label %bb145.i + +bb15: ; preds = %bb11, %bb8 + br i1 false, label %return, label %bb9 + +return: ; preds = %bb15 + ret void +} diff --git a/test/CodeGen/ARM/ldr.ll b/test/CodeGen/ARM/ldr.ll index 23c0b99..ea99655 100644 --- a/test/CodeGen/ARM/ldr.ll +++ b/test/CodeGen/ARM/ldr.ll @@ -1,23 +1,59 @@ -; RUN: llvm-as < %s | llc -march=arm | \ -; RUN: grep {ldr r0} | count 3 +; RUN: llvm-as < %s | llc -march=arm | grep {ldr r0} | count 7 +; RUN: llvm-as < %s | llc -march=arm | grep mov | grep 1 +; RUN: llvm-as < %s | llc -march=arm | not grep mvn +; RUN: llvm-as < %s | llc -march=arm | grep ldr | grep lsl +; RUN: llvm-as < %s | llc -march=arm | grep ldr | grep lsr define i32 @f1(i32* %v) { entry: - %tmp = load i32* %v ; <i32> [#uses=1] + %tmp = load i32* %v ret i32 %tmp } define i32 @f2(i32* %v) { entry: - %tmp2 = getelementptr i32* %v, i32 1023 ; <i32*> [#uses=1] - %tmp = load i32* %tmp2 ; <i32> [#uses=1] + %tmp2 = getelementptr i32* %v, i32 1023 + %tmp = load i32* %tmp2 ret i32 %tmp } define i32 @f3(i32* %v) { entry: - %tmp2 = getelementptr i32* %v, i32 1024 ; <i32*> [#uses=1] - %tmp = load i32* %tmp2 ; <i32> [#uses=1] + %tmp2 = getelementptr i32* %v, i32 1024 + %tmp = load i32* %tmp2 ret i32 %tmp } +define i32 @f4(i32 %base) { +entry: + %tmp1 = sub i32 %base, 128 + %tmp2 = inttoptr i32 %tmp1 to i32* + %tmp3 = load i32* %tmp2 + ret i32 %tmp3 +} + +define i32 @f5(i32 %base, i32 %offset) { +entry: + %tmp1 = add i32 %base, %offset + %tmp2 = inttoptr i32 %tmp1 to i32* + %tmp3 = load i32* %tmp2 + ret i32 %tmp3 +} + +define i32 @f6(i32 %base, i32 %offset) { +entry: + %tmp1 = shl i32 %offset, 2 + %tmp2 = add i32 %base, %tmp1 + %tmp3 = inttoptr i32 %tmp2 to i32* + %tmp4 = load i32* %tmp3 + ret i32 %tmp4 +} + +define i32 @f7(i32 %base, i32 %offset) { +entry: + %tmp1 = lshr i32 %offset, 2 + %tmp2 = add i32 %base, %tmp1 + %tmp3 = inttoptr i32 %tmp2 to i32* + %tmp4 = load i32* %tmp3 + ret i32 %tmp4 +} diff --git a/test/CodeGen/ARM/sxt_rot.ll b/test/CodeGen/ARM/sxt_rot.ll index bfecce8..e9f302c 100644 --- a/test/CodeGen/ARM/sxt_rot.ll +++ b/test/CodeGen/ARM/sxt_rot.ll @@ -1,8 +1,15 @@ ; RUN: llvm-as < %s | llc -march=arm -mattr=+v6 | \ -; RUN: grep sxtb | count 1 +; RUN: grep sxtb | count 2 +; RUN: llvm-as < %s | llc -march=arm -mattr=+v6 | \ +; RUN: grep sxtb | grep ror | count 1 ; RUN: llvm-as < %s | llc -march=arm -mattr=+v6 | \ ; RUN: grep sxtab | count 1 +define i32 @test0(i8 %A) { + %B = sext i8 %A to i32 + ret i32 %B +} + define i8 @test1(i32 %A) signext { %B = lshr i32 %A, 8 %C = shl i32 %A, 24 diff --git a/test/CodeGen/PowerPC/available-externally.ll b/test/CodeGen/PowerPC/available-externally.ll new file mode 100644 index 0000000..cfad6ea --- /dev/null +++ b/test/CodeGen/PowerPC/available-externally.ll @@ -0,0 +1,69 @@ +; RUN: llvm-as < %s | llc | grep {bl L_exact_log2.stub} +; PR4482 +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" +target triple = "powerpc-apple-darwin8" + +define i32 @foo(i64 %x) nounwind { +entry: + %x_addr = alloca i64 ; <i64*> [#uses=2] + %retval = alloca i32 ; <i32*> [#uses=2] + %0 = alloca i32 ; <i32*> [#uses=2] + %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] + store i64 %x, i64* %x_addr + %1 = load i64* %x_addr, align 8 ; <i64> [#uses=1] + %2 = call i32 @exact_log2(i64 %1) nounwind ; <i32> [#uses=1] + store i32 %2, i32* %0, align 4 + %3 = load i32* %0, align 4 ; <i32> [#uses=1] + store i32 %3, i32* %retval, align 4 + br label %return + +return: ; preds = %entry + %retval1 = load i32* %retval ; <i32> [#uses=1] + ret i32 %retval1 +} + +define available_externally i32 @exact_log2(i64 %x) nounwind { +entry: + %x_addr = alloca i64 ; <i64*> [#uses=6] + %retval = alloca i32 ; <i32*> [#uses=2] + %iftmp.0 = alloca i32 ; <i32*> [#uses=3] + %0 = alloca i32 ; <i32*> [#uses=2] + %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] + store i64 %x, i64* %x_addr + %1 = load i64* %x_addr, align 8 ; <i64> [#uses=1] + %2 = sub i64 0, %1 ; <i64> [#uses=1] + %3 = load i64* %x_addr, align 8 ; <i64> [#uses=1] + %4 = and i64 %2, %3 ; <i64> [#uses=1] + %5 = load i64* %x_addr, align 8 ; <i64> [#uses=1] + %6 = icmp ne i64 %4, %5 ; <i1> [#uses=1] + br i1 %6, label %bb2, label %bb + +bb: ; preds = %entry + %7 = load i64* %x_addr, align 8 ; <i64> [#uses=1] + %8 = icmp eq i64 %7, 0 ; <i1> [#uses=1] + br i1 %8, label %bb2, label %bb1 + +bb1: ; preds = %bb + %9 = load i64* %x_addr, align 8 ; <i64> [#uses=1] + %10 = call i64 @llvm.cttz.i64(i64 %9) ; <i64> [#uses=1] + %11 = trunc i64 %10 to i32 ; <i32> [#uses=1] + store i32 %11, i32* %iftmp.0, align 4 + br label %bb3 + +bb2: ; preds = %bb, %entry + store i32 -1, i32* %iftmp.0, align 4 + br label %bb3 + +bb3: ; preds = %bb2, %bb1 + %12 = load i32* %iftmp.0, align 4 ; <i32> [#uses=1] + store i32 %12, i32* %0, align 4 + %13 = load i32* %0, align 4 ; <i32> [#uses=1] + store i32 %13, i32* %retval, align 4 + br label %return + +return: ; preds = %bb3 + %retval4 = load i32* %retval ; <i32> [#uses=1] + ret i32 %retval4 +} + +declare i64 @llvm.cttz.i64(i64) nounwind readnone diff --git a/test/CodeGen/Thumb2/load-global.ll b/test/CodeGen/Thumb2/load-global.ll index 0ffcb95..1b1fe7b 100644 --- a/test/CodeGen/Thumb2/load-global.ll +++ b/test/CodeGen/Thumb2/load-global.ll @@ -1,5 +1,15 @@ -; RUN: llvm-as < %s | llc -mtriple=thumbv7-apple-darwin -; RUN: llvm-as < %s | llc -mtriple=thumbv7-apple-darwin -relocation-model=pic | grep add | grep pc +; RUN: llvm-as < %s | \ +; RUN: llc -mtriple=thumbv7-apple-darwin -relocation-model=static | \ +; RUN: not grep {L_G\$non_lazy_ptr} +; RUN: llvm-as < %s | \ +; RUN: llc -mtriple=thumbv7-apple-darwin -relocation-model=dynamic-no-pic | \ +; RUN: grep {L_G\$non_lazy_ptr} | count 2 +; RUN: llvm-as < %s | \ +; RUN: llc -mtriple=thumbv7-apple-darwin -relocation-model=pic | \ +; RUN: grep {ldr.*pc} | count 1 +; RUN: llvm-as < %s | \ +; RUN: llc -mtriple=thumbv7-linux-gnueabi -relocation-model=pic | \ +; RUN: grep {GOT} | count 1 @G = external global i32 diff --git a/test/CodeGen/Thumb2/thumb2-adc.ll b/test/CodeGen/Thumb2/thumb2-adc.ll index 4424c1a..c1565b3 100644 --- a/test/CodeGen/Thumb2/thumb2-adc.ll +++ b/test/CodeGen/Thumb2/thumb2-adc.ll @@ -1,32 +1,32 @@ ; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {adc\\W*r\[0-9\],\\W*r\[0-9\],\\W*#\[0-9\]*} | grep {#171\\|#1179666\\|#872428544\\|#1448498774\\|#66846720} | count 5 -; 734439407617 = 0x000000ab00000001 +; 734439407618 = 0x000000ab00000002 define i64 @f1(i64 %a) { - %tmp = add i64 %a, 734439407617 + %tmp = add i64 %a, 734439407618 ret i64 %tmp } -; 5066626890203137 = 0x0012001200000001 +; 5066626890203138 = 0x0012001200000002 define i64 @f2(i64 %a) { - %tmp = add i64 %a, 5066626890203137 + %tmp = add i64 %a, 5066626890203138 ret i64 %tmp } -; 3747052064576897025 = 0x3400340000000001 +; 3747052064576897026 = 0x3400340000000002 define i64 @f3(i64 %a) { - %tmp = add i64 %a, 3747052064576897025 + %tmp = add i64 %a, 3747052064576897026 ret i64 %tmp } -; 6221254862626095105 = 0x5656565600000001 +; 6221254862626095106 = 0x5656565600000002 define i64 @f4(i64 %a) { - %tmp = add i64 %a, 6221254862626095105 + %tmp = add i64 %a, 6221254862626095106 ret i64 %tmp } -; 287104476244869121 = 0x03fc000000000001 +; 287104476244869122 = 0x03fc000000000002 define i64 @f5(i64 %a) { - %tmp = add i64 %a, 287104476244869121 + %tmp = add i64 %a, 287104476244869122 ret i64 %tmp } diff --git a/test/CodeGen/Thumb2/thumb2-add2.ll b/test/CodeGen/Thumb2/thumb2-add2.ll index f94b3c1..be89508 100644 --- a/test/CodeGen/Thumb2/thumb2-add2.ll +++ b/test/CodeGen/Thumb2/thumb2-add2.ll @@ -29,8 +29,3 @@ define i32 @f5(i32 %a) { %tmp = add i32 %a, 510 ret i32 %tmp } - -define i32 @f6(i32 %a) { - %tmp = add i32 %a, 4095 - ret i32 %tmp -} diff --git a/test/CodeGen/Thumb2/thumb2-add5.ll b/test/CodeGen/Thumb2/thumb2-add5.ll index 5870be2..2245214 100644 --- a/test/CodeGen/Thumb2/thumb2-add5.ll +++ b/test/CodeGen/Thumb2/thumb2-add5.ll @@ -1,6 +1,36 @@ -; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {add\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\]} | count 1 +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {add\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\]$} | count 1 +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {add\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\],\\W*lsl\\W*#5$} | count 1 +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {add\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\],\\W*lsr\\W*#6$} | count 1 +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {add\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\],\\W*asr\\W*#7$} | count 1 +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {add\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\],\\W*ror\\W*#8$} | count 1 define i32 @f1(i32 %a, i32 %b) { %tmp = add i32 %a, %b ret i32 %tmp } + +define i32 @f2(i32 %a, i32 %b) { + %tmp = shl i32 %b, 5 + %tmp1 = add i32 %a, %tmp + ret i32 %tmp1 +} + +define i32 @f3(i32 %a, i32 %b) { + %tmp = lshr i32 %b, 6 + %tmp1 = add i32 %a, %tmp + ret i32 %tmp1 +} + +define i32 @f4(i32 %a, i32 %b) { + %tmp = ashr i32 %b, 7 + %tmp1 = add i32 %a, %tmp + ret i32 %tmp1 +} + +define i32 @f5(i32 %a, i32 %b) { + %l8 = shl i32 %a, 24 + %r8 = lshr i32 %a, 8 + %tmp = or i32 %l8, %r8 + %tmp1 = add i32 %a, %tmp + ret i32 %tmp1 +} diff --git a/test/CodeGen/Thumb2/thumb2-and.ll b/test/CodeGen/Thumb2/thumb2-and.ll index 360c977..ab191d5 100644 --- a/test/CodeGen/Thumb2/thumb2-and.ll +++ b/test/CodeGen/Thumb2/thumb2-and.ll @@ -1,6 +1,36 @@ -; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {and\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\]} | count 1 +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {and\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\]$} | count 1 +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {and\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\],\\W*lsl\\W*#5$} | count 1 +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {and\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\],\\W*lsr\\W*#6$} | count 1 +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {and\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\],\\W*asr\\W*#7$} | count 1 +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {and\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\],\\W*ror\\W*#8$} | count 1 define i32 @f1(i32 %a, i32 %b) { %tmp = and i32 %a, %b ret i32 %tmp } + +define i32 @f2(i32 %a, i32 %b) { + %tmp = shl i32 %b, 5 + %tmp1 = and i32 %a, %tmp + ret i32 %tmp1 +} + +define i32 @f3(i32 %a, i32 %b) { + %tmp = lshr i32 %b, 6 + %tmp1 = and i32 %a, %tmp + ret i32 %tmp1 +} + +define i32 @f4(i32 %a, i32 %b) { + %tmp = ashr i32 %b, 7 + %tmp1 = and i32 %a, %tmp + ret i32 %tmp1 +} + +define i32 @f5(i32 %a, i32 %b) { + %l8 = shl i32 %a, 24 + %r8 = lshr i32 %a, 8 + %tmp = or i32 %l8, %r8 + %tmp1 = and i32 %a, %tmp + ret i32 %tmp1 +} diff --git a/test/CodeGen/Thumb2/thumb2-bic.ll b/test/CodeGen/Thumb2/thumb2-bic.ll index ac15ad6..f5a3d20 100644 --- a/test/CodeGen/Thumb2/thumb2-bic.ll +++ b/test/CodeGen/Thumb2/thumb2-bic.ll @@ -1,4 +1,8 @@ -; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {bic\\W*r\[0-9\]*,\\W*r\[0-9\]*,\\W*r\[0-9\]*} | count 4 +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {bic\\W*r\[0-9\]*,\\W*r\[0-9\]*,\\W*r\[0-9\]*$} | count 4 +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {bic\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\],\\W*lsl\\W*#5$} | count 1 +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {bic\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\],\\W*lsr\\W*#6$} | count 1 +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {bic\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\],\\W*asr\\W*#7$} | count 1 +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {bic\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\],\\W*ror\\W*#8$} | count 1 define i32 @f1(i32 %a, i32 %b) { %tmp = xor i32 %b, 4294967295 @@ -23,3 +27,33 @@ define i32 @f4(i32 %a, i32 %b) { %tmp1 = and i32 %tmp, %a ret i32 %tmp1 } + +define i32 @f5(i32 %a, i32 %b) { + %tmp = shl i32 %b, 5 + %tmp1 = xor i32 4294967295, %tmp + %tmp2 = and i32 %a, %tmp1 + ret i32 %tmp2 +} + +define i32 @f6(i32 %a, i32 %b) { + %tmp = lshr i32 %b, 6 + %tmp1 = xor i32 %tmp, 4294967295 + %tmp2 = and i32 %tmp1, %a + ret i32 %tmp2 +} + +define i32 @f7(i32 %a, i32 %b) { + %tmp = ashr i32 %b, 7 + %tmp1 = xor i32 %tmp, 4294967295 + %tmp2 = and i32 %a, %tmp1 + ret i32 %tmp2 +} + +define i32 @f8(i32 %a, i32 %b) { + %l8 = shl i32 %a, 24 + %r8 = lshr i32 %a, 8 + %tmp = or i32 %l8, %r8 + %tmp1 = xor i32 4294967295, %tmp + %tmp2 = and i32 %tmp1, %a + ret i32 %tmp2 +} diff --git a/test/CodeGen/Thumb2/thumb2-cmn.ll b/test/CodeGen/Thumb2/thumb2-cmn.ll new file mode 100644 index 0000000..ffe8b98 --- /dev/null +++ b/test/CodeGen/Thumb2/thumb2-cmn.ll @@ -0,0 +1,59 @@ +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {cmn\\W*r\[0-9\],\\W*r\[0-9\]$} | count 4 +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {cmn\\W*r\[0-9\],\\W*r\[0-9\],\\W*lsl\\W*#5$} | count 1 +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {cmn\\W*r\[0-9\],\\W*r\[0-9\],\\W*lsr\\W*#6$} | count 1 +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {cmn\\W*r\[0-9\],\\W*r\[0-9\],\\W*asr\\W*#7$} | count 1 +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {cmn\\W*r\[0-9\],\\W*r\[0-9\],\\W*ror\\W*#8$} | count 1 + +define i1 @f1(i32 %a, i32 %b) { + %nb = sub i32 0, %b + %tmp = icmp ne i32 %a, %nb + ret i1 %tmp +} + +define i1 @f2(i32 %a, i32 %b) { + %nb = sub i32 0, %b + %tmp = icmp ne i32 %nb, %a + ret i1 %tmp +} + +define i1 @f3(i32 %a, i32 %b) { + %nb = sub i32 0, %b + %tmp = icmp eq i32 %a, %nb + ret i1 %tmp +} + +define i1 @f4(i32 %a, i32 %b) { + %nb = sub i32 0, %b + %tmp = icmp eq i32 %nb, %a + ret i1 %tmp +} + +define i1 @f5(i32 %a, i32 %b) { + %tmp = shl i32 %b, 5 + %nb = sub i32 0, %tmp + %tmp1 = icmp eq i32 %nb, %a + ret i1 %tmp1 +} + +define i1 @f6(i32 %a, i32 %b) { + %tmp = lshr i32 %b, 6 + %nb = sub i32 0, %tmp + %tmp1 = icmp ne i32 %nb, %a + ret i1 %tmp1 +} + +define i1 @f7(i32 %a, i32 %b) { + %tmp = ashr i32 %b, 7 + %nb = sub i32 0, %tmp + %tmp1 = icmp eq i32 %a, %nb + ret i1 %tmp1 +} + +define i1 @f8(i32 %a, i32 %b) { + %l8 = shl i32 %a, 24 + %r8 = lshr i32 %a, 8 + %tmp = or i32 %l8, %r8 + %nb = sub i32 0, %tmp + %tmp1 = icmp ne i32 %a, %nb + ret i1 %tmp1 +} diff --git a/test/CodeGen/Thumb2/thumb2-cmp.ll b/test/CodeGen/Thumb2/thumb2-cmp.ll index cd2442b..63f20cd 100644 --- a/test/CodeGen/Thumb2/thumb2-cmp.ll +++ b/test/CodeGen/Thumb2/thumb2-cmp.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep "cmp " | grep {#187\\|#11141290\\|#3422604288\\|#1114112\\|#3722304989} | count 5 +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {cmp\\W*r\[0-9\],\\W*#\[0-9\]*$} | grep {#187\\|#11141290\\|#3422604288\\|#1114112\\|#3722304989} | count 5 ; 0x000000bb = 187 define i1 @f1(i32 %a) { diff --git a/test/CodeGen/Thumb2/thumb2-cmp2.ll b/test/CodeGen/Thumb2/thumb2-cmp2.ll index 8c60b46..368a3b3 100644 --- a/test/CodeGen/Thumb2/thumb2-cmp2.ll +++ b/test/CodeGen/Thumb2/thumb2-cmp2.ll @@ -1,4 +1,8 @@ -; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {cmp\\W*r\[0-9\],\\W*r\[0-9\]} | count 2 +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {cmp\\W*r\[0-9\],\\W*r\[0-9\]$} | count 2 +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {cmp\\W*r\[0-9\],\\W*r\[0-9\],\\W*lsl\\W*#5$} | count 1 +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {cmp\\W*r\[0-9\],\\W*r\[0-9\],\\W*lsr\\W*#6$} | count 1 +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {cmp\\W*r\[0-9\],\\W*r\[0-9\],\\W*asr\\W*#7$} | count 1 +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {cmp\\W*r\[0-9\],\\W*r\[0-9\],\\W*ror\\W*#8$} | count 1 define i1 @f1(i32 %a, i32 %b) { %tmp = icmp ne i32 %a, %b @@ -9,3 +13,29 @@ define i1 @f2(i32 %a, i32 %b) { %tmp = icmp eq i32 %a, %b ret i1 %tmp } + +define i1 @f6(i32 %a, i32 %b) { + %tmp = shl i32 %b, 5 + %tmp1 = icmp eq i32 %tmp, %a + ret i1 %tmp1 +} + +define i1 @f7(i32 %a, i32 %b) { + %tmp = lshr i32 %b, 6 + %tmp1 = icmp ne i32 %tmp, %a + ret i1 %tmp1 +} + +define i1 @f8(i32 %a, i32 %b) { + %tmp = ashr i32 %b, 7 + %tmp1 = icmp eq i32 %a, %tmp + ret i1 %tmp1 +} + +define i1 @f9(i32 %a, i32 %b) { + %l8 = shl i32 %a, 24 + %r8 = lshr i32 %a, 8 + %tmp = or i32 %l8, %r8 + %tmp1 = icmp ne i32 %a, %tmp + ret i1 %tmp1 +} diff --git a/test/CodeGen/Thumb2/thumb2-eor.ll b/test/CodeGen/Thumb2/thumb2-eor.ll index ec98f64..56bb46a 100644 --- a/test/CodeGen/Thumb2/thumb2-eor.ll +++ b/test/CodeGen/Thumb2/thumb2-eor.ll @@ -1,6 +1,41 @@ -; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {eor\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\]} | count 1 +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {eor\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\]$} | count 2 +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {eor\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\],\\W*lsl\\W*#5$} | count 1 +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {eor\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\],\\W*lsr\\W*#6$} | count 1 +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {eor\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\],\\W*asr\\W*#7$} | count 1 +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {eor\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\],\\W*ror\\W*#8$} | count 1 define i32 @f1(i32 %a, i32 %b) { %tmp = xor i32 %a, %b ret i32 %tmp } + +define i32 @f2(i32 %a, i32 %b) { + %tmp = xor i32 %b, %a + ret i32 %tmp +} + +define i32 @f3(i32 %a, i32 %b) { + %tmp = shl i32 %b, 5 + %tmp1 = xor i32 %a, %tmp + ret i32 %tmp1 +} + +define i32 @f4(i32 %a, i32 %b) { + %tmp = lshr i32 %b, 6 + %tmp1 = xor i32 %tmp, %a + ret i32 %tmp1 +} + +define i32 @f5(i32 %a, i32 %b) { + %tmp = ashr i32 %b, 7 + %tmp1 = xor i32 %a, %tmp + ret i32 %tmp1 +} + +define i32 @f6(i32 %a, i32 %b) { + %l8 = shl i32 %a, 24 + %r8 = lshr i32 %a, 8 + %tmp = or i32 %l8, %r8 + %tmp1 = xor i32 %tmp, %a + ret i32 %tmp1 +} diff --git a/test/CodeGen/Thumb2/thumb2-jumptbl.ll b/test/CodeGen/Thumb2/thumb2-jumptbl.ll new file mode 100644 index 0000000..512c669 --- /dev/null +++ b/test/CodeGen/Thumb2/thumb2-jumptbl.ll @@ -0,0 +1,26 @@ +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {ldr\\W*pc,} | count 1 + +define i32 @foo(i32 %a) nounwind { +entry: + switch i32 %a, label %bb4 [ + i32 1, label %bb5 + i32 2, label %bb1 + i32 3, label %bb2 + i32 5, label %bb3 + ] + +bb1: ; preds = %entry + ret i32 1 + +bb2: ; preds = %entry + ret i32 1234 + +bb3: ; preds = %entry + ret i32 3456 + +bb4: ; preds = %entry + ret i32 0 + +bb5: ; preds = %entry + ret i32 12 +} diff --git a/test/CodeGen/Thumb2/thumb2-ldr.ll b/test/CodeGen/Thumb2/thumb2-ldr.ll new file mode 100644 index 0000000..19c7584 --- /dev/null +++ b/test/CodeGen/Thumb2/thumb2-ldr.ll @@ -0,0 +1,59 @@ +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {ldr r0} | count 7 +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep mov | grep 1 +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | not grep mvn +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep ldr | grep lsl +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep lsr | not grep ldr + +define i32 @f1(i32* %v) { +entry: + %tmp = load i32* %v + ret i32 %tmp +} + +define i32 @f2(i32* %v) { +entry: + %tmp2 = getelementptr i32* %v, i32 1023 + %tmp = load i32* %tmp2 + ret i32 %tmp +} + +define i32 @f3(i32* %v) { +entry: + %tmp2 = getelementptr i32* %v, i32 1024 + %tmp = load i32* %tmp2 + ret i32 %tmp +} + +define i32 @f4(i32 %base) { +entry: + %tmp1 = sub i32 %base, 128 + %tmp2 = inttoptr i32 %tmp1 to i32* + %tmp3 = load i32* %tmp2 + ret i32 %tmp3 +} + +define i32 @f5(i32 %base, i32 %offset) { +entry: + %tmp1 = add i32 %base, %offset + %tmp2 = inttoptr i32 %tmp1 to i32* + %tmp3 = load i32* %tmp2 + ret i32 %tmp3 +} + +define i32 @f6(i32 %base, i32 %offset) { +entry: + %tmp1 = shl i32 %offset, 2 + %tmp2 = add i32 %base, %tmp1 + %tmp3 = inttoptr i32 %tmp2 to i32* + %tmp4 = load i32* %tmp3 + ret i32 %tmp4 +} + +define i32 @f7(i32 %base, i32 %offset) { +entry: + %tmp1 = lshr i32 %offset, 2 + %tmp2 = add i32 %base, %tmp1 + %tmp3 = inttoptr i32 %tmp2 to i32* + %tmp4 = load i32* %tmp3 + ret i32 %tmp4 +} diff --git a/test/CodeGen/Thumb2/thumb2-ldr_ext.ll b/test/CodeGen/Thumb2/thumb2-ldr_ext.ll new file mode 100644 index 0000000..d48ecef --- /dev/null +++ b/test/CodeGen/Thumb2/thumb2-ldr_ext.ll @@ -0,0 +1,28 @@ +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep ldrb | count 1 +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep ldrh | count 1 +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep ldrsb | count 1 +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep ldrsh | count 1 + +define i32 @test1(i8* %v.pntr.s0.u1) { + %tmp.u = load i8* %v.pntr.s0.u1 + %tmp1.s = zext i8 %tmp.u to i32 + ret i32 %tmp1.s +} + +define i32 @test2(i16* %v.pntr.s0.u1) { + %tmp.u = load i16* %v.pntr.s0.u1 + %tmp1.s = zext i16 %tmp.u to i32 + ret i32 %tmp1.s +} + +define i32 @test3(i8* %v.pntr.s1.u0) { + %tmp.s = load i8* %v.pntr.s1.u0 + %tmp1.s = sext i8 %tmp.s to i32 + ret i32 %tmp1.s +} + +define i32 @test4() { + %tmp.s = load i16* null + %tmp1.s = sext i16 %tmp.s to i32 + ret i32 %tmp1.s +} diff --git a/test/CodeGen/Thumb2/thumb2-ldr_post.ll b/test/CodeGen/Thumb2/thumb2-ldr_post.ll new file mode 100644 index 0000000..79ffa82 --- /dev/null +++ b/test/CodeGen/Thumb2/thumb2-ldr_post.ll @@ -0,0 +1,12 @@ +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | \ +; RUN: grep {ldr.*\\\[.*\],} | count 1 + +define i32 @test(i32 %a, i32 %b, i32 %c) { + %tmp1 = mul i32 %a, %b ; <i32> [#uses=2] + %tmp2 = inttoptr i32 %tmp1 to i32* ; <i32*> [#uses=1] + %tmp3 = load i32* %tmp2 ; <i32> [#uses=1] + %tmp4 = sub i32 %tmp1, 8 ; <i32> [#uses=1] + %tmp5 = mul i32 %tmp4, %tmp3 ; <i32> [#uses=1] + ret i32 %tmp5 +} + diff --git a/test/CodeGen/Thumb2/thumb2-ldr_pre.ll b/test/CodeGen/Thumb2/thumb2-ldr_pre.ll new file mode 100644 index 0000000..f773e63 --- /dev/null +++ b/test/CodeGen/Thumb2/thumb2-ldr_pre.ll @@ -0,0 +1,28 @@ +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | \ +; RUN: grep {ldr.*\\!} | count 3 +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | \ +; RUN: grep {ldrsb.*\\!} | count 1 + +define i32* @test1(i32* %X, i32* %dest) { + %Y = getelementptr i32* %X, i32 4 ; <i32*> [#uses=2] + %A = load i32* %Y ; <i32> [#uses=1] + store i32 %A, i32* %dest + ret i32* %Y +} + +define i32 @test2(i32 %a, i32 %b) { + %tmp1 = sub i32 %a, 64 ; <i32> [#uses=2] + %tmp2 = inttoptr i32 %tmp1 to i32* ; <i32*> [#uses=1] + %tmp3 = load i32* %tmp2 ; <i32> [#uses=1] + %tmp4 = sub i32 %tmp1, %b ; <i32> [#uses=1] + %tmp5 = add i32 %tmp4, %tmp3 ; <i32> [#uses=1] + ret i32 %tmp5 +} + +define i8* @test3(i8* %X, i32* %dest) { + %tmp1 = getelementptr i8* %X, i32 4 + %tmp2 = load i8* %tmp1 + %tmp3 = sext i8 %tmp2 to i32 + store i32 %tmp3, i32* %dest + ret i8* %tmp1 +} diff --git a/test/CodeGen/Thumb2/thumb2-ldrb.ll b/test/CodeGen/Thumb2/thumb2-ldrb.ll new file mode 100644 index 0000000..5bacb8e --- /dev/null +++ b/test/CodeGen/Thumb2/thumb2-ldrb.ll @@ -0,0 +1,60 @@ +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {ldrb r0} | count 7 +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep mov | grep 1 +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | not grep mvn +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep ldrb | grep lsl +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep lsr | not grep ldrb + +define i8 @f1(i8* %v) { +entry: + %tmp = load i8* %v + ret i8 %tmp +} + +define i8 @f2(i8* %v) { +entry: + %tmp2 = getelementptr i8* %v, i8 1023 + %tmp = load i8* %tmp2 + ret i8 %tmp +} + +define i8 @f3(i32 %base) { +entry: + %tmp1 = add i32 %base, 4096 + %tmp2 = inttoptr i32 %tmp1 to i8* + %tmp3 = load i8* %tmp2 + ret i8 %tmp3 +} + +define i8 @f4(i32 %base) { +entry: + %tmp1 = sub i32 %base, 128 + %tmp2 = inttoptr i32 %tmp1 to i8* + %tmp3 = load i8* %tmp2 + ret i8 %tmp3 +} + +define i8 @f5(i32 %base, i32 %offset) { +entry: + %tmp1 = add i32 %base, %offset + %tmp2 = inttoptr i32 %tmp1 to i8* + %tmp3 = load i8* %tmp2 + ret i8 %tmp3 +} + +define i8 @f6(i32 %base, i32 %offset) { +entry: + %tmp1 = shl i32 %offset, 2 + %tmp2 = add i32 %base, %tmp1 + %tmp3 = inttoptr i32 %tmp2 to i8* + %tmp4 = load i8* %tmp3 + ret i8 %tmp4 +} + +define i8 @f7(i32 %base, i32 %offset) { +entry: + %tmp1 = lshr i32 %offset, 2 + %tmp2 = add i32 %base, %tmp1 + %tmp3 = inttoptr i32 %tmp2 to i8* + %tmp4 = load i8* %tmp3 + ret i8 %tmp4 +} diff --git a/test/CodeGen/Thumb2/thumb2-ldrh.ll b/test/CodeGen/Thumb2/thumb2-ldrh.ll new file mode 100644 index 0000000..15f803e --- /dev/null +++ b/test/CodeGen/Thumb2/thumb2-ldrh.ll @@ -0,0 +1,59 @@ +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {ldrh r0} | count 7 +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep mov | grep 1 +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | not grep mvn +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep ldrh | grep lsl +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep lsr | not grep ldrh + +define i16 @f1(i16* %v) { +entry: + %tmp = load i16* %v + ret i16 %tmp +} + +define i16 @f2(i16* %v) { +entry: + %tmp2 = getelementptr i16* %v, i16 1023 + %tmp = load i16* %tmp2 + ret i16 %tmp +} + +define i16 @f3(i16* %v) { +entry: + %tmp2 = getelementptr i16* %v, i16 2048 + %tmp = load i16* %tmp2 + ret i16 %tmp +} + +define i16 @f4(i32 %base) { +entry: + %tmp1 = sub i32 %base, 128 + %tmp2 = inttoptr i32 %tmp1 to i16* + %tmp3 = load i16* %tmp2 + ret i16 %tmp3 +} + +define i16 @f5(i32 %base, i32 %offset) { +entry: + %tmp1 = add i32 %base, %offset + %tmp2 = inttoptr i32 %tmp1 to i16* + %tmp3 = load i16* %tmp2 + ret i16 %tmp3 +} + +define i16 @f6(i32 %base, i32 %offset) { +entry: + %tmp1 = shl i32 %offset, 2 + %tmp2 = add i32 %base, %tmp1 + %tmp3 = inttoptr i32 %tmp2 to i16* + %tmp4 = load i16* %tmp3 + ret i16 %tmp4 +} + +define i16 @f7(i32 %base, i32 %offset) { +entry: + %tmp1 = lshr i32 %offset, 2 + %tmp2 = add i32 %base, %tmp1 + %tmp3 = inttoptr i32 %tmp2 to i16* + %tmp4 = load i16* %tmp3 + ret i16 %tmp4 +} diff --git a/test/CodeGen/Thumb2/thumb2-mvn2.ll b/test/CodeGen/Thumb2/thumb2-mvn2.ll index 178f02b..df9b11b 100644 --- a/test/CodeGen/Thumb2/thumb2-mvn2.ll +++ b/test/CodeGen/Thumb2/thumb2-mvn2.ll @@ -1,4 +1,8 @@ -; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {mvn\\W*r\[0-9\]*,\\W*r\[0-9\]*} | count 2 +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {mvn\\W*r\[0-9\]*,\\W*r\[0-9\]*$} | count 2 +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {mvn\\W*r\[0-9\],\\W*r\[0-9\],\\W*lsl\\W*#5$} | count 1 +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {mvn\\W*r\[0-9\],\\W*r\[0-9\],\\W*lsr\\W*#6$} | count 1 +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {mvn\\W*r\[0-9\],\\W*r\[0-9\],\\W*asr\\W*#7$} | count 1 +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {mvn\\W*r\[0-9\],\\W*r\[0-9\],\\W*ror\\W*#8$} | count 1 define i32 @f1(i32 %a) { %tmp = xor i32 4294967295, %a @@ -9,3 +13,29 @@ define i32 @f2(i32 %a) { %tmp = xor i32 %a, 4294967295 ret i32 %tmp } + +define i32 @f5(i32 %a) { + %tmp = shl i32 %a, 5 + %tmp1 = xor i32 %tmp, 4294967295 + ret i32 %tmp1 +} + +define i32 @f6(i32 %a) { + %tmp = lshr i32 %a, 6 + %tmp1 = xor i32 %tmp, 4294967295 + ret i32 %tmp1 +} + +define i32 @f7(i32 %a) { + %tmp = ashr i32 %a, 7 + %tmp1 = xor i32 %tmp, 4294967295 + ret i32 %tmp1 +} + +define i32 @f8(i32 %a) { + %l8 = shl i32 %a, 24 + %r8 = lshr i32 %a, 8 + %tmp = or i32 %l8, %r8 + %tmp1 = xor i32 %tmp, 4294967295 + ret i32 %tmp1 +} diff --git a/test/CodeGen/Thumb2/thumb2-orn.ll b/test/CodeGen/Thumb2/thumb2-orn.ll index 1add347..92c4564 100644 --- a/test/CodeGen/Thumb2/thumb2-orn.ll +++ b/test/CodeGen/Thumb2/thumb2-orn.ll @@ -1,4 +1,8 @@ -; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {orn\\W*r\[0-9\]*,\\W*r\[0-9\]*,\\W*r\[0-9\]*} | count 4 +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {orn\\W*r\[0-9\]*,\\W*r\[0-9\]*,\\W*r\[0-9\]*$} | count 4 +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {orn\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\],\\W*lsl\\W*#5$} | count 1 +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {orn\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\],\\W*lsr\\W*#6$} | count 1 +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {orn\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\],\\W*asr\\W*#7$} | count 1 +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {orn\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\],\\W*ror\\W*#8$} | count 1 define i32 @f1(i32 %a, i32 %b) { %tmp = xor i32 %b, 4294967295 @@ -23,3 +27,33 @@ define i32 @f4(i32 %a, i32 %b) { %tmp1 = or i32 %tmp, %a ret i32 %tmp1 } + +define i32 @f5(i32 %a, i32 %b) { + %tmp = shl i32 %b, 5 + %tmp1 = xor i32 4294967295, %tmp + %tmp2 = or i32 %a, %tmp1 + ret i32 %tmp2 +} + +define i32 @f6(i32 %a, i32 %b) { + %tmp = lshr i32 %b, 6 + %tmp1 = xor i32 4294967295, %tmp + %tmp2 = or i32 %a, %tmp1 + ret i32 %tmp2 +} + +define i32 @f7(i32 %a, i32 %b) { + %tmp = ashr i32 %b, 7 + %tmp1 = xor i32 4294967295, %tmp + %tmp2 = or i32 %a, %tmp1 + ret i32 %tmp2 +} + +define i32 @f8(i32 %a, i32 %b) { + %l8 = shl i32 %a, 24 + %r8 = lshr i32 %a, 8 + %tmp = or i32 %l8, %r8 + %tmp1 = xor i32 4294967295, %tmp + %tmp2 = or i32 %a, %tmp1 + ret i32 %tmp2 +} diff --git a/test/CodeGen/Thumb2/thumb2-orr.ll b/test/CodeGen/Thumb2/thumb2-orr.ll index 9222946..9891658 100644 --- a/test/CodeGen/Thumb2/thumb2-orr.ll +++ b/test/CodeGen/Thumb2/thumb2-orr.ll @@ -1,6 +1,36 @@ -; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {orr\\W*r\[0-9\]*,\\W*r\[0-9\]*,\\W*r\[0-9\]*} | count 1 +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {orr\\W*r\[0-9\]*,\\W*r\[0-9\]*,\\W*r\[0-9\]*$} | count 1 +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {orr\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\],\\W*lsl\\W*#5$} | count 1 +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {orr\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\],\\W*lsr\\W*#6$} | count 1 +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {orr\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\],\\W*asr\\W*#7$} | count 1 +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {orr\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\],\\W*ror\\W*#8$} | count 1 define i32 @f1(i32 %a, i32 %b) { %tmp2 = or i32 %a, %b ret i32 %tmp2 } + +define i32 @f5(i32 %a, i32 %b) { + %tmp = shl i32 %b, 5 + %tmp2 = or i32 %a, %tmp + ret i32 %tmp2 +} + +define i32 @f6(i32 %a, i32 %b) { + %tmp = lshr i32 %b, 6 + %tmp2 = or i32 %a, %tmp + ret i32 %tmp2 +} + +define i32 @f7(i32 %a, i32 %b) { + %tmp = ashr i32 %b, 7 + %tmp2 = or i32 %a, %tmp + ret i32 %tmp2 +} + +define i32 @f8(i32 %a, i32 %b) { + %l8 = shl i32 %a, 24 + %r8 = lshr i32 %a, 8 + %tmp = or i32 %l8, %r8 + %tmp2 = or i32 %a, %tmp + ret i32 %tmp2 +} diff --git a/test/CodeGen/Thumb2/thumb2-rsb.ll b/test/CodeGen/Thumb2/thumb2-rsb.ll index 934e377..5779687 100644 --- a/test/CodeGen/Thumb2/thumb2-rsb.ll +++ b/test/CodeGen/Thumb2/thumb2-rsb.ll @@ -1,9 +1,30 @@ -; XFAIL: * -; this will match as "sub" until we get register shifting +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {rsb\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\],\\W*lsl\\W*#5$} | count 1 +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {rsb\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\],\\W*lsr\\W*#6$} | count 1 +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {rsb\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\],\\W*asr\\W*#7$} | count 1 +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {rsb\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\],\\W*ror\\W*#8$} | count 1 -; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {rsb\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\]*} | count 1 +define i32 @f2(i32 %a, i32 %b) { + %tmp = shl i32 %b, 5 + %tmp1 = sub i32 %tmp, %a + ret i32 %tmp1 +} + +define i32 @f3(i32 %a, i32 %b) { + %tmp = lshr i32 %b, 6 + %tmp1 = sub i32 %tmp, %a + ret i32 %tmp1 +} + +define i32 @f4(i32 %a, i32 %b) { + %tmp = ashr i32 %b, 7 + %tmp1 = sub i32 %tmp, %a + ret i32 %tmp1 +} -define i32 @f1(i32 %a, i32 %b) { - %tmp = sub i32 %b, %a - ret i32 %tmp +define i32 @f5(i32 %a, i32 %b) { + %l8 = shl i32 %a, 24 + %r8 = lshr i32 %a, 8 + %tmp = or i32 %l8, %r8 + %tmp1 = sub i32 %tmp, %a + ret i32 %tmp1 } diff --git a/test/CodeGen/Thumb2/thumb2-sbc2.ll b/test/CodeGen/Thumb2/thumb2-sbc2.ll new file mode 100644 index 0000000..4302f76 --- /dev/null +++ b/test/CodeGen/Thumb2/thumb2-sbc2.ll @@ -0,0 +1,6 @@ +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {sbc\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\]*} | count 1 + +define i64 @f1(i64 %a, i64 %b) { + %tmp = sub i64 %a, %b + ret i64 %tmp +} diff --git a/test/CodeGen/Thumb2/thumb2-str.ll b/test/CodeGen/Thumb2/thumb2-str.ll new file mode 100644 index 0000000..4097a6c --- /dev/null +++ b/test/CodeGen/Thumb2/thumb2-str.ll @@ -0,0 +1,63 @@ +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {str\\W*r\[0-9\],\\W*\\\[r\[0-9\]*\\\]$} | count 1 +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {str\\W*r\[0-9\],\\W*\\\[r\[0-9\]*,\\W*#+4092\\\]$} | count 1 +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {str\\W*r\[0-9\],\\W*\\\[r\[0-9\]*,\\W*#-128\\\]$} | count 2 +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | not grep {str\\W*r\[0-9\],\\W*\\\[r\[0-9\]*,\\W*#+4096\\\]$} +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {str\\W*r\[0-9\],\\W*\\\[r\[0-9\]*,\\W*+r\[0-9\]*\\\]$} | count 3 +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {str\\W*r\[0-9\],\\W*\\\[r\[0-9\]*,\\W*+r\[0-9\]*,\\Wlsl #2\\\]$} | count 1 + +define i32 @f1(i32 %a, i32* %v) { + store i32 %a, i32* %v + ret i32 %a +} + +define i32 @f2(i32 %a, i32* %v) { + %tmp2 = getelementptr i32* %v, i32 1023 + store i32 %a, i32* %tmp2 + ret i32 %a +} + +define i32 @f2a(i32 %a, i32* %v) { + %tmp2 = getelementptr i32* %v, i32 -32 + store i32 %a, i32* %tmp2 + ret i32 %a +} + +define i32 @f3(i32 %a, i32* %v) { + %tmp2 = getelementptr i32* %v, i32 1024 + store i32 %a, i32* %tmp2 + ret i32 %a +} + +define i32 @f4(i32 %a, i32 %base) { +entry: + %tmp1 = sub i32 %base, 128 + %tmp2 = inttoptr i32 %tmp1 to i32* + store i32 %a, i32* %tmp2 + ret i32 %a +} + +define i32 @f5(i32 %a, i32 %base, i32 %offset) { +entry: + %tmp1 = add i32 %base, %offset + %tmp2 = inttoptr i32 %tmp1 to i32* + store i32 %a, i32* %tmp2 + ret i32 %a +} + +define i32 @f6(i32 %a, i32 %base, i32 %offset) { +entry: + %tmp1 = shl i32 %offset, 2 + %tmp2 = add i32 %base, %tmp1 + %tmp3 = inttoptr i32 %tmp2 to i32* + store i32 %a, i32* %tmp3 + ret i32 %a +} + +define i32 @f7(i32 %a, i32 %base, i32 %offset) { +entry: + %tmp1 = lshr i32 %offset, 2 + %tmp2 = add i32 %base, %tmp1 + %tmp3 = inttoptr i32 %tmp2 to i32* + store i32 %a, i32* %tmp3 + ret i32 %a +} diff --git a/test/CodeGen/Thumb2/thumb2-str_post.ll b/test/CodeGen/Thumb2/thumb2-str_post.ll new file mode 100644 index 0000000..536011c --- /dev/null +++ b/test/CodeGen/Thumb2/thumb2-str_post.ll @@ -0,0 +1,21 @@ +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | \ +; RUN: grep {strh .*\\\[.*\], #-4} | count 1 +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | \ +; RUN: grep {str .*\\\[.*\],} | count 1 + +define i16 @test1(i32* %X, i16* %A) { + %Y = load i32* %X ; <i32> [#uses=1] + %tmp1 = trunc i32 %Y to i16 ; <i16> [#uses=1] + store i16 %tmp1, i16* %A + %tmp2 = ptrtoint i16* %A to i16 ; <i16> [#uses=1] + %tmp3 = sub i16 %tmp2, 4 ; <i16> [#uses=1] + ret i16 %tmp3 +} + +define i32 @test2(i32* %X, i32* %A) { + %Y = load i32* %X ; <i32> [#uses=1] + store i32 %Y, i32* %A + %tmp1 = ptrtoint i32* %A to i32 ; <i32> [#uses=1] + %tmp2 = sub i32 %tmp1, 4 ; <i32> [#uses=1] + ret i32 %tmp2 +} diff --git a/test/CodeGen/Thumb2/thumb2-str_pre.ll b/test/CodeGen/Thumb2/thumb2-str_pre.ll new file mode 100644 index 0000000..1e93b70 --- /dev/null +++ b/test/CodeGen/Thumb2/thumb2-str_pre.ll @@ -0,0 +1,18 @@ +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | \ +; RUN: grep {str.*\\!} | count 2 + +define void @test1(i32* %X, i32* %A, i32** %dest) { + %B = load i32* %A ; <i32> [#uses=1] + %Y = getelementptr i32* %X, i32 4 ; <i32*> [#uses=2] + store i32 %B, i32* %Y + store i32* %Y, i32** %dest + ret void +} + +define i16* @test2(i16* %X, i32* %A) { + %B = load i32* %A ; <i32> [#uses=1] + %Y = getelementptr i16* %X, i32 4 ; <i16*> [#uses=2] + %tmp = trunc i32 %B to i16 ; <i16> [#uses=1] + store i16 %tmp, i16* %Y + ret i16* %Y +} diff --git a/test/CodeGen/Thumb2/thumb2-strb.ll b/test/CodeGen/Thumb2/thumb2-strb.ll new file mode 100644 index 0000000..d8401cd6 --- /dev/null +++ b/test/CodeGen/Thumb2/thumb2-strb.ll @@ -0,0 +1,63 @@ +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {strb\\W*r\[0-9\],\\W*\\\[r\[0-9\]*\\\]$} | count 1 +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {strb\\W*r\[0-9\],\\W*\\\[r\[0-9\]*,\\W*#+4092\\\]$} | count 1 +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {strb\\W*r\[0-9\],\\W*\\\[r\[0-9\]*,\\W*#-128\\\]$} | count 2 +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | not grep {strb\\W*r\[0-9\],\\W*\\\[r\[0-9\]*,\\W*#+4096\\\]$} +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {strb\\W*r\[0-9\],\\W*\\\[r\[0-9\]*,\\W*+r\[0-9\]*\\\]$} | count 3 +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {strb\\W*r\[0-9\],\\W*\\\[r\[0-9\]*,\\W*+r\[0-9\]*,\\Wlsl #2\\\]$} | count 1 + +define i8 @f1(i8 %a, i8* %v) { + store i8 %a, i8* %v + ret i8 %a +} + +define i8 @f2(i8 %a, i8* %v) { + %tmp2 = getelementptr i8* %v, i32 4092 + store i8 %a, i8* %tmp2 + ret i8 %a +} + +define i8 @f2a(i8 %a, i8* %v) { + %tmp2 = getelementptr i8* %v, i32 -128 + store i8 %a, i8* %tmp2 + ret i8 %a +} + +define i8 @f3(i8 %a, i8* %v) { + %tmp2 = getelementptr i8* %v, i32 4096 + store i8 %a, i8* %tmp2 + ret i8 %a +} + +define i8 @f4(i8 %a, i32 %base) { +entry: + %tmp1 = sub i32 %base, 128 + %tmp2 = inttoptr i32 %tmp1 to i8* + store i8 %a, i8* %tmp2 + ret i8 %a +} + +define i8 @f5(i8 %a, i32 %base, i32 %offset) { +entry: + %tmp1 = add i32 %base, %offset + %tmp2 = inttoptr i32 %tmp1 to i8* + store i8 %a, i8* %tmp2 + ret i8 %a +} + +define i8 @f6(i8 %a, i32 %base, i32 %offset) { +entry: + %tmp1 = shl i32 %offset, 2 + %tmp2 = add i32 %base, %tmp1 + %tmp3 = inttoptr i32 %tmp2 to i8* + store i8 %a, i8* %tmp3 + ret i8 %a +} + +define i8 @f7(i8 %a, i32 %base, i32 %offset) { +entry: + %tmp1 = lshr i32 %offset, 2 + %tmp2 = add i32 %base, %tmp1 + %tmp3 = inttoptr i32 %tmp2 to i8* + store i8 %a, i8* %tmp3 + ret i8 %a +} diff --git a/test/CodeGen/Thumb2/thumb2-strh.ll b/test/CodeGen/Thumb2/thumb2-strh.ll new file mode 100644 index 0000000..80dedf0 --- /dev/null +++ b/test/CodeGen/Thumb2/thumb2-strh.ll @@ -0,0 +1,63 @@ +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {strh\\W*r\[0-9\],\\W*\\\[r\[0-9\]*\\\]$} | count 1 +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {strh\\W*r\[0-9\],\\W*\\\[r\[0-9\]*,\\W*#+4092\\\]$} | count 1 +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {strh\\W*r\[0-9\],\\W*\\\[r\[0-9\]*,\\W*#-128\\\]$} | count 2 +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | not grep {strh\\W*r\[0-9\],\\W*\\\[r\[0-9\]*,\\W*#+4096\\\]$} +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {strh\\W*r\[0-9\],\\W*\\\[r\[0-9\]*,\\W*+r\[0-9\]*\\\]$} | count 3 +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {strh\\W*r\[0-9\],\\W*\\\[r\[0-9\]*,\\W*+r\[0-9\]*,\\Wlsl #2\\\]$} | count 1 + +define i16 @f1(i16 %a, i16* %v) { + store i16 %a, i16* %v + ret i16 %a +} + +define i16 @f2(i16 %a, i16* %v) { + %tmp2 = getelementptr i16* %v, i32 2046 + store i16 %a, i16* %tmp2 + ret i16 %a +} + +define i16 @f2a(i16 %a, i16* %v) { + %tmp2 = getelementptr i16* %v, i32 -64 + store i16 %a, i16* %tmp2 + ret i16 %a +} + +define i16 @f3(i16 %a, i16* %v) { + %tmp2 = getelementptr i16* %v, i32 2048 + store i16 %a, i16* %tmp2 + ret i16 %a +} + +define i16 @f4(i16 %a, i32 %base) { +entry: + %tmp1 = sub i32 %base, 128 + %tmp2 = inttoptr i32 %tmp1 to i16* + store i16 %a, i16* %tmp2 + ret i16 %a +} + +define i16 @f5(i16 %a, i32 %base, i32 %offset) { +entry: + %tmp1 = add i32 %base, %offset + %tmp2 = inttoptr i32 %tmp1 to i16* + store i16 %a, i16* %tmp2 + ret i16 %a +} + +define i16 @f6(i16 %a, i32 %base, i32 %offset) { +entry: + %tmp1 = shl i32 %offset, 2 + %tmp2 = add i32 %base, %tmp1 + %tmp3 = inttoptr i32 %tmp2 to i16* + store i16 %a, i16* %tmp3 + ret i16 %a +} + +define i16 @f7(i16 %a, i32 %base, i32 %offset) { +entry: + %tmp1 = lshr i32 %offset, 2 + %tmp2 = add i32 %base, %tmp1 + %tmp3 = inttoptr i32 %tmp2 to i16* + store i16 %a, i16* %tmp3 + ret i16 %a +} diff --git a/test/CodeGen/Thumb2/thumb2-sub.ll b/test/CodeGen/Thumb2/thumb2-sub.ll new file mode 100644 index 0000000..cf82704 --- /dev/null +++ b/test/CodeGen/Thumb2/thumb2-sub.ll @@ -0,0 +1,31 @@ +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {sub\[w\]\\?\\W*r\[0-9\],\\W*r\[0-9\],\\W*#\[0-9\]*} | grep {#171\\|#1179666\\|#872428544\\|#1448498774\\|#510} | count 5 + +; 171 = 0x000000ab +define i32 @f1(i32 %a) { + %tmp = sub i32 %a, 171 + ret i32 %tmp +} + +; 1179666 = 0x00120012 +define i32 @f2(i32 %a) { + %tmp = sub i32 %a, 1179666 + ret i32 %tmp +} + +; 872428544 = 0x34003400 +define i32 @f3(i32 %a) { + %tmp = sub i32 %a, 872428544 + ret i32 %tmp +} + +; 1448498774 = 0x56565656 +define i32 @f4(i32 %a) { + %tmp = sub i32 %a, 1448498774 + ret i32 %tmp +} + +; 510 = 0x000001fe +define i32 @f5(i32 %a) { + %tmp = sub i32 %a, 510 + ret i32 %tmp +} diff --git a/test/CodeGen/Thumb2/thumb2-sub2.ll b/test/CodeGen/Thumb2/thumb2-sub2.ll new file mode 100644 index 0000000..c7ebd22 --- /dev/null +++ b/test/CodeGen/Thumb2/thumb2-sub2.ll @@ -0,0 +1,6 @@ +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {subw\\W*r\[0-9\],\\W*r\[0-9\],\\W*#\[0-9\]*} | grep {#4095} | count 1 + +define i32 @f1(i32 %a) { + %tmp = sub i32 %a, 4095 + ret i32 %tmp +} diff --git a/test/CodeGen/Thumb2/thumb2-sub4.ll b/test/CodeGen/Thumb2/thumb2-sub4.ll new file mode 100644 index 0000000..fd283fd --- /dev/null +++ b/test/CodeGen/Thumb2/thumb2-sub4.ll @@ -0,0 +1,36 @@ +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {sub\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\]$} | count 1 +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {sub\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\],\\W*lsl\\W*#5$} | count 1 +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {sub\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\],\\W*lsr\\W*#6$} | count 1 +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {sub\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\],\\W*asr\\W*#7$} | count 1 +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {sub\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\],\\W*ror\\W*#8$} | count 1 + +define i32 @f1(i32 %a, i32 %b) { + %tmp = sub i32 %a, %b + ret i32 %tmp +} + +define i32 @f2(i32 %a, i32 %b) { + %tmp = shl i32 %b, 5 + %tmp1 = sub i32 %a, %tmp + ret i32 %tmp1 +} + +define i32 @f3(i32 %a, i32 %b) { + %tmp = lshr i32 %b, 6 + %tmp1 = sub i32 %a, %tmp + ret i32 %tmp1 +} + +define i32 @f4(i32 %a, i32 %b) { + %tmp = ashr i32 %b, 7 + %tmp1 = sub i32 %a, %tmp + ret i32 %tmp1 +} + +define i32 @f5(i32 %a, i32 %b) { + %l8 = shl i32 %a, 24 + %r8 = lshr i32 %a, 8 + %tmp = or i32 %l8, %r8 + %tmp1 = sub i32 %a, %tmp + ret i32 %tmp1 +} diff --git a/test/CodeGen/Thumb2/thumb2-sub5.ll b/test/CodeGen/Thumb2/thumb2-sub5.ll new file mode 100644 index 0000000..3e9ec25 --- /dev/null +++ b/test/CodeGen/Thumb2/thumb2-sub5.ll @@ -0,0 +1,6 @@ +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {subs\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\]} | count 1 + +define i64 @f1(i64 %a, i64 %b) { + %tmp = sub i64 %a, %b + ret i64 %tmp +} diff --git a/test/CodeGen/Thumb2/thumb2-sxt_rot.ll b/test/CodeGen/Thumb2/thumb2-sxt_rot.ll new file mode 100644 index 0000000..4afe354 --- /dev/null +++ b/test/CodeGen/Thumb2/thumb2-sxt_rot.ll @@ -0,0 +1,29 @@ +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | \ +; RUN: grep sxtb | count 2 +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | \ +; RUN: grep sxtb | grep ror | count 1 +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | \ +; RUN: grep sxtab | count 1 + +define i32 @test0(i8 %A) { + %B = sext i8 %A to i32 + ret i32 %B +} + +define i8 @test1(i32 %A) signext { + %B = lshr i32 %A, 8 + %C = shl i32 %A, 24 + %D = or i32 %B, %C + %E = trunc i32 %D to i8 + ret i8 %E +} + +define i32 @test2(i32 %A, i32 %X) signext { + %B = lshr i32 %A, 8 + %C = shl i32 %A, 24 + %D = or i32 %B, %C + %E = trunc i32 %D to i8 + %F = sext i8 %E to i32 + %G = add i32 %F, %X + ret i32 %G +} diff --git a/test/CodeGen/Thumb2/thumb2-teq.ll b/test/CodeGen/Thumb2/thumb2-teq.ll new file mode 100644 index 0000000..c3c2094 --- /dev/null +++ b/test/CodeGen/Thumb2/thumb2-teq.ll @@ -0,0 +1,71 @@ +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {teq\\W*r\[0-9\],\\W*#\[0-9\]*} | grep {#187\\|#11141290\\|#3422604288\\|#1114112\\|#3722304989} | count 10 + +; 0x000000bb = 187 +define i1 @f1(i32 %a) { + %tmp = xor i32 %a, 187 + %tmp1 = icmp ne i32 %tmp, 0 + ret i1 %tmp1 +} + +; 0x000000bb = 187 +define i1 @f2(i32 %a) { + %tmp = xor i32 %a, 187 + %tmp1 = icmp eq i32 0, %tmp + ret i1 %tmp1 +} + +; 0x00aa00aa = 11141290 +define i1 @f3(i32 %a) { + %tmp = xor i32 %a, 11141290 + %tmp1 = icmp eq i32 %tmp, 0 + ret i1 %tmp1 +} + +; 0x00aa00aa = 11141290 +define i1 @f4(i32 %a) { + %tmp = xor i32 %a, 11141290 + %tmp1 = icmp ne i32 0, %tmp + ret i1 %tmp1 +} + +; 0xcc00cc00 = 3422604288 +define i1 @f5(i32 %a) { + %tmp = xor i32 %a, 3422604288 + %tmp1 = icmp ne i32 %tmp, 0 + ret i1 %tmp1 +} + +; 0xcc00cc00 = 3422604288 +define i1 @f6(i32 %a) { + %tmp = xor i32 %a, 3422604288 + %tmp1 = icmp eq i32 0, %tmp + ret i1 %tmp1 +} + +; 0xdddddddd = 3722304989 +define i1 @f7(i32 %a) { + %tmp = xor i32 %a, 3722304989 + %tmp1 = icmp eq i32 %tmp, 0 + ret i1 %tmp1 +} + +; 0xdddddddd = 3722304989 +define i1 @f8(i32 %a) { + %tmp = xor i32 %a, 3722304989 + %tmp1 = icmp ne i32 0, %tmp + ret i1 %tmp1 +} + +; 0x00110000 = 1114112 +define i1 @f9(i32 %a) { + %tmp = xor i32 %a, 1114112 + %tmp1 = icmp ne i32 %tmp, 0 + ret i1 %tmp1 +} + +; 0x00110000 = 1114112 +define i1 @f10(i32 %a) { + %tmp = xor i32 %a, 1114112 + %tmp1 = icmp eq i32 0, %tmp + ret i1 %tmp1 +} diff --git a/test/CodeGen/Thumb2/thumb2-teq2.ll b/test/CodeGen/Thumb2/thumb2-teq2.ll new file mode 100644 index 0000000..fe2b2c8 --- /dev/null +++ b/test/CodeGen/Thumb2/thumb2-teq2.ll @@ -0,0 +1,59 @@ +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {teq\\W*r\[0-9\],\\W*r\[0-9\]$} | count 4 +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {teq\\W*r\[0-9\],\\W*r\[0-9\],\\W*lsl\\W*#5$} | count 1 +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {teq\\W*r\[0-9\],\\W*r\[0-9\],\\W*lsr\\W*#6$} | count 1 +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {teq\\W*r\[0-9\],\\W*r\[0-9\],\\W*asr\\W*#7$} | count 1 +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {teq\\W*r\[0-9\],\\W*r\[0-9\],\\W*ror\\W*#8$} | count 1 + +define i1 @f1(i32 %a, i32 %b) { + %tmp = xor i32 %a, %b + %tmp1 = icmp ne i32 %tmp, 0 + ret i1 %tmp1 +} + +define i1 @f2(i32 %a, i32 %b) { + %tmp = xor i32 %a, %b + %tmp1 = icmp eq i32 %tmp, 0 + ret i1 %tmp1 +} + +define i1 @f3(i32 %a, i32 %b) { + %tmp = xor i32 %a, %b + %tmp1 = icmp ne i32 0, %tmp + ret i1 %tmp1 +} + +define i1 @f4(i32 %a, i32 %b) { + %tmp = xor i32 %a, %b + %tmp1 = icmp eq i32 0, %tmp + ret i1 %tmp1 +} + +define i1 @f6(i32 %a, i32 %b) { + %tmp = shl i32 %b, 5 + %tmp1 = xor i32 %a, %tmp + %tmp2 = icmp eq i32 %tmp1, 0 + ret i1 %tmp2 +} + +define i1 @f7(i32 %a, i32 %b) { + %tmp = lshr i32 %b, 6 + %tmp1 = xor i32 %a, %tmp + %tmp2 = icmp eq i32 %tmp1, 0 + ret i1 %tmp2 +} + +define i1 @f8(i32 %a, i32 %b) { + %tmp = ashr i32 %b, 7 + %tmp1 = xor i32 %a, %tmp + %tmp2 = icmp eq i32 %tmp1, 0 + ret i1 %tmp2 +} + +define i1 @f9(i32 %a, i32 %b) { + %l8 = shl i32 %a, 24 + %r8 = lshr i32 %a, 8 + %tmp = or i32 %l8, %r8 + %tmp1 = xor i32 %a, %tmp + %tmp2 = icmp eq i32 %tmp1, 0 + ret i1 %tmp2 +} diff --git a/test/CodeGen/Thumb2/thumb2-tst.ll b/test/CodeGen/Thumb2/thumb2-tst.ll new file mode 100644 index 0000000..9e2d3e5 --- /dev/null +++ b/test/CodeGen/Thumb2/thumb2-tst.ll @@ -0,0 +1,71 @@ +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {tst\\W*r\[0-9\],\\W*#\[0-9\]*} | grep {#187\\|#11141290\\|#3422604288\\|#1114112\\|#3722304989} | count 10 + +; 0x000000bb = 187 +define i1 @f1(i32 %a) { + %tmp = and i32 %a, 187 + %tmp1 = icmp ne i32 %tmp, 0 + ret i1 %tmp1 +} + +; 0x000000bb = 187 +define i1 @f2(i32 %a) { + %tmp = and i32 %a, 187 + %tmp1 = icmp eq i32 0, %tmp + ret i1 %tmp1 +} + +; 0x00aa00aa = 11141290 +define i1 @f3(i32 %a) { + %tmp = and i32 %a, 11141290 + %tmp1 = icmp eq i32 %tmp, 0 + ret i1 %tmp1 +} + +; 0x00aa00aa = 11141290 +define i1 @f4(i32 %a) { + %tmp = and i32 %a, 11141290 + %tmp1 = icmp ne i32 0, %tmp + ret i1 %tmp1 +} + +; 0xcc00cc00 = 3422604288 +define i1 @f5(i32 %a) { + %tmp = and i32 %a, 3422604288 + %tmp1 = icmp ne i32 %tmp, 0 + ret i1 %tmp1 +} + +; 0xcc00cc00 = 3422604288 +define i1 @f6(i32 %a) { + %tmp = and i32 %a, 3422604288 + %tmp1 = icmp eq i32 0, %tmp + ret i1 %tmp1 +} + +; 0xdddddddd = 3722304989 +define i1 @f7(i32 %a) { + %tmp = and i32 %a, 3722304989 + %tmp1 = icmp eq i32 %tmp, 0 + ret i1 %tmp1 +} + +; 0xdddddddd = 3722304989 +define i1 @f8(i32 %a) { + %tmp = and i32 %a, 3722304989 + %tmp1 = icmp ne i32 0, %tmp + ret i1 %tmp1 +} + +; 0x00110000 = 1114112 +define i1 @f9(i32 %a) { + %tmp = and i32 %a, 1114112 + %tmp1 = icmp ne i32 %tmp, 0 + ret i1 %tmp1 +} + +; 0x00110000 = 1114112 +define i1 @f10(i32 %a) { + %tmp = and i32 %a, 1114112 + %tmp1 = icmp eq i32 0, %tmp + ret i1 %tmp1 +} diff --git a/test/CodeGen/Thumb2/thumb2-tst2.ll b/test/CodeGen/Thumb2/thumb2-tst2.ll new file mode 100644 index 0000000..c0f404c --- /dev/null +++ b/test/CodeGen/Thumb2/thumb2-tst2.ll @@ -0,0 +1,59 @@ +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {tst\\W*r\[0-9\],\\W*r\[0-9\]$} | count 4 +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {tst\\W*r\[0-9\],\\W*r\[0-9\],\\W*lsl\\W*#5$} | count 1 +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {tst\\W*r\[0-9\],\\W*r\[0-9\],\\W*lsr\\W*#6$} | count 1 +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {tst\\W*r\[0-9\],\\W*r\[0-9\],\\W*asr\\W*#7$} | count 1 +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep {tst\\W*r\[0-9\],\\W*r\[0-9\],\\W*ror\\W*#8$} | count 1 + +define i1 @f1(i32 %a, i32 %b) { + %tmp = and i32 %a, %b + %tmp1 = icmp ne i32 %tmp, 0 + ret i1 %tmp1 +} + +define i1 @f2(i32 %a, i32 %b) { + %tmp = and i32 %a, %b + %tmp1 = icmp eq i32 %tmp, 0 + ret i1 %tmp1 +} + +define i1 @f3(i32 %a, i32 %b) { + %tmp = and i32 %a, %b + %tmp1 = icmp ne i32 0, %tmp + ret i1 %tmp1 +} + +define i1 @f4(i32 %a, i32 %b) { + %tmp = and i32 %a, %b + %tmp1 = icmp eq i32 0, %tmp + ret i1 %tmp1 +} + +define i1 @f6(i32 %a, i32 %b) { + %tmp = shl i32 %b, 5 + %tmp1 = and i32 %a, %tmp + %tmp2 = icmp eq i32 %tmp1, 0 + ret i1 %tmp2 +} + +define i1 @f7(i32 %a, i32 %b) { + %tmp = lshr i32 %b, 6 + %tmp1 = and i32 %a, %tmp + %tmp2 = icmp eq i32 %tmp1, 0 + ret i1 %tmp2 +} + +define i1 @f8(i32 %a, i32 %b) { + %tmp = ashr i32 %b, 7 + %tmp1 = and i32 %a, %tmp + %tmp2 = icmp eq i32 %tmp1, 0 + ret i1 %tmp2 +} + +define i1 @f9(i32 %a, i32 %b) { + %l8 = shl i32 %a, 24 + %r8 = lshr i32 %a, 8 + %tmp = or i32 %l8, %r8 + %tmp1 = and i32 %a, %tmp + %tmp2 = icmp eq i32 %tmp1, 0 + ret i1 %tmp2 +} diff --git a/test/CodeGen/Thumb2/thumb2-uxt_rot.ll b/test/CodeGen/Thumb2/thumb2-uxt_rot.ll new file mode 100644 index 0000000..0d1cc18 --- /dev/null +++ b/test/CodeGen/Thumb2/thumb2-uxt_rot.ll @@ -0,0 +1,24 @@ +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep uxtb | count 1 +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep uxtab | count 1 +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep uxth | count 1 + +define i8 @test1(i32 %A.u) zeroext { + %B.u = trunc i32 %A.u to i8 + ret i8 %B.u +} + +define i32 @test2(i32 %A.u, i32 %B.u) zeroext { + %C.u = trunc i32 %B.u to i8 + %D.u = zext i8 %C.u to i32 + %E.u = add i32 %A.u, %D.u + ret i32 %E.u +} + +define i32 @test3(i32 %A.u) zeroext { + %B.u = lshr i32 %A.u, 8 + %C.u = shl i32 %A.u, 24 + %D.u = or i32 %B.u, %C.u + %E.u = trunc i32 %D.u to i16 + %F.u = zext i16 %E.u to i32 + ret i32 %F.u +} diff --git a/test/CodeGen/Thumb2/thumb2-uxtb.ll b/test/CodeGen/Thumb2/thumb2-uxtb.ll new file mode 100644 index 0000000..28a5fe4 --- /dev/null +++ b/test/CodeGen/Thumb2/thumb2-uxtb.ll @@ -0,0 +1,74 @@ +; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | \ +; RUN: grep uxt | count 10 + +define i32 @test1(i32 %x) { + %tmp1 = and i32 %x, 16711935 ; <i32> [#uses=1] + ret i32 %tmp1 +} + +define i32 @test2(i32 %x) { + %tmp1 = lshr i32 %x, 8 ; <i32> [#uses=1] + %tmp2 = and i32 %tmp1, 16711935 ; <i32> [#uses=1] + ret i32 %tmp2 +} + +define i32 @test3(i32 %x) { + %tmp1 = lshr i32 %x, 8 ; <i32> [#uses=1] + %tmp2 = and i32 %tmp1, 16711935 ; <i32> [#uses=1] + ret i32 %tmp2 +} + +define i32 @test4(i32 %x) { + %tmp1 = lshr i32 %x, 8 ; <i32> [#uses=1] + %tmp6 = and i32 %tmp1, 16711935 ; <i32> [#uses=1] + ret i32 %tmp6 +} + +define i32 @test5(i32 %x) { + %tmp1 = lshr i32 %x, 8 ; <i32> [#uses=1] + %tmp2 = and i32 %tmp1, 16711935 ; <i32> [#uses=1] + ret i32 %tmp2 +} + +define i32 @test6(i32 %x) { + %tmp1 = lshr i32 %x, 16 ; <i32> [#uses=1] + %tmp2 = and i32 %tmp1, 255 ; <i32> [#uses=1] + %tmp4 = shl i32 %x, 16 ; <i32> [#uses=1] + %tmp5 = and i32 %tmp4, 16711680 ; <i32> [#uses=1] + %tmp6 = or i32 %tmp2, %tmp5 ; <i32> [#uses=1] + ret i32 %tmp6 +} + +define i32 @test7(i32 %x) { + %tmp1 = lshr i32 %x, 16 ; <i32> [#uses=1] + %tmp2 = and i32 %tmp1, 255 ; <i32> [#uses=1] + %tmp4 = shl i32 %x, 16 ; <i32> [#uses=1] + %tmp5 = and i32 %tmp4, 16711680 ; <i32> [#uses=1] + %tmp6 = or i32 %tmp2, %tmp5 ; <i32> [#uses=1] + ret i32 %tmp6 +} + +define i32 @test8(i32 %x) { + %tmp1 = shl i32 %x, 8 ; <i32> [#uses=1] + %tmp2 = and i32 %tmp1, 16711680 ; <i32> [#uses=1] + %tmp5 = lshr i32 %x, 24 ; <i32> [#uses=1] + %tmp6 = or i32 %tmp2, %tmp5 ; <i32> [#uses=1] + ret i32 %tmp6 +} + +define i32 @test9(i32 %x) { + %tmp1 = lshr i32 %x, 24 ; <i32> [#uses=1] + %tmp4 = shl i32 %x, 8 ; <i32> [#uses=1] + %tmp5 = and i32 %tmp4, 16711680 ; <i32> [#uses=1] + %tmp6 = or i32 %tmp5, %tmp1 ; <i32> [#uses=1] + ret i32 %tmp6 +} + +define i32 @test10(i32 %p0) { + %tmp1 = lshr i32 %p0, 7 ; <i32> [#uses=1] + %tmp2 = and i32 %tmp1, 16253176 ; <i32> [#uses=2] + %tmp4 = lshr i32 %tmp2, 5 ; <i32> [#uses=1] + %tmp5 = and i32 %tmp4, 458759 ; <i32> [#uses=1] + %tmp7 = or i32 %tmp5, %tmp2 ; <i32> [#uses=1] + ret i32 %tmp7 +} diff --git a/test/CodeGen/Thumb2/tls1.ll b/test/CodeGen/Thumb2/tls1.ll new file mode 100644 index 0000000..6abb6eb --- /dev/null +++ b/test/CodeGen/Thumb2/tls1.ll @@ -0,0 +1,20 @@ +; RUN: llvm-as < %s | llc -mtriple=thumbv7-linux-gnueabi | \ +; RUN: grep {i(tpoff)} +; RUN: llvm-as < %s | llc -mtriple=thumbv7-linux-gnueabi | \ +; RUN: grep {__aeabi_read_tp} +; RUN: llvm-as < %s | llc -mtriple=thumbv7-linux-gnueabi \ +; RUN: -relocation-model=pic | grep {__tls_get_addr} + + +@i = thread_local global i32 15 ; <i32*> [#uses=2] + +define i32 @f() { +entry: + %tmp1 = load i32* @i ; <i32> [#uses=1] + ret i32 %tmp1 +} + +define i32* @g() { +entry: + ret i32* @i +} diff --git a/test/CodeGen/Thumb2/tls2.ll b/test/CodeGen/Thumb2/tls2.ll new file mode 100644 index 0000000..3396b0b --- /dev/null +++ b/test/CodeGen/Thumb2/tls2.ll @@ -0,0 +1,19 @@ +; RUN: llvm-as < %s | llc -mtriple=thumbv7-linux-gnueabi | \ +; RUN: grep {i(gottpoff)} +; RUN: llvm-as < %s | llc -mtriple=thumbv7-linux-gnueabi | \ +; RUN: grep {ldr r., \[pc, r.\]} +; RUN: llvm-as < %s | llc -mtriple=thumbv7-linux-gnueabi \ +; RUN: -relocation-model=pic | grep {__tls_get_addr} + +@i = external thread_local global i32 ; <i32*> [#uses=2] + +define i32 @f() { +entry: + %tmp1 = load i32* @i ; <i32> [#uses=1] + ret i32 %tmp1 +} + +define i32* @g() { +entry: + ret i32* @i +} diff --git a/test/CodeGen/X86/fast-isel-constpool.ll b/test/CodeGen/X86/fast-isel-constpool.ll new file mode 100644 index 0000000..ac2595a --- /dev/null +++ b/test/CodeGen/X86/fast-isel-constpool.ll @@ -0,0 +1,17 @@ +; RUN: llvm-as < %s | llc -fast-isel | grep {LCPI1_0(%rip)} +; Make sure fast isel uses rip-relative addressing when required. +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" +target triple = "x86_64-apple-darwin9.0" + +define i32 @f0(double %x) nounwind { +entry: + %retval = alloca i32 ; <i32*> [#uses=2] + %x.addr = alloca double ; <double*> [#uses=2] + store double %x, double* %x.addr + %tmp = load double* %x.addr ; <double> [#uses=1] + %cmp = fcmp olt double %tmp, 8.500000e-01 ; <i1> [#uses=1] + %conv = zext i1 %cmp to i32 ; <i32> [#uses=1] + store i32 %conv, i32* %retval + %0 = load i32* %retval ; <i32> [#uses=1] + ret i32 %0 +} diff --git a/test/CodeGen/X86/fast-isel-gv.ll b/test/CodeGen/X86/fast-isel-gv.ll new file mode 100644 index 0000000..b2f8850 --- /dev/null +++ b/test/CodeGen/X86/fast-isel-gv.ll @@ -0,0 +1,24 @@ +; RUN: llvm-as < %s | llc -fast-isel | grep {_kill@GOTPCREL(%rip)} +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" +target triple = "x86_64-apple-darwin10.0" +@f = global i8 (...)* @kill ; <i8 (...)**> [#uses=1] + +declare signext i8 @kill(...) + +define i32 @main() nounwind ssp { +entry: + %retval = alloca i32 ; <i32*> [#uses=2] + %0 = alloca i32 ; <i32*> [#uses=2] + %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] + %1 = load i8 (...)** @f, align 8 ; <i8 (...)*> [#uses=1] + %2 = icmp ne i8 (...)* %1, @kill ; <i1> [#uses=1] + %3 = zext i1 %2 to i32 ; <i32> [#uses=1] + store i32 %3, i32* %0, align 4 + %4 = load i32* %0, align 4 ; <i32> [#uses=1] + store i32 %4, i32* %retval, align 4 + br label %return + +return: ; preds = %entry + %retval1 = load i32* %retval ; <i32> [#uses=1] + ret i32 %retval1 +} diff --git a/test/CodeGen/X86/inline-asm-fpstack3.ll b/test/CodeGen/X86/inline-asm-fpstack3.ll new file mode 100644 index 0000000..ac89a1d --- /dev/null +++ b/test/CodeGen/X86/inline-asm-fpstack3.ll @@ -0,0 +1,15 @@ +; RUN: llvm-as < %s | llc -march=x86 > %t +; RUN: grep {fld %%st(0)} %t +; PR4459 + +declare x86_fp80 @ceil(x86_fp80) + +declare void @test(x86_fp80) + +define void @test2(x86_fp80 %a) { +entry: + %0 = call x86_fp80 @ceil(x86_fp80 %a) + call void asm sideeffect "fistpl $0", "{st}"( x86_fp80 %0) + call void @test(x86_fp80 %0 ) + ret void +} diff --git a/test/CodeGen/X86/inline-asm-fpstack4.ll b/test/CodeGen/X86/inline-asm-fpstack4.ll new file mode 100644 index 0000000..c9122fa --- /dev/null +++ b/test/CodeGen/X86/inline-asm-fpstack4.ll @@ -0,0 +1,15 @@ +; RUN: llvm-as < %s | llc -march=x86 +; PR4484 + +declare x86_fp80 @ceil() + +declare void @test(x86_fp80) + +define void @test2(x86_fp80 %a) { +entry: + %0 = call x86_fp80 @ceil() + call void asm sideeffect "fistpl $0", "{st},~{st}"(x86_fp80 %a) + call void @test(x86_fp80 %0) + ret void +} + diff --git a/test/CodeGen/X86/inline-asm-fpstack5.ll b/test/CodeGen/X86/inline-asm-fpstack5.ll new file mode 100644 index 0000000..64f3788 --- /dev/null +++ b/test/CodeGen/X86/inline-asm-fpstack5.ll @@ -0,0 +1,15 @@ +; RUN: llvm-as < %s | llc -march=x86 +; PR4485 + +define void @test(x86_fp80* %a) { +entry: + %0 = load x86_fp80* %a, align 16 + %1 = fmul x86_fp80 %0, 0xK4006B400000000000000 + %2 = fmul x86_fp80 %1, 0xK4012F424000000000000 + tail call void asm sideeffect "fistpl $0", "{st},~{st}"(x86_fp80 %2) + %3 = load x86_fp80* %a, align 16 + %4 = fmul x86_fp80 %3, 0xK4006B400000000000000 + %5 = fmul x86_fp80 %4, 0xK4012F424000000000000 + tail call void asm sideeffect "fistpl $0", "{st},~{st}"(x86_fp80 %5) + ret void +} |
