diff options
Diffstat (limited to 'test/CodeGen')
32 files changed, 211 insertions, 66 deletions
diff --git a/test/CodeGen/ARM/2009-10-27-double-align.ll b/test/CodeGen/ARM/2009-10-27-double-align.ll index a4e7685..f17d059 100644 --- a/test/CodeGen/ARM/2009-10-27-double-align.ll +++ b/test/CodeGen/ARM/2009-10-27-double-align.ll @@ -4,8 +4,8 @@ define arm_aapcscc void @g() { entry: -;CHECK: [sp, #+8] -;CHECK: [sp, #+12] +;CHECK: [sp, #8] +;CHECK: [sp, #12] ;CHECK: [sp] tail call arm_aapcscc void (i8*, ...)* @f(i8* getelementptr ([1 x i8]* @.str, i32 0, i32 0), i32 1, double 2.000000e+00, i32 3, double 4.000000e+00) ret void diff --git a/test/CodeGen/ARM/2009-10-30.ll b/test/CodeGen/ARM/2009-10-30.ll index 90a5bd2..87d1a8b 100644 --- a/test/CodeGen/ARM/2009-10-30.ll +++ b/test/CodeGen/ARM/2009-10-30.ll @@ -6,7 +6,7 @@ define void @f(i32 %a1, i32 %a2, i32 %a3, i32 %a4, i32 %a5, ...) { entry: ;CHECK: sub sp, sp, #4 ;CHECK: add r{{[0-9]+}}, sp, #8 -;CHECK: str r{{[0-9]+}}, [sp], #+4 +;CHECK: str r{{[0-9]+}}, [sp], #4 ;CHECK: bx lr %ap = alloca i8*, align 4 %ap1 = bitcast i8** %ap to i8* diff --git a/test/CodeGen/ARM/2010-03-18-ldm-rtrn.ll b/test/CodeGen/ARM/2010-03-18-ldm-rtrn.ll new file mode 100644 index 0000000..31525ef --- /dev/null +++ b/test/CodeGen/ARM/2010-03-18-ldm-rtrn.ll @@ -0,0 +1,13 @@ +; RUN: llc < %s -mtriple=armv4-unknown-eabi | FileCheck %s +; RUN: llc < %s -mtriple=armv5-unknown-eabi | FileCheck %s +; RUN: llc < %s -mtriple=armv6-unknown-eabi | FileCheck %s + +define i32 @bar(i32 %a) nounwind { +entry: + %0 = tail call i32 @foo(i32 %a) nounwind ; <i32> [#uses=1] + %1 = add nsw i32 %0, 3 ; <i32> [#uses=1] +; CHECK: ldmia sp!, {r11, pc} + ret i32 %1 +} + +declare i32 @foo(i32) diff --git a/test/CodeGen/ARM/arm-negative-stride.ll b/test/CodeGen/ARM/arm-negative-stride.ll index 52ab871..fb0f8ff 100644 --- a/test/CodeGen/ARM/arm-negative-stride.ll +++ b/test/CodeGen/ARM/arm-negative-stride.ll @@ -5,7 +5,7 @@ define void @test(i32* %P, i32 %A, i32 %i) nounwind { entry: -; CHECK: str r1, [{{r.*}}, +{{r.*}}, lsl #2] +; CHECK: str r1, [{{r.*}}, {{r.*}}, lsl #2] icmp eq i32 %i, 0 ; <i1>:0 [#uses=1] br i1 %0, label %return, label %bb diff --git a/test/CodeGen/ARM/globals.ll b/test/CodeGen/ARM/globals.ll index 886c0d5..adb4497 100644 --- a/test/CodeGen/ARM/globals.ll +++ b/test/CodeGen/ARM/globals.ll @@ -41,7 +41,7 @@ define i32 @test1() { ; DarwinPIC: _test1: ; DarwinPIC: ldr r0, LCPI1_0 ; DarwinPIC: LPC1_0: -; DarwinPIC: ldr r0, [pc, +r0] +; DarwinPIC: ldr r0, [pc, r0] ; DarwinPIC: ldr r0, [r0] ; DarwinPIC: bx lr @@ -63,7 +63,7 @@ define i32 @test1() { ; LinuxPIC: .LPC1_0: ; LinuxPIC: add r0, pc, r0 -; LinuxPIC: ldr r0, [r1, +r0] +; LinuxPIC: ldr r0, [r1, r0] ; LinuxPIC: ldr r0, [r0] ; LinuxPIC: bx lr diff --git a/test/CodeGen/ARM/ifcvt5.ll b/test/CodeGen/ARM/ifcvt5.ll index 623f2cb..8677ce5 100644 --- a/test/CodeGen/ARM/ifcvt5.ll +++ b/test/CodeGen/ARM/ifcvt5.ll @@ -11,7 +11,7 @@ entry: define void @t1(i32 %a, i32 %b) { ; CHECK: t1: -; CHECK: ldmfdlt sp!, {r7, pc} +; CHECK: ldmialt sp!, {r7, pc} entry: %tmp1 = icmp sgt i32 %a, 10 ; <i1> [#uses=1] br i1 %tmp1, label %cond_true, label %UnifiedReturnBlock diff --git a/test/CodeGen/ARM/ifcvt6.ll b/test/CodeGen/ARM/ifcvt6.ll index d7fcf7d..342208b 100644 --- a/test/CodeGen/ARM/ifcvt6.ll +++ b/test/CodeGen/ARM/ifcvt6.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=arm -mtriple=arm-apple-darwin | \ ; RUN: grep cmpne | count 1 ; RUN: llc < %s -march=arm -mtriple=arm-apple-darwin | \ -; RUN: grep ldmfdhi | count 1 +; RUN: grep ldmiahi | count 1 define void @foo(i32 %X, i32 %Y) { entry: diff --git a/test/CodeGen/ARM/ifcvt7.ll b/test/CodeGen/ARM/ifcvt7.ll index c60ad93..eb97085 100644 --- a/test/CodeGen/ARM/ifcvt7.ll +++ b/test/CodeGen/ARM/ifcvt7.ll @@ -3,7 +3,7 @@ ; RUN: llc < %s -march=arm -mtriple=arm-apple-darwin | \ ; RUN: grep moveq | count 1 ; RUN: llc < %s -march=arm -mtriple=arm-apple-darwin | \ -; RUN: grep ldmfdeq | count 1 +; RUN: grep ldmiaeq | count 1 ; FIXME: Need post-ifcvt branch folding to get rid of the extra br at end of BB1. %struct.quad_struct = type { i32, i32, %struct.quad_struct*, %struct.quad_struct*, %struct.quad_struct*, %struct.quad_struct*, %struct.quad_struct* } diff --git a/test/CodeGen/ARM/ifcvt8.ll b/test/CodeGen/ARM/ifcvt8.ll index a7da834..1e39060 100644 --- a/test/CodeGen/ARM/ifcvt8.ll +++ b/test/CodeGen/ARM/ifcvt8.ll @@ -1,5 +1,5 @@ ; RUN: llc < %s -march=arm -mtriple=arm-apple-darwin | \ -; RUN: grep ldmfdne | count 1 +; RUN: grep ldmiane | count 1 %struct.SString = type { i8*, i32, i32 } diff --git a/test/CodeGen/ARM/ldm.ll b/test/CodeGen/ARM/ldm.ll index 1a016a0..9a2dc82 100644 --- a/test/CodeGen/ARM/ldm.ll +++ b/test/CodeGen/ARM/ldm.ll @@ -24,7 +24,7 @@ define i32 @t2() { define i32 @t3() { ; CHECK: t3: ; CHECK: ldmib -; CHECK: ldmfd sp! +; CHECK: ldmia sp! %tmp = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 1) ; <i32> [#uses=1] %tmp3 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 2) ; <i32> [#uses=1] %tmp5 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 3) ; <i32> [#uses=1] diff --git a/test/CodeGen/ARM/ldrd.ll b/test/CodeGen/ARM/ldrd.ll index c366e2d..895562a 100644 --- a/test/CodeGen/ARM/ldrd.ll +++ b/test/CodeGen/ARM/ldrd.ll @@ -10,10 +10,10 @@ entry: ;V6: ldrd r2, [r2] ;V5: ldr r3, [r2] -;V5: ldr r2, [r2, #+4] +;V5: ldr r2, [r2, #4] ;EABI: ldr r3, [r2] -;EABI: ldr r2, [r2, #+4] +;EABI: ldr r2, [r2, #4] %0 = load i64** @b, align 4 %1 = load i64* %0, align 4 diff --git a/test/CodeGen/ARM/str_pre-2.ll b/test/CodeGen/ARM/str_pre-2.ll index f8d3df2..553cd64 100644 --- a/test/CodeGen/ARM/str_pre-2.ll +++ b/test/CodeGen/ARM/str_pre-2.ll @@ -1,5 +1,5 @@ ; RUN: llc < %s -mtriple=arm-linux-gnu | grep {str.*\\!} -; RUN: llc < %s -mtriple=arm-linux-gnu | grep {ldr.*\\\[.*\], #+4} +; RUN: llc < %s -mtriple=arm-linux-gnu | grep {ldr.*\\\[.*\], #4} @b = external global i64* diff --git a/test/CodeGen/ARM/tls2.ll b/test/CodeGen/ARM/tls2.ll index d932f90..57370c4 100644 --- a/test/CodeGen/ARM/tls2.ll +++ b/test/CodeGen/ARM/tls2.ll @@ -7,7 +7,7 @@ define i32 @f() { ; CHECK-NONPIC: f: -; CHECK-NONPIC: ldr {{r.}}, [pc, +{{r.}}] +; CHECK-NONPIC: ldr {{r.}}, [pc, {{r.}}] ; CHECK-NONPIC: i(gottpoff) ; CHECK-PIC: f: ; CHECK-PIC: __tls_get_addr @@ -18,7 +18,7 @@ entry: define i32* @g() { ; CHECK-NONPIC: g: -; CHECK-NONPIC: ldr {{r.}}, [pc, +{{r.}}] +; CHECK-NONPIC: ldr {{r.}}, [pc, {{r.}}] ; CHECK-NONPIC: i(gottpoff) ; CHECK-PIC: g: ; CHECK-PIC: __tls_get_addr diff --git a/test/CodeGen/Generic/dbg_value.ll b/test/CodeGen/Generic/dbg_value.ll new file mode 100644 index 0000000..ce3364d --- /dev/null +++ b/test/CodeGen/Generic/dbg_value.ll @@ -0,0 +1,13 @@ +; RUN: llc < %s +; rdar://7759395 + +%0 = type { i32, i32 } + +define void @t(%0*, i32, i32, i32, i32) nounwind { + tail call void @llvm.dbg.value(metadata !{%0* %0}, i64 0, metadata !0) + unreachable +} + +declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone + +!0 = metadata !{i32 0} ; diff --git a/test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll b/test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll index b4b6ed9..bfb7f6e 100644 --- a/test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll +++ b/test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll @@ -12,10 +12,10 @@ define weak arm_aapcs_vfpcc i32 @_ZNKSs7compareERKSs(%"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >"* %this, %"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >"* %__str) { ; CHECK: _ZNKSs7compareERKSs: ; CHECK: it ne -; CHECK-NEXT: ldmfdne.w +; CHECK-NEXT: ldmiane.w ; CHECK-NEXT: itt eq ; CHECK-NEXT: subeq.w -; CHECK-NEXT: ldmfdeq.w +; CHECK-NEXT: ldmiaeq.w entry: %0 = tail call arm_aapcs_vfpcc i32 @_ZNKSs4sizeEv(%"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >"* %this) ; <i32> [#uses=3] %1 = tail call arm_aapcs_vfpcc i32 @_ZNKSs4sizeEv(%"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >"* %__str) ; <i32> [#uses=3] diff --git a/test/CodeGen/Thumb2/large-stack.ll b/test/CodeGen/Thumb2/large-stack.ll index fe0e506..9729534 100644 --- a/test/CodeGen/Thumb2/large-stack.ll +++ b/test/CodeGen/Thumb2/large-stack.ll @@ -27,7 +27,7 @@ define i32 @test3() { ; DARWIN: sub.w sp, sp, #805306368 ; DARWIN: sub sp, #20 ; LINUX: test3: -; LINUX: stmfd sp!, {r4, r7, r11, lr} +; LINUX: stmdb sp!, {r4, r7, r11, lr} ; LINUX: sub.w sp, sp, #805306368 ; LINUX: sub sp, #16 %retval = alloca i32, align 4 diff --git a/test/CodeGen/Thumb2/ldr-str-imm12.ll b/test/CodeGen/Thumb2/ldr-str-imm12.ll index f007b5c..55cdac9 100644 --- a/test/CodeGen/Thumb2/ldr-str-imm12.ll +++ b/test/CodeGen/Thumb2/ldr-str-imm12.ll @@ -22,7 +22,7 @@ define arm_apcscc %union.rec* @Manifest(%union.rec* %x, %union.rec* %env, %struct.STYLE* %style, %union.rec** %bthr, %union.rec** %fthr, %union.rec** %target, %union.rec** %crs, i32 %ok, i32 %need_expand, %union.rec** %enclose, i32 %fcr) nounwind { entry: -; CHECK: ldr.w r9, [r7, #+28] +; CHECK: ldr.w r9, [r7, #28] %xgaps.i = alloca [32 x %union.rec*], align 4 ; <[32 x %union.rec*]*> [#uses=0] %ycomp.i = alloca [32 x %union.rec*], align 4 ; <[32 x %union.rec*]*> [#uses=0] br i1 false, label %bb, label %bb20 @@ -50,9 +50,9 @@ bb119: ; preds = %bb20, %bb20 bb420: ; preds = %bb20, %bb20 ; CHECK: bb420 ; CHECK: str r{{[0-7]}}, [sp] -; CHECK: str r{{[0-7]}}, [sp, #+4] -; CHECK: str r{{[0-7]}}, [sp, #+8] -; CHECK: str{{(.w)?}} r{{[0-9]+}}, [sp, #+24] +; CHECK: str r{{[0-7]}}, [sp, #4] +; CHECK: str r{{[0-7]}}, [sp, #8] +; CHECK: str{{(.w)?}} r{{[0-9]+}}, [sp, #24] store %union.rec* null, %union.rec** @zz_hold, align 4 store %union.rec* null, %union.rec** @zz_res, align 4 store %union.rec* %x, %union.rec** @zz_hold, align 4 diff --git a/test/CodeGen/Thumb2/thumb2-ldr.ll b/test/CodeGen/Thumb2/thumb2-ldr.ll index 94888fd..88434f1 100644 --- a/test/CodeGen/Thumb2/thumb2-ldr.ll +++ b/test/CodeGen/Thumb2/thumb2-ldr.ll @@ -11,7 +11,7 @@ entry: define i32 @f2(i32* %v) { entry: ; CHECK: f2: -; CHECK: ldr.w r0, [r0, #+4092] +; CHECK: ldr.w r0, [r0, #4092] %tmp2 = getelementptr i32* %v, i32 1023 %tmp = load i32* %tmp2 ret i32 %tmp diff --git a/test/CodeGen/Thumb2/thumb2-ldrh.ll b/test/CodeGen/Thumb2/thumb2-ldrh.ll index f1fb79c..fee97bf 100644 --- a/test/CodeGen/Thumb2/thumb2-ldrh.ll +++ b/test/CodeGen/Thumb2/thumb2-ldrh.ll @@ -11,7 +11,7 @@ entry: define i16 @f2(i16* %v) { entry: ; CHECK: f2: -; CHECK: ldrh.w r0, [r0, #+2046] +; CHECK: ldrh.w r0, [r0, #2046] %tmp2 = getelementptr i16* %v, i16 1023 %tmp = load i16* %tmp2 ret i16 %tmp diff --git a/test/CodeGen/Thumb2/thumb2-str.ll b/test/CodeGen/Thumb2/thumb2-str.ll index 3eeec8c..11bb936 100644 --- a/test/CodeGen/Thumb2/thumb2-str.ll +++ b/test/CodeGen/Thumb2/thumb2-str.ll @@ -9,7 +9,7 @@ define i32 @f1(i32 %a, i32* %v) { define i32 @f2(i32 %a, i32* %v) { ; CHECK: f2: -; CHECK: str.w r0, [r1, #+4092] +; CHECK: str.w r0, [r1, #4092] %tmp2 = getelementptr i32* %v, i32 1023 store i32 %a, i32* %tmp2 ret i32 %a diff --git a/test/CodeGen/Thumb2/thumb2-str_pre.ll b/test/CodeGen/Thumb2/thumb2-str_pre.ll index 9af960b..1e6616a 100644 --- a/test/CodeGen/Thumb2/thumb2-str_pre.ll +++ b/test/CodeGen/Thumb2/thumb2-str_pre.ll @@ -2,7 +2,7 @@ define void @test1(i32* %X, i32* %A, i32** %dest) { ; CHECK: test1 -; CHECK: str r1, [r0, #+16]! +; CHECK: str r1, [r0, #16]! %B = load i32* %A ; <i32> [#uses=1] %Y = getelementptr i32* %X, i32 4 ; <i32*> [#uses=2] store i32 %B, i32* %Y @@ -12,7 +12,7 @@ define void @test1(i32* %X, i32* %A, i32** %dest) { define i16* @test2(i16* %X, i32* %A) { ; CHECK: test2 -; CHECK: strh r1, [r0, #+8]! +; CHECK: strh r1, [r0, #8]! %B = load i32* %A ; <i32> [#uses=1] %Y = getelementptr i16* %X, i32 4 ; <i16*> [#uses=2] %tmp = trunc i32 %B to i16 ; <i16> [#uses=1] diff --git a/test/CodeGen/Thumb2/thumb2-strb.ll b/test/CodeGen/Thumb2/thumb2-strb.ll index 1ebb938..7978e7f 100644 --- a/test/CodeGen/Thumb2/thumb2-strb.ll +++ b/test/CodeGen/Thumb2/thumb2-strb.ll @@ -9,7 +9,7 @@ define i8 @f1(i8 %a, i8* %v) { define i8 @f2(i8 %a, i8* %v) { ; CHECK: f2: -; CHECK: strb.w r0, [r1, #+4092] +; CHECK: strb.w r0, [r1, #4092] %tmp2 = getelementptr i8* %v, i32 4092 store i8 %a, i8* %tmp2 ret i8 %a diff --git a/test/CodeGen/Thumb2/thumb2-strh.ll b/test/CodeGen/Thumb2/thumb2-strh.ll index b0eb8c1..97110a7 100644 --- a/test/CodeGen/Thumb2/thumb2-strh.ll +++ b/test/CodeGen/Thumb2/thumb2-strh.ll @@ -9,7 +9,7 @@ define i16 @f1(i16 %a, i16* %v) { define i16 @f2(i16 %a, i16* %v) { ; CHECK: f2: -; CHECK: strh.w r0, [r1, #+4092] +; CHECK: strh.w r0, [r1, #4092] %tmp2 = getelementptr i16* %v, i32 2046 store i16 %a, i16* %tmp2 ret i16 %a diff --git a/test/CodeGen/X86/2007-01-08-InstrSched.ll b/test/CodeGen/X86/2007-01-08-InstrSched.ll index 317ed0a..58e186b 100644 --- a/test/CodeGen/X86/2007-01-08-InstrSched.ll +++ b/test/CodeGen/X86/2007-01-08-InstrSched.ll @@ -11,12 +11,12 @@ define float @foo(float %x) nounwind { %tmp14 = fadd float %tmp12, %tmp7 ret float %tmp14 -; CHECK: mulss LCPI1_3(%rip) -; CHECK-NEXT: mulss LCPI1_0(%rip) -; CHECK-NEXT: mulss LCPI1_1(%rip) -; CHECK-NEXT: mulss LCPI1_2(%rip) -; CHECK-NEXT: addss -; CHECK-NEXT: addss -; CHECK-NEXT: addss -; CHECK-NEXT: ret +; CHECK: mulss LCPI1_0(%rip) +; CHECK: mulss LCPI1_1(%rip) +; CHECK: addss +; CHECK: mulss LCPI1_2(%rip) +; CHECK: addss +; CHECK: mulss LCPI1_3(%rip) +; CHECK: addss +; CHECK: ret } diff --git a/test/CodeGen/X86/2010-03-17-ISelBug.ll b/test/CodeGen/X86/2010-03-17-ISelBug.ll new file mode 100644 index 0000000..609b4e2 --- /dev/null +++ b/test/CodeGen/X86/2010-03-17-ISelBug.ll @@ -0,0 +1,39 @@ +; RUN: llc < %s -mtriple=i386-apple-darwin5 +; rdar://7761790 + +%"struct..0$_485" = type { i16, i16, i32 } +%union.PPToken = type { %"struct..0$_485" } +%struct.PPOperation = type { %union.PPToken, %union.PPToken, [6 x %union.PPToken], i32, i32, i32, [1 x i32], [0 x i8] } + +define i32* @t() align 2 nounwind { +entry: + %operation = alloca %struct.PPOperation, align 8 ; <%struct.PPOperation*> [#uses=2] + %0 = load i32*** null, align 4 ; [#uses=1] + %1 = ptrtoint i32** %0 to i32 ; <i32> [#uses=1] + %2 = sub nsw i32 %1, undef ; <i32> [#uses=2] + br i1 false, label %bb20, label %bb.nph380 + +bb20: ; preds = %entry + ret i32* null + +bb.nph380: ; preds = %entry + %scevgep403 = getelementptr %struct.PPOperation* %operation, i32 0, i32 1, i32 0, i32 2 ; <i32*> [#uses=1] + %3 = ashr i32 %2, 1 ; <i32> [#uses=1] + %tmp405 = and i32 %3, -2 ; <i32> [#uses=1] + %scevgep408 = getelementptr %struct.PPOperation* %operation, i32 0, i32 1, i32 0, i32 1 ; <i16*> [#uses=1] + %tmp410 = and i32 %2, -4 ; <i32> [#uses=1] + br label %bb169 + +bb169: ; preds = %bb169, %bb.nph380 + %index.6379 = phi i32 [ 0, %bb.nph380 ], [ %4, %bb169 ] ; <i32> [#uses=3] + %tmp404 = mul i32 %index.6379, -2 ; <i32> [#uses=1] + %tmp406 = add i32 %tmp405, %tmp404 ; <i32> [#uses=1] + %scevgep407 = getelementptr i32* %scevgep403, i32 %tmp406 ; <i32*> [#uses=1] + %tmp409 = mul i32 %index.6379, -4 ; <i32> [#uses=1] + %tmp411 = add i32 %tmp410, %tmp409 ; <i32> [#uses=1] + %scevgep412 = getelementptr i16* %scevgep408, i32 %tmp411 ; <i16*> [#uses=1] + store i16 undef, i16* %scevgep412, align 2 + store i32 undef, i32* %scevgep407, align 4 + %4 = add nsw i32 %index.6379, 1 ; <i32> [#uses=1] + br label %bb169 +} diff --git a/test/CodeGen/X86/gather-addresses.ll b/test/CodeGen/X86/gather-addresses.ll index 0719838..3e730de 100644 --- a/test/CodeGen/X86/gather-addresses.ll +++ b/test/CodeGen/X86/gather-addresses.ll @@ -1,4 +1,5 @@ ; RUN: llc -march=x86-64 < %s | FileCheck %s +; rdar://7398554 ; When doing vector gather-scatter index calculation with 32-bit indices, ; bounce the vector off of cache rather than shuffling each individual diff --git a/test/CodeGen/X86/lsr-reuse.ll b/test/CodeGen/X86/lsr-reuse.ll index 2f6fb3f..ab71555 100644 --- a/test/CodeGen/X86/lsr-reuse.ll +++ b/test/CodeGen/X86/lsr-reuse.ll @@ -8,10 +8,10 @@ target triple = "x86_64-unknown-unknown" ; CHECK: full_me_0: ; CHECK: movsd (%rsi), %xmm0 -; CHECK: addq $8, %rsi ; CHECK: mulsd (%rdx), %xmm0 -; CHECK: addq $8, %rdx ; CHECK: movsd %xmm0, (%rdi) +; CHECK: addq $8, %rsi +; CHECK: addq $8, %rdx ; CHECK: addq $8, %rdi ; CHECK: decq %rcx ; CHECK: jne @@ -53,10 +53,10 @@ return: ; CHECK: mulsd -2048(%rdx), %xmm0 ; CHECK: movsd %xmm0, -2048(%rdi) ; CHECK: movsd (%rsi), %xmm0 -; CHECK: addq $8, %rsi ; CHECK: divsd (%rdx), %xmm0 -; CHECK: addq $8, %rdx ; CHECK: movsd %xmm0, (%rdi) +; CHECK: addq $8, %rsi +; CHECK: addq $8, %rdx ; CHECK: addq $8, %rdi ; CHECK: decq %rcx ; CHECK: jne @@ -99,10 +99,10 @@ return: ; CHECK: mulsd (%rdx), %xmm0 ; CHECK: movsd %xmm0, (%rdi) ; CHECK: movsd -2048(%rsi), %xmm0 -; CHECK: addq $8, %rsi ; CHECK: divsd -2048(%rdx), %xmm0 -; CHECK: addq $8, %rdx ; CHECK: movsd %xmm0, -2048(%rdi) +; CHECK: addq $8, %rsi +; CHECK: addq $8, %rdx ; CHECK: addq $8, %rdi ; CHECK: decq %rcx ; CHECK: jne @@ -144,10 +144,10 @@ return: ; CHECK: mulsd (%rdx), %xmm0 ; CHECK: movsd %xmm0, (%rdi) ; CHECK: movsd -4096(%rsi), %xmm0 -; CHECK: addq $8, %rsi ; CHECK: divsd -4096(%rdx), %xmm0 -; CHECK: addq $8, %rdx ; CHECK: movsd %xmm0, -4096(%rdi) +; CHECK: addq $8, %rsi +; CHECK: addq $8, %rdx ; CHECK: addq $8, %rdi ; CHECK: decq %rcx ; CHECK: jne @@ -310,10 +310,10 @@ return: ; CHECK: addsd (%rsi), %xmm0 ; CHECK: movsd %xmm0, (%rdx) ; CHECK: movsd 40(%rdi), %xmm0 -; CHECK: addq $8, %rdi ; CHECK: subsd 40(%rsi), %xmm0 -; CHECK: addq $8, %rsi ; CHECK: movsd %xmm0, 40(%rdx) +; CHECK: addq $8, %rdi +; CHECK: addq $8, %rsi ; CHECK: addq $8, %rdx ; CHECK: decq %rcx ; CHECK: jne diff --git a/test/CodeGen/X86/sibcall.ll b/test/CodeGen/X86/sibcall.ll index 90315fd..ce35b45 100644 --- a/test/CodeGen/X86/sibcall.ll +++ b/test/CodeGen/X86/sibcall.ll @@ -57,11 +57,11 @@ define void @t5(void ()* nocapture %x) nounwind ssp { entry: ; 32: t5: ; 32-NOT: call -; 32: jmpl * +; 32: jmpl *4(%esp) ; 64: t5: ; 64-NOT: call -; 64: jmpq * +; 64: jmpq *%rdi tail call void %x() nounwind ret void } @@ -215,4 +215,59 @@ entry: ret %struct.ns* %0 } +; rdar://6195379 +; llvm can't do sibcall for this in 32-bit mode (yet). declare fastcc %struct.ns* @foo7(%struct.cp* byval align 4, i8 signext) nounwind ssp + +%struct.__block_descriptor = type { i64, i64 } +%struct.__block_descriptor_withcopydispose = type { i64, i64, i8*, i8* } +%struct.__block_literal_1 = type { i8*, i32, i32, i8*, %struct.__block_descriptor* } +%struct.__block_literal_2 = type { i8*, i32, i32, i8*, %struct.__block_descriptor_withcopydispose*, void ()* } + +define void @t14(%struct.__block_literal_2* nocapture %.block_descriptor) nounwind ssp { +entry: +; 64: t14: +; 64: movq 32(%rdi) +; 64-NOT: movq 16(%rdi) +; 64: jmpq *16(%rdi) + %0 = getelementptr inbounds %struct.__block_literal_2* %.block_descriptor, i64 0, i32 5 ; <void ()**> [#uses=1] + %1 = load void ()** %0, align 8 ; <void ()*> [#uses=2] + %2 = bitcast void ()* %1 to %struct.__block_literal_1* ; <%struct.__block_literal_1*> [#uses=1] + %3 = getelementptr inbounds %struct.__block_literal_1* %2, i64 0, i32 3 ; <i8**> [#uses=1] + %4 = load i8** %3, align 8 ; <i8*> [#uses=1] + %5 = bitcast i8* %4 to void (i8*)* ; <void (i8*)*> [#uses=1] + %6 = bitcast void ()* %1 to i8* ; <i8*> [#uses=1] + tail call void %5(i8* %6) nounwind + ret void +} + +; rdar://7726868 +%struct.foo = type { [4 x i32] } + +define void @t15(%struct.foo* noalias sret %agg.result) nounwind { +; 32: t15: +; 32: call {{_?}}f +; 32: ret $4 + +; 64: t15: +; 64: callq {{_?}}f +; 64: ret + tail call fastcc void @f(%struct.foo* noalias sret %agg.result) nounwind + ret void +} + +declare void @f(%struct.foo* noalias sret) nounwind + +define void @t16() nounwind ssp { +entry: +; 32: t16: +; 32: call {{_?}}bar4 +; 32: fstp + +; 64: t16: +; 64: jmp {{_?}}bar4 + %0 = tail call double @bar4() nounwind + ret void +} + +declare double @bar4() diff --git a/test/CodeGen/X86/sse2.ll b/test/CodeGen/X86/sse2.ll index f2b8010..20b8eac 100644 --- a/test/CodeGen/X86/sse2.ll +++ b/test/CodeGen/X86/sse2.ll @@ -10,10 +10,10 @@ define void @t1(<2 x double>* %r, <2 x double>* %A, double %B) nounwind { ; CHECK: t1: ; CHECK: movl 8(%esp), %eax -; CHECK-NEXT: movl 4(%esp), %ecx ; CHECK-NEXT: movapd (%eax), %xmm0 ; CHECK-NEXT: movlpd 12(%esp), %xmm0 -; CHECK-NEXT: movapd %xmm0, (%ecx) +; CHECK-NEXT: movl 4(%esp), %eax +; CHECK-NEXT: movapd %xmm0, (%eax) ; CHECK-NEXT: ret } @@ -26,9 +26,9 @@ define void @t2(<2 x double>* %r, <2 x double>* %A, double %B) nounwind { ; CHECK: t2: ; CHECK: movl 8(%esp), %eax -; CHECK-NEXT: movl 4(%esp), %ecx ; CHECK-NEXT: movapd (%eax), %xmm0 ; CHECK-NEXT: movhpd 12(%esp), %xmm0 -; CHECK-NEXT: movapd %xmm0, (%ecx) +; CHECK-NEXT: movl 4(%esp), %eax +; CHECK-NEXT: movapd %xmm0, (%eax) ; CHECK-NEXT: ret } diff --git a/test/CodeGen/X86/sse3.ll b/test/CodeGen/X86/sse3.ll index 921161e..e9c2c01 100644 --- a/test/CodeGen/X86/sse3.ll +++ b/test/CodeGen/X86/sse3.ll @@ -17,8 +17,8 @@ entry: ; X64: t0: ; X64: movddup (%rsi), %xmm0 -; X64: xorl %eax, %eax ; X64: pshuflw $0, %xmm0, %xmm0 +; X64: xorl %eax, %eax ; X64: pinsrw $0, %eax, %xmm0 ; X64: movaps %xmm0, (%rdi) ; X64: ret @@ -169,11 +169,11 @@ define internal void @t10() nounwind { ret void ; X64: t10: ; X64: pextrw $4, %xmm0, %eax -; X64: pextrw $6, %xmm0, %edx ; X64: movlhps %xmm1, %xmm1 ; X64: pshuflw $8, %xmm1, %xmm1 ; X64: pinsrw $2, %eax, %xmm1 -; X64: pinsrw $3, %edx, %xmm1 +; X64: pextrw $6, %xmm0, %eax +; X64: pinsrw $3, %eax, %xmm1 } @@ -184,8 +184,8 @@ entry: ret <8 x i16> %tmp7 ; X64: t11: -; X64: movlhps %xmm0, %xmm0 ; X64: movd %xmm1, %eax +; X64: movlhps %xmm0, %xmm0 ; X64: pshuflw $1, %xmm0, %xmm0 ; X64: pinsrw $1, %eax, %xmm0 ; X64: ret @@ -198,8 +198,8 @@ entry: ret <8 x i16> %tmp9 ; X64: t12: -; X64: movlhps %xmm0, %xmm0 ; X64: pextrw $3, %xmm1, %eax +; X64: movlhps %xmm0, %xmm0 ; X64: pshufhw $3, %xmm0, %xmm0 ; X64: pinsrw $5, %eax, %xmm0 ; X64: ret diff --git a/test/CodeGen/X86/sse42.ll b/test/CodeGen/X86/sse42.ll index c9c4d01..1723909 100644 --- a/test/CodeGen/X86/sse42.ll +++ b/test/CodeGen/X86/sse42.ll @@ -9,10 +9,10 @@ define i32 @crc32_8(i32 %a, i8 %b) nounwind { %tmp = call i32 @llvm.x86.sse42.crc32.8(i32 %a, i8 %b) ret i32 %tmp ; X32: _crc32_8: -; X32: crc32 8(%esp), %eax +; X32: crc32b 8(%esp), %eax ; X64: _crc32_8: -; X64: crc32 %sil, %eax +; X64: crc32b %sil, %eax } @@ -20,10 +20,10 @@ define i32 @crc32_16(i32 %a, i16 %b) nounwind { %tmp = call i32 @llvm.x86.sse42.crc32.16(i32 %a, i16 %b) ret i32 %tmp ; X32: _crc32_16: -; X32: crc32 8(%esp), %eax +; X32: crc32w 8(%esp), %eax ; X64: _crc32_16: -; X64: crc32 %si, %eax +; X64: crc32w %si, %eax } @@ -31,8 +31,8 @@ define i32 @crc32_32(i32 %a, i32 %b) nounwind { %tmp = call i32 @llvm.x86.sse42.crc32.32(i32 %a, i32 %b) ret i32 %tmp ; X32: _crc32_32: -; X32: crc32 8(%esp), %eax +; X32: crc32l 8(%esp), %eax ; X64: _crc32_32: -; X64: crc32 %esi, %eax +; X64: crc32l %esi, %eax } diff --git a/test/CodeGen/X86/widen_load-2.ll b/test/CodeGen/X86/widen_load-2.ll index 11383fa..58b557a 100644 --- a/test/CodeGen/X86/widen_load-2.ll +++ b/test/CodeGen/X86/widen_load-2.ll @@ -152,4 +152,28 @@ define void @add31i8(%i8vec31* nocapture sret %ret, %i8vec31* %ap, %i8vec31* %bp %x = add %i8vec31 %a, %b store %i8vec31 %x, %i8vec31* %ret, align 16 ret void -}
\ No newline at end of file +} + + +%i8vec3pack = type { <3 x i8>, i8 } +define %i8vec3pack @rot() nounwind { +; CHECK: shrb +entry: + %X = alloca %i8vec3pack, align 4 + %rot = alloca %i8vec3pack, align 4 + %result = alloca %i8vec3pack, align 4 + %storetmp = bitcast %i8vec3pack* %X to <3 x i8>* + store <3 x i8> <i8 -98, i8 -98, i8 -98>, <3 x i8>* %storetmp + %storetmp1 = bitcast %i8vec3pack* %rot to <3 x i8>* + store <3 x i8> <i8 1, i8 1, i8 1>, <3 x i8>* %storetmp1 + %tmp = load %i8vec3pack* %X + %extractVec = extractvalue %i8vec3pack %tmp, 0 + %tmp2 = load %i8vec3pack* %rot + %extractVec3 = extractvalue %i8vec3pack %tmp2, 0 + %shr = lshr <3 x i8> %extractVec, %extractVec3 + %storetmp4 = bitcast %i8vec3pack* %result to <3 x i8>* + store <3 x i8> %shr, <3 x i8>* %storetmp4 + %tmp5 = load %i8vec3pack* %result + ret %i8vec3pack %tmp5 +} + |
