diff options
Diffstat (limited to 'test/CodeGen/Thumb2')
22 files changed, 267 insertions, 55 deletions
diff --git a/test/CodeGen/Thumb2/2009-09-28-ITBlockBug.ll b/test/CodeGen/Thumb2/2009-09-28-ITBlockBug.ll index e84e867..8d03b52 100644 --- a/test/CodeGen/Thumb2/2009-09-28-ITBlockBug.ll +++ b/test/CodeGen/Thumb2/2009-09-28-ITBlockBug.ll @@ -6,10 +6,8 @@ define arm_apcscc void @t() nounwind { ; CHECK: t: -; CHECK: ittt eq -; CHECK-NEXT: addeq -; CHECK-NEXT: movweq -; CHECK-NEXT: movteq +; CHECK: it eq +; CHECK-NEXT: cmpeq entry: %pix_a.i294 = alloca [4 x %struct.pix_pos], align 4 ; <[4 x %struct.pix_pos]*> [#uses=2] br i1 undef, label %land.rhs, label %lor.end diff --git a/test/CodeGen/Thumb2/2009-11-11-ScavengerAssert.ll b/test/CodeGen/Thumb2/2009-11-11-ScavengerAssert.ll new file mode 100644 index 0000000..9f2e399 --- /dev/null +++ b/test/CodeGen/Thumb2/2009-11-11-ScavengerAssert.ll @@ -0,0 +1,85 @@ +; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 + +%struct.OP = type { %struct.OP*, %struct.OP*, %struct.OP* ()*, i32, i16, i16, i8, i8 } +%struct.SV = type { i8*, i32, i32 } + +declare arm_apcscc void @Perl_mg_set(%struct.SV*) nounwind + +define arm_apcscc %struct.OP* @Perl_pp_complement() nounwind { +entry: + %0 = load %struct.SV** null, align 4 ; <%struct.SV*> [#uses=2] + br i1 undef, label %bb21, label %bb5 + +bb5: ; preds = %entry + br i1 undef, label %bb13, label %bb6 + +bb6: ; preds = %bb5 + br i1 undef, label %bb8, label %bb7 + +bb7: ; preds = %bb6 + %1 = getelementptr inbounds %struct.SV* %0, i32 0, i32 0 ; <i8**> [#uses=1] + %2 = load i8** %1, align 4 ; <i8*> [#uses=1] + %3 = getelementptr inbounds i8* %2, i32 12 ; <i8*> [#uses=1] + %4 = bitcast i8* %3 to i32* ; <i32*> [#uses=1] + %5 = load i32* %4, align 4 ; <i32> [#uses=1] + %storemerge5 = xor i32 %5, -1 ; <i32> [#uses=1] + call arm_apcscc void @Perl_sv_setiv(%struct.SV* undef, i32 %storemerge5) nounwind + %6 = getelementptr inbounds %struct.SV* undef, i32 0, i32 2 ; <i32*> [#uses=1] + %7 = load i32* %6, align 4 ; <i32> [#uses=1] + %8 = and i32 %7, 16384 ; <i32> [#uses=1] + %9 = icmp eq i32 %8, 0 ; <i1> [#uses=1] + br i1 %9, label %bb12, label %bb11 + +bb8: ; preds = %bb6 + unreachable + +bb11: ; preds = %bb7 + call arm_apcscc void @Perl_mg_set(%struct.SV* undef) nounwind + br label %bb12 + +bb12: ; preds = %bb11, %bb7 + store %struct.SV* undef, %struct.SV** null, align 4 + br label %bb44 + +bb13: ; preds = %bb5 + %10 = call arm_apcscc i32 @Perl_sv_2uv(%struct.SV* %0) nounwind ; <i32> [#uses=0] + br i1 undef, label %bb.i, label %bb1.i + +bb.i: ; preds = %bb13 + call arm_apcscc void @Perl_sv_setiv(%struct.SV* undef, i32 undef) nounwind + br label %Perl_sv_setuv.exit + +bb1.i: ; preds = %bb13 + br label %Perl_sv_setuv.exit + +Perl_sv_setuv.exit: ; preds = %bb1.i, %bb.i + %11 = getelementptr inbounds %struct.SV* undef, i32 0, i32 2 ; <i32*> [#uses=1] + %12 = load i32* %11, align 4 ; <i32> [#uses=1] + %13 = and i32 %12, 16384 ; <i32> [#uses=1] + %14 = icmp eq i32 %13, 0 ; <i1> [#uses=1] + br i1 %14, label %bb20, label %bb19 + +bb19: ; preds = %Perl_sv_setuv.exit + call arm_apcscc void @Perl_mg_set(%struct.SV* undef) nounwind + br label %bb20 + +bb20: ; preds = %bb19, %Perl_sv_setuv.exit + store %struct.SV* undef, %struct.SV** null, align 4 + br label %bb44 + +bb21: ; preds = %entry + br i1 undef, label %bb23, label %bb22 + +bb22: ; preds = %bb21 + unreachable + +bb23: ; preds = %bb21 + unreachable + +bb44: ; preds = %bb20, %bb12 + ret %struct.OP* undef +} + +declare arm_apcscc void @Perl_sv_setiv(%struct.SV*, i32) nounwind + +declare arm_apcscc i32 @Perl_sv_2uv(%struct.SV*) nounwind diff --git a/test/CodeGen/Thumb2/2009-11-13-STRDBug.ll b/test/CodeGen/Thumb2/2009-11-13-STRDBug.ll new file mode 100644 index 0000000..8a67bb1 --- /dev/null +++ b/test/CodeGen/Thumb2/2009-11-13-STRDBug.ll @@ -0,0 +1,20 @@ +; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 +; rdar://7394794 + +define arm_apcscc void @lshift_double(i64 %l1, i64 %h1, i64 %count, i32 %prec, i64* nocapture %lv, i64* nocapture %hv, i32 %arith) nounwind { +entry: + %..i = select i1 false, i64 0, i64 0 ; <i64> [#uses=1] + br i1 undef, label %bb11.i, label %bb6.i + +bb6.i: ; preds = %entry + %0 = lshr i64 %h1, 0 ; <i64> [#uses=1] + store i64 %0, i64* %hv, align 4 + %1 = lshr i64 %l1, 0 ; <i64> [#uses=1] + %2 = or i64 0, %1 ; <i64> [#uses=1] + store i64 %2, i64* %lv, align 4 + br label %bb11.i + +bb11.i: ; preds = %bb6.i, %entry + store i64 %..i, i64* %lv, align 4 + ret void +} diff --git a/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll b/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll index 4320328..eefbae5 100644 --- a/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll +++ b/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -mcpu=cortex-a8 | grep fcpys | count 4 +; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -mcpu=cortex-a8 | grep vmov.f32 | count 4 define arm_apcscc void @fht(float* nocapture %fz, i16 signext %n) nounwind { entry: diff --git a/test/CodeGen/Thumb2/large-stack.ll b/test/CodeGen/Thumb2/large-stack.ll index 865b17b..18d507c 100644 --- a/test/CodeGen/Thumb2/large-stack.ll +++ b/test/CodeGen/Thumb2/large-stack.ll @@ -18,7 +18,7 @@ define void @test2() { define i32 @test3() { ; CHECK: test3: ; CHECK: sub.w sp, sp, #805306368 -; CHECK: sub sp, #4 * 4 +; CHECK: sub sp, #6 * 4 %retval = alloca i32, align 4 %tmp = alloca i32, align 4 %a = alloca [805306369 x i8], align 16 diff --git a/test/CodeGen/Thumb2/load-global.ll b/test/CodeGen/Thumb2/load-global.ll index 4fd4525..9286670 100644 --- a/test/CodeGen/Thumb2/load-global.ll +++ b/test/CodeGen/Thumb2/load-global.ll @@ -14,7 +14,7 @@ define i32 @test1() { ; PIC: _test1 ; PIC: add r0, pc -; PIC: .long L_G$non_lazy_ptr-(LPC0+4) +; PIC: .long L_G$non_lazy_ptr-(LPC1_0+4) ; LINUX: test1 ; LINUX: .long G(GOT) diff --git a/test/CodeGen/Thumb2/lsr-deficiency.ll b/test/CodeGen/Thumb2/lsr-deficiency.ll new file mode 100644 index 0000000..7b1b57a --- /dev/null +++ b/test/CodeGen/Thumb2/lsr-deficiency.ll @@ -0,0 +1,37 @@ +; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 -relocation-model=pic | FileCheck %s +; rdar://7387640 + +; FIXME: We still need to rewrite array reference iv of stride -4 with loop +; count iv of stride -1. + +@G = external global i32 ; <i32*> [#uses=2] +@array = external global i32* ; <i32**> [#uses=1] + +define arm_apcscc void @t() nounwind optsize { +; CHECK: t: +; CHECK: mov.w r2, #4000 +; CHECK: movw r3, #1001 +entry: + %.pre = load i32* @G, align 4 ; <i32> [#uses=1] + br label %bb + +bb: ; preds = %bb, %entry +; CHECK: LBB1_1: +; CHECK: subs r3, #1 +; CHECK: cmp r3, #0 +; CHECK: sub.w r2, r2, #4 + %0 = phi i32 [ %.pre, %entry ], [ %3, %bb ] ; <i32> [#uses=1] + %indvar = phi i32 [ 0, %entry ], [ %indvar.next, %bb ] ; <i32> [#uses=2] + %tmp5 = sub i32 1000, %indvar ; <i32> [#uses=1] + %1 = load i32** @array, align 4 ; <i32*> [#uses=1] + %scevgep = getelementptr i32* %1, i32 %tmp5 ; <i32*> [#uses=1] + %2 = load i32* %scevgep, align 4 ; <i32> [#uses=1] + %3 = add nsw i32 %2, %0 ; <i32> [#uses=2] + store i32 %3, i32* @G, align 4 + %indvar.next = add i32 %indvar, 1 ; <i32> [#uses=2] + %exitcond = icmp eq i32 %indvar.next, 1001 ; <i1> [#uses=1] + br i1 %exitcond, label %return, label %bb + +return: ; preds = %bb + ret void +} diff --git a/test/CodeGen/Thumb2/machine-licm.ll b/test/CodeGen/Thumb2/machine-licm.ll index 64309c4..912939b 100644 --- a/test/CodeGen/Thumb2/machine-licm.ll +++ b/test/CodeGen/Thumb2/machine-licm.ll @@ -1,5 +1,6 @@ ; RUN: llc < %s -mtriple=thumbv7-apple-darwin -relocation-model=pic -disable-fp-elim | FileCheck %s ; rdar://7353541 +; rdar://7354376 ; The generated code is no where near ideal. It's not recognizing the two ; constantpool entries being loaded can be merged into one. @@ -15,8 +16,13 @@ entry: bb.nph: ; preds = %entry ; CHECK: BB#1 -; CHECK: ldr{{.*}} r{{[0-9]+}}, LCPI1_0 -; CHECK: ldr{{.*}} r{{[0-9]+}}, LCPI1_1 +; CHECK: ldr.n r2, LCPI1_0 +; CHECK: add r2, pc +; CHECK: ldr r{{[0-9]+}}, [r2] +; CHECK: LBB1_2 +; CHECK: LCPI1_0: +; CHECK-NOT: LCPI1_1: +; CHECK: .section %.pre = load i32* @GV, align 4 ; <i32> [#uses=1] br label %bb diff --git a/test/CodeGen/Thumb2/thumb2-cbnz.ll b/test/CodeGen/Thumb2/thumb2-cbnz.ll index 64587c1..0fc6899 100644 --- a/test/CodeGen/Thumb2/thumb2-cbnz.ll +++ b/test/CodeGen/Thumb2/thumb2-cbnz.ll @@ -20,7 +20,8 @@ bb7: ; preds = %bb3 br i1 %a, label %bb11, label %bb9 bb9: ; preds = %bb7 -; CHECK: @ BB#2: +; CHECK: cmp r0, #0 +; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cbnz %0 = tail call arm_apcscc double @floor(double %b) nounwind readnone ; <double> [#uses=0] br label %bb11 diff --git a/test/CodeGen/Thumb2/thumb2-ifcvt3.ll b/test/CodeGen/Thumb2/thumb2-ifcvt3.ll index 1d45d3c..496158c 100644 --- a/test/CodeGen/Thumb2/thumb2-ifcvt3.ll +++ b/test/CodeGen/Thumb2/thumb2-ifcvt3.ll @@ -23,7 +23,7 @@ bb52: ; preds = %newFuncRoot ; CHECK: movne ; CHECK: moveq ; CHECK: pop -; CHECK-NEXT: LBB1_2: +; CHECK-NEXT: LBB1_1: %0 = load i64* @posed, align 4 ; <i64> [#uses=3] %1 = sub i64 %0, %.reload78 ; <i64> [#uses=1] %2 = ashr i64 %1, 1 ; <i64> [#uses=3] diff --git a/test/CodeGen/Thumb2/thumb2-jtb.ll b/test/CodeGen/Thumb2/thumb2-jtb.ll index 7d093ec..f5a56e5 100644 --- a/test/CodeGen/Thumb2/thumb2-jtb.ll +++ b/test/CodeGen/Thumb2/thumb2-jtb.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=thumb -mattr=+thumb2 | not grep tbb +; RUN: llc < %s -march=thumb -mattr=+thumb2 -arm-adjust-jump-tables=0 | not grep tbb ; Do not use tbb / tbh if any destination is before the jumptable. ; rdar://7102917 diff --git a/test/CodeGen/Thumb2/thumb2-select_xform.ll b/test/CodeGen/Thumb2/thumb2-select_xform.ll index b4274ad..44fa245 100644 --- a/test/CodeGen/Thumb2/thumb2-select_xform.ll +++ b/test/CodeGen/Thumb2/thumb2-select_xform.ll @@ -1,8 +1,12 @@ -; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep mov | count 3 -; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep mvn | count 1 -; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep it | count 3 +; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s define i32 @t1(i32 %a, i32 %b, i32 %c) nounwind { +; CHECK: t1 +; CHECK: mvn r0, #-2147483648 +; CHECK: cmp r2, #10 +; CHECK: add.w r0, r1, r0 +; CHECK: it gt +; CHECK: movgt r0, r1 %tmp1 = icmp sgt i32 %c, 10 %tmp2 = select i1 %tmp1, i32 0, i32 2147483647 %tmp3 = add i32 %tmp2, %b @@ -10,6 +14,12 @@ define i32 @t1(i32 %a, i32 %b, i32 %c) nounwind { } define i32 @t2(i32 %a, i32 %b, i32 %c) nounwind { +; CHECK: t2 +; CHECK: add.w r0, r1, #-2147483648 +; CHECK: cmp r2, #10 +; CHECK: it gt +; CHECK: movgt r0, r1 + %tmp1 = icmp sgt i32 %c, 10 %tmp2 = select i1 %tmp1, i32 0, i32 2147483648 %tmp3 = add i32 %tmp2, %b @@ -17,6 +27,11 @@ define i32 @t2(i32 %a, i32 %b, i32 %c) nounwind { } define i32 @t3(i32 %a, i32 %b, i32 %c, i32 %d) nounwind { +; CHECK: t3 +; CHECK: sub.w r0, r1, #10 +; CHECK: cmp r2, #10 +; CHECK: it gt +; CHECK: movgt r0, r1 %tmp1 = icmp sgt i32 %c, 10 %tmp2 = select i1 %tmp1, i32 0, i32 10 %tmp3 = sub i32 %b, %tmp2 diff --git a/test/CodeGen/Thumb2/thumb2-shifter.ll b/test/CodeGen/Thumb2/thumb2-shifter.ll index 7746cd3..b106ced 100644 --- a/test/CodeGen/Thumb2/thumb2-shifter.ll +++ b/test/CodeGen/Thumb2/thumb2-shifter.ll @@ -1,22 +1,24 @@ -; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep lsl -; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep lsr -; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep asr -; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep ror -; RUN: llc < %s -march=thumb -mattr=+thumb2 | not grep mov +; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s define i32 @t2ADDrs_lsl(i32 %X, i32 %Y) { +; CHECK: t2ADDrs_lsl +; CHECK: add.w r0, r0, r1, lsl #16 %A = shl i32 %Y, 16 %B = add i32 %X, %A ret i32 %B } define i32 @t2ADDrs_lsr(i32 %X, i32 %Y) { +; CHECK: t2ADDrs_lsr +; CHECK: add.w r0, r0, r1, lsr #16 %A = lshr i32 %Y, 16 %B = add i32 %X, %A ret i32 %B } define i32 @t2ADDrs_asr(i32 %X, i32 %Y) { +; CHECK: t2ADDrs_asr +; CHECK: add.w r0, r0, r1, asr #16 %A = ashr i32 %Y, 16 %B = add i32 %X, %A ret i32 %B @@ -24,6 +26,8 @@ define i32 @t2ADDrs_asr(i32 %X, i32 %Y) { ; i32 ror(n) = (x >> n) | (x << (32 - n)) define i32 @t2ADDrs_ror(i32 %X, i32 %Y) { +; CHECK: t2ADDrs_ror +; CHECK: add.w r0, r0, r1, ror #16 %A = lshr i32 %Y, 16 %B = shl i32 %Y, 16 %C = or i32 %B, %A @@ -32,6 +36,10 @@ define i32 @t2ADDrs_ror(i32 %X, i32 %Y) { } define i32 @t2ADDrs_noRegShift(i32 %X, i32 %Y, i8 %sh) { +; CHECK: t2ADDrs_noRegShift +; CHECK: uxtb r2, r2 +; CHECK: lsls r1, r2 +; CHECK: add r0, r1 %shift.upgrd.1 = zext i8 %sh to i32 %A = shl i32 %Y, %shift.upgrd.1 %B = add i32 %X, %A diff --git a/test/CodeGen/Thumb2/thumb2-smla.ll b/test/CodeGen/Thumb2/thumb2-smla.ll index 66cc884..092ec27 100644 --- a/test/CodeGen/Thumb2/thumb2-smla.ll +++ b/test/CodeGen/Thumb2/thumb2-smla.ll @@ -1,7 +1,8 @@ -; RUN: llc < %s -march=thumb -mattr=+thumb2 | \ -; RUN: grep smlabt | count 1 +; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s define i32 @f3(i32 %a, i16 %x, i32 %y) { +; CHECK: f3 +; CHECK: smlabt r0, r1, r2, r0 %tmp = sext i16 %x to i32 ; <i32> [#uses=1] %tmp2 = ashr i32 %y, 16 ; <i32> [#uses=1] %tmp3 = mul i32 %tmp2, %tmp ; <i32> [#uses=1] diff --git a/test/CodeGen/Thumb2/thumb2-smul.ll b/test/CodeGen/Thumb2/thumb2-smul.ll index cdbf4ca..16ea85d 100644 --- a/test/CodeGen/Thumb2/thumb2-smul.ll +++ b/test/CodeGen/Thumb2/thumb2-smul.ll @@ -1,12 +1,11 @@ -; RUN: llc < %s -march=thumb -mattr=+thumb2 | \ -; RUN: grep smulbt | count 1 -; RUN: llc < %s -march=thumb -mattr=+thumb2 | \ -; RUN: grep smultt | count 1 +; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s @x = weak global i16 0 ; <i16*> [#uses=1] @y = weak global i16 0 ; <i16*> [#uses=0] define i32 @f1(i32 %y) { +; CHECK: f1 +; CHECK: smulbt r0, r1, r0 %tmp = load i16* @x ; <i16> [#uses=1] %tmp1 = add i16 %tmp, 2 ; <i16> [#uses=1] %tmp2 = sext i16 %tmp1 to i32 ; <i32> [#uses=1] @@ -16,6 +15,8 @@ define i32 @f1(i32 %y) { } define i32 @f2(i32 %x, i32 %y) { +; CHECK: f2 +; CHECK: smultt r0, r1, r0 %tmp1 = ashr i32 %x, 16 ; <i32> [#uses=1] %tmp3 = ashr i32 %y, 16 ; <i32> [#uses=1] %tmp4 = mul i32 %tmp3, %tmp1 ; <i32> [#uses=1] diff --git a/test/CodeGen/Thumb2/thumb2-spill-q.ll b/test/CodeGen/Thumb2/thumb2-spill-q.ll index 0a7221c..aef167b 100644 --- a/test/CodeGen/Thumb2/thumb2-spill-q.ll +++ b/test/CodeGen/Thumb2/thumb2-spill-q.ll @@ -11,8 +11,9 @@ declare <4 x float> @llvm.arm.neon.vld1.v4f32(i8*) nounwind readonly define arm_apcscc void @aaa(%quuz* %this, i8* %block) { ; CHECK: aaa: -; CHECK: vstmia sp -; CHECK: vldmia sp +; CHECK: bic sp, sp, #15 +; CHECK: vst1.64 {{.*}}sp, :128 +; CHECK: vld1.64 {{.*}}sp, :128 entry: %0 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef) nounwind ; <<4 x float>> [#uses=1] store float 6.300000e+01, float* undef, align 4 diff --git a/test/CodeGen/Thumb2/thumb2-str_pre.ll b/test/CodeGen/Thumb2/thumb2-str_pre.ll index 6c804ee..9af960b 100644 --- a/test/CodeGen/Thumb2/thumb2-str_pre.ll +++ b/test/CodeGen/Thumb2/thumb2-str_pre.ll @@ -1,7 +1,8 @@ -; RUN: llc < %s -march=thumb -mattr=+thumb2 | \ -; RUN: grep {str.*\\!} | count 2 +; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s define void @test1(i32* %X, i32* %A, i32** %dest) { +; CHECK: test1 +; CHECK: str r1, [r0, #+16]! %B = load i32* %A ; <i32> [#uses=1] %Y = getelementptr i32* %X, i32 4 ; <i32*> [#uses=2] store i32 %B, i32* %Y @@ -10,6 +11,8 @@ define void @test1(i32* %X, i32* %A, i32** %dest) { } define i16* @test2(i16* %X, i32* %A) { +; CHECK: test2 +; CHECK: strh r1, [r0, #+8]! %B = load i32* %A ; <i32> [#uses=1] %Y = getelementptr i16* %X, i32 4 ; <i16*> [#uses=2] %tmp = trunc i32 %B to i16 ; <i16> [#uses=1] diff --git a/test/CodeGen/Thumb2/thumb2-sxt_rot.ll b/test/CodeGen/Thumb2/thumb2-sxt_rot.ll index 33ed543..054d5df 100644 --- a/test/CodeGen/Thumb2/thumb2-sxt_rot.ll +++ b/test/CodeGen/Thumb2/thumb2-sxt_rot.ll @@ -1,16 +1,15 @@ -; RUN: llc < %s -march=thumb -mattr=+thumb2 | \ -; RUN: grep sxtb | count 2 -; RUN: llc < %s -march=thumb -mattr=+thumb2 | \ -; RUN: grep sxtb | grep ror | count 1 -; RUN: llc < %s -march=thumb -mattr=+thumb2 | \ -; RUN: grep sxtab | count 1 +; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s define i32 @test0(i8 %A) { +; CHECK: test0 +; CHECK: sxtb r0, r0 %B = sext i8 %A to i32 ret i32 %B } define i8 @test1(i32 %A) signext { +; CHECK: test1 +; CHECK: sxtb.w r0, r0, ror #8 %B = lshr i32 %A, 8 %C = shl i32 %A, 24 %D = or i32 %B, %C @@ -19,6 +18,9 @@ define i8 @test1(i32 %A) signext { } define i32 @test2(i32 %A, i32 %X) signext { +; CHECK: test2 +; CHECK: lsrs r0, r0, #8 +; CHECK: sxtab r0, r1, r0 %B = lshr i32 %A, 8 %C = shl i32 %A, 24 %D = or i32 %B, %C diff --git a/test/CodeGen/Thumb2/thumb2-tbh.ll b/test/CodeGen/Thumb2/thumb2-tbh.ll index c5cb6f3..2cf1d6a 100644 --- a/test/CodeGen/Thumb2/thumb2-tbh.ll +++ b/test/CodeGen/Thumb2/thumb2-tbh.ll @@ -2,8 +2,6 @@ ; Thumb2 target should reorder the bb's in order to use tbb / tbh. -; XFAIL: * - %struct.R_flstr = type { i32, i32, i8* } %struct._T_tstr = type { i32, %struct.R_flstr*, %struct._T_tstr* } @_C_nextcmd = external global i32 ; <i32*> [#uses=3] @@ -18,7 +16,7 @@ declare arm_apcscc noalias i8* @calloc(i32, i32) nounwind define arm_apcscc i32 @main(i32 %argc, i8** nocapture %argv) nounwind { ; CHECK: main: -; CHECK: tbh +; CHECK: tbb entry: br label %bb42.i @@ -26,7 +24,7 @@ bb1.i2: ; preds = %bb42.i br label %bb40.i bb5.i: ; preds = %bb42.i - %0 = or i32 %_Y_flags.1, 32 ; <i32> [#uses=1] + %0 = or i32 %argc, 32 ; <i32> [#uses=1] br label %bb40.i bb7.i: ; preds = %bb42.i @@ -66,14 +64,10 @@ bb39.i: ; preds = %bb42.i unreachable bb40.i: ; preds = %bb42.i, %bb5.i, %bb1.i2 - %_Y_flags.0 = phi i32 [ 0, %bb1.i2 ], [ %0, %bb5.i ], [ %_Y_flags.1, %bb42.i ] ; <i32> [#uses=1] - %_Y_eflag.b.0 = phi i1 [ %_Y_eflag.b.1, %bb1.i2 ], [ %_Y_eflag.b.1, %bb5.i ], [ true, %bb42.i ] ; <i1> [#uses=1] br label %bb42.i bb42.i: ; preds = %bb40.i, %entry - %_Y_eflag.b.1 = phi i1 [ false, %entry ], [ %_Y_eflag.b.0, %bb40.i ] ; <i1> [#uses=2] - %_Y_flags.1 = phi i32 [ 0, %entry ], [ %_Y_flags.0, %bb40.i ] ; <i32> [#uses=2] - switch i32 undef, label %bb39.i [ + switch i32 %argc, label %bb39.i [ i32 67, label %bb33.i i32 70, label %bb35.i i32 77, label %bb37.i diff --git a/test/CodeGen/Thumb2/thumb2-teq2.ll b/test/CodeGen/Thumb2/thumb2-teq2.ll index c6867d9..0f122f2 100644 --- a/test/CodeGen/Thumb2/thumb2-teq2.ll +++ b/test/CodeGen/Thumb2/thumb2-teq2.ll @@ -1,34 +1,40 @@ -; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {teq\\.w\\W*r\[0-9\],\\W*r\[0-9\]$} | count 4 -; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {teq\\.w\\W*r\[0-9\],\\W*r\[0-9\],\\W*lsl\\W*#5$} | count 1 -; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {teq\\.w\\W*r\[0-9\],\\W*r\[0-9\],\\W*lsr\\W*#6$} | count 1 -; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {teq\\.w\\W*r\[0-9\],\\W*r\[0-9\],\\W*asr\\W*#7$} | count 1 -; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {teq\\.w\\W*r\[0-9\],\\W*r\[0-9\],\\W*ror\\W*#8$} | count 1 +; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s define i1 @f1(i32 %a, i32 %b) { +; CHECK: f1 +; CHECK: teq.w r0, r1 %tmp = xor i32 %a, %b %tmp1 = icmp ne i32 %tmp, 0 ret i1 %tmp1 } define i1 @f2(i32 %a, i32 %b) { +; CHECK: f2 +; CHECK: teq.w r0, r1 %tmp = xor i32 %a, %b %tmp1 = icmp eq i32 %tmp, 0 ret i1 %tmp1 } define i1 @f3(i32 %a, i32 %b) { +; CHECK: f3 +; CHECK: teq.w r0, r1 %tmp = xor i32 %a, %b %tmp1 = icmp ne i32 0, %tmp ret i1 %tmp1 } define i1 @f4(i32 %a, i32 %b) { +; CHECK: f4 +; CHECK: teq.w r0, r1 %tmp = xor i32 %a, %b %tmp1 = icmp eq i32 0, %tmp ret i1 %tmp1 } define i1 @f6(i32 %a, i32 %b) { +; CHECK: f6 +; CHECK: teq.w r0, r1, lsl #5 %tmp = shl i32 %b, 5 %tmp1 = xor i32 %a, %tmp %tmp2 = icmp eq i32 %tmp1, 0 @@ -36,6 +42,8 @@ define i1 @f6(i32 %a, i32 %b) { } define i1 @f7(i32 %a, i32 %b) { +; CHECK: f7 +; CHECK: teq.w r0, r1, lsr #6 %tmp = lshr i32 %b, 6 %tmp1 = xor i32 %a, %tmp %tmp2 = icmp eq i32 %tmp1, 0 @@ -43,6 +51,8 @@ define i1 @f7(i32 %a, i32 %b) { } define i1 @f8(i32 %a, i32 %b) { +; CHECK: f8 +; CHECK: teq.w r0, r1, asr #7 %tmp = ashr i32 %b, 7 %tmp1 = xor i32 %a, %tmp %tmp2 = icmp eq i32 %tmp1, 0 @@ -50,6 +60,8 @@ define i1 @f8(i32 %a, i32 %b) { } define i1 @f9(i32 %a, i32 %b) { +; CHECK: f9 +; CHECK: teq.w r0, r0, ror #8 %l8 = shl i32 %a, 24 %r8 = lshr i32 %a, 8 %tmp = or i32 %l8, %r8 diff --git a/test/CodeGen/Thumb2/thumb2-uxt_rot.ll b/test/CodeGen/Thumb2/thumb2-uxt_rot.ll index 37919dd..75e1d70 100644 --- a/test/CodeGen/Thumb2/thumb2-uxt_rot.ll +++ b/test/CodeGen/Thumb2/thumb2-uxt_rot.ll @@ -1,13 +1,15 @@ -; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep uxtb | count 1 -; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep uxtab | count 1 -; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep uxth | count 1 +; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s define i8 @test1(i32 %A.u) zeroext { +; CHECK: test1 +; CHECK: uxtb r0, r0 %B.u = trunc i32 %A.u to i8 ret i8 %B.u } define i32 @test2(i32 %A.u, i32 %B.u) zeroext { +; CHECK: test2 +; CHECK: uxtab r0, r0, r1 %C.u = trunc i32 %B.u to i8 %D.u = zext i8 %C.u to i32 %E.u = add i32 %A.u, %D.u @@ -15,6 +17,8 @@ define i32 @test2(i32 %A.u, i32 %B.u) zeroext { } define i32 @test3(i32 %A.u) zeroext { +; CHECK: test3 +; CHECK: uxth.w r0, r0, ror #8 %B.u = lshr i32 %A.u, 8 %C.u = shl i32 %A.u, 24 %D.u = or i32 %B.u, %C.u diff --git a/test/CodeGen/Thumb2/thumb2-uxtb.ll b/test/CodeGen/Thumb2/thumb2-uxtb.ll index 4022d95..4e23f53 100644 --- a/test/CodeGen/Thumb2/thumb2-uxtb.ll +++ b/test/CodeGen/Thumb2/thumb2-uxtb.ll @@ -1,36 +1,47 @@ -; RUN: llc < %s -march=thumb -mattr=+thumb2 | \ -; RUN: grep uxt | count 10 +; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s define i32 @test1(i32 %x) { +; CHECK: test1 +; CHECK: uxtb16.w r0, r0 %tmp1 = and i32 %x, 16711935 ; <i32> [#uses=1] ret i32 %tmp1 } define i32 @test2(i32 %x) { +; CHECK: test2 +; CHECK: uxtb16.w r0, r0, ror #8 %tmp1 = lshr i32 %x, 8 ; <i32> [#uses=1] %tmp2 = and i32 %tmp1, 16711935 ; <i32> [#uses=1] ret i32 %tmp2 } define i32 @test3(i32 %x) { +; CHECK: test3 +; CHECK: uxtb16.w r0, r0, ror #8 %tmp1 = lshr i32 %x, 8 ; <i32> [#uses=1] %tmp2 = and i32 %tmp1, 16711935 ; <i32> [#uses=1] ret i32 %tmp2 } define i32 @test4(i32 %x) { +; CHECK: test4 +; CHECK: uxtb16.w r0, r0, ror #8 %tmp1 = lshr i32 %x, 8 ; <i32> [#uses=1] %tmp6 = and i32 %tmp1, 16711935 ; <i32> [#uses=1] ret i32 %tmp6 } define i32 @test5(i32 %x) { +; CHECK: test5 +; CHECK: uxtb16.w r0, r0, ror #8 %tmp1 = lshr i32 %x, 8 ; <i32> [#uses=1] %tmp2 = and i32 %tmp1, 16711935 ; <i32> [#uses=1] ret i32 %tmp2 } define i32 @test6(i32 %x) { +; CHECK: test6 +; CHECK: uxtb16.w r0, r0, ror #16 %tmp1 = lshr i32 %x, 16 ; <i32> [#uses=1] %tmp2 = and i32 %tmp1, 255 ; <i32> [#uses=1] %tmp4 = shl i32 %x, 16 ; <i32> [#uses=1] @@ -40,6 +51,8 @@ define i32 @test6(i32 %x) { } define i32 @test7(i32 %x) { +; CHECK: test7 +; CHECK: uxtb16.w r0, r0, ror #16 %tmp1 = lshr i32 %x, 16 ; <i32> [#uses=1] %tmp2 = and i32 %tmp1, 255 ; <i32> [#uses=1] %tmp4 = shl i32 %x, 16 ; <i32> [#uses=1] @@ -49,6 +62,8 @@ define i32 @test7(i32 %x) { } define i32 @test8(i32 %x) { +; CHECK: test8 +; CHECK: uxtb16.w r0, r0, ror #24 %tmp1 = shl i32 %x, 8 ; <i32> [#uses=1] %tmp2 = and i32 %tmp1, 16711680 ; <i32> [#uses=1] %tmp5 = lshr i32 %x, 24 ; <i32> [#uses=1] @@ -57,6 +72,8 @@ define i32 @test8(i32 %x) { } define i32 @test9(i32 %x) { +; CHECK: test9 +; CHECK: uxtb16.w r0, r0, ror #24 %tmp1 = lshr i32 %x, 24 ; <i32> [#uses=1] %tmp4 = shl i32 %x, 8 ; <i32> [#uses=1] %tmp5 = and i32 %tmp4, 16711680 ; <i32> [#uses=1] @@ -65,6 +82,13 @@ define i32 @test9(i32 %x) { } define i32 @test10(i32 %p0) { +; CHECK: test10 +; CHECK: mov.w r1, #16253176 +; CHECK: and.w r0, r1, r0, lsr #7 +; CHECK: lsrs r1, r0, #5 +; CHECK: uxtb16.w r1, r1 +; CHECK: orr.w r0, r1, r0 + %tmp1 = lshr i32 %p0, 7 ; <i32> [#uses=1] %tmp2 = and i32 %tmp1, 16253176 ; <i32> [#uses=2] %tmp4 = lshr i32 %tmp2, 5 ; <i32> [#uses=1] |
