diff options
Diffstat (limited to 'test/CodeGen/PowerPC')
20 files changed, 252 insertions, 251 deletions
diff --git a/test/CodeGen/PowerPC/2007-01-15-AsmDialect.ll b/test/CodeGen/PowerPC/2007-01-15-AsmDialect.ll index 7b00ac6..c779288 100644 --- a/test/CodeGen/PowerPC/2007-01-15-AsmDialect.ll +++ b/test/CodeGen/PowerPC/2007-01-15-AsmDialect.ll @@ -7,7 +7,6 @@ entry: %temp = alloca i32, align 4 ; <i32*> [#uses=2] %ctz_x = alloca i32, align 4 ; <i32*> [#uses=3] %ctz_c = alloca i32, align 4 ; <i32*> [#uses=2] - "alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] store i32 61440, i32* %ctz_x %tmp = load i32* %ctz_x ; <i32> [#uses=1] %tmp1 = sub i32 0, %tmp ; <i32> [#uses=1] diff --git a/test/CodeGen/PowerPC/2007-05-22-tailmerge-3.ll b/test/CodeGen/PowerPC/2007-05-22-tailmerge-3.ll index 42f2152..c141551 100644 --- a/test/CodeGen/PowerPC/2007-05-22-tailmerge-3.ll +++ b/test/CodeGen/PowerPC/2007-05-22-tailmerge-3.ll @@ -13,7 +13,6 @@ entry: %i_addr = alloca i32 ; <i32*> [#uses=2] %q_addr = alloca i32 ; <i32*> [#uses=2] %retval = alloca i32, align 4 ; <i32*> [#uses=1] - "alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] store i32 %i, i32* %i_addr store i32 %q, i32* %q_addr %tmp = load i32* %i_addr ; <i32> [#uses=1] diff --git a/test/CodeGen/PowerPC/2007-05-30-dagcombine-miscomp.ll b/test/CodeGen/PowerPC/2007-05-30-dagcombine-miscomp.ll index 2938c70..72e93a9 100644 --- a/test/CodeGen/PowerPC/2007-05-30-dagcombine-miscomp.ll +++ b/test/CodeGen/PowerPC/2007-05-30-dagcombine-miscomp.ll @@ -4,7 +4,7 @@ target triple = "powerpc-apple-darwin8.8.0" ; RUN: llc < %s -march=ppc32 | grep {rlwinm r3, r3, 23, 30, 30} ; PR1473 -define i8 @foo(i16 zeroext %a) zeroext { +define zeroext i8 @foo(i16 zeroext %a) { %tmp2 = lshr i16 %a, 10 ; <i16> [#uses=1] %tmp23 = trunc i16 %tmp2 to i8 ; <i8> [#uses=1] %tmp4 = shl i8 %tmp23, 1 ; <i8> [#uses=1] diff --git a/test/CodeGen/PowerPC/2008-03-24-CoalescerBug.ll b/test/CodeGen/PowerPC/2008-03-24-CoalescerBug.ll index 8776d9a..01c83cb 100644 --- a/test/CodeGen/PowerPC/2008-03-24-CoalescerBug.ll +++ b/test/CodeGen/PowerPC/2008-03-24-CoalescerBug.ll @@ -18,7 +18,7 @@ define void @"-[PFTPersistentSymbols saveSymbolWithName:address:path:lineNumber: entry: br i1 false, label %bb12, label %bb21 bb12: ; preds = %entry - %tmp17 = tail call i8 inttoptr (i64 4294901504 to i8 (%struct..0objc_object*, %struct.objc_selector*, %struct.NSArray*)*)( %struct..0objc_object* null, %struct.objc_selector* null, %struct.NSArray* bitcast (%struct.__builtin_CFString* @0 to %struct.NSArray*) ) signext nounwind ; <i8> [#uses=0] + %tmp17 = tail call signext i8 inttoptr (i64 4294901504 to i8 (%struct..0objc_object*, %struct.objc_selector*, %struct.NSArray*)*)( %struct..0objc_object* null, %struct.objc_selector* null, %struct.NSArray* bitcast (%struct.__builtin_CFString* @0 to %struct.NSArray*) ) nounwind ; <i8> [#uses=0] br i1 false, label %bb25, label %bb21 bb21: ; preds = %bb12, %entry %tmp24 = or i64 %flags, 4 ; <i64> [#uses=1] diff --git a/test/CodeGen/PowerPC/2008-07-15-SignExtendInreg.ll b/test/CodeGen/PowerPC/2008-07-15-SignExtendInreg.ll index 5cd8c34..21b0c61 100644 --- a/test/CodeGen/PowerPC/2008-07-15-SignExtendInreg.ll +++ b/test/CodeGen/PowerPC/2008-07-15-SignExtendInreg.ll @@ -2,7 +2,7 @@ target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128" target triple = "powerpc-apple-darwin9" -define i16 @t(i16* %dct) signext nounwind { +define signext i16 @t(i16* %dct) nounwind { entry: load i16* null, align 2 ; <i16>:0 [#uses=2] lshr i16 %0, 11 ; <i16>:1 [#uses=0] diff --git a/test/CodeGen/PowerPC/2008-10-30-IllegalShift.ll b/test/CodeGen/PowerPC/2008-10-30-IllegalShift.ll deleted file mode 100644 index 83f3f6f..0000000 --- a/test/CodeGen/PowerPC/2008-10-30-IllegalShift.ll +++ /dev/null @@ -1,14 +0,0 @@ -; RUN: llc < %s -march=ppc32 -; PR2986 -@argc = external global i32 ; <i32*> [#uses=1] -@buffer = external global [32 x i8], align 4 ; <[32 x i8]*> [#uses=1] - -define void @test1() nounwind noinline { -entry: - %0 = load i32* @argc, align 4 ; <i32> [#uses=1] - %1 = trunc i32 %0 to i8 ; <i8> [#uses=1] - tail call void @llvm.memset.i32(i8* getelementptr ([32 x i8]* @buffer, i32 0, i32 0), i8 %1, i32 17, i32 4) - unreachable -} - -declare void @llvm.memset.i32(i8*, i8, i32, i32) nounwind diff --git a/test/CodeGen/PowerPC/2009-11-15-ReMatBug.ll b/test/CodeGen/PowerPC/2009-11-15-ReMatBug.ll deleted file mode 100644 index 54f4b2e..0000000 --- a/test/CodeGen/PowerPC/2009-11-15-ReMatBug.ll +++ /dev/null @@ -1,155 +0,0 @@ -; RUN: llc < %s -mtriple=powerpc-apple-darwin8 - -%struct.FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.__sbuf, %struct.__sFILEX*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 } -%struct.__gcov_var = type { %struct.FILE*, i32, i32, i32, i32, i32, i32, [1025 x i32] } -%struct.__sFILEX = type opaque -%struct.__sbuf = type { i8*, i32 } -%struct.gcov_ctr_info = type { i32, i64*, void (i64*, i32)* } -%struct.gcov_ctr_summary = type { i32, i32, i64, i64, i64 } -%struct.gcov_fn_info = type { i32, i32, [0 x i32] } -%struct.gcov_info = type { i32, %struct.gcov_info*, i32, i8*, i32, %struct.gcov_fn_info*, i32, [0 x %struct.gcov_ctr_info] } -%struct.gcov_summary = type { i32, [1 x %struct.gcov_ctr_summary] } - -@__gcov_var = external global %struct.__gcov_var ; <%struct.__gcov_var*> [#uses=1] -@__sF = external global [0 x %struct.FILE] ; <[0 x %struct.FILE]*> [#uses=1] -@.str = external constant [56 x i8], align 4 ; <[56 x i8]*> [#uses=1] -@gcov_list = external global %struct.gcov_info* ; <%struct.gcov_info**> [#uses=1] -@.str7 = external constant [35 x i8], align 4 ; <[35 x i8]*> [#uses=1] -@.str8 = external constant [9 x i8], align 4 ; <[9 x i8]*> [#uses=1] -@.str9 = external constant [10 x i8], align 4 ; <[10 x i8]*> [#uses=1] -@.str10 = external constant [36 x i8], align 4 ; <[36 x i8]*> [#uses=1] - -declare i32 @"\01_fprintf$LDBL128"(%struct.FILE*, i8*, ...) nounwind - -define void @gcov_exit() nounwind { -entry: - %gi_ptr.0357 = load %struct.gcov_info** @gcov_list, align 4 ; <%struct.gcov_info*> [#uses=1] - %0 = alloca i8, i32 undef, align 1 ; <i8*> [#uses=3] - br i1 undef, label %return, label %bb.nph341 - -bb.nph341: ; preds = %entry - %object27 = bitcast %struct.gcov_summary* undef to i8* ; <i8*> [#uses=1] - br label %bb25 - -bb25: ; preds = %read_fatal, %bb.nph341 - %gi_ptr.1329 = phi %struct.gcov_info* [ %gi_ptr.0357, %bb.nph341 ], [ undef, %read_fatal ] ; <%struct.gcov_info*> [#uses=1] - call void @llvm.memset.i32(i8* %object27, i8 0, i32 36, i32 8) - br i1 undef, label %bb49.1, label %bb48 - -bb48: ; preds = %bb25 - br label %bb49.1 - -bb51: ; preds = %bb48.4, %bb49.3 - switch i32 undef, label %bb58 [ - i32 0, label %rewrite - i32 1734567009, label %bb59 - ] - -bb58: ; preds = %bb51 - %1 = call i32 (%struct.FILE*, i8*, ...)* @"\01_fprintf$LDBL128"(%struct.FILE* getelementptr inbounds ([0 x %struct.FILE]* @__sF, i32 0, i32 2), i8* getelementptr inbounds ([35 x i8]* @.str7, i32 0, i32 0), i8* %0) nounwind ; <i32> [#uses=0] - br label %read_fatal - -bb59: ; preds = %bb51 - br i1 undef, label %bb60, label %bb3.i156 - -bb3.i156: ; preds = %bb59 - store i8 52, i8* undef, align 1 - store i8 42, i8* undef, align 1 - %2 = call i32 (%struct.FILE*, i8*, ...)* @"\01_fprintf$LDBL128"(%struct.FILE* getelementptr inbounds ([0 x %struct.FILE]* @__sF, i32 0, i32 2), i8* getelementptr inbounds ([56 x i8]* @.str, i32 0, i32 0), i8* %0, i8* undef, i8* undef) nounwind ; <i32> [#uses=0] - br label %read_fatal - -bb60: ; preds = %bb59 - br i1 undef, label %bb78.preheader, label %rewrite - -bb78.preheader: ; preds = %bb60 - br i1 undef, label %bb62, label %bb80 - -bb62: ; preds = %bb78.preheader - br i1 undef, label %bb64, label %read_mismatch - -bb64: ; preds = %bb62 - br i1 undef, label %bb65, label %read_mismatch - -bb65: ; preds = %bb64 - br i1 undef, label %bb75, label %read_mismatch - -read_mismatch: ; preds = %bb98, %bb119.preheader, %bb72, %bb71, %bb65, %bb64, %bb62 - %3 = icmp eq i32 undef, -1 ; <i1> [#uses=1] - %iftmp.11.0 = select i1 %3, i8* getelementptr inbounds ([10 x i8]* @.str9, i32 0, i32 0), i8* getelementptr inbounds ([9 x i8]* @.str8, i32 0, i32 0) ; <i8*> [#uses=1] - %4 = call i32 (%struct.FILE*, i8*, ...)* @"\01_fprintf$LDBL128"(%struct.FILE* getelementptr inbounds ([0 x %struct.FILE]* @__sF, i32 0, i32 2), i8* getelementptr inbounds ([36 x i8]* @.str10, i32 0, i32 0), i8* %0, i8* %iftmp.11.0) nounwind ; <i32> [#uses=0] - br label %read_fatal - -bb71: ; preds = %bb75 - %5 = load i32* undef, align 4 ; <i32> [#uses=1] - %6 = getelementptr inbounds %struct.gcov_info* %gi_ptr.1329, i32 0, i32 7, i32 undef, i32 2 ; <void (i64*, i32)**> [#uses=1] - %7 = load void (i64*, i32)** %6, align 4 ; <void (i64*, i32)*> [#uses=1] - %8 = call i32 @__gcov_read_unsigned() nounwind ; <i32> [#uses=1] - %9 = call i32 @__gcov_read_unsigned() nounwind ; <i32> [#uses=1] - %10 = icmp eq i32 %tmp386, %8 ; <i1> [#uses=1] - br i1 %10, label %bb72, label %read_mismatch - -bb72: ; preds = %bb71 - %11 = icmp eq i32 undef, %9 ; <i1> [#uses=1] - br i1 %11, label %bb73, label %read_mismatch - -bb73: ; preds = %bb72 - call void %7(i64* null, i32 %5) nounwind - unreachable - -bb74: ; preds = %bb75 - %12 = add i32 %13, 1 ; <i32> [#uses=1] - br label %bb75 - -bb75: ; preds = %bb74, %bb65 - %13 = phi i32 [ %12, %bb74 ], [ 0, %bb65 ] ; <i32> [#uses=2] - %tmp386 = add i32 0, 27328512 ; <i32> [#uses=1] - %14 = shl i32 1, %13 ; <i32> [#uses=1] - %15 = load i32* undef, align 4 ; <i32> [#uses=1] - %16 = and i32 %15, %14 ; <i32> [#uses=1] - %17 = icmp eq i32 %16, 0 ; <i1> [#uses=1] - br i1 %17, label %bb74, label %bb71 - -bb80: ; preds = %bb78.preheader - unreachable - -read_fatal: ; preds = %read_mismatch, %bb3.i156, %bb58 - br i1 undef, label %return, label %bb25 - -rewrite: ; preds = %bb60, %bb51 - store i32 -1, i32* getelementptr inbounds (%struct.__gcov_var* @__gcov_var, i32 0, i32 6), align 4 - br i1 undef, label %bb94, label %bb119.preheader - -bb94: ; preds = %rewrite - unreachable - -bb119.preheader: ; preds = %rewrite - br i1 undef, label %read_mismatch, label %bb98 - -bb98: ; preds = %bb119.preheader - br label %read_mismatch - -return: ; preds = %read_fatal, %entry - ret void - -bb49.1: ; preds = %bb48, %bb25 - br i1 undef, label %bb49.2, label %bb48.2 - -bb49.2: ; preds = %bb48.2, %bb49.1 - br i1 undef, label %bb49.3, label %bb48.3 - -bb48.2: ; preds = %bb49.1 - br label %bb49.2 - -bb49.3: ; preds = %bb48.3, %bb49.2 - br i1 undef, label %bb51, label %bb48.4 - -bb48.3: ; preds = %bb49.2 - br label %bb49.3 - -bb48.4: ; preds = %bb49.3 - br label %bb51 -} - -declare i32 @__gcov_read_unsigned() nounwind - -declare void @llvm.memset.i32(i8* nocapture, i8, i32, i32) nounwind diff --git a/test/CodeGen/PowerPC/and-elim.ll b/test/CodeGen/PowerPC/and-elim.ll index 3685361..a1ec29b 100644 --- a/test/CodeGen/PowerPC/and-elim.ll +++ b/test/CodeGen/PowerPC/and-elim.ll @@ -9,7 +9,7 @@ define void @test(i8* %P) { ret void } -define i16 @test2(i16 zeroext %crc) zeroext { +define zeroext i16 @test2(i16 zeroext %crc) { ; No and's should be needed for the i16s here. %tmp.1 = lshr i16 %crc, 1 %tmp.7 = xor i16 %tmp.1, 40961 diff --git a/test/CodeGen/PowerPC/and_sext.ll b/test/CodeGen/PowerPC/and_sext.ll index c6d234e..df48ccf 100644 --- a/test/CodeGen/PowerPC/and_sext.ll +++ b/test/CodeGen/PowerPC/and_sext.ll @@ -9,7 +9,7 @@ define i32 @test1(i32 %mode.0.i.0) { ret i32 %tmp.81 } -define i16 @test2(i16 signext %X, i16 signext %x) signext { +define signext i16 @test2(i16 signext %X, i16 signext %x) { %tmp = sext i16 %X to i32 %tmp1 = sext i16 %x to i32 %tmp2 = add i32 %tmp, %tmp1 @@ -20,7 +20,7 @@ define i16 @test2(i16 signext %X, i16 signext %x) signext { ret i16 %retval } -define i16 @test3(i32 zeroext %X) signext { +define signext i16 @test3(i32 zeroext %X) { %tmp1 = lshr i32 %X, 16 %tmp2 = trunc i32 %tmp1 to i16 ret i16 %tmp2 diff --git a/test/CodeGen/PowerPC/atomic-1.ll b/test/CodeGen/PowerPC/atomic-1.ll index ec4e42d..a2cf170 100644 --- a/test/CodeGen/PowerPC/atomic-1.ll +++ b/test/CodeGen/PowerPC/atomic-1.ll @@ -1,21 +1,23 @@ ; RUN: llc < %s -march=ppc32 | grep lwarx | count 3 ; RUN: llc < %s -march=ppc32 | grep stwcx. | count 4 -define i32 @exchange_and_add(i32* %mem, i32 %val) nounwind { - %tmp = call i32 @llvm.atomic.load.add.i32( i32* %mem, i32 %val ) - ret i32 %tmp +define i32 @exchange_and_add(i32* %mem, i32 %val) nounwind { + %tmp = call i32 @llvm.atomic.load.add.i32.p0i32(i32* %mem, i32 %val) + ret i32 %tmp } -define i32 @exchange_and_cmp(i32* %mem) nounwind { - %tmp = call i32 @llvm.atomic.cmp.swap.i32( i32* %mem, i32 0, i32 1 ) - ret i32 %tmp +define i32 @exchange_and_cmp(i32* %mem) nounwind { + %tmp = call i32 @llvm.atomic.cmp.swap.i32.p0i32(i32* %mem, i32 0, i32 1) + ret i32 %tmp } -define i32 @exchange(i32* %mem, i32 %val) nounwind { - %tmp = call i32 @llvm.atomic.swap.i32( i32* %mem, i32 1 ) - ret i32 %tmp +define i32 @exchange(i32* %mem, i32 %val) nounwind { + %tmp = call i32 @llvm.atomic.swap.i32.p0i32(i32* %mem, i32 1) + ret i32 %tmp } -declare i32 @llvm.atomic.load.add.i32(i32*, i32) nounwind -declare i32 @llvm.atomic.cmp.swap.i32(i32*, i32, i32) nounwind -declare i32 @llvm.atomic.swap.i32(i32*, i32) nounwind +declare i32 @llvm.atomic.load.add.i32.p0i32(i32* nocapture, i32) nounwind + +declare i32 @llvm.atomic.cmp.swap.i32.p0i32(i32* nocapture, i32, i32) nounwind + +declare i32 @llvm.atomic.swap.i32.p0i32(i32* nocapture, i32) nounwind diff --git a/test/CodeGen/PowerPC/atomic-2.ll b/test/CodeGen/PowerPC/atomic-2.ll index 6d9daef9..0fa2a29 100644 --- a/test/CodeGen/PowerPC/atomic-2.ll +++ b/test/CodeGen/PowerPC/atomic-2.ll @@ -1,21 +1,23 @@ ; RUN: llc < %s -march=ppc64 | grep ldarx | count 3 ; RUN: llc < %s -march=ppc64 | grep stdcx. | count 4 -define i64 @exchange_and_add(i64* %mem, i64 %val) nounwind { - %tmp = call i64 @llvm.atomic.load.add.i64( i64* %mem, i64 %val ) - ret i64 %tmp +define i64 @exchange_and_add(i64* %mem, i64 %val) nounwind { + %tmp = call i64 @llvm.atomic.load.add.i64.p0i64(i64* %mem, i64 %val) + ret i64 %tmp } -define i64 @exchange_and_cmp(i64* %mem) nounwind { - %tmp = call i64 @llvm.atomic.cmp.swap.i64( i64* %mem, i64 0, i64 1 ) - ret i64 %tmp +define i64 @exchange_and_cmp(i64* %mem) nounwind { + %tmp = call i64 @llvm.atomic.cmp.swap.i64.p0i64(i64* %mem, i64 0, i64 1) + ret i64 %tmp } -define i64 @exchange(i64* %mem, i64 %val) nounwind { - %tmp = call i64 @llvm.atomic.swap.i64( i64* %mem, i64 1 ) - ret i64 %tmp +define i64 @exchange(i64* %mem, i64 %val) nounwind { + %tmp = call i64 @llvm.atomic.swap.i64.p0i64(i64* %mem, i64 1) + ret i64 %tmp } -declare i64 @llvm.atomic.load.add.i64(i64*, i64) nounwind -declare i64 @llvm.atomic.cmp.swap.i64(i64*, i64, i64) nounwind -declare i64 @llvm.atomic.swap.i64(i64*, i64) nounwind +declare i64 @llvm.atomic.load.add.i64.p0i64(i64* nocapture, i64) nounwind + +declare i64 @llvm.atomic.cmp.swap.i64.p0i64(i64* nocapture, i64, i64) nounwind + +declare i64 @llvm.atomic.swap.i64.p0i64(i64* nocapture, i64) nounwind diff --git a/test/CodeGen/PowerPC/calls.ll b/test/CodeGen/PowerPC/calls.ll index 0db184f..29bcb20 100644 --- a/test/CodeGen/PowerPC/calls.ll +++ b/test/CodeGen/PowerPC/calls.ll @@ -1,7 +1,7 @@ ; Test various forms of calls. ; RUN: llc < %s -march=ppc32 | \ -; RUN: grep {bl } | count 2 +; RUN: grep {bl } | count 1 ; RUN: llc < %s -march=ppc32 | \ ; RUN: grep {bctrl} | count 1 ; RUN: llc < %s -march=ppc32 | \ @@ -14,11 +14,6 @@ define void @test_direct() { ret void } -define void @test_extsym(i8* %P) { - free i8* %P - ret void -} - define void @test_indirect(void ()* %fp) { call void %fp( ) ret void diff --git a/test/CodeGen/PowerPC/invalid-memcpy.ll b/test/CodeGen/PowerPC/invalid-memcpy.ll deleted file mode 100644 index 3b1f306..0000000 --- a/test/CodeGen/PowerPC/invalid-memcpy.ll +++ /dev/null @@ -1,20 +0,0 @@ -; RUN: llc < %s -march=ppc32 -; RUN: llc < %s -march=ppc64 - -; This testcase is invalid (the alignment specified for memcpy is -; greater than the alignment guaranteed for Qux or C.0.1173, but it -; should compile, not crash the code generator. - -@C.0.1173 = external constant [33 x i8] ; <[33 x i8]*> [#uses=1] - -define void @Bork() { -entry: - %Qux = alloca [33 x i8] ; <[33 x i8]*> [#uses=1] - %Qux1 = bitcast [33 x i8]* %Qux to i8* ; <i8*> [#uses=1] - call void @llvm.memcpy.i64( i8* %Qux1, i8* getelementptr ([33 x i8]* @C.0.1173, i32 0, i32 0), i64 33, i32 8 ) - ret void -} - -declare void @llvm.memcpy.i64(i8*, i8*, i64, i32) - - diff --git a/test/CodeGen/PowerPC/mul-with-overflow.ll b/test/CodeGen/PowerPC/mul-with-overflow.ll index f03e3cb..76d06df 100644 --- a/test/CodeGen/PowerPC/mul-with-overflow.ll +++ b/test/CodeGen/PowerPC/mul-with-overflow.ll @@ -1,14 +1,14 @@ ; RUN: llc < %s -march=ppc32 declare {i32, i1} @llvm.umul.with.overflow.i32(i32 %a, i32 %b) -define i1 @a(i32 %x) zeroext nounwind { +define zeroext i1 @a(i32 %x) nounwind { %res = call {i32, i1} @llvm.umul.with.overflow.i32(i32 %x, i32 3) %obil = extractvalue {i32, i1} %res, 1 ret i1 %obil } declare {i32, i1} @llvm.smul.with.overflow.i32(i32 %a, i32 %b) -define i1 @b(i32 %x) zeroext nounwind { +define zeroext i1 @b(i32 %x) nounwind { %res = call {i32, i1} @llvm.smul.with.overflow.i32(i32 %x, i32 3) %obil = extractvalue {i32, i1} %res, 1 ret i1 %obil diff --git a/test/CodeGen/PowerPC/multiple-return-values.ll b/test/CodeGen/PowerPC/multiple-return-values.ll deleted file mode 100644 index b9317f9..0000000 --- a/test/CodeGen/PowerPC/multiple-return-values.ll +++ /dev/null @@ -1,17 +0,0 @@ -; RUN: llc < %s -march=ppc32 -; RUN: llc < %s -march=ppc64 - -define {i64, float} @bar(i64 %a, float %b) { - %y = add i64 %a, 7 - %z = fadd float %b, 7.0 - ret i64 %y, float %z -} - -define i64 @foo() { - %M = call {i64, float} @bar(i64 21, float 21.0) - %N = getresult {i64, float} %M, 0 - %O = getresult {i64, float} %M, 1 - %P = fptosi float %O to i64 - %Q = add i64 %P, %N - ret i64 %Q -} diff --git a/test/CodeGen/PowerPC/ppc32-vaarg.ll b/test/CodeGen/PowerPC/ppc32-vaarg.ll new file mode 100644 index 0000000..6042991 --- /dev/null +++ b/test/CodeGen/PowerPC/ppc32-vaarg.ll @@ -0,0 +1,167 @@ +; RUN: llc -O0 < %s | FileCheck %s +;ModuleID = 'test.c' +target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32" +target triple = "powerpc-unknown-freebsd9.0" + +%struct.__va_list_tag = type { i8, i8, i16, i8*, i8* } + +@var1 = common global i64 0, align 8 +@var2 = common global double 0.0, align 8 +@var3 = common global i32 0, align 4 + +define void @ppcvaargtest(%struct.__va_list_tag* %ap) nounwind { + entry: + %x = va_arg %struct.__va_list_tag* %ap, i64; Get from r5,r6 +; CHECK: lbz 4, 0(3) +; CHECK-NEXT: lwz 5, 4(3) +; CHECK-NEXT: rlwinm 6, 4, 0, 31, 31 +; CHECK-NEXT: cmplwi 0, 6, 0 +; CHECK-NEXT: addi 6, 4, 1 +; CHECK-NEXT: stw 3, -4(1) +; CHECK-NEXT: stw 6, -8(1) +; CHECK-NEXT: stw 4, -12(1) +; CHECK-NEXT: stw 5, -16(1) +; CHECK-NEXT: bne 0, .LBB0_2 +; CHECK-NEXT: # BB#1: # %entry +; CHECK-NEXT: lwz 3, -12(1) +; CHECK-NEXT: stw 3, -8(1) +; CHECK-NEXT: .LBB0_2: # %entry +; CHECK-NEXT: lwz 3, -8(1) +; CHECK-NEXT: lwz 4, -4(1) +; CHECK-NEXT: lwz 5, 8(4) +; CHECK-NEXT: slwi 6, 3, 2 +; CHECK-NEXT: addi 7, 3, 2 +; CHECK-NEXT: cmpwi 0, 3, 8 +; CHECK-NEXT: lwz 3, -16(1) +; CHECK-NEXT: addi 8, 3, 4 +; CHECK-NEXT: add 5, 5, 6 +; CHECK-NEXT: mfcr 0 # cr0 +; CHECK-NEXT: stw 0, -20(1) +; CHECK-NEXT: stw 5, -24(1) +; CHECK-NEXT: stw 3, -28(1) +; CHECK-NEXT: stw 7, -32(1) +; CHECK-NEXT: stw 8, -36(1) +; CHECK-NEXT: blt 0, .LBB0_4 +; CHECK-NEXT: # BB#3: # %entry +; CHECK-NEXT: lwz 3, -36(1) +; CHECK-NEXT: stw 3, -28(1) +; CHECK-NEXT: .LBB0_4: # %entry +; CHECK-NEXT: lwz 3, -28(1) +; CHECK-NEXT: lwz 4, -32(1) +; CHECK-NEXT: lwz 5, -4(1) +; CHECK-NEXT: stb 4, 0(5) +; CHECK-NEXT: lwz 4, -24(1) +; CHECK-NEXT: lwz 0, -20(1) +; CHECK-NEXT: mtcrf 128, 0 +; CHECK-NEXT: stw 3, -40(1) +; CHECK-NEXT: stw 4, -44(1) +; CHECK-NEXT: blt 0, .LBB0_6 +; CHECK-NEXT: # BB#5: # %entry +; CHECK-NEXT: lwz 3, -16(1) +; CHECK-NEXT: stw 3, -44(1) +; CHECK-NEXT: .LBB0_6: # %entry +; CHECK-NEXT: lwz 3, -44(1) +; CHECK-NEXT: lwz 4, -40(1) +; CHECK-NEXT: lwz 5, -4(1) +; CHECK-NEXT: stw 4, 4(5) + store i64 %x, i64* @var1, align 8 +; CHECK-NEXT: lis 4, var1@ha +; CHECK-NEXT: lwz 6, 4(3) +; CHECK-NEXT: lwz 3, 0(3) +; CHECK-NEXT: la 7, var1@l(4) +; CHECK-NEXT: stw 3, var1@l(4) +; CHECK-NEXT: stw 6, 4(7) + %y = va_arg %struct.__va_list_tag* %ap, double; From f1 +; CHECK-NEXT: lbz 3, 1(5) +; CHECK-NEXT: lwz 4, 4(5) +; CHECK-NEXT: lwz 6, 8(5) +; CHECK-NEXT: slwi 7, 3, 3 +; CHECK-NEXT: add 6, 6, 7 +; CHECK-NEXT: addi 7, 3, 1 +; CHECK-NEXT: cmpwi 0, 3, 8 +; CHECK-NEXT: addi 3, 4, 8 +; CHECK-NEXT: addi 6, 6, 32 +; CHECK-NEXT: mr 8, 4 +; CHECK-NEXT: mfcr 0 # cr0 +; CHECK-NEXT: stw 0, -48(1) +; CHECK-NEXT: stw 4, -52(1) +; CHECK-NEXT: stw 6, -56(1) +; CHECK-NEXT: stw 7, -60(1) +; CHECK-NEXT: stw 3, -64(1) +; CHECK-NEXT: stw 8, -68(1) +; CHECK-NEXT: blt 0, .LBB0_8 +; CHECK-NEXT: # BB#7: # %entry +; CHECK-NEXT: lwz 3, -64(1) +; CHECK-NEXT: stw 3, -68(1) +; CHECK-NEXT: .LBB0_8: # %entry +; CHECK-NEXT: lwz 3, -68(1) +; CHECK-NEXT: lwz 4, -60(1) +; CHECK-NEXT: lwz 5, -4(1) +; CHECK-NEXT: stb 4, 1(5) +; CHECK-NEXT: lwz 4, -56(1) +; CHECK-NEXT: lwz 0, -48(1) +; CHECK-NEXT: mtcrf 128, 0 +; CHECK-NEXT: stw 4, -72(1) +; CHECK-NEXT: stw 3, -76(1) +; CHECK-NEXT: blt 0, .LBB0_10 +; CHECK-NEXT: # BB#9: # %entry +; CHECK-NEXT: lwz 3, -52(1) +; CHECK-NEXT: stw 3, -72(1) +; CHECK-NEXT: .LBB0_10: # %entry +; CHECK-NEXT: lwz 3, -72(1) +; CHECK-NEXT: lwz 4, -76(1) +; CHECK-NEXT: lwz 5, -4(1) +; CHECK-NEXT: stw 4, 4(5) +; CHECK-NEXT: lfd 0, 0(3) + store double %y, double* @var2, align 8 +; CHECK-NEXT: lis 3, var2@ha +; CHECK-NEXT: stfd 0, var2@l(3) + %z = va_arg %struct.__va_list_tag* %ap, i32; From r7 +; CHECK-NEXT: lbz 3, 0(5) +; CHECK-NEXT: lwz 4, 4(5) +; CHECK-NEXT: lwz 6, 8(5) +; CHECK-NEXT: slwi 7, 3, 2 +; CHECK-NEXT: addi 8, 3, 1 +; CHECK-NEXT: cmpwi 0, 3, 8 +; CHECK-NEXT: addi 3, 4, 4 +; CHECK-NEXT: add 6, 6, 7 +; CHECK-NEXT: mr 7, 4 +; CHECK-NEXT: stw 6, -80(1) +; CHECK-NEXT: stw 8, -84(1) +; CHECK-NEXT: stw 3, -88(1) +; CHECK-NEXT: stw 4, -92(1) +; CHECK-NEXT: stw 7, -96(1) +; CHECK-NEXT: mfcr 0 # cr0 +; CHECK-NEXT: stw 0, -100(1) +; CHECK-NEXT: blt 0, .LBB0_12 +; CHECK-NEXT: # BB#11: # %entry +; CHECK-NEXT: lwz 3, -88(1) +; CHECK-NEXT: stw 3, -96(1) +; CHECK-NEXT: .LBB0_12: # %entry +; CHECK-NEXT: lwz 3, -96(1) +; CHECK-NEXT: lwz 4, -84(1) +; CHECK-NEXT: lwz 5, -4(1) +; CHECK-NEXT: stb 4, 0(5) +; CHECK-NEXT: lwz 4, -80(1) +; CHECK-NEXT: lwz 0, -100(1) +; CHECK-NEXT: mtcrf 128, 0 +; CHECK-NEXT: stw 4, -104(1) +; CHECK-NEXT: stw 3, -108(1) +; CHECK-NEXT: blt 0, .LBB0_14 +; CHECK-NEXT: # BB#13: # %entry +; CHECK-NEXT: lwz 3, -92(1) +; CHECK-NEXT: stw 3, -104(1) +; CHECK-NEXT: .LBB0_14: # %entry +; CHECK-NEXT: lwz 3, -104(1) +; CHECK-NEXT: lwz 4, -108(1) +; CHECK-NEXT: lwz 5, -4(1) +; CHECK-NEXT: stw 4, 4(5) +; CHECK-NEXT: lwz 3, 0(3) + store i32 %z, i32* @var3, align 4 +; CHECK-NEXT: lis 4, var3@ha +; CHECK-NEXT: stw 3, var3@l(4) + ret void +; CHECK-NEXT: stw 5, -112(1) +; CHECK-NEXT: blr +} + diff --git a/test/CodeGen/PowerPC/ppc64-32bit-addic.ll b/test/CodeGen/PowerPC/ppc64-32bit-addic.ll new file mode 100644 index 0000000..4d323da --- /dev/null +++ b/test/CodeGen/PowerPC/ppc64-32bit-addic.ll @@ -0,0 +1,29 @@ +; Check that the ADDIC optimizations are not applied on PPC64 +; RUN: llc < %s | FileCheck %s +; ModuleID = 'os_unix.c' +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64" +target triple = "powerpc64-unknown-freebsd9.0" + +define i32 @notZero(i32 %call) nounwind { +entry: +; CHECK-NOT: addic + %not.tobool = icmp ne i32 %call, 0 + %. = zext i1 %not.tobool to i32 + ret i32 %. +} + +define i32 @isMinusOne(i32 %call) nounwind { +entry: +; CHECK-NOT: addic + %not.tobool = icmp eq i32 %call, -1 + %. = zext i1 %not.tobool to i32 + ret i32 %. +} + +define i32 @isNotMinusOne(i32 %call) nounwind { +entry: +; CHECK-NOT: addic + %not.tobool = icmp ne i32 %call, -1 + %. = zext i1 %not.tobool to i32 + ret i32 %. +} diff --git a/test/CodeGen/PowerPC/ppc64-crash.ll b/test/CodeGen/PowerPC/ppc64-crash.ll new file mode 100644 index 0000000..073c322 --- /dev/null +++ b/test/CodeGen/PowerPC/ppc64-crash.ll @@ -0,0 +1,14 @@ +; RUN: llc %s -o - + +; ModuleID = 'undo.c' +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64" +target triple = "powerpc64-unknown-freebsd" + +%struct.__sFILE = type {} +%struct.pos_T = type { i64 } + +; check that we're not copying stuff between R and X registers +define internal void @serialize_pos(%struct.pos_T* byval %pos, %struct.__sFILE* %fp) nounwind { +entry: + ret void +} diff --git a/test/CodeGen/PowerPC/small-arguments.ll b/test/CodeGen/PowerPC/small-arguments.ll index 31bcee6..b4767b0 100644 --- a/test/CodeGen/PowerPC/small-arguments.ll +++ b/test/CodeGen/PowerPC/small-arguments.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -march=ppc32 | not grep {extsh\\|rlwinm} -declare i16 @foo() signext +declare signext i16 @foo() define i32 @test1(i16 signext %X) { %Y = sext i16 %X to i32 ;; dead @@ -14,12 +14,12 @@ define i32 @test2(i16 zeroext %X) { } define void @test3() { - %tmp.0 = call i16 @foo() signext ;; no extsh! + %tmp.0 = call signext i16 @foo() ;; no extsh! %tmp.1 = icmp slt i16 %tmp.0, 1234 br i1 %tmp.1, label %then, label %UnifiedReturnBlock then: - call i32 @test1(i16 0 signext) + call i32 @test1(i16 signext 0) ret void UnifiedReturnBlock: ret void @@ -46,7 +46,7 @@ define i32 @test6(i32* %P) { ret i32 %tmp.2 } -define i16 @test7(float %a) zeroext { +define zeroext i16 @test7(float %a) { %tmp.1 = fptoui float %a to i16 ret i16 %tmp.1 } diff --git a/test/CodeGen/PowerPC/vector.ll b/test/CodeGen/PowerPC/vector.ll index ee4da31..e4c3b0d 100644 --- a/test/CodeGen/PowerPC/vector.ll +++ b/test/CodeGen/PowerPC/vector.ll @@ -1,6 +1,6 @@ ; Test that vectors are scalarized/lowered correctly. ; RUN: llc < %s -march=ppc32 -mcpu=g5 > %t -; RUN: llc < %s -march=ppc32 -mcpu=g3 > %t +; RUN: llc < %s -march=ppc32 -mcpu=g3 >> %t %d8 = type <8 x double> %f1 = type <1 x float> |
