diff options
Diffstat (limited to 'test/CodeGen/PowerPC')
227 files changed, 1165 insertions, 510 deletions
diff --git a/test/CodeGen/PowerPC/2004-11-29-ShrCrash.ll b/test/CodeGen/PowerPC/2004-11-29-ShrCrash.ll index 70f294a..f95465c 100644 --- a/test/CodeGen/PowerPC/2004-11-29-ShrCrash.ll +++ b/test/CodeGen/PowerPC/2004-11-29-ShrCrash.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc32 +; RUN: llc < %s -march=ppc32 define void @test() { %tr1 = lshr i32 1, 0 ; <i32> [#uses=0] ret void diff --git a/test/CodeGen/PowerPC/2004-11-30-shift-crash.ll b/test/CodeGen/PowerPC/2004-11-30-shift-crash.ll index 93a9123..c3bfa49 100644 --- a/test/CodeGen/PowerPC/2004-11-30-shift-crash.ll +++ b/test/CodeGen/PowerPC/2004-11-30-shift-crash.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc32 +; RUN: llc < %s -march=ppc32 define void @main() { %tr4 = shl i64 1, 0 ; <i64> [#uses=0] diff --git a/test/CodeGen/PowerPC/2004-11-30-shr-var-crash.ll b/test/CodeGen/PowerPC/2004-11-30-shr-var-crash.ll index 1a1aca4..dea654a 100644 --- a/test/CodeGen/PowerPC/2004-11-30-shr-var-crash.ll +++ b/test/CodeGen/PowerPC/2004-11-30-shr-var-crash.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc32 +; RUN: llc < %s -march=ppc32 define void @main() { %shamt = add i8 0, 1 ; <i8> [#uses=1] diff --git a/test/CodeGen/PowerPC/2004-12-12-ZeroSizeCommon.ll b/test/CodeGen/PowerPC/2004-12-12-ZeroSizeCommon.ll index 3e490b1..fc190a48 100644 --- a/test/CodeGen/PowerPC/2004-12-12-ZeroSizeCommon.ll +++ b/test/CodeGen/PowerPC/2004-12-12-ZeroSizeCommon.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc32 | not grep .comm.*X,0 +; RUN: llc < %s -march=ppc32 | not grep .comm.*X,0 @X = linkonce global { } zeroinitializer ; <{ }*> [#uses=0] diff --git a/test/CodeGen/PowerPC/2005-01-14-SetSelectCrash.ll b/test/CodeGen/PowerPC/2005-01-14-SetSelectCrash.ll index f84caaf..ad02ece 100644 --- a/test/CodeGen/PowerPC/2005-01-14-SetSelectCrash.ll +++ b/test/CodeGen/PowerPC/2005-01-14-SetSelectCrash.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc32 +; RUN: llc < %s -march=ppc32 define i32 @main() { %setle = icmp sle i64 1, 0 ; <i1> [#uses=1] diff --git a/test/CodeGen/PowerPC/2005-01-14-UndefLong.ll b/test/CodeGen/PowerPC/2005-01-14-UndefLong.ll index 7b3e9b4..671bf80 100644 --- a/test/CodeGen/PowerPC/2005-01-14-UndefLong.ll +++ b/test/CodeGen/PowerPC/2005-01-14-UndefLong.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc32 +; RUN: llc < %s -march=ppc32 define i64 @test() { ret i64 undef diff --git a/test/CodeGen/PowerPC/2005-08-12-rlwimi-crash.ll b/test/CodeGen/PowerPC/2005-08-12-rlwimi-crash.ll index 8e8fee2..95012c3 100644 --- a/test/CodeGen/PowerPC/2005-08-12-rlwimi-crash.ll +++ b/test/CodeGen/PowerPC/2005-08-12-rlwimi-crash.ll @@ -1,6 +1,6 @@ ; this should not crash the ppc backend -; RUN: llvm-as < %s | llc -march=ppc32 +; RUN: llc < %s -march=ppc32 define i32 @test(i32 %j.0.0.i) { diff --git a/test/CodeGen/PowerPC/2005-09-02-LegalizeDuplicatesCalls.ll b/test/CodeGen/PowerPC/2005-09-02-LegalizeDuplicatesCalls.ll index 428dd0c..5d1df46 100644 --- a/test/CodeGen/PowerPC/2005-09-02-LegalizeDuplicatesCalls.ll +++ b/test/CodeGen/PowerPC/2005-09-02-LegalizeDuplicatesCalls.ll @@ -1,6 +1,6 @@ ; This function should have exactly one call to fixdfdi, no more! -; RUN: llvm-as < %s | llc -march=ppc32 -mattr=-64bit | \ +; RUN: llc < %s -march=ppc32 -mattr=-64bit | \ ; RUN: grep {bl .*fixdfdi} | count 1 define double @test2(double %tmp.7705) { diff --git a/test/CodeGen/PowerPC/2005-10-08-ArithmeticRotate.ll b/test/CodeGen/PowerPC/2005-10-08-ArithmeticRotate.ll index 54f24c6..8a5d3b0 100644 --- a/test/CodeGen/PowerPC/2005-10-08-ArithmeticRotate.ll +++ b/test/CodeGen/PowerPC/2005-10-08-ArithmeticRotate.ll @@ -1,7 +1,7 @@ ; This was erroneously being turned into an rlwinm instruction. ; The sign bit does matter in this case. -; RUN: llvm-as < %s | llc -march=ppc32 | grep srawi +; RUN: llc < %s -march=ppc32 | grep srawi define i32 @test(i32 %X) { %Y = and i32 %X, -2 ; <i32> [#uses=1] diff --git a/test/CodeGen/PowerPC/2005-11-30-vastart-crash.ll b/test/CodeGen/PowerPC/2005-11-30-vastart-crash.ll index d56cffc..047a12b 100644 --- a/test/CodeGen/PowerPC/2005-11-30-vastart-crash.ll +++ b/test/CodeGen/PowerPC/2005-11-30-vastart-crash.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc +; RUN: llc < %s target datalayout = "E-p:32:32" target triple = "powerpc-apple-darwin8.2.0" diff --git a/test/CodeGen/PowerPC/2006-01-11-darwin-fp-argument.ll b/test/CodeGen/PowerPC/2006-01-11-darwin-fp-argument.ll index 1b3bde8..97bb48e 100644 --- a/test/CodeGen/PowerPC/2006-01-11-darwin-fp-argument.ll +++ b/test/CodeGen/PowerPC/2006-01-11-darwin-fp-argument.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc | not grep {, f1} +; RUN: llc < %s | not grep {, f1} target datalayout = "E-p:32:32" target triple = "powerpc-apple-darwin8.2.0" diff --git a/test/CodeGen/PowerPC/2006-01-20-ShiftPartsCrash.ll b/test/CodeGen/PowerPC/2006-01-20-ShiftPartsCrash.ll index 86ad718..fbf2540 100644 --- a/test/CodeGen/PowerPC/2006-01-20-ShiftPartsCrash.ll +++ b/test/CodeGen/PowerPC/2006-01-20-ShiftPartsCrash.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc +; RUN: llc < %s define void @iterative_hash_host_wide_int() { %zero = alloca i32 ; <i32*> [#uses=2] diff --git a/test/CodeGen/PowerPC/2006-04-01-FloatDoubleExtend.ll b/test/CodeGen/PowerPC/2006-04-01-FloatDoubleExtend.ll index 8500260..172e348 100644 --- a/test/CodeGen/PowerPC/2006-04-01-FloatDoubleExtend.ll +++ b/test/CodeGen/PowerPC/2006-04-01-FloatDoubleExtend.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc32 +; RUN: llc < %s -march=ppc32 define double @CalcSpeed(float %tmp127) { diff --git a/test/CodeGen/PowerPC/2006-04-05-splat-ish.ll b/test/CodeGen/PowerPC/2006-04-05-splat-ish.ll index a536fa1..969772e 100644 --- a/test/CodeGen/PowerPC/2006-04-05-splat-ish.ll +++ b/test/CodeGen/PowerPC/2006-04-05-splat-ish.ll @@ -1,5 +1,4 @@ -; RUN: llvm-as < %s | \ -; RUN: llc -march=ppc32 -mtriple=powerpc-apple-darwin8 -mcpu=g5 | \ +; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -mcpu=g5 | \ ; RUN: grep {vspltish v.*, 10} define void @test(<8 x i16>* %P) { diff --git a/test/CodeGen/PowerPC/2006-04-19-vmaddfp-crash.ll b/test/CodeGen/PowerPC/2006-04-19-vmaddfp-crash.ll index b79cce2..d225664 100644 --- a/test/CodeGen/PowerPC/2006-04-19-vmaddfp-crash.ll +++ b/test/CodeGen/PowerPC/2006-04-19-vmaddfp-crash.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 +; RUN: llc < %s -march=ppc32 -mcpu=g5 ; END. define void @test(i8* %stack) { diff --git a/test/CodeGen/PowerPC/2006-05-12-rlwimi-crash.ll b/test/CodeGen/PowerPC/2006-05-12-rlwimi-crash.ll index e1033c3..0205d10 100644 --- a/test/CodeGen/PowerPC/2006-05-12-rlwimi-crash.ll +++ b/test/CodeGen/PowerPC/2006-05-12-rlwimi-crash.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc32 +; RUN: llc < %s -march=ppc32 ; END. %struct.attr_desc = type { i8*, %struct.attr_desc*, %struct.attr_value*, %struct.attr_value*, i32 } diff --git a/test/CodeGen/PowerPC/2006-07-07-ComputeMaskedBits.ll b/test/CodeGen/PowerPC/2006-07-07-ComputeMaskedBits.ll index 33807ca..1b8b064 100644 --- a/test/CodeGen/PowerPC/2006-07-07-ComputeMaskedBits.ll +++ b/test/CodeGen/PowerPC/2006-07-07-ComputeMaskedBits.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -mtriple=powerpc64-apple-darwin | grep extsw | count 2 +; RUN: llc < %s -mtriple=powerpc64-apple-darwin | grep extsw | count 2 @lens = external global i8* ; <i8**> [#uses=1] @vals = external global i32* ; <i32**> [#uses=1] diff --git a/test/CodeGen/PowerPC/2006-07-19-stwbrx-crash.ll b/test/CodeGen/PowerPC/2006-07-19-stwbrx-crash.ll index c25cf21..65dd568 100644 --- a/test/CodeGen/PowerPC/2006-07-19-stwbrx-crash.ll +++ b/test/CodeGen/PowerPC/2006-07-19-stwbrx-crash.ll @@ -1,6 +1,6 @@ -; RUN: llvm-as < %s | llc -march=ppc32 +; RUN: llc < %s -march=ppc32 -define void @img2buf(i32 %symbol_size_in_bytes, i16* %ui16) { +define void @img2buf(i32 %symbol_size_in_bytes, i16* %ui16) nounwind { %tmp93 = load i16* null ; <i16> [#uses=1] %tmp99 = call i16 @llvm.bswap.i16( i16 %tmp93 ) ; <i16> [#uses=1] store i16 %tmp99, i16* %ui16 diff --git a/test/CodeGen/PowerPC/2006-08-11-RetVector.ll b/test/CodeGen/PowerPC/2006-08-11-RetVector.ll index 1043e45..a947e5c 100644 --- a/test/CodeGen/PowerPC/2006-08-11-RetVector.ll +++ b/test/CodeGen/PowerPC/2006-08-11-RetVector.ll @@ -1,5 +1,5 @@ -; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | grep vsldoi -; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | not grep vor +; RUN: llc < %s -march=ppc32 -mcpu=g5 | grep vsldoi +; RUN: llc < %s -march=ppc32 -mcpu=g5 | not grep vor define <4 x float> @func(<4 x float> %fp0, <4 x float> %fp1) { %tmp76 = shufflevector <4 x float> %fp0, <4 x float> %fp1, <4 x i32> < i32 0, i32 1, i32 2, i32 7 > ; <<4 x float>> [#uses=1] diff --git a/test/CodeGen/PowerPC/2006-08-15-SelectionCrash.ll b/test/CodeGen/PowerPC/2006-08-15-SelectionCrash.ll index aff4ede..cb76b5c 100644 --- a/test/CodeGen/PowerPC/2006-08-15-SelectionCrash.ll +++ b/test/CodeGen/PowerPC/2006-08-15-SelectionCrash.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc +; RUN: llc < %s %struct..0anon = type { i32 } %struct.rtx_def = type { i16, i8, i8, [1 x %struct..0anon] } diff --git a/test/CodeGen/PowerPC/2006-09-28-shift_64.ll b/test/CodeGen/PowerPC/2006-09-28-shift_64.ll index 5210dd1..f748a8b 100644 --- a/test/CodeGen/PowerPC/2006-09-28-shift_64.ll +++ b/test/CodeGen/PowerPC/2006-09-28-shift_64.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc64 +; RUN: llc < %s -march=ppc64 target datalayout = "E-p:64:64" target triple = "powerpc64-apple-darwin8" diff --git a/test/CodeGen/PowerPC/2006-10-11-combiner-aa-regression.ll b/test/CodeGen/PowerPC/2006-10-11-combiner-aa-regression.ll index 7a65c00..57ed250 100644 --- a/test/CodeGen/PowerPC/2006-10-11-combiner-aa-regression.ll +++ b/test/CodeGen/PowerPC/2006-10-11-combiner-aa-regression.ll @@ -1,5 +1,4 @@ -; RUN: llvm-as < %s | \ -; RUN: llc -march=ppc32 -combiner-alias-analysis | grep f5 +; RUN: llc < %s -march=ppc32 -combiner-alias-analysis | grep f5 target datalayout = "E-p:32:32" target triple = "powerpc-apple-darwin8.2.0" diff --git a/test/CodeGen/PowerPC/2006-10-13-Miscompile.ll b/test/CodeGen/PowerPC/2006-10-13-Miscompile.ll index 6621cec..002a064 100644 --- a/test/CodeGen/PowerPC/2006-10-13-Miscompile.ll +++ b/test/CodeGen/PowerPC/2006-10-13-Miscompile.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc32 | not grep IMPLICIT_DEF +; RUN: llc < %s -march=ppc32 | not grep IMPLICIT_DEF define void @foo(i64 %X) { entry: diff --git a/test/CodeGen/PowerPC/2006-10-17-brcc-miscompile.ll b/test/CodeGen/PowerPC/2006-10-17-brcc-miscompile.ll index 313568c..3d462b4 100644 --- a/test/CodeGen/PowerPC/2006-10-17-brcc-miscompile.ll +++ b/test/CodeGen/PowerPC/2006-10-17-brcc-miscompile.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc32 | grep xor +; RUN: llc < %s -march=ppc32 | grep xor target datalayout = "E-p:32:32" target triple = "powerpc-apple-darwin8.7.0" diff --git a/test/CodeGen/PowerPC/2006-10-17-ppc64-alloca.ll b/test/CodeGen/PowerPC/2006-10-17-ppc64-alloca.ll index 6dc1ff0..3284f0a 100644 --- a/test/CodeGen/PowerPC/2006-10-17-ppc64-alloca.ll +++ b/test/CodeGen/PowerPC/2006-10-17-ppc64-alloca.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc64 +; RUN: llc < %s -march=ppc64 define i32* @foo(i32 %n) { %A = alloca i32, i32 %n ; <i32*> [#uses=1] diff --git a/test/CodeGen/PowerPC/2006-11-10-DAGCombineMiscompile.ll b/test/CodeGen/PowerPC/2006-11-10-DAGCombineMiscompile.ll index 80ef479..49b3b9d 100644 --- a/test/CodeGen/PowerPC/2006-11-10-DAGCombineMiscompile.ll +++ b/test/CodeGen/PowerPC/2006-11-10-DAGCombineMiscompile.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc32 | grep rlwimi +; RUN: llc < %s -march=ppc32 | grep rlwimi define void @test(i16 %div.0.i.i.i.i, i32 %L_num.0.i.i.i.i, i32 %tmp1.i.i206.i.i, i16* %P) { %X = shl i16 %div.0.i.i.i.i, 1 ; <i16> [#uses=1] diff --git a/test/CodeGen/PowerPC/2006-11-29-AltivecFPSplat.ll b/test/CodeGen/PowerPC/2006-11-29-AltivecFPSplat.ll index 7680c21..61b9967 100644 --- a/test/CodeGen/PowerPC/2006-11-29-AltivecFPSplat.ll +++ b/test/CodeGen/PowerPC/2006-11-29-AltivecFPSplat.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 +; RUN: llc < %s -march=ppc32 -mcpu=g5 define void @glgRunProcessor15() { %tmp26355.i = shufflevector <4 x float> zeroinitializer, <4 x float> < float 0x379FFFE000000000, float 0x379FFFE000000000, float 0x379FFFE000000000, float 0x379FFFE000000000 >, <4 x i32> < i32 0, i32 1, i32 2, i32 7 >; <<4 x float>> [#uses=1] diff --git a/test/CodeGen/PowerPC/2006-12-07-LargeAlloca.ll b/test/CodeGen/PowerPC/2006-12-07-LargeAlloca.ll index be3b863..ba86304 100644 --- a/test/CodeGen/PowerPC/2006-12-07-LargeAlloca.ll +++ b/test/CodeGen/PowerPC/2006-12-07-LargeAlloca.ll @@ -1,6 +1,6 @@ -; RUN: llvm-as < %s | llc -march=ppc64 -; RUN: llvm-as < %s | llc -march=ppc32 -; RUN: llvm-as < %s | llc +; RUN: llc < %s -march=ppc64 +; RUN: llc < %s -march=ppc32 +; RUN: llc < %s define void @bitap() { entry: diff --git a/test/CodeGen/PowerPC/2006-12-07-SelectCrash.ll b/test/CodeGen/PowerPC/2006-12-07-SelectCrash.ll index 058166f..6d9a3fa 100644 --- a/test/CodeGen/PowerPC/2006-12-07-SelectCrash.ll +++ b/test/CodeGen/PowerPC/2006-12-07-SelectCrash.ll @@ -1,6 +1,6 @@ -; RUN: llvm-as < %s | llc -march=ppc64 -; RUN: llvm-as < %s | llc -march=ppc32 -; RUN: llvm-as < %s | llc +; RUN: llc < %s -march=ppc64 +; RUN: llc < %s -march=ppc32 +; RUN: llc < %s @qsz.b = external global i1 ; <i1*> [#uses=1] diff --git a/test/CodeGen/PowerPC/2007-01-04-ArgExtension.ll b/test/CodeGen/PowerPC/2007-01-04-ArgExtension.ll index 19fedf9..805528c 100644 --- a/test/CodeGen/PowerPC/2007-01-04-ArgExtension.ll +++ b/test/CodeGen/PowerPC/2007-01-04-ArgExtension.ll @@ -1,5 +1,5 @@ -; RUN: llvm-as < %s | llc -march=ppc32 | grep extsb -; RUN: llvm-as < %s | llc -march=ppc32 | grep extsh +; RUN: llc < %s -march=ppc32 | grep extsb +; RUN: llc < %s -march=ppc32 | grep extsh define i32 @p1(i8 %c, i16 %s) { entry: diff --git a/test/CodeGen/PowerPC/2007-01-15-AsmDialect.ll b/test/CodeGen/PowerPC/2007-01-15-AsmDialect.ll index d9374ed..7b00ac6 100644 --- a/test/CodeGen/PowerPC/2007-01-15-AsmDialect.ll +++ b/test/CodeGen/PowerPC/2007-01-15-AsmDialect.ll @@ -1,7 +1,7 @@ -; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-apple-darwin8 | \ +; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 | \ ; RUN: grep cntlzw -define i32 @foo() { +define i32 @foo() nounwind { entry: %retval = alloca i32, align 4 ; <i32*> [#uses=2] %temp = alloca i32, align 4 ; <i32*> [#uses=2] diff --git a/test/CodeGen/PowerPC/2007-01-29-lbrx-asm.ll b/test/CodeGen/PowerPC/2007-01-29-lbrx-asm.ll index f2c951e..0c45472 100644 --- a/test/CodeGen/PowerPC/2007-01-29-lbrx-asm.ll +++ b/test/CodeGen/PowerPC/2007-01-29-lbrx-asm.ll @@ -1,5 +1,5 @@ -; RUN: llvm-as < %s | llc -march=ppc32 -; RUN: llvm-as < %s | llc -march=ppc64 +; RUN: llc < %s -march=ppc32 +; RUN: llc < %s -march=ppc64 define i16 @test(i8* %d1, i16* %d2) { %tmp237 = call i16 asm "lhbrx $0, $2, $1", "=r,r,bO,m"( i8* %d1, i32 0, i16* %d2 ) ; <i16> [#uses=1] diff --git a/test/CodeGen/PowerPC/2007-01-31-InlineAsmAddrMode.ll b/test/CodeGen/PowerPC/2007-01-31-InlineAsmAddrMode.ll index d476462..fe5145d 100644 --- a/test/CodeGen/PowerPC/2007-01-31-InlineAsmAddrMode.ll +++ b/test/CodeGen/PowerPC/2007-01-31-InlineAsmAddrMode.ll @@ -1,5 +1,5 @@ -; RUN: llvm-as < %s | llc -march=ppc32 -; RUN: llvm-as < %s | llc -march=ppc64 +; RUN: llc < %s -march=ppc32 +; RUN: llc < %s -march=ppc64 ; Test two things: 1) that a frameidx can be rewritten in an inline asm ; 2) that inline asms can handle reg+imm addr modes. diff --git a/test/CodeGen/PowerPC/2007-02-16-AlignPacked.ll b/test/CodeGen/PowerPC/2007-02-16-AlignPacked.ll index 97f6a01..621d43b 100644 --- a/test/CodeGen/PowerPC/2007-02-16-AlignPacked.ll +++ b/test/CodeGen/PowerPC/2007-02-16-AlignPacked.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-apple-darwin8.8.0 | \ +; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8.8.0 | \ ; RUN: grep align.*3 @X = global <{i32, i32}> <{ i32 1, i32 123 }> diff --git a/test/CodeGen/PowerPC/2007-02-16-InlineAsmNConstraint.ll b/test/CodeGen/PowerPC/2007-02-16-InlineAsmNConstraint.ll index 5a3d3b5..f48f365 100644 --- a/test/CodeGen/PowerPC/2007-02-16-InlineAsmNConstraint.ll +++ b/test/CodeGen/PowerPC/2007-02-16-InlineAsmNConstraint.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc +; RUN: llc < %s target datalayout = "E-p:32:32" target triple = "powerpc-apple-darwin8.8.0" diff --git a/test/CodeGen/PowerPC/2007-02-23-lr-saved-twice.ll b/test/CodeGen/PowerPC/2007-02-23-lr-saved-twice.ll index 3eef9c5..0473857 100644 --- a/test/CodeGen/PowerPC/2007-02-23-lr-saved-twice.ll +++ b/test/CodeGen/PowerPC/2007-02-23-lr-saved-twice.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc | grep mflr | count 1 +; RUN: llc < %s | grep mflr | count 1 target datalayout = "e-p:32:32" target triple = "powerpc-apple-darwin8" diff --git a/test/CodeGen/PowerPC/2007-03-24-cntlzd.ll b/test/CodeGen/PowerPC/2007-03-24-cntlzd.ll index 098e748..e93395a 100644 --- a/test/CodeGen/PowerPC/2007-03-24-cntlzd.ll +++ b/test/CodeGen/PowerPC/2007-03-24-cntlzd.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc64 -mcpu=g5 | grep cntlzd +; RUN: llc < %s -march=ppc64 -mcpu=g5 | grep cntlzd define i32 @_ZNK4llvm5APInt17countLeadingZerosEv(i64 *%t) { %tmp19 = load i64* %t diff --git a/test/CodeGen/PowerPC/2007-03-30-SpillerCrash.ll b/test/CodeGen/PowerPC/2007-03-30-SpillerCrash.ll index 637208b..d43916d 100644 --- a/test/CodeGen/PowerPC/2007-03-30-SpillerCrash.ll +++ b/test/CodeGen/PowerPC/2007-03-30-SpillerCrash.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 +; RUN: llc < %s -march=ppc32 -mcpu=g5 define void @test(<4 x float>*, { { i16, i16, i32 } }*) { xOperationInitMasks.exit: diff --git a/test/CodeGen/PowerPC/2007-04-24-InlineAsm-I-Modifier.ll b/test/CodeGen/PowerPC/2007-04-24-InlineAsm-I-Modifier.ll index 656b831..86fd947 100644 --- a/test/CodeGen/PowerPC/2007-04-24-InlineAsm-I-Modifier.ll +++ b/test/CodeGen/PowerPC/2007-04-24-InlineAsm-I-Modifier.ll @@ -1,5 +1,5 @@ -; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-apple-darwin8.8.0 | grep {foo r3, r4} -; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-apple-darwin8.8.0 | grep {bari r3, 47} +; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8.8.0 | grep {foo r3, r4} +; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8.8.0 | grep {bari r3, 47} ; PR1351 diff --git a/test/CodeGen/PowerPC/2007-04-30-InlineAsmEarlyClobber.ll b/test/CodeGen/PowerPC/2007-04-30-InlineAsmEarlyClobber.ll index ba0f8fe..f2fdedf 100644 --- a/test/CodeGen/PowerPC/2007-04-30-InlineAsmEarlyClobber.ll +++ b/test/CodeGen/PowerPC/2007-04-30-InlineAsmEarlyClobber.ll @@ -1,7 +1,7 @@ -; RUN: llvm-as < %s | llc | grep {subfc r3,r5,r4} -; RUN: llvm-as < %s | llc | grep {subfze r4,r2} -; RUN: llvm-as < %s | llc -regalloc=local | grep {subfc r5,r2,r4} -; RUN: llvm-as < %s | llc -regalloc=local | grep {subfze r2,r3} +; RUN: llc < %s | grep {subfc r3,r5,r4} +; RUN: llc < %s | grep {subfze r4,r2} +; RUN: llc < %s -regalloc=local | grep {subfc r5,r2,r4} +; RUN: llc < %s -regalloc=local | grep {subfze r2,r3} ; The first argument of subfc must not be the same as any other register. ; PR1357 diff --git a/test/CodeGen/PowerPC/2007-05-03-InlineAsm-S-Constraint.ll b/test/CodeGen/PowerPC/2007-05-03-InlineAsm-S-Constraint.ll index 989a751..1df5140 100644 --- a/test/CodeGen/PowerPC/2007-05-03-InlineAsm-S-Constraint.ll +++ b/test/CodeGen/PowerPC/2007-05-03-InlineAsm-S-Constraint.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc +; RUN: llc < %s ; PR1382 target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64" diff --git a/test/CodeGen/PowerPC/2007-05-14-InlineAsmSelectCrash.ll b/test/CodeGen/PowerPC/2007-05-14-InlineAsmSelectCrash.ll index b64de68..e4e9314 100644 --- a/test/CodeGen/PowerPC/2007-05-14-InlineAsmSelectCrash.ll +++ b/test/CodeGen/PowerPC/2007-05-14-InlineAsmSelectCrash.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc32 +; RUN: llc < %s -march=ppc32 target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64" target triple = "powerpc-apple-darwin8.8.0" %struct..0anon = type { i32 } diff --git a/test/CodeGen/PowerPC/2007-05-22-tailmerge-3.ll b/test/CodeGen/PowerPC/2007-05-22-tailmerge-3.ll index 5a86418..42f2152 100644 --- a/test/CodeGen/PowerPC/2007-05-22-tailmerge-3.ll +++ b/test/CodeGen/PowerPC/2007-05-22-tailmerge-3.ll @@ -1,7 +1,7 @@ -; RUN: llvm-as < %s | llc -march=ppc32 | grep bl.*baz | count 2 -; RUN: llvm-as < %s | llc -march=ppc32 | grep bl.*quux | count 2 -; RUN: llvm-as < %s | llc -march=ppc32 -enable-tail-merge | grep bl.*baz | count 1 -; RUN: llvm-as < %s | llc -march=ppc32 -enable-tail-merge=1 | grep bl.*quux | count 1 +; RUN: llc < %s -march=ppc32 | grep bl.*baz | count 2 +; RUN: llc < %s -march=ppc32 | grep bl.*quux | count 2 +; RUN: llc < %s -march=ppc32 -enable-tail-merge | grep bl.*baz | count 1 +; RUN: llc < %s -march=ppc32 -enable-tail-merge=1 | grep bl.*quux | count 1 ; Check that tail merging is not the default on ppc, and that -enable-tail-merge works. ; ModuleID = 'tail.c' diff --git a/test/CodeGen/PowerPC/2007-05-30-dagcombine-miscomp.ll b/test/CodeGen/PowerPC/2007-05-30-dagcombine-miscomp.ll index ae853f6..2938c70 100644 --- a/test/CodeGen/PowerPC/2007-05-30-dagcombine-miscomp.ll +++ b/test/CodeGen/PowerPC/2007-05-30-dagcombine-miscomp.ll @@ -1,7 +1,7 @@ target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64" target triple = "powerpc-apple-darwin8.8.0" -; RUN: llvm-as < %s | llc -march=ppc32 | grep {rlwinm r3, r3, 23, 30, 30} +; RUN: llc < %s -march=ppc32 | grep {rlwinm r3, r3, 23, 30, 30} ; PR1473 define i8 @foo(i16 zeroext %a) zeroext { diff --git a/test/CodeGen/PowerPC/2007-06-28-BCCISelBug.ll b/test/CodeGen/PowerPC/2007-06-28-BCCISelBug.ll index 58260ec..6de7a09 100644 --- a/test/CodeGen/PowerPC/2007-06-28-BCCISelBug.ll +++ b/test/CodeGen/PowerPC/2007-06-28-BCCISelBug.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc32 -mattr=+altivec +; RUN: llc < %s -march=ppc32 -mattr=+altivec %struct.XATest = type { float, i16, i8, i8 } %struct.XArrayRange = type { i8, i8, i8, i8 } diff --git a/test/CodeGen/PowerPC/2007-08-04-CoalescerAssert.ll b/test/CodeGen/PowerPC/2007-08-04-CoalescerAssert.ll index 34df7bb..06f40d9 100644 --- a/test/CodeGen/PowerPC/2007-08-04-CoalescerAssert.ll +++ b/test/CodeGen/PowerPC/2007-08-04-CoalescerAssert.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc64 +; RUN: llc < %s -march=ppc64 ; PR1596 %struct._obstack_chunk = type { i8* } diff --git a/test/CodeGen/PowerPC/2007-09-04-AltivecDST.ll b/test/CodeGen/PowerPC/2007-09-04-AltivecDST.ll index 9c8fa97..82ef2b8 100644 --- a/test/CodeGen/PowerPC/2007-09-04-AltivecDST.ll +++ b/test/CodeGen/PowerPC/2007-09-04-AltivecDST.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc64 | grep dst | count 4 +; RUN: llc < %s -march=ppc64 | grep dst | count 4 define hidden void @_Z4borkPc(i8* %image) { entry: diff --git a/test/CodeGen/PowerPC/2007-09-07-LoadStoreIdxForms.ll b/test/CodeGen/PowerPC/2007-09-07-LoadStoreIdxForms.ll index c5e7a4d..ea7de98 100644 --- a/test/CodeGen/PowerPC/2007-09-07-LoadStoreIdxForms.ll +++ b/test/CodeGen/PowerPC/2007-09-07-LoadStoreIdxForms.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc64 | grep lwzx +; RUN: llc < %s -march=ppc64 | grep lwzx %struct.__db_region = type { %struct.__mutex_t, [4 x i8], %struct.anon, i32, [1 x i32] } %struct.__mutex_t = type { i32 } diff --git a/test/CodeGen/PowerPC/2007-09-08-unaligned.ll b/test/CodeGen/PowerPC/2007-09-08-unaligned.ll index f6bd333..898c470 100644 --- a/test/CodeGen/PowerPC/2007-09-08-unaligned.ll +++ b/test/CodeGen/PowerPC/2007-09-08-unaligned.ll @@ -1,7 +1,7 @@ -; RUN: llvm-as < %s | llc | grep stfd | count 3 -; RUN: llvm-as < %s | llc | grep stfs | count 1 -; RUN: llvm-as < %s | llc | grep lfd | count 2 -; RUN: llvm-as < %s | llc | grep lfs | count 2 +; RUN: llc < %s | grep stfd | count 3 +; RUN: llc < %s | grep stfs | count 1 +; RUN: llc < %s | grep lfd | count 2 +; RUN: llc < %s | grep lfs | count 2 ; ModuleID = 'foo.c' target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128" target triple = "powerpc-apple-darwin8" diff --git a/test/CodeGen/PowerPC/2007-09-11-RegCoalescerAssert.ll b/test/CodeGen/PowerPC/2007-09-11-RegCoalescerAssert.ll index bb7aba4..d12698b 100644 --- a/test/CodeGen/PowerPC/2007-09-11-RegCoalescerAssert.ll +++ b/test/CodeGen/PowerPC/2007-09-11-RegCoalescerAssert.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc64 +; RUN: llc < %s -march=ppc64 %struct.TCMalloc_SpinLock = type { i32 } diff --git a/test/CodeGen/PowerPC/2007-09-12-LiveIntervalsAssert.ll b/test/CodeGen/PowerPC/2007-09-12-LiveIntervalsAssert.ll index f4b87cf..5cfe54e 100644 --- a/test/CodeGen/PowerPC/2007-09-12-LiveIntervalsAssert.ll +++ b/test/CodeGen/PowerPC/2007-09-12-LiveIntervalsAssert.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -mtriple=powerpc64-apple-darwin +; RUN: llc < %s -mtriple=powerpc64-apple-darwin declare void @cxa_atexit_check_1(i8*) diff --git a/test/CodeGen/PowerPC/2007-10-16-InlineAsmFrameOffset.ll b/test/CodeGen/PowerPC/2007-10-16-InlineAsmFrameOffset.ll index e71a8fb..c4152b4 100644 --- a/test/CodeGen/PowerPC/2007-10-16-InlineAsmFrameOffset.ll +++ b/test/CodeGen/PowerPC/2007-10-16-InlineAsmFrameOffset.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc32 +; RUN: llc < %s -march=ppc32 ; rdar://5538377 %struct.disk_unsigned = type { i32 } diff --git a/test/CodeGen/PowerPC/2007-10-18-PtrArithmetic.ll b/test/CodeGen/PowerPC/2007-10-18-PtrArithmetic.ll index bd11b5d..84fadd1 100644 --- a/test/CodeGen/PowerPC/2007-10-18-PtrArithmetic.ll +++ b/test/CodeGen/PowerPC/2007-10-18-PtrArithmetic.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc64 -mattr=+altivec +; RUN: llc < %s -march=ppc64 -mattr=+altivec %struct.inoutprops = type <{ i8, [3 x i8] }> define void @bork(float* %argA, float* %argB, float* %res, i8 %inoutspec.0) { diff --git a/test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert.ll b/test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert.ll index bca6e5a..ee61478 100644 --- a/test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert.ll +++ b/test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -mtriple=powerpc64-apple-darwin9 -regalloc=local -relocation-model=pic +; RUN: llc < %s -mtriple=powerpc64-apple-darwin9 -regalloc=local -relocation-model=pic %struct.NSError = type opaque %struct.NSManagedObjectContext = type opaque diff --git a/test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert2.ll b/test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert2.ll index 80ef6f1..5a07a9b 100644 --- a/test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert2.ll +++ b/test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert2.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -mtriple=powerpc64-apple-darwin9 -regalloc=local -relocation-model=pic +; RUN: llc < %s -mtriple=powerpc64-apple-darwin9 -regalloc=local -relocation-model=pic %struct.NSError = type opaque %struct.NSManagedObjectContext = type opaque diff --git a/test/CodeGen/PowerPC/2007-11-04-CoalescerCrash.ll b/test/CodeGen/PowerPC/2007-11-04-CoalescerCrash.ll index e49d59a..a9f242b 100644 --- a/test/CodeGen/PowerPC/2007-11-04-CoalescerCrash.ll +++ b/test/CodeGen/PowerPC/2007-11-04-CoalescerCrash.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -mtriple=powerpc-apple-darwin +; RUN: llc < %s -mtriple=powerpc-apple-darwin %struct.HDescriptor = type <{ i32, i32 }> diff --git a/test/CodeGen/PowerPC/2007-11-16-landingpad-split.ll b/test/CodeGen/PowerPC/2007-11-16-landingpad-split.ll index a0649e0..439ef14 100644 --- a/test/CodeGen/PowerPC/2007-11-16-landingpad-split.ll +++ b/test/CodeGen/PowerPC/2007-11-16-landingpad-split.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -enable-eh +; RUN: llc < %s -enable-eh ;; Formerly crashed, see PR 1508 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128" target triple = "powerpc64-apple-darwin8" diff --git a/test/CodeGen/PowerPC/2007-11-19-VectorSplitting.ll b/test/CodeGen/PowerPC/2007-11-19-VectorSplitting.ll index aca0faa..d1f0285 100644 --- a/test/CodeGen/PowerPC/2007-11-19-VectorSplitting.ll +++ b/test/CodeGen/PowerPC/2007-11-19-VectorSplitting.ll @@ -1,6 +1,6 @@ -; RUN: llvm-as < %s | llc -; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g3 -; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 +; RUN: llc < %s +; RUN: llc < %s -march=ppc32 -mcpu=g3 +; RUN: llc < %s -march=ppc32 -mcpu=g5 ; PR1811 define void @execute_shader(<4 x float>* %OUT, <4 x float>* %IN, <4 x float>* diff --git a/test/CodeGen/PowerPC/2008-01-25-EmptyFunction.ll b/test/CodeGen/PowerPC/2008-01-25-EmptyFunction.ll index 38ae87c..db2ab87 100644 --- a/test/CodeGen/PowerPC/2008-01-25-EmptyFunction.ll +++ b/test/CodeGen/PowerPC/2008-01-25-EmptyFunction.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc32 | grep nop +; RUN: llc < %s -march=ppc32 | grep nop target triple = "powerpc-apple-darwin8" diff --git a/test/CodeGen/PowerPC/2008-02-05-LiveIntervalsAssert.ll b/test/CodeGen/PowerPC/2008-02-05-LiveIntervalsAssert.ll index 5b9cd1d..791e9e6 100644 --- a/test/CodeGen/PowerPC/2008-02-05-LiveIntervalsAssert.ll +++ b/test/CodeGen/PowerPC/2008-02-05-LiveIntervalsAssert.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -mtriple=powerpc-apple-darwin +; RUN: llc < %s -mtriple=powerpc-apple-darwin %struct.Handle = type { %struct.oopDesc** } %struct.JNI_ArgumentPusher = type { %struct.SignatureIterator, %struct.JavaCallArguments* } diff --git a/test/CodeGen/PowerPC/2008-02-09-LocalRegAllocAssert.ll b/test/CodeGen/PowerPC/2008-02-09-LocalRegAllocAssert.ll index 5edf6b7..cfa1b10 100644 --- a/test/CodeGen/PowerPC/2008-02-09-LocalRegAllocAssert.ll +++ b/test/CodeGen/PowerPC/2008-02-09-LocalRegAllocAssert.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -mtriple=powerpc-apple-darwin -regalloc=local +; RUN: llc < %s -mtriple=powerpc-apple-darwin -regalloc=local define i32 @bork(i64 %foo, i64 %bar) { entry: diff --git a/test/CodeGen/PowerPC/2008-03-05-RegScavengerAssert.ll b/test/CodeGen/PowerPC/2008-03-05-RegScavengerAssert.ll index 8101a35..e50fac4 100644 --- a/test/CodeGen/PowerPC/2008-03-05-RegScavengerAssert.ll +++ b/test/CodeGen/PowerPC/2008-03-05-RegScavengerAssert.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -mtriple=powerpc-apple-darwin -enable-ppc32-regscavenger +; RUN: llc < %s -mtriple=powerpc-apple-darwin -enable-ppc32-regscavenger declare i8* @bar(i32) diff --git a/test/CodeGen/PowerPC/2008-03-06-KillInfo.ll b/test/CodeGen/PowerPC/2008-03-06-KillInfo.ll index 919de33..222dde4 100644 --- a/test/CodeGen/PowerPC/2008-03-06-KillInfo.ll +++ b/test/CodeGen/PowerPC/2008-03-06-KillInfo.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc64 -enable-ppc64-regscavenger +; RUN: llc < %s -march=ppc64 -enable-ppc64-regscavenger @.str242 = external constant [3 x i8] ; <[3 x i8]*> [#uses=1] define fastcc void @ParseContent(i8* %buf, i32 %bufsize) { diff --git a/test/CodeGen/PowerPC/2008-03-17-RegScavengerCrash.ll b/test/CodeGen/PowerPC/2008-03-17-RegScavengerCrash.ll index eaeccc5..9f35b83 100644 --- a/test/CodeGen/PowerPC/2008-03-17-RegScavengerCrash.ll +++ b/test/CodeGen/PowerPC/2008-03-17-RegScavengerCrash.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc32 -enable-ppc32-regscavenger +; RUN: llc < %s -march=ppc32 -enable-ppc32-regscavenger %struct._cpp_strbuf = type { i8*, i32, i32 } %struct.cpp_string = type { i32, i8* } diff --git a/test/CodeGen/PowerPC/2008-03-18-RegScavengerAssert.ll b/test/CodeGen/PowerPC/2008-03-18-RegScavengerAssert.ll index 061c585..dd425f5 100644 --- a/test/CodeGen/PowerPC/2008-03-18-RegScavengerAssert.ll +++ b/test/CodeGen/PowerPC/2008-03-18-RegScavengerAssert.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc64 -enable-ppc64-regscavenger +; RUN: llc < %s -march=ppc64 -enable-ppc64-regscavenger define i16 @test(i8* %d1, i16* %d2) { %tmp237 = call i16 asm "lhbrx $0, $2, $1", "=r,r,bO,m"( i8* %d1, i32 0, i16* %d2 ) diff --git a/test/CodeGen/PowerPC/2008-03-24-AddressRegImm.ll b/test/CodeGen/PowerPC/2008-03-24-AddressRegImm.ll index 395c986..a8fef05 100644 --- a/test/CodeGen/PowerPC/2008-03-24-AddressRegImm.ll +++ b/test/CodeGen/PowerPC/2008-03-24-AddressRegImm.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc64 +; RUN: llc < %s -march=ppc64 define fastcc i8* @page_rec_get_next(i8* %rec) nounwind { entry: diff --git a/test/CodeGen/PowerPC/2008-03-24-CoalescerBug.ll b/test/CodeGen/PowerPC/2008-03-24-CoalescerBug.ll index 67c167a..8776d9a 100644 --- a/test/CodeGen/PowerPC/2008-03-24-CoalescerBug.ll +++ b/test/CodeGen/PowerPC/2008-03-24-CoalescerBug.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc32 +; RUN: llc < %s -march=ppc32 %struct..0objc_object = type { %struct.objc_class* } %struct.NSArray = type { %struct..0objc_object } diff --git a/test/CodeGen/PowerPC/2008-03-26-CoalescerBug.ll b/test/CodeGen/PowerPC/2008-03-26-CoalescerBug.ll index 0b748d2..8e5bf56 100644 --- a/test/CodeGen/PowerPC/2008-03-26-CoalescerBug.ll +++ b/test/CodeGen/PowerPC/2008-03-26-CoalescerBug.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -mtriple=powerpc-apple-darwin +; RUN: llc < %s -mtriple=powerpc-apple-darwin define i32 @t(i64 %byteStart, i32 %activeIndex) nounwind { entry: diff --git a/test/CodeGen/PowerPC/2008-04-10-LiveIntervalCrash.ll b/test/CodeGen/PowerPC/2008-04-10-LiveIntervalCrash.ll index 410736d..2706337 100644 --- a/test/CodeGen/PowerPC/2008-04-10-LiveIntervalCrash.ll +++ b/test/CodeGen/PowerPC/2008-04-10-LiveIntervalCrash.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -mtriple=powerpc-apple-darwin +; RUN: llc < %s -mtriple=powerpc-apple-darwin define fastcc i64 @nonzero_bits1() nounwind { entry: diff --git a/test/CodeGen/PowerPC/2008-04-16-CoalescerBug.ll b/test/CodeGen/PowerPC/2008-04-16-CoalescerBug.ll index 357ab10..839098e 100644 --- a/test/CodeGen/PowerPC/2008-04-16-CoalescerBug.ll +++ b/test/CodeGen/PowerPC/2008-04-16-CoalescerBug.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -mtriple=powerpc-apple-darwin +; RUN: llc < %s -mtriple=powerpc-apple-darwin ; Avoid reading memory that's already freed. @llvm.used = appending global [1 x i8*] [ i8* bitcast (i32 (i64)* @_Z13GetSectorSizey to i8*) ], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0] diff --git a/test/CodeGen/PowerPC/2008-04-23-CoalescerCrash.ll b/test/CodeGen/PowerPC/2008-04-23-CoalescerCrash.ll index a390e52..7b6d491 100644 --- a/test/CodeGen/PowerPC/2008-04-23-CoalescerCrash.ll +++ b/test/CodeGen/PowerPC/2008-04-23-CoalescerCrash.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -mtriple=powerpc-apple-darwin +; RUN: llc < %s -mtriple=powerpc-apple-darwin @_ZL10DeviceCode = internal global i16 0 ; <i16*> [#uses=1] @.str19 = internal constant [64 x i8] c"unlock_then_erase_sector: failed to erase block (status= 0x%x)\0A\00" ; <[64 x i8]*> [#uses=1] diff --git a/test/CodeGen/PowerPC/2008-05-01-ppc_fp128.ll b/test/CodeGen/PowerPC/2008-05-01-ppc_fp128.ll index 5c40b9e..d42c814 100644 --- a/test/CodeGen/PowerPC/2008-05-01-ppc_fp128.ll +++ b/test/CodeGen/PowerPC/2008-05-01-ppc_fp128.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc32 +; RUN: llc < %s -march=ppc32 target triple = "powerpc-apple-darwin9.2.2" define i256 @func(ppc_fp128 %a, ppc_fp128 %b, ppc_fp128 %c, ppc_fp128 %d) nounwind readnone { diff --git a/test/CodeGen/PowerPC/2008-06-19-LegalizerCrash.ll b/test/CodeGen/PowerPC/2008-06-19-LegalizerCrash.ll index d337e37..6b40b24 100644 --- a/test/CodeGen/PowerPC/2008-06-19-LegalizerCrash.ll +++ b/test/CodeGen/PowerPC/2008-06-19-LegalizerCrash.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc32 +; RUN: llc < %s -march=ppc32 define void @t() nounwind { call void null( ppc_fp128 undef ) diff --git a/test/CodeGen/PowerPC/2008-06-21-F128LoadStore.ll b/test/CodeGen/PowerPC/2008-06-21-F128LoadStore.ll index 92b5ca2..862559b 100644 --- a/test/CodeGen/PowerPC/2008-06-21-F128LoadStore.ll +++ b/test/CodeGen/PowerPC/2008-06-21-F128LoadStore.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc32 +; RUN: llc < %s -march=ppc32 @g = external global ppc_fp128 @h = external global ppc_fp128 diff --git a/test/CodeGen/PowerPC/2008-06-23-LiveVariablesCrash.ll b/test/CodeGen/PowerPC/2008-06-23-LiveVariablesCrash.ll index d3238d2..83c5511 100644 --- a/test/CodeGen/PowerPC/2008-06-23-LiveVariablesCrash.ll +++ b/test/CodeGen/PowerPC/2008-06-23-LiveVariablesCrash.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc32 +; RUN: llc < %s -march=ppc32 ; <rdar://problem/6020042> define i32 @bork() nounwind { diff --git a/test/CodeGen/PowerPC/2008-07-10-SplatMiscompile.ll b/test/CodeGen/PowerPC/2008-07-10-SplatMiscompile.ll index b6b9c89..8802b97 100644 --- a/test/CodeGen/PowerPC/2008-07-10-SplatMiscompile.ll +++ b/test/CodeGen/PowerPC/2008-07-10-SplatMiscompile.ll @@ -1,5 +1,5 @@ -; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | grep vadduhm -; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | grep vsubuhm +; RUN: llc < %s -march=ppc32 -mcpu=g5 | grep vadduhm +; RUN: llc < %s -march=ppc32 -mcpu=g5 | grep vsubuhm define <4 x i32> @test() nounwind { ret <4 x i32> < i32 4293066722, i32 4293066722, i32 4293066722, i32 4293066722> diff --git a/test/CodeGen/PowerPC/2008-07-15-Bswap.ll b/test/CodeGen/PowerPC/2008-07-15-Bswap.ll index 7060fe5..4a834f9 100644 --- a/test/CodeGen/PowerPC/2008-07-15-Bswap.ll +++ b/test/CodeGen/PowerPC/2008-07-15-Bswap.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc +; RUN: llc < %s target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128" target triple = "powerpc-apple-darwin9" %struct.BiPartSrcDescriptor = type <{ %"struct.BiPartSrcDescriptor::$_105" }> diff --git a/test/CodeGen/PowerPC/2008-07-15-Fabs.ll b/test/CodeGen/PowerPC/2008-07-15-Fabs.ll index f55ffac..17737d9 100644 --- a/test/CodeGen/PowerPC/2008-07-15-Fabs.ll +++ b/test/CodeGen/PowerPC/2008-07-15-Fabs.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc +; RUN: llc < %s target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128" target triple = "powerpc-apple-darwin9" diff --git a/test/CodeGen/PowerPC/2008-07-15-SignExtendInreg.ll b/test/CodeGen/PowerPC/2008-07-15-SignExtendInreg.ll index 32e3642..5cd8c34 100644 --- a/test/CodeGen/PowerPC/2008-07-15-SignExtendInreg.ll +++ b/test/CodeGen/PowerPC/2008-07-15-SignExtendInreg.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc +; RUN: llc < %s target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128" target triple = "powerpc-apple-darwin9" diff --git a/test/CodeGen/PowerPC/2008-07-17-Fneg.ll b/test/CodeGen/PowerPC/2008-07-17-Fneg.ll index a7f8181..dc1e936 100644 --- a/test/CodeGen/PowerPC/2008-07-17-Fneg.ll +++ b/test/CodeGen/PowerPC/2008-07-17-Fneg.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc +; RUN: llc < %s target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128" target triple = "powerpc-apple-darwin9" diff --git a/test/CodeGen/PowerPC/2008-07-24-PPC64-CCBug.ll b/test/CodeGen/PowerPC/2008-07-24-PPC64-CCBug.ll index 2ccca25..c9c05e1 100644 --- a/test/CodeGen/PowerPC/2008-07-24-PPC64-CCBug.ll +++ b/test/CodeGen/PowerPC/2008-07-24-PPC64-CCBug.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -mtriple=powerpc64-apple-darwin | grep lwz | grep 228 +; RUN: llc < %s -mtriple=powerpc64-apple-darwin | grep lwz | grep 228 @"\01LC" = internal constant [4 x i8] c"%d\0A\00" ; <[4 x i8]*> [#uses=1] diff --git a/test/CodeGen/PowerPC/2008-09-12-CoalescerBug.ll b/test/CodeGen/PowerPC/2008-09-12-CoalescerBug.ll index b625ceb..97844dd 100644 --- a/test/CodeGen/PowerPC/2008-09-12-CoalescerBug.ll +++ b/test/CodeGen/PowerPC/2008-09-12-CoalescerBug.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -mtriple=powerpc-apple-darwin +; RUN: llc < %s -mtriple=powerpc-apple-darwin %struct.CGLDI = type { %struct.cgli*, i32, i32, i32, i32, i32, i8*, i32, void (%struct.CGLSI*, i32, %struct.CGLDI*)*, i8*, %struct.vv_t } %struct.cgli = type { i32, %struct.cgli*, void (%struct.cgli*, i8*, i8*, i32, i32, i32, i32, i32, i32, i32, i32)*, i32, i8*, i8*, i8*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, i8*, i32*, %struct._cgro*, %struct._cgro*, float, float, float, float, i32, i8*, float, i8*, [16 x i32] } diff --git a/test/CodeGen/PowerPC/2008-10-17-AsmMatchingOperands.ll b/test/CodeGen/PowerPC/2008-10-17-AsmMatchingOperands.ll index 00ca811..91c36ef 100644 --- a/test/CodeGen/PowerPC/2008-10-17-AsmMatchingOperands.ll +++ b/test/CodeGen/PowerPC/2008-10-17-AsmMatchingOperands.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc +; RUN: llc < %s ; XFAIL: * ; PR2356 target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128" diff --git a/test/CodeGen/PowerPC/2008-10-28-UnprocessedNode.ll b/test/CodeGen/PowerPC/2008-10-28-UnprocessedNode.ll index c760b41..f474a6d 100644 --- a/test/CodeGen/PowerPC/2008-10-28-UnprocessedNode.ll +++ b/test/CodeGen/PowerPC/2008-10-28-UnprocessedNode.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc64 +; RUN: llc < %s -march=ppc64 define void @__divtc3({ ppc_fp128, ppc_fp128 }* noalias sret %agg.result, ppc_fp128 %a, ppc_fp128 %b, ppc_fp128 %c, ppc_fp128 %d) nounwind { entry: diff --git a/test/CodeGen/PowerPC/2008-10-28-f128-i32.ll b/test/CodeGen/PowerPC/2008-10-28-f128-i32.ll index 071c788..f4c06fb 100644 --- a/test/CodeGen/PowerPC/2008-10-28-f128-i32.ll +++ b/test/CodeGen/PowerPC/2008-10-28-f128-i32.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc32 -o - | not grep fixunstfsi +; RUN: llc < %s -march=ppc32 -o - | not grep fixunstfsi define i64 @__fixunstfdi(ppc_fp128 %a) nounwind readnone { entry: diff --git a/test/CodeGen/PowerPC/2008-10-30-IllegalShift.ll b/test/CodeGen/PowerPC/2008-10-30-IllegalShift.ll index af9a54e..83f3f6f 100644 --- a/test/CodeGen/PowerPC/2008-10-30-IllegalShift.ll +++ b/test/CodeGen/PowerPC/2008-10-30-IllegalShift.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc32 +; RUN: llc < %s -march=ppc32 ; PR2986 @argc = external global i32 ; <i32*> [#uses=1] @buffer = external global [32 x i8], align 4 ; <[32 x i8]*> [#uses=1] diff --git a/test/CodeGen/PowerPC/2008-10-31-PPCF128Libcalls.ll b/test/CodeGen/PowerPC/2008-10-31-PPCF128Libcalls.ll index 0ad5b06..20683b9 100644 --- a/test/CodeGen/PowerPC/2008-10-31-PPCF128Libcalls.ll +++ b/test/CodeGen/PowerPC/2008-10-31-PPCF128Libcalls.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc +; RUN: llc < %s ; PR2988 target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128" target triple = "powerpc-apple-darwin10.0" diff --git a/test/CodeGen/PowerPC/2008-12-02-LegalizeTypeAssert.ll b/test/CodeGen/PowerPC/2008-12-02-LegalizeTypeAssert.ll index f5b3e93..9ed7f6f 100644 --- a/test/CodeGen/PowerPC/2008-12-02-LegalizeTypeAssert.ll +++ b/test/CodeGen/PowerPC/2008-12-02-LegalizeTypeAssert.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -mtriple=powerpc64-apple-darwin9.5 +; RUN: llc < %s -mtriple=powerpc64-apple-darwin9.5 define void @__multc3({ ppc_fp128, ppc_fp128 }* noalias sret %agg.result, ppc_fp128 %a, ppc_fp128 %b, ppc_fp128 %c, ppc_fp128 %d) nounwind { entry: diff --git a/test/CodeGen/PowerPC/2008-12-12-EH.ll b/test/CodeGen/PowerPC/2008-12-12-EH.ll index 21218f5..b56c22a 100644 --- a/test/CodeGen/PowerPC/2008-12-12-EH.ll +++ b/test/CodeGen/PowerPC/2008-12-12-EH.ll @@ -1,5 +1,5 @@ -; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-unknown-linux-gnu | grep ^.L_Z1fv.eh -; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-apple-darwin9 | grep ^__Z1fv.eh +; RUN: llc < %s -march=ppc32 -mtriple=powerpc-unknown-linux-gnu | grep ^.L_Z1fv.eh +; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin9 | grep ^__Z1fv.eh define void @_Z1fv() { entry: diff --git a/test/CodeGen/PowerPC/2009-01-16-DeclareISelBug.ll b/test/CodeGen/PowerPC/2009-01-16-DeclareISelBug.ll index 0cf5518..d49d58d 100644 --- a/test/CodeGen/PowerPC/2009-01-16-DeclareISelBug.ll +++ b/test/CodeGen/PowerPC/2009-01-16-DeclareISelBug.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -mtriple=powerpc-apple-darwin9.5 +; RUN: llc < %s -mtriple=powerpc-apple-darwin9.5 ; rdar://6499616 %llvm.dbg.anchor.type = type { i32, i32 } diff --git a/test/CodeGen/PowerPC/2009-03-17-LSRBug.ll b/test/CodeGen/PowerPC/2009-03-17-LSRBug.ll index a898de0..172531e 100644 --- a/test/CodeGen/PowerPC/2009-03-17-LSRBug.ll +++ b/test/CodeGen/PowerPC/2009-03-17-LSRBug.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -mtriple=powerpc-apple-darwin10 +; RUN: llc < %s -mtriple=powerpc-apple-darwin10 ; rdar://6692215 define fastcc void @_qsort(i8* %a, i32 %n, i32 %es, i32 (i8*, i8*)* %cmp, i32 %depth_limit) nounwind optsize ssp { diff --git a/test/CodeGen/PowerPC/2009-05-28-LegalizeBRCC.ll b/test/CodeGen/PowerPC/2009-05-28-LegalizeBRCC.ll index 4ea43ec..29d115d 100644 --- a/test/CodeGen/PowerPC/2009-05-28-LegalizeBRCC.ll +++ b/test/CodeGen/PowerPC/2009-05-28-LegalizeBRCC.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -mtriple=powerpc-apple-darwin10 +; RUN: llc < %s -mtriple=powerpc-apple-darwin10 ; PR4280 define i32 @__fixunssfsi(float %a) nounwind readnone { diff --git a/test/CodeGen/PowerPC/2009-07-16-InlineAsm-M-Operand.ll b/test/CodeGen/PowerPC/2009-07-16-InlineAsm-M-Operand.ll new file mode 100644 index 0000000..f64e3dc --- /dev/null +++ b/test/CodeGen/PowerPC/2009-07-16-InlineAsm-M-Operand.ll @@ -0,0 +1,16 @@ +; RUN: llc < %s -march=ppc32 -verify-machineinstrs + +; Machine code verifier will call isRegTiedToDefOperand() on /all/ register use +; operands. We must make sure that the operand flag is found correctly. + +; This test case is actually not specific to PowerPC, but the (imm, reg) format +; of PowerPC "m" operands trigger this bug. + +define void @memory_asm_operand(i32 %a) { + ; "m" operand will be represented as: + ; INLINEASM <es:fake $0>, 10, %R2, 20, -4, %R1 + ; It is difficult to find the flag operand (20) when starting from %R1 + call i32 asm "lbzx $0, $1", "=r,m" (i32 %a) + ret void +} + diff --git a/test/CodeGen/PowerPC/2009-08-17-inline-asm-addr-mode-breakage.ll b/test/CodeGen/PowerPC/2009-08-17-inline-asm-addr-mode-breakage.ll new file mode 100644 index 0000000..5d09696 --- /dev/null +++ b/test/CodeGen/PowerPC/2009-08-17-inline-asm-addr-mode-breakage.ll @@ -0,0 +1,25 @@ +; RUN: llc < %s -march=ppc32 | FileCheck %s +; ModuleID = '<stdin>' +target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128" +target triple = "powerpc-apple-darwin10.0" +; It is wrong on powerpc to substitute reg+reg for $0; the stw opcode +; would have to change. + +@x = external global [0 x i32] ; <[0 x i32]*> [#uses=1] + +define void @foo(i32 %y) nounwind ssp { +entry: +; CHECK: foo +; CHECK: add r2 +; CHECK: 0(r2) + %y_addr = alloca i32 ; <i32*> [#uses=2] + %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] + store i32 %y, i32* %y_addr + %0 = load i32* %y_addr, align 4 ; <i32> [#uses=1] + %1 = getelementptr inbounds [0 x i32]* @x, i32 0, i32 %0 ; <i32*> [#uses=1] + call void asm sideeffect "isync\0A\09eieio\0A\09stw $1, $0", "=*o,r,~{memory}"(i32* %1, i32 0) nounwind + br label %return + +return: ; preds = %entry + ret void +} diff --git a/test/CodeGen/PowerPC/2009-08-23-linkerprivate.ll b/test/CodeGen/PowerPC/2009-08-23-linkerprivate.ll new file mode 100644 index 0000000..12c4c99 --- /dev/null +++ b/test/CodeGen/PowerPC/2009-08-23-linkerprivate.ll @@ -0,0 +1,8 @@ +; RUN: llc < %s -march=ppc32 -mtriple=ppc-apple-darwin | FileCheck %s + +; ModuleID = '/Volumes/MacOS9/tests/WebKit/JavaScriptCore/profiler/ProfilerServer.mm' + +@"\01l_objc_msgSend_fixup_alloc" = linker_private hidden global i32 0, section "__DATA, __objc_msgrefs, coalesced", align 16 ; <i32*> [#uses=0] + +; CHECK: .globl l_objc_msgSend_fixup_alloc +; CHECK: .weak_definition l_objc_msgSend_fixup_alloc diff --git a/test/CodeGen/PowerPC/2009-09-18-carrybit.ll b/test/CodeGen/PowerPC/2009-09-18-carrybit.ll new file mode 100644 index 0000000..6c23a61 --- /dev/null +++ b/test/CodeGen/PowerPC/2009-09-18-carrybit.ll @@ -0,0 +1,62 @@ +; RUN: llc -march=ppc32 < %s | FileCheck %s +; ModuleID = '<stdin>' +target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128" +target triple = "powerpc-apple-darwin9.6" + +define i64 @foo(i64 %r.0.ph, i64 %q.0.ph, i32 %sr1.1.ph) nounwind { +entry: +; CHECK: foo: +; CHECK: subfc +; CHECK: subfe +; CHECK: subfc +; CHECK: subfe + %tmp0 = add i64 %r.0.ph, -1 ; <i64> [#uses=1] + br label %bb40 + +bb40: ; preds = %bb40, %entry + %indvar = phi i32 [ 0, %entry ], [ %indvar.next, %bb40 ] ; <i32> [#uses=1] + %carry.0274 = phi i32 [ 0, %entry ], [%tmp122, %bb40 ] ; <i32> [#uses=1] + %r.0273 = phi i64 [ %r.0.ph, %entry ], [ %tmp124, %bb40 ] ; <i64> [#uses=2] + %q.0272 = phi i64 [ %q.0.ph, %entry ], [ %ins169, %bb40 ] ; <i64> [#uses=3] + %tmp1 = lshr i64 %r.0273, 31 ; <i64> [#uses=1] + %tmp2 = trunc i64 %tmp1 to i32 ; <i32> [#uses=1] + %tmp3 = and i32 %tmp2, -2 ; <i32> [#uses=1] + %tmp213 = trunc i64 %r.0273 to i32 ; <i32> [#uses=2] + %tmp106 = lshr i32 %tmp213, 31 ; <i32> [#uses=1] + %tmp107 = or i32 %tmp3, %tmp106 ; <i32> [#uses=1] + %tmp215 = zext i32 %tmp107 to i64 ; <i64> [#uses=1] + %tmp216 = shl i64 %tmp215, 32 ; <i64> [#uses=1] + %tmp108 = shl i32 %tmp213, 1 ; <i32> [#uses=1] + %tmp109 = lshr i64 %q.0272, 63 ; <i64> [#uses=1] + %tmp110 = trunc i64 %tmp109 to i32 ; <i32> [#uses=1] + %tmp111 = or i32 %tmp108, %tmp110 ; <i32> [#uses=1] + %tmp222 = zext i32 %tmp111 to i64 ; <i64> [#uses=1] + %ins224 = or i64 %tmp216, %tmp222 ; <i64> [#uses=2] + %tmp112 = lshr i64 %q.0272, 31 ; <i64> [#uses=1] + %tmp113 = trunc i64 %tmp112 to i32 ; <i32> [#uses=1] + %tmp114 = and i32 %tmp113, -2 ; <i32> [#uses=1] + %tmp158 = trunc i64 %q.0272 to i32 ; <i32> [#uses=2] + %tmp115 = lshr i32 %tmp158, 31 ; <i32> [#uses=1] + %tmp116 = or i32 %tmp114, %tmp115 ; <i32> [#uses=1] + %tmp160 = zext i32 %tmp116 to i64 ; <i64> [#uses=1] + %tmp161 = shl i64 %tmp160, 32 ; <i64> [#uses=1] + %tmp117 = shl i32 %tmp158, 1 ; <i32> [#uses=1] + %tmp118 = or i32 %tmp117, %carry.0274 ; <i32> [#uses=1] + %tmp167 = zext i32 %tmp118 to i64 ; <i64> [#uses=1] + %ins169 = or i64 %tmp161, %tmp167 ; <i64> [#uses=2] + %tmp119 = sub i64 %tmp0, %ins224 ; <i64> [#uses=1] + %tmp120 = ashr i64 %tmp119, 63 ; <i64> [#uses=2] + %tmp121 = trunc i64 %tmp120 to i32 ; <i32> [#uses=1] + %tmp122 = and i32 %tmp121, 1 ; <i32> [#uses=2] + %tmp123 = and i64 %tmp120, %q.0.ph ; <i64> [#uses=1] + %tmp124 = sub i64 %ins224, %tmp123 ; <i64> [#uses=2] + %indvar.next = add i32 %indvar, 1 ; <i32> [#uses=2] + %exitcond = icmp eq i32 %indvar.next, %sr1.1.ph ; <i1> [#uses=1] + br i1 %exitcond, label %bb41.bb42_crit_edge, label %bb40 + +bb41.bb42_crit_edge: ; preds = %bb40 + %phitmp278 = zext i32 %tmp122 to i64 ; <i64> [#uses=1] + %tmp125 = shl i64 %ins169, 1 ; <i64> [#uses=1] + %tmp126 = or i64 %phitmp278, %tmp125 ; <i64> [#uses=2] + ret i64 %tmp126 +} diff --git a/test/CodeGen/PowerPC/Atomics-32.ll b/test/CodeGen/PowerPC/Atomics-32.ll index f3246fd..03905a3 100644 --- a/test/CodeGen/PowerPC/Atomics-32.ll +++ b/test/CodeGen/PowerPC/Atomics-32.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc32 +; RUN: llc < %s -march=ppc32 ; ModuleID = 'Atomics.c' target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128" target triple = "powerpc-apple-darwin9" diff --git a/test/CodeGen/PowerPC/Atomics-64.ll b/test/CodeGen/PowerPC/Atomics-64.ll index c3de710..1dc4310 100644 --- a/test/CodeGen/PowerPC/Atomics-64.ll +++ b/test/CodeGen/PowerPC/Atomics-64.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc64 +; RUN: llc < %s -march=ppc64 ; ModuleID = 'Atomics.c' target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128" target triple = "powerpc64-apple-darwin9" diff --git a/test/CodeGen/PowerPC/Frames-alloca.ll b/test/CodeGen/PowerPC/Frames-alloca.ll index 45c13a7..25fc626 100644 --- a/test/CodeGen/PowerPC/Frames-alloca.ll +++ b/test/CodeGen/PowerPC/Frames-alloca.ll @@ -1,35 +1,28 @@ -; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-apple-darwin8 | \ -; RUN: grep {stw r31, 20(r1)} -; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-apple-darwin8 -enable-ppc32-regscavenger | \ -; RUN: grep {stwu r1, -80(r1)} -; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-apple-darwin8 | \ -; RUN: grep {lwz r1, 0(r1)} -; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-apple-darwin8 | \ -; RUN: grep {lwz r31, 20(r1)} -; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | \ -; RUN: grep {stw r31, 20(r1)} -; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-apple-darwin8 -disable-fp-elim -enable-ppc32-regscavenger | \ -; RUN: grep {stwu r1, -80(r1)} -; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | \ -; RUN: grep {lwz r1, 0(r1)} -; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | \ -; RUN: grep {lwz r31, 20(r1)} -; RUN: llvm-as < %s | llc -march=ppc64 -mtriple=powerpc-apple-darwin8 | \ -; RUN: grep {std r31, 40(r1)} -; RUN: llvm-as < %s | llc -march=ppc64 -mtriple=powerpc-apple-darwin8 | \ -; RUN: grep {stdu r1, -112(r1)} -; RUN: llvm-as < %s | llc -march=ppc64 -mtriple=powerpc-apple-darwin8 | \ -; RUN: grep {ld r1, 0(r1)} -; RUN: llvm-as < %s | llc -march=ppc64 -mtriple=powerpc-apple-darwin8 | \ -; RUN: grep {ld r31, 40(r1)} -; RUN: llvm-as < %s | llc -march=ppc64 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | \ -; RUN: grep {std r31, 40(r1)} -; RUN: llvm-as < %s | llc -march=ppc64 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | \ -; RUN: grep {stdu r1, -112(r1)} -; RUN: llvm-as < %s | llc -march=ppc64 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | \ -; RUN: grep {ld r1, 0(r1)} -; RUN: llvm-as < %s | llc -march=ppc64 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | \ -; RUN: grep {ld r31, 40(r1)} +; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 | FileCheck %s -check-prefix=PPC32 +; RUN: llc < %s -march=ppc64 -mtriple=powerpc-apple-darwin8 | FileCheck %s -check-prefix=PPC64 +; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | FileCheck %s -check-prefix=PPC32-NOFP +; RUN: llc < %s -march=ppc64 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | FileCheck %s -check-prefix=PPC64-NOFP +; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -enable-ppc32-regscavenger | FileCheck %s -check-prefix=PPC32 +; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -enable-ppc32-regscavenger | FileCheck %s -check-prefix=PPC32-RS +; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -disable-fp-elim -enable-ppc32-regscavenger | FileCheck %s -check-prefix=PPC32-RS-NOFP + +; CHECK-PPC32: stw r31, 20(r1) +; CHECK-PPC32: lwz r1, 0(r1) +; CHECK-PPC32: lwz r31, 20(r1) +; CHECK-PPC32-NOFP: stw r31, 20(r1) +; CHECK-PPC32-NOFP: lwz r1, 0(r1) +; CHECK-PPC32-NOFP: lwz r31, 20(r1) +; CHECK-PPC32-RS: stwu r1, -80(r1) +; CHECK-PPC32-RS-NOFP: stwu r1, -80(r1) + +; CHECK-PPC64: std r31, 40(r1) +; CHECK-PPC64: stdu r1, -112(r1) +; CHECK-PPC64: ld r1, 0(r1) +; CHECK-PPC64: ld r31, 40(r1) +; CHECK-PPC64-NOFP: std r31, 40(r1) +; CHECK-PPC64-NOFP: stdu r1, -112(r1) +; CHECK-PPC64-NOFP: ld r1, 0(r1) +; CHECK-PPC64-NOFP: ld r31, 40(r1) define i32* @f1(i32 %n) { %tmp = alloca i32, i32 %n ; <i32*> [#uses=1] diff --git a/test/CodeGen/PowerPC/Frames-large.ll b/test/CodeGen/PowerPC/Frames-large.ll index 0a15d22..fda2e4f 100644 --- a/test/CodeGen/PowerPC/Frames-large.ll +++ b/test/CodeGen/PowerPC/Frames-large.ll @@ -1,77 +1,52 @@ -; RUN: llvm-as < %s | \ -; RUN: llc -march=ppc32 -mtriple=powerpc-apple-darwin8 | \ -; RUN: not grep {stw r31, 20(r1)} -; RUN: llvm-as < %s | \ -; RUN: llc -march=ppc32 -mtriple=powerpc-apple-darwin8 | grep {lis r0, -1} -; RUN: llvm-as < %s | \ -; RUN: llc -march=ppc32 -mtriple=powerpc-apple-darwin8 | \ -; RUN: grep {ori r0, r0, 32704} -; RUN: llvm-as < %s | \ -; RUN: llc -march=ppc32 -mtriple=powerpc-apple-darwin8 | \ -; RUN: grep {stwux r1, r1, r0} -; RUN: llvm-as < %s | \ -; RUN: llc -march=ppc32 -mtriple=powerpc-apple-darwin8 | \ -; RUN: grep {lwz r1, 0(r1)} -; RUN: llvm-as < %s | \ -; RUN: llc -march=ppc32 -mtriple=powerpc-apple-darwin8 | \ -; RUN: not grep {lwz r31, 20(r1)} -; RUN: llvm-as < %s | \ -; RUN: llc -march=ppc32 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | \ -; RUN: grep {stw r31, 20(r1)} -; RUN: llvm-as < %s | \ -; RUN: llc -march=ppc32 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | \ -; RUN: grep {lis r0, -1} -; RUN: llvm-as < %s | \ -; RUN: llc -march=ppc32 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | \ -; RUN: grep {ori r0, r0, 32704} -; RUN: llvm-as < %s | \ -; RUN: llc -march=ppc32 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | \ -; RUN: grep {stwux r1, r1, r0} -; RUN: llvm-as < %s | \ -; RUN: llc -march=ppc32 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | \ -; RUN: grep {lwz r1, 0(r1)} -; RUN: llvm-as < %s | \ -; RUN: llc -march=ppc32 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | \ -; RUN: grep {lwz r31, 20(r1)} -; RUN: llvm-as < %s | \ -; RUN: llc -march=ppc64 -mtriple=powerpc-apple-darwin8 | \ -; RUN: not grep {std r31, 40(r1)} -; RUN: llvm-as < %s | \ -; RUN: llc -march=ppc64 -mtriple=powerpc-apple-darwin8 | \ -; RUN: grep {lis r0, -1} -; RUN: llvm-as < %s | \ -; RUN: llc -march=ppc64 -mtriple=powerpc-apple-darwin8 | \ -; RUN: grep {ori r0, r0, 32656} -; RUN: llvm-as < %s | \ -; RUN: llc -march=ppc64 -mtriple=powerpc-apple-darwin8 | \ -; RUN: grep {stdux r1, r1, r0} -; RUN: llvm-as < %s | \ -; RUN: llc -march=ppc64 -mtriple=powerpc-apple-darwin8 | \ -; RUN: grep {ld r1, 0(r1)} -; RUN: llvm-as < %s | \ -; RUN: llc -march=ppc64 -mtriple=powerpc-apple-darwin8 | \ -; RUN: not grep {ld r31, 40(r1)} -; RUN: llvm-as < %s | \ -; RUN: llc -march=ppc64 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | \ -; RUN: grep {std r31, 40(r1)} -; RUN: llvm-as < %s | \ -; RUN: llc -march=ppc64 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | \ -; RUN: grep {lis r0, -1} -; RUN: llvm-as < %s | \ -; RUN: llc -march=ppc64 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | \ -; RUN: grep {ori r0, r0, 32656} -; RUN: llvm-as < %s | \ -; RUN: llc -march=ppc64 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | \ -; RUN: grep {stdux r1, r1, r0} -; RUN: llvm-as < %s | \ -; RUN: llc -march=ppc64 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | \ -; RUN: grep {ld r1, 0(r1)} -; RUN: llvm-as < %s | \ -; RUN: llc -march=ppc64 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | \ -; RUN: grep {ld r31, 40(r1)} +; RUN: llvm-as < %s > %t.bc +; RUN: llc < %t.bc -march=ppc32 | FileCheck %s -check-prefix=PPC32-NOFP +; RUN: llc < %t.bc -march=ppc32 -disable-fp-elim | FileCheck %s -check-prefix=PPC32-FP -define i32* @f1() { +; RUN: llc < %t.bc -march=ppc64 | FileCheck %s -check-prefix=PPC64-NOFP +; RUN: llc < %t.bc -march=ppc64 -disable-fp-elim | FileCheck %s -check-prefix=PPC64-FP + + +target triple = "powerpc-apple-darwin8" + +define i32* @f1() nounwind { %tmp = alloca i32, i32 8191 ; <i32*> [#uses=1] ret i32* %tmp } +; PPC32-NOFP: _f1: +; PPC32-NOFP: lis r0, -1 +; PPC32-NOFP: ori r0, r0, 32704 +; PPC32-NOFP: stwux r1, r1, r0 +; PPC32-NOFP: addi r3, r1, 68 +; PPC32-NOFP: lwz r1, 0(r1) +; PPC32-NOFP: blr + +; PPC32-FP: _f1: +; PPC32-FP: stw r31, 20(r1) +; PPC32-FP: lis r0, -1 +; PPC32-FP: ori r0, r0, 32704 +; PPC32-FP: stwux r1, r1, r0 +; ... +; PPC32-FP: lwz r1, 0(r1) +; PPC32-FP: lwz r31, 20(r1) +; PPC32-FP: blr + + +; PPC64-NOFP: _f1: +; PPC64-NOFP: lis r0, -1 +; PPC64-NOFP: ori r0, r0, 32656 +; PPC64-NOFP: stdux r1, r1, r0 +; PPC64-NOFP: addi r3, r1, 116 +; PPC64-NOFP: ld r1, 0(r1) +; PPC64-NOFP: blr + + +; PPC64-FP: _f1: +; PPC64-FP: std r31, 40(r1) +; PPC64-FP: lis r0, -1 +; PPC64-FP: ori r0, r0, 32656 +; PPC64-FP: stdux r1, r1, r0 +; ... +; PPC64-FP: ld r1, 0(r1) +; PPC64-FP: ld r31, 40(r1) +; PPC64-FP: blr diff --git a/test/CodeGen/PowerPC/Frames-leaf.ll b/test/CodeGen/PowerPC/Frames-leaf.ll index 11b64703..c2e1d6b 100644 --- a/test/CodeGen/PowerPC/Frames-leaf.ll +++ b/test/CodeGen/PowerPC/Frames-leaf.ll @@ -1,34 +1,34 @@ -; RUN: llvm-as < %s | llc -march=ppc32 | \ +; RUN: llc < %s -march=ppc32 | \ ; RUN: not grep {stw r31, 20(r1)} -; RUN: llvm-as < %s | llc -march=ppc32 | \ +; RUN: llc < %s -march=ppc32 | \ ; RUN: not grep {stwu r1, -.*(r1)} -; RUN: llvm-as < %s | llc -march=ppc32 | \ +; RUN: llc < %s -march=ppc32 | \ ; RUN: not grep {addi r1, r1, } -; RUN: llvm-as < %s | llc -march=ppc32 | \ +; RUN: llc < %s -march=ppc32 | \ ; RUN: not grep {lwz r31, 20(r1)} -; RUN: llvm-as < %s | llc -march=ppc32 -disable-fp-elim | \ +; RUN: llc < %s -march=ppc32 -disable-fp-elim | \ ; RUN: not grep {stw r31, 20(r1)} -; RUN: llvm-as < %s | llc -march=ppc32 -disable-fp-elim | \ +; RUN: llc < %s -march=ppc32 -disable-fp-elim | \ ; RUN: not grep {stwu r1, -.*(r1)} -; RUN: llvm-as < %s | llc -march=ppc32 -disable-fp-elim | \ +; RUN: llc < %s -march=ppc32 -disable-fp-elim | \ ; RUN: not grep {addi r1, r1, } -; RUN: llvm-as < %s | llc -march=ppc32 -disable-fp-elim | \ +; RUN: llc < %s -march=ppc32 -disable-fp-elim | \ ; RUN: not grep {lwz r31, 20(r1)} -; RUN: llvm-as < %s | llc -march=ppc64 | \ +; RUN: llc < %s -march=ppc64 | \ ; RUN: not grep {std r31, 40(r1)} -; RUN: llvm-as < %s | llc -march=ppc64 | \ +; RUN: llc < %s -march=ppc64 | \ ; RUN: not grep {stdu r1, -.*(r1)} -; RUN: llvm-as < %s | llc -march=ppc64 | \ +; RUN: llc < %s -march=ppc64 | \ ; RUN: not grep {addi r1, r1, } -; RUN: llvm-as < %s | llc -march=ppc64 | \ +; RUN: llc < %s -march=ppc64 | \ ; RUN: not grep {ld r31, 40(r1)} -; RUN: llvm-as < %s | llc -march=ppc64 -disable-fp-elim | \ +; RUN: llc < %s -march=ppc64 -disable-fp-elim | \ ; RUN: not grep {stw r31, 40(r1)} -; RUN: llvm-as < %s | llc -march=ppc64 -disable-fp-elim | \ +; RUN: llc < %s -march=ppc64 -disable-fp-elim | \ ; RUN: not grep {stdu r1, -.*(r1)} -; RUN: llvm-as < %s | llc -march=ppc64 -disable-fp-elim | \ +; RUN: llc < %s -march=ppc64 -disable-fp-elim | \ ; RUN: not grep {addi r1, r1, } -; RUN: llvm-as < %s | llc -march=ppc64 -disable-fp-elim | \ +; RUN: llc < %s -march=ppc64 -disable-fp-elim | \ ; RUN: not grep {ld r31, 40(r1)} define i32* @f1() { diff --git a/test/CodeGen/PowerPC/Frames-small.ll b/test/CodeGen/PowerPC/Frames-small.ll index 4ea3afb..6875704 100644 --- a/test/CodeGen/PowerPC/Frames-small.ll +++ b/test/CodeGen/PowerPC/Frames-small.ll @@ -1,26 +1,22 @@ -; RUN: llvm-as < %s | \ -; RUN: llc -march=ppc32 -mtriple=powerpc-apple-darwin8 -o %t1 -f +; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -o %t1 ; RUN not grep {stw r31, 20(r1)} %t1 ; RUN: grep {stwu r1, -16448(r1)} %t1 ; RUN: grep {addi r1, r1, 16448} %t1 -; RUN: llvm-as < %s | \ +; RUN: llc < %s -march=ppc32 | \ ; RUN: not grep {lwz r31, 20(r1)} -; RUN: llvm-as < %s | \ -; RUN: llc -march=ppc32 -mtriple=powerpc-apple-darwin8 -disable-fp-elim \ -; RUN: -o %t2 -f +; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -disable-fp-elim \ +; RUN: -o %t2 ; RUN: grep {stw r31, 20(r1)} %t2 ; RUN: grep {stwu r1, -16448(r1)} %t2 ; RUN: grep {addi r1, r1, 16448} %t2 ; RUN: grep {lwz r31, 20(r1)} %t2 -; RUN: llvm-as < %s | \ -; RUN: llc -march=ppc64 -mtriple=powerpc-apple-darwin8 -o %t3 -f +; RUN: llc < %s -march=ppc64 -mtriple=powerpc-apple-darwin8 -o %t3 ; RUN: not grep {std r31, 40(r1)} %t3 ; RUN: grep {stdu r1, -16496(r1)} %t3 ; RUN: grep {addi r1, r1, 16496} %t3 ; RUN: not grep {ld r31, 40(r1)} %t3 -; RUN: llvm-as < %s | \ -; RUN: llc -march=ppc64 -mtriple=powerpc-apple-darwin8 -disable-fp-elim \ -; RUN: -o %t4 -f +; RUN: llc < %s -march=ppc64 -mtriple=powerpc-apple-darwin8 -disable-fp-elim \ +; RUN: -o %t4 ; RUN: grep {std r31, 40(r1)} %t4 ; RUN: grep {stdu r1, -16496(r1)} %t4 ; RUN: grep {addi r1, r1, 16496} %t4 diff --git a/test/CodeGen/PowerPC/LargeAbsoluteAddr.ll b/test/CodeGen/PowerPC/LargeAbsoluteAddr.ll index 1705379..0f7acac 100644 --- a/test/CodeGen/PowerPC/LargeAbsoluteAddr.ll +++ b/test/CodeGen/PowerPC/LargeAbsoluteAddr.ll @@ -1,8 +1,8 @@ -; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-apple-darwin | \ +; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin | \ ; RUN: grep {stw r3, 32751} -; RUN: llvm-as < %s | llc -march=ppc64 -mtriple=powerpc-apple-darwin | \ +; RUN: llc < %s -march=ppc64 -mtriple=powerpc-apple-darwin | \ ; RUN: grep {stw r3, 32751} -; RUN: llvm-as < %s | llc -march=ppc64 -mtriple=powerpc-apple-darwin | \ +; RUN: llc < %s -march=ppc64 -mtriple=powerpc-apple-darwin | \ ; RUN: grep {std r2, 9024} define void @test() { diff --git a/test/CodeGen/PowerPC/addc.ll b/test/CodeGen/PowerPC/addc.ll index 406053b..09a7fbd 100644 --- a/test/CodeGen/PowerPC/addc.ll +++ b/test/CodeGen/PowerPC/addc.ll @@ -1,5 +1,5 @@ ; All of these should be codegen'd without loading immediates -; RUN: llvm-as < %s | llc -march=ppc32 -o %t -f +; RUN: llc < %s -march=ppc32 -o %t ; RUN: grep addc %t | count 1 ; RUN: grep adde %t | count 1 ; RUN: grep addze %t | count 1 diff --git a/test/CodeGen/PowerPC/addi-reassoc.ll b/test/CodeGen/PowerPC/addi-reassoc.ll index bee8660..2b71ce6 100644 --- a/test/CodeGen/PowerPC/addi-reassoc.ll +++ b/test/CodeGen/PowerPC/addi-reassoc.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc32 | not grep addi +; RUN: llc < %s -march=ppc32 | not grep addi %struct.X = type { [5 x i8] } diff --git a/test/CodeGen/PowerPC/align.ll b/test/CodeGen/PowerPC/align.ll index 7ffbe36..e619faa 100644 --- a/test/CodeGen/PowerPC/align.ll +++ b/test/CodeGen/PowerPC/align.ll @@ -1,8 +1,8 @@ -; RUN: llvm-as < %s | llc -march=ppc32 | \ +; RUN: llc < %s -march=ppc32 | \ ; RUN: grep align.4 | count 1 -; RUN: llvm-as < %s | llc -march=ppc32 | \ +; RUN: llc < %s -march=ppc32 | \ ; RUN: grep align.2 | count 1 -; RUN: llvm-as < %s | llc -march=ppc32 | \ +; RUN: llc < %s -march=ppc32 | \ ; RUN: grep align.3 | count 1 @A = global <4 x i32> < i32 10, i32 20, i32 30, i32 40 > ; <<4 x i32>*> [#uses=0] diff --git a/test/CodeGen/PowerPC/and-branch.ll b/test/CodeGen/PowerPC/and-branch.ll index f0bb5ea..0484f88 100644 --- a/test/CodeGen/PowerPC/and-branch.ll +++ b/test/CodeGen/PowerPC/and-branch.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc32 | not grep mfcr +; RUN: llc < %s -march=ppc32 | not grep mfcr define void @foo(i32 %X, i32 %Y, i32 %Z) { entry: diff --git a/test/CodeGen/PowerPC/and-elim.ll b/test/CodeGen/PowerPC/and-elim.ll index eef8f51..3685361 100644 --- a/test/CodeGen/PowerPC/and-elim.ll +++ b/test/CodeGen/PowerPC/and-elim.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc32 | not grep rlwin +; RUN: llc < %s -march=ppc32 | not grep rlwin define void @test(i8* %P) { %W = load i8* %P diff --git a/test/CodeGen/PowerPC/and-imm.ll b/test/CodeGen/PowerPC/and-imm.ll index 9c80649..64a45e5 100644 --- a/test/CodeGen/PowerPC/and-imm.ll +++ b/test/CodeGen/PowerPC/and-imm.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc32 | not grep {ori\\|lis} +; RUN: llc < %s -march=ppc32 | not grep {ori\\|lis} ; andi. r3, r3, 32769 define i32 @test(i32 %X) { diff --git a/test/CodeGen/PowerPC/and_add.ll b/test/CodeGen/PowerPC/and_add.ll index f103e7c..517e775 100644 --- a/test/CodeGen/PowerPC/and_add.ll +++ b/test/CodeGen/PowerPC/and_add.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc32 -o %t -f +; RUN: llc < %s -march=ppc32 -o %t ; RUN: grep slwi %t ; RUN: not grep addi %t ; RUN: not grep rlwinm %t diff --git a/test/CodeGen/PowerPC/and_sext.ll b/test/CodeGen/PowerPC/and_sext.ll index e0e498d..c6d234e 100644 --- a/test/CodeGen/PowerPC/and_sext.ll +++ b/test/CodeGen/PowerPC/and_sext.ll @@ -1,6 +1,6 @@ ; These tests should not contain a sign extend. -; RUN: llvm-as < %s | llc -march=ppc32 | not grep extsh -; RUN: llvm-as < %s | llc -march=ppc32 | not grep extsb +; RUN: llc < %s -march=ppc32 | not grep extsh +; RUN: llc < %s -march=ppc32 | not grep extsb define i32 @test1(i32 %mode.0.i.0) { %tmp.79 = trunc i32 %mode.0.i.0 to i16 diff --git a/test/CodeGen/PowerPC/and_sra.ll b/test/CodeGen/PowerPC/and_sra.ll index c780605..e6c02d8 100644 --- a/test/CodeGen/PowerPC/and_sra.ll +++ b/test/CodeGen/PowerPC/and_sra.ll @@ -1,5 +1,5 @@ ; Neither of these functions should contain algebraic right shifts -; RUN: llvm-as < %s | llc -march=ppc32 | not grep srawi +; RUN: llc < %s -march=ppc32 | not grep srawi define i32 @test1(i32 %mode.0.i.0) { %tmp.79 = bitcast i32 %mode.0.i.0 to i32 ; <i32> [#uses=1] diff --git a/test/CodeGen/PowerPC/atomic-1.ll b/test/CodeGen/PowerPC/atomic-1.ll index f6bb298..ec4e42d 100644 --- a/test/CodeGen/PowerPC/atomic-1.ll +++ b/test/CodeGen/PowerPC/atomic-1.ll @@ -1,5 +1,5 @@ -; RUN: llvm-as < %s | llc -march=ppc32 | grep lwarx | count 3 -; RUN: llvm-as < %s | llc -march=ppc32 | grep stwcx. | count 4 +; RUN: llc < %s -march=ppc32 | grep lwarx | count 3 +; RUN: llc < %s -march=ppc32 | grep stwcx. | count 4 define i32 @exchange_and_add(i32* %mem, i32 %val) nounwind { %tmp = call i32 @llvm.atomic.load.add.i32( i32* %mem, i32 %val ) diff --git a/test/CodeGen/PowerPC/atomic-2.ll b/test/CodeGen/PowerPC/atomic-2.ll index 77b7b08..6d9daef9 100644 --- a/test/CodeGen/PowerPC/atomic-2.ll +++ b/test/CodeGen/PowerPC/atomic-2.ll @@ -1,5 +1,5 @@ -; RUN: llvm-as < %s | llc -march=ppc64 | grep ldarx | count 3 -; RUN: llvm-as < %s | llc -march=ppc64 | grep stdcx. | count 4 +; RUN: llc < %s -march=ppc64 | grep ldarx | count 3 +; RUN: llc < %s -march=ppc64 | grep stdcx. | count 4 define i64 @exchange_and_add(i64* %mem, i64 %val) nounwind { %tmp = call i64 @llvm.atomic.load.add.i64( i64* %mem, i64 %val ) diff --git a/test/CodeGen/PowerPC/available-externally.ll b/test/CodeGen/PowerPC/available-externally.ll index cfad6ea..fdead7d 100644 --- a/test/CodeGen/PowerPC/available-externally.ll +++ b/test/CodeGen/PowerPC/available-externally.ll @@ -1,69 +1,71 @@ -; RUN: llvm-as < %s | llc | grep {bl L_exact_log2.stub} +; RUN: llc < %s -relocation-model=static | FileCheck %s -check-prefix=STATIC +; RUN: llc < %s -relocation-model=pic | FileCheck %s -check-prefix=PIC +; RUN: llc < %s -relocation-model=dynamic-no-pic | FileCheck %s -check-prefix=DYNAMIC ; PR4482 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" target triple = "powerpc-apple-darwin8" define i32 @foo(i64 %x) nounwind { entry: - %x_addr = alloca i64 ; <i64*> [#uses=2] - %retval = alloca i32 ; <i32*> [#uses=2] - %0 = alloca i32 ; <i32*> [#uses=2] - %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] - store i64 %x, i64* %x_addr - %1 = load i64* %x_addr, align 8 ; <i64> [#uses=1] - %2 = call i32 @exact_log2(i64 %1) nounwind ; <i32> [#uses=1] - store i32 %2, i32* %0, align 4 - %3 = load i32* %0, align 4 ; <i32> [#uses=1] - store i32 %3, i32* %retval, align 4 - br label %return - -return: ; preds = %entry - %retval1 = load i32* %retval ; <i32> [#uses=1] - ret i32 %retval1 +; STATIC: _foo: +; STATIC: bl _exact_log2 +; STATIC: blr +; STATIC: .subsections_via_symbols + +; PIC: _foo: +; PIC: bl L_exact_log2$stub +; PIC: blr + +; DYNAMIC: _foo: +; DYNAMIC: bl L_exact_log2$stub +; DYNAMIC: blr + + %A = call i32 @exact_log2(i64 %x) nounwind + ret i32 %A } define available_externally i32 @exact_log2(i64 %x) nounwind { entry: - %x_addr = alloca i64 ; <i64*> [#uses=6] - %retval = alloca i32 ; <i32*> [#uses=2] - %iftmp.0 = alloca i32 ; <i32*> [#uses=3] - %0 = alloca i32 ; <i32*> [#uses=2] - %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] - store i64 %x, i64* %x_addr - %1 = load i64* %x_addr, align 8 ; <i64> [#uses=1] - %2 = sub i64 0, %1 ; <i64> [#uses=1] - %3 = load i64* %x_addr, align 8 ; <i64> [#uses=1] - %4 = and i64 %2, %3 ; <i64> [#uses=1] - %5 = load i64* %x_addr, align 8 ; <i64> [#uses=1] - %6 = icmp ne i64 %4, %5 ; <i1> [#uses=1] - br i1 %6, label %bb2, label %bb - -bb: ; preds = %entry - %7 = load i64* %x_addr, align 8 ; <i64> [#uses=1] - %8 = icmp eq i64 %7, 0 ; <i1> [#uses=1] - br i1 %8, label %bb2, label %bb1 - -bb1: ; preds = %bb - %9 = load i64* %x_addr, align 8 ; <i64> [#uses=1] - %10 = call i64 @llvm.cttz.i64(i64 %9) ; <i64> [#uses=1] - %11 = trunc i64 %10 to i32 ; <i32> [#uses=1] - store i32 %11, i32* %iftmp.0, align 4 - br label %bb3 - -bb2: ; preds = %bb, %entry - store i32 -1, i32* %iftmp.0, align 4 - br label %bb3 - -bb3: ; preds = %bb2, %bb1 - %12 = load i32* %iftmp.0, align 4 ; <i32> [#uses=1] - store i32 %12, i32* %0, align 4 - %13 = load i32* %0, align 4 ; <i32> [#uses=1] - store i32 %13, i32* %retval, align 4 - br label %return - -return: ; preds = %bb3 - %retval4 = load i32* %retval ; <i32> [#uses=1] - ret i32 %retval4 + ret i32 42 } -declare i64 @llvm.cttz.i64(i64) nounwind readnone + +; PIC: .section __TEXT,__picsymbolstub1,symbol_stubs,pure_instructions,32 +; PIC: L_exact_log2$stub: +; PIC: .indirect_symbol _exact_log2 +; PIC: mflr r0 +; PIC: bcl 20,31,L_exact_log2$stub$tmp + +; PIC: L_exact_log2$stub$tmp: +; PIC: mflr r11 +; PIC: addis r11,r11,ha16(L_exact_log2$lazy_ptr-L_exact_log2$stub$tmp) +; PIC: mtlr r0 +; PIC: lwzu r12,lo16(L_exact_log2$lazy_ptr-L_exact_log2$stub$tmp)(r11) +; PIC: mtctr r12 +; PIC: bctr + +; PIC: .section __DATA,__la_symbol_ptr,lazy_symbol_pointers +; PIC: L_exact_log2$lazy_ptr: +; PIC: .indirect_symbol _exact_log2 +; PIC: .long dyld_stub_binding_helper + +; PIC: .subsections_via_symbols + + +; DYNAMIC: .section __TEXT,__symbol_stub1,symbol_stubs,pure_instructions,16 +; DYNAMIC: L_exact_log2$stub: +; DYNAMIC: .indirect_symbol _exact_log2 +; DYNAMIC: lis r11,ha16(L_exact_log2$lazy_ptr) +; DYNAMIC: lwzu r12,lo16(L_exact_log2$lazy_ptr)(r11) +; DYNAMIC: mtctr r12 +; DYNAMIC: bctr + +; DYNAMIC: .section __DATA,__la_symbol_ptr,lazy_symbol_pointers +; DYNAMIC: L_exact_log2$lazy_ptr: +; DYNAMIC: .indirect_symbol _exact_log2 +; DYNAMIC: .long dyld_stub_binding_helper + + + + + diff --git a/test/CodeGen/PowerPC/big-endian-actual-args.ll b/test/CodeGen/PowerPC/big-endian-actual-args.ll index d239357..009f468 100644 --- a/test/CodeGen/PowerPC/big-endian-actual-args.ll +++ b/test/CodeGen/PowerPC/big-endian-actual-args.ll @@ -1,6 +1,6 @@ -; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-unknown-linux-gnu | \ +; RUN: llc < %s -march=ppc32 -mtriple=powerpc-unknown-linux-gnu | \ ; RUN: grep {addc 4, 4, 6} -; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-unknown-linux-gnu | \ +; RUN: llc < %s -march=ppc32 -mtriple=powerpc-unknown-linux-gnu | \ ; RUN: grep {adde 3, 3, 5} define i64 @foo(i64 %x, i64 %y) { diff --git a/test/CodeGen/PowerPC/big-endian-call-result.ll b/test/CodeGen/PowerPC/big-endian-call-result.ll index ab136f6..fe85404 100644 --- a/test/CodeGen/PowerPC/big-endian-call-result.ll +++ b/test/CodeGen/PowerPC/big-endian-call-result.ll @@ -1,6 +1,6 @@ -; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-unknown-linux-gnu | \ +; RUN: llc < %s -march=ppc32 -mtriple=powerpc-unknown-linux-gnu | \ ; RUN: grep {addic 4, 4, 1} -; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-unknown-linux-gnu | \ +; RUN: llc < %s -march=ppc32 -mtriple=powerpc-unknown-linux-gnu | \ ; RUN: grep {addze 3, 3} declare i64 @foo() diff --git a/test/CodeGen/PowerPC/big-endian-formal-args.ll b/test/CodeGen/PowerPC/big-endian-formal-args.ll index 08589f4..e46e1ec 100644 --- a/test/CodeGen/PowerPC/big-endian-formal-args.ll +++ b/test/CodeGen/PowerPC/big-endian-formal-args.ll @@ -1,10 +1,10 @@ -; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-unknown-linux-gnu | \ +; RUN: llc < %s -march=ppc32 -mtriple=powerpc-unknown-linux-gnu | \ ; RUN: grep {li 6, 3} -; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-unknown-linux-gnu | \ +; RUN: llc < %s -march=ppc32 -mtriple=powerpc-unknown-linux-gnu | \ ; RUN: grep {li 4, 2} -; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-unknown-linux-gnu | \ +; RUN: llc < %s -march=ppc32 -mtriple=powerpc-unknown-linux-gnu | \ ; RUN: grep {li 3, 0} -; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-unknown-linux-gnu | \ +; RUN: llc < %s -march=ppc32 -mtriple=powerpc-unknown-linux-gnu | \ ; RUN: grep {mr 5, 3} declare void @bar(i64 %x, i64 %y) diff --git a/test/CodeGen/PowerPC/branch-opt.ll b/test/CodeGen/PowerPC/branch-opt.ll index 4aa55a3..cc02e40 100644 --- a/test/CodeGen/PowerPC/branch-opt.ll +++ b/test/CodeGen/PowerPC/branch-opt.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc32 | \ +; RUN: llc < %s -march=ppc32 | \ ; RUN: grep {b LBB.*} | count 4 target datalayout = "E-p:32:32" diff --git a/test/CodeGen/PowerPC/bswap-load-store.ll b/test/CodeGen/PowerPC/bswap-load-store.ll index e450eb8..7eb3bbb 100644 --- a/test/CodeGen/PowerPC/bswap-load-store.ll +++ b/test/CodeGen/PowerPC/bswap-load-store.ll @@ -1,11 +1,11 @@ -; RUN: llvm-as < %s | llc -march=ppc32 | \ +; RUN: llc < %s -march=ppc32 | \ ; RUN: grep {stwbrx\\|lwbrx\\|sthbrx\\|lhbrx} | count 4 -; RUN: llvm-as < %s | llc -march=ppc32 | not grep rlwinm -; RUN: llvm-as < %s | llc -march=ppc32 | not grep rlwimi -; RUN: llvm-as < %s | llc -march=ppc64 | \ +; RUN: llc < %s -march=ppc32 | not grep rlwinm +; RUN: llc < %s -march=ppc32 | not grep rlwimi +; RUN: llc < %s -march=ppc64 | \ ; RUN: grep {stwbrx\\|lwbrx\\|sthbrx\\|lhbrx} | count 4 -; RUN: llvm-as < %s | llc -march=ppc64 | not grep rlwinm -; RUN: llvm-as < %s | llc -march=ppc64 | not grep rlwimi +; RUN: llc < %s -march=ppc64 | not grep rlwinm +; RUN: llc < %s -march=ppc64 | not grep rlwimi define void @STWBRX(i32 %i, i8* %ptr, i32 %off) { %tmp1 = getelementptr i8* %ptr, i32 %off ; <i8*> [#uses=1] diff --git a/test/CodeGen/PowerPC/buildvec_canonicalize.ll b/test/CodeGen/PowerPC/buildvec_canonicalize.ll index 20ff3db..0454c58 100644 --- a/test/CodeGen/PowerPC/buildvec_canonicalize.ll +++ b/test/CodeGen/PowerPC/buildvec_canonicalize.ll @@ -1,11 +1,9 @@ ; There should be exactly one vxor here. -; RUN: llvm-as < %s | \ -; RUN: llc -march=ppc32 -mcpu=g5 --enable-unsafe-fp-math | \ +; RUN: llc < %s -march=ppc32 -mcpu=g5 --enable-unsafe-fp-math | \ ; RUN: grep vxor | count 1 ; There should be exactly one vsplti here. -; RUN: llvm-as < %s | \ -; RUN: llc -march=ppc32 -mcpu=g5 --enable-unsafe-fp-math | \ +; RUN: llc < %s -march=ppc32 -mcpu=g5 --enable-unsafe-fp-math | \ ; RUN: grep vsplti | count 1 define void @VXOR(<4 x float>* %P1, <4 x i32>* %P2, <4 x float>* %P3) { diff --git a/test/CodeGen/PowerPC/calls.ll b/test/CodeGen/PowerPC/calls.ll index 034c141..0db184f 100644 --- a/test/CodeGen/PowerPC/calls.ll +++ b/test/CodeGen/PowerPC/calls.ll @@ -1,10 +1,10 @@ ; Test various forms of calls. -; RUN: llvm-as < %s | llc -march=ppc32 | \ +; RUN: llc < %s -march=ppc32 | \ ; RUN: grep {bl } | count 2 -; RUN: llvm-as < %s | llc -march=ppc32 | \ +; RUN: llc < %s -march=ppc32 | \ ; RUN: grep {bctrl} | count 1 -; RUN: llvm-as < %s | llc -march=ppc32 | \ +; RUN: llc < %s -march=ppc32 | \ ; RUN: grep {bla } | count 1 declare void @foo() diff --git a/test/CodeGen/PowerPC/cmp-cmp.ll b/test/CodeGen/PowerPC/cmp-cmp.ll index 07964d5..35a5e42 100644 --- a/test/CodeGen/PowerPC/cmp-cmp.ll +++ b/test/CodeGen/PowerPC/cmp-cmp.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc32 | not grep mfcr +; RUN: llc < %s -march=ppc32 | not grep mfcr define void @test(i64 %X) { %tmp1 = and i64 %X, 3 ; <i64> [#uses=1] diff --git a/test/CodeGen/PowerPC/compare-duplicate.ll b/test/CodeGen/PowerPC/compare-duplicate.ll index df2dfdc..f5108c3 100644 --- a/test/CodeGen/PowerPC/compare-duplicate.ll +++ b/test/CodeGen/PowerPC/compare-duplicate.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -mtriple=powerpc-apple-darwin8 | not grep slwi +; RUN: llc < %s -mtriple=powerpc-apple-darwin8 | not grep slwi define i32 @test(i32 %A, i32 %B) { %C = sub i32 %B, %A diff --git a/test/CodeGen/PowerPC/compare-simm.ll b/test/CodeGen/PowerPC/compare-simm.ll index b0ef2d3..5ba0500 100644 --- a/test/CodeGen/PowerPC/compare-simm.ll +++ b/test/CodeGen/PowerPC/compare-simm.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-apple-darwin8 | \ +; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 | \ ; RUN: grep {cmpwi cr0, r3, -1} define i32 @test(i32 %x) { diff --git a/test/CodeGen/PowerPC/constants.ll b/test/CodeGen/PowerPC/constants.ll index b58f59a..8901e02 100644 --- a/test/CodeGen/PowerPC/constants.ll +++ b/test/CodeGen/PowerPC/constants.ll @@ -1,9 +1,9 @@ ; All of these routines should be perform optimal load of constants. -; RUN: llvm-as < %s | llc -march=ppc32 | \ +; RUN: llc < %s -march=ppc32 | \ ; RUN: grep lis | count 5 -; RUN: llvm-as < %s | llc -march=ppc32 | \ +; RUN: llc < %s -march=ppc32 | \ ; RUN: grep ori | count 3 -; RUN: llvm-as < %s | llc -march=ppc32 | \ +; RUN: llc < %s -march=ppc32 | \ ; RUN: grep {li } | count 4 define i32 @f1() { diff --git a/test/CodeGen/PowerPC/cr_spilling.ll b/test/CodeGen/PowerPC/cr_spilling.ll index 4584c71..b215868 100644 --- a/test/CodeGen/PowerPC/cr_spilling.ll +++ b/test/CodeGen/PowerPC/cr_spilling.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc32 -regalloc=local -O0 -relocation-model=pic -o - +; RUN: llc < %s -march=ppc32 -regalloc=local -O0 -relocation-model=pic -o - ; PR1638 @.str242 = external constant [3 x i8] ; <[3 x i8]*> [#uses=1] diff --git a/test/CodeGen/PowerPC/cttz.ll b/test/CodeGen/PowerPC/cttz.ll index 2c51e8a..ab493a0 100644 --- a/test/CodeGen/PowerPC/cttz.ll +++ b/test/CodeGen/PowerPC/cttz.ll @@ -1,5 +1,5 @@ ; Make sure this testcase does not use ctpop -; RUN: llvm-as < %s | llc -march=ppc32 | grep -i cntlzw +; RUN: llc < %s -march=ppc32 | grep -i cntlzw declare i32 @llvm.cttz.i32(i32) diff --git a/test/CodeGen/PowerPC/darwin-labels.ll b/test/CodeGen/PowerPC/darwin-labels.ll index ceebc70..af23369 100644 --- a/test/CodeGen/PowerPC/darwin-labels.ll +++ b/test/CodeGen/PowerPC/darwin-labels.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc | grep {foo bar":} +; RUN: llc < %s | grep {foo bar":} target datalayout = "E-p:32:32" target triple = "powerpc-apple-darwin8.2.0" diff --git a/test/CodeGen/PowerPC/delete-node.ll b/test/CodeGen/PowerPC/delete-node.ll index 0b1d734..a26c211 100644 --- a/test/CodeGen/PowerPC/delete-node.ll +++ b/test/CodeGen/PowerPC/delete-node.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc32 +; RUN: llc < %s -march=ppc32 ; The DAGCombiner leaves behind a dead node in this testcase. Currently ; ISel is ignoring dead nodes, though it would be preferable for diff --git a/test/CodeGen/PowerPC/div-2.ll b/test/CodeGen/PowerPC/div-2.ll index 26e6221..2fc916f 100644 --- a/test/CodeGen/PowerPC/div-2.ll +++ b/test/CodeGen/PowerPC/div-2.ll @@ -1,5 +1,5 @@ -; RUN: llvm-as < %s | llc -march=ppc32 | not grep srawi -; RUN: llvm-as < %s | llc -march=ppc32 | grep blr +; RUN: llc < %s -march=ppc32 | not grep srawi +; RUN: llc < %s -march=ppc32 | grep blr define i32 @test1(i32 %X) { %Y = and i32 %X, 15 ; <i32> [#uses=1] diff --git a/test/CodeGen/PowerPC/eqv-andc-orc-nor.ll b/test/CodeGen/PowerPC/eqv-andc-orc-nor.ll index 7be8a34..558fd1b 100644 --- a/test/CodeGen/PowerPC/eqv-andc-orc-nor.ll +++ b/test/CodeGen/PowerPC/eqv-andc-orc-nor.ll @@ -1,12 +1,12 @@ -; RUN: llvm-as < %s | llc -march=ppc32 | \ +; RUN: llc < %s -march=ppc32 | \ ; RUN: grep eqv | count 3 -; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | \ +; RUN: llc < %s -march=ppc32 -mcpu=g5 | \ ; RUN: grep andc | count 3 -; RUN: llvm-as < %s | llc -march=ppc32 | \ +; RUN: llc < %s -march=ppc32 | \ ; RUN: grep orc | count 2 -; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | \ +; RUN: llc < %s -march=ppc32 -mcpu=g5 | \ ; RUN: grep nor | count 3 -; RUN: llvm-as < %s | llc -march=ppc32 | \ +; RUN: llc < %s -march=ppc32 | \ ; RUN: grep nand | count 1 define i32 @EQV1(i32 %X, i32 %Y) { diff --git a/test/CodeGen/PowerPC/extsh.ll b/test/CodeGen/PowerPC/extsh.ll index 5eca8ce..506ff86 100644 --- a/test/CodeGen/PowerPC/extsh.ll +++ b/test/CodeGen/PowerPC/extsh.ll @@ -1,5 +1,5 @@ ; This should turn into a single extsh -; RUN: llvm-as < %s | llc -march=ppc32 | grep extsh | count 1 +; RUN: llc < %s -march=ppc32 | grep extsh | count 1 define i32 @test(i32 %X) { %tmp.81 = shl i32 %X, 16 ; <i32> [#uses=1] %tmp.82 = ashr i32 %tmp.81, 16 ; <i32> [#uses=1] diff --git a/test/CodeGen/PowerPC/fabs.ll b/test/CodeGen/PowerPC/fabs.ll index 54e49b0..6ef740f 100644 --- a/test/CodeGen/PowerPC/fabs.ll +++ b/test/CodeGen/PowerPC/fabs.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-apple-darwin | grep {fabs f1, f1} +; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin | grep {fabs f1, f1} define double @fabs(double %f) { entry: diff --git a/test/CodeGen/PowerPC/fma.ll b/test/CodeGen/PowerPC/fma.ll index 4a6fe70..815c72c 100644 --- a/test/CodeGen/PowerPC/fma.ll +++ b/test/CodeGen/PowerPC/fma.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc32 | \ +; RUN: llc < %s -march=ppc32 | \ ; RUN: egrep {fn?madd|fn?msub} | count 8 define double @test_FMADD1(double %A, double %B, double %C) { diff --git a/test/CodeGen/PowerPC/fnabs.ll b/test/CodeGen/PowerPC/fnabs.ll index 6c10dfb..bbd5c71 100644 --- a/test/CodeGen/PowerPC/fnabs.ll +++ b/test/CodeGen/PowerPC/fnabs.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc32 | grep fnabs +; RUN: llc < %s -march=ppc32 | grep fnabs declare double @fabs(double) diff --git a/test/CodeGen/PowerPC/fneg.ll b/test/CodeGen/PowerPC/fneg.ll index 9579a74..0bd31bb 100644 --- a/test/CodeGen/PowerPC/fneg.ll +++ b/test/CodeGen/PowerPC/fneg.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc32 | not grep fneg +; RUN: llc < %s -march=ppc32 | not grep fneg define double @test1(double %a, double %b, double %c, double %d) { entry: diff --git a/test/CodeGen/PowerPC/fold-li.ll b/test/CodeGen/PowerPC/fold-li.ll index 2ac79f1..92d8da5 100644 --- a/test/CodeGen/PowerPC/fold-li.ll +++ b/test/CodeGen/PowerPC/fold-li.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc32 | \ +; RUN: llc < %s -march=ppc32 | \ ; RUN: grep -v align | not grep li ;; Test that immediates are folded into these instructions correctly. diff --git a/test/CodeGen/PowerPC/fp-branch.ll b/test/CodeGen/PowerPC/fp-branch.ll index 3db6ced..673da02 100644 --- a/test/CodeGen/PowerPC/fp-branch.ll +++ b/test/CodeGen/PowerPC/fp-branch.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc32 | grep fcmp | count 1 +; RUN: llc < %s -march=ppc32 | grep fcmp | count 1 declare i1 @llvm.isunordered.f64(double, double) diff --git a/test/CodeGen/PowerPC/fp-int-fp.ll b/test/CodeGen/PowerPC/fp-int-fp.ll index 1b78b01..18f7f83 100644 --- a/test/CodeGen/PowerPC/fp-int-fp.ll +++ b/test/CodeGen/PowerPC/fp-int-fp.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | not grep r1 +; RUN: llc < %s -march=ppc32 -mcpu=g5 | not grep r1 define double @test1(double %X) { %Y = fptosi double %X to i64 ; <i64> [#uses=1] diff --git a/test/CodeGen/PowerPC/fp_to_uint.ll b/test/CodeGen/PowerPC/fp_to_uint.ll index 43502bb..1360b62 100644 --- a/test/CodeGen/PowerPC/fp_to_uint.ll +++ b/test/CodeGen/PowerPC/fp_to_uint.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc32 | grep fctiwz | count 1 +; RUN: llc < %s -march=ppc32 | grep fctiwz | count 1 define i16 @foo(float %a) { entry: diff --git a/test/CodeGen/PowerPC/fpcopy.ll b/test/CodeGen/PowerPC/fpcopy.ll index 7d80596..7b9446b 100644 --- a/test/CodeGen/PowerPC/fpcopy.ll +++ b/test/CodeGen/PowerPC/fpcopy.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc32 | not grep fmr +; RUN: llc < %s -march=ppc32 | not grep fmr define double @test(float %F) { %F.upgrd.1 = fpext float %F to double ; <double> [#uses=1] diff --git a/test/CodeGen/PowerPC/frounds.ll b/test/CodeGen/PowerPC/frounds.ll index 0d8e621..8eeadc3 100644 --- a/test/CodeGen/PowerPC/frounds.ll +++ b/test/CodeGen/PowerPC/frounds.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc32 +; RUN: llc < %s -march=ppc32 define i32 @foo() { entry: diff --git a/test/CodeGen/PowerPC/fsqrt.ll b/test/CodeGen/PowerPC/fsqrt.ll index 1260c60..74a8725 100644 --- a/test/CodeGen/PowerPC/fsqrt.ll +++ b/test/CodeGen/PowerPC/fsqrt.ll @@ -1,17 +1,13 @@ ; fsqrt should be generated when the fsqrt feature is enabled, but not ; otherwise. -; RUN: llvm-as < %s | \ -; RUN: llc -march=ppc32 -mtriple=powerpc-apple-darwin8 -mattr=+fsqrt | \ +; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -mattr=+fsqrt | \ ; RUN: grep {fsqrt f1, f1} -; RUN: llvm-as < %s | \ -; RUN: llc -march=ppc32 -mtriple=powerpc-apple-darwin8 -mcpu=g5 | \ -; RUN: grep {fsqrt f1, f1} -; RUN: llvm-as < %s | \ -; RUN: llc -march=ppc32 -mtriple=powerpc-apple-darwin8 -mattr=-fsqrt | \ +; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -mcpu=g5 | \ +; RUN: grep {fsqrt f1, f1} +; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -mattr=-fsqrt | \ ; RUN: not grep {fsqrt f1, f1} -; RUN: llvm-as < %s | \ -; RUN: llc -march=ppc32 -mtriple=powerpc-apple-darwin8 -mcpu=g4 | \ +; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -mcpu=g4 | \ ; RUN: not grep {fsqrt f1, f1} declare double @llvm.sqrt.f64(double) diff --git a/test/CodeGen/PowerPC/hello.ll b/test/CodeGen/PowerPC/hello.ll index 1d7275f..ea27e92 100644 --- a/test/CodeGen/PowerPC/hello.ll +++ b/test/CodeGen/PowerPC/hello.ll @@ -1,5 +1,5 @@ -; RUN: llvm-as < %s | llc -march=ppc32 -; RUN: llvm-as < %s | llc -march=ppc64 +; RUN: llc < %s -march=ppc32 +; RUN: llc < %s -march=ppc64 ; PR1399 @.str = internal constant [13 x i8] c"Hello World!\00" diff --git a/test/CodeGen/PowerPC/hidden-vis-2.ll b/test/CodeGen/PowerPC/hidden-vis-2.ll index 4c9ae55..e9e2c0a 100644 --- a/test/CodeGen/PowerPC/hidden-vis-2.ll +++ b/test/CodeGen/PowerPC/hidden-vis-2.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -mtriple=powerpc-apple-darwin9 | grep non_lazy_ptr | count 6 +; RUN: llc < %s -mtriple=powerpc-apple-darwin9 | grep non_lazy_ptr | count 6 @x = external hidden global i32 ; <i32*> [#uses=1] @y = extern_weak hidden global i32 ; <i32*> [#uses=1] diff --git a/test/CodeGen/PowerPC/hidden-vis.ll b/test/CodeGen/PowerPC/hidden-vis.ll index e04c89a..b2cc143 100644 --- a/test/CodeGen/PowerPC/hidden-vis.ll +++ b/test/CodeGen/PowerPC/hidden-vis.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -mtriple=powerpc-apple-darwin9 | not grep non_lazy_ptr +; RUN: llc < %s -mtriple=powerpc-apple-darwin9 | not grep non_lazy_ptr @x = weak hidden global i32 0 ; <i32*> [#uses=1] diff --git a/test/CodeGen/PowerPC/i128-and-beyond.ll b/test/CodeGen/PowerPC/i128-and-beyond.ll index 9e0d6c3..51bcab2 100644 --- a/test/CodeGen/PowerPC/i128-and-beyond.ll +++ b/test/CodeGen/PowerPC/i128-and-beyond.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc32 | grep 4294967295 | count 28 +; RUN: llc < %s -march=ppc32 | grep 4294967295 | count 28 ; These static initializers are too big to hand off to assemblers ; as monolithic blobs. diff --git a/test/CodeGen/PowerPC/i64_fp.ll b/test/CodeGen/PowerPC/i64_fp.ll index 5ff2684..d53c948 100644 --- a/test/CodeGen/PowerPC/i64_fp.ll +++ b/test/CodeGen/PowerPC/i64_fp.ll @@ -1,21 +1,21 @@ ; fcfid and fctid should be generated when the 64bit feature is enabled, but not ; otherwise. -; RUN: llvm-as < %s | llc -march=ppc32 -mattr=+64bit | \ +; RUN: llc < %s -march=ppc32 -mattr=+64bit | \ ; RUN: grep fcfid -; RUN: llvm-as < %s | llc -march=ppc32 -mattr=+64bit | \ +; RUN: llc < %s -march=ppc32 -mattr=+64bit | \ ; RUN: grep fctidz -; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | \ +; RUN: llc < %s -march=ppc32 -mcpu=g5 | \ ; RUN: grep fcfid -; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | \ +; RUN: llc < %s -march=ppc32 -mcpu=g5 | \ ; RUN: grep fctidz -; RUN: llvm-as < %s | llc -march=ppc32 -mattr=-64bit | \ +; RUN: llc < %s -march=ppc32 -mattr=-64bit | \ ; RUN: not grep fcfid -; RUN: llvm-as < %s | llc -march=ppc32 -mattr=-64bit | \ +; RUN: llc < %s -march=ppc32 -mattr=-64bit | \ ; RUN: not grep fctidz -; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g4 | \ +; RUN: llc < %s -march=ppc32 -mcpu=g4 | \ ; RUN: not grep fcfid -; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g4 | \ +; RUN: llc < %s -march=ppc32 -mcpu=g4 | \ ; RUN: not grep fctidz define double @X(double %Y) { diff --git a/test/CodeGen/PowerPC/iabs.ll b/test/CodeGen/PowerPC/iabs.ll index 677b41b..a43f09c 100644 --- a/test/CodeGen/PowerPC/iabs.ll +++ b/test/CodeGen/PowerPC/iabs.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc32 -stats |& \ +; RUN: llc < %s -march=ppc32 -stats |& \ ; RUN: grep {4 .*Number of machine instrs printed} ;; Integer absolute value, should produce something as good as: diff --git a/test/CodeGen/PowerPC/illegal-element-type.ll b/test/CodeGen/PowerPC/illegal-element-type.ll index 54a0665..58bd055 100644 --- a/test/CodeGen/PowerPC/illegal-element-type.ll +++ b/test/CodeGen/PowerPC/illegal-element-type.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g3 +; RUN: llc < %s -march=ppc32 -mcpu=g3 define void @foo() { entry: diff --git a/test/CodeGen/PowerPC/inlineasm-copy.ll b/test/CodeGen/PowerPC/inlineasm-copy.ll index c0a3979..e1ff82d 100644 --- a/test/CodeGen/PowerPC/inlineasm-copy.ll +++ b/test/CodeGen/PowerPC/inlineasm-copy.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc32 | not grep mr +; RUN: llc < %s -march=ppc32 | not grep mr define i32 @test(i32 %Y, i32 %X) { entry: diff --git a/test/CodeGen/PowerPC/int-fp-conv-0.ll b/test/CodeGen/PowerPC/int-fp-conv-0.ll index 82a1826..983d2b8 100644 --- a/test/CodeGen/PowerPC/int-fp-conv-0.ll +++ b/test/CodeGen/PowerPC/int-fp-conv-0.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc64 > %t +; RUN: llc < %s -march=ppc64 > %t ; RUN: grep __floattitf %t ; RUN: grep __fixunstfti %t diff --git a/test/CodeGen/PowerPC/int-fp-conv-1.ll b/test/CodeGen/PowerPC/int-fp-conv-1.ll index 583408c..6c82723 100644 --- a/test/CodeGen/PowerPC/int-fp-conv-1.ll +++ b/test/CodeGen/PowerPC/int-fp-conv-1.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc64 | grep __floatditf +; RUN: llc < %s -march=ppc64 | grep __floatditf define i64 @__fixunstfdi(ppc_fp128 %a) nounwind { entry: diff --git a/test/CodeGen/PowerPC/invalid-memcpy.ll b/test/CodeGen/PowerPC/invalid-memcpy.ll index 6df968d..3b1f306 100644 --- a/test/CodeGen/PowerPC/invalid-memcpy.ll +++ b/test/CodeGen/PowerPC/invalid-memcpy.ll @@ -1,5 +1,5 @@ -; RUN: llvm-as < %s | llc -march=ppc32 -; RUN: llvm-as < %s | llc -march=ppc64 +; RUN: llc < %s -march=ppc32 +; RUN: llc < %s -march=ppc64 ; This testcase is invalid (the alignment specified for memcpy is ; greater than the alignment guaranteed for Qux or C.0.1173, but it diff --git a/test/CodeGen/PowerPC/inverted-bool-compares.ll b/test/CodeGen/PowerPC/inverted-bool-compares.ll index f8c5f11..aa7e4d6 100644 --- a/test/CodeGen/PowerPC/inverted-bool-compares.ll +++ b/test/CodeGen/PowerPC/inverted-bool-compares.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc32 | not grep xori +; RUN: llc < %s -march=ppc32 | not grep xori define i32 @test(i1 %B, i32* %P) { br i1 %B, label %T, label %F diff --git a/test/CodeGen/PowerPC/ispositive.ll b/test/CodeGen/PowerPC/ispositive.ll index 192d738..4161e34 100644 --- a/test/CodeGen/PowerPC/ispositive.ll +++ b/test/CodeGen/PowerPC/ispositive.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-apple-darwin8 | \ +; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 | \ ; RUN: grep {srwi r3, r3, 31} define i32 @test1(i32 %X) { diff --git a/test/CodeGen/PowerPC/itofp128.ll b/test/CodeGen/PowerPC/itofp128.ll index 4d74511..6d9ef95 100644 --- a/test/CodeGen/PowerPC/itofp128.ll +++ b/test/CodeGen/PowerPC/itofp128.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc64 +; RUN: llc < %s -march=ppc64 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128" target triple = "powerpc64-apple-darwin9.2.0" diff --git a/test/CodeGen/PowerPC/lha.ll b/test/CodeGen/PowerPC/lha.ll index e8f73ee..3a100c1 100644 --- a/test/CodeGen/PowerPC/lha.ll +++ b/test/CodeGen/PowerPC/lha.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc32 | grep lha +; RUN: llc < %s -march=ppc32 | grep lha define i32 @test(i16* %a) { %tmp.1 = load i16* %a ; <i16> [#uses=1] diff --git a/test/CodeGen/PowerPC/load-constant-addr.ll b/test/CodeGen/PowerPC/load-constant-addr.ll index d2be04e..f1d061c 100644 --- a/test/CodeGen/PowerPC/load-constant-addr.ll +++ b/test/CodeGen/PowerPC/load-constant-addr.ll @@ -1,6 +1,6 @@ ; Should fold the ori into the lfs. -; RUN: llvm-as < %s | llc -march=ppc32 | grep lfs -; RUN: llvm-as < %s | llc -march=ppc32 | not grep ori +; RUN: llc < %s -march=ppc32 | grep lfs +; RUN: llc < %s -march=ppc32 | not grep ori define float @test() { %tmp.i = load float* inttoptr (i32 186018016 to float*) ; <float> [#uses=1] diff --git a/test/CodeGen/PowerPC/long-compare.ll b/test/CodeGen/PowerPC/long-compare.ll index 7b90725..94c2526 100644 --- a/test/CodeGen/PowerPC/long-compare.ll +++ b/test/CodeGen/PowerPC/long-compare.ll @@ -1,7 +1,7 @@ -; RUN: llvm-as < %s | llc -march=ppc32 | grep cntlzw -; RUN: llvm-as < %s | llc -march=ppc32 | not grep xori -; RUN: llvm-as < %s | llc -march=ppc32 | not grep {li } -; RUN: llvm-as < %s | llc -march=ppc32 | not grep {mr } +; RUN: llc < %s -march=ppc32 | grep cntlzw +; RUN: llc < %s -march=ppc32 | not grep xori +; RUN: llc < %s -march=ppc32 | not grep {li } +; RUN: llc < %s -march=ppc32 | not grep {mr } define i1 @test(i64 %x) { %tmp = icmp ult i64 %x, 4294967296 diff --git a/test/CodeGen/PowerPC/longdbl-truncate.ll b/test/CodeGen/PowerPC/longdbl-truncate.ll index a873824..e5f63c6 100644 --- a/test/CodeGen/PowerPC/longdbl-truncate.ll +++ b/test/CodeGen/PowerPC/longdbl-truncate.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc +; RUN: llc < %s target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128" target triple = "powerpc-apple-darwin8" diff --git a/test/CodeGen/PowerPC/mask64.ll b/test/CodeGen/PowerPC/mask64.ll index 69d2200..139621a 100644 --- a/test/CodeGen/PowerPC/mask64.ll +++ b/test/CodeGen/PowerPC/mask64.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc +; RUN: llc < %s target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128" target triple = "powerpc64-apple-darwin9.2.0" diff --git a/test/CodeGen/PowerPC/mem-rr-addr-mode.ll b/test/CodeGen/PowerPC/mem-rr-addr-mode.ll index fd0e1d4..5661ef9 100644 --- a/test/CodeGen/PowerPC/mem-rr-addr-mode.ll +++ b/test/CodeGen/PowerPC/mem-rr-addr-mode.ll @@ -1,5 +1,5 @@ -; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | grep li.*16 -; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | not grep addi +; RUN: llc < %s -march=ppc32 -mcpu=g5 | grep li.*16 +; RUN: llc < %s -march=ppc32 -mcpu=g5 | not grep addi ; Codegen lvx (R+16) as t = li 16, lvx t,R ; This shares the 16 between the two loads. diff --git a/test/CodeGen/PowerPC/mem_update.ll b/test/CodeGen/PowerPC/mem_update.ll index a152762..b267719 100644 --- a/test/CodeGen/PowerPC/mem_update.ll +++ b/test/CodeGen/PowerPC/mem_update.ll @@ -1,6 +1,6 @@ -; RUN: llvm-as < %s | llc -march=ppc32 -enable-ppc-preinc | \ +; RUN: llc < %s -march=ppc32 -enable-ppc-preinc | \ ; RUN: not grep addi -; RUN: llvm-as < %s | llc -march=ppc64 -enable-ppc-preinc | \ +; RUN: llc < %s -march=ppc64 -enable-ppc-preinc | \ ; RUN: not grep addi @Glob = global i64 4 ; <i64*> [#uses=2] diff --git a/test/CodeGen/PowerPC/mul-neg-power-2.ll b/test/CodeGen/PowerPC/mul-neg-power-2.ll index 90446d7..9688d6e 100644 --- a/test/CodeGen/PowerPC/mul-neg-power-2.ll +++ b/test/CodeGen/PowerPC/mul-neg-power-2.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc32 | not grep mul +; RUN: llc < %s -march=ppc32 | not grep mul define i32 @test1(i32 %a) { %tmp.1 = mul i32 %a, -2 ; <i32> [#uses=1] diff --git a/test/CodeGen/PowerPC/mul-with-overflow.ll b/test/CodeGen/PowerPC/mul-with-overflow.ll index 0276846..f03e3cb 100644 --- a/test/CodeGen/PowerPC/mul-with-overflow.ll +++ b/test/CodeGen/PowerPC/mul-with-overflow.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc32 +; RUN: llc < %s -march=ppc32 declare {i32, i1} @llvm.umul.with.overflow.i32(i32 %a, i32 %b) define i1 @a(i32 %x) zeroext nounwind { diff --git a/test/CodeGen/PowerPC/mulhs.ll b/test/CodeGen/PowerPC/mulhs.ll index 3b0daad..9ab8d99 100644 --- a/test/CodeGen/PowerPC/mulhs.ll +++ b/test/CodeGen/PowerPC/mulhs.ll @@ -1,5 +1,5 @@ ; All of these ands and shifts should be folded into rlwimi's -; RUN: llvm-as < %s | llc -march=ppc32 -o %t -f +; RUN: llc < %s -march=ppc32 -o %t ; RUN: not grep mulhwu %t ; RUN: not grep srawi %t ; RUN: not grep add %t diff --git a/test/CodeGen/PowerPC/multiple-return-values.ll b/test/CodeGen/PowerPC/multiple-return-values.ll index 3f75f7d..b9317f9 100644 --- a/test/CodeGen/PowerPC/multiple-return-values.ll +++ b/test/CodeGen/PowerPC/multiple-return-values.ll @@ -1,5 +1,5 @@ -; RUN: llvm-as < %s | llc -march=ppc32 -; RUN: llvm-as < %s | llc -march=ppc64 +; RUN: llc < %s -march=ppc32 +; RUN: llc < %s -march=ppc64 define {i64, float} @bar(i64 %a, float %b) { %y = add i64 %a, 7 diff --git a/test/CodeGen/PowerPC/neg.ll b/test/CodeGen/PowerPC/neg.ll index c135599..c673912 100644 --- a/test/CodeGen/PowerPC/neg.ll +++ b/test/CodeGen/PowerPC/neg.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc32 | grep neg +; RUN: llc < %s -march=ppc32 | grep neg define i32 @test(i32 %X) { %Y = sub i32 0, %X ; <i32> [#uses=1] diff --git a/test/CodeGen/PowerPC/no-dead-strip.ll b/test/CodeGen/PowerPC/no-dead-strip.ll index e7ceaae..3459413 100644 --- a/test/CodeGen/PowerPC/no-dead-strip.ll +++ b/test/CodeGen/PowerPC/no-dead-strip.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc | grep {no_dead_strip.*_X} +; RUN: llc < %s | grep {no_dead_strip.*_X} target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64" target triple = "powerpc-apple-darwin8.8.0" diff --git a/test/CodeGen/PowerPC/or-addressing-mode.ll b/test/CodeGen/PowerPC/or-addressing-mode.ll index 9b6e955..e50374e 100644 --- a/test/CodeGen/PowerPC/or-addressing-mode.ll +++ b/test/CodeGen/PowerPC/or-addressing-mode.ll @@ -1,5 +1,5 @@ -; RUN: llvm-as < %s | llc -mtriple=powerpc-apple-darwin8 | not grep ori -; RUN: llvm-as < %s | llc -mtriple=powerpc-apple-darwin8 | not grep rlwimi +; RUN: llc < %s -mtriple=powerpc-apple-darwin8 | not grep ori +; RUN: llc < %s -mtriple=powerpc-apple-darwin8 | not grep rlwimi define i32 @test1(i8* %P) { %tmp.2.i = ptrtoint i8* %P to i32 ; <i32> [#uses=2] diff --git a/test/CodeGen/PowerPC/ppcf128-1-opt.ll b/test/CodeGen/PowerPC/ppcf128-1-opt.ll index e3c5ab1..2fc1720 100644 --- a/test/CodeGen/PowerPC/ppcf128-1-opt.ll +++ b/test/CodeGen/PowerPC/ppcf128-1-opt.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc > %t +; RUN: llc < %s > %t ; ModuleID = '<stdin>' target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128" target triple = "powerpc-apple-darwin8" diff --git a/test/CodeGen/PowerPC/ppcf128-1.ll b/test/CodeGen/PowerPC/ppcf128-1.ll index a487de7..1047fe5 100644 --- a/test/CodeGen/PowerPC/ppcf128-1.ll +++ b/test/CodeGen/PowerPC/ppcf128-1.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | opt -std-compile-opts | llc > %t +; RUN: opt < %s -std-compile-opts | llc > %t ; ModuleID = 'ld3.c' target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128" target triple = "powerpc-apple-darwin8" diff --git a/test/CodeGen/PowerPC/ppcf128-2.ll b/test/CodeGen/PowerPC/ppcf128-2.ll index 4318226..7eee354 100644 --- a/test/CodeGen/PowerPC/ppcf128-2.ll +++ b/test/CodeGen/PowerPC/ppcf128-2.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc64 +; RUN: llc < %s -march=ppc64 define i64 @__fixtfdi(ppc_fp128 %a) nounwind { entry: diff --git a/test/CodeGen/PowerPC/ppcf128-3.ll b/test/CodeGen/PowerPC/ppcf128-3.ll index 3a51f4d..5043b62 100644 --- a/test/CodeGen/PowerPC/ppcf128-3.ll +++ b/test/CodeGen/PowerPC/ppcf128-3.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc32 +; RUN: llc < %s -march=ppc32 %struct.stp_sequence = type { double, double } define i32 @stp_sequence_set_short_data(%struct.stp_sequence* %sequence, i32 %count, i16* %data) { diff --git a/test/CodeGen/PowerPC/ppcf128-4.ll b/test/CodeGen/PowerPC/ppcf128-4.ll index 16d6178..104a25e 100644 --- a/test/CodeGen/PowerPC/ppcf128-4.ll +++ b/test/CodeGen/PowerPC/ppcf128-4.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc32 +; RUN: llc < %s -march=ppc32 define ppc_fp128 @__floatditf(i64 %u) nounwind { entry: diff --git a/test/CodeGen/PowerPC/pr3711_widen_bit.ll b/test/CodeGen/PowerPC/pr3711_widen_bit.ll index e601e96..7abdeda 100644 --- a/test/CodeGen/PowerPC/pr3711_widen_bit.ll +++ b/test/CodeGen/PowerPC/pr3711_widen_bit.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 +; RUN: llc < %s -march=ppc32 -mcpu=g5 ; Test that causes a abort in expanding a bit convert due to a missing support ; for widening. diff --git a/test/CodeGen/PowerPC/private.ll b/test/CodeGen/PowerPC/private.ll index 0f0d134..d6e6770 100644 --- a/test/CodeGen/PowerPC/private.ll +++ b/test/CodeGen/PowerPC/private.ll @@ -1,25 +1,23 @@ ; Test to make sure that the 'private' is used correctly. ; -; RUN: llvm-as < %s | llc -mtriple=powerpc-unknown-linux-gnu > %t +; RUN: llc < %s -mtriple=powerpc-unknown-linux-gnu > %t ; RUN: grep .Lfoo: %t ; RUN: grep bl.*\.Lfoo %t ; RUN: grep .Lbaz: %t ; RUN: grep lis.*\.Lbaz %t -; RUN: llvm-as < %s | llc -mtriple=powerpc-apple-darwin > %t +; RUN: llc < %s -mtriple=powerpc-apple-darwin > %t ; RUN: grep L_foo: %t ; RUN: grep bl.*\L_foo %t ; RUN: grep L_baz: %t ; RUN: grep lis.*\L_baz %t -declare void @foo() - -define private void @foo() { +define private void @foo() nounwind { ret void } @baz = private global i32 4; -define i32 @bar() { +define i32 @bar() nounwind { call void @foo() %1 = load i32* @baz, align 4 ret i32 %1 diff --git a/test/CodeGen/PowerPC/reg-coalesce-simple.ll b/test/CodeGen/PowerPC/reg-coalesce-simple.ll index b86ed1a..e0ddb42 100644 --- a/test/CodeGen/PowerPC/reg-coalesce-simple.ll +++ b/test/CodeGen/PowerPC/reg-coalesce-simple.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc32 | not grep or +; RUN: llc < %s -march=ppc32 | not grep or %struct.foo = type { i32, i32, [0 x i8] } diff --git a/test/CodeGen/PowerPC/retaddr.ll b/test/CodeGen/PowerPC/retaddr.ll index f4cad34..9f8647d 100644 --- a/test/CodeGen/PowerPC/retaddr.ll +++ b/test/CodeGen/PowerPC/retaddr.ll @@ -1,6 +1,6 @@ -; RUN: llvm-as < %s | llc -march=ppc32 | grep mflr -; RUN: llvm-as < %s | llc -march=ppc32 | grep lwz -; RUN: llvm-as < %s | llc -march=ppc64 | grep {ld r., 16(r1)} +; RUN: llc < %s -march=ppc32 | grep mflr +; RUN: llc < %s -march=ppc32 | grep lwz +; RUN: llc < %s -march=ppc64 | grep {ld r., 16(r1)} target triple = "powerpc-apple-darwin8" diff --git a/test/CodeGen/PowerPC/return-val-i128.ll b/test/CodeGen/PowerPC/return-val-i128.ll index 27a5004..e14a438 100644 --- a/test/CodeGen/PowerPC/return-val-i128.ll +++ b/test/CodeGen/PowerPC/return-val-i128.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc64 +; RUN: llc < %s -march=ppc64 define i128 @__fixsfdi(float %a) { entry: diff --git a/test/CodeGen/PowerPC/rlwimi-commute.ll b/test/CodeGen/PowerPC/rlwimi-commute.ll index f8a42b5..6410c63 100644 --- a/test/CodeGen/PowerPC/rlwimi-commute.ll +++ b/test/CodeGen/PowerPC/rlwimi-commute.ll @@ -1,5 +1,5 @@ -; RUN: llvm-as < %s | llc -march=ppc32 | grep rlwimi -; RUN: llvm-as < %s | llc -march=ppc32 | not grep {or } +; RUN: llc < %s -march=ppc32 | grep rlwimi +; RUN: llc < %s -march=ppc32 | not grep {or } ; Make sure there is no register-register copies here. diff --git a/test/CodeGen/PowerPC/rlwimi.ll b/test/CodeGen/PowerPC/rlwimi.ll index 5e310bb..556ca3d 100644 --- a/test/CodeGen/PowerPC/rlwimi.ll +++ b/test/CodeGen/PowerPC/rlwimi.ll @@ -1,6 +1,6 @@ ; All of these ands and shifts should be folded into rlwimi's -; RUN: llvm-as < %s | llc -march=ppc32 | not grep and -; RUN: llvm-as < %s | llc -march=ppc32 | grep rlwimi | count 8 +; RUN: llc < %s -march=ppc32 | not grep and +; RUN: llc < %s -march=ppc32 | grep rlwimi | count 8 define i32 @test1(i32 %x, i32 %y) { entry: diff --git a/test/CodeGen/PowerPC/rlwimi2.ll b/test/CodeGen/PowerPC/rlwimi2.ll index 33eaacf..59a3655 100644 --- a/test/CodeGen/PowerPC/rlwimi2.ll +++ b/test/CodeGen/PowerPC/rlwimi2.ll @@ -1,5 +1,5 @@ ; All of these ands and shifts should be folded into rlwimi's -; RUN: llvm-as < %s | llc -march=ppc32 -o %t -f +; RUN: llc < %s -march=ppc32 -o %t ; RUN: grep rlwimi %t | count 3 ; RUN: grep srwi %t | count 1 ; RUN: not grep slwi %t diff --git a/test/CodeGen/PowerPC/rlwimi3.ll b/test/CodeGen/PowerPC/rlwimi3.ll index fedcfbf..05d37bf 100644 --- a/test/CodeGen/PowerPC/rlwimi3.ll +++ b/test/CodeGen/PowerPC/rlwimi3.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc32 -stats |& \ +; RUN: llc < %s -march=ppc32 -stats |& \ ; RUN: grep {Number of machine instrs printed} | grep 12 define i16 @Trans16Bit(i32 %srcA, i32 %srcB, i32 %alpha) { diff --git a/test/CodeGen/PowerPC/rlwinm.ll b/test/CodeGen/PowerPC/rlwinm.ll index 9d34865..699f6e7 100644 --- a/test/CodeGen/PowerPC/rlwinm.ll +++ b/test/CodeGen/PowerPC/rlwinm.ll @@ -1,5 +1,5 @@ ; All of these ands and shifts should be folded into rlwimi's -; RUN: llvm-as < %s | llc -march=ppc32 -o %t -f +; RUN: llc < %s -march=ppc32 -o %t ; RUN: not grep and %t ; RUN: not grep srawi %t ; RUN: not grep srwi %t diff --git a/test/CodeGen/PowerPC/rlwinm2.ll b/test/CodeGen/PowerPC/rlwinm2.ll index 06ceaa2..46542d8 100644 --- a/test/CodeGen/PowerPC/rlwinm2.ll +++ b/test/CodeGen/PowerPC/rlwinm2.ll @@ -1,5 +1,5 @@ ; All of these ands and shifts should be folded into rlw[i]nm instructions -; RUN: llvm-as < %s | llc -march=ppc32 -o %t -f +; RUN: llc < %s -march=ppc32 -o %t ; RUN: not grep and %t ; RUN: not grep srawi %t ; RUN: not grep srwi %t diff --git a/test/CodeGen/PowerPC/rotl-2.ll b/test/CodeGen/PowerPC/rotl-2.ll index df10459..d32ef59 100644 --- a/test/CodeGen/PowerPC/rotl-2.ll +++ b/test/CodeGen/PowerPC/rotl-2.ll @@ -1,6 +1,6 @@ -; RUN: llvm-as < %s | llc -march=ppc32 | grep rlwinm | count 4 -; RUN: llvm-as < %s | llc -march=ppc32 | grep rlwnm | count 2 -; RUN: llvm-as < %s | llc -march=ppc32 | not grep or +; RUN: llc < %s -march=ppc32 | grep rlwinm | count 4 +; RUN: llc < %s -march=ppc32 | grep rlwnm | count 2 +; RUN: llc < %s -march=ppc32 | not grep or define i32 @rotl32(i32 %A, i8 %Amt) nounwind { %shift.upgrd.1 = zext i8 %Amt to i32 ; <i32> [#uses=1] diff --git a/test/CodeGen/PowerPC/rotl-64.ll b/test/CodeGen/PowerPC/rotl-64.ll index 3963d9a..674c9e4 100644 --- a/test/CodeGen/PowerPC/rotl-64.ll +++ b/test/CodeGen/PowerPC/rotl-64.ll @@ -1,5 +1,5 @@ -; RUN: llvm-as < %s | llc -march=ppc64 | grep rldicl -; RUN: llvm-as < %s | llc -march=ppc64 | grep rldcl +; RUN: llc < %s -march=ppc64 | grep rldicl +; RUN: llc < %s -march=ppc64 | grep rldcl ; PR1613 define i64 @t1(i64 %A) { diff --git a/test/CodeGen/PowerPC/rotl.ll b/test/CodeGen/PowerPC/rotl.ll index aab5c83..56fc4a8 100644 --- a/test/CodeGen/PowerPC/rotl.ll +++ b/test/CodeGen/PowerPC/rotl.ll @@ -1,5 +1,5 @@ -; RUN: llvm-as < %s | llc -march=ppc32 | grep rlwnm | count 2 -; RUN: llvm-as < %s | llc -march=ppc32 | grep rlwinm | count 2 +; RUN: llc < %s -march=ppc32 | grep rlwnm | count 2 +; RUN: llc < %s -march=ppc32 | grep rlwinm | count 2 define i32 @rotlw(i32 %x, i32 %sh) { entry: diff --git a/test/CodeGen/PowerPC/sections.ll b/test/CodeGen/PowerPC/sections.ll new file mode 100644 index 0000000..1af3709 --- /dev/null +++ b/test/CodeGen/PowerPC/sections.ll @@ -0,0 +1,8 @@ +; Test to make sure that bss sections are printed with '.section' directive. +; RUN: llc < %s -mtriple=powerpc-unknown-linux-gnu | FileCheck %s + +@A = global i32 0 + +; CHECK: .section .bss,"aw",@nobits +; CHECK: .global A + diff --git a/test/CodeGen/PowerPC/select-cc.ll b/test/CodeGen/PowerPC/select-cc.ll index f9464c4..ccc6489 100644 --- a/test/CodeGen/PowerPC/select-cc.ll +++ b/test/CodeGen/PowerPC/select-cc.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc32 +; RUN: llc < %s -march=ppc32 ; PR3011 define <2 x double> @vector_select(<2 x double> %x, <2 x double> %y) nounwind { diff --git a/test/CodeGen/PowerPC/select_lt0.ll b/test/CodeGen/PowerPC/select_lt0.ll index 86eb201..95ba84a 100644 --- a/test/CodeGen/PowerPC/select_lt0.ll +++ b/test/CodeGen/PowerPC/select_lt0.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc32 | not grep cmp +; RUN: llc < %s -march=ppc32 | not grep cmp define i32 @seli32_1(i32 %a) { entry: diff --git a/test/CodeGen/PowerPC/setcc_no_zext.ll b/test/CodeGen/PowerPC/setcc_no_zext.ll index c31f35c..9b2036e 100644 --- a/test/CodeGen/PowerPC/setcc_no_zext.ll +++ b/test/CodeGen/PowerPC/setcc_no_zext.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc32 | not grep rlwinm +; RUN: llc < %s -march=ppc32 | not grep rlwinm define i32 @setcc_one_or_zero(i32* %a) { entry: diff --git a/test/CodeGen/PowerPC/seteq-0.ll b/test/CodeGen/PowerPC/seteq-0.ll index 0f0afe9..688b29a 100644 --- a/test/CodeGen/PowerPC/seteq-0.ll +++ b/test/CodeGen/PowerPC/seteq-0.ll @@ -1,5 +1,4 @@ -; RUN: llvm-as < %s | \ -; RUN: llc -march=ppc32 -mtriple=powerpc-apple-darwin8 | \ +; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 | \ ; RUN: grep {srwi r., r., 5} define i32 @eq0(i32 %a) { diff --git a/test/CodeGen/PowerPC/shift128.ll b/test/CodeGen/PowerPC/shift128.ll index cf5b3fc..8e518c1 100644 --- a/test/CodeGen/PowerPC/shift128.ll +++ b/test/CodeGen/PowerPC/shift128.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc64 | grep sld | count 5 +; RUN: llc < %s -march=ppc64 | grep sld | count 5 define i128 @foo_lshr(i128 %x, i128 %y) { %r = lshr i128 %x, %y diff --git a/test/CodeGen/PowerPC/shl_elim.ll b/test/CodeGen/PowerPC/shl_elim.ll index 3dc4772..f177c4a 100644 --- a/test/CodeGen/PowerPC/shl_elim.ll +++ b/test/CodeGen/PowerPC/shl_elim.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc32 | not grep slwi +; RUN: llc < %s -march=ppc32 | not grep slwi define i32 @test1(i64 %a) { %tmp29 = lshr i64 %a, 24 ; <i64> [#uses=1] diff --git a/test/CodeGen/PowerPC/shl_sext.ll b/test/CodeGen/PowerPC/shl_sext.ll index 61e5cdb..1f35eb4 100644 --- a/test/CodeGen/PowerPC/shl_sext.ll +++ b/test/CodeGen/PowerPC/shl_sext.ll @@ -1,5 +1,5 @@ ; This test should not contain a sign extend -; RUN: llvm-as < %s | llc -march=ppc32 | not grep extsb +; RUN: llc < %s -march=ppc32 | not grep extsb define i32 @test(i32 %mode.0.i.0) { %tmp.79 = trunc i32 %mode.0.i.0 to i8 ; <i8> [#uses=1] diff --git a/test/CodeGen/PowerPC/sign_ext_inreg1.ll b/test/CodeGen/PowerPC/sign_ext_inreg1.ll index 0e67f77..2679c8e 100644 --- a/test/CodeGen/PowerPC/sign_ext_inreg1.ll +++ b/test/CodeGen/PowerPC/sign_ext_inreg1.ll @@ -1,5 +1,5 @@ -; RUN: llvm-as < %s | llc -march=ppc32 | grep srwi -; RUN: llvm-as < %s | llc -march=ppc32 | not grep rlwimi +; RUN: llc < %s -march=ppc32 | grep srwi +; RUN: llc < %s -march=ppc32 | not grep rlwimi define i32 @baz(i64 %a) { %tmp29 = lshr i64 %a, 24 ; <i64> [#uses=1] diff --git a/test/CodeGen/PowerPC/small-arguments.ll b/test/CodeGen/PowerPC/small-arguments.ll index e211e86..31bcee6 100644 --- a/test/CodeGen/PowerPC/small-arguments.ll +++ b/test/CodeGen/PowerPC/small-arguments.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc32 | not grep {extsh\\|rlwinm} +; RUN: llc < %s -march=ppc32 | not grep {extsh\\|rlwinm} declare i16 @foo() signext diff --git a/test/CodeGen/PowerPC/stfiwx-2.ll b/test/CodeGen/PowerPC/stfiwx-2.ll index 5c4a834b..c49b25c 100644 --- a/test/CodeGen/PowerPC/stfiwx-2.ll +++ b/test/CodeGen/PowerPC/stfiwx-2.ll @@ -1,6 +1,6 @@ ; This cannot be a stfiwx -; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | grep stb -; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | not grep stfiwx +; RUN: llc < %s -march=ppc32 -mcpu=g5 | grep stb +; RUN: llc < %s -march=ppc32 -mcpu=g5 | not grep stfiwx define void @test(float %F, i8* %P) { %I = fptosi float %F to i32 diff --git a/test/CodeGen/PowerPC/stfiwx.ll b/test/CodeGen/PowerPC/stfiwx.ll index c4afb63..d1c3f52 100644 --- a/test/CodeGen/PowerPC/stfiwx.ll +++ b/test/CodeGen/PowerPC/stfiwx.ll @@ -1,10 +1,8 @@ -; RUN: llvm-as < %s | \ -; RUN: llc -march=ppc32 -mtriple=powerpc-apple-darwin8 -mattr=stfiwx -o %t1 -f +; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -mattr=stfiwx -o %t1 ; RUN: grep stfiwx %t1 ; RUN: not grep r1 %t1 -; RUN: llvm-as < %s | \ -; RUN: llc -march=ppc32 -mtriple=powerpc-apple-darwin8 -mattr=-stfiwx \ -; RUN: -o %t2 -f +; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -mattr=-stfiwx \ +; RUN: -o %t2 ; RUN: not grep stfiwx %t2 ; RUN: grep r1 %t2 diff --git a/test/CodeGen/PowerPC/store-load-fwd.ll b/test/CodeGen/PowerPC/store-load-fwd.ll index 5cc4784..25663c1 100644 --- a/test/CodeGen/PowerPC/store-load-fwd.ll +++ b/test/CodeGen/PowerPC/store-load-fwd.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc32 | not grep lwz +; RUN: llc < %s -march=ppc32 | not grep lwz define i32 @test(i32* %P) { store i32 1, i32* %P diff --git a/test/CodeGen/PowerPC/subc.ll b/test/CodeGen/PowerPC/subc.ll index 4ac9596..5914dca 100644 --- a/test/CodeGen/PowerPC/subc.ll +++ b/test/CodeGen/PowerPC/subc.ll @@ -1,5 +1,5 @@ ; All of these should be codegen'd without loading immediates -; RUN: llvm-as < %s | llc -march=ppc32 -o %t -f +; RUN: llc < %s -march=ppc32 -o %t ; RUN: grep subfc %t | count 1 ; RUN: grep subfe %t | count 1 ; RUN: grep subfze %t | count 1 diff --git a/test/CodeGen/PowerPC/tailcall1-64.ll b/test/CodeGen/PowerPC/tailcall1-64.ll index f39b40b..e9c83a5 100644 --- a/test/CodeGen/PowerPC/tailcall1-64.ll +++ b/test/CodeGen/PowerPC/tailcall1-64.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc64 -tailcallopt | grep TC_RETURNd8 +; RUN: llc < %s -march=ppc64 -tailcallopt | grep TC_RETURNd8 define fastcc i32 @tailcallee(i32 %a1, i32 %a2, i32 %a3, i32 %a4) { entry: ret i32 %a3 diff --git a/test/CodeGen/PowerPC/tailcall1.ll b/test/CodeGen/PowerPC/tailcall1.ll index 1fc4b94..08f3392 100644 --- a/test/CodeGen/PowerPC/tailcall1.ll +++ b/test/CodeGen/PowerPC/tailcall1.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc32 -tailcallopt | grep TC_RETURN +; RUN: llc < %s -march=ppc32 -tailcallopt | grep TC_RETURN define fastcc i32 @tailcallee(i32 %a1, i32 %a2, i32 %a3, i32 %a4) { entry: ret i32 %a3 diff --git a/test/CodeGen/PowerPC/tailcallpic1.ll b/test/CodeGen/PowerPC/tailcallpic1.ll index 678d366..f3f5028 100644 --- a/test/CodeGen/PowerPC/tailcallpic1.ll +++ b/test/CodeGen/PowerPC/tailcallpic1.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -tailcallopt -mtriple=powerpc-apple-darwin -relocation-model=pic | grep TC_RETURN +; RUN: llc < %s -tailcallopt -mtriple=powerpc-apple-darwin -relocation-model=pic | grep TC_RETURN diff --git a/test/CodeGen/PowerPC/tango.net.ftp.FtpClient.ll b/test/CodeGen/PowerPC/tango.net.ftp.FtpClient.ll new file mode 100644 index 0000000..8a1288a --- /dev/null +++ b/test/CodeGen/PowerPC/tango.net.ftp.FtpClient.ll @@ -0,0 +1,583 @@ +; RUN: llc < %s +; PR4534 + +; ModuleID = 'tango.net.ftp.FtpClient.bc' +target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128" +target triple = "powerpc-apple-darwin9.6.0" + %"byte[]" = type { i32, i8* } +@.str167 = external constant [11 x i8] ; <[11 x i8]*> [#uses=1] +@.str170 = external constant [11 x i8] ; <[11 x i8]*> [#uses=2] +@.str171 = external constant [5 x i8] ; <[5 x i8]*> [#uses=1] +@llvm.used = appending global [1 x i8*] [i8* bitcast (void (%"byte[]")* @foo to i8*)], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0] + +define fastcc void @foo(%"byte[]" %line_arg) { +entry: + %line_arg830 = extractvalue %"byte[]" %line_arg, 0 ; <i32> [#uses=12] + %line_arg831 = extractvalue %"byte[]" %line_arg, 1 ; <i8*> [#uses=17] + %t5 = load i8* %line_arg831 ; <i8> [#uses=1] + br label %forcondi + +forcondi: ; preds = %forbodyi, %entry + %l.0i = phi i32 [ 10, %entry ], [ %t4i, %forbodyi ] ; <i32> [#uses=2] + %p.0i = phi i8* [ getelementptr ([11 x i8]* @.str167, i32 0, i32 -1), %entry ], [ %t7i, %forbodyi ] ; <i8*> [#uses=1] + %t4i = add i32 %l.0i, -1 ; <i32> [#uses=1] + %t5i = icmp eq i32 %l.0i, 0 ; <i1> [#uses=1] + br i1 %t5i, label %forcond.i, label %forbodyi + +forbodyi: ; preds = %forcondi + %t7i = getelementptr i8* %p.0i, i32 1 ; <i8*> [#uses=2] + %t8i = load i8* %t7i ; <i8> [#uses=1] + %t12i = icmp eq i8 %t8i, %t5 ; <i1> [#uses=1] + br i1 %t12i, label %forcond.i, label %forcondi + +forcond.i: ; preds = %forbody.i, %forbodyi, %forcondi + %storemerge.i = phi i32 [ %t106.i, %forbody.i ], [ 1, %forcondi ], [ 1, %forbodyi ] ; <i32> [#uses=1] + %t77.i286 = phi i1 [ %phit3, %forbody.i ], [ false, %forcondi ], [ false, %forbodyi ] ; <i1> [#uses=1] + br i1 %t77.i286, label %forcond.i295, label %forbody.i + +forbody.i: ; preds = %forcond.i + %t106.i = add i32 %storemerge.i, 1 ; <i32> [#uses=2] + %phit3 = icmp ugt i32 %t106.i, 3 ; <i1> [#uses=1] + br label %forcond.i + +forcond.i295: ; preds = %forbody.i301, %forcond.i + %storemerge.i292 = phi i32 [ %t106.i325, %forbody.i301 ], [ 4, %forcond.i ] ; <i32> [#uses=1] + %t77.i293 = phi i1 [ %phit2, %forbody.i301 ], [ false, %forcond.i ] ; <i1> [#uses=1] + br i1 %t77.i293, label %forcond.i332, label %forbody.i301 + +forbody.i301: ; preds = %forcond.i295 + %t106.i325 = add i32 %storemerge.i292, 1 ; <i32> [#uses=2] + %phit2 = icmp ugt i32 %t106.i325, 6 ; <i1> [#uses=1] + br label %forcond.i295 + +forcond.i332: ; preds = %forbody.i338, %forcond.i295 + %storemerge.i329 = phi i32 [ %t106.i362, %forbody.i338 ], [ 7, %forcond.i295 ] ; <i32> [#uses=3] + %t77.i330 = phi i1 [ %phit1, %forbody.i338 ], [ false, %forcond.i295 ] ; <i1> [#uses=1] + br i1 %t77.i330, label %wcond.i370, label %forbody.i338 + +forbody.i338: ; preds = %forcond.i332 + %t106.i362 = add i32 %storemerge.i329, 1 ; <i32> [#uses=2] + %phit1 = icmp ugt i32 %t106.i362, 9 ; <i1> [#uses=1] + br label %forcond.i332 + +wcond.i370: ; preds = %wbody.i372, %forcond.i332 + %.frame.0.11 = phi i32 [ %t18.i371.c, %wbody.i372 ], [ %storemerge.i329, %forcond.i332 ] ; <i32> [#uses=2] + %t3.i368 = phi i32 [ %t18.i371.c, %wbody.i372 ], [ %storemerge.i329, %forcond.i332 ] ; <i32> [#uses=5] + %t4.i369 = icmp ult i32 %t3.i368, %line_arg830 ; <i1> [#uses=1] + br i1 %t4.i369, label %andand.i378, label %wcond22.i383 + +wbody.i372: ; preds = %andand.i378 + %t18.i371.c = add i32 %t3.i368, 1 ; <i32> [#uses=2] + br label %wcond.i370 + +andand.i378: ; preds = %wcond.i370 + %t11.i375 = getelementptr i8* %line_arg831, i32 %t3.i368 ; <i8*> [#uses=1] + %t12.i376 = load i8* %t11.i375 ; <i8> [#uses=1] + %t14.i377 = icmp eq i8 %t12.i376, 32 ; <i1> [#uses=1] + br i1 %t14.i377, label %wbody.i372, label %wcond22.i383 + +wcond22.i383: ; preds = %wbody23.i385, %andand.i378, %wcond.i370 + %.frame.0.10 = phi i32 [ %t50.i384, %wbody23.i385 ], [ %.frame.0.11, %wcond.i370 ], [ %.frame.0.11, %andand.i378 ] ; <i32> [#uses=2] + %t49.i381 = phi i32 [ %t50.i384, %wbody23.i385 ], [ %t3.i368, %wcond.i370 ], [ %t3.i368, %andand.i378 ] ; <i32> [#uses=5] + %t32.i382 = icmp ult i32 %t49.i381, %line_arg830 ; <i1> [#uses=1] + br i1 %t32.i382, label %andand33.i391, label %wcond54.i396 + +wbody23.i385: ; preds = %andand33.i391 + %t50.i384 = add i32 %t49.i381, 1 ; <i32> [#uses=2] + br label %wcond22.i383 + +andand33.i391: ; preds = %wcond22.i383 + %t42.i388 = getelementptr i8* %line_arg831, i32 %t49.i381 ; <i8*> [#uses=1] + %t43.i389 = load i8* %t42.i388 ; <i8> [#uses=1] + %t45.i390 = icmp eq i8 %t43.i389, 32 ; <i1> [#uses=1] + br i1 %t45.i390, label %wcond54.i396, label %wbody23.i385 + +wcond54.i396: ; preds = %wbody55.i401, %andand33.i391, %wcond22.i383 + %.frame.0.9 = phi i32 [ %t82.i400, %wbody55.i401 ], [ %.frame.0.10, %wcond22.i383 ], [ %.frame.0.10, %andand33.i391 ] ; <i32> [#uses=2] + %t81.i394 = phi i32 [ %t82.i400, %wbody55.i401 ], [ %t49.i381, %wcond22.i383 ], [ %t49.i381, %andand33.i391 ] ; <i32> [#uses=3] + %t64.i395 = icmp ult i32 %t81.i394, %line_arg830 ; <i1> [#uses=1] + br i1 %t64.i395, label %andand65.i407, label %wcond.i716 + +wbody55.i401: ; preds = %andand65.i407 + %t82.i400 = add i32 %t81.i394, 1 ; <i32> [#uses=2] + br label %wcond54.i396 + +andand65.i407: ; preds = %wcond54.i396 + %t74.i404 = getelementptr i8* %line_arg831, i32 %t81.i394 ; <i8*> [#uses=1] + %t75.i405 = load i8* %t74.i404 ; <i8> [#uses=1] + %t77.i406 = icmp eq i8 %t75.i405, 32 ; <i1> [#uses=1] + br i1 %t77.i406, label %wbody55.i401, label %wcond.i716 + +wcond.i716: ; preds = %wbody.i717, %andand65.i407, %wcond54.i396 + %.frame.0.0 = phi i32 [ %t18.i.c829, %wbody.i717 ], [ %.frame.0.9, %wcond54.i396 ], [ %.frame.0.9, %andand65.i407 ] ; <i32> [#uses=7] + %t4.i715 = icmp ult i32 %.frame.0.0, %line_arg830 ; <i1> [#uses=1] + br i1 %t4.i715, label %andand.i721, label %wcond22.i724 + +wbody.i717: ; preds = %andand.i721 + %t18.i.c829 = add i32 %.frame.0.0, 1 ; <i32> [#uses=1] + br label %wcond.i716 + +andand.i721: ; preds = %wcond.i716 + %t11.i718 = getelementptr i8* %line_arg831, i32 %.frame.0.0 ; <i8*> [#uses=1] + %t12.i719 = load i8* %t11.i718 ; <i8> [#uses=1] + %t14.i720 = icmp eq i8 %t12.i719, 32 ; <i1> [#uses=1] + br i1 %t14.i720, label %wbody.i717, label %wcond22.i724 + +wcond22.i724: ; preds = %wbody23.i726, %andand.i721, %wcond.i716 + %.frame.0.1 = phi i32 [ %t50.i725, %wbody23.i726 ], [ %.frame.0.0, %wcond.i716 ], [ %.frame.0.0, %andand.i721 ] ; <i32> [#uses=2] + %t49.i722 = phi i32 [ %t50.i725, %wbody23.i726 ], [ %.frame.0.0, %wcond.i716 ], [ %.frame.0.0, %andand.i721 ] ; <i32> [#uses=5] + %t32.i723 = icmp ult i32 %t49.i722, %line_arg830 ; <i1> [#uses=1] + br i1 %t32.i723, label %andand33.i731, label %wcond54.i734 + +wbody23.i726: ; preds = %andand33.i731 + %t50.i725 = add i32 %t49.i722, 1 ; <i32> [#uses=2] + br label %wcond22.i724 + +andand33.i731: ; preds = %wcond22.i724 + %t42.i728 = getelementptr i8* %line_arg831, i32 %t49.i722 ; <i8*> [#uses=1] + %t43.i729 = load i8* %t42.i728 ; <i8> [#uses=1] + %t45.i730 = icmp eq i8 %t43.i729, 32 ; <i1> [#uses=1] + br i1 %t45.i730, label %wcond54.i734, label %wbody23.i726 + +wcond54.i734: ; preds = %wbody55.i736, %andand33.i731, %wcond22.i724 + %.frame.0.2 = phi i32 [ %t82.i735, %wbody55.i736 ], [ %.frame.0.1, %wcond22.i724 ], [ %.frame.0.1, %andand33.i731 ] ; <i32> [#uses=2] + %t81.i732 = phi i32 [ %t82.i735, %wbody55.i736 ], [ %t49.i722, %wcond22.i724 ], [ %t49.i722, %andand33.i731 ] ; <i32> [#uses=3] + %t64.i733 = icmp ult i32 %t81.i732, %line_arg830 ; <i1> [#uses=1] + br i1 %t64.i733, label %andand65.i740, label %wcond.i750 + +wbody55.i736: ; preds = %andand65.i740 + %t82.i735 = add i32 %t81.i732, 1 ; <i32> [#uses=2] + br label %wcond54.i734 + +andand65.i740: ; preds = %wcond54.i734 + %t74.i737 = getelementptr i8* %line_arg831, i32 %t81.i732 ; <i8*> [#uses=1] + %t75.i738 = load i8* %t74.i737 ; <i8> [#uses=1] + %t77.i739 = icmp eq i8 %t75.i738, 32 ; <i1> [#uses=1] + br i1 %t77.i739, label %wbody55.i736, label %wcond.i750 + +wcond.i750: ; preds = %wbody.i752, %andand65.i740, %wcond54.i734 + %.frame.0.3 = phi i32 [ %t18.i751.c, %wbody.i752 ], [ %.frame.0.2, %wcond54.i734 ], [ %.frame.0.2, %andand65.i740 ] ; <i32> [#uses=11] + %t4.i749 = icmp ult i32 %.frame.0.3, %line_arg830 ; <i1> [#uses=1] + br i1 %t4.i749, label %andand.i758, label %wcond22.i761 + +wbody.i752: ; preds = %andand.i758 + %t18.i751.c = add i32 %.frame.0.3, 1 ; <i32> [#uses=1] + br label %wcond.i750 + +andand.i758: ; preds = %wcond.i750 + %t11.i755 = getelementptr i8* %line_arg831, i32 %.frame.0.3 ; <i8*> [#uses=1] + %t12.i756 = load i8* %t11.i755 ; <i8> [#uses=1] + %t14.i757 = icmp eq i8 %t12.i756, 32 ; <i1> [#uses=1] + br i1 %t14.i757, label %wbody.i752, label %wcond22.i761 + +wcond22.i761: ; preds = %wbody23.i763, %andand.i758, %wcond.i750 + %.frame.0.4 = phi i32 [ %t50.i762, %wbody23.i763 ], [ %.frame.0.3, %wcond.i750 ], [ %.frame.0.3, %andand.i758 ] ; <i32> [#uses=2] + %t49.i759 = phi i32 [ %t50.i762, %wbody23.i763 ], [ %.frame.0.3, %wcond.i750 ], [ %.frame.0.3, %andand.i758 ] ; <i32> [#uses=7] + %t32.i760 = icmp ult i32 %t49.i759, %line_arg830 ; <i1> [#uses=1] + br i1 %t32.i760, label %andand33.i769, label %wcond54.i773 + +wbody23.i763: ; preds = %andand33.i769 + %t50.i762 = add i32 %t49.i759, 1 ; <i32> [#uses=2] + br label %wcond22.i761 + +andand33.i769: ; preds = %wcond22.i761 + %t42.i766 = getelementptr i8* %line_arg831, i32 %t49.i759 ; <i8*> [#uses=1] + %t43.i767 = load i8* %t42.i766 ; <i8> [#uses=1] + %t45.i768 = icmp eq i8 %t43.i767, 32 ; <i1> [#uses=1] + br i1 %t45.i768, label %wcond54.i773, label %wbody23.i763 + +wcond54.i773: ; preds = %wbody55.i775, %andand33.i769, %wcond22.i761 + %.frame.0.5 = phi i32 [ %t82.i774, %wbody55.i775 ], [ %.frame.0.4, %wcond22.i761 ], [ %.frame.0.4, %andand33.i769 ] ; <i32> [#uses=1] + %t81.i770 = phi i32 [ %t82.i774, %wbody55.i775 ], [ %t49.i759, %wcond22.i761 ], [ %t49.i759, %andand33.i769 ] ; <i32> [#uses=3] + %t64.i771 = icmp ult i32 %t81.i770, %line_arg830 ; <i1> [#uses=1] + br i1 %t64.i771, label %andand65.i780, label %Dt3net3ftp9FClient13FConnection13pListLineMFAaZS5t3net3ftp9FClient11FFileInfo10p_wordMFZAa.exit786 + +wbody55.i775: ; preds = %andand65.i780 + %t82.i774 = add i32 %t81.i770, 1 ; <i32> [#uses=2] + br label %wcond54.i773 + +andand65.i780: ; preds = %wcond54.i773 + %t74.i777 = getelementptr i8* %line_arg831, i32 %t81.i770 ; <i8*> [#uses=1] + %t75.i778 = load i8* %t74.i777 ; <i8> [#uses=1] + %t77.i779 = icmp eq i8 %t75.i778, 32 ; <i1> [#uses=1] + br i1 %t77.i779, label %wbody55.i775, label %Dt3net3ftp9FClient13FConnection13pListLineMFAaZS5t3net3ftp9FClient11FFileInfo10p_wordMFZAa.exit786 + +Dt3net3ftp9FClient13FConnection13pListLineMFAaZS5t3net3ftp9FClient11FFileInfo10p_wordMFZAa.exit786: ; preds = %andand65.i780, %wcond54.i773 + %t89.i782 = getelementptr i8* %line_arg831, i32 %.frame.0.3 ; <i8*> [#uses=4] + %t90.i783 = sub i32 %t49.i759, %.frame.0.3 ; <i32> [#uses=2] + br label %wcond.i792 + +wcond.i792: ; preds = %wbody.i794, %Dt3net3ftp9FClient13FConnection13pListLineMFAaZS5t3net3ftp9FClient11FFileInfo10p_wordMFZAa.exit786 + %.frame.0.6 = phi i32 [ %.frame.0.5, %Dt3net3ftp9FClient13FConnection13pListLineMFAaZS5t3net3ftp9FClient11FFileInfo10p_wordMFZAa.exit786 ], [ %t18.i793.c, %wbody.i794 ] ; <i32> [#uses=9] + %t4.i791 = icmp ult i32 %.frame.0.6, %line_arg830 ; <i1> [#uses=1] + br i1 %t4.i791, label %andand.i800, label %wcond22.i803 + +wbody.i794: ; preds = %andand.i800 + %t18.i793.c = add i32 %.frame.0.6, 1 ; <i32> [#uses=1] + br label %wcond.i792 + +andand.i800: ; preds = %wcond.i792 + %t11.i797 = getelementptr i8* %line_arg831, i32 %.frame.0.6 ; <i8*> [#uses=1] + %t12.i798 = load i8* %t11.i797 ; <i8> [#uses=1] + %t14.i799 = icmp eq i8 %t12.i798, 32 ; <i1> [#uses=1] + br i1 %t14.i799, label %wbody.i794, label %wcond22.i803 + +wcond22.i803: ; preds = %wbody23.i805, %andand.i800, %wcond.i792 + %t49.i801 = phi i32 [ %t50.i804, %wbody23.i805 ], [ %.frame.0.6, %wcond.i792 ], [ %.frame.0.6, %andand.i800 ] ; <i32> [#uses=7] + %t32.i802 = icmp ult i32 %t49.i801, %line_arg830 ; <i1> [#uses=1] + br i1 %t32.i802, label %andand33.i811, label %wcond54.i815 + +wbody23.i805: ; preds = %andand33.i811 + %t50.i804 = add i32 %t49.i801, 1 ; <i32> [#uses=1] + br label %wcond22.i803 + +andand33.i811: ; preds = %wcond22.i803 + %t42.i808 = getelementptr i8* %line_arg831, i32 %t49.i801 ; <i8*> [#uses=1] + %t43.i809 = load i8* %t42.i808 ; <i8> [#uses=1] + %t45.i810 = icmp eq i8 %t43.i809, 32 ; <i1> [#uses=1] + br i1 %t45.i810, label %wcond54.i815, label %wbody23.i805 + +wcond54.i815: ; preds = %wbody55.i817, %andand33.i811, %wcond22.i803 + %t81.i812 = phi i32 [ %t82.i816, %wbody55.i817 ], [ %t49.i801, %wcond22.i803 ], [ %t49.i801, %andand33.i811 ] ; <i32> [#uses=3] + %t64.i813 = icmp ult i32 %t81.i812, %line_arg830 ; <i1> [#uses=1] + br i1 %t64.i813, label %andand65.i822, label %Dt3net3ftp9FClient13FConnection13pListLineMFAaZS5t3net3ftp9FClient11FFileInfo10p_wordMFZAa.exit828 + +wbody55.i817: ; preds = %andand65.i822 + %t82.i816 = add i32 %t81.i812, 1 ; <i32> [#uses=1] + br label %wcond54.i815 + +andand65.i822: ; preds = %wcond54.i815 + %t74.i819 = getelementptr i8* %line_arg831, i32 %t81.i812 ; <i8*> [#uses=1] + %t75.i820 = load i8* %t74.i819 ; <i8> [#uses=1] + %t77.i821 = icmp eq i8 %t75.i820, 32 ; <i1> [#uses=1] + br i1 %t77.i821, label %wbody55.i817, label %Dt3net3ftp9FClient13FConnection13pListLineMFAaZS5t3net3ftp9FClient11FFileInfo10p_wordMFZAa.exit828 + +Dt3net3ftp9FClient13FConnection13pListLineMFAaZS5t3net3ftp9FClient11FFileInfo10p_wordMFZAa.exit828: ; preds = %andand65.i822, %wcond54.i815 + %t89.i824 = getelementptr i8* %line_arg831, i32 %.frame.0.6 ; <i8*> [#uses=4] + %t90.i825 = sub i32 %t49.i801, %.frame.0.6 ; <i32> [#uses=2] + %t63 = load i8* %t89.i824 ; <i8> [#uses=2] + br label %forcondi622 + +forcondi622: ; preds = %forbodyi626, %Dt3net3ftp9FClient13FConnection13pListLineMFAaZS5t3net3ftp9FClient11FFileInfo10p_wordMFZAa.exit828 + %l.0i618 = phi i32 [ 10, %Dt3net3ftp9FClient13FConnection13pListLineMFAaZS5t3net3ftp9FClient11FFileInfo10p_wordMFZAa.exit828 ], [ %t4i620, %forbodyi626 ] ; <i32> [#uses=2] + %p.0i619 = phi i8* [ getelementptr ([11 x i8]* @.str170, i32 0, i32 -1), %Dt3net3ftp9FClient13FConnection13pListLineMFAaZS5t3net3ftp9FClient11FFileInfo10p_wordMFZAa.exit828 ], [ %t7i623, %forbodyi626 ] ; <i8*> [#uses=1] + %t4i620 = add i32 %l.0i618, -1 ; <i32> [#uses=1] + %t5i621 = icmp eq i32 %l.0i618, 0 ; <i1> [#uses=1] + br i1 %t5i621, label %if65, label %forbodyi626 + +forbodyi626: ; preds = %forcondi622 + %t7i623 = getelementptr i8* %p.0i619, i32 1 ; <i8*> [#uses=3] + %t8i624 = load i8* %t7i623 ; <i8> [#uses=1] + %t12i625 = icmp eq i8 %t8i624, %t63 ; <i1> [#uses=1] + br i1 %t12i625, label %ifi630, label %forcondi622 + +ifi630: ; preds = %forbodyi626 + %t15i627 = ptrtoint i8* %t7i623 to i32 ; <i32> [#uses=1] + %t17i629 = sub i32 %t15i627, ptrtoint ([11 x i8]* @.str170 to i32) ; <i32> [#uses=1] + %phit636 = icmp eq i32 %t17i629, 10 ; <i1> [#uses=1] + br i1 %phit636, label %if65, label %e67 + +if65: ; preds = %ifi630, %forcondi622 + %t4i532 = icmp eq i32 %t49.i759, %.frame.0.3 ; <i1> [#uses=1] + br i1 %t4i532, label %Dt4x7c7I11V4tTaZ4tFAaKbKkZk.exit.i576, label %forcondi539 + +forcondi539: ; preds = %zi546, %if65 + %sign.1.i533 = phi i1 [ %sign.0.i543, %zi546 ], [ false, %if65 ] ; <i1> [#uses=2] + %l.0i534 = phi i32 [ %t33i545, %zi546 ], [ %t90.i783, %if65 ] ; <i32> [#uses=3] + %p.0i535 = phi i8* [ %t30i544, %zi546 ], [ %t89.i782, %if65 ] ; <i8*> [#uses=6] + %c.0.ini536 = phi i8* [ %t30i544, %zi546 ], [ %t89.i782, %if65 ] ; <i8*> [#uses=1] + %c.0i537 = load i8* %c.0.ini536 ; <i8> [#uses=2] + %t8i538 = icmp eq i32 %l.0i534, 0 ; <i1> [#uses=1] + br i1 %t8i538, label %endfori550, label %forbodyi540 + +forbodyi540: ; preds = %forcondi539 + switch i8 %c.0i537, label %endfori550 [ + i8 32, label %zi546 + i8 9, label %zi546 + i8 45, label %if20i541 + i8 43, label %if26i542 + ] + +if20i541: ; preds = %forbodyi540 + br label %zi546 + +if26i542: ; preds = %forbodyi540 + br label %zi546 + +zi546: ; preds = %if26i542, %if20i541, %forbodyi540, %forbodyi540 + %sign.0.i543 = phi i1 [ false, %if26i542 ], [ true, %if20i541 ], [ %sign.1.i533, %forbodyi540 ], [ %sign.1.i533, %forbodyi540 ] ; <i1> [#uses=1] + %t30i544 = getelementptr i8* %p.0i535, i32 1 ; <i8*> [#uses=2] + %t33i545 = add i32 %l.0i534, -1 ; <i32> [#uses=1] + br label %forcondi539 + +endfori550: ; preds = %forbodyi540, %forcondi539 + %t37i547 = icmp eq i8 %c.0i537, 48 ; <i1> [#uses=1] + %t39i548 = icmp sgt i32 %l.0i534, 1 ; <i1> [#uses=1] + %or.condi549 = and i1 %t37i547, %t39i548 ; <i1> [#uses=1] + br i1 %or.condi549, label %if40i554, label %endif41i564 + +if40i554: ; preds = %endfori550 + %t43i551 = getelementptr i8* %p.0i535, i32 1 ; <i8*> [#uses=2] + %t44i552 = load i8* %t43i551 ; <i8> [#uses=1] + %t45i553 = zext i8 %t44i552 to i32 ; <i32> [#uses=1] + switch i32 %t45i553, label %endif41i564 [ + i32 120, label %case46i556 + i32 88, label %case46i556 + i32 98, label %case51i558 + i32 66, label %case51i558 + i32 111, label %case56i560 + i32 79, label %case56i560 + ] + +case46i556: ; preds = %if40i554, %if40i554 + %t48i555 = getelementptr i8* %p.0i535, i32 2 ; <i8*> [#uses=1] + br label %endif41i564 + +case51i558: ; preds = %if40i554, %if40i554 + %t53i557 = getelementptr i8* %p.0i535, i32 2 ; <i8*> [#uses=1] + br label %endif41i564 + +case56i560: ; preds = %if40i554, %if40i554 + %t58i559 = getelementptr i8* %p.0i535, i32 2 ; <i8*> [#uses=1] + br label %endif41i564 + +endif41i564: ; preds = %case56i560, %case51i558, %case46i556, %if40i554, %endfori550 + %r.0i561 = phi i32 [ 0, %if40i554 ], [ 8, %case56i560 ], [ 2, %case51i558 ], [ 16, %case46i556 ], [ 0, %endfori550 ] ; <i32> [#uses=2] + %p.2i562 = phi i8* [ %t43i551, %if40i554 ], [ %t58i559, %case56i560 ], [ %t53i557, %case51i558 ], [ %t48i555, %case46i556 ], [ %p.0i535, %endfori550 ] ; <i8*> [#uses=2] + %t63i563 = icmp eq i32 %r.0i561, 0 ; <i1> [#uses=1] + br i1 %t63i563, label %Dt4x7c7I11V4tTaZ4tFAaKbKkZk.exit.i576, label %if70i568 + +if70i568: ; preds = %endif41i564 + br label %Dt4x7c7I11V4tTaZ4tFAaKbKkZk.exit.i576 + +Dt4x7c7I11V4tTaZ4tFAaKbKkZk.exit.i576: ; preds = %if70i568, %endif41i564, %if65 + %radix.0.i570 = phi i32 [ 0, %if65 ], [ %r.0i561, %if70i568 ], [ 10, %endif41i564 ] ; <i32> [#uses=2] + %p.1i571 = phi i8* [ %p.2i562, %if70i568 ], [ %t89.i782, %if65 ], [ %p.2i562, %endif41i564 ] ; <i8*> [#uses=1] + %t84i572 = ptrtoint i8* %p.1i571 to i32 ; <i32> [#uses=1] + %t85i573 = ptrtoint i8* %t89.i782 to i32 ; <i32> [#uses=1] + %t86i574 = sub i32 %t84i572, %t85i573 ; <i32> [#uses=2] + %t6.i575 = sub i32 %t90.i783, %t86i574 ; <i32> [#uses=1] + %t59i604 = zext i32 %radix.0.i570 to i64 ; <i64> [#uses=1] + br label %fcondi581 + +fcondi581: ; preds = %if55i610, %Dt4x7c7I11V4tTaZ4tFAaKbKkZk.exit.i576 + %value.0i577 = phi i64 [ 0, %Dt4x7c7I11V4tTaZ4tFAaKbKkZk.exit.i576 ], [ %t65i607, %if55i610 ] ; <i64> [#uses=1] + %fkey.0i579 = phi i32 [ 0, %Dt4x7c7I11V4tTaZ4tFAaKbKkZk.exit.i576 ], [ %t70i609, %if55i610 ] ; <i32> [#uses=3] + %t3i580 = icmp ult i32 %fkey.0i579, %t6.i575 ; <i1> [#uses=1] + br i1 %t3i580, label %fbodyi587, label %wcond.i422 + +fbodyi587: ; preds = %fcondi581 + %t5.s.i582 = add i32 %t86i574, %fkey.0i579 ; <i32> [#uses=1] + %t89.i782.s = add i32 %.frame.0.3, %t5.s.i582 ; <i32> [#uses=1] + %t5i583 = getelementptr i8* %line_arg831, i32 %t89.i782.s ; <i8*> [#uses=1] + %t6i584 = load i8* %t5i583 ; <i8> [#uses=6] + %t6.off84i585 = add i8 %t6i584, -48 ; <i8> [#uses=1] + %or.cond.i28.i586 = icmp ugt i8 %t6.off84i585, 9 ; <i1> [#uses=1] + br i1 %or.cond.i28.i586, label %ei590, label %endifi603 + +ei590: ; preds = %fbodyi587 + %t6.off83i588 = add i8 %t6i584, -97 ; <i8> [#uses=1] + %or.cond81i589 = icmp ugt i8 %t6.off83i588, 25 ; <i1> [#uses=1] + br i1 %or.cond81i589, label %e24i595, label %if22i592 + +if22i592: ; preds = %ei590 + %t27i591 = add i8 %t6i584, -39 ; <i8> [#uses=1] + br label %endifi603 + +e24i595: ; preds = %ei590 + %t6.offi593 = add i8 %t6i584, -65 ; <i8> [#uses=1] + %or.cond82i594 = icmp ugt i8 %t6.offi593, 25 ; <i1> [#uses=1] + br i1 %or.cond82i594, label %wcond.i422, label %if39i597 + +if39i597: ; preds = %e24i595 + %t44.i29.i596 = add i8 %t6i584, -7 ; <i8> [#uses=1] + br label %endifi603 + +endifi603: ; preds = %if39i597, %if22i592, %fbodyi587 + %c.0.i30.i598 = phi i8 [ %t27i591, %if22i592 ], [ %t44.i29.i596, %if39i597 ], [ %t6i584, %fbodyi587 ] ; <i8> [#uses=1] + %t48.i31.i599 = zext i8 %c.0.i30.i598 to i32 ; <i32> [#uses=1] + %t49i600 = add i32 %t48.i31.i599, 208 ; <i32> [#uses=1] + %t52i601 = and i32 %t49i600, 255 ; <i32> [#uses=2] + %t54i602 = icmp ult i32 %t52i601, %radix.0.i570 ; <i1> [#uses=1] + br i1 %t54i602, label %if55i610, label %wcond.i422 + +if55i610: ; preds = %endifi603 + %t61i605 = mul i64 %value.0i577, %t59i604 ; <i64> [#uses=1] + %t64i606 = zext i32 %t52i601 to i64 ; <i64> [#uses=1] + %t65i607 = add i64 %t61i605, %t64i606 ; <i64> [#uses=1] + %t70i609 = add i32 %fkey.0i579, 1 ; <i32> [#uses=1] + br label %fcondi581 + +e67: ; preds = %ifi630 + %t4i447 = icmp eq i32 %t49.i801, %.frame.0.6 ; <i1> [#uses=1] + br i1 %t4i447, label %Dt4x7c7I11V4tTaZ4tFAaKbKkZk.exit.i491, label %forcondi454 + +forcondi454: ; preds = %zi461, %e67 + %c.0i452 = phi i8 [ %c.0i452.pre, %zi461 ], [ %t63, %e67 ] ; <i8> [#uses=2] + %sign.1.i448 = phi i1 [ %sign.0.i458, %zi461 ], [ false, %e67 ] ; <i1> [#uses=2] + %l.0i449 = phi i32 [ %t33i460, %zi461 ], [ %t90.i825, %e67 ] ; <i32> [#uses=3] + %p.0i450 = phi i8* [ %t30i459, %zi461 ], [ %t89.i824, %e67 ] ; <i8*> [#uses=5] + %t8i453 = icmp eq i32 %l.0i449, 0 ; <i1> [#uses=1] + br i1 %t8i453, label %endfori465, label %forbodyi455 + +forbodyi455: ; preds = %forcondi454 + switch i8 %c.0i452, label %endfori465 [ + i8 32, label %zi461 + i8 9, label %zi461 + i8 45, label %if20i456 + i8 43, label %if26i457 + ] + +if20i456: ; preds = %forbodyi455 + br label %zi461 + +if26i457: ; preds = %forbodyi455 + br label %zi461 + +zi461: ; preds = %if26i457, %if20i456, %forbodyi455, %forbodyi455 + %sign.0.i458 = phi i1 [ false, %if26i457 ], [ true, %if20i456 ], [ %sign.1.i448, %forbodyi455 ], [ %sign.1.i448, %forbodyi455 ] ; <i1> [#uses=1] + %t30i459 = getelementptr i8* %p.0i450, i32 1 ; <i8*> [#uses=2] + %t33i460 = add i32 %l.0i449, -1 ; <i32> [#uses=1] + %c.0i452.pre = load i8* %t30i459 ; <i8> [#uses=1] + br label %forcondi454 + +endfori465: ; preds = %forbodyi455, %forcondi454 + %t37i462 = icmp eq i8 %c.0i452, 48 ; <i1> [#uses=1] + %t39i463 = icmp sgt i32 %l.0i449, 1 ; <i1> [#uses=1] + %or.condi464 = and i1 %t37i462, %t39i463 ; <i1> [#uses=1] + br i1 %or.condi464, label %if40i469, label %endif41i479 + +if40i469: ; preds = %endfori465 + %t43i466 = getelementptr i8* %p.0i450, i32 1 ; <i8*> [#uses=2] + %t44i467 = load i8* %t43i466 ; <i8> [#uses=1] + %t45i468 = zext i8 %t44i467 to i32 ; <i32> [#uses=1] + switch i32 %t45i468, label %endif41i479 [ + i32 120, label %case46i471 + i32 111, label %case56i475 + ] + +case46i471: ; preds = %if40i469 + %t48i470 = getelementptr i8* %p.0i450, i32 2 ; <i8*> [#uses=1] + br label %endif41i479 + +case56i475: ; preds = %if40i469 + %t58i474 = getelementptr i8* %p.0i450, i32 2 ; <i8*> [#uses=1] + br label %endif41i479 + +endif41i479: ; preds = %case56i475, %case46i471, %if40i469, %endfori465 + %r.0i476 = phi i32 [ 0, %if40i469 ], [ 8, %case56i475 ], [ 16, %case46i471 ], [ 0, %endfori465 ] ; <i32> [#uses=2] + %p.2i477 = phi i8* [ %t43i466, %if40i469 ], [ %t58i474, %case56i475 ], [ %t48i470, %case46i471 ], [ %p.0i450, %endfori465 ] ; <i8*> [#uses=2] + %t63i478 = icmp eq i32 %r.0i476, 0 ; <i1> [#uses=1] + br i1 %t63i478, label %Dt4x7c7I11V4tTaZ4tFAaKbKkZk.exit.i491, label %if70i483 + +if70i483: ; preds = %endif41i479 + br label %Dt4x7c7I11V4tTaZ4tFAaKbKkZk.exit.i491 + +Dt4x7c7I11V4tTaZ4tFAaKbKkZk.exit.i491: ; preds = %if70i483, %endif41i479, %e67 + %radix.0.i485 = phi i32 [ 0, %e67 ], [ %r.0i476, %if70i483 ], [ 10, %endif41i479 ] ; <i32> [#uses=2] + %p.1i486 = phi i8* [ %p.2i477, %if70i483 ], [ %t89.i824, %e67 ], [ %p.2i477, %endif41i479 ] ; <i8*> [#uses=1] + %t84i487 = ptrtoint i8* %p.1i486 to i32 ; <i32> [#uses=1] + %t85i488 = ptrtoint i8* %t89.i824 to i32 ; <i32> [#uses=1] + %t86i489 = sub i32 %t84i487, %t85i488 ; <i32> [#uses=2] + %ttt = sub i32 %t90.i825, %t86i489 ; <i32> [#uses=1] + %t59i519 = zext i32 %radix.0.i485 to i64 ; <i64> [#uses=1] + br label %fcondi496 + +fcondi496: ; preds = %if55i525, %Dt4x7c7I11V4tTaZ4tFAaKbKkZk.exit.i491 + %value.0i492 = phi i64 [ 0, %Dt4x7c7I11V4tTaZ4tFAaKbKkZk.exit.i491 ], [ %t65i522, %if55i525 ] ; <i64> [#uses=1] + %fkey.0i494 = phi i32 [ 0, %Dt4x7c7I11V4tTaZ4tFAaKbKkZk.exit.i491 ], [ %t70i524, %if55i525 ] ; <i32> [#uses=3] + %t3i495 = icmp ult i32 %fkey.0i494, %ttt ; <i1> [#uses=1] + br i1 %t3i495, label %fbodyi502, label %wcond.i422 + +fbodyi502: ; preds = %fcondi496 + %t5.s.i497 = add i32 %t86i489, %fkey.0i494 ; <i32> [#uses=1] + %t89.i824.s = add i32 %.frame.0.6, %t5.s.i497 ; <i32> [#uses=1] + %t5i498 = getelementptr i8* %line_arg831, i32 %t89.i824.s ; <i8*> [#uses=1] + %t6i499 = load i8* %t5i498 ; <i8> [#uses=6] + %t6.off84i500 = add i8 %t6i499, -48 ; <i8> [#uses=1] + %or.cond.i28.i501 = icmp ugt i8 %t6.off84i500, 9 ; <i1> [#uses=1] + br i1 %or.cond.i28.i501, label %ei505, label %endifi518 + +ei505: ; preds = %fbodyi502 + %t6.off83i503 = add i8 %t6i499, -97 ; <i8> [#uses=1] + %or.cond81i504 = icmp ugt i8 %t6.off83i503, 25 ; <i1> [#uses=1] + br i1 %or.cond81i504, label %e24i510, label %if22i507 + +if22i507: ; preds = %ei505 + %t27i506 = add i8 %t6i499, -39 ; <i8> [#uses=1] + br label %endifi518 + +e24i510: ; preds = %ei505 + %t6.offi508 = add i8 %t6i499, -65 ; <i8> [#uses=1] + %or.cond82i509 = icmp ugt i8 %t6.offi508, 25 ; <i1> [#uses=1] + br i1 %or.cond82i509, label %wcond.i422, label %if39i512 + +if39i512: ; preds = %e24i510 + %t44.i29.i511 = add i8 %t6i499, -7 ; <i8> [#uses=1] + br label %endifi518 + +endifi518: ; preds = %if39i512, %if22i507, %fbodyi502 + %c.0.i30.i513 = phi i8 [ %t27i506, %if22i507 ], [ %t44.i29.i511, %if39i512 ], [ %t6i499, %fbodyi502 ] ; <i8> [#uses=1] + %t48.i31.i514 = zext i8 %c.0.i30.i513 to i32 ; <i32> [#uses=1] + %t49i515 = add i32 %t48.i31.i514, 208 ; <i32> [#uses=1] + %t52i516 = and i32 %t49i515, 255 ; <i32> [#uses=2] + %t54i517 = icmp ult i32 %t52i516, %radix.0.i485 ; <i1> [#uses=1] + br i1 %t54i517, label %if55i525, label %wcond.i422 + +if55i525: ; preds = %endifi518 + %t61i520 = mul i64 %value.0i492, %t59i519 ; <i64> [#uses=1] + %t64i521 = zext i32 %t52i516 to i64 ; <i64> [#uses=1] + %t65i522 = add i64 %t61i520, %t64i521 ; <i64> [#uses=1] + %t70i524 = add i32 %fkey.0i494, 1 ; <i32> [#uses=1] + br label %fcondi496 + +wcond.i422: ; preds = %e40.i, %endifi518, %e24i510, %fcondi496, %endifi603, %e24i595, %fcondi581 + %sarg60.pn.i = phi i8* [ %p.0.i, %e40.i ], [ undef, %fcondi496 ], [ undef, %e24i510 ], [ undef, %endifi518 ], [ undef, %endifi603 ], [ undef, %e24i595 ], [ undef, %fcondi581 ] ; <i8*> [#uses=3] + %start_arg.pn.i = phi i32 [ %t49.i443, %e40.i ], [ 0, %fcondi496 ], [ 0, %e24i510 ], [ 0, %endifi518 ], [ 0, %endifi603 ], [ 0, %e24i595 ], [ 0, %fcondi581 ] ; <i32> [#uses=3] + %extent.0.i = phi i32 [ %t51.i, %e40.i ], [ undef, %fcondi496 ], [ undef, %e24i510 ], [ undef, %endifi518 ], [ undef, %endifi603 ], [ undef, %e24i595 ], [ undef, %fcondi581 ] ; <i32> [#uses=3] + %p.0.i = getelementptr i8* %sarg60.pn.i, i32 %start_arg.pn.i ; <i8*> [#uses=2] + %p.0.s63.i = add i32 %start_arg.pn.i, -1 ; <i32> [#uses=1] + %t2i424 = getelementptr i8* %sarg60.pn.i, i32 %p.0.s63.i ; <i8*> [#uses=1] + br label %forcondi430 + +forcondi430: ; preds = %forbodyi434, %wcond.i422 + %l.0i426 = phi i32 [ %extent.0.i, %wcond.i422 ], [ %t4i428, %forbodyi434 ] ; <i32> [#uses=2] + %p.0i427 = phi i8* [ %t2i424, %wcond.i422 ], [ %t7i431, %forbodyi434 ] ; <i8*> [#uses=1] + %t4i428 = add i32 %l.0i426, -1 ; <i32> [#uses=1] + %t5i429 = icmp eq i32 %l.0i426, 0 ; <i1> [#uses=1] + br i1 %t5i429, label %e.i441, label %forbodyi434 + +forbodyi434: ; preds = %forcondi430 + %t7i431 = getelementptr i8* %p.0i427, i32 1 ; <i8*> [#uses=3] + %t8i432 = load i8* %t7i431 ; <i8> [#uses=1] + %t12i433 = icmp eq i8 %t8i432, 32 ; <i1> [#uses=1] + br i1 %t12i433, label %ifi438, label %forcondi430 + +ifi438: ; preds = %forbodyi434 + %t15i435 = ptrtoint i8* %t7i431 to i32 ; <i32> [#uses=1] + %t16i436 = ptrtoint i8* %p.0.i to i32 ; <i32> [#uses=1] + %t17i437 = sub i32 %t15i435, %t16i436 ; <i32> [#uses=1] + br label %e.i441 + +e.i441: ; preds = %ifi438, %forcondi430 + %t2561.i = phi i32 [ %t17i437, %ifi438 ], [ %extent.0.i, %forcondi430 ] ; <i32> [#uses=2] + %p.0.s.i = add i32 %start_arg.pn.i, %t2561.i ; <i32> [#uses=1] + %t32.s.i = add i32 %p.0.s.i, -1 ; <i32> [#uses=1] + %t2i.i = getelementptr i8* %sarg60.pn.i, i32 %t32.s.i ; <i8*> [#uses=1] + br label %forbodyi.i + +forbodyi.i: ; preds = %forbodyi.i, %e.i441 + %p.0i.i = phi i8* [ %t2i.i, %e.i441 ], [ %t7i.i, %forbodyi.i ] ; <i8*> [#uses=1] + %s2.0i.i = phi i8* [ getelementptr ([5 x i8]* @.str171, i32 0, i32 0), %e.i441 ], [ %t11i.i, %forbodyi.i ] ; <i8*> [#uses=2] + %t7i.i = getelementptr i8* %p.0i.i, i32 1 ; <i8*> [#uses=2] + %t8i.i = load i8* %t7i.i ; <i8> [#uses=1] + %t11i.i = getelementptr i8* %s2.0i.i, i32 1 ; <i8*> [#uses=1] + %t12i.i = load i8* %s2.0i.i ; <i8> [#uses=1] + %t14i.i = icmp eq i8 %t8i.i, %t12i.i ; <i1> [#uses=1] + br i1 %t14i.i, label %forbodyi.i, label %e40.i + +e40.i: ; preds = %forbodyi.i + %t49.i443 = add i32 %t2561.i, 1 ; <i32> [#uses=2] + %t51.i = sub i32 %extent.0.i, %t49.i443 ; <i32> [#uses=1] + br label %wcond.i422 +} diff --git a/test/CodeGen/PowerPC/trampoline.ll b/test/CodeGen/PowerPC/trampoline.ll index 530c782..bc05bb1 100644 --- a/test/CodeGen/PowerPC/trampoline.ll +++ b/test/CodeGen/PowerPC/trampoline.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc32 | grep {__trampoline_setup} +; RUN: llc < %s -march=ppc32 | grep {__trampoline_setup} module asm "\09.lazy_reference .objc_class_name_NSImageRep" module asm "\09.objc_class_name_NSBitmapImageRep=0" diff --git a/test/CodeGen/PowerPC/unsafe-math.ll b/test/CodeGen/PowerPC/unsafe-math.ll index d211b3b..ef97912 100644 --- a/test/CodeGen/PowerPC/unsafe-math.ll +++ b/test/CodeGen/PowerPC/unsafe-math.ll @@ -1,5 +1,5 @@ -; RUN: llvm-as < %s | llc -march=ppc32 | grep fmul | count 2 -; RUN: llvm-as < %s | llc -march=ppc32 -enable-unsafe-fp-math | \ +; RUN: llc < %s -march=ppc32 | grep fmul | count 2 +; RUN: llc < %s -march=ppc32 -enable-unsafe-fp-math | \ ; RUN: grep fmul | count 1 define double @foo(double %X) { diff --git a/test/CodeGen/PowerPC/vcmp-fold.ll b/test/CodeGen/PowerPC/vcmp-fold.ll index 815bb0a..7a42c27 100644 --- a/test/CodeGen/PowerPC/vcmp-fold.ll +++ b/test/CodeGen/PowerPC/vcmp-fold.ll @@ -1,6 +1,6 @@ ; This should fold the "vcmpbfp." and "vcmpbfp" instructions into a single ; "vcmpbfp.". -; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | grep vcmpbfp | count 1 +; RUN: llc < %s -march=ppc32 -mcpu=g5 | grep vcmpbfp | count 1 define void @test(<4 x float>* %x, <4 x float>* %y, i32* %P) { diff --git a/test/CodeGen/PowerPC/vec_br_cmp.ll b/test/CodeGen/PowerPC/vec_br_cmp.ll index 6d79967..c34d850 100644 --- a/test/CodeGen/PowerPC/vec_br_cmp.ll +++ b/test/CodeGen/PowerPC/vec_br_cmp.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 -o %t -f +; RUN: llc < %s -march=ppc32 -mcpu=g5 -o %t ; RUN: grep vcmpeqfp. %t ; RUN: not grep mfcr %t diff --git a/test/CodeGen/PowerPC/vec_call.ll b/test/CodeGen/PowerPC/vec_call.ll index 8e7a08e..4511315 100644 --- a/test/CodeGen/PowerPC/vec_call.ll +++ b/test/CodeGen/PowerPC/vec_call.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 +; RUN: llc < %s -march=ppc32 -mcpu=g5 define <4 x i32> @test_arg(<4 x i32> %A, <4 x i32> %B) { %C = add <4 x i32> %A, %B ; <<4 x i32>> [#uses=1] diff --git a/test/CodeGen/PowerPC/vec_constants.ll b/test/CodeGen/PowerPC/vec_constants.ll index c4b42b9e..32c6f48 100644 --- a/test/CodeGen/PowerPC/vec_constants.ll +++ b/test/CodeGen/PowerPC/vec_constants.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | not grep CPI +; RUN: llc < %s -march=ppc32 -mcpu=g5 | not grep CPI define void @test1(<4 x i32>* %P1, <4 x i32>* %P2, <4 x float>* %P3) { %tmp = load <4 x i32>* %P1 ; <<4 x i32>> [#uses=1] diff --git a/test/CodeGen/PowerPC/vec_fneg.ll b/test/CodeGen/PowerPC/vec_fneg.ll index 9fdbffd..e01e659 100644 --- a/test/CodeGen/PowerPC/vec_fneg.ll +++ b/test/CodeGen/PowerPC/vec_fneg.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | grep vsubfp +; RUN: llc < %s -march=ppc32 -mcpu=g5 | grep vsubfp define void @t(<4 x float>* %A) { %tmp2 = load <4 x float>* %A diff --git a/test/CodeGen/PowerPC/vec_insert.ll b/test/CodeGen/PowerPC/vec_insert.ll index 04bbe65..185454c 100644 --- a/test/CodeGen/PowerPC/vec_insert.ll +++ b/test/CodeGen/PowerPC/vec_insert.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | grep sth +; RUN: llc < %s -march=ppc32 -mcpu=g5 | grep sth define <8 x i16> @insert(<8 x i16> %foo, i16 %a) nounwind { entry: diff --git a/test/CodeGen/PowerPC/vec_misaligned.ll b/test/CodeGen/PowerPC/vec_misaligned.ll index 15376cae..d7ed64a5 100644 --- a/test/CodeGen/PowerPC/vec_misaligned.ll +++ b/test/CodeGen/PowerPC/vec_misaligned.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 +; RUN: llc < %s -march=ppc32 -mcpu=g5 target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128" target triple = "powerpc-apple-darwin8" diff --git a/test/CodeGen/PowerPC/vec_mul.ll b/test/CodeGen/PowerPC/vec_mul.ll index b061fa9..80f4de4 100644 --- a/test/CodeGen/PowerPC/vec_mul.ll +++ b/test/CodeGen/PowerPC/vec_mul.ll @@ -1,5 +1,5 @@ -; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | not grep mullw -; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | grep vmsumuhm +; RUN: llc < %s -march=ppc32 -mcpu=g5 | not grep mullw +; RUN: llc < %s -march=ppc32 -mcpu=g5 | grep vmsumuhm define <4 x i32> @test_v4i32(<4 x i32>* %X, <4 x i32>* %Y) { %tmp = load <4 x i32>* %X ; <<4 x i32>> [#uses=1] diff --git a/test/CodeGen/PowerPC/vec_perf_shuffle.ll b/test/CodeGen/PowerPC/vec_perf_shuffle.ll index 5bb1b60..2c3594d 100644 --- a/test/CodeGen/PowerPC/vec_perf_shuffle.ll +++ b/test/CodeGen/PowerPC/vec_perf_shuffle.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | not grep vperm +; RUN: llc < %s -march=ppc32 -mcpu=g5 | not grep vperm define <4 x float> @test_uu72(<4 x float>* %P1, <4 x float>* %P2) { %V1 = load <4 x float>* %P1 ; <<4 x float>> [#uses=1] diff --git a/test/CodeGen/PowerPC/vec_shift.ll b/test/CodeGen/PowerPC/vec_shift.ll index 0cc699c..646fb5f 100644 --- a/test/CodeGen/PowerPC/vec_shift.ll +++ b/test/CodeGen/PowerPC/vec_shift.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 +; RUN: llc < %s -march=ppc32 -mcpu=g5 ; PR3628 define void @update(<4 x i32> %val, <4 x i32>* %dst) nounwind { diff --git a/test/CodeGen/PowerPC/vec_shuffle.ll b/test/CodeGen/PowerPC/vec_shuffle.ll index 1289dca..8270632 100644 --- a/test/CodeGen/PowerPC/vec_shuffle.ll +++ b/test/CodeGen/PowerPC/vec_shuffle.ll @@ -1,6 +1,6 @@ -; RUN: llvm-as < %s | opt -instcombine | \ +; RUN: opt < %s -instcombine | \ ; RUN: llc -march=ppc32 -mcpu=g5 | not grep vperm -; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 > %t +; RUN: llc < %s -march=ppc32 -mcpu=g5 > %t ; RUN: grep vsldoi %t | count 2 ; RUN: grep vmrgh %t | count 7 ; RUN: grep vmrgl %t | count 6 diff --git a/test/CodeGen/PowerPC/vec_splat.ll b/test/CodeGen/PowerPC/vec_splat.ll index 7b7e4fe..6123728 100644 --- a/test/CodeGen/PowerPC/vec_splat.ll +++ b/test/CodeGen/PowerPC/vec_splat.ll @@ -1,7 +1,7 @@ ; Test that vectors are scalarized/lowered correctly. -; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g3 | \ +; RUN: llc < %s -march=ppc32 -mcpu=g3 | \ ; RUN: grep stfs | count 4 -; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 -o %t -f +; RUN: llc < %s -march=ppc32 -mcpu=g5 -o %t ; RUN: grep vspltw %t | count 2 ; RUN: grep vsplti %t | count 3 ; RUN: grep vsplth %t | count 1 diff --git a/test/CodeGen/PowerPC/vec_vrsave.ll b/test/CodeGen/PowerPC/vec_vrsave.ll index 06769f6..2a03d58 100644 --- a/test/CodeGen/PowerPC/vec_vrsave.ll +++ b/test/CodeGen/PowerPC/vec_vrsave.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 -o %t -f +; RUN: llc < %s -march=ppc32 -mcpu=g5 -o %t ; RUN: grep vrlw %t ; RUN: not grep spr %t ; RUN: not grep vrsave %t diff --git a/test/CodeGen/PowerPC/vec_zero.ll b/test/CodeGen/PowerPC/vec_zero.ll index 7350e91..f862b2c 100644 --- a/test/CodeGen/PowerPC/vec_zero.ll +++ b/test/CodeGen/PowerPC/vec_zero.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | grep vxor +; RUN: llc < %s -march=ppc32 -mcpu=g5 | grep vxor define void @foo(<4 x float>* %P) { %T = load <4 x float>* %P ; <<4 x float>> [#uses=1] diff --git a/test/CodeGen/PowerPC/vector-identity-shuffle.ll b/test/CodeGen/PowerPC/vector-identity-shuffle.ll index aefd266..dfa2e35 100644 --- a/test/CodeGen/PowerPC/vector-identity-shuffle.ll +++ b/test/CodeGen/PowerPC/vector-identity-shuffle.ll @@ -1,5 +1,5 @@ -; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | grep test: -; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | not grep vperm +; RUN: llc < %s -march=ppc32 -mcpu=g5 | grep test: +; RUN: llc < %s -march=ppc32 -mcpu=g5 | not grep vperm define void @test(<4 x float>* %tmp2.i) { %tmp2.i.upgrd.1 = load <4 x float>* %tmp2.i ; <<4 x float>> [#uses=4] diff --git a/test/CodeGen/PowerPC/vector.ll b/test/CodeGen/PowerPC/vector.ll index a6c17b4..ee4da31 100644 --- a/test/CodeGen/PowerPC/vector.ll +++ b/test/CodeGen/PowerPC/vector.ll @@ -1,6 +1,6 @@ ; Test that vectors are scalarized/lowered correctly. -; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 > %t -; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g3 > %t +; RUN: llc < %s -march=ppc32 -mcpu=g5 > %t +; RUN: llc < %s -march=ppc32 -mcpu=g3 > %t %d8 = type <8 x double> %f1 = type <1 x float> |
