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-rw-r--r--test/CodeGen/Mips/2008-07-31-fcopysign.ll4
-rw-r--r--test/CodeGen/Mips/2011-05-26-BranchKillsVreg.ll43
-rw-r--r--test/CodeGen/Mips/alloca.ll31
-rw-r--r--test/CodeGen/Mips/atomic.ll253
-rw-r--r--test/CodeGen/Mips/blockaddr.ll16
-rwxr-xr-xtest/CodeGen/Mips/cmov.ll18
-rw-r--r--test/CodeGen/Mips/double2int.ll8
-rw-r--r--test/CodeGen/Mips/eh.ll78
-rw-r--r--test/CodeGen/Mips/fcopysign.ll55
-rw-r--r--test/CodeGen/Mips/frame-address.ll12
-rw-r--r--test/CodeGen/Mips/gprestore.ll32
-rw-r--r--test/CodeGen/Mips/i64arg.ll34
-rw-r--r--test/CodeGen/Mips/internalfunc.ll2
-rw-r--r--test/CodeGen/Mips/largeimmprinting.ll23
-rw-r--r--test/CodeGen/Mips/o32_cc_byval.ll127
-rw-r--r--test/CodeGen/Mips/o32_cc_vararg.ll75
-rw-r--r--test/CodeGen/Mips/tls.ll46
-rw-r--r--test/CodeGen/Mips/weak.ll12
18 files changed, 818 insertions, 51 deletions
diff --git a/test/CodeGen/Mips/2008-07-31-fcopysign.ll b/test/CodeGen/Mips/2008-07-31-fcopysign.ll
index 47382f9..f152acc 100644
--- a/test/CodeGen/Mips/2008-07-31-fcopysign.ll
+++ b/test/CodeGen/Mips/2008-07-31-fcopysign.ll
@@ -2,6 +2,10 @@
; RUN: grep abs.s %t | count 1
; RUN: grep neg.s %t | count 1
+; FIXME: Should not emit abs.s or neg.s since these instructions produce
+; incorrect results if the operand is NaN.
+; REQUIRES: disabled
+
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
target triple = "mipsallegrexel-unknown-psp-elf"
diff --git a/test/CodeGen/Mips/2011-05-26-BranchKillsVreg.ll b/test/CodeGen/Mips/2011-05-26-BranchKillsVreg.ll
new file mode 100644
index 0000000..1255949
--- /dev/null
+++ b/test/CodeGen/Mips/2011-05-26-BranchKillsVreg.ll
@@ -0,0 +1,43 @@
+; RUN: llc < %s -verify-coalescing
+; PR10046
+;
+; PHI elimination splits the critical edge from %while.end415 to %if.end427.
+; This requires updating the BNE-J terminators to a BEQ. The BNE instruction
+; kills a virtual register, and LiveVariables must be updated with the new kill
+; instruction.
+
+target datalayout = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-n32"
+target triple = "mips-ellcc-linux"
+
+define i32 @mergesort(i8* %base, i32 %nmemb, i32 %size, i32 (i8*, i8*)* nocapture %cmp) nounwind {
+entry:
+ br i1 undef, label %return, label %if.end13
+
+if.end13: ; preds = %entry
+ br label %while.body
+
+while.body: ; preds = %while.body, %if.end13
+ %list1.0482 = phi i8* [ %base, %if.end13 ], [ null, %while.body ]
+ br i1 undef, label %while.end415, label %while.body
+
+while.end415: ; preds = %while.body
+ br i1 undef, label %if.then419, label %if.end427
+
+if.then419: ; preds = %while.end415
+ %call425 = tail call i8* @memmove(i8* %list1.0482, i8* undef, i32 undef) nounwind
+ br label %if.end427
+
+if.end427: ; preds = %if.then419, %while.end415
+ %list2.1 = phi i8* [ undef, %if.then419 ], [ %list1.0482, %while.end415 ]
+ tail call void @free(i8* %list2.1)
+ unreachable
+
+return: ; preds = %entry
+ ret i32 -1
+}
+
+
+declare i8* @memmove(i8*, i8*, i32)
+
+declare void @free(i8*)
+
diff --git a/test/CodeGen/Mips/alloca.ll b/test/CodeGen/Mips/alloca.ll
new file mode 100644
index 0000000..50eeecf
--- /dev/null
+++ b/test/CodeGen/Mips/alloca.ll
@@ -0,0 +1,31 @@
+; RUN: llc -march=mipsel -mcpu=4ke < %s | FileCheck %s
+
+define i32 @twoalloca(i32 %size) nounwind {
+entry:
+; CHECK: subu $[[T0:[0-9]+]], $sp, $[[SZ:[0-9]+]]
+; CHECK: addu $sp, $zero, $[[T0]]
+; CHECK: addu $[[SP1:[0-9]+]], $zero, $sp
+; CHECK: subu $[[T1:[0-9]+]], $sp, $[[SZ]]
+; CHECK: addu $sp, $zero, $[[T1]]
+; CHECK: addu $[[SP2:[0-9]+]], $zero, $sp
+; CHECK: lw $25, %call16(foo)($gp)
+; CHECK: addiu $4, $[[SP1]], 24
+; CHECK: jalr $25
+; CHECK: lw $25, %call16(foo)($gp)
+; CHECK: addiu $4, $[[SP2]], 24
+; CHECK: jalr $25
+ %tmp1 = alloca i8, i32 %size, align 4
+ %add.ptr = getelementptr inbounds i8* %tmp1, i32 5
+ store i8 97, i8* %add.ptr, align 1
+ %tmp4 = alloca i8, i32 %size, align 4
+ call void @foo2(double 1.000000e+00, double 2.000000e+00, i32 3) nounwind
+ %call = call i32 @foo(i8* %tmp1) nounwind
+ %call7 = call i32 @foo(i8* %tmp4) nounwind
+ %add = add nsw i32 %call7, %call
+ ret i32 %add
+}
+
+declare void @foo2(double, double, i32)
+
+declare i32 @foo(i8*)
+
diff --git a/test/CodeGen/Mips/atomic.ll b/test/CodeGen/Mips/atomic.ll
new file mode 100644
index 0000000..2d5555b
--- /dev/null
+++ b/test/CodeGen/Mips/atomic.ll
@@ -0,0 +1,253 @@
+; RUN: llc -march=mipsel -mcpu=mips2 < %s | FileCheck %s
+
+
+declare i32 @llvm.atomic.load.add.i32.p0i32(i32* nocapture, i32) nounwind
+declare i32 @llvm.atomic.load.nand.i32.p0i32(i32* nocapture, i32) nounwind
+declare i32 @llvm.atomic.swap.i32.p0i32(i32* nocapture, i32) nounwind
+declare i32 @llvm.atomic.cmp.swap.i32.p0i32(i32* nocapture, i32, i32) nounwind
+
+declare i8 @llvm.atomic.load.add.i8.p0i8(i8* nocapture, i8) nounwind
+declare i8 @llvm.atomic.load.sub.i8.p0i8(i8* nocapture, i8) nounwind
+declare i8 @llvm.atomic.load.nand.i8.p0i8(i8* nocapture, i8) nounwind
+declare i8 @llvm.atomic.swap.i8.p0i8(i8* nocapture, i8) nounwind
+declare i8 @llvm.atomic.cmp.swap.i8.p0i8(i8* nocapture, i8, i8) nounwind
+
+
+@x = common global i32 0, align 4
+
+define i32 @AtomicLoadAdd32(i32 %incr) nounwind {
+entry:
+ %0 = call i32 @llvm.atomic.load.add.i32.p0i32(i32* @x, i32 %incr)
+ ret i32 %0
+
+; CHECK: AtomicLoadAdd32:
+; CHECK: lw $[[R0:[0-9]+]], %got(x)($gp)
+; CHECK: $[[BB0:[A-Z_0-9]+]]:
+; CHECK: ll $[[R1:[0-9]+]], 0($[[R0]])
+; CHECK: or $2, $zero, $[[R1]]
+; CHECK: addu $[[R2:[0-9]+]], $[[R1]], $4
+; CHECK: sc $[[R2]], 0($[[R0]])
+; CHECK: beq $[[R2]], $zero, $[[BB0]]
+}
+
+define i32 @AtomicLoadNand32(i32 %incr) nounwind {
+entry:
+ %0 = call i32 @llvm.atomic.load.nand.i32.p0i32(i32* @x, i32 %incr)
+ ret i32 %0
+
+; CHECK: AtomicLoadNand32:
+; CHECK: lw $[[R0:[0-9]+]], %got(x)($gp)
+; CHECK: $[[BB0:[A-Z_0-9]+]]:
+; CHECK: ll $[[R1:[0-9]+]], 0($[[R0]])
+; CHECK: or $2, $zero, $[[R1]]
+; CHECK: and $[[R1]], $[[R1]], $4
+; CHECK: nor $[[R2:[0-9]+]], $zero, $[[R1]]
+; CHECK: sc $[[R2]], 0($[[R0]])
+; CHECK: beq $[[R2]], $zero, $[[BB0]]
+}
+
+define i32 @AtomicSwap32(i32 %oldval) nounwind {
+entry:
+ %0 = call i32 @llvm.atomic.swap.i32.p0i32(i32* @x, i32 %oldval)
+ ret i32 %0
+
+; CHECK: AtomicSwap32:
+; CHECK: lw $[[R0:[0-9]+]], %got(x)($gp)
+; CHECK: sw $4, [[OFFSET:[0-9]+]]($sp)
+; CHECK: $[[BB0:[A-Z_0-9]+]]:
+; CHECK: ll $[[R1:[0-9]+]], 0($[[R0]])
+; CHECK: or $2, $zero, $[[R1]]
+; CHECK: lw $[[R2:[0-9]+]], [[OFFSET]]($sp)
+; CHECK: or $[[R3:[0-9]+]], $zero, $[[R2]]
+; CHECK: sc $[[R3]], 0($[[R0]])
+; CHECK: beq $[[R3]], $zero, $[[BB0]]
+}
+
+define i32 @AtomicCmpSwap32(i32 %oldval, i32 %newval) nounwind {
+entry:
+ %0 = call i32 @llvm.atomic.cmp.swap.i32.p0i32(i32* @x, i32 %oldval, i32 %newval)
+ ret i32 %0
+
+; CHECK: AtomicCmpSwap32:
+; CHECK: lw $[[R0:[0-9]+]], %got(x)($gp)
+; CHECK: sw $5, [[OFFSET:[0-9]+]]($sp)
+; CHECK: $[[BB0:[A-Z_0-9]+]]:
+; CHECK: ll $2, 0($[[R0]])
+; CHECK: bne $2, $4, $[[BB1:[A-Z_0-9]+]]
+; CHECK: lw $[[R1:[0-9]+]], [[OFFSET]]($sp)
+; CHECK: or $[[R2:[0-9]+]], $zero, $[[R1]]
+; CHECK: sc $[[R2]], 0($[[R0]])
+; CHECK: beq $[[R2]], $zero, $[[BB0]]
+; CHECK: $[[BB1]]:
+}
+
+
+
+@y = common global i8 0, align 1
+
+define signext i8 @AtomicLoadAdd8(i8 signext %incr) nounwind {
+entry:
+ %0 = call i8 @llvm.atomic.load.add.i8.p0i8(i8* @y, i8 %incr)
+ ret i8 %0
+
+; CHECK: AtomicLoadAdd8:
+; CHECK: lw $[[R0:[0-9]+]], %got(y)($gp)
+; CHECK: addiu $[[R1:[0-9]+]], $zero, -4
+; CHECK: and $[[R2:[0-9]+]], $[[R0]], $[[R1]]
+; CHECK: andi $[[R3:[0-9]+]], $[[R0]], 3
+; CHECK: sll $[[R4:[0-9]+]], $[[R3]], 3
+; CHECK: ori $[[R5:[0-9]+]], $zero, 255
+; CHECK: sll $[[R6:[0-9]+]], $[[R5]], $[[R4]]
+; CHECK: nor $[[R7:[0-9]+]], $zero, $[[R6]]
+; CHECK: andi $[[R8:[0-9]+]], $4, 255
+; CHECK: sll $[[R9:[0-9]+]], $[[R8]], $[[R4]]
+
+; CHECK: $[[BB0:[A-Z_0-9]+]]:
+; CHECK: ll $[[R10:[0-9]+]], 0($[[R2]])
+; CHECK: addu $[[R11:[0-9]+]], $[[R10]], $[[R9]]
+; CHECK: and $[[R12:[0-9]+]], $[[R11]], $[[R6]]
+; CHECK: and $[[R13:[0-9]+]], $[[R10]], $[[R7]]
+; CHECK: or $[[R14:[0-9]+]], $[[R13]], $[[R12]]
+; CHECK: sc $[[R14]], 0($[[R2]])
+; CHECK: beq $[[R14]], $zero, $[[BB0]]
+
+; CHECK: and $[[R15:[0-9]+]], $[[R10]], $[[R6]]
+; CHECK: srl $[[R16:[0-9]+]], $[[R15]], $[[R4]]
+; CHECK: sll $[[R17:[0-9]+]], $[[R16]], 24
+; CHECK: sra $2, $[[R17]], 24
+}
+
+define signext i8 @AtomicLoadSub8(i8 signext %incr) nounwind {
+entry:
+ %0 = call i8 @llvm.atomic.load.sub.i8.p0i8(i8* @y, i8 %incr)
+ ret i8 %0
+
+; CHECK: AtomicLoadSub8:
+; CHECK: lw $[[R0:[0-9]+]], %got(y)($gp)
+; CHECK: addiu $[[R1:[0-9]+]], $zero, -4
+; CHECK: and $[[R2:[0-9]+]], $[[R0]], $[[R1]]
+; CHECK: andi $[[R3:[0-9]+]], $[[R0]], 3
+; CHECK: sll $[[R4:[0-9]+]], $[[R3]], 3
+; CHECK: ori $[[R5:[0-9]+]], $zero, 255
+; CHECK: sll $[[R6:[0-9]+]], $[[R5]], $[[R4]]
+; CHECK: nor $[[R7:[0-9]+]], $zero, $[[R6]]
+; CHECK: subu $[[R18:[0-9]+]], $zero, $4
+; CHECK: andi $[[R8:[0-9]+]], $[[R18]], 255
+; CHECK: sll $[[R9:[0-9]+]], $[[R8]], $[[R4]]
+
+; CHECK: $[[BB0:[A-Z_0-9]+]]:
+; CHECK: ll $[[R10:[0-9]+]], 0($[[R2]])
+; CHECK: addu $[[R11:[0-9]+]], $[[R10]], $[[R9]]
+; CHECK: and $[[R12:[0-9]+]], $[[R11]], $[[R6]]
+; CHECK: and $[[R13:[0-9]+]], $[[R10]], $[[R7]]
+; CHECK: or $[[R14:[0-9]+]], $[[R13]], $[[R12]]
+; CHECK: sc $[[R14]], 0($[[R2]])
+; CHECK: beq $[[R14]], $zero, $[[BB0]]
+
+; CHECK: and $[[R15:[0-9]+]], $[[R10]], $[[R6]]
+; CHECK: srl $[[R16:[0-9]+]], $[[R15]], $[[R4]]
+; CHECK: sll $[[R17:[0-9]+]], $[[R16]], 24
+; CHECK: sra $2, $[[R17]], 24
+}
+
+define signext i8 @AtomicLoadNand8(i8 signext %incr) nounwind {
+entry:
+ %0 = call i8 @llvm.atomic.load.nand.i8.p0i8(i8* @y, i8 %incr)
+ ret i8 %0
+
+; CHECK: AtomicLoadNand8:
+; CHECK: lw $[[R0:[0-9]+]], %got(y)($gp)
+; CHECK: addiu $[[R1:[0-9]+]], $zero, -4
+; CHECK: and $[[R2:[0-9]+]], $[[R0]], $[[R1]]
+; CHECK: andi $[[R3:[0-9]+]], $[[R0]], 3
+; CHECK: sll $[[R4:[0-9]+]], $[[R3]], 3
+; CHECK: ori $[[R5:[0-9]+]], $zero, 255
+; CHECK: sll $[[R6:[0-9]+]], $[[R5]], $[[R4]]
+; CHECK: nor $[[R7:[0-9]+]], $zero, $[[R6]]
+; CHECK: andi $[[R8:[0-9]+]], $4, 255
+; CHECK: sll $[[R9:[0-9]+]], $[[R8]], $[[R4]]
+
+; CHECK: $[[BB0:[A-Z_0-9]+]]:
+; CHECK: ll $[[R10:[0-9]+]], 0($[[R2]])
+; CHECK: and $[[R18:[0-9]+]], $[[R10]], $[[R9]]
+; CHECK: nor $[[R11:[0-9]+]], $zero, $[[R18]]
+; CHECK: and $[[R12:[0-9]+]], $[[R11]], $[[R6]]
+; CHECK: and $[[R13:[0-9]+]], $[[R10]], $[[R7]]
+; CHECK: or $[[R14:[0-9]+]], $[[R13]], $[[R12]]
+; CHECK: sc $[[R14]], 0($[[R2]])
+; CHECK: beq $[[R14]], $zero, $[[BB0]]
+
+; CHECK: and $[[R15:[0-9]+]], $[[R10]], $[[R6]]
+; CHECK: srl $[[R16:[0-9]+]], $[[R15]], $[[R4]]
+; CHECK: sll $[[R17:[0-9]+]], $[[R16]], 24
+; CHECK: sra $2, $[[R17]], 24
+}
+
+define signext i8 @AtomicSwap8(i8 signext %oldval) nounwind {
+entry:
+ %0 = call i8 @llvm.atomic.swap.i8.p0i8(i8* @y, i8 %oldval)
+ ret i8 %0
+
+; CHECK: AtomicSwap8:
+; CHECK: lw $[[R0:[0-9]+]], %got(y)($gp)
+; CHECK: addiu $[[R1:[0-9]+]], $zero, -4
+; CHECK: and $[[R2:[0-9]+]], $[[R0]], $[[R1]]
+; CHECK: andi $[[R3:[0-9]+]], $[[R0]], 3
+; CHECK: sll $[[R4:[0-9]+]], $[[R3]], 3
+; CHECK: ori $[[R5:[0-9]+]], $zero, 255
+; CHECK: sll $[[R6:[0-9]+]], $[[R5]], $[[R4]]
+; CHECK: nor $[[R7:[0-9]+]], $zero, $[[R6]]
+; CHECK: andi $[[R8:[0-9]+]], $4, 255
+; CHECK: sll $[[R9:[0-9]+]], $[[R8]], $[[R4]]
+; CHECK: sw $[[R9]], [[OFFSET:[0-9]+]]($sp)
+
+; CHECK: $[[BB0:[A-Z_0-9]+]]:
+; CHECK: ll $[[R10:[0-9]+]], 0($[[R2]])
+; CHECK: lw $[[R18:[0-9]+]], [[OFFSET]]($sp)
+; CHECK: or $[[R11:[0-9]+]], $zero, $[[R18]]
+; CHECK: and $[[R12:[0-9]+]], $[[R11]], $[[R6]]
+; CHECK: and $[[R13:[0-9]+]], $[[R10]], $[[R7]]
+; CHECK: or $[[R14:[0-9]+]], $[[R13]], $[[R12]]
+; CHECK: sc $[[R14]], 0($[[R2]])
+; CHECK: beq $[[R14]], $zero, $[[BB0]]
+
+; CHECK: and $[[R15:[0-9]+]], $[[R10]], $[[R6]]
+; CHECK: srl $[[R16:[0-9]+]], $[[R15]], $[[R4]]
+; CHECK: sll $[[R17:[0-9]+]], $[[R16]], 24
+; CHECK: sra $2, $[[R17]], 24
+}
+
+define signext i8 @AtomicCmpSwap8(i8 signext %oldval, i8 signext %newval) nounwind {
+entry:
+ %0 = call i8 @llvm.atomic.cmp.swap.i8.p0i8(i8* @y, i8 %oldval, i8 %newval)
+ ret i8 %0
+
+; CHECK: AtomicCmpSwap8:
+; CHECK: lw $[[R0:[0-9]+]], %got(y)($gp)
+; CHECK: addiu $[[R1:[0-9]+]], $zero, -4
+; CHECK: and $[[R2:[0-9]+]], $[[R0]], $[[R1]]
+; CHECK: andi $[[R3:[0-9]+]], $[[R0]], 3
+; CHECK: sll $[[R4:[0-9]+]], $[[R3]], 3
+; CHECK: ori $[[R5:[0-9]+]], $zero, 255
+; CHECK: sll $[[R6:[0-9]+]], $[[R5]], $[[R4]]
+; CHECK: nor $[[R7:[0-9]+]], $zero, $[[R6]]
+; CHECK: andi $[[R8:[0-9]+]], $4, 255
+; CHECK: sll $[[R9:[0-9]+]], $[[R8]], $[[R4]]
+; CHECK: andi $[[R10:[0-9]+]], $5, 255
+; CHECK: sll $[[R11:[0-9]+]], $[[R10]], $[[R4]]
+
+; CHECK: $[[BB0:[A-Z_0-9]+]]:
+; CHECK: ll $[[R12:[0-9]+]], 0($[[R2]])
+; CHECK: and $[[R13:[0-9]+]], $[[R12]], $[[R6]]
+; CHECK: bne $[[R13]], $[[R9]], $[[BB1:[A-Z_0-9]+]]
+
+; CHECK: and $[[R14:[0-9]+]], $[[R12]], $[[R7]]
+; CHECK: or $[[R15:[0-9]+]], $[[R14]], $[[R11]]
+; CHECK: sc $[[R15]], 0($[[R2]])
+; CHECK: beq $[[R15]], $zero, $[[BB0]]
+
+; CHECK: $[[BB1]]:
+; CHECK: srl $[[R16:[0-9]+]], $[[R13]], $[[R4]]
+; CHECK: sll $[[R17:[0-9]+]], $[[R16]], 24
+; CHECK: sra $2, $[[R17]], 24
+}
diff --git a/test/CodeGen/Mips/blockaddr.ll b/test/CodeGen/Mips/blockaddr.ll
index e9af304..6de6b77 100644
--- a/test/CodeGen/Mips/blockaddr.ll
+++ b/test/CodeGen/Mips/blockaddr.ll
@@ -8,14 +8,14 @@ entry:
ret i8* %x
}
-; CHECK-PIC: lw $[[R0:[0-9]+]], %got($tmp1)($gp)
-; CHECK-PIC: addiu ${{[0-9]+}}, $[[R0]], %lo($tmp1)
-; CHECK-PIC: lw $[[R1:[0-9]+]], %got($tmp2)($gp)
-; CHECK-PIC: addiu ${{[0-9]+}}, $[[R1]], %lo($tmp2)
-; CHECK-STATIC: lui $[[R2:[0-9]+]], %hi($tmp1)
-; CHECK-STATIC: addiu ${{[0-9]+}}, $[[R2]], %lo($tmp1)
-; CHECK-STATIC: lui $[[R3:[0-9]+]], %hi($tmp2)
-; CHECK-STATIC: addiu ${{[0-9]+}}, $[[R3]], %lo($tmp2)
+; CHECK-PIC: lw $[[R0:[0-9]+]], %got($tmp[[T0:[0-9]+]])($gp)
+; CHECK-PIC: addiu ${{[0-9]+}}, $[[R0]], %lo($tmp[[T0]])
+; CHECK-PIC: lw $[[R1:[0-9]+]], %got($tmp[[T1:[0-9]+]])($gp)
+; CHECK-PIC: addiu ${{[0-9]+}}, $[[R1]], %lo($tmp[[T1]])
+; CHECK-STATIC: lui $[[R2:[0-9]+]], %hi($tmp[[T0:[0-9]+]])
+; CHECK-STATIC: addiu ${{[0-9]+}}, $[[R2]], %lo($tmp[[T0]])
+; CHECK-STATIC: lui $[[R3:[0-9]+]], %hi($tmp[[T1:[0-9]+]])
+; CHECK-STATIC: addiu ${{[0-9]+}}, $[[R3]], %lo($tmp[[T1]])
define void @f() nounwind {
entry:
%call = tail call i8* @dummy(i8* blockaddress(@f, %baz))
diff --git a/test/CodeGen/Mips/cmov.ll b/test/CodeGen/Mips/cmov.ll
index 8329c89..ec37961 100755
--- a/test/CodeGen/Mips/cmov.ll
+++ b/test/CodeGen/Mips/cmov.ll
@@ -4,8 +4,8 @@
@i1 = global [3 x i32] [i32 1, i32 2, i32 3], align 4
@i3 = common global i32* null, align 4
-; CHECK: lw ${{[0-9]+}}, %got(i3)($gp)
; CHECK: addiu ${{[0-9]+}}, $gp, %got(i1)
+; CHECK: lw ${{[0-9]+}}, %got(i3)($gp)
define i32* @cmov1(i32 %s) nounwind readonly {
entry:
%tobool = icmp ne i32 %s, 0
@@ -14,3 +14,19 @@ entry:
ret i32* %cond
}
+@c = global i32 1, align 4
+@d = global i32 0, align 4
+
+; CHECK: cmov2:
+; CHECK: addiu $[[R0:[0-9]+]], $gp, %got(c)
+; CHECK: addiu $[[R1:[0-9]+]], $gp, %got(d)
+; CHECK: movn $[[R1]], $[[R0]], ${{[0-9]+}}
+define i32 @cmov2(i32 %s) nounwind readonly {
+entry:
+ %tobool = icmp ne i32 %s, 0
+ %tmp1 = load i32* @c, align 4
+ %tmp2 = load i32* @d, align 4
+ %cond = select i1 %tobool, i32 %tmp1, i32 %tmp2
+ ret i32 %cond
+}
+
diff --git a/test/CodeGen/Mips/double2int.ll b/test/CodeGen/Mips/double2int.ll
new file mode 100644
index 0000000..3d033e1
--- /dev/null
+++ b/test/CodeGen/Mips/double2int.ll
@@ -0,0 +1,8 @@
+; RUN: llc -march=mips -mcpu=4ke < %s | FileCheck %s
+
+define i32 @f1(double %d) nounwind readnone {
+entry:
+; CHECK: trunc.w.d $f{{[0-9]+}}, $f12
+ %conv = fptosi double %d to i32
+ ret i32 %conv
+}
diff --git a/test/CodeGen/Mips/eh.ll b/test/CodeGen/Mips/eh.ll
new file mode 100644
index 0000000..765b778
--- /dev/null
+++ b/test/CodeGen/Mips/eh.ll
@@ -0,0 +1,78 @@
+; RUN: llc < %s -march=mipsel -mcpu=4ke | FileCheck %s -check-prefix=CHECK-EL
+; RUN: llc < %s -march=mips -mcpu=4ke | FileCheck %s -check-prefix=CHECK-EB
+
+@g1 = global double 0.000000e+00, align 8
+@_ZTId = external constant i8*
+
+define void @_Z1fd(double %i2) {
+entry:
+; CHECK-EL: addiu $sp, $sp
+; CHECK-EL: .cfi_def_cfa_offset
+; CHECK-EL: sdc1 $f20
+; CHECK-EL: sw $ra
+; CHECK-EL: sw $17
+; CHECK-EL: sw $16
+; CHECK-EL: .cfi_offset 52, -8
+; CHECK-EL: .cfi_offset 53, -4
+; CHECK-EB: .cfi_offset 53, -8
+; CHECK-EB: .cfi_offset 52, -4
+; CHECK-EL: .cfi_offset 31, -12
+; CHECK-EL: .cfi_offset 17, -16
+; CHECK-EL: .cfi_offset 16, -20
+; CHECK-EL: .cprestore
+
+ %exception = tail call i8* @__cxa_allocate_exception(i32 8) nounwind
+ %0 = bitcast i8* %exception to double*
+ store double 3.200000e+00, double* %0, align 8, !tbaa !0
+ invoke void @__cxa_throw(i8* %exception, i8* bitcast (i8** @_ZTId to i8*), i8* null) noreturn
+ to label %unreachable unwind label %lpad
+
+lpad: ; preds = %entry
+; CHECK-EL: # %lpad
+; CHECK-EL: lw $gp
+; CHECK-EL: beq $5
+
+ %exn = tail call i8* @llvm.eh.exception() nounwind
+ %eh.selector = tail call i32 (i8*, i8*, ...)* @llvm.eh.selector(i8* %exn, i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*), i8* bitcast (i8** @_ZTId to i8*)) nounwind
+ %1 = tail call i32 @llvm.eh.typeid.for(i8* bitcast (i8** @_ZTId to i8*)) nounwind
+ %2 = icmp eq i32 %eh.selector, %1
+ br i1 %2, label %catch, label %eh.resume
+
+catch: ; preds = %lpad
+ %3 = tail call i8* @__cxa_begin_catch(i8* %exn) nounwind
+ %4 = bitcast i8* %3 to double*
+ %exn.scalar = load double* %4, align 8
+ %add = fadd double %exn.scalar, %i2
+ store double %add, double* @g1, align 8, !tbaa !0
+ tail call void @__cxa_end_catch() nounwind
+ ret void
+
+eh.resume: ; preds = %lpad
+ tail call void @llvm.eh.resume(i8* %exn, i32 %eh.selector) noreturn
+ unreachable
+
+unreachable: ; preds = %entry
+ unreachable
+}
+
+declare i8* @__cxa_allocate_exception(i32)
+
+declare i8* @llvm.eh.exception() nounwind readonly
+
+declare i32 @__gxx_personality_v0(...)
+
+declare i32 @llvm.eh.selector(i8*, i8*, ...) nounwind
+
+declare i32 @llvm.eh.typeid.for(i8*) nounwind
+
+declare void @llvm.eh.resume(i8*, i32)
+
+declare void @__cxa_throw(i8*, i8*, i8*)
+
+declare i8* @__cxa_begin_catch(i8*)
+
+declare void @__cxa_end_catch()
+
+!0 = metadata !{metadata !"double", metadata !1}
+!1 = metadata !{metadata !"omnipotent char", metadata !2}
+!2 = metadata !{metadata !"Simple C/C++ TBAA", null}
diff --git a/test/CodeGen/Mips/fcopysign.ll b/test/CodeGen/Mips/fcopysign.ll
new file mode 100644
index 0000000..14c6507
--- /dev/null
+++ b/test/CodeGen/Mips/fcopysign.ll
@@ -0,0 +1,55 @@
+; RUN: llc < %s -march=mipsel -mcpu=4ke | FileCheck %s -check-prefix=CHECK-EL
+; RUN: llc < %s -march=mips -mcpu=4ke | FileCheck %s -check-prefix=CHECK-EB
+
+define double @func0(double %d0, double %d1) nounwind readnone {
+entry:
+; CHECK-EL: func0:
+; CHECK-EL: lui $[[T0:[0-9]+]], 32767
+; CHECK-EL: lui $[[T1:[0-9]+]], 32768
+; CHECK-EL: mfc1 $[[HI0:[0-9]+]], $f13
+; CHECK-EL: ori $[[MSK0:[0-9]+]], $[[T0]], 65535
+; CHECK-EL: mfc1 $[[HI1:[0-9]+]], $f15
+; CHECK-EL: ori $[[MSK1:[0-9]+]], $[[T1]], 0
+; CHECK-EL: and $[[AND0:[0-9]+]], $[[HI0]], $[[MSK0]]
+; CHECK-EL: and $[[AND1:[0-9]+]], $[[HI1]], $[[MSK1]]
+; CHECK-EL: mfc1 $[[LO0:[0-9]+]], $f12
+; CHECK-EL: or $[[OR:[0-9]+]], $[[AND0]], $[[AND1]]
+; CHECK-EL: mtc1 $[[LO0]], $f0
+; CHECK-EL: mtc1 $[[OR]], $f1
+;
+; CHECK-EB: lui $[[T0:[0-9]+]], 32767
+; CHECK-EB: lui $[[T1:[0-9]+]], 32768
+; CHECK-EB: mfc1 $[[HI0:[0-9]+]], $f12
+; CHECK-EB: ori $[[MSK0:[0-9]+]], $[[T0]], 65535
+; CHECK-EB: mfc1 $[[HI1:[0-9]+]], $f14
+; CHECK-EB: ori $[[MSK1:[0-9]+]], $[[T1]], 0
+; CHECK-EB: and $[[AND0:[0-9]+]], $[[HI0]], $[[MSK0]]
+; CHECK-EB: and $[[AND1:[0-9]+]], $[[HI1]], $[[MSK1]]
+; CHECK-EB: or $[[OR:[0-9]+]], $[[AND0]], $[[AND1]]
+; CHECK-EB: mfc1 $[[LO0:[0-9]+]], $f13
+; CHECK-EB: mtc1 $[[OR]], $f0
+; CHECK-EB: mtc1 $[[LO0]], $f1
+ %call = tail call double @copysign(double %d0, double %d1) nounwind readnone
+ ret double %call
+}
+
+declare double @copysign(double, double) nounwind readnone
+
+define float @func1(float %f0, float %f1) nounwind readnone {
+entry:
+; CHECK-EL: func1:
+; CHECK-EL: lui $[[T0:[0-9]+]], 32767
+; CHECK-EL: lui $[[T1:[0-9]+]], 32768
+; CHECK-EL: mfc1 $[[ARG0:[0-9]+]], $f12
+; CHECK-EL: ori $[[MSK0:[0-9]+]], $[[T0]], 65535
+; CHECK-EL: mfc1 $[[ARG1:[0-9]+]], $f14
+; CHECK-EL: ori $[[MSK1:[0-9]+]], $[[T1]], 0
+; CHECK-EL: and $[[T2:[0-9]+]], $[[ARG0]], $[[MSK0]]
+; CHECK-EL: and $[[T3:[0-9]+]], $[[ARG1]], $[[MSK1]]
+; CHECK-EL: or $[[T4:[0-9]+]], $[[T2]], $[[T3]]
+; CHECK-EL: mtc1 $[[T4]], $f0
+ %call = tail call float @copysignf(float %f0, float %f1) nounwind readnone
+ ret float %call
+}
+
+declare float @copysignf(float, float) nounwind readnone
diff --git a/test/CodeGen/Mips/frame-address.ll b/test/CodeGen/Mips/frame-address.ll
new file mode 100644
index 0000000..c48ce7e
--- /dev/null
+++ b/test/CodeGen/Mips/frame-address.ll
@@ -0,0 +1,12 @@
+; RUN: llc -march=mipsel -mcpu=mips2 < %s | FileCheck %s
+
+declare i8* @llvm.frameaddress(i32) nounwind readnone
+
+define i8* @f() nounwind {
+entry:
+ %0 = call i8* @llvm.frameaddress(i32 0)
+ ret i8* %0
+
+; CHECK: addu $fp, $sp, $zero
+; CHECK: addu $2, $zero, $fp
+}
diff --git a/test/CodeGen/Mips/gprestore.ll b/test/CodeGen/Mips/gprestore.ll
new file mode 100644
index 0000000..ee7e131
--- /dev/null
+++ b/test/CodeGen/Mips/gprestore.ll
@@ -0,0 +1,32 @@
+; RUN: llc -march=mips < %s | FileCheck %s
+
+@p = external global i32
+@q = external global i32
+@r = external global i32
+
+define void @f0() nounwind {
+entry:
+; CHECK: jalr
+; CHECK-NOT: got({{.*}})($gp)
+; CHECK: lw $gp
+; CHECK: jalr
+; CHECK-NOT: got({{.*}})($gp)
+; CHECK: lw $gp
+; CHECK: jalr
+; CHECK-NOT: got({{.*}})($gp)
+; CHECK: lw $gp
+ tail call void (...)* @f1() nounwind
+ %tmp = load i32* @p, align 4
+ tail call void @f2(i32 %tmp) nounwind
+ %tmp1 = load i32* @q, align 4
+ %tmp2 = load i32* @r, align 4
+ tail call void @f3(i32 %tmp1, i32 %tmp2) nounwind
+ ret void
+}
+
+declare void @f1(...)
+
+declare void @f2(i32)
+
+declare void @f3(i32, i32)
+
diff --git a/test/CodeGen/Mips/i64arg.ll b/test/CodeGen/Mips/i64arg.ll
new file mode 100644
index 0000000..9a30453
--- /dev/null
+++ b/test/CodeGen/Mips/i64arg.ll
@@ -0,0 +1,34 @@
+; RUN: llc -march=mips -mcpu=4ke < %s | FileCheck %s
+
+define void @f1(i64 %ll1, float %f, i64 %ll, i32 %i, float %f2) nounwind {
+entry:
+; CHECK: addu $[[R1:[0-9]+]], $zero, $5
+; CHECK: addu $[[R0:[0-9]+]], $zero, $4
+; CHECK: lw $25, %call16(ff1)
+; CHECK: ori $6, ${{[0-9]+}}, 3855
+; CHECK: ori $7, ${{[0-9]+}}, 22136
+; CHECK: jalr
+ tail call void @ff1(i32 %i, i64 1085102592623924856) nounwind
+; CHECK: lw $25, %call16(ff2)
+; CHECK: lw $[[R2:[0-9]+]], 80($sp)
+; CHECK: lw $[[R3:[0-9]+]], 84($sp)
+; CHECK: addu $4, $zero, $[[R2]]
+; CHECK: addu $5, $zero, $[[R3]]
+; CHECK: jalr $25
+ tail call void @ff2(i64 %ll, double 3.000000e+00) nounwind
+ %sub = add nsw i32 %i, -1
+; CHECK: sw $[[R0]], 24($sp)
+; CHECK: sw $[[R1]], 28($sp)
+; CHECK: lw $25, %call16(ff3)
+; CHECK: addu $6, $zero, $[[R2]]
+; CHECK: addu $7, $zero, $[[R3]]
+; CHECK: jalr $25
+ tail call void @ff3(i32 %i, i64 %ll, i32 %sub, i64 %ll1) nounwind
+ ret void
+}
+
+declare void @ff1(i32, i64)
+
+declare void @ff2(i64, double)
+
+declare void @ff3(i32, i64, i32, i64)
diff --git a/test/CodeGen/Mips/internalfunc.ll b/test/CodeGen/Mips/internalfunc.ll
index fdfa01a..50d0993 100644
--- a/test/CodeGen/Mips/internalfunc.ll
+++ b/test/CodeGen/Mips/internalfunc.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=mips | FileCheck %s
+; RUN: llc < %s -march=mipsel -mcpu=4ke | FileCheck %s
@caller.sf1 = internal unnamed_addr global void (...)* null, align 4
@gf1 = external global void (...)*
diff --git a/test/CodeGen/Mips/largeimmprinting.ll b/test/CodeGen/Mips/largeimmprinting.ll
new file mode 100644
index 0000000..fd7ae9e
--- /dev/null
+++ b/test/CodeGen/Mips/largeimmprinting.ll
@@ -0,0 +1,23 @@
+; RUN: llc -march=mipsel -mcpu=4ke < %s | FileCheck %s
+
+%struct.S1 = type { [65536 x i8] }
+
+@s1 = external global %struct.S1
+
+define void @f() nounwind {
+entry:
+; CHECK: lui $at, 65534
+; CHECK: addu $at, $sp, $at
+; CHECK: addiu $sp, $at, -16
+; CHECK: .cprestore 65536
+
+ %agg.tmp = alloca %struct.S1, align 1
+ %tmp = getelementptr inbounds %struct.S1* %agg.tmp, i32 0, i32 0, i32 0
+ call void @llvm.memcpy.p0i8.p0i8.i32(i8* %tmp, i8* getelementptr inbounds (%struct.S1* @s1, i32 0, i32 0, i32 0), i32 65536, i32 1, i1 false)
+ call void @f2(%struct.S1* byval %agg.tmp) nounwind
+ ret void
+}
+
+declare void @f2(%struct.S1* byval)
+
+declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32, i1) nounwind
diff --git a/test/CodeGen/Mips/o32_cc_byval.ll b/test/CodeGen/Mips/o32_cc_byval.ll
new file mode 100644
index 0000000..b78c393
--- /dev/null
+++ b/test/CodeGen/Mips/o32_cc_byval.ll
@@ -0,0 +1,127 @@
+; RUN: llc -march=mipsel -mcpu=4ke < %s | FileCheck %s
+
+%0 = type { i8, i16, i32, i64, double, i32, [4 x i8] }
+%struct.S1 = type { i8, i16, i32, i64, double, i32 }
+%struct.S2 = type { [4 x i32] }
+%struct.S3 = type { i8 }
+
+@f1.s1 = internal unnamed_addr constant %0 { i8 1, i16 2, i32 3, i64 4, double 5.000000e+00, i32 6, [4 x i8] undef }, align 8
+@f1.s2 = internal unnamed_addr constant %struct.S2 { [4 x i32] [i32 7, i32 8, i32 9, i32 10] }, align 4
+
+define void @f1() nounwind {
+entry:
+; CHECK: lw $[[R1:[0-9]+]], %got(f1.s1)($gp)
+; CHECK: addiu $[[R0:[0-9]+]], $[[R1]], %lo(f1.s1)
+; CHECK: lw $[[R2:[0-9]+]], 8($[[R0]])
+; CHECK: lw $[[R7:[0-9]+]], 12($[[R0]])
+; CHECK: lw $[[R3:[0-9]+]], 16($[[R0]])
+; CHECK: lw $[[R4:[0-9]+]], 20($[[R0]])
+; CHECK: lw $[[R5:[0-9]+]], 24($[[R0]])
+; CHECK: lw $[[R6:[0-9]+]], 28($[[R0]])
+; CHECK: sw $[[R2]], 16($sp)
+; CHECK: sw $[[R7]], 20($sp)
+; CHECK: sw $[[R3]], 24($sp)
+; CHECK: sw $[[R4]], 28($sp)
+; CHECK: sw $[[R5]], 32($sp)
+; CHECK: sw $[[R6]], 36($sp)
+; CHECK: lw $6, 0($[[R0]])
+; CHECK: lw $7, 4($[[R0]])
+ %agg.tmp10 = alloca %struct.S3, align 4
+ call void @callee1(float 2.000000e+01, %struct.S1* byval bitcast (%0* @f1.s1 to %struct.S1*)) nounwind
+ call void @callee2(%struct.S2* byval @f1.s2) nounwind
+ %tmp11 = getelementptr inbounds %struct.S3* %agg.tmp10, i32 0, i32 0
+ store i8 11, i8* %tmp11, align 4
+ call void @callee3(float 2.100000e+01, %struct.S3* byval %agg.tmp10, %struct.S1* byval bitcast (%0* @f1.s1 to %struct.S1*)) nounwind
+ ret void
+}
+
+declare void @callee1(float, %struct.S1* byval)
+
+declare void @callee2(%struct.S2* byval)
+
+declare void @callee3(float, %struct.S3* byval, %struct.S1* byval)
+
+define void @f2(float %f, %struct.S1* nocapture byval %s1) nounwind {
+entry:
+; CHECK: addiu $sp, $sp, -56
+; CHECK: sw $6, 64($sp)
+; CHECK: sw $7, 68($sp)
+; CHECK: ldc1 $f[[F0:[0-9]+]], 80($sp)
+; CHECK: lw $[[R2:[0-9]+]], 68($sp)
+; CHECK: lh $[[R1:[0-9]+]], 66($sp)
+; CHECK: lb $[[R0:[0-9]+]], 64($sp)
+; CHECK: lw $[[R3:[0-9]+]], 72($sp)
+; CHECK: lw $[[R4:[0-9]+]], 76($sp)
+; CHECK: lw $4, 88($sp)
+; CHECK: sw $[[R3]], 16($sp)
+; CHECK: sw $[[R4]], 20($sp)
+; CHECK: sw $[[R2]], 24($sp)
+; CHECK: sw $[[R1]], 28($sp)
+; CHECK: sw $[[R0]], 32($sp)
+; CHECK: mfc1 $6, $f[[F0]]
+
+ %i2 = getelementptr inbounds %struct.S1* %s1, i32 0, i32 5
+ %tmp = load i32* %i2, align 4, !tbaa !0
+ %d = getelementptr inbounds %struct.S1* %s1, i32 0, i32 4
+ %tmp1 = load double* %d, align 8, !tbaa !3
+ %ll = getelementptr inbounds %struct.S1* %s1, i32 0, i32 3
+ %tmp2 = load i64* %ll, align 8, !tbaa !4
+ %i = getelementptr inbounds %struct.S1* %s1, i32 0, i32 2
+ %tmp3 = load i32* %i, align 4, !tbaa !0
+ %s = getelementptr inbounds %struct.S1* %s1, i32 0, i32 1
+ %tmp4 = load i16* %s, align 2, !tbaa !5
+ %c = getelementptr inbounds %struct.S1* %s1, i32 0, i32 0
+ %tmp5 = load i8* %c, align 1, !tbaa !1
+ tail call void @callee4(i32 %tmp, double %tmp1, i64 %tmp2, i32 %tmp3, i16 signext %tmp4, i8 signext %tmp5, float %f) nounwind
+ ret void
+}
+
+declare void @callee4(i32, double, i64, i32, i16 signext, i8 signext, float)
+
+define void @f3(%struct.S2* nocapture byval %s2) nounwind {
+entry:
+; CHECK: addiu $sp, $sp, -56
+; CHECK: sw $4, 56($sp)
+; CHECK: sw $5, 60($sp)
+; CHECK: sw $6, 64($sp)
+; CHECK: sw $7, 68($sp)
+; CHECK: lw $[[R0:[0-9]+]], 68($sp)
+; CHECK: lw $4, 56($sp)
+; CHECK: sw $[[R0]], 24($sp)
+
+ %arrayidx = getelementptr inbounds %struct.S2* %s2, i32 0, i32 0, i32 0
+ %tmp = load i32* %arrayidx, align 4, !tbaa !0
+ %arrayidx2 = getelementptr inbounds %struct.S2* %s2, i32 0, i32 0, i32 3
+ %tmp3 = load i32* %arrayidx2, align 4, !tbaa !0
+ tail call void @callee4(i32 %tmp, double 2.000000e+00, i64 3, i32 %tmp3, i16 signext 4, i8 signext 5, float 6.000000e+00) nounwind
+ ret void
+}
+
+define void @f4(float %f, %struct.S3* nocapture byval %s3, %struct.S1* nocapture byval %s1) nounwind {
+entry:
+; CHECK: addiu $sp, $sp, -56
+; CHECK: sw $5, 60($sp)
+; CHECK: sw $6, 64($sp)
+; CHECK: sw $7, 68($sp)
+; CHECK: lw $[[R1:[0-9]+]], 88($sp)
+; CHECK: lb $[[R0:[0-9]+]], 60($sp)
+; CHECK: lw $4, 68($sp)
+; CHECK: sw $[[R1]], 24($sp)
+; CHECK: sw $[[R0]], 32($sp)
+
+ %i = getelementptr inbounds %struct.S1* %s1, i32 0, i32 2
+ %tmp = load i32* %i, align 4, !tbaa !0
+ %i2 = getelementptr inbounds %struct.S1* %s1, i32 0, i32 5
+ %tmp1 = load i32* %i2, align 4, !tbaa !0
+ %c = getelementptr inbounds %struct.S3* %s3, i32 0, i32 0
+ %tmp2 = load i8* %c, align 1, !tbaa !1
+ tail call void @callee4(i32 %tmp, double 2.000000e+00, i64 3, i32 %tmp1, i16 signext 4, i8 signext %tmp2, float 6.000000e+00) nounwind
+ ret void
+}
+
+!0 = metadata !{metadata !"int", metadata !1}
+!1 = metadata !{metadata !"omnipotent char", metadata !2}
+!2 = metadata !{metadata !"Simple C/C++ TBAA", null}
+!3 = metadata !{metadata !"double", metadata !1}
+!4 = metadata !{metadata !"long long", metadata !1}
+!5 = metadata !{metadata !"short", metadata !1}
diff --git a/test/CodeGen/Mips/o32_cc_vararg.ll b/test/CodeGen/Mips/o32_cc_vararg.ll
index 1f71ed2..14ce04b 100644
--- a/test/CodeGen/Mips/o32_cc_vararg.ll
+++ b/test/CodeGen/Mips/o32_cc_vararg.ll
@@ -1,5 +1,4 @@
; RUN: llc -march=mipsel -mcpu=mips2 -pre-RA-sched=source < %s | FileCheck %s
-; RUN: llc -march=mipsel -mcpu=mips2 -pre-RA-sched=source < %s -regalloc=basic | FileCheck %s
; All test functions do the same thing - they return the first variable
@@ -30,11 +29,11 @@ entry:
ret i32 %tmp
; CHECK: va1:
-; CHECK: addiu $sp, $sp, -32
-; CHECK: sw $7, 44($sp)
-; CHECK: sw $6, 40($sp)
-; CHECK: sw $5, 36($sp)
-; CHECK: lw $2, 36($sp)
+; CHECK: addiu $sp, $sp, -16
+; CHECK: sw $7, 28($sp)
+; CHECK: sw $6, 24($sp)
+; CHECK: sw $5, 20($sp)
+; CHECK: lw $2, 20($sp)
}
; check whether the variable double argument will be accessed from the 8-byte
@@ -56,11 +55,11 @@ entry:
ret double %tmp
; CHECK: va2:
-; CHECK: addiu $sp, $sp, -40
-; CHECK: sw $7, 52($sp)
-; CHECK: sw $6, 48($sp)
-; CHECK: sw $5, 44($sp)
-; CHECK: addiu $[[R0:[0-9]+]], $sp, 44
+; CHECK: addiu $sp, $sp, -16
+; CHECK: sw $7, 28($sp)
+; CHECK: sw $6, 24($sp)
+; CHECK: sw $5, 20($sp)
+; CHECK: addiu $[[R0:[0-9]+]], $sp, 20
; CHECK: addiu $[[R1:[0-9]+]], $[[R0]], 7
; CHECK: addiu $[[R2:[0-9]+]], $zero, -8
; CHECK: and $[[R3:[0-9]+]], $[[R1]], $[[R2]]
@@ -84,10 +83,10 @@ entry:
ret i32 %tmp
; CHECK: va3:
-; CHECK: addiu $sp, $sp, -40
-; CHECK: sw $7, 52($sp)
-; CHECK: sw $6, 48($sp)
-; CHECK: lw $2, 48($sp)
+; CHECK: addiu $sp, $sp, -16
+; CHECK: sw $7, 28($sp)
+; CHECK: sw $6, 24($sp)
+; CHECK: lw $2, 24($sp)
}
; double
@@ -107,14 +106,11 @@ entry:
ret double %tmp
; CHECK: va4:
-; CHECK: addiu $sp, $sp, -48
-; CHECK: sw $7, 60($sp)
-; CHECK: sw $6, 56($sp)
-; CHECK: addiu $[[R0:[0-9]+]], $sp, 56
-; CHECK: addiu $[[R1:[0-9]+]], $[[R0]], 7
-; CHECK: addiu $[[R2:[0-9]+]], $zero, -8
-; CHECK: and $[[R3:[0-9]+]], $[[R1]], $[[R2]]
-; CHECK: ldc1 $f0, 0($[[R3]])
+; CHECK: addiu $sp, $sp, -24
+; CHECK: sw $7, 36($sp)
+; CHECK: sw $6, 32($sp)
+; CHECK: addiu ${{[0-9]+}}, $sp, 32
+; CHECK: ldc1 $f0, 32($sp)
}
; int
@@ -138,9 +134,9 @@ entry:
ret i32 %tmp
; CHECK: va5:
-; CHECK: addiu $sp, $sp, -40
-; CHECK: sw $7, 52($sp)
-; CHECK: lw $2, 52($sp)
+; CHECK: addiu $sp, $sp, -24
+; CHECK: sw $7, 36($sp)
+; CHECK: lw $2, 36($sp)
}
; double
@@ -164,9 +160,9 @@ entry:
ret double %tmp
; CHECK: va6:
-; CHECK: addiu $sp, $sp, -48
-; CHECK: sw $7, 60($sp)
-; CHECK: addiu $[[R0:[0-9]+]], $sp, 60
+; CHECK: addiu $sp, $sp, -24
+; CHECK: sw $7, 36($sp)
+; CHECK: addiu $[[R0:[0-9]+]], $sp, 36
; CHECK: addiu $[[R1:[0-9]+]], $[[R0]], 7
; CHECK: addiu $[[R2:[0-9]+]], $zero, -8
; CHECK: and $[[R3:[0-9]+]], $[[R1]], $[[R2]]
@@ -192,8 +188,8 @@ entry:
ret i32 %tmp
; CHECK: va7:
-; CHECK: addiu $sp, $sp, -40
-; CHECK: lw $2, 56($sp)
+; CHECK: addiu $sp, $sp, -24
+; CHECK: lw $2, 40($sp)
}
; double
@@ -215,12 +211,9 @@ entry:
ret double %tmp
; CHECK: va8:
-; CHECK: addiu $sp, $sp, -48
-; CHECK: addiu $[[R0:[0-9]+]], $sp, 64
-; CHECK: addiu $[[R1:[0-9]+]], $[[R0]], 7
-; CHECK: addiu $[[R2:[0-9]+]], $zero, -8
-; CHECK: and $[[R3:[0-9]+]], $[[R1]], $[[R2]]
-; CHECK: ldc1 $f0, 0($[[R3]])
+; CHECK: addiu $sp, $sp, -32
+; CHECK: addiu ${{[0-9]+}}, $sp, 48
+; CHECK: ldc1 $f0, 48($sp)
}
; int
@@ -244,8 +237,8 @@ entry:
ret i32 %tmp
; CHECK: va9:
-; CHECK: addiu $sp, $sp, -56
-; CHECK: lw $2, 76($sp)
+; CHECK: addiu $sp, $sp, -32
+; CHECK: lw $2, 52($sp)
}
; double
@@ -269,8 +262,8 @@ entry:
ret double %tmp
; CHECK: va10:
-; CHECK: addiu $sp, $sp, -56
-; CHECK: addiu $[[R0:[0-9]+]], $sp, 76
+; CHECK: addiu $sp, $sp, -32
+; CHECK: addiu $[[R0:[0-9]+]], $sp, 52
; CHECK: addiu $[[R1:[0-9]+]], $[[R0]], 7
; CHECK: addiu $[[R2:[0-9]+]], $zero, -8
; CHECK: and $[[R3:[0-9]+]], $[[R1]], $[[R2]]
diff --git a/test/CodeGen/Mips/tls.ll b/test/CodeGen/Mips/tls.ll
new file mode 100644
index 0000000..034738b
--- /dev/null
+++ b/test/CodeGen/Mips/tls.ll
@@ -0,0 +1,46 @@
+; RUN: llc -march=mipsel -mcpu=mips2 < %s | FileCheck %s -check-prefix=PIC
+; RUN: llc -march=mipsel -mcpu=mips2 -relocation-model=static < %s \
+; RUN: | FileCheck %s -check-prefix=STATIC
+
+
+@t1 = thread_local global i32 0, align 4
+
+define i32 @f1() nounwind {
+entry:
+ %tmp = load i32* @t1, align 4
+ ret i32 %tmp
+
+; CHECK: f1:
+
+; PIC: lw $25, %call16(__tls_get_addr)($gp)
+; PIC: addiu $4, $gp, %tlsgd(t1)
+; PIC: jalr $25
+; PIC: lw $2, 0($2)
+
+; STATIC: rdhwr $3, $29
+; STATIC: lui $[[R0:[0-9]+]], %tprel_hi(t1)
+; STATIC: addiu $[[R1:[0-9]+]], $[[R0]], %tprel_lo(t1)
+; STATIC: addu $[[R2:[0-9]+]], $3, $[[R1]]
+; STATIC: lw $2, 0($[[R2]])
+}
+
+
+@t2 = external thread_local global i32
+
+define i32 @f2() nounwind {
+entry:
+ %tmp = load i32* @t2, align 4
+ ret i32 %tmp
+
+; CHECK: f2:
+
+; PIC: lw $25, %call16(__tls_get_addr)($gp)
+; PIC: addiu $4, $gp, %tlsgd(t2)
+; PIC: jalr $25
+; PIC: lw $2, 0($2)
+
+; STATIC: rdhwr $3, $29
+; STATIC: lw $[[R0:[0-9]+]], %gottprel(t2)($gp)
+; STATIC: addu $[[R1:[0-9]+]], $3, $[[R0]]
+; STATIC: lw $2, 0($[[R1]])
+}
diff --git a/test/CodeGen/Mips/weak.ll b/test/CodeGen/Mips/weak.ll
new file mode 100644
index 0000000..09dd2a4
--- /dev/null
+++ b/test/CodeGen/Mips/weak.ll
@@ -0,0 +1,12 @@
+; RUN: llc -march=mips < %s | FileCheck %s
+
+@t = common global i32 (...)* null, align 4
+
+define void @f() nounwind {
+entry:
+ store i32 (...)* @test_weak, i32 (...)** @t, align 4
+ ret void
+}
+
+; CHECK: .weak test_weak
+declare extern_weak i32 @test_weak(...)
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