diff options
Diffstat (limited to 'test/CodeGen/Mips')
72 files changed, 1941 insertions, 147 deletions
diff --git a/test/CodeGen/Mips/2008-07-23-fpcmp.ll b/test/CodeGen/Mips/2008-07-23-fpcmp.ll index 519e4b9..9c547f1 100644 --- a/test/CodeGen/Mips/2008-07-23-fpcmp.ll +++ b/test/CodeGen/Mips/2008-07-23-fpcmp.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -march=mips -o %t -; RUN: grep {c\\..*\\.s} %t | count 3 -; RUN: grep {bc1\[tf\]} %t | count 3 +; RUN: grep "c\..*\.s" %t | count 3 +; RUN: grep "bc1[tf]" %t | count 3 ; FIXME: Disabled because branch instructions are generated where ; conditional move instructions are expected. diff --git a/test/CodeGen/Mips/2008-07-29-icmp.ll b/test/CodeGen/Mips/2008-07-29-icmp.ll index e85a749..e88e3d3 100644 --- a/test/CodeGen/Mips/2008-07-29-icmp.ll +++ b/test/CodeGen/Mips/2008-07-29-icmp.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=mips | grep {b\[ne\]\[eq\]} | count 1 +; RUN: llc < %s -march=mips | grep "b[ne][eq]" | count 1 ; FIXME: Disabled because branch instructions are generated where ; conditional move instructions are expected. diff --git a/test/CodeGen/Mips/2010-07-20-Switch.ll b/test/CodeGen/Mips/2010-07-20-Switch.ll index aaf6767..261fe9d 100644 --- a/test/CodeGen/Mips/2010-07-20-Switch.ll +++ b/test/CodeGen/Mips/2010-07-20-Switch.ll @@ -7,19 +7,22 @@ entry: %x = alloca i32, align 4 ; <i32*> [#uses=2] store volatile i32 2, i32* %x, align 4 %0 = load volatile i32* %x, align 4 ; <i32> [#uses=1] -; STATIC-O32: lui $[[R0:[0-9]+]], %hi($JTI0_0) -; STATIC-O32: addiu ${{[0-9]+}}, $[[R0]], %lo($JTI0_0) -; STATIC-O32: sll ${{[0-9]+}}, ${{[0-9]+}}, 2 -; PIC-O32: lw $[[R0:[0-9]+]], %got($JTI0_0) -; PIC-O32: addiu ${{[0-9]+}}, $[[R0]], %lo($JTI0_0) -; PIC-O32: sll ${{[0-9]+}}, ${{[0-9]+}}, 2 -; PIC-O32: addu $[[R1:[0-9]+]], ${{[0-9]+}}, $gp -; PIC-O32: jr $[[R1]] -; PIC-N64: ld $[[R0:[0-9]+]], %got_page($JTI0_0) -; PIC-N64: daddiu ${{[0-9]+}}, $[[R0]], %got_ofst($JTI0_0) -; PIC-N64: dsll ${{[0-9]+}}, ${{[0-9]+}}, 3 -; PIC-N64: daddu $[[R1:[0-9]+]], ${{[0-9]+}}, $gp -; PIC-N64: jr $[[R1]] +; STATIC-O32: sll $[[R0:[0-9]+]], ${{[0-9]+}}, 2 +; STATIC-O32: lui $[[R1:[0-9]+]], %hi($JTI0_0) +; STATIC-O32: addu $[[R2:[0-9]+]], $[[R0]], $[[R1]] +; STATIC-O32: lw $[[R3:[0-9]+]], %lo($JTI0_0)($[[R2]]) +; PIC-O32: sll $[[R0:[0-9]+]], ${{[0-9]+}}, 2 +; PIC-O32: lw $[[R1:[0-9]+]], %got($JTI0_0) +; PIC-O32: addu $[[R2:[0-9]+]], $[[R0]], $[[R1]] +; PIC-O32: lw $[[R4:[0-9]+]], %lo($JTI0_0)($[[R2]]) +; PIC-O32: addu $[[R5:[0-9]+]], $[[R4:[0-9]+]] +; PIC-O32: jr $[[R5]] +; PIC-N64: dsll $[[R0:[0-9]+]], ${{[0-9]+}}, 3 +; PIC-N64: ld $[[R1:[0-9]+]], %got_page($JTI0_0) +; PIC-N64: daddu $[[R2:[0-9]+]], $[[R0:[0-9]+]], $[[R1]] +; PIC-N64: ld $[[R4:[0-9]+]], %got_ofst($JTI0_0)($[[R2]]) +; PIC-N64: daddu $[[R5:[0-9]+]], $[[R4:[0-9]+]] +; PIC-N64: jr $[[R5]] switch i32 %0, label %bb4 [ i32 0, label %bb5 i32 1, label %bb1 @@ -30,7 +33,6 @@ entry: bb1: ; preds = %entry ret i32 2 -; CHECK: STATIC-O32: $BB0_2 bb2: ; preds = %entry ret i32 0 diff --git a/test/CodeGen/Mips/alloca.ll b/test/CodeGen/Mips/alloca.ll index 15c73e2..29f43c8 100644 --- a/test/CodeGen/Mips/alloca.ll +++ b/test/CodeGen/Mips/alloca.ll @@ -4,14 +4,10 @@ define i32 @twoalloca(i32 %size) nounwind { entry: ; CHECK: subu $[[T0:[0-9]+]], $sp, $[[SZ:[0-9]+]] ; CHECK: addu $sp, $zero, $[[T0]] -; CHECK: addiu $[[T1:[0-9]+]], $sp, [[OFF:[0-9]+]] ; CHECK: subu $[[T2:[0-9]+]], $sp, $[[SZ]] ; CHECK: addu $sp, $zero, $[[T2]] -; CHECK: addiu $[[T3:[0-9]+]], $sp, [[OFF]] -; CHECK: lw $[[T4:[0-9]+]], %call16(foo)($gp) -; CHECK: addu $25, $zero, $[[T4]] -; CHECK: addu $4, $zero, $[[T1]] -; CHECK: jalr $25 +; CHECK: addu $4, $zero, $[[T0]] +; CHECK: addu $4, $zero, $[[T2]] %tmp1 = alloca i8, i32 %size, align 4 %add.ptr = getelementptr inbounds i8* %tmp1, i32 5 store i8 97, i8* %add.ptr, align 1 @@ -31,14 +27,9 @@ declare i32 @foo(i8*) define i32 @alloca2(i32 %size) nounwind { entry: -; dynamic allocated stack area and $gp restore slot have the same offsets -; relative to $sp. -; ; CHECK: alloca2 -; CHECK: .cprestore [[OFF:[0-9]+]] -; CHECK: subu $[[T0:[0-9]+]], $sp, $[[SZ:[0-9]+]] +; CHECK: subu $[[T0:[0-9]+]], $sp ; CHECK: addu $sp, $zero, $[[T0]] -; CHECK: addiu $[[T1:[0-9]+]], $sp, [[OFF]] %tmp1 = alloca i8, i32 %size, align 4 %0 = bitcast i8* %tmp1 to i32* @@ -46,7 +37,7 @@ entry: br i1 %cmp, label %if.then, label %if.else if.then: ; preds = %entry -; CHECK: addiu $4, $[[T1]], 40 +; CHECK: addiu $4, $[[T0]], 40 %add.ptr = getelementptr inbounds i8* %tmp1, i32 40 %1 = bitcast i8* %add.ptr to i32* @@ -56,7 +47,7 @@ if.then: ; preds = %entry br label %if.end if.else: ; preds = %entry -; CHECK: addiu $4, $[[T1]], 12 +; CHECK: addiu $4, $[[T0]], 12 %add.ptr5 = getelementptr inbounds i8* %tmp1, i32 12 %2 = bitcast i8* %add.ptr5 to i32* @@ -64,7 +55,7 @@ if.else: ; preds = %entry br label %if.end if.end: ; preds = %if.else, %if.then -; CHECK: lw $5, 0($[[T1]]) +; CHECK: lw $5, 0($[[T0]]) ; CHECK: lw $25, %call16(printf) %.pre-phi = phi i32* [ %2, %if.else ], [ %.pre, %if.then ] diff --git a/test/CodeGen/Mips/analyzebranch.ll b/test/CodeGen/Mips/analyzebranch.ll index bc5bcc3..8ec5d93 100644 --- a/test/CodeGen/Mips/analyzebranch.ll +++ b/test/CodeGen/Mips/analyzebranch.ll @@ -2,9 +2,8 @@ define double @foo(double %a, double %b) nounwind readnone { entry: -; CHECK: bc1f $BB0_2 +; CHECK: bc1f $BB ; CHECK: nop -; CHECK: # BB#1: %cmp = fcmp ogt double %a, 0.000000e+00 br i1 %cmp, label %if.end6, label %if.else @@ -26,9 +25,8 @@ return: ; preds = %if.else, %if.end6 define void @f1(float %f) nounwind { entry: -; CHECK: bc1f $BB1_1 +; CHECK: bc1f $BB ; CHECK: nop -; CHECK: # BB#2: %cmp = fcmp une float %f, 0.000000e+00 br i1 %cmp, label %if.then, label %if.end diff --git a/test/CodeGen/Mips/and1.ll b/test/CodeGen/Mips/and1.ll new file mode 100644 index 0000000..4ff1204 --- /dev/null +++ b/test/CodeGen/Mips/and1.ll @@ -0,0 +1,17 @@ +; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 + +@x = global i32 65504, align 4 +@y = global i32 60929, align 4 +@.str = private unnamed_addr constant [7 x i8] c"%08x \0A\00", align 1 + +define i32 @main() nounwind { +entry: + %0 = load i32* @x, align 4 + %1 = load i32* @y, align 4 + %and = and i32 %0, %1 +; 16: and ${{[0-9]+}}, ${{[0-9]+}} + %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([7 x i8]* @.str, i32 0, i32 0), i32 %and) + ret i32 0 +} + +declare i32 @printf(i8*, ...) diff --git a/test/CodeGen/Mips/asm-large-immediate.ll b/test/CodeGen/Mips/asm-large-immediate.ll new file mode 100644 index 0000000..246fff6 --- /dev/null +++ b/test/CodeGen/Mips/asm-large-immediate.ll @@ -0,0 +1,10 @@ +; RUN: llc -march=mipsel < %s | FileCheck %s +define void @test() { +entry: +; CHECK: /* result: 68719476738 */ + tail call void asm sideeffect "/* result: ${0:c} */", "i,~{dirflag},~{fpsr},~{flags}"( i64 68719476738 ) +; CHECK: /* result: -68719476738 */ + tail call void asm sideeffect "/* result: ${0:n} */", "i,~{dirflag},~{fpsr},~{flags}"( i64 68719476738 ) + ret void +} + diff --git a/test/CodeGen/Mips/atomic.ll b/test/CodeGen/Mips/atomic.ll index a4763b1..050689d 100644 --- a/test/CodeGen/Mips/atomic.ll +++ b/test/CodeGen/Mips/atomic.ll @@ -8,7 +8,7 @@ entry: ret i32 %0 ; CHECK: AtomicLoadAdd32: -; CHECK: lw $[[R0:[0-9]+]], %got(x)($gp) +; CHECK: lw $[[R0:[0-9]+]], %got(x) ; CHECK: $[[BB0:[A-Z_0-9]+]]: ; CHECK: ll $[[R1:[0-9]+]], 0($[[R0]]) ; CHECK: addu $[[R2:[0-9]+]], $[[R1]], $4 @@ -22,7 +22,7 @@ entry: ret i32 %0 ; CHECK: AtomicLoadNand32: -; CHECK: lw $[[R0:[0-9]+]], %got(x)($gp) +; CHECK: lw $[[R0:[0-9]+]], %got(x) ; CHECK: $[[BB0:[A-Z_0-9]+]]: ; CHECK: ll $[[R1:[0-9]+]], 0($[[R0]]) ; CHECK: and $[[R3:[0-9]+]], $[[R1]], $4 @@ -40,7 +40,7 @@ entry: ret i32 %0 ; CHECK: AtomicSwap32: -; CHECK: lw $[[R0:[0-9]+]], %got(x)($gp) +; CHECK: lw $[[R0:[0-9]+]], %got(x) ; CHECK: $[[BB0:[A-Z_0-9]+]]: ; CHECK: ll ${{[0-9]+}}, 0($[[R0]]) ; CHECK: sc $[[R2:[0-9]+]], 0($[[R0]]) @@ -56,7 +56,7 @@ entry: ret i32 %0 ; CHECK: AtomicCmpSwap32: -; CHECK: lw $[[R0:[0-9]+]], %got(x)($gp) +; CHECK: lw $[[R0:[0-9]+]], %got(x) ; CHECK: $[[BB0:[A-Z_0-9]+]]: ; CHECK: ll $2, 0($[[R0]]) ; CHECK: bne $2, $4, $[[BB1:[A-Z_0-9]+]] @@ -75,7 +75,7 @@ entry: ret i8 %0 ; CHECK: AtomicLoadAdd8: -; CHECK: lw $[[R0:[0-9]+]], %got(y)($gp) +; CHECK: lw $[[R0:[0-9]+]], %got(y) ; CHECK: addiu $[[R1:[0-9]+]], $zero, -4 ; CHECK: and $[[R2:[0-9]+]], $[[R0]], $[[R1]] ; CHECK: andi $[[R3:[0-9]+]], $[[R0]], 3 @@ -106,7 +106,7 @@ entry: ret i8 %0 ; CHECK: AtomicLoadSub8: -; CHECK: lw $[[R0:[0-9]+]], %got(y)($gp) +; CHECK: lw $[[R0:[0-9]+]], %got(y) ; CHECK: addiu $[[R1:[0-9]+]], $zero, -4 ; CHECK: and $[[R2:[0-9]+]], $[[R0]], $[[R1]] ; CHECK: andi $[[R3:[0-9]+]], $[[R0]], 3 @@ -137,7 +137,7 @@ entry: ret i8 %0 ; CHECK: AtomicLoadNand8: -; CHECK: lw $[[R0:[0-9]+]], %got(y)($gp) +; CHECK: lw $[[R0:[0-9]+]], %got(y) ; CHECK: addiu $[[R1:[0-9]+]], $zero, -4 ; CHECK: and $[[R2:[0-9]+]], $[[R0]], $[[R1]] ; CHECK: andi $[[R3:[0-9]+]], $[[R0]], 3 @@ -169,7 +169,7 @@ entry: ret i8 %0 ; CHECK: AtomicSwap8: -; CHECK: lw $[[R0:[0-9]+]], %got(y)($gp) +; CHECK: lw $[[R0:[0-9]+]], %got(y) ; CHECK: addiu $[[R1:[0-9]+]], $zero, -4 ; CHECK: and $[[R2:[0-9]+]], $[[R0]], $[[R1]] ; CHECK: andi $[[R3:[0-9]+]], $[[R0]], 3 @@ -198,7 +198,7 @@ entry: ret i8 %0 ; CHECK: AtomicCmpSwap8: -; CHECK: lw $[[R0:[0-9]+]], %got(y)($gp) +; CHECK: lw $[[R0:[0-9]+]], %got(y) ; CHECK: addiu $[[R1:[0-9]+]], $zero, -4 ; CHECK: and $[[R2:[0-9]+]], $[[R0]], $[[R1]] ; CHECK: andi $[[R3:[0-9]+]], $[[R0]], 3 @@ -242,3 +242,19 @@ entry: ; CHECK: sync 0 } +; make sure that this assertion in +; TwoAddressInstructionPass::TryInstructionTransform does not fail: +; +; line 1203: assert(TargetRegisterInfo::isVirtualRegister(regB) && +; +; it failed when MipsDAGToDAGISel::ReplaceUsesWithZeroReg replaced an +; operand of an atomic instruction with register $zero. +@a = external global i32 + +define i32 @zeroreg() nounwind { +entry: + %0 = cmpxchg i32* @a, i32 1, i32 0 seq_cst + %1 = icmp eq i32 %0, 1 + %conv = zext i1 %1 to i32 + ret i32 %conv +} diff --git a/test/CodeGen/Mips/cmov.ll b/test/CodeGen/Mips/cmov.ll index 03254a9..3af899a 100755 --- a/test/CodeGen/Mips/cmov.ll +++ b/test/CodeGen/Mips/cmov.ll @@ -5,10 +5,12 @@ @i1 = global [3 x i32] [i32 1, i32 2, i32 3], align 4 @i3 = common global i32* null, align 4 -; O32: lw ${{[0-9]+}}, %got(i3)($gp) -; O32: addiu ${{[0-9]+}}, $gp, %got(i1) -; N64: ld ${{[0-9]+}}, %got_disp(i3)($gp) -; N64: daddiu ${{[0-9]+}}, $gp, %got_disp(i1) +; O32: lw $[[R0:[0-9]+]], %got(i3) +; O32: addiu $[[R1:[0-9]+]], ${{[0-9]+}}, %got(i1) +; O32: movn $[[R0]], $[[R1]], ${{[0-9]+}} +; N64: ldr $[[R0:[0-9]+]] +; N64: ld $[[R1:[0-9]+]], %got_disp(i1) +; N64: movn $[[R0]], $[[R1]], ${{[0-9]+}} define i32* @cmov1(i32 %s) nounwind readonly { entry: %tobool = icmp ne i32 %s, 0 @@ -21,12 +23,12 @@ entry: @d = global i32 0, align 4 ; O32: cmov2: -; O32: addiu $[[R1:[0-9]+]], $gp, %got(d) -; O32: addiu $[[R0:[0-9]+]], $gp, %got(c) +; O32: addiu $[[R1:[0-9]+]], ${{[a-z0-9]+}}, %got(d) +; O32: addiu $[[R0:[0-9]+]], ${{[a-z0-9]+}}, %got(c) ; O32: movn $[[R1]], $[[R0]], ${{[0-9]+}} ; N64: cmov2: -; N64: daddiu $[[R1:[0-9]+]], $gp, %got_disp(d) -; N64: daddiu $[[R0:[0-9]+]], $gp, %got_disp(c) +; N64: daddiu $[[R1:[0-9]+]], ${{[0-9]+}}, %got_disp(d) +; N64: daddiu $[[R0:[0-9]+]], ${{[0-9]+}}, %got_disp(c) ; N64: movn $[[R1]], $[[R0]], ${{[0-9]+}} define i32 @cmov2(i32 %s) nounwind readonly { entry: @@ -37,3 +39,23 @@ entry: ret i32 %cond } +; O32: cmov3: +; O32: xori $[[R0:[0-9]+]], ${{[0-9]+}}, 234 +; O32: movz ${{[0-9]+}}, ${{[0-9]+}}, $[[R0]] +define i32 @cmov3(i32 %a, i32 %b, i32 %c) nounwind readnone { +entry: + %cmp = icmp eq i32 %a, 234 + %cond = select i1 %cmp, i32 %b, i32 %c + ret i32 %cond +} + +; N64: cmov4: +; N64: xori $[[R0:[0-9]+]], ${{[0-9]+}}, 234 +; N64: movz ${{[0-9]+}}, ${{[0-9]+}}, $[[R0]] +define i64 @cmov4(i32 %a, i64 %b, i64 %c) nounwind readnone { +entry: + %cmp = icmp eq i32 %a, 234 + %cond = select i1 %cmp, i64 %b, i64 %c + ret i64 %cond +} + diff --git a/test/CodeGen/Mips/cprestore.ll b/test/CodeGen/Mips/cprestore.ll index 57d022f..a618b67 100644 --- a/test/CodeGen/Mips/cprestore.ll +++ b/test/CodeGen/Mips/cprestore.ll @@ -1,4 +1,6 @@ -; RUN: llc -march=mipsel < %s | FileCheck %s +; DISABLE: llc -march=mipsel < %s | FileCheck %s +; RUN: false +; XFAIL: * ; CHECK: .set macro ; CHECK: .set at diff --git a/test/CodeGen/Mips/eh.ll b/test/CodeGen/Mips/eh.ll index 2e2f9a4..d14150a 100644 --- a/test/CodeGen/Mips/eh.ll +++ b/test/CodeGen/Mips/eh.ll @@ -15,7 +15,6 @@ entry: ; CHECK-EB: .cfi_offset 53, -8 ; CHECK-EB: .cfi_offset 52, -4 ; CHECK-EL: .cfi_offset 31, -12 -; CHECK-EL: .cprestore %exception = tail call i8* @__cxa_allocate_exception(i32 8) nounwind %0 = bitcast i8* %exception to double* @@ -25,7 +24,6 @@ entry: lpad: ; preds = %entry ; CHECK-EL: # %lpad -; CHECK-EL: lw $gp ; CHECK-EL: bne $5 %exn.val = landingpad { i8*, i32 } personality i32 (...)* @__gxx_personality_v0 diff --git a/test/CodeGen/Mips/fabs.ll b/test/CodeGen/Mips/fabs.ll index b296ab3..49d8a72 100644 --- a/test/CodeGen/Mips/fabs.ll +++ b/test/CodeGen/Mips/fabs.ll @@ -1,8 +1,8 @@ -; RUN: llc < %s -march=mipsel -mcpu=mips32 | FileCheck %s -check-prefix=32 -; RUN: llc < %s -march=mipsel -mcpu=mips32r2 | FileCheck %s -check-prefix=32R2 -; RUN: llc < %s -march=mips64el -mcpu=mips64 -mattr=n64 | FileCheck %s -check-prefix=64 -; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -mattr=n64 | FileCheck %s -check-prefix=64R2 -; RUN: llc < %s -march=mipsel -mcpu=mips32 -enable-no-nans-fp-math | FileCheck %s -check-prefix=NO-NAN +; RUN: llc < %s -mtriple=mipsel-linux-gnu -mcpu=mips32 | FileCheck %s -check-prefix=32 +; RUN: llc < %s -mtriple=mipsel-linux-gnu -mcpu=mips32r2 | FileCheck %s -check-prefix=32R2 +; RUN: llc < %s -mtriple=mips64el-linux-gnu -mcpu=mips64 -mattr=n64 | FileCheck %s -check-prefix=64 +; RUN: llc < %s -mtriple=mips64el-linux-gnu -mcpu=mips64r2 -mattr=n64 | FileCheck %s -check-prefix=64R2 +; RUN: llc < %s -mtriple=mipsel-linux-gnu -mcpu=mips32 -enable-no-nans-fp-math | FileCheck %s -check-prefix=NO-NAN define float @foo0(float %a) nounwind readnone { entry: diff --git a/test/CodeGen/Mips/fastcc.ll b/test/CodeGen/Mips/fastcc.ll new file mode 100644 index 0000000..82919e7 --- /dev/null +++ b/test/CodeGen/Mips/fastcc.ll @@ -0,0 +1,253 @@ +; RUN: llc < %s -march=mipsel | FileCheck %s + +@gi0 = external global i32 +@gi1 = external global i32 +@gi2 = external global i32 +@gi3 = external global i32 +@gi4 = external global i32 +@gi5 = external global i32 +@gi6 = external global i32 +@gi7 = external global i32 +@gi8 = external global i32 +@gi9 = external global i32 +@gi10 = external global i32 +@gi11 = external global i32 +@gi12 = external global i32 +@gi13 = external global i32 +@gi14 = external global i32 +@gi15 = external global i32 +@gi16 = external global i32 +@gfa0 = external global float +@gfa1 = external global float +@gfa2 = external global float +@gfa3 = external global float +@gfa4 = external global float +@gfa5 = external global float +@gfa6 = external global float +@gfa7 = external global float +@gfa8 = external global float +@gfa9 = external global float +@gfa10 = external global float +@gfa11 = external global float +@gfa12 = external global float +@gfa13 = external global float +@gfa14 = external global float +@gfa15 = external global float +@gfa16 = external global float +@gfa17 = external global float +@gfa18 = external global float +@gfa19 = external global float +@gfa20 = external global float +@gf0 = external global float +@gf1 = external global float +@gf2 = external global float +@gf3 = external global float +@gf4 = external global float +@gf5 = external global float +@gf6 = external global float +@gf7 = external global float +@gf8 = external global float +@gf9 = external global float +@gf10 = external global float +@gf11 = external global float +@gf12 = external global float +@gf13 = external global float +@gf14 = external global float +@gf15 = external global float +@gf16 = external global float +@gf17 = external global float +@gf18 = external global float +@gf19 = external global float +@gf20 = external global float +@g0 = external global i32 +@g1 = external global i32 +@g2 = external global i32 +@g3 = external global i32 +@g4 = external global i32 +@g5 = external global i32 +@g6 = external global i32 +@g7 = external global i32 +@g8 = external global i32 +@g9 = external global i32 +@g10 = external global i32 +@g11 = external global i32 +@g12 = external global i32 +@g13 = external global i32 +@g14 = external global i32 +@g15 = external global i32 +@g16 = external global i32 + +define void @caller0() nounwind { +entry: +; CHECK: caller0 +; CHECK: lw $3 +; CHECK: lw $24 +; CHECK: lw $15 +; CHECK: lw $14 +; CHECK: lw $13 +; CHECK: lw $12 +; CHECK: lw $11 +; CHECK: lw $10 +; CHECK: lw $9 +; CHECK: lw $8 +; CHECK: lw $7 +; CHECK: lw $6 +; CHECK: lw $5 +; CHECK: lw $4 + + %0 = load i32* @gi0, align 4 + %1 = load i32* @gi1, align 4 + %2 = load i32* @gi2, align 4 + %3 = load i32* @gi3, align 4 + %4 = load i32* @gi4, align 4 + %5 = load i32* @gi5, align 4 + %6 = load i32* @gi6, align 4 + %7 = load i32* @gi7, align 4 + %8 = load i32* @gi8, align 4 + %9 = load i32* @gi9, align 4 + %10 = load i32* @gi10, align 4 + %11 = load i32* @gi11, align 4 + %12 = load i32* @gi12, align 4 + %13 = load i32* @gi13, align 4 + %14 = load i32* @gi14, align 4 + %15 = load i32* @gi15, align 4 + %16 = load i32* @gi16, align 4 + tail call fastcc void @callee0(i32 %0, i32 %1, i32 %2, i32 %3, i32 %4, i32 %5, i32 %6, i32 %7, i32 %8, i32 %9, i32 %10, i32 %11, i32 %12, i32 %13, i32 %14, i32 %15, i32 %16) + ret void +} + +define internal fastcc void @callee0(i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %a4, i32 %a5, i32 %a6, i32 %a7, i32 %a8, i32 %a9, i32 %a10, i32 %a11, i32 %a12, i32 %a13, i32 %a14, i32 %a15, i32 %a16) nounwind noinline { +entry: +; CHECK: callee0 +; CHECK: sw $4 +; CHECK: sw $5 +; CHECK: sw $6 +; CHECK: sw $7 +; CHECK: sw $8 +; CHECK: sw $9 +; CHECK: sw $10 +; CHECK: sw $11 +; CHECK: sw $12 +; CHECK: sw $13 +; CHECK: sw $14 +; CHECK: sw $15 +; CHECK: sw $24 +; CHECK: sw $3 + + store i32 %a0, i32* @g0, align 4 + store i32 %a1, i32* @g1, align 4 + store i32 %a2, i32* @g2, align 4 + store i32 %a3, i32* @g3, align 4 + store i32 %a4, i32* @g4, align 4 + store i32 %a5, i32* @g5, align 4 + store i32 %a6, i32* @g6, align 4 + store i32 %a7, i32* @g7, align 4 + store i32 %a8, i32* @g8, align 4 + store i32 %a9, i32* @g9, align 4 + store i32 %a10, i32* @g10, align 4 + store i32 %a11, i32* @g11, align 4 + store i32 %a12, i32* @g12, align 4 + store i32 %a13, i32* @g13, align 4 + store i32 %a14, i32* @g14, align 4 + store i32 %a15, i32* @g15, align 4 + store i32 %a16, i32* @g16, align 4 + ret void +} + +define void @caller1(float %a0, float %a1, float %a2, float %a3, float %a4, float %a5, float %a6, float %a7, float %a8, float %a9, float %a10, float %a11, float %a12, float %a13, float %a14, float %a15, float %a16, float %a17, float %a18, float %a19, float %a20) nounwind { +entry: +; CHECK: caller1 +; CHECK: lwc1 $f19 +; CHECK: lwc1 $f18 +; CHECK: lwc1 $f17 +; CHECK: lwc1 $f16 +; CHECK: lwc1 $f15 +; CHECK: lwc1 $f14 +; CHECK: lwc1 $f13 +; CHECK: lwc1 $f12 +; CHECK: lwc1 $f11 +; CHECK: lwc1 $f10 +; CHECK: lwc1 $f9 +; CHECK: lwc1 $f8 +; CHECK: lwc1 $f7 +; CHECK: lwc1 $f6 +; CHECK: lwc1 $f5 +; CHECK: lwc1 $f4 +; CHECK: lwc1 $f3 +; CHECK: lwc1 $f2 +; CHECK: lwc1 $f1 +; CHECK: lwc1 $f0 + + %0 = load float* @gfa0, align 4 + %1 = load float* @gfa1, align 4 + %2 = load float* @gfa2, align 4 + %3 = load float* @gfa3, align 4 + %4 = load float* @gfa4, align 4 + %5 = load float* @gfa5, align 4 + %6 = load float* @gfa6, align 4 + %7 = load float* @gfa7, align 4 + %8 = load float* @gfa8, align 4 + %9 = load float* @gfa9, align 4 + %10 = load float* @gfa10, align 4 + %11 = load float* @gfa11, align 4 + %12 = load float* @gfa12, align 4 + %13 = load float* @gfa13, align 4 + %14 = load float* @gfa14, align 4 + %15 = load float* @gfa15, align 4 + %16 = load float* @gfa16, align 4 + %17 = load float* @gfa17, align 4 + %18 = load float* @gfa18, align 4 + %19 = load float* @gfa19, align 4 + %20 = load float* @gfa20, align 4 + tail call fastcc void @callee1(float %0, float %1, float %2, float %3, float %4, float %5, float %6, float %7, float %8, float %9, float %10, float %11, float %12, float %13, float %14, float %15, float %16, float %17, float %18, float %19, float %20) + ret void +} + +define internal fastcc void @callee1(float %a0, float %a1, float %a2, float %a3, float %a4, float %a5, float %a6, float %a7, float %a8, float %a9, float %a10, float %a11, float %a12, float %a13, float %a14, float %a15, float %a16, float %a17, float %a18, float %a19, float %a20) nounwind noinline { +entry: +; CHECK: callee1 +; CHECK: swc1 $f0 +; CHECK: swc1 $f1 +; CHECK: swc1 $f2 +; CHECK: swc1 $f3 +; CHECK: swc1 $f4 +; CHECK: swc1 $f5 +; CHECK: swc1 $f6 +; CHECK: swc1 $f7 +; CHECK: swc1 $f8 +; CHECK: swc1 $f9 +; CHECK: swc1 $f10 +; CHECK: swc1 $f11 +; CHECK: swc1 $f12 +; CHECK: swc1 $f13 +; CHECK: swc1 $f14 +; CHECK: swc1 $f15 +; CHECK: swc1 $f16 +; CHECK: swc1 $f17 +; CHECK: swc1 $f18 +; CHECK: swc1 $f19 + + store float %a0, float* @gf0, align 4 + store float %a1, float* @gf1, align 4 + store float %a2, float* @gf2, align 4 + store float %a3, float* @gf3, align 4 + store float %a4, float* @gf4, align 4 + store float %a5, float* @gf5, align 4 + store float %a6, float* @gf6, align 4 + store float %a7, float* @gf7, align 4 + store float %a8, float* @gf8, align 4 + store float %a9, float* @gf9, align 4 + store float %a10, float* @gf10, align 4 + store float %a11, float* @gf11, align 4 + store float %a12, float* @gf12, align 4 + store float %a13, float* @gf13, align 4 + store float %a14, float* @gf14, align 4 + store float %a15, float* @gf15, align 4 + store float %a16, float* @gf16, align 4 + store float %a17, float* @gf17, align 4 + store float %a18, float* @gf18, align 4 + store float %a19, float* @gf19, align 4 + store float %a20, float* @gf20, align 4 + ret void +} + diff --git a/test/CodeGen/Mips/fp-indexed-ls.ll b/test/CodeGen/Mips/fp-indexed-ls.ll index 08bd6e7..1c4a3fd 100644 --- a/test/CodeGen/Mips/fp-indexed-ls.ll +++ b/test/CodeGen/Mips/fp-indexed-ls.ll @@ -28,7 +28,7 @@ entry: define float @foo2(i32 %b, i32 %c) nounwind readonly { entry: -; CHECK: luxc1 +; CHECK-NOT: luxc1 %arrayidx1 = getelementptr inbounds [4 x %struct.S]* @s, i32 0, i32 %b, i32 0, i32 %c %0 = load float* %arrayidx1, align 1 ret float %0 @@ -54,7 +54,7 @@ entry: define void @foo5(i32 %b, i32 %c) nounwind { entry: -; CHECK: suxc1 +; CHECK-NOT: suxc1 %0 = load float* @gf, align 4 %arrayidx1 = getelementptr inbounds [4 x %struct.S]* @s, i32 0, i32 %b, i32 0, i32 %c store float %0, float* %arrayidx1, align 1 @@ -64,7 +64,7 @@ entry: define double @foo6(i32 %b, i32 %c) nounwind readonly { entry: ; CHECK: foo6 -; CHECK-NOT: ldxc1 +; CHECK-NOT: luxc1 %arrayidx1 = getelementptr inbounds [4 x %struct.S2]* @s2, i32 0, i32 %b, i32 0, i32 %c %0 = load double* %arrayidx1, align 1 ret double %0 @@ -73,7 +73,7 @@ entry: define void @foo7(i32 %b, i32 %c) nounwind { entry: ; CHECK: foo7 -; CHECK-NOT: sdxc1 +; CHECK-NOT: suxc1 %0 = load double* @gd, align 8 %arrayidx1 = getelementptr inbounds [4 x %struct.S2]* @s2, i32 0, i32 %b, i32 0, i32 %c store double %0, double* %arrayidx1, align 1 @@ -83,7 +83,7 @@ entry: define float @foo8() nounwind readonly { entry: ; CHECK: foo8 -; CHECK: luxc1 +; CHECK-NOT: luxc1 %0 = load float* getelementptr inbounds (%struct.S3* @s3, i32 0, i32 1), align 1 ret float %0 } @@ -91,7 +91,7 @@ entry: define void @foo9(float %f) nounwind { entry: ; CHECK: foo9 -; CHECK: suxc1 +; CHECK-NOT: suxc1 store float %f, float* getelementptr inbounds (%struct.S3* @s3, i32 0, i32 1), align 1 ret void } diff --git a/test/CodeGen/Mips/fp-spill-reload.ll b/test/CodeGen/Mips/fp-spill-reload.ll new file mode 100644 index 0000000..f9887a5 --- /dev/null +++ b/test/CodeGen/Mips/fp-spill-reload.ll @@ -0,0 +1,39 @@ +; RUN: llc -march=mipsel < %s | FileCheck %s +; check that $fp is not reserved. + +define void @foo0(i32* nocapture %b) nounwind { +entry: +; CHECK: sw $fp +; CHECK: lw $fp + %0 = load i32* %b, align 4 + %arrayidx.1 = getelementptr inbounds i32* %b, i32 1 + %1 = load i32* %arrayidx.1, align 4 + %add.1 = add nsw i32 %1, 1 + %arrayidx.2 = getelementptr inbounds i32* %b, i32 2 + %2 = load i32* %arrayidx.2, align 4 + %add.2 = add nsw i32 %2, 2 + %arrayidx.3 = getelementptr inbounds i32* %b, i32 3 + %3 = load i32* %arrayidx.3, align 4 + %add.3 = add nsw i32 %3, 3 + %arrayidx.4 = getelementptr inbounds i32* %b, i32 4 + %4 = load i32* %arrayidx.4, align 4 + %add.4 = add nsw i32 %4, 4 + %arrayidx.5 = getelementptr inbounds i32* %b, i32 5 + %5 = load i32* %arrayidx.5, align 4 + %add.5 = add nsw i32 %5, 5 + %arrayidx.6 = getelementptr inbounds i32* %b, i32 6 + %6 = load i32* %arrayidx.6, align 4 + %add.6 = add nsw i32 %6, 6 + %arrayidx.7 = getelementptr inbounds i32* %b, i32 7 + %7 = load i32* %arrayidx.7, align 4 + %add.7 = add nsw i32 %7, 7 + call void @foo2(i32 %0, i32 %add.1, i32 %add.2, i32 %add.3, i32 %add.4, i32 %add.5, i32 %add.6, i32 %add.7) nounwind + call void bitcast (void (...)* @foo1 to void ()*)() nounwind + call void @foo2(i32 %0, i32 %add.1, i32 %add.2, i32 %add.3, i32 %add.4, i32 %add.5, i32 %add.6, i32 %add.7) nounwind + ret void +} + +declare void @foo2(i32, i32, i32, i32, i32, i32, i32, i32) + +declare void @foo1(...) + diff --git a/test/CodeGen/Mips/global-pointer-reg.ll b/test/CodeGen/Mips/global-pointer-reg.ll index 174d1f9..1c0eb01 100644 --- a/test/CodeGen/Mips/global-pointer-reg.ll +++ b/test/CodeGen/Mips/global-pointer-reg.ll @@ -1,4 +1,6 @@ -; RUN: llc < %s -march=mipsel -mips-fix-global-base-reg=false | FileCheck %s +; DISABLED: llc < %s -march=mipsel -mips-fix-global-base-reg=false | FileCheck %s +; RUN: false +; XFAIL: * @g0 = external global i32 @g1 = external global i32 diff --git a/test/CodeGen/Mips/gprestore.ll b/test/CodeGen/Mips/gprestore.ll index ee7e131..cbcf0c9 100644 --- a/test/CodeGen/Mips/gprestore.ll +++ b/test/CodeGen/Mips/gprestore.ll @@ -1,4 +1,6 @@ -; RUN: llc -march=mips < %s | FileCheck %s +; DISABLE: llc -march=mips < %s | FileCheck %s +; RUN: false +; XFAIL: * @p = external global i32 @q = external global i32 diff --git a/test/CodeGen/Mips/helloworld.ll b/test/CodeGen/Mips/helloworld.ll new file mode 100644 index 0000000..bee93ac --- /dev/null +++ b/test/CodeGen/Mips/helloworld.ll @@ -0,0 +1,34 @@ +; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=C1 +; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=C2 +; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=PE +; +; re-enable this when mips16's jalr is fixed. +; DISABLED: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=SR + + +@.str = private unnamed_addr constant [13 x i8] c"hello world\0A\00", align 1 + +define i32 @main() nounwind { +entry: + %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([13 x i8]* @.str, i32 0, i32 0)) + ret i32 0 + +; SR: .set mips16 # @main + +; SR: save $ra, [[FS:[0-9]+]] +; PE: li $[[T1:[0-9]+]], %hi(_gp_disp) +; PE: addiu $[[T2:[0-9]+]], $pc, %lo(_gp_disp) +; PE: sll $[[T3:[0-9]+]], $[[T1]], 16 +; C1: lw ${{[0-9]+}}, %got($.str)(${{[0-9]+}}) +; C2: lw ${{[0-9]+}}, %call16(printf)(${{[0-9]+}}) +; C1: addiu ${{[0-9]+}}, %lo($.str) +; C2: move $25, ${{[0-9]+}} +; C1: move $gp, ${{[0-9]+}} +; C1: jalr ${{[0-9]+}} +; SR: restore $ra, [[FS]] +; PE: li $2, 0 +; PE: jr $ra + +} + +declare i32 @printf(i8*, ...) diff --git a/test/CodeGen/Mips/inlineasm-cnstrnt-bad-I-1.ll b/test/CodeGen/Mips/inlineasm-cnstrnt-bad-I-1.ll new file mode 100644 index 0000000..f9e53cb --- /dev/null +++ b/test/CodeGen/Mips/inlineasm-cnstrnt-bad-I-1.ll @@ -0,0 +1,15 @@ +; +;This is a negative test. The constant value given for the constraint +;is greater than 16 bits. +; +; RUN: not llc -march=mipsel < %s 2> %t +; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s + +define i32 @main() nounwind { +entry: + +;CHECK-ERRORS: error: invalid operand for inline asm constraint 'I' + tail call i32 asm sideeffect "addi $0,$1,$2", "=r,r,I"(i32 7, i32 1048576) nounwind + ret i32 0 +} + diff --git a/test/CodeGen/Mips/inlineasm-cnstrnt-bad-J.ll b/test/CodeGen/Mips/inlineasm-cnstrnt-bad-J.ll new file mode 100644 index 0000000..1fdf672 --- /dev/null +++ b/test/CodeGen/Mips/inlineasm-cnstrnt-bad-J.ll @@ -0,0 +1,16 @@ +; +;This is a negative test. The constant value given for the constraint (J) +;is non-zero (3). +; +; RUN: not llc -march=mipsel < %s 2> %t +; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s + +define i32 @main() nounwind { +entry: + +;CHECK-ERRORS: error: invalid operand for inline asm constraint 'J' + + tail call i32 asm "addi $0,$1,$2", "=r,r,J"(i32 1024, i32 3) nounwind + ret i32 0 +} + diff --git a/test/CodeGen/Mips/inlineasm-cnstrnt-bad-K.ll b/test/CodeGen/Mips/inlineasm-cnstrnt-bad-K.ll new file mode 100644 index 0000000..3baf437 --- /dev/null +++ b/test/CodeGen/Mips/inlineasm-cnstrnt-bad-K.ll @@ -0,0 +1,16 @@ +; +;This is a negative test. The constant value given for the constraint (K) +;is greater than 16 bits (0x00100000). +; +; RUN: not llc -march=mipsel < %s 2> %t +; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s + +define i32 @main() nounwind { +entry: + +;CHECK-ERRORS: error: invalid operand for inline asm constraint 'K' + + tail call i32 asm "addu $0,$1,$2", "=r,r,K"(i32 1024, i32 1048576) nounwind + ret i32 0 +} + diff --git a/test/CodeGen/Mips/inlineasm-cnstrnt-bad-L.ll b/test/CodeGen/Mips/inlineasm-cnstrnt-bad-L.ll new file mode 100644 index 0000000..49dcc87 --- /dev/null +++ b/test/CodeGen/Mips/inlineasm-cnstrnt-bad-L.ll @@ -0,0 +1,16 @@ +; +;This is a negative test. The constant value given for the constraint (L) +;is non-zero in the lower 16 bits (0x00100003). +; +; RUN: not llc -march=mipsel < %s 2> %t +; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s + +define i32 @main() nounwind { +entry: + +;CHECK-ERRORS: error: invalid operand for inline asm constraint 'L' + + tail call i32 asm "addi $0,$1,$2", "=r,r,L"(i32 7, i32 1048579) nounwind + ret i32 0 +} + diff --git a/test/CodeGen/Mips/inlineasm-cnstrnt-bad-N.ll b/test/CodeGen/Mips/inlineasm-cnstrnt-bad-N.ll new file mode 100644 index 0000000..770669d --- /dev/null +++ b/test/CodeGen/Mips/inlineasm-cnstrnt-bad-N.ll @@ -0,0 +1,17 @@ + +;This is a negative test. The constant value given for the constraint (N). +;immediate in the range of -65535 to -1 (inclusive). +;Our example uses the positive value 3. +; +; RUN: not llc -march=mipsel < %s 2> %t +; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s + +define i32 @main() nounwind { +entry: + +;CHECK-ERRORS: error: invalid operand for inline asm constraint 'N' + + tail call i32 asm sideeffect "addi $0,$1,$2", "=r,r,N"(i32 7, i32 3) nounwind + ret i32 0 +} + diff --git a/test/CodeGen/Mips/inlineasm-cnstrnt-bad-O.ll b/test/CodeGen/Mips/inlineasm-cnstrnt-bad-O.ll new file mode 100644 index 0000000..cd4431a --- /dev/null +++ b/test/CodeGen/Mips/inlineasm-cnstrnt-bad-O.ll @@ -0,0 +1,16 @@ +; +;This is a negative test. The constant value given for the constraint (O). +;signed 15 bit immediate (+- 16383). +;Our example uses the positive value 16384. +; +; RUN: not llc -march=mipsel < %s 2> %t +; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s + +define i32 @main() nounwind { +entry: + +;CHECK-ERRORS: error: invalid operand for inline asm constraint 'O' + + tail call i32 asm sideeffect "addi $0,$1,$2", "=r,r,O"(i32 undef, i32 16384) nounwind + ret i32 0 +} diff --git a/test/CodeGen/Mips/inlineasm-cnstrnt-bad-P.ll b/test/CodeGen/Mips/inlineasm-cnstrnt-bad-P.ll new file mode 100644 index 0000000..0a4739e --- /dev/null +++ b/test/CodeGen/Mips/inlineasm-cnstrnt-bad-P.ll @@ -0,0 +1,16 @@ +; +; This is a negative test. The constant value given for the constraint (P). +; A constant in the range of 1 to 655535 inclusive. +; Our example uses the positive value 655536. +; +; RUN: not llc -march=mipsel < %s 2> %t +; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s + +define i32 @main() nounwind { +entry: + +;CHECK-ERRORS: error: invalid operand for inline asm constraint 'P' + + tail call i32 asm sideeffect "addi $0,$1,$2", "=r,r,P"(i32 undef, i32 655536) nounwind + ret i32 0 +} diff --git a/test/CodeGen/Mips/inlineasm-cnstrnt-reg.ll b/test/CodeGen/Mips/inlineasm-cnstrnt-reg.ll new file mode 100644 index 0000000..94ded30 --- /dev/null +++ b/test/CodeGen/Mips/inlineasm-cnstrnt-reg.ll @@ -0,0 +1,44 @@ +; Positive test for inline register constraints +; +; RUN: llc -march=mipsel < %s | FileCheck %s + +define i32 @main() nounwind { +entry: + +; r with char +;CHECK: #APP +;CHECK: addi ${{[0-9]+}},${{[0-9]+}},23 +;CHECK: #NO_APP + tail call i8 asm sideeffect "addi $0,$1,$2", "=r,r,n"(i8 27, i8 23) nounwind + +; r with short +;CHECK: #APP +;CHECK: addi ${{[0-9]+}},${{[0-9]+}},13 +;CHECK: #NO_APP + tail call i16 asm sideeffect "addi $0,$1,$2", "=r,r,n"(i16 17, i16 13) nounwind + +; r with int +;CHECK: #APP +;CHECK: addi ${{[0-9]+}},${{[0-9]+}},3 +;CHECK: #NO_APP + tail call i32 asm sideeffect "addi $0,$1,$2", "=r,r,n"(i32 7, i32 3) nounwind + +; Now c with 1024: make sure register $25 is picked +; CHECK: #APP +; CHECK: addi $25,${{[0-9]+}},1024 +; CHECK: #NO_APP + tail call i32 asm sideeffect "addi $0,$1,$2", "=c,c,I"(i32 4194304, i32 1024) nounwind + +; Now l with 1024: make sure register lo is picked. We do this by checking the instruction +; after the inline expression for a mflo to pull the value out of lo. +; CHECK: #APP +; CHECK-NEXT: mtlo ${{[0-9]+}} +; CHECK-NEXT: madd ${{[0-9]+}},${{[0-9]+}} +; CHECK-NEXT: #NO_APP +; CHECK-NEXT: mflo ${{[0-9]+}} + %bosco = alloca i32, align 4 + call i32 asm sideeffect "\09mtlo $3 \0A\09\09madd $1,$2 ", "=l,r,r,r"(i32 7, i32 6, i32 44) nounwind + store volatile i32 %4, i32* %bosco, align 4 + + ret i32 0 +} diff --git a/test/CodeGen/Mips/inlineasm-cnstrnt-reg64.ll b/test/CodeGen/Mips/inlineasm-cnstrnt-reg64.ll new file mode 100644 index 0000000..7870666 --- /dev/null +++ b/test/CodeGen/Mips/inlineasm-cnstrnt-reg64.ll @@ -0,0 +1,20 @@ +; +; Register constraint "r" shouldn't take long long unless +; The target is 64 bit. +; +; +; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=n64 < %s | FileCheck %s + + +define i32 @main() nounwind { +entry: + + +; r with long long +;CHECK: #APP +;CHECK: addi ${{[0-9]+}},${{[0-9]+}},3 +;CHECK: #NO_APP + tail call i64 asm sideeffect "addi $0,$1,$2", "=r,r,i"(i64 7, i64 3) nounwind + ret i32 0 +} + diff --git a/test/CodeGen/Mips/inlineasm-operand-code.ll b/test/CodeGen/Mips/inlineasm-operand-code.ll new file mode 100644 index 0000000..0197899 --- /dev/null +++ b/test/CodeGen/Mips/inlineasm-operand-code.ll @@ -0,0 +1,153 @@ +; Positive test for inline register constraints +; +; RUN: llc -march=mipsel < %s | FileCheck -check-prefix=CHECK_LITTLE_32 %s +; RUN: llc -march=mips < %s | FileCheck -check-prefix=CHECK_BIG_32 %s + +%union.u_tag = type { i64 } +%struct.anon = type { i32, i32 } +@uval = common global %union.u_tag zeroinitializer, align 8 + +; X with -3 +define i32 @constraint_X() nounwind { +entry: +;CHECK_LITTLE_32: constraint_X: +;CHECK_LITTLE_32: #APP +;CHECK_LITTLE_32: addi ${{[0-9]+}},${{[0-9]+}},0xfffffffffffffffd +;CHECK_LITTLE_32: #NO_APP + tail call i32 asm sideeffect "addi $0,$1,${2:X}", "=r,r,I"(i32 7, i32 -3) ; + ret i32 0 +} + +; x with -3 +define i32 @constraint_x() nounwind { +entry: +;CHECK_LITTLE_32: constraint_x: +;CHECK_LITTLE_32: #APP +;CHECK_LITTLE_32: addi ${{[0-9]+}},${{[0-9]+}},0xfffd +;CHECK_LITTLE_32: #NO_APP + tail call i32 asm sideeffect "addi $0,$1,${2:x}", "=r,r,I"(i32 7, i32 -3) ; + ret i32 0 +} + +; d with -3 +define i32 @constraint_d() nounwind { +entry: +;CHECK_LITTLE_32: constraint_d: +;CHECK_LITTLE_32: #APP +;CHECK_LITTLE_32: addi ${{[0-9]+}},${{[0-9]+}},-3 +;CHECK_LITTLE_32: #NO_APP + tail call i32 asm sideeffect "addi $0,$1,${2:d}", "=r,r,I"(i32 7, i32 -3) ; + ret i32 0 +} + +; m with -3 +define i32 @constraint_m() nounwind { +entry: +;CHECK_LITTLE_32: constraint_m: +;CHECK_LITTLE_32: #APP +;CHECK_LITTLE_32: addi ${{[0-9]+}},${{[0-9]+}},-4 +;CHECK_LITTLE_32: #NO_APP + tail call i32 asm sideeffect "addi $0,$1,${2:m}", "=r,r,I"(i32 7, i32 -3) ; + ret i32 0 +} + +; z with -3 +define i32 @constraint_z() nounwind { +entry: +;CHECK_LITTLE_32: constraint_z: +;CHECK_LITTLE_32: #APP +;CHECK_LITTLE_32: addi ${{[0-9]+}},${{[0-9]+}},-3 +;CHECK_LITTLE_32: #NO_APP + tail call i32 asm sideeffect "addi $0,$1,${2:z}", "=r,r,I"(i32 7, i32 -3) ; + +; z with 0 +;CHECK_LITTLE_32: #APP +;CHECK_LITTLE_32: addi ${{[0-9]+}},${{[0-9]+}},$0 +;CHECK_LITTLE_32: #NO_APP + tail call i32 asm sideeffect "addi $0,$1,${2:z}", "=r,r,I"(i32 7, i32 0) nounwind + ret i32 0 +} + +; a long long in 32 bit mode (use to assert) +define i32 @constraint_longlong() nounwind { +entry: +;CHECK_LITTLE_32: constraint_longlong: +;CHECK_LITTLE_32: #APP +;CHECK_LITTLE_32: addi ${{[0-9]+}},${{[0-9]+}},3 +;CHECK_LITTLE_32: #NO_APP + tail call i64 asm sideeffect "addi $0,$1,$2 \0A\09", "=r,r,X"(i64 1229801703532086340, i64 3) nounwind + ret i32 0 +} + +; D, in little endian the source reg will be 4 bytes into the long long +define i32 @constraint_D() nounwind { +entry: +;CHECK_LITTLE_32: constraint_D: +;CHECK_LITTLE_32: lw ${{[0-9]+}}, %got(uval)(${{[0-9,a-z]+}}) +;CHECK_LITTLE_32: lw $[[SECOND:[0-9]+]], 4(${{[0-9]+}}) +;CHECK_LITTLE_32: lw $[[FIRST:[0-9]+]], 0(${{[0-9]+}}) +;CHECK_LITTLE_32: #APP +;CHECK_LITTLE_32: or ${{[0-9]+}},$[[SECOND]],${{[0-9]+}} +;CHECK_LITTLE_32: #NO_APP + +; D, in big endian the source reg will also be 4 bytes into the long long +;CHECK_BIG_32: constraint_D: +;CHECK_BIG_32: lw ${{[0-9]+}}, %got(uval)(${{[0-9,a-z]+}}) +;CHECK_BIG_32: lw $[[SECOND:[0-9]+]], 4(${{[0-9]+}}) +;CHECK_BIG_32: lw $[[FIRST:[0-9]+]], 0(${{[0-9]+}}) +;CHECK_BIG_32: #APP +;CHECK_BIG_32: or ${{[0-9]+}},$[[SECOND]],${{[0-9]+}} +;CHECK_BIG_32: #NO_APP + %bosco = load i64* getelementptr inbounds (%union.u_tag* @uval, i32 0, i32 0), align 8 + %trunc1 = trunc i64 %bosco to i32 + tail call i32 asm sideeffect "or $0,${1:D},$2", "=r,r,r"(i64 %bosco, i32 %trunc1) nounwind + ret i32 0 +} + +; L, in little endian the source reg will be 0 bytes into the long long +define i32 @constraint_L() nounwind { +entry: +;CHECK_LITTLE_32: constraint_L: +;CHECK_LITTLE_32: lw ${{[0-9]+}}, %got(uval)(${{[0-9,a-z]+}}) +;CHECK_LITTLE_32: lw $[[SECOND:[0-9]+]], 4(${{[0-9]+}}) +;CHECK_LITTLE_32: lw $[[FIRST:[0-9]+]], 0(${{[0-9]+}}) +;CHECK_LITTLE_32: #APP +;CHECK_LITTLE_32: or ${{[0-9]+}},$[[FIRST]],${{[0-9]+}} +;CHECK_LITTLE_32: #NO_APP +; L, in big endian the source reg will be 4 bytes into the long long +;CHECK_BIG_32: constraint_L: +;CHECK_BIG_32: lw ${{[0-9]+}}, %got(uval)(${{[0-9,a-z]+}}) +;CHECK_BIG_32: lw $[[SECOND:[0-9]+]], 4(${{[0-9]+}}) +;CHECK_BIG_32: lw $[[FIRST:[0-9]+]], 0(${{[0-9]+}}) +;CHECK_BIG_32: #APP +;CHECK_BIG_32: or ${{[0-9]+}},$[[SECOND]],${{[0-9]+}} +;CHECK_BIG_32: #NO_APP + %bosco = load i64* getelementptr inbounds (%union.u_tag* @uval, i32 0, i32 0), align 8 + %trunc1 = trunc i64 %bosco to i32 + tail call i32 asm sideeffect "or $0,${1:L},$2", "=r,r,r"(i64 %bosco, i32 %trunc1) nounwind + ret i32 0 +} + +; M, in little endian the source reg will be 4 bytes into the long long +define i32 @constraint_M() nounwind { +entry: +;CHECK_LITTLE_32: constraint_M: +;CHECK_LITTLE_32: lw ${{[0-9]+}}, %got(uval)(${{[0-9,a-z]+}}) +;CHECK_LITTLE_32: lw $[[SECOND:[0-9]+]], 4(${{[0-9]+}}) +;CHECK_LITTLE_32: lw $[[FIRST:[0-9]+]], 0(${{[0-9]+}}) +;CHECK_LITTLE_32: #APP +;CHECK_LITTLE_32: or ${{[0-9]+}},$[[SECOND]],${{[0-9]+}} +;CHECK_LITTLE_32: #NO_APP +; M, in big endian the source reg will be 0 bytes into the long long +;CHECK_BIG_32: constraint_M: +;CHECK_BIG_32: lw ${{[0-9]+}}, %got(uval)(${{[0-9,a-z]+}}) +;CHECK_BIG_32: lw $[[SECOND:[0-9]+]], 4(${{[0-9]+}}) +;CHECK_BIG_32: lw $[[FIRST:[0-9]+]], 0(${{[0-9]+}}) +;CHECK_BIG_32: #APP +;CHECK_BIG_32: or ${{[0-9]+}},$[[FIRST]],${{[0-9]+}} +;CHECK_BIG_32: #NO_APP + %bosco = load i64* getelementptr inbounds (%union.u_tag* @uval, i32 0, i32 0), align 8 + %trunc1 = trunc i64 %bosco to i32 + tail call i32 asm sideeffect "or $0,${1:M},$2", "=r,r,r"(i64 %bosco, i32 %trunc1) nounwind + ret i32 0 +} diff --git a/test/CodeGen/Mips/inlineasm_constraint.ll b/test/CodeGen/Mips/inlineasm_constraint.ll new file mode 100644 index 0000000..5adec3b --- /dev/null +++ b/test/CodeGen/Mips/inlineasm_constraint.ll @@ -0,0 +1,55 @@ +; RUN: llc -march=mipsel < %s | FileCheck %s + +define i32 @main() nounwind { +entry: + +; First I with short +; CHECK: #APP +; CHECK: addi ${{[0-9]+}},${{[0-9]+}},4096 +; CHECK: #NO_APP + tail call i16 asm sideeffect "addi $0,$1,$2", "=r,r,I"(i16 7, i16 4096) nounwind + +; Then I with int +; CHECK: #APP +; CHECK: addi ${{[0-9]+}},${{[0-9]+}},-3 +; CHECK: #NO_APP + tail call i32 asm sideeffect "addi $0,$1,$2", "=r,r,I"(i32 7, i32 -3) nounwind + +; Now J with 0 +; CHECK: #APP +; CHECK: addi ${{[0-9]+}},${{[0-9]+}},0 +; CHECK: #NO_APP + tail call i32 asm sideeffect "addi $0,$1,$2\0A\09 ", "=r,r,J"(i32 7, i16 0) nounwind + +; Now K with 64 +; CHECK: #APP +; CHECK: addu ${{[0-9]+}},${{[0-9]+}},64 +; CHECK: #NO_APP + tail call i16 asm sideeffect "addu $0,$1,$2\0A\09 ", "=r,r,K"(i16 7, i16 64) nounwind + +; Now L with 0x00100000 +; CHECK: #APP +; CHECK: add ${{[0-9]+}},${{[0-9]+}},${{[0-9]+}} +; CHECK: #NO_APP + tail call i32 asm sideeffect "add $0,$1,$3\0A\09", "=r,r,L,r"(i32 7, i32 1048576, i32 0) nounwind + +; Now N with -3 +; CHECK: #APP +; CHECK: addi ${{[0-9]+}},${{[0-9]+}},-3 +; CHECK: #NO_APP + tail call i32 asm sideeffect "addi $0,$1,$2", "=r,r,N"(i32 7, i32 -3) nounwind + +; Now O with -3 +; CHECK: #APP +; CHECK: addi ${{[0-9]+}},${{[0-9]+}},-3 +; CHECK: #NO_APP + tail call i32 asm sideeffect "addi $0,$1,$2", "=r,r,O"(i32 7, i16 -3) nounwind + +; Now P with 65535 +; CHECK: #APP +; CHECK: addi ${{[0-9]+}},${{[0-9]+}},65535 +; CHECK: #NO_APP + tail call i32 asm sideeffect "addi $0,$1,$2", "=r,r,P"(i32 7, i32 65535) nounwind + + ret i32 0 +} diff --git a/test/CodeGen/Mips/inlineasmmemop.ll b/test/CodeGen/Mips/inlineasmmemop.ll index 4b31a88..1c7c443 100644 --- a/test/CodeGen/Mips/inlineasmmemop.ll +++ b/test/CodeGen/Mips/inlineasmmemop.ll @@ -11,7 +11,7 @@ entry: ; CHECK: #APP ; CHECK: lw $[[T3:[0-9]+]], 0($[[T0]]) ; CHECK: #NO_APP -; CHECK: lw $[[T1:[0-9]+]], %got(g1)($gp) +; CHECK: lw $[[T1:[0-9]+]], %got(g1) ; CHECK: sw $[[T3]], 0($[[T1]]) %l1 = alloca i32, align 4 diff --git a/test/CodeGen/Mips/internalfunc.ll b/test/CodeGen/Mips/internalfunc.ll index 434b386..863375a 100644 --- a/test/CodeGen/Mips/internalfunc.ll +++ b/test/CodeGen/Mips/internalfunc.ll @@ -6,7 +6,7 @@ define i32 @main(i32 %argc, i8** nocapture %argv) nounwind { entry: -; CHECK: lw $[[R0:[0-9]+]], %got(f2)($gp) +; CHECK: lw $[[R0:[0-9]+]], %got(f2) ; CHECK: addiu $25, $[[R0]], %lo(f2) tail call fastcc void @f2() ret i32 0 @@ -14,7 +14,7 @@ entry: define void @caller(i32 %a0, i32 %a1) nounwind { entry: -; CHECK: lw $[[R1:[0-9]+]], %got(caller.sf1)($gp) +; CHECK: lw $[[R1:[0-9]+]], %got(caller.sf1) ; CHECK: lw $25, %lo(caller.sf1)($[[R1]]) %tobool = icmp eq i32 %a1, 0 br i1 %tobool, label %if.end, label %if.then @@ -25,9 +25,9 @@ if.then: ; preds = %entry br label %if.end if.end: ; preds = %entry, %if.then -; CHECK: lw $[[R2:[0-9]+]], %got(sf2)($gp) +; CHECK: lw $[[R2:[0-9]+]], %got(sf2) ; CHECK: addiu ${{[0-9]+}}, $[[R2]], %lo(sf2) -; CHECK: lw $[[R3:[0-9]+]], %got(caller.sf1)($gp) +; CHECK: lw $[[R3:[0-9]+]], %got(caller.sf1) ; CHECK: sw ${{[0-9]+}}, %lo(caller.sf1)($[[R3]]) %tobool3 = icmp ne i32 %a0, 0 %tmp4 = load void (...)** @gf1, align 4 diff --git a/test/CodeGen/Mips/largeimmprinting.ll b/test/CodeGen/Mips/largeimmprinting.ll index b7c9a9c..2e54879 100644 --- a/test/CodeGen/Mips/largeimmprinting.ll +++ b/test/CodeGen/Mips/largeimmprinting.ll @@ -6,10 +6,9 @@ define void @f() nounwind { entry: -; CHECK: lui $at, 65534 -; CHECK: addiu $at, $at, -24 +; CHECK: lui $at, 65535 +; CHECK: addiu $at, $at, -16 ; CHECK: addu $sp, $sp, $at -; CHECK: .cprestore 65536 %agg.tmp = alloca %struct.S1, align 1 %tmp = getelementptr inbounds %struct.S1* %agg.tmp, i32 0, i32 0, i32 0 diff --git a/test/CodeGen/Mips/lb1.ll b/test/CodeGen/Mips/lb1.ll new file mode 100644 index 0000000..aac2767 --- /dev/null +++ b/test/CodeGen/Mips/lb1.ll @@ -0,0 +1,18 @@ +; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 + +@c = global i8 -1, align 1 +@.str = private unnamed_addr constant [5 x i8] c"%i \0A\00", align 1 + +define i32 @main() nounwind { +entry: + %i = alloca i32, align 4 + %0 = load i8* @c, align 1 +; 16: lb ${{[0-9]+}}, 0(${{[0-9]+}}) + %conv = sext i8 %0 to i32 + store i32 %conv, i32* %i, align 4 + %1 = load i32* %i, align 4 + %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([5 x i8]* @.str, i32 0, i32 0), i32 %1) + ret i32 0 +} + +declare i32 @printf(i8*, ...) diff --git a/test/CodeGen/Mips/lbu1.ll b/test/CodeGen/Mips/lbu1.ll new file mode 100644 index 0000000..63e0cca --- /dev/null +++ b/test/CodeGen/Mips/lbu1.ll @@ -0,0 +1,19 @@ +; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 + +@c = global i8 97, align 1 +@.str = private unnamed_addr constant [5 x i8] c"%c \0A\00", align 1 + +define i32 @main() nounwind { +entry: + %i = alloca i32, align 4 + %0 = load i8* @c, align 1 + %conv = zext i8 %0 to i32 +; 16: lbu ${{[0-9]+}}, 0(${{[0-9]+}}) + store i32 %conv, i32* %i, align 4 + %1 = load i8* @c, align 1 + %conv1 = zext i8 %1 to i32 + %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([5 x i8]* @.str, i32 0, i32 0), i32 %conv1) + ret i32 0 +} + +declare i32 @printf(i8*, ...) diff --git a/test/CodeGen/Mips/lh1.ll b/test/CodeGen/Mips/lh1.ll new file mode 100644 index 0000000..1f95b09 --- /dev/null +++ b/test/CodeGen/Mips/lh1.ll @@ -0,0 +1,18 @@ +; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 + +@s = global i16 -1, align 2 +@.str = private unnamed_addr constant [5 x i8] c"%i \0A\00", align 1 + +define i32 @main() nounwind { +entry: + %i = alloca i32, align 4 + %0 = load i16* @s, align 2 + %conv = sext i16 %0 to i32 +; 16: lh ${{[0-9]+}}, 0(${{[0-9]+}}) + store i32 %conv, i32* %i, align 4 + %1 = load i32* %i, align 4 + %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([5 x i8]* @.str, i32 0, i32 0), i32 %1) + ret i32 0 +} + +declare i32 @printf(i8*, ...) diff --git a/test/CodeGen/Mips/lhu1.ll b/test/CodeGen/Mips/lhu1.ll new file mode 100644 index 0000000..0cfcede --- /dev/null +++ b/test/CodeGen/Mips/lhu1.ll @@ -0,0 +1,19 @@ +; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 + + +@s = global i16 255, align 2 +@.str = private unnamed_addr constant [5 x i8] c"%i \0A\00", align 1 + +define i32 @main() nounwind { +entry: + %i = alloca i32, align 4 + %0 = load i16* @s, align 2 + %conv = zext i16 %0 to i32 +; 16: lhu ${{[0-9]+}}, 0(${{[0-9]+}}) + store i32 %conv, i32* %i, align 4 + %1 = load i32* %i, align 4 + %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([5 x i8]* @.str, i32 0, i32 0), i32 %1) + ret i32 0 +} + +declare i32 @printf(i8*, ...) diff --git a/test/CodeGen/Mips/load-store-left-right.ll b/test/CodeGen/Mips/load-store-left-right.ll new file mode 100644 index 0000000..d0928ee --- /dev/null +++ b/test/CodeGen/Mips/load-store-left-right.ll @@ -0,0 +1,29 @@ +; RUN: llc -march=mipsel < %s | FileCheck -check-prefix=EL %s +; RUN: llc -march=mips < %s | FileCheck -check-prefix=EB %s + +%struct.SI = type { i32 } + +@si = common global %struct.SI zeroinitializer, align 1 + +define i32 @foo_load_i() nounwind readonly { +entry: +; EL: lwl $[[R0:[0-9]+]], 3($[[R1:[0-9]+]]) +; EL: lwr $[[R0]], 0($[[R1]]) +; EB: lwl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]]) +; EB: lwr $[[R0]], 3($[[R1]]) + + %0 = load i32* getelementptr inbounds (%struct.SI* @si, i32 0, i32 0), align 1 + ret i32 %0 +} + +define void @foo_store_i(i32 %a) nounwind { +entry: +; EL: swl $[[R0:[0-9]+]], 3($[[R1:[0-9]+]]) +; EL: swr $[[R0]], 0($[[R1]]) +; EB: swl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]]) +; EB: swr $[[R0]], 3($[[R1]]) + + store i32 %a, i32* getelementptr inbounds (%struct.SI* @si, i32 0, i32 0), align 1 + ret void +} + diff --git a/test/CodeGen/Mips/longbranch.ll b/test/CodeGen/Mips/longbranch.ll new file mode 100644 index 0000000..0227b88 --- /dev/null +++ b/test/CodeGen/Mips/longbranch.ll @@ -0,0 +1,25 @@ +; RUN: llc -march=mipsel -force-mips-long-branch < %s | FileCheck %s -check-prefix=O32 +; RUN: llc -march=mips64el -mcpu=mips64 -mattr=n64 -force-mips-long-branch < %s | FileCheck %s -check-prefix=N64 + +@g0 = external global i32 + +define void @foo1(i32 %s) nounwind { +entry: +; O32: bal +; N64: bal +; N64: highest +; N64: higher + + %tobool = icmp eq i32 %s, 0 + br i1 %tobool, label %if.end, label %if.then + +if.then: ; preds = %entry + %0 = load i32* @g0, align 4 + %add = add nsw i32 %0, 12 + store i32 %add, i32* @g0, align 4 + br label %if.end + +if.end: ; preds = %entry, %if.then + ret void +} + diff --git a/test/CodeGen/Mips/machineverifier.ll b/test/CodeGen/Mips/machineverifier.ll new file mode 100644 index 0000000..c673fe5 --- /dev/null +++ b/test/CodeGen/Mips/machineverifier.ll @@ -0,0 +1,21 @@ +; RUN: llc < %s -march=mipsel -verify-machineinstrs +; Make sure machine verifier understands the last instruction of a basic block +; is not the terminator instruction after delay slot filler pass is run. + +@g = external global i32 + +define void @foo() nounwind { +entry: + %0 = load i32* @g, align 4 + %tobool = icmp eq i32 %0, 0 + br i1 %tobool, label %if.end, label %if.then + +if.then: ; preds = %entry + %add = add nsw i32 %0, 10 + store i32 %add, i32* @g, align 4 + br label %if.end + +if.end: ; preds = %entry, %if.then + ret void +} + diff --git a/test/CodeGen/Mips/memcpy.ll b/test/CodeGen/Mips/memcpy.ll new file mode 100644 index 0000000..39764a9 --- /dev/null +++ b/test/CodeGen/Mips/memcpy.ll @@ -0,0 +1,19 @@ +; RUN: llc -march=mipsel < %s | FileCheck %s + +%struct.S1 = type { i32, [41 x i8] } + +@.str = private unnamed_addr constant [31 x i8] c"abcdefghijklmnopqrstuvwxyzABCD\00", align 1 + +define void @foo1(%struct.S1* %s1, i8 signext %n) nounwind { +entry: +; CHECK-NOT: call16(memcpy + + %arraydecay = getelementptr inbounds %struct.S1* %s1, i32 0, i32 1, i32 0 + tail call void @llvm.memcpy.p0i8.p0i8.i32(i8* %arraydecay, i8* getelementptr inbounds ([31 x i8]* @.str, i32 0, i32 0), i32 31, i32 1, i1 false) + %arrayidx = getelementptr inbounds %struct.S1* %s1, i32 0, i32 1, i32 40 + store i8 %n, i8* %arrayidx, align 1 + ret void +} + +declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32, i1) nounwind + diff --git a/test/CodeGen/Mips/mips64-fp-indexed-ls.ll b/test/CodeGen/Mips/mips64-fp-indexed-ls.ll index 09745fb..bbdc05c 100644 --- a/test/CodeGen/Mips/mips64-fp-indexed-ls.ll +++ b/test/CodeGen/Mips/mips64-fp-indexed-ls.ll @@ -30,7 +30,7 @@ entry: define float @foo2(i32 %b, i32 %c) nounwind readonly { entry: -; CHECK: luxc1 +; CHECK-NOT: luxc1 %idxprom = zext i32 %c to i64 %idxprom1 = zext i32 %b to i64 %arrayidx2 = getelementptr inbounds [4 x %struct.S]* @s, i64 0, i64 %idxprom1, i32 0, i64 %idxprom @@ -60,7 +60,7 @@ entry: define void @foo5(i32 %b, i32 %c) nounwind { entry: -; CHECK: suxc1 +; CHECK-NOT: suxc1 %0 = load float* @gf, align 4 %idxprom = zext i32 %c to i64 %idxprom1 = zext i32 %b to i64 @@ -72,7 +72,7 @@ entry: define double @foo6(i32 %b, i32 %c) nounwind readonly { entry: ; CHECK: foo6 -; CHECK-NOT: ldxc1 +; CHECK-NOT: luxc1 %idxprom = zext i32 %c to i64 %idxprom1 = zext i32 %b to i64 %arrayidx2 = getelementptr inbounds [4 x %struct.S2]* @s2, i64 0, i64 %idxprom1, i32 0, i64 %idxprom @@ -83,7 +83,7 @@ entry: define void @foo7(i32 %b, i32 %c) nounwind { entry: ; CHECK: foo7 -; CHECK-NOT: sdxc1 +; CHECK-NOT: suxc1 %0 = load double* @gd, align 8 %idxprom = zext i32 %c to i64 %idxprom1 = zext i32 %b to i64 @@ -95,7 +95,7 @@ entry: define float @foo8() nounwind readonly { entry: ; CHECK: foo8 -; CHECK: luxc1 +; CHECK-NOT: luxc1 %0 = load float* getelementptr inbounds (%struct.S3* @s3, i64 0, i32 1), align 1 ret float %0 } @@ -103,7 +103,7 @@ entry: define void @foo9(float %f) nounwind { entry: ; CHECK: foo9 -; CHECK: suxc1 +; CHECK-NOT: suxc1 store float %f, float* getelementptr inbounds (%struct.S3* @s3, i64 0, i32 1), align 1 ret void } diff --git a/test/CodeGen/Mips/mips64load-store-left-right.ll b/test/CodeGen/Mips/mips64load-store-left-right.ll new file mode 100644 index 0000000..4561429 --- /dev/null +++ b/test/CodeGen/Mips/mips64load-store-left-right.ll @@ -0,0 +1,73 @@ +; RUN: llc -march=mips64el -mcpu=mips64 -mattr=n64 < %s | FileCheck -check-prefix=EL %s +; RUN: llc -march=mips64 -mcpu=mips64 -mattr=n64 < %s | FileCheck -check-prefix=EB %s + +%struct.SLL = type { i64 } +%struct.SI = type { i32 } +%struct.SUI = type { i32 } + +@sll = common global %struct.SLL zeroinitializer, align 1 +@si = common global %struct.SI zeroinitializer, align 1 +@sui = common global %struct.SUI zeroinitializer, align 1 + +define i64 @foo_load_ll() nounwind readonly { +entry: +; EL: ldl $[[R0:[0-9]+]], 7($[[R1:[0-9]+]]) +; EL: ldr $[[R0]], 0($[[R1]]) +; EB: ldl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]]) +; EB: ldr $[[R0]], 7($[[R1]]) + + %0 = load i64* getelementptr inbounds (%struct.SLL* @sll, i64 0, i32 0), align 1 + ret i64 %0 +} + +define i64 @foo_load_i() nounwind readonly { +entry: +; EL: lwl $[[R0:[0-9]+]], 3($[[R1:[0-9]+]]) +; EL: lwr $[[R0]], 0($[[R1]]) +; EB: lwl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]]) +; EB: lwr $[[R0]], 3($[[R1]]) + + %0 = load i32* getelementptr inbounds (%struct.SI* @si, i64 0, i32 0), align 1 + %conv = sext i32 %0 to i64 + ret i64 %conv +} + +define i64 @foo_load_ui() nounwind readonly { +entry: +; EL: lwl $[[R0:[0-9]+]], 3($[[R1:[0-9]+]]) +; EL: lwr $[[R0]], 0($[[R1]]) +; EL: daddiu $[[R2:[0-9]+]], $zero, 1 +; EL: dsll $[[R3:[0-9]+]], $[[R2]], 32 +; EL: daddiu $[[R4:[0-9]+]], $[[R3]], -1 +; EL: and ${{[0-9]+}}, $[[R0]], $[[R4]] +; EB: lwl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]]) +; EB: lwr $[[R0]], 3($[[R1]]) + + + %0 = load i32* getelementptr inbounds (%struct.SUI* @sui, i64 0, i32 0), align 1 + %conv = zext i32 %0 to i64 + ret i64 %conv +} + +define void @foo_store_ll(i64 %a) nounwind { +entry: +; EL: sdl $[[R0:[0-9]+]], 7($[[R1:[0-9]+]]) +; EL: sdr $[[R0]], 0($[[R1]]) +; EB: sdl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]]) +; EB: sdr $[[R0]], 7($[[R1]]) + + store i64 %a, i64* getelementptr inbounds (%struct.SLL* @sll, i64 0, i32 0), align 1 + ret void +} + +define void @foo_store_i(i32 %a) nounwind { +entry: +; EL: swl $[[R0:[0-9]+]], 3($[[R1:[0-9]+]]) +; EL: swr $[[R0]], 0($[[R1]]) +; EB: swl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]]) +; EB: swr $[[R0]], 3($[[R1]]) + + store i32 %a, i32* getelementptr inbounds (%struct.SI* @si, i64 0, i32 0), align 1 + ret void +} + diff --git a/test/CodeGen/Mips/neg1.ll b/test/CodeGen/Mips/neg1.ll new file mode 100644 index 0000000..281e626 --- /dev/null +++ b/test/CodeGen/Mips/neg1.ll @@ -0,0 +1,15 @@ +; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 + +@i = global i32 10, align 4 +@.str = private unnamed_addr constant [5 x i8] c"%i \0A\00", align 1 + +define i32 @main() nounwind { +entry: + %0 = load i32* @i, align 4 + %sub = sub nsw i32 0, %0 +; 16: neg ${{[0-9]+}}, ${{[0-9]+}} + %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([5 x i8]* @.str, i32 0, i32 0), i32 %sub) + ret i32 0 +} + +declare i32 @printf(i8*, ...) diff --git a/test/CodeGen/Mips/not1.ll b/test/CodeGen/Mips/not1.ll new file mode 100644 index 0000000..2163b23 --- /dev/null +++ b/test/CodeGen/Mips/not1.ll @@ -0,0 +1,16 @@ +; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 + +@x = global i32 65504, align 4 +@y = global i32 60929, align 4 +@.str = private unnamed_addr constant [7 x i8] c"%08x \0A\00", align 1 + +define i32 @main() nounwind { +entry: + %0 = load i32* @x, align 4 + %neg = xor i32 %0, -1 +; 16: not ${{[0-9]+}}, ${{[0-9]+}} + %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([7 x i8]* @.str, i32 0, i32 0), i32 %neg) + ret i32 0 +} + +declare i32 @printf(i8*, ...) diff --git a/test/CodeGen/Mips/null.ll b/test/CodeGen/Mips/null.ll new file mode 100644 index 0000000..7beae99 --- /dev/null +++ b/test/CodeGen/Mips/null.ll @@ -0,0 +1,13 @@ +; RUN: llc -march=mipsel -mcpu=mips16 < %s | FileCheck %s -check-prefix=16 + + +define i32 @main() nounwind { +entry: + ret i32 0 + +; 16: .set mips16 # @main + + +; 16: jr $ra + +} diff --git a/test/CodeGen/Mips/o32_cc_byval.ll b/test/CodeGen/Mips/o32_cc_byval.ll index c5cbc7a..eac0d80 100644 --- a/test/CodeGen/Mips/o32_cc_byval.ll +++ b/test/CodeGen/Mips/o32_cc_byval.ll @@ -10,19 +10,19 @@ define void @f1() nounwind { entry: -; CHECK: lw $[[R1:[0-9]+]], %got(f1.s1)($gp) +; CHECK: lw $[[R1:[0-9]+]], %got(f1.s1) ; CHECK: addiu $[[R0:[0-9]+]], $[[R1]], %lo(f1.s1) ; CHECK: lw $[[R6:[0-9]+]], 28($[[R0]]) -; CHECK: lw $[[R5:[0-9]+]], 24($[[R0]]) -; CHECK: lw $[[R4:[0-9]+]], 20($[[R0]]) -; CHECK: lw $[[R3:[0-9]+]], 16($[[R0]]) -; CHECK: lw $[[R7:[0-9]+]], 12($[[R0]]) -; CHECK: lw $[[R2:[0-9]+]], 8($[[R0]]) ; CHECK: sw $[[R6]], 36($sp) +; CHECK: lw $[[R5:[0-9]+]], 24($[[R0]]) ; CHECK: sw $[[R5]], 32($sp) +; CHECK: lw $[[R4:[0-9]+]], 20($[[R0]]) ; CHECK: sw $[[R4]], 28($sp) +; CHECK: lw $[[R3:[0-9]+]], 16($[[R0]]) ; CHECK: sw $[[R3]], 24($sp) +; CHECK: lw $[[R7:[0-9]+]], 12($[[R0]]) ; CHECK: sw $[[R7]], 20($sp) +; CHECK: lw $[[R2:[0-9]+]], 8($[[R0]]) ; CHECK: sw $[[R2]], 16($sp) ; CHECK: lw $7, 4($[[R0]]) ; CHECK: lw $6, %lo(f1.s1)($[[R1]]) @@ -43,16 +43,16 @@ declare void @callee3(float, %struct.S3* byval, %struct.S1* byval) define void @f2(float %f, %struct.S1* nocapture byval %s1) nounwind { entry: -; CHECK: addiu $sp, $sp, -56 -; CHECK: sw $7, 68($sp) -; CHECK: sw $6, 64($sp) -; CHECK: lw $4, 88($sp) -; CHECK: ldc1 $f[[F0:[0-9]+]], 80($sp) -; CHECK: lw $[[R3:[0-9]+]], 72($sp) -; CHECK: lw $[[R4:[0-9]+]], 76($sp) -; CHECK: lw $[[R2:[0-9]+]], 68($sp) -; CHECK: lh $[[R1:[0-9]+]], 66($sp) -; CHECK: lb $[[R0:[0-9]+]], 64($sp) +; CHECK: addiu $sp, $sp, -48 +; CHECK: sw $7, 60($sp) +; CHECK: sw $6, 56($sp) +; CHECK: lw $4, 80($sp) +; CHECK: ldc1 $f[[F0:[0-9]+]], 72($sp) +; CHECK: lw $[[R3:[0-9]+]], 64($sp) +; CHECK: lw $[[R4:[0-9]+]], 68($sp) +; CHECK: lw $[[R2:[0-9]+]], 60($sp) +; CHECK: lh $[[R1:[0-9]+]], 58($sp) +; CHECK: lb $[[R0:[0-9]+]], 56($sp) ; CHECK: sw $[[R0]], 32($sp) ; CHECK: sw $[[R1]], 28($sp) ; CHECK: sw $[[R2]], 24($sp) @@ -80,13 +80,13 @@ declare void @callee4(i32, double, i64, i32, i16 signext, i8 signext, float) define void @f3(%struct.S2* nocapture byval %s2) nounwind { entry: -; CHECK: addiu $sp, $sp, -56 -; CHECK: sw $7, 68($sp) -; CHECK: sw $6, 64($sp) -; CHECK: sw $5, 60($sp) -; CHECK: sw $4, 56($sp) -; CHECK: lw $4, 56($sp) -; CHECK: lw $[[R0:[0-9]+]], 68($sp) +; CHECK: addiu $sp, $sp, -48 +; CHECK: sw $7, 60($sp) +; CHECK: sw $6, 56($sp) +; CHECK: sw $5, 52($sp) +; CHECK: sw $4, 48($sp) +; CHECK: lw $4, 48($sp) +; CHECK: lw $[[R0:[0-9]+]], 60($sp) ; CHECK: sw $[[R0]], 24($sp) %arrayidx = getelementptr inbounds %struct.S2* %s2, i32 0, i32 0, i32 0 @@ -99,13 +99,13 @@ entry: define void @f4(float %f, %struct.S3* nocapture byval %s3, %struct.S1* nocapture byval %s1) nounwind { entry: -; CHECK: addiu $sp, $sp, -56 -; CHECK: sw $7, 68($sp) -; CHECK: sw $6, 64($sp) -; CHECK: sw $5, 60($sp) -; CHECK: lw $4, 68($sp) -; CHECK: lw $[[R1:[0-9]+]], 88($sp) -; CHECK: lb $[[R0:[0-9]+]], 60($sp) +; CHECK: addiu $sp, $sp, -48 +; CHECK: sw $7, 60($sp) +; CHECK: sw $6, 56($sp) +; CHECK: sw $5, 52($sp) +; CHECK: lw $4, 60($sp) +; CHECK: lw $[[R1:[0-9]+]], 80($sp) +; CHECK: lb $[[R0:[0-9]+]], 52($sp) ; CHECK: sw $[[R0]], 32($sp) ; CHECK: sw $[[R1]], 24($sp) diff --git a/test/CodeGen/Mips/o32_cc_vararg.ll b/test/CodeGen/Mips/o32_cc_vararg.ll index 4a3d9ab..35332b6 100644 --- a/test/CodeGen/Mips/o32_cc_vararg.ll +++ b/test/CodeGen/Mips/o32_cc_vararg.ll @@ -1,6 +1,5 @@ ; RUN: llc -march=mipsel -pre-RA-sched=source < %s | FileCheck %s - ; All test functions do the same thing - they return the first variable ; argument. diff --git a/test/CodeGen/Mips/or1.ll b/test/CodeGen/Mips/or1.ll new file mode 100644 index 0000000..b1c3696 --- /dev/null +++ b/test/CodeGen/Mips/or1.ll @@ -0,0 +1,17 @@ +; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 + +@x = global i32 65504, align 4 +@y = global i32 60929, align 4 +@.str = private unnamed_addr constant [7 x i8] c"%08x \0A\00", align 1 + +define i32 @main() nounwind { +entry: + %0 = load i32* @x, align 4 + %1 = load i32* @y, align 4 + %or = or i32 %0, %1 +; 16: or ${{[0-9]+}}, ${{[0-9]+}} + %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([7 x i8]* @.str, i32 0, i32 0), i32 %or) + ret i32 0 +} + +declare i32 @printf(i8*, ...) diff --git a/test/CodeGen/Mips/ra-allocatable.ll b/test/CodeGen/Mips/ra-allocatable.ll new file mode 100644 index 0000000..7621788 --- /dev/null +++ b/test/CodeGen/Mips/ra-allocatable.ll @@ -0,0 +1,288 @@ +; RUN: llc < %s -march=mipsel | FileCheck %s + +@a0 = external global i32 +@b0 = external global i32* +@a1 = external global i32 +@b1 = external global i32* +@a2 = external global i32 +@b2 = external global i32* +@a3 = external global i32 +@b3 = external global i32* +@a4 = external global i32 +@b4 = external global i32* +@a5 = external global i32 +@b5 = external global i32* +@a6 = external global i32 +@b6 = external global i32* +@a7 = external global i32 +@b7 = external global i32* +@a8 = external global i32 +@b8 = external global i32* +@a9 = external global i32 +@b9 = external global i32* +@a10 = external global i32 +@b10 = external global i32* +@a11 = external global i32 +@b11 = external global i32* +@a12 = external global i32 +@b12 = external global i32* +@a13 = external global i32 +@b13 = external global i32* +@a14 = external global i32 +@b14 = external global i32* +@a15 = external global i32 +@b15 = external global i32* +@a16 = external global i32 +@b16 = external global i32* +@a17 = external global i32 +@b17 = external global i32* +@a18 = external global i32 +@b18 = external global i32* +@a19 = external global i32 +@b19 = external global i32* +@a20 = external global i32 +@b20 = external global i32* +@a21 = external global i32 +@b21 = external global i32* +@a22 = external global i32 +@b22 = external global i32* +@a23 = external global i32 +@b23 = external global i32* +@a24 = external global i32 +@b24 = external global i32* +@a25 = external global i32 +@b25 = external global i32* +@a26 = external global i32 +@b26 = external global i32* +@a27 = external global i32 +@b27 = external global i32* +@a28 = external global i32 +@b28 = external global i32* +@a29 = external global i32 +@b29 = external global i32* +@c0 = external global i32* +@c1 = external global i32* +@c2 = external global i32* +@c3 = external global i32* +@c4 = external global i32* +@c5 = external global i32* +@c6 = external global i32* +@c7 = external global i32* +@c8 = external global i32* +@c9 = external global i32* +@c10 = external global i32* +@c11 = external global i32* +@c12 = external global i32* +@c13 = external global i32* +@c14 = external global i32* +@c15 = external global i32* +@c16 = external global i32* +@c17 = external global i32* +@c18 = external global i32* +@c19 = external global i32* +@c20 = external global i32* +@c21 = external global i32* +@c22 = external global i32* +@c23 = external global i32* +@c24 = external global i32* +@c25 = external global i32* +@c26 = external global i32* +@c27 = external global i32* +@c28 = external global i32* +@c29 = external global i32* + +define i32 @f1() nounwind { +entry: +; CHECK: sw $ra, {{[0-9]+}}($sp) # 4-byte Folded Spill +; CHECK: $ra +; CHECK: lw $ra, {{[0-9]+}}($sp) # 4-byte Folded Reload +; CHECK: jr $ra + + %0 = load i32* @a0, align 4, !tbaa !0 + %1 = load i32** @b0, align 4, !tbaa !3 + store i32 %0, i32* %1, align 4, !tbaa !0 + %2 = load i32* @a1, align 4, !tbaa !0 + %3 = load i32** @b1, align 4, !tbaa !3 + store i32 %2, i32* %3, align 4, !tbaa !0 + %4 = load i32* @a2, align 4, !tbaa !0 + %5 = load i32** @b2, align 4, !tbaa !3 + store i32 %4, i32* %5, align 4, !tbaa !0 + %6 = load i32* @a3, align 4, !tbaa !0 + %7 = load i32** @b3, align 4, !tbaa !3 + store i32 %6, i32* %7, align 4, !tbaa !0 + %8 = load i32* @a4, align 4, !tbaa !0 + %9 = load i32** @b4, align 4, !tbaa !3 + store i32 %8, i32* %9, align 4, !tbaa !0 + %10 = load i32* @a5, align 4, !tbaa !0 + %11 = load i32** @b5, align 4, !tbaa !3 + store i32 %10, i32* %11, align 4, !tbaa !0 + %12 = load i32* @a6, align 4, !tbaa !0 + %13 = load i32** @b6, align 4, !tbaa !3 + store i32 %12, i32* %13, align 4, !tbaa !0 + %14 = load i32* @a7, align 4, !tbaa !0 + %15 = load i32** @b7, align 4, !tbaa !3 + store i32 %14, i32* %15, align 4, !tbaa !0 + %16 = load i32* @a8, align 4, !tbaa !0 + %17 = load i32** @b8, align 4, !tbaa !3 + store i32 %16, i32* %17, align 4, !tbaa !0 + %18 = load i32* @a9, align 4, !tbaa !0 + %19 = load i32** @b9, align 4, !tbaa !3 + store i32 %18, i32* %19, align 4, !tbaa !0 + %20 = load i32* @a10, align 4, !tbaa !0 + %21 = load i32** @b10, align 4, !tbaa !3 + store i32 %20, i32* %21, align 4, !tbaa !0 + %22 = load i32* @a11, align 4, !tbaa !0 + %23 = load i32** @b11, align 4, !tbaa !3 + store i32 %22, i32* %23, align 4, !tbaa !0 + %24 = load i32* @a12, align 4, !tbaa !0 + %25 = load i32** @b12, align 4, !tbaa !3 + store i32 %24, i32* %25, align 4, !tbaa !0 + %26 = load i32* @a13, align 4, !tbaa !0 + %27 = load i32** @b13, align 4, !tbaa !3 + store i32 %26, i32* %27, align 4, !tbaa !0 + %28 = load i32* @a14, align 4, !tbaa !0 + %29 = load i32** @b14, align 4, !tbaa !3 + store i32 %28, i32* %29, align 4, !tbaa !0 + %30 = load i32* @a15, align 4, !tbaa !0 + %31 = load i32** @b15, align 4, !tbaa !3 + store i32 %30, i32* %31, align 4, !tbaa !0 + %32 = load i32* @a16, align 4, !tbaa !0 + %33 = load i32** @b16, align 4, !tbaa !3 + store i32 %32, i32* %33, align 4, !tbaa !0 + %34 = load i32* @a17, align 4, !tbaa !0 + %35 = load i32** @b17, align 4, !tbaa !3 + store i32 %34, i32* %35, align 4, !tbaa !0 + %36 = load i32* @a18, align 4, !tbaa !0 + %37 = load i32** @b18, align 4, !tbaa !3 + store i32 %36, i32* %37, align 4, !tbaa !0 + %38 = load i32* @a19, align 4, !tbaa !0 + %39 = load i32** @b19, align 4, !tbaa !3 + store i32 %38, i32* %39, align 4, !tbaa !0 + %40 = load i32* @a20, align 4, !tbaa !0 + %41 = load i32** @b20, align 4, !tbaa !3 + store i32 %40, i32* %41, align 4, !tbaa !0 + %42 = load i32* @a21, align 4, !tbaa !0 + %43 = load i32** @b21, align 4, !tbaa !3 + store i32 %42, i32* %43, align 4, !tbaa !0 + %44 = load i32* @a22, align 4, !tbaa !0 + %45 = load i32** @b22, align 4, !tbaa !3 + store i32 %44, i32* %45, align 4, !tbaa !0 + %46 = load i32* @a23, align 4, !tbaa !0 + %47 = load i32** @b23, align 4, !tbaa !3 + store i32 %46, i32* %47, align 4, !tbaa !0 + %48 = load i32* @a24, align 4, !tbaa !0 + %49 = load i32** @b24, align 4, !tbaa !3 + store i32 %48, i32* %49, align 4, !tbaa !0 + %50 = load i32* @a25, align 4, !tbaa !0 + %51 = load i32** @b25, align 4, !tbaa !3 + store i32 %50, i32* %51, align 4, !tbaa !0 + %52 = load i32* @a26, align 4, !tbaa !0 + %53 = load i32** @b26, align 4, !tbaa !3 + store i32 %52, i32* %53, align 4, !tbaa !0 + %54 = load i32* @a27, align 4, !tbaa !0 + %55 = load i32** @b27, align 4, !tbaa !3 + store i32 %54, i32* %55, align 4, !tbaa !0 + %56 = load i32* @a28, align 4, !tbaa !0 + %57 = load i32** @b28, align 4, !tbaa !3 + store i32 %56, i32* %57, align 4, !tbaa !0 + %58 = load i32* @a29, align 4, !tbaa !0 + %59 = load i32** @b29, align 4, !tbaa !3 + store i32 %58, i32* %59, align 4, !tbaa !0 + %60 = load i32* @a0, align 4, !tbaa !0 + %61 = load i32** @c0, align 4, !tbaa !3 + store i32 %60, i32* %61, align 4, !tbaa !0 + %62 = load i32* @a1, align 4, !tbaa !0 + %63 = load i32** @c1, align 4, !tbaa !3 + store i32 %62, i32* %63, align 4, !tbaa !0 + %64 = load i32* @a2, align 4, !tbaa !0 + %65 = load i32** @c2, align 4, !tbaa !3 + store i32 %64, i32* %65, align 4, !tbaa !0 + %66 = load i32* @a3, align 4, !tbaa !0 + %67 = load i32** @c3, align 4, !tbaa !3 + store i32 %66, i32* %67, align 4, !tbaa !0 + %68 = load i32* @a4, align 4, !tbaa !0 + %69 = load i32** @c4, align 4, !tbaa !3 + store i32 %68, i32* %69, align 4, !tbaa !0 + %70 = load i32* @a5, align 4, !tbaa !0 + %71 = load i32** @c5, align 4, !tbaa !3 + store i32 %70, i32* %71, align 4, !tbaa !0 + %72 = load i32* @a6, align 4, !tbaa !0 + %73 = load i32** @c6, align 4, !tbaa !3 + store i32 %72, i32* %73, align 4, !tbaa !0 + %74 = load i32* @a7, align 4, !tbaa !0 + %75 = load i32** @c7, align 4, !tbaa !3 + store i32 %74, i32* %75, align 4, !tbaa !0 + %76 = load i32* @a8, align 4, !tbaa !0 + %77 = load i32** @c8, align 4, !tbaa !3 + store i32 %76, i32* %77, align 4, !tbaa !0 + %78 = load i32* @a9, align 4, !tbaa !0 + %79 = load i32** @c9, align 4, !tbaa !3 + store i32 %78, i32* %79, align 4, !tbaa !0 + %80 = load i32* @a10, align 4, !tbaa !0 + %81 = load i32** @c10, align 4, !tbaa !3 + store i32 %80, i32* %81, align 4, !tbaa !0 + %82 = load i32* @a11, align 4, !tbaa !0 + %83 = load i32** @c11, align 4, !tbaa !3 + store i32 %82, i32* %83, align 4, !tbaa !0 + %84 = load i32* @a12, align 4, !tbaa !0 + %85 = load i32** @c12, align 4, !tbaa !3 + store i32 %84, i32* %85, align 4, !tbaa !0 + %86 = load i32* @a13, align 4, !tbaa !0 + %87 = load i32** @c13, align 4, !tbaa !3 + store i32 %86, i32* %87, align 4, !tbaa !0 + %88 = load i32* @a14, align 4, !tbaa !0 + %89 = load i32** @c14, align 4, !tbaa !3 + store i32 %88, i32* %89, align 4, !tbaa !0 + %90 = load i32* @a15, align 4, !tbaa !0 + %91 = load i32** @c15, align 4, !tbaa !3 + store i32 %90, i32* %91, align 4, !tbaa !0 + %92 = load i32* @a16, align 4, !tbaa !0 + %93 = load i32** @c16, align 4, !tbaa !3 + store i32 %92, i32* %93, align 4, !tbaa !0 + %94 = load i32* @a17, align 4, !tbaa !0 + %95 = load i32** @c17, align 4, !tbaa !3 + store i32 %94, i32* %95, align 4, !tbaa !0 + %96 = load i32* @a18, align 4, !tbaa !0 + %97 = load i32** @c18, align 4, !tbaa !3 + store i32 %96, i32* %97, align 4, !tbaa !0 + %98 = load i32* @a19, align 4, !tbaa !0 + %99 = load i32** @c19, align 4, !tbaa !3 + store i32 %98, i32* %99, align 4, !tbaa !0 + %100 = load i32* @a20, align 4, !tbaa !0 + %101 = load i32** @c20, align 4, !tbaa !3 + store i32 %100, i32* %101, align 4, !tbaa !0 + %102 = load i32* @a21, align 4, !tbaa !0 + %103 = load i32** @c21, align 4, !tbaa !3 + store i32 %102, i32* %103, align 4, !tbaa !0 + %104 = load i32* @a22, align 4, !tbaa !0 + %105 = load i32** @c22, align 4, !tbaa !3 + store i32 %104, i32* %105, align 4, !tbaa !0 + %106 = load i32* @a23, align 4, !tbaa !0 + %107 = load i32** @c23, align 4, !tbaa !3 + store i32 %106, i32* %107, align 4, !tbaa !0 + %108 = load i32* @a24, align 4, !tbaa !0 + %109 = load i32** @c24, align 4, !tbaa !3 + store i32 %108, i32* %109, align 4, !tbaa !0 + %110 = load i32* @a25, align 4, !tbaa !0 + %111 = load i32** @c25, align 4, !tbaa !3 + store i32 %110, i32* %111, align 4, !tbaa !0 + %112 = load i32* @a26, align 4, !tbaa !0 + %113 = load i32** @c26, align 4, !tbaa !3 + store i32 %112, i32* %113, align 4, !tbaa !0 + %114 = load i32* @a27, align 4, !tbaa !0 + %115 = load i32** @c27, align 4, !tbaa !3 + store i32 %114, i32* %115, align 4, !tbaa !0 + %116 = load i32* @a28, align 4, !tbaa !0 + %117 = load i32** @c28, align 4, !tbaa !3 + store i32 %116, i32* %117, align 4, !tbaa !0 + %118 = load i32* @a29, align 4, !tbaa !0 + %119 = load i32** @c29, align 4, !tbaa !3 + store i32 %118, i32* %119, align 4, !tbaa !0 + %120 = load i32* @a0, align 4, !tbaa !0 + ret i32 %120 +} + +!0 = metadata !{metadata !"int", metadata !1} +!1 = metadata !{metadata !"omnipotent char", metadata !2} +!2 = metadata !{metadata !"Simple C/C++ TBAA"} +!3 = metadata !{metadata !"any pointer", metadata !1} diff --git a/test/CodeGen/Mips/rdhwr-directives.ll b/test/CodeGen/Mips/rdhwr-directives.ll new file mode 100644 index 0000000..27010d4 --- /dev/null +++ b/test/CodeGen/Mips/rdhwr-directives.ll @@ -0,0 +1,15 @@ +; RUN: llc -march=mipsel -mcpu=mips32 -relocation-model=static < %s | FileCheck %s + +@a = external thread_local global i32 + +define i32 @foo() nounwind readonly { +entry: +; CHECK: .set push +; CHECK: .set mips32r2 +; CHECK: rdhwr +; CHECK: .set pop + + %0 = load i32* @a, align 4 + ret i32 %0 +} + diff --git a/test/CodeGen/Mips/return_address.ll b/test/CodeGen/Mips/return_address.ll new file mode 100644 index 0000000..e1c9241 --- /dev/null +++ b/test/CodeGen/Mips/return_address.ll @@ -0,0 +1,23 @@ +; RUN: llc -march=mipsel < %s | FileCheck %s + +define i8* @f1() nounwind { +entry: + %0 = call i8* @llvm.returnaddress(i32 0) + ret i8* %0 + +; CHECK: addu $2, $zero, $ra +} + +define i8* @f2() nounwind { +entry: + call void @g() + %0 = call i8* @llvm.returnaddress(i32 0) + ret i8* %0 + +; CHECK: addu $[[R0:[0-9]+]], $zero, $ra +; CHECK: jal +; CHECK: addu $2, $zero, $[[R0]] +} + +declare i8* @llvm.returnaddress(i32) nounwind readnone +declare void @g() diff --git a/test/CodeGen/Mips/sb1.ll b/test/CodeGen/Mips/sb1.ll new file mode 100644 index 0000000..e1a28d4 --- /dev/null +++ b/test/CodeGen/Mips/sb1.ll @@ -0,0 +1,20 @@ +; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 + +@i = global i32 97, align 4 +@c = common global i8 0, align 1 +@.str = private unnamed_addr constant [8 x i8] c"%i %c \0A\00", align 1 + +define i32 @main() nounwind { +entry: + %0 = load i32* @i, align 4 + %conv = trunc i32 %0 to i8 + store i8 %conv, i8* @c, align 1 + %1 = load i32* @i, align 4 + %2 = load i8* @c, align 1 + %conv1 = sext i8 %2 to i32 +; 16: sb ${{[0-9]+}}, 0(${{[0-9]+}}) + %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([8 x i8]* @.str, i32 0, i32 0), i32 %1, i32 %conv1) + ret i32 0 +} + +declare i32 @printf(i8*, ...) diff --git a/test/CodeGen/Mips/selectcc.ll b/test/CodeGen/Mips/selectcc.ll new file mode 100644 index 0000000..a17517e --- /dev/null +++ b/test/CodeGen/Mips/selectcc.ll @@ -0,0 +1,27 @@ +; RUN: llc -march=mipsel < %s + +@gf0 = external global float +@gf1 = external global float +@gd0 = external global double +@gd1 = external global double + +define float @select_cc_f32(float %a, float %b) nounwind { +entry: + store float 0.000000e+00, float* @gf0, align 4 + store float 1.000000e+00, float* @gf1, align 4 + %cmp = fcmp olt float %a, %b + %conv = zext i1 %cmp to i32 + %conv1 = sitofp i32 %conv to float + ret float %conv1 +} + +define double @select_cc_f64(double %a, double %b) nounwind { +entry: + store double 0.000000e+00, double* @gd0, align 8 + store double 1.000000e+00, double* @gd1, align 8 + %cmp = fcmp olt double %a, %b + %conv = zext i1 %cmp to i32 + %conv1 = sitofp i32 %conv to double + ret double %conv1 +} + diff --git a/test/CodeGen/Mips/sh1.ll b/test/CodeGen/Mips/sh1.ll new file mode 100644 index 0000000..1746ae2 --- /dev/null +++ b/test/CodeGen/Mips/sh1.ll @@ -0,0 +1,20 @@ +; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 + +@i = global i32 97, align 4 +@s = common global i16 0, align 2 +@.str = private unnamed_addr constant [9 x i8] c"%i %hi \0A\00", align 1 + +define i32 @main() nounwind { +entry: + %0 = load i32* @i, align 4 + %conv = trunc i32 %0 to i16 + store i16 %conv, i16* @s, align 2 + %1 = load i32* @i, align 4 + %2 = load i16* @s, align 2 + %conv1 = sext i16 %2 to i32 +; 16: sh ${{[0-9]+}}, 0(${{[0-9]+}}) + %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([9 x i8]* @.str, i32 0, i32 0), i32 %1, i32 %conv1) + ret i32 0 +} + +declare i32 @printf(i8*, ...) diff --git a/test/CodeGen/Mips/shift-parts.ll b/test/CodeGen/Mips/shift-parts.ll new file mode 100644 index 0000000..38cbf28 --- /dev/null +++ b/test/CodeGen/Mips/shift-parts.ll @@ -0,0 +1,29 @@ +; RUN: llc -march=mipsel < %s | FileCheck %s + +define i64 @shl0(i64 %a, i32 %b) nounwind readnone { +entry: +; CHECK: shl0 +; CHECK-NOT: lw $25, %call16(__ + %sh_prom = zext i32 %b to i64 + %shl = shl i64 %a, %sh_prom + ret i64 %shl +} + +define i64 @shr1(i64 %a, i32 %b) nounwind readnone { +entry: +; CHECK: shr1 +; CHECK-NOT: lw $25, %call16(__ + %sh_prom = zext i32 %b to i64 + %shr = lshr i64 %a, %sh_prom + ret i64 %shr +} + +define i64 @sra2(i64 %a, i32 %b) nounwind readnone { +entry: +; CHECK: sra2 +; CHECK-NOT: lw $25, %call16(__ + %sh_prom = zext i32 %b to i64 + %shr = ashr i64 %a, %sh_prom + ret i64 %shr +} + diff --git a/test/CodeGen/Mips/sitofp-selectcc-opt.ll b/test/CodeGen/Mips/sitofp-selectcc-opt.ll new file mode 100644 index 0000000..576cbd8 --- /dev/null +++ b/test/CodeGen/Mips/sitofp-selectcc-opt.ll @@ -0,0 +1,22 @@ +; RUN: llc -march=mipsel < %s | FileCheck %s + +@foo12.d4 = internal unnamed_addr global double 0.000000e+00, align 8 + +define double @foo12(i32 %a, i32, i64 %b) nounwind { +entry: +; check that this transformation doesn't happen: +; (sint_to_fp (setcc x, y, cc)) -> (select_cc x, y, -1.0, 0.0,, cc) +; +; CHECK-NOT: # double -1.000000e+00 + + %tobool1 = icmp ne i32 %a, 0 + %not.tobool = icmp ne i64 %b, 0 + %tobool1. = or i1 %tobool1, %not.tobool + %lor.ext = zext i1 %tobool1. to i32 + %conv = sitofp i32 %lor.ext to double + %1 = load double* @foo12.d4, align 8 + %add = fadd double %conv, %1 + store double %add, double* @foo12.d4, align 8 + ret double %add +} + diff --git a/test/CodeGen/Mips/sll1.ll b/test/CodeGen/Mips/sll1.ll new file mode 100644 index 0000000..fdcd38c --- /dev/null +++ b/test/CodeGen/Mips/sll1.ll @@ -0,0 +1,19 @@ +; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 + +@i = global i32 10, align 4 +@j = global i32 0, align 4 +@.str = private unnamed_addr constant [5 x i8] c"%i \0A\00", align 1 + +define i32 @main() nounwind { +entry: +; 16: sll ${{[0-9]+}}, ${{[0-9]+}}, {{[0-9]+}} + %0 = load i32* @i, align 4 + %shl = shl i32 %0, 4 +; 16: sll ${{[0-9]+}}, ${{[0-9]+}}, {{[0-9]+}} + store i32 %shl, i32* @j, align 4 + %1 = load i32* @j, align 4 + %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([5 x i8]* @.str, i32 0, i32 0), i32 %1) + ret i32 0 +} + +declare i32 @printf(i8*, ...) diff --git a/test/CodeGen/Mips/sll2.ll b/test/CodeGen/Mips/sll2.ll new file mode 100644 index 0000000..c2af454 --- /dev/null +++ b/test/CodeGen/Mips/sll2.ll @@ -0,0 +1,19 @@ +; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 + +@i = global i32 10, align 4 +@j = global i32 4, align 4 +@.str = private unnamed_addr constant [5 x i8] c"%i \0A\00", align 1 + +define i32 @main() nounwind { +entry: + %0 = load i32* @i, align 4 + %1 = load i32* @j, align 4 + %shl = shl i32 %0, %1 +; 16: sllv ${{[0-9]+}}, ${{[0-9]+}} + store i32 %shl, i32* @i, align 4 + %2 = load i32* @j, align 4 + %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([5 x i8]* @.str, i32 0, i32 0), i32 %2) + ret i32 0 +} + +declare i32 @printf(i8*, ...) diff --git a/test/CodeGen/Mips/sra1.ll b/test/CodeGen/Mips/sra1.ll new file mode 100644 index 0000000..15bf8d6 --- /dev/null +++ b/test/CodeGen/Mips/sra1.ll @@ -0,0 +1,15 @@ +; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 + +@i = global i32 -354, align 4 +@.str = private unnamed_addr constant [5 x i8] c"%i \0A\00", align 1 + +define i32 @main() nounwind { +entry: + %0 = load i32* @i, align 4 + %shr = ashr i32 %0, 3 +; 16: sra ${{[0-9]+}}, ${{[0-9]+}}, {{[0-9]+}} + %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([5 x i8]* @.str, i32 0, i32 0), i32 %shr) + ret i32 0 +} + +declare i32 @printf(i8*, ...) diff --git a/test/CodeGen/Mips/sra2.ll b/test/CodeGen/Mips/sra2.ll new file mode 100644 index 0000000..26bf19d --- /dev/null +++ b/test/CodeGen/Mips/sra2.ll @@ -0,0 +1,17 @@ +; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 + +@i = global i32 -354, align 4 +@j = global i32 3, align 4 +@.str = private unnamed_addr constant [5 x i8] c"%i \0A\00", align 1 + +define i32 @main() nounwind { +entry: + %0 = load i32* @i, align 4 + %1 = load i32* @j, align 4 + %shr = ashr i32 %0, %1 +; 16: srav ${{[0-9]+}}, ${{[0-9]+}} + %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([5 x i8]* @.str, i32 0, i32 0), i32 %shr) + ret i32 0 +} + +declare i32 @printf(i8*, ...) diff --git a/test/CodeGen/Mips/srl1.ll b/test/CodeGen/Mips/srl1.ll new file mode 100644 index 0000000..3474283 --- /dev/null +++ b/test/CodeGen/Mips/srl1.ll @@ -0,0 +1,18 @@ +; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 + +@i = global i32 10654, align 4 +@j = global i32 0, align 4 +@.str = private unnamed_addr constant [5 x i8] c"%i \0A\00", align 1 + +define i32 @main() nounwind { +entry: + %0 = load i32* @i, align 4 + %shr = lshr i32 %0, 4 +; 16: srl ${{[0-9]+}}, ${{[0-9]+}}, {{[0-9]+}} + store i32 %shr, i32* @j, align 4 + %1 = load i32* @j, align 4 + %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([5 x i8]* @.str, i32 0, i32 0), i32 %1) + ret i32 0 +} + +declare i32 @printf(i8*, ...) diff --git a/test/CodeGen/Mips/srl2.ll b/test/CodeGen/Mips/srl2.ll new file mode 100644 index 0000000..26ec092 --- /dev/null +++ b/test/CodeGen/Mips/srl2.ll @@ -0,0 +1,20 @@ +; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 + +@i = global i32 10654, align 4 +@j = global i32 0, align 4 +@k = global i32 4, align 4 +@.str = private unnamed_addr constant [5 x i8] c"%i \0A\00", align 1 + +define i32 @main() nounwind { +entry: + %0 = load i32* @i, align 4 + %1 = load i32* @k, align 4 + %shr = lshr i32 %0, %1 +; 16: srlv ${{[0-9]+}}, ${{[0-9]+}} + store i32 %shr, i32* @j, align 4 + %2 = load i32* @j, align 4 + %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([5 x i8]* @.str, i32 0, i32 0), i32 %2) + ret i32 0 +} + +declare i32 @printf(i8*, ...) diff --git a/test/CodeGen/Mips/stacksize.ll b/test/CodeGen/Mips/stacksize.ll new file mode 100644 index 0000000..42021b2 --- /dev/null +++ b/test/CodeGen/Mips/stacksize.ll @@ -0,0 +1,9 @@ +; RUN: llc -march=mipsel -relocation-model=static < %s | FileCheck %s + +define i32 @foo(i32 %a) nounwind readnone { +entry: +; check that stack size is zero. +; CHECK-NOT: addiu $sp, $sp + %add = add nsw i32 %a, 1 + ret i32 %add +} diff --git a/test/CodeGen/Mips/sub1.ll b/test/CodeGen/Mips/sub1.ll new file mode 100644 index 0000000..195750b --- /dev/null +++ b/test/CodeGen/Mips/sub1.ll @@ -0,0 +1,15 @@ +; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 + +@i = global i32 10, align 4 +@.str = private unnamed_addr constant [4 x i8] c"%i\0A\00", align 1 + +define i32 @main() nounwind { +entry: + %0 = load i32* @i, align 4 + %sub = sub nsw i32 %0, 5 +; 16: addiu ${{[0-9]+}}, -{{[0-9]+}} + %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i32 %sub) + ret i32 0 +} + +declare i32 @printf(i8*, ...) diff --git a/test/CodeGen/Mips/sub2.ll b/test/CodeGen/Mips/sub2.ll new file mode 100644 index 0000000..4f6bfcc --- /dev/null +++ b/test/CodeGen/Mips/sub2.ll @@ -0,0 +1,17 @@ +; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 + +@i = global i32 10, align 4 +@j = global i32 20, align 4 +@.str = private unnamed_addr constant [4 x i8] c"%i\0A\00", align 1 + +define i32 @main() nounwind { +entry: + %0 = load i32* @j, align 4 + %1 = load i32* @i, align 4 + %sub = sub nsw i32 %0, %1 +; 16: subu ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}} + %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i32 %sub) + ret i32 0 +} + +declare i32 @printf(i8*, ...) diff --git a/test/CodeGen/Mips/swzero.ll b/test/CodeGen/Mips/swzero.ll index da1e036..9f91a39 100644 --- a/test/CodeGen/Mips/swzero.ll +++ b/test/CodeGen/Mips/swzero.ll @@ -4,7 +4,8 @@ define void @zero_u(%struct.unaligned* nocapture %p) nounwind { entry: -; CHECK: usw $zero +; CHECK: swl $zero +; CHECK: swr $zero %x = getelementptr inbounds %struct.unaligned* %p, i32 0, i32 0 store i32 0, i32* %x, align 1 ret void diff --git a/test/CodeGen/Mips/tls-alias.ll b/test/CodeGen/Mips/tls-alias.ll new file mode 100644 index 0000000..d681091 --- /dev/null +++ b/test/CodeGen/Mips/tls-alias.ll @@ -0,0 +1,10 @@ +; RUN: llc -march=mipsel -relocation-model=pic < %s | FileCheck %s + +@foo = thread_local global i32 42 +@bar = hidden alias i32* @foo + +define i32* @zed() { +; CHECK: __tls_get_addr +; CHECK-NEXT: %tlsgd(bar) + ret i32* @bar +} diff --git a/test/CodeGen/Mips/tls-models.ll b/test/CodeGen/Mips/tls-models.ll new file mode 100644 index 0000000..8f5789e --- /dev/null +++ b/test/CodeGen/Mips/tls-models.ll @@ -0,0 +1,113 @@ +; RUN: llc -march=mipsel < %s | FileCheck -check-prefix=CHECK-PIC %s +; RUN: llc -march=mipsel -relocation-model=static < %s | FileCheck -check-prefix=CHECK-NONPIC %s + +@external_gd = external thread_local global i32 +@internal_gd = internal thread_local global i32 42 + +@external_ld = external thread_local(localdynamic) global i32 +@internal_ld = internal thread_local(localdynamic) global i32 42 + +@external_ie = external thread_local(initialexec) global i32 +@internal_ie = internal thread_local(initialexec) global i32 42 + +@external_le = external thread_local(localexec) global i32 +@internal_le = internal thread_local(localexec) global i32 42 + +; ----- no model specified ----- + +define i32* @f1() { +entry: + ret i32* @external_gd + + ; Non-PIC code can use initial-exec, PIC code has to use general dynamic. + ; CHECK-NONPIC: f1: + ; CHECK-NONPIC: %gottprel + ; CHECK-PIC: f1: + ; CHECK-PIC: %tlsgd +} + +define i32* @f2() { +entry: + ret i32* @internal_gd + + ; Non-PIC code can use local exec, PIC code can use local dynamic. + ; CHECK-NONPIC: f2: + ; CHECK-NONPIC: %tprel_hi + ; CHECK-PIC: f2: + ; CHECK-PIC: %tlsldm +} + + +; ----- localdynamic specified ----- + +define i32* @f3() { +entry: + ret i32* @external_ld + + ; Non-PIC code can use initial exec, PIC should use local dynamic. + ; CHECK-NONPIC: f3: + ; CHECK-NONPIC: %gottprel + ; CHECK-PIC: f3: + ; CHECK-PIC: %tlsldm +} + +define i32* @f4() { +entry: + ret i32* @internal_ld + + ; Non-PIC code can use local exec, PIC code can use local dynamic. + ; CHECK-NONPIC: f4: + ; CHECK-NONPIC: %tprel_hi + ; CHECK-PIC: f4: + ; CHECK-PIC: %tlsldm +} + + +; ----- initialexec specified ----- + +define i32* @f5() { +entry: + ret i32* @external_ie + + ; Non-PIC and PIC code will use initial exec as specified. + ; CHECK-NONPIC: f5: + ; CHECK-NONPIC: %gottprel + ; CHECK-PIC: f5: + ; CHECK-PIC: %gottprel +} + +define i32* @f6() { +entry: + ret i32* @internal_ie + + ; Non-PIC code can use local exec, PIC code use initial exec as specified. + ; CHECK-NONPIC: f6: + ; CHECK-NONPIC: %tprel_hi + ; CHECK-PIC: f6: + ; CHECK-PIC: %gottprel +} + + +; ----- localexec specified ----- + +define i32* @f7() { +entry: + ret i32* @external_le + + ; Non-PIC and PIC code will use local exec as specified. + ; CHECK-NONPIC: f7: + ; CHECK-NONPIC: %tprel_hi + ; CHECK-PIC: f7: + ; CHECK-PIC: %tprel_hi +} + +define i32* @f8() { +entry: + ret i32* @internal_le + + ; Non-PIC and PIC code will use local exec as specified. + ; CHECK-NONPIC: f8: + ; CHECK-NONPIC: %tprel_hi + ; CHECK-PIC: f8: + ; CHECK-PIC: %tprel_hi +} diff --git a/test/CodeGen/Mips/tls.ll b/test/CodeGen/Mips/tls.ll index a3c4768..a7ddb96 100644 --- a/test/CodeGen/Mips/tls.ll +++ b/test/CodeGen/Mips/tls.ll @@ -13,8 +13,9 @@ entry: ; CHECK: f1: -; PIC: lw $25, %call16(__tls_get_addr)($gp) -; PIC: addiu $4, $gp, %tlsgd(t1) +; PIC: addu $[[R0:[a-z0-9]+]], $2, $25 +; PIC: lw $25, %call16(__tls_get_addr)($[[R0]]) +; PIC: addiu $4, $[[R0]], %tlsgd(t1) ; PIC: jalr $25 ; PIC: lw $2, 0($2) @@ -35,18 +36,19 @@ entry: ; CHECK: f2: -; PIC: lw $25, %call16(__tls_get_addr)($gp) -; PIC: addiu $4, $gp, %tlsgd(t2) +; PIC: addu $[[R0:[a-z0-9]+]], $2, $25 +; PIC: lw $25, %call16(__tls_get_addr)($[[R0]]) +; PIC: addiu $4, $[[R0]], %tlsgd(t2) ; PIC: jalr $25 ; PIC: lw $2, 0($2) ; STATICGP: lui $[[R0:[0-9]+]], %hi(__gnu_local_gp) ; STATICGP: addiu $[[GP:[0-9]+]], $[[R0]], %lo(__gnu_local_gp) ; STATICGP: lw ${{[0-9]+}}, %gottprel(t2)($[[GP]]) -; STATIC: lui $gp, %hi(__gnu_local_gp) -; STATIC: addiu $gp, $gp, %lo(__gnu_local_gp) +; STATIC: lui $[[R0:[0-9]+]], %hi(__gnu_local_gp) +; STATIC: addiu $[[GP:[0-9]+]], $[[R0]], %lo(__gnu_local_gp) ; STATIC: rdhwr $3, $29 -; STATIC: lw $[[R0:[0-9]+]], %gottprel(t2)($gp) +; STATIC: lw $[[R0:[0-9]+]], %gottprel(t2)($[[GP]]) ; STATIC: addu $[[R1:[0-9]+]], $3, $[[R0]] ; STATIC: lw $2, 0($[[R1]]) } @@ -57,7 +59,7 @@ define i32 @f3() nounwind { entry: ; CHECK: f3: -; PIC: addiu $4, $gp, %tlsldm(f3.i) +; PIC: addiu $4, ${{[a-z0-9]+}}, %tlsldm(f3.i) ; PIC: jalr $25 ; PIC: lui $[[R0:[0-9]+]], %dtprel_hi(f3.i) ; PIC: addu $[[R1:[0-9]+]], $[[R0]], $2 diff --git a/test/CodeGen/Mips/unalignedload.ll b/test/CodeGen/Mips/unalignedload.ll index 6a087ba..7f880b6 100644 --- a/test/CodeGen/Mips/unalignedload.ll +++ b/test/CodeGen/Mips/unalignedload.ll @@ -9,27 +9,17 @@ define void @foo1() nounwind { entry: -; CHECK-EL: ulhu $4, 2 -; CHECK-EL: lw $25, %call16(foo2) -; CHECK-EL: lw $[[R0:[0-9]+]], %got(s4) -; CHECK-EL: lbu $[[R1:[0-9]+]], 6($[[R0]]) -; CHECK-EL: sll $[[R3:[0-9]+]], $[[R1]], 16 -; CHECK-EL: ulhu $[[R2:[0-9]+]], 4($[[R0]]) -; CHECK-EL: or $5, $[[R2]], $[[R3]] -; CHECK-EL: ulw $4, 0($[[R0]]) -; CHECK-EL: lw $25, %call16(foo4) +; CHECK-EL: lbu ${{[0-9]+}}, 2($[[R0:[0-9]+]]) +; CHECK-EL: lbu ${{[0-9]+}}, 3($[[R0]]) +; CHECK-EL: jalr +; CHECK-EL: lwl $[[R1:[0-9]+]], 3($[[R2:[0-9]+]]) +; CHECK-EL: lwr $[[R1]], 0($[[R2]]) -; CHECK-EB: ulhu $[[R0:[0-9]+]], 2 -; CHECK-EB: sll $4, $[[R0]], 16 -; CHECK-EB: lw $25, %call16(foo2) -; CHECK-EB: lw $[[R1:[0-9]+]], %got(s4) -; CHECK-EB: lbu $[[R3:[0-9]+]], 6($[[R1]]) -; CHECK-EB: sll $[[R5:[0-9]+]], $[[R3]], 8 -; CHECK-EB: ulhu $[[R2:[0-9]+]], 4($[[R1]]) -; CHECK-EB: sll $[[R4:[0-9]+]], $[[R2]], 16 -; CHECK-EB: or $5, $[[R4]], $[[R5]] -; CHECK-EB: ulw $4, 0($[[R1]]) -; CHECK-EB: lw $25, %call16(foo4) +; CHECK-EB: lbu ${{[0-9]+}}, 3($[[R0:[0-9]+]]) +; CHECK-EB: lbu ${{[0-9]+}}, 2($[[R0]]) +; CHECK-EB: jalr +; CHECK-EB: lwl $[[R1:[0-9]+]], 0($[[R2:[0-9]+]]) +; CHECK-BE: lwr $[[R1]], 3($[[R2]]) tail call void @foo2(%struct.S1* byval getelementptr inbounds (%struct.S2* @s2, i32 0, i32 1)) nounwind tail call void @foo4(%struct.S4* byval @s4) nounwind diff --git a/test/CodeGen/Mips/xor1.ll b/test/CodeGen/Mips/xor1.ll new file mode 100644 index 0000000..f2c1316 --- /dev/null +++ b/test/CodeGen/Mips/xor1.ll @@ -0,0 +1,17 @@ +; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 + +@x = global i32 65504, align 4 +@y = global i32 60929, align 4 +@.str = private unnamed_addr constant [7 x i8] c"%08x \0A\00", align 1 + +define i32 @main() nounwind { +entry: + %0 = load i32* @x, align 4 + %1 = load i32* @y, align 4 + %xor = xor i32 %0, %1 +; 16: xor ${{[0-9]+}}, ${{[0-9]+}} + %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([7 x i8]* @.str, i32 0, i32 0), i32 %xor) + ret i32 0 +} + +declare i32 @printf(i8*, ...) diff --git a/test/CodeGen/Mips/zeroreg.ll b/test/CodeGen/Mips/zeroreg.ll index b890e1d..79ed609 100644 --- a/test/CodeGen/Mips/zeroreg.ll +++ b/test/CodeGen/Mips/zeroreg.ll @@ -4,8 +4,7 @@ define i32 @foo0(i32 %s) nounwind readonly { entry: -; CHECK-NOT: addiu -; CHECK: movn +; CHECK: movn ${{[0-9]+}}, $zero %tobool = icmp ne i32 %s, 0 %0 = load i32* @g1, align 4, !tbaa !0 %cond = select i1 %tobool, i32 0, i32 %0 @@ -14,8 +13,7 @@ entry: define i32 @foo1(i32 %s) nounwind readonly { entry: -; CHECK-NOT: addiu -; CHECK: movz +; CHECK: movz ${{[0-9]+}}, $zero %tobool = icmp ne i32 %s, 0 %0 = load i32* @g1, align 4, !tbaa !0 %cond = select i1 %tobool, i32 %0, i32 0 |
