diff options
Diffstat (limited to 'test/CodeGen/Mips/o32_cc_vararg.ll')
| -rw-r--r-- | test/CodeGen/Mips/o32_cc_vararg.ll | 75 |
1 files changed, 34 insertions, 41 deletions
diff --git a/test/CodeGen/Mips/o32_cc_vararg.ll b/test/CodeGen/Mips/o32_cc_vararg.ll index 1f71ed2..14ce04b 100644 --- a/test/CodeGen/Mips/o32_cc_vararg.ll +++ b/test/CodeGen/Mips/o32_cc_vararg.ll @@ -1,5 +1,4 @@ ; RUN: llc -march=mipsel -mcpu=mips2 -pre-RA-sched=source < %s | FileCheck %s -; RUN: llc -march=mipsel -mcpu=mips2 -pre-RA-sched=source < %s -regalloc=basic | FileCheck %s ; All test functions do the same thing - they return the first variable @@ -30,11 +29,11 @@ entry: ret i32 %tmp ; CHECK: va1: -; CHECK: addiu $sp, $sp, -32 -; CHECK: sw $7, 44($sp) -; CHECK: sw $6, 40($sp) -; CHECK: sw $5, 36($sp) -; CHECK: lw $2, 36($sp) +; CHECK: addiu $sp, $sp, -16 +; CHECK: sw $7, 28($sp) +; CHECK: sw $6, 24($sp) +; CHECK: sw $5, 20($sp) +; CHECK: lw $2, 20($sp) } ; check whether the variable double argument will be accessed from the 8-byte @@ -56,11 +55,11 @@ entry: ret double %tmp ; CHECK: va2: -; CHECK: addiu $sp, $sp, -40 -; CHECK: sw $7, 52($sp) -; CHECK: sw $6, 48($sp) -; CHECK: sw $5, 44($sp) -; CHECK: addiu $[[R0:[0-9]+]], $sp, 44 +; CHECK: addiu $sp, $sp, -16 +; CHECK: sw $7, 28($sp) +; CHECK: sw $6, 24($sp) +; CHECK: sw $5, 20($sp) +; CHECK: addiu $[[R0:[0-9]+]], $sp, 20 ; CHECK: addiu $[[R1:[0-9]+]], $[[R0]], 7 ; CHECK: addiu $[[R2:[0-9]+]], $zero, -8 ; CHECK: and $[[R3:[0-9]+]], $[[R1]], $[[R2]] @@ -84,10 +83,10 @@ entry: ret i32 %tmp ; CHECK: va3: -; CHECK: addiu $sp, $sp, -40 -; CHECK: sw $7, 52($sp) -; CHECK: sw $6, 48($sp) -; CHECK: lw $2, 48($sp) +; CHECK: addiu $sp, $sp, -16 +; CHECK: sw $7, 28($sp) +; CHECK: sw $6, 24($sp) +; CHECK: lw $2, 24($sp) } ; double @@ -107,14 +106,11 @@ entry: ret double %tmp ; CHECK: va4: -; CHECK: addiu $sp, $sp, -48 -; CHECK: sw $7, 60($sp) -; CHECK: sw $6, 56($sp) -; CHECK: addiu $[[R0:[0-9]+]], $sp, 56 -; CHECK: addiu $[[R1:[0-9]+]], $[[R0]], 7 -; CHECK: addiu $[[R2:[0-9]+]], $zero, -8 -; CHECK: and $[[R3:[0-9]+]], $[[R1]], $[[R2]] -; CHECK: ldc1 $f0, 0($[[R3]]) +; CHECK: addiu $sp, $sp, -24 +; CHECK: sw $7, 36($sp) +; CHECK: sw $6, 32($sp) +; CHECK: addiu ${{[0-9]+}}, $sp, 32 +; CHECK: ldc1 $f0, 32($sp) } ; int @@ -138,9 +134,9 @@ entry: ret i32 %tmp ; CHECK: va5: -; CHECK: addiu $sp, $sp, -40 -; CHECK: sw $7, 52($sp) -; CHECK: lw $2, 52($sp) +; CHECK: addiu $sp, $sp, -24 +; CHECK: sw $7, 36($sp) +; CHECK: lw $2, 36($sp) } ; double @@ -164,9 +160,9 @@ entry: ret double %tmp ; CHECK: va6: -; CHECK: addiu $sp, $sp, -48 -; CHECK: sw $7, 60($sp) -; CHECK: addiu $[[R0:[0-9]+]], $sp, 60 +; CHECK: addiu $sp, $sp, -24 +; CHECK: sw $7, 36($sp) +; CHECK: addiu $[[R0:[0-9]+]], $sp, 36 ; CHECK: addiu $[[R1:[0-9]+]], $[[R0]], 7 ; CHECK: addiu $[[R2:[0-9]+]], $zero, -8 ; CHECK: and $[[R3:[0-9]+]], $[[R1]], $[[R2]] @@ -192,8 +188,8 @@ entry: ret i32 %tmp ; CHECK: va7: -; CHECK: addiu $sp, $sp, -40 -; CHECK: lw $2, 56($sp) +; CHECK: addiu $sp, $sp, -24 +; CHECK: lw $2, 40($sp) } ; double @@ -215,12 +211,9 @@ entry: ret double %tmp ; CHECK: va8: -; CHECK: addiu $sp, $sp, -48 -; CHECK: addiu $[[R0:[0-9]+]], $sp, 64 -; CHECK: addiu $[[R1:[0-9]+]], $[[R0]], 7 -; CHECK: addiu $[[R2:[0-9]+]], $zero, -8 -; CHECK: and $[[R3:[0-9]+]], $[[R1]], $[[R2]] -; CHECK: ldc1 $f0, 0($[[R3]]) +; CHECK: addiu $sp, $sp, -32 +; CHECK: addiu ${{[0-9]+}}, $sp, 48 +; CHECK: ldc1 $f0, 48($sp) } ; int @@ -244,8 +237,8 @@ entry: ret i32 %tmp ; CHECK: va9: -; CHECK: addiu $sp, $sp, -56 -; CHECK: lw $2, 76($sp) +; CHECK: addiu $sp, $sp, -32 +; CHECK: lw $2, 52($sp) } ; double @@ -269,8 +262,8 @@ entry: ret double %tmp ; CHECK: va10: -; CHECK: addiu $sp, $sp, -56 -; CHECK: addiu $[[R0:[0-9]+]], $sp, 76 +; CHECK: addiu $sp, $sp, -32 +; CHECK: addiu $[[R0:[0-9]+]], $sp, 52 ; CHECK: addiu $[[R1:[0-9]+]], $[[R0]], 7 ; CHECK: addiu $[[R2:[0-9]+]], $zero, -8 ; CHECK: and $[[R3:[0-9]+]], $[[R1]], $[[R2]] |
