diff options
Diffstat (limited to 'test/CodeGen/ARM')
84 files changed, 860 insertions, 249 deletions
diff --git a/test/CodeGen/ARM/2008-02-04-LocalRegAllocBug.ll b/test/CodeGen/ARM/2008-02-04-LocalRegAllocBug.ll index f775c61..fd2f462 100644 --- a/test/CodeGen/ARM/2008-02-04-LocalRegAllocBug.ll +++ b/test/CodeGen/ARM/2008-02-04-LocalRegAllocBug.ll @@ -1,4 +1,3 @@ -; RUN: llc < %s -mtriple=arm-linux-gnueabi -regalloc=local ; RUN: llc < %s -mtriple=arm-linux-gnueabi -regalloc=fast ; PR1925 diff --git a/test/CodeGen/ARM/2008-02-29-RegAllocLocal.ll b/test/CodeGen/ARM/2008-02-29-RegAllocLocal.ll index 8ef8c7b..44da8e7 100644 --- a/test/CodeGen/ARM/2008-02-29-RegAllocLocal.ll +++ b/test/CodeGen/ARM/2008-02-29-RegAllocLocal.ll @@ -1,4 +1,3 @@ -; RUN: llc < %s -mtriple=arm-apple-darwin -regalloc=local ; RUN: llc < %s -mtriple=arm-apple-darwin -regalloc=fast ; PR1925 diff --git a/test/CodeGen/ARM/2009-05-07-RegAllocLocal.ll b/test/CodeGen/ARM/2009-05-07-RegAllocLocal.ll index 912e6f9..524b5eb 100644 --- a/test/CodeGen/ARM/2009-05-07-RegAllocLocal.ll +++ b/test/CodeGen/ARM/2009-05-07-RegAllocLocal.ll @@ -1,4 +1,3 @@ -; RUN: llc < %s -mtriple=armv5-unknown-linux-gnueabi -O0 -regalloc=local ; RUN: llc < %s -mtriple=armv5-unknown-linux-gnueabi -O0 -regalloc=fast ; PR4100 @.str = external constant [30 x i8] ; <[30 x i8]*> [#uses=1] diff --git a/test/CodeGen/ARM/2009-06-22-CoalescerBug.ll b/test/CodeGen/ARM/2009-06-22-CoalescerBug.ll index e068be7..7e9b066 100644 --- a/test/CodeGen/ARM/2009-06-22-CoalescerBug.ll +++ b/test/CodeGen/ARM/2009-06-22-CoalescerBug.ll @@ -3,7 +3,7 @@ %struct.rtunion = type { i64 } %struct.rtx_def = type { i16, i8, i8, [1 x %struct.rtunion] } -define arm_apcscc void @simplify_unary_real(i8* nocapture %p) nounwind { +define void @simplify_unary_real(i8* nocapture %p) nounwind { entry: %tmp121 = load i64* null, align 4 ; <i64> [#uses=1] %0 = getelementptr %struct.rtx_def* null, i32 0, i32 3, i32 3, i32 0 ; <i64*> [#uses=1] diff --git a/test/CodeGen/ARM/2009-06-30-RegScavengerAssert.ll b/test/CodeGen/ARM/2009-06-30-RegScavengerAssert.ll index 17efe00..812f018 100644 --- a/test/CodeGen/ARM/2009-06-30-RegScavengerAssert.ll +++ b/test/CodeGen/ARM/2009-06-30-RegScavengerAssert.ll @@ -8,11 +8,11 @@ @"\01LC16" = external constant [33 x i8], align 1 ; <[33 x i8]*> [#uses=1] @"\01LC17" = external constant [47 x i8], align 1 ; <[47 x i8]*> [#uses=1] -declare arm_apcscc i32 @printf(i8* nocapture, ...) nounwind +declare i32 @printf(i8* nocapture, ...) nounwind -declare arm_apcscc void @diff(i8*, i8*, i32, i32, i32, i32) nounwind +declare void @diff(i8*, i8*, i32, i32, i32, i32) nounwind -define arm_apcscc void @SIM(i8* %A, i8* %B, i32 %M, i32 %N, i32 %K, [256 x i32]* %V, i32 %Q, i32 %R, i32 %nseq) nounwind { +define void @SIM(i8* %A, i8* %B, i32 %M, i32 %N, i32 %K, [256 x i32]* %V, i32 %Q, i32 %R, i32 %nseq) nounwind { entry: br i1 undef, label %bb5, label %bb @@ -44,17 +44,17 @@ bb11: ; preds = %bb9 store i32 0, i32* @no_mat, align 4 store i32 0, i32* @no_mis, align 4 %3 = getelementptr i8* %B, i32 %0 ; <i8*> [#uses=1] - tail call arm_apcscc void @diff(i8* undef, i8* %3, i32 undef, i32 undef, i32 undef, i32 undef) nounwind + tail call void @diff(i8* undef, i8* %3, i32 undef, i32 undef, i32 undef, i32 undef) nounwind %4 = sitofp i32 undef to double ; <double> [#uses=1] %5 = fdiv double %4, 1.000000e+01 ; <double> [#uses=1] - %6 = tail call arm_apcscc i32 (i8*, ...)* @printf(i8* getelementptr ([29 x i8]* @"\01LC12", i32 0, i32 0), double %5) nounwind ; <i32> [#uses=0] + %6 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([29 x i8]* @"\01LC12", i32 0, i32 0), double %5) nounwind ; <i32> [#uses=0] %7 = load i32* @al_len, align 4 ; <i32> [#uses=1] %8 = load i32* @no_mat, align 4 ; <i32> [#uses=1] %9 = load i32* @no_mis, align 4 ; <i32> [#uses=1] %10 = sub i32 %7, %8 ; <i32> [#uses=1] %11 = sub i32 %10, %9 ; <i32> [#uses=1] - %12 = tail call arm_apcscc i32 (i8*, ...)* @printf(i8* getelementptr ([33 x i8]* @"\01LC16", i32 0, i32 0), i32 %11) nounwind ; <i32> [#uses=0] - %13 = tail call arm_apcscc i32 (i8*, ...)* @printf(i8* getelementptr ([47 x i8]* @"\01LC17", i32 0, i32 0), i32 undef, i32 %1, i32 undef, i32 undef) nounwind ; <i32> [#uses=0] + %12 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([33 x i8]* @"\01LC16", i32 0, i32 0), i32 %11) nounwind ; <i32> [#uses=0] + %13 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([47 x i8]* @"\01LC17", i32 0, i32 0), i32 undef, i32 %1, i32 undef, i32 undef) nounwind ; <i32> [#uses=0] br i1 undef, label %bb15, label %bb12 bb12: ; preds = %bb11 diff --git a/test/CodeGen/ARM/2009-06-30-RegScavengerAssert2.ll b/test/CodeGen/ARM/2009-06-30-RegScavengerAssert2.ll index f520be3..f5fb97c 100644 --- a/test/CodeGen/ARM/2009-06-30-RegScavengerAssert2.ll +++ b/test/CodeGen/ARM/2009-06-30-RegScavengerAssert2.ll @@ -6,11 +6,11 @@ @"\01LC15" = external constant [33 x i8], align 1 ; <[33 x i8]*> [#uses=1] @"\01LC17" = external constant [47 x i8], align 1 ; <[47 x i8]*> [#uses=1] -declare arm_apcscc i32 @printf(i8* nocapture, ...) nounwind +declare i32 @printf(i8* nocapture, ...) nounwind -declare arm_apcscc void @diff(i8*, i8*, i32, i32, i32, i32) nounwind +declare void @diff(i8*, i8*, i32, i32, i32, i32) nounwind -define arm_apcscc void @SIM(i8* %A, i8* %B, i32 %M, i32 %N, i32 %K, [256 x i32]* %V, i32 %Q, i32 %R, i32 %nseq) nounwind { +define void @SIM(i8* %A, i8* %B, i32 %M, i32 %N, i32 %K, [256 x i32]* %V, i32 %Q, i32 %R, i32 %nseq) nounwind { entry: br i1 undef, label %bb5, label %bb @@ -41,11 +41,11 @@ bb11: ; preds = %bb9 store i32 0, i32* @no_mat, align 4 store i32 0, i32* @no_mis, align 4 %4 = getelementptr i8* %B, i32 %0 ; <i8*> [#uses=1] - tail call arm_apcscc void @diff(i8* undef, i8* %4, i32 undef, i32 %3, i32 undef, i32 undef) nounwind - %5 = tail call arm_apcscc i32 (i8*, ...)* @printf(i8* getelementptr ([33 x i8]* @"\01LC11", i32 0, i32 0), i32 %tmp13) nounwind ; <i32> [#uses=0] + tail call void @diff(i8* undef, i8* %4, i32 undef, i32 %3, i32 undef, i32 undef) nounwind + %5 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([33 x i8]* @"\01LC11", i32 0, i32 0), i32 %tmp13) nounwind ; <i32> [#uses=0] %6 = load i32* @no_mis, align 4 ; <i32> [#uses=1] - %7 = tail call arm_apcscc i32 (i8*, ...)* @printf(i8* getelementptr ([33 x i8]* @"\01LC15", i32 0, i32 0), i32 %6) nounwind ; <i32> [#uses=0] - %8 = tail call arm_apcscc i32 (i8*, ...)* @printf(i8* getelementptr ([47 x i8]* @"\01LC17", i32 0, i32 0), i32 undef, i32 %1, i32 undef, i32 %2) nounwind ; <i32> [#uses=0] + %7 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([33 x i8]* @"\01LC15", i32 0, i32 0), i32 %6) nounwind ; <i32> [#uses=0] + %8 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([47 x i8]* @"\01LC17", i32 0, i32 0), i32 undef, i32 %1, i32 undef, i32 %2) nounwind ; <i32> [#uses=0] br i1 undef, label %bb15, label %bb12 bb12: ; preds = %bb11 diff --git a/test/CodeGen/ARM/2009-06-30-RegScavengerAssert3.ll b/test/CodeGen/ARM/2009-06-30-RegScavengerAssert3.ll index eee6ff9..d7e4c90 100644 --- a/test/CodeGen/ARM/2009-06-30-RegScavengerAssert3.ll +++ b/test/CodeGen/ARM/2009-06-30-RegScavengerAssert3.ll @@ -2,7 +2,7 @@ @JJ = external global i32* ; <i32**> [#uses=1] -define arm_apcscc void @SIM(i8* %A, i8* %B, i32 %M, i32 %N, i32 %K, [256 x i32]* %V, i32 %Q, i32 %R, i32 %nseq) nounwind { +define void @SIM(i8* %A, i8* %B, i32 %M, i32 %N, i32 %K, [256 x i32]* %V, i32 %Q, i32 %R, i32 %nseq) nounwind { entry: br i1 undef, label %bb5, label %bb diff --git a/test/CodeGen/ARM/2009-06-30-RegScavengerAssert4.ll b/test/CodeGen/ARM/2009-06-30-RegScavengerAssert4.ll index 93c92b1..77c133a 100644 --- a/test/CodeGen/ARM/2009-06-30-RegScavengerAssert4.ll +++ b/test/CodeGen/ARM/2009-06-30-RegScavengerAssert4.ll @@ -6,9 +6,9 @@ @no_mis = external global i32 ; <i32*> [#uses=1] @name1 = external global i8* ; <i8**> [#uses=1] -declare arm_apcscc void @diff(i8*, i8*, i32, i32, i32, i32) nounwind +declare void @diff(i8*, i8*, i32, i32, i32, i32) nounwind -define arm_apcscc void @SIM(i8* %A, i8* %B, i32 %M, i32 %N, i32 %K, [256 x i32]* %V, i32 %Q, i32 %R, i32 %nseq) nounwind { +define void @SIM(i8* %A, i8* %B, i32 %M, i32 %N, i32 %K, [256 x i32]* %V, i32 %Q, i32 %R, i32 %nseq) nounwind { entry: br i1 undef, label %bb5, label %bb @@ -35,7 +35,7 @@ bb11: ; preds = %bb9 store i32 0, i32* @no_mis, align 4 %1 = getelementptr i8* %A, i32 0 ; <i8*> [#uses=1] %2 = getelementptr i8* %B, i32 0 ; <i8*> [#uses=1] - tail call arm_apcscc void @diff(i8* %1, i8* %2, i32 undef, i32 undef, i32 undef, i32 undef) nounwind + tail call void @diff(i8* %1, i8* %2, i32 undef, i32 undef, i32 undef, i32 undef) nounwind br i1 undef, label %bb15, label %bb12 bb12: ; preds = %bb11 diff --git a/test/CodeGen/ARM/2009-06-30-RegScavengerAssert5.ll b/test/CodeGen/ARM/2009-06-30-RegScavengerAssert5.ll index 277283d..16f5d1d 100644 --- a/test/CodeGen/ARM/2009-06-30-RegScavengerAssert5.ll +++ b/test/CodeGen/ARM/2009-06-30-RegScavengerAssert5.ll @@ -2,7 +2,7 @@ @XX = external global i32* ; <i32**> [#uses=1] -define arm_apcscc void @SIM(i8* %A, i8* %B, i32 %M, i32 %N, i32 %K, [256 x i32]* %V, i32 %Q, i32 %R, i32 %nseq) nounwind { +define void @SIM(i8* %A, i8* %B, i32 %M, i32 %N, i32 %K, [256 x i32]* %V, i32 %Q, i32 %R, i32 %nseq) nounwind { entry: br i1 undef, label %bb5, label %bb diff --git a/test/CodeGen/ARM/2009-07-01-CommuteBug.ll b/test/CodeGen/ARM/2009-07-01-CommuteBug.ll index 5c0e5fa..f0d79ce 100644 --- a/test/CodeGen/ARM/2009-07-01-CommuteBug.ll +++ b/test/CodeGen/ARM/2009-07-01-CommuteBug.ll @@ -4,7 +4,7 @@ @II = external global i32* ; <i32**> [#uses=1] @JJ = external global i32* ; <i32**> [#uses=1] -define arm_apcscc void @SIM(i8* %A, i8* %B, i32 %M, i32 %N, i32 %K, [256 x i32]* %V, i32 %Q, i32 %R, i32 %nseq) nounwind { +define void @SIM(i8* %A, i8* %B, i32 %M, i32 %N, i32 %K, [256 x i32]* %V, i32 %Q, i32 %R, i32 %nseq) nounwind { entry: br i1 undef, label %bb5, label %bb diff --git a/test/CodeGen/ARM/2009-07-18-RewriterBug.ll b/test/CodeGen/ARM/2009-07-18-RewriterBug.ll index 2b7ccd8..454fee5 100644 --- a/test/CodeGen/ARM/2009-07-18-RewriterBug.ll +++ b/test/CodeGen/ARM/2009-07-18-RewriterBug.ll @@ -8,7 +8,7 @@ @_2E_str7 = internal constant [21 x i8] c"ERROR: Only 1 point!\00", section "__TEXT,__cstring,cstring_literals", align 1 ; <[21 x i8]*> [#uses=1] @llvm.used = appending global [1 x i8*] [i8* bitcast (void (%struct.EDGE_PAIR*, %struct.VERTEX*, %struct.VERTEX*)* @build_delaunay to i8*)], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0] -define arm_apcscc void @build_delaunay(%struct.EDGE_PAIR* noalias nocapture sret %agg.result, %struct.VERTEX* %tree, %struct.VERTEX* %extra) nounwind { +define void @build_delaunay(%struct.EDGE_PAIR* noalias nocapture sret %agg.result, %struct.VERTEX* %tree, %struct.VERTEX* %extra) nounwind { entry: %delright = alloca %struct.EDGE_PAIR, align 8 ; <%struct.EDGE_PAIR*> [#uses=3] %delleft = alloca %struct.EDGE_PAIR, align 8 ; <%struct.EDGE_PAIR*> [#uses=3] @@ -29,10 +29,10 @@ bb1.i: ; preds = %bb1.i, %bb br i1 %6, label %get_low.exit, label %bb1.i get_low.exit: ; preds = %bb1.i - call arm_apcscc void @build_delaunay(%struct.EDGE_PAIR* noalias sret %delright, %struct.VERTEX* %2, %struct.VERTEX* %extra) nounwind + call void @build_delaunay(%struct.EDGE_PAIR* noalias sret %delright, %struct.VERTEX* %2, %struct.VERTEX* %extra) nounwind %7 = getelementptr %struct.VERTEX* %tree, i32 0, i32 1 ; <%struct.VERTEX**> [#uses=1] %8 = load %struct.VERTEX** %7, align 4 ; <%struct.VERTEX*> [#uses=1] - call arm_apcscc void @build_delaunay(%struct.EDGE_PAIR* noalias sret %delleft, %struct.VERTEX* %8, %struct.VERTEX* %tree) nounwind + call void @build_delaunay(%struct.EDGE_PAIR* noalias sret %delleft, %struct.VERTEX* %8, %struct.VERTEX* %tree) nounwind %9 = getelementptr %struct.EDGE_PAIR* %delleft, i32 0, i32 0 ; <%struct.edge_rec**> [#uses=1] %10 = load %struct.edge_rec** %9, align 8 ; <%struct.edge_rec*> [#uses=2] %11 = getelementptr %struct.EDGE_PAIR* %delleft, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] @@ -141,7 +141,7 @@ bb5.i: ; preds = %bb3.i %85 = inttoptr i32 %84 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] %86 = getelementptr %struct.edge_rec* %ldi_addr.0.i, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] %87 = load %struct.VERTEX** %86, align 4 ; <%struct.VERTEX*> [#uses=1] - %88 = call arm_apcscc %struct.edge_rec* @alloc_edge() nounwind ; <%struct.edge_rec*> [#uses=6] + %88 = call %struct.edge_rec* @alloc_edge() nounwind ; <%struct.edge_rec*> [#uses=6] %89 = getelementptr %struct.edge_rec* %88, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=4] store %struct.edge_rec* %88, %struct.edge_rec** %89, align 4 %90 = getelementptr %struct.edge_rec* %88, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=2] @@ -780,7 +780,7 @@ bb24.i: ; preds = %bb23.i, %bb21.i %592 = and i32 %589, -64 ; <i32> [#uses=1] %593 = or i32 %591, %592 ; <i32> [#uses=1] %594 = inttoptr i32 %593 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] - %595 = call arm_apcscc %struct.edge_rec* @alloc_edge() nounwind ; <%struct.edge_rec*> [#uses=5] + %595 = call %struct.edge_rec* @alloc_edge() nounwind ; <%struct.edge_rec*> [#uses=5] %596 = getelementptr %struct.edge_rec* %595, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=4] store %struct.edge_rec* %595, %struct.edge_rec** %596, align 4 %597 = getelementptr %struct.edge_rec* %595, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] @@ -882,7 +882,7 @@ bb25.i: ; preds = %bb23.i, %bb22.i %677 = and i32 %674, -64 ; <i32> [#uses=1] %678 = or i32 %676, %677 ; <i32> [#uses=1] %679 = inttoptr i32 %678 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] - %680 = call arm_apcscc %struct.edge_rec* @alloc_edge() nounwind ; <%struct.edge_rec*> [#uses=4] + %680 = call %struct.edge_rec* @alloc_edge() nounwind ; <%struct.edge_rec*> [#uses=4] %681 = getelementptr %struct.edge_rec* %680, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=5] store %struct.edge_rec* %680, %struct.edge_rec** %681, align 4 %682 = getelementptr %struct.edge_rec* %680, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] @@ -1005,15 +1005,15 @@ bb7: ; preds = %bb %762 = getelementptr %struct.VERTEX* %tree, i32 0, i32 1 ; <%struct.VERTEX**> [#uses=1] %763 = load %struct.VERTEX** %762, align 4 ; <%struct.VERTEX*> [#uses=4] %764 = icmp eq %struct.VERTEX* %763, null ; <i1> [#uses=1] - %765 = call arm_apcscc %struct.edge_rec* @alloc_edge() nounwind ; <%struct.edge_rec*> [#uses=5] + %765 = call %struct.edge_rec* @alloc_edge() nounwind ; <%struct.edge_rec*> [#uses=5] %766 = getelementptr %struct.edge_rec* %765, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=4] store %struct.edge_rec* %765, %struct.edge_rec** %766, align 4 %767 = getelementptr %struct.edge_rec* %765, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=3] br i1 %764, label %bb10, label %bb11 bb8: ; preds = %entry - %768 = call arm_apcscc i32 @puts(i8* getelementptr ([21 x i8]* @_2E_str7, i32 0, i32 0)) nounwind ; <i32> [#uses=0] - call arm_apcscc void @exit(i32 -1) noreturn nounwind + %768 = call i32 @puts(i8* getelementptr ([21 x i8]* @_2E_str7, i32 0, i32 0)) nounwind ; <i32> [#uses=0] + call void @exit(i32 -1) noreturn nounwind unreachable bb10: ; preds = %bb7 @@ -1053,7 +1053,7 @@ bb11: ; preds = %bb7 store %struct.VERTEX* %tree, %struct.VERTEX** %790, align 4 %791 = getelementptr %struct.edge_rec* %785, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] store %struct.edge_rec* %783, %struct.edge_rec** %791, align 4 - %792 = call arm_apcscc %struct.edge_rec* @alloc_edge() nounwind ; <%struct.edge_rec*> [#uses=4] + %792 = call %struct.edge_rec* @alloc_edge() nounwind ; <%struct.edge_rec*> [#uses=4] %793 = getelementptr %struct.edge_rec* %792, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=4] store %struct.edge_rec* %792, %struct.edge_rec** %793, align 4 %794 = getelementptr %struct.edge_rec* %792, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] @@ -1117,7 +1117,7 @@ bb11: ; preds = %bb7 %843 = or i32 %841, %842 ; <i32> [#uses=1] %844 = inttoptr i32 %843 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] %845 = load %struct.VERTEX** %767, align 4 ; <%struct.VERTEX*> [#uses=1] - %846 = call arm_apcscc %struct.edge_rec* @alloc_edge() nounwind ; <%struct.edge_rec*> [#uses=4] + %846 = call %struct.edge_rec* @alloc_edge() nounwind ; <%struct.edge_rec*> [#uses=4] %847 = getelementptr %struct.edge_rec* %846, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=7] store %struct.edge_rec* %846, %struct.edge_rec** %847, align 4 %848 = getelementptr %struct.edge_rec* %846, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] @@ -1316,8 +1316,8 @@ bb15: ; preds = %bb14, %bb13, %bb11, %bb10, %bb6 ret void } -declare arm_apcscc i32 @puts(i8* nocapture) nounwind +declare i32 @puts(i8* nocapture) nounwind -declare arm_apcscc void @exit(i32) noreturn nounwind +declare void @exit(i32) noreturn nounwind -declare arm_apcscc %struct.edge_rec* @alloc_edge() nounwind +declare %struct.edge_rec* @alloc_edge() nounwind diff --git a/test/CodeGen/ARM/2009-07-22-ScavengerAssert.ll b/test/CodeGen/ARM/2009-07-22-ScavengerAssert.ll index b4b989b..d477ba98 100644 --- a/test/CodeGen/ARM/2009-07-22-ScavengerAssert.ll +++ b/test/CodeGen/ARM/2009-07-22-ScavengerAssert.ll @@ -6,9 +6,9 @@ %struct.cli_bm_patt = type { i8*, i8*, i16, i16, i8*, i8*, i8, %struct.cli_bm_patt*, i16 } %struct.cli_matcher = type { i16, i8, i8*, %struct.cli_bm_patt**, i32*, i32, i8, i8, %struct.cli_ac_node*, %struct.cli_ac_node**, %struct.cli_ac_patt**, i32, i32, i32 } -declare arm_apcscc i32 @strlen(i8* nocapture) nounwind readonly +declare i32 @strlen(i8* nocapture) nounwind readonly -define arm_apcscc i32 @cli_ac_addsig(%struct.cli_matcher* nocapture %root, i8* %virname, i8* %hexsig, i32 %sigid, i16 zeroext %parts, i16 zeroext %partno, i16 zeroext %type, i32 %mindist, i32 %maxdist, i8* %offset, i8 zeroext %target) nounwind { +define i32 @cli_ac_addsig(%struct.cli_matcher* nocapture %root, i8* %virname, i8* %hexsig, i32 %sigid, i16 zeroext %parts, i16 zeroext %partno, i16 zeroext %type, i32 %mindist, i32 %maxdist, i8* %offset, i8 zeroext %target) nounwind { entry: br i1 undef, label %bb126, label %bb1 @@ -86,7 +86,7 @@ bb52: ; preds = %cli_calloc.exit %0 = load i16* undef, align 4 ; <i16> [#uses=1] %1 = icmp eq i16 %0, 0 ; <i1> [#uses=1] %iftmp.20.0 = select i1 %1, i8* %hexsig, i8* null ; <i8*> [#uses=1] - %2 = tail call arm_apcscc i32 @strlen(i8* %iftmp.20.0) nounwind readonly ; <i32> [#uses=0] + %2 = tail call i32 @strlen(i8* %iftmp.20.0) nounwind readonly ; <i32> [#uses=0] unreachable bb126: ; preds = %entry diff --git a/test/CodeGen/ARM/2009-07-22-SchedulerAssert.ll b/test/CodeGen/ARM/2009-07-22-SchedulerAssert.ll index 24f4990..6761687 100644 --- a/test/CodeGen/ARM/2009-07-22-SchedulerAssert.ll +++ b/test/CodeGen/ARM/2009-07-22-SchedulerAssert.ll @@ -6,7 +6,7 @@ %struct.cli_bm_patt = type { i8*, i8*, i16, i16, i8*, i8*, i8, %struct.cli_bm_patt*, i16 } %struct.cli_matcher = type { i16, i8, i8*, %struct.cli_bm_patt**, i32*, i32, i8, i8, %struct.cli_ac_node*, %struct.cli_ac_node**, %struct.cli_ac_patt**, i32, i32, i32 } -define arm_apcscc i32 @cli_ac_addsig(%struct.cli_matcher* nocapture %root, i8* %virname, i8* %hexsig, i32 %sigid, i16 zeroext %parts, i16 zeroext %partno, i16 zeroext %type, i32 %mindist, i32 %maxdist, i8* %offset, i8 zeroext %target) nounwind { +define i32 @cli_ac_addsig(%struct.cli_matcher* nocapture %root, i8* %virname, i8* %hexsig, i32 %sigid, i16 zeroext %parts, i16 zeroext %partno, i16 zeroext %type, i32 %mindist, i32 %maxdist, i8* %offset, i8 zeroext %target) nounwind { entry: br i1 undef, label %bb126, label %bb1 diff --git a/test/CodeGen/ARM/2009-07-29-VFP3Registers.ll b/test/CodeGen/ARM/2009-07-29-VFP3Registers.ll index e1d19d1..5003fbd 100644 --- a/test/CodeGen/ARM/2009-07-29-VFP3Registers.ll +++ b/test/CodeGen/ARM/2009-07-29-VFP3Registers.ll @@ -4,7 +4,7 @@ declare double @llvm.exp.f64(double) nounwind readonly -define arm_apcscc void @findratio(double* nocapture %res1, double* nocapture %res2) nounwind { +define void @findratio(double* nocapture %res1, double* nocapture %res2) nounwind { entry: br label %bb diff --git a/test/CodeGen/ARM/2009-08-02-RegScavengerAssert-Neon.ll b/test/CodeGen/ARM/2009-08-02-RegScavengerAssert-Neon.ll index 2d4e58d..a656c49 100644 --- a/test/CodeGen/ARM/2009-08-02-RegScavengerAssert-Neon.ll +++ b/test/CodeGen/ARM/2009-08-02-RegScavengerAssert-Neon.ll @@ -4,7 +4,7 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64" target triple = "armv7-apple-darwin9" -define arm_apcscc <4 x i32> @scale(<4 x i32> %v, i32 %f) nounwind { +define <4 x i32> @scale(<4 x i32> %v, i32 %f) nounwind { entry: %v_addr = alloca <4 x i32> ; <<4 x i32>*> [#uses=2] %f_addr = alloca i32 ; <i32*> [#uses=2] diff --git a/test/CodeGen/ARM/2009-08-04-RegScavengerAssert-2.ll b/test/CodeGen/ARM/2009-08-04-RegScavengerAssert-2.ll index 65ffed2..3097522 100644 --- a/test/CodeGen/ARM/2009-08-04-RegScavengerAssert-2.ll +++ b/test/CodeGen/ARM/2009-08-04-RegScavengerAssert-2.ll @@ -1,10 +1,10 @@ -; RUN: llc < %s -mtriple=armv6-elf +; RUN: llc < %s -mtriple=arm-linux-gnueabi ; PR4528 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64" target triple = "armv6-elf" -define arm_aapcscc i32 @file_read_actor(i32* nocapture %desc, i32* %page, i32 %offset, i32 %size) nounwind optsize { +define i32 @file_read_actor(i32* nocapture %desc, i32* %page, i32 %offset, i32 %size) nounwind optsize { entry: br i1 undef, label %fault_in_pages_writeable.exit, label %bb5.i @@ -26,8 +26,8 @@ bb2: ; preds = %fault_in_pages_writeable.exit unreachable bb3: ; preds = %fault_in_pages_writeable.exit - %1 = tail call arm_aapcscc i32 @__copy_to_user(i8* undef, i8* undef, i32 undef) nounwind ; <i32> [#uses=0] + %1 = tail call i32 @__copy_to_user(i8* undef, i8* undef, i32 undef) nounwind ; <i32> [#uses=0] unreachable } -declare arm_aapcscc i32 @__copy_to_user(i8*, i8*, i32) +declare i32 @__copy_to_user(i8*, i8*, i32) diff --git a/test/CodeGen/ARM/2009-08-04-RegScavengerAssert.ll b/test/CodeGen/ARM/2009-08-04-RegScavengerAssert.ll index 9e5372a..d666f12 100644 --- a/test/CodeGen/ARM/2009-08-04-RegScavengerAssert.ll +++ b/test/CodeGen/ARM/2009-08-04-RegScavengerAssert.ll @@ -1,7 +1,7 @@ -; RUN: llc < %s -mtriple=armv6-elf +; RUN: llc < %s -mtriple=arm-linux-gnueabi ; PR4528 -define arm_aapcscc i32 @file_read_actor(i32 %desc, i32 %page, i32 %offset, i32 %size) nounwind optsize { +define i32 @file_read_actor(i32 %desc, i32 %page, i32 %offset, i32 %size) nounwind optsize { entry: br i1 undef, label %fault_in_pages_writeable.exit, label %bb5.i @@ -18,8 +18,8 @@ bb2: ; preds = %fault_in_pages_writeable.exit unreachable bb3: ; preds = %fault_in_pages_writeable.exit - %2 = tail call arm_aapcscc i32 @__copy_to_user(i8* undef, i8* undef, i32 undef) nounwind ; <i32> [#uses=0] + %2 = tail call i32 @__copy_to_user(i8* undef, i8* undef, i32 undef) nounwind ; <i32> [#uses=0] unreachable } -declare arm_aapcscc i32 @__copy_to_user(i8*, i8*, i32) +declare i32 @__copy_to_user(i8*, i8*, i32) diff --git a/test/CodeGen/ARM/2009-08-15-RegScavenger-EarlyClobber.ll b/test/CodeGen/ARM/2009-08-15-RegScavenger-EarlyClobber.ll index 18d68f7..4b41015 100644 --- a/test/CodeGen/ARM/2009-08-15-RegScavenger-EarlyClobber.ll +++ b/test/CodeGen/ARM/2009-08-15-RegScavenger-EarlyClobber.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm +; RUN: llc < %s -mtriple=arm-linux-gnueabi ; PR4528 ; Inline asm is allowed to contain operands "=&r", "0". @@ -6,7 +6,7 @@ %struct.device_dma_parameters = type { i32, i32 } %struct.iovec = type { i8*, i32 } -define arm_aapcscc i32 @generic_segment_checks(%struct.iovec* nocapture %iov, i32* nocapture %nr_segs, i32* nocapture %count, i32 %access_flags) nounwind optsize { +define i32 @generic_segment_checks(%struct.iovec* nocapture %iov, i32* nocapture %nr_segs, i32* nocapture %count, i32 %access_flags) nounwind optsize { entry: br label %bb8 diff --git a/test/CodeGen/ARM/2009-08-15-RegScavengerAssert.ll b/test/CodeGen/ARM/2009-08-15-RegScavengerAssert.ll index a46482c..2993647 100644 --- a/test/CodeGen/ARM/2009-08-15-RegScavengerAssert.ll +++ b/test/CodeGen/ARM/2009-08-15-RegScavengerAssert.ll @@ -1,10 +1,10 @@ -; RUN: llc < %s -march=arm +; RUN: llc < %s -mtriple=arm-linux-gnueabi ; PR4716 -define arm_aapcscc void @_start() nounwind naked { +define void @_start() nounwind naked { entry: - tail call arm_aapcscc void @exit(i32 undef) noreturn nounwind + tail call void @exit(i32 undef) noreturn nounwind unreachable } -declare arm_aapcscc void @exit(i32) noreturn nounwind +declare void @exit(i32) noreturn nounwind diff --git a/test/CodeGen/ARM/2009-08-21-PostRAKill.ll b/test/CodeGen/ARM/2009-08-21-PostRAKill.ll index 84915c4..c598fe6 100644 --- a/test/CodeGen/ARM/2009-08-21-PostRAKill.ll +++ b/test/CodeGen/ARM/2009-08-21-PostRAKill.ll @@ -7,7 +7,7 @@ target triple = "armv7-apple-darwin9" %struct.tree = type { i32, double, double, %struct.tree*, %struct.tree*, %struct.tree*, %struct.tree* } @g = common global %struct.tree* null -define arm_apcscc %struct.tree* @tsp(%struct.tree* %t, i32 %nproc) nounwind { +define %struct.tree* @tsp(%struct.tree* %t, i32 %nproc) nounwind { entry: %t.idx51.val.i = load double* null ; <double> [#uses=1] br i1 undef, label %bb4.i, label %bb.i diff --git a/test/CodeGen/ARM/2009-08-21-PostRAKill2.ll b/test/CodeGen/ARM/2009-08-21-PostRAKill2.ll index a21ffc3..cc92c26 100644 --- a/test/CodeGen/ARM/2009-08-21-PostRAKill2.ll +++ b/test/CodeGen/ARM/2009-08-21-PostRAKill2.ll @@ -9,7 +9,7 @@ target triple = "armv7-apple-darwin9" %struct.icstruct = type { [3 x i32], i16 } %struct.node = type { i16, double, [3 x double], i32, i32 } -declare arm_apcscc double @floor(double) nounwind readnone +declare double @floor(double) nounwind readnone define void @intcoord(%struct.icstruct* noalias nocapture sret %agg.result, i1 %a, double %b) { entry: @@ -28,7 +28,7 @@ bb7: ; preds = %bb3 br i1 %a, label %bb11, label %bb9 bb9: ; preds = %bb7 - %0 = tail call arm_apcscc double @floor(double %b) nounwind readnone ; <double> [#uses=0] + %0 = tail call double @floor(double %b) nounwind readnone ; <double> [#uses=0] br label %bb11 bb11: ; preds = %bb9, %bb7 diff --git a/test/CodeGen/ARM/2009-08-21-PostRAKill3.ll b/test/CodeGen/ARM/2009-08-21-PostRAKill3.ll index e3d8ea6..90a4a42 100644 --- a/test/CodeGen/ARM/2009-08-21-PostRAKill3.ll +++ b/test/CodeGen/ARM/2009-08-21-PostRAKill3.ll @@ -9,7 +9,7 @@ target triple = "armv7-apple-darwin9" %struct.Patient = type { i32, i32, i32, %struct.Village* } %struct.Village = type { [4 x %struct.Village*], %struct.Village*, %struct.List, %struct.Hosp, i32, i32 } -define arm_apcscc %struct.Village* @alloc_tree(i32 %level, i32 %label, %struct.Village* %back, i1 %p) nounwind { +define %struct.Village* @alloc_tree(i32 %level, i32 %label, %struct.Village* %back, i1 %p) nounwind { entry: br i1 %p, label %bb8, label %bb1 diff --git a/test/CodeGen/ARM/2009-08-21-PostRAKill4.ll b/test/CodeGen/ARM/2009-08-21-PostRAKill4.ll index 9123377..5cfc68d 100644 --- a/test/CodeGen/ARM/2009-08-21-PostRAKill4.ll +++ b/test/CodeGen/ARM/2009-08-21-PostRAKill4.ll @@ -8,19 +8,19 @@ target triple = "armv7-apple-darwin9" @.str1 = external constant [31 x i8], align 1 ; <[31 x i8]*> [#uses=1] @.str2 = external constant [4 x i8], align 1 ; <[4 x i8]*> [#uses=1] -declare arm_apcscc i32 @getUnknown(i32, ...) nounwind +declare i32 @getUnknown(i32, ...) nounwind declare void @llvm.va_start(i8*) nounwind declare void @llvm.va_end(i8*) nounwind -declare arm_apcscc i32 @printf(i8* nocapture, ...) nounwind +declare i32 @printf(i8* nocapture, ...) nounwind -define arm_apcscc i32 @main() nounwind { +define i32 @main() nounwind { entry: - %0 = tail call arm_apcscc i32 (i8*, ...)* @printf(i8* getelementptr ([31 x i8]* @.str1, i32 0, i32 0), i32 1, i32 1, i32 1, i32 1, i32 1, i32 1) nounwind ; <i32> [#uses=0] - %1 = tail call arm_apcscc i32 (i8*, ...)* @printf(i8* getelementptr ([31 x i8]* @.str1, i32 0, i32 0), i32 -128, i32 116, i32 116, i32 -3852, i32 -31232, i32 -1708916736) nounwind ; <i32> [#uses=0] - %2 = tail call arm_apcscc i32 (i32, ...)* @getUnknown(i32 undef, i32 116, i32 116, i32 -3852, i32 -31232, i32 30556, i32 -1708916736) nounwind ; <i32> [#uses=1] - %3 = tail call arm_apcscc i32 (i8*, ...)* @printf(i8* getelementptr ([4 x i8]* @.str2, i32 0, i32 0), i32 %2) nounwind ; <i32> [#uses=0] + %0 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([31 x i8]* @.str1, i32 0, i32 0), i32 1, i32 1, i32 1, i32 1, i32 1, i32 1) nounwind ; <i32> [#uses=0] + %1 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([31 x i8]* @.str1, i32 0, i32 0), i32 -128, i32 116, i32 116, i32 -3852, i32 -31232, i32 -1708916736) nounwind ; <i32> [#uses=0] + %2 = tail call i32 (i32, ...)* @getUnknown(i32 undef, i32 116, i32 116, i32 -3852, i32 -31232, i32 30556, i32 -1708916736) nounwind ; <i32> [#uses=1] + %3 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([4 x i8]* @.str2, i32 0, i32 0), i32 %2) nounwind ; <i32> [#uses=0] ret i32 0 } diff --git a/test/CodeGen/ARM/2009-08-23-linkerprivate.ll b/test/CodeGen/ARM/2009-08-23-linkerprivate.ll index 0fad533..392c70a 100644 --- a/test/CodeGen/ARM/2009-08-23-linkerprivate.ll +++ b/test/CodeGen/ARM/2009-08-23-linkerprivate.ll @@ -2,7 +2,7 @@ ; ModuleID = '/Volumes/MacOS9/tests/WebKit/JavaScriptCore/profiler/ProfilerServer.mm' -@"\01l_objc_msgSend_fixup_alloc" = linker_private hidden global i32 0, section "__DATA, __objc_msgrefs, coalesced", align 16 ; <i32*> [#uses=0] +@"\01l_objc_msgSend_fixup_alloc" = linker_private_weak hidden global i32 0, section "__DATA, __objc_msgrefs, coalesced", align 16 ; CHECK: .globl l_objc_msgSend_fixup_alloc ; CHECK: .weak_definition l_objc_msgSend_fixup_alloc diff --git a/test/CodeGen/ARM/2009-08-26-ScalarToVector.ll b/test/CodeGen/ARM/2009-08-26-ScalarToVector.ll index c6ef256..5407013 100644 --- a/test/CodeGen/ARM/2009-08-26-ScalarToVector.ll +++ b/test/CodeGen/ARM/2009-08-26-ScalarToVector.ll @@ -10,7 +10,7 @@ target triple = "thumbv7-elf" declare <2 x i32> @llvm.arm.neon.vpadd.v2i32(<2 x i32>, <2 x i32>) nounwind readnone -define arm_apcscc void @_ZN6squish10ClusterFit9Compress3EPv(%quuz* %this, i8* %block) { +define void @_ZN6squish10ClusterFit9Compress3EPv(%quuz* %this, i8* %block) { entry: %0 = lshr <4 x i32> zeroinitializer, <i32 31, i32 31, i32 31, i32 31> ; <<4 x i32>> [#uses=1] %1 = shufflevector <4 x i32> %0, <4 x i32> undef, <2 x i32> <i32 2, i32 3> ; <<2 x i32>> [#uses=1] diff --git a/test/CodeGen/ARM/2009-08-27-ScalarToVector.ll b/test/CodeGen/ARM/2009-08-27-ScalarToVector.ll index bc5bfe9..cac8569 100644 --- a/test/CodeGen/ARM/2009-08-27-ScalarToVector.ll +++ b/test/CodeGen/ARM/2009-08-27-ScalarToVector.ll @@ -8,7 +8,7 @@ target triple = "thumbv7-elf" %quux = type { i32 (...)**, %baz*, i32 } %quuz = type { %quux, i32, %bar, [128 x i8], [16 x %foo], %foo, %foo, %foo } -define arm_apcscc void @aaaa(%quuz* %this, i8* %block) { +define void @aaaa(%quuz* %this, i8* %block) { entry: br i1 undef, label %bb.nph269, label %bb201 diff --git a/test/CodeGen/ARM/2009-08-29-ExtractEltf32.ll b/test/CodeGen/ARM/2009-08-29-ExtractEltf32.ll index d5178b4..5bd30ea 100644 --- a/test/CodeGen/ARM/2009-08-29-ExtractEltf32.ll +++ b/test/CodeGen/ARM/2009-08-29-ExtractEltf32.ll @@ -2,7 +2,7 @@ target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32" target triple = "thumbv7-elf" -define arm_apcscc void @foo() nounwind { +define void @foo() nounwind { entry: %0 = tail call <2 x float> @llvm.arm.neon.vpadd.v2f32(<2 x float> undef, <2 x float> undef) nounwind ; <<2 x float>> [#uses=1] %tmp28 = extractelement <2 x float> %0, i32 0 ; <float> [#uses=1] diff --git a/test/CodeGen/ARM/2009-08-29-TooLongSplat.ll b/test/CodeGen/ARM/2009-08-29-TooLongSplat.ll index 266fce6..4655962 100644 --- a/test/CodeGen/ARM/2009-08-29-TooLongSplat.ll +++ b/test/CodeGen/ARM/2009-08-29-TooLongSplat.ll @@ -2,7 +2,7 @@ target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32" target triple = "thumbv7-elf" -define arm_apcscc void @aaa() nounwind { +define void @aaa() nounwind { entry: %0 = fmul <4 x float> undef, <float 1.000000e+00, float 1.000000e+01, float 1.000000e+02, float 0x3EB0C6F7A0000000> ; <<4 x float>> [#uses=1] %tmp31 = extractelement <4 x float> %0, i32 0 ; <float> [#uses=1] diff --git a/test/CodeGen/ARM/2009-08-31-LSDA-Name.ll b/test/CodeGen/ARM/2009-08-31-LSDA-Name.ll index c0ad65f..397eba4 100644 --- a/test/CodeGen/ARM/2009-08-31-LSDA-Name.ll +++ b/test/CodeGen/ARM/2009-08-31-LSDA-Name.ll @@ -2,7 +2,7 @@ %struct.A = type { i32* } -define arm_apcscc void @"\01-[MyFunction Name:]"() { +define void @"\01-[MyFunction Name:]"() { entry: %save_filt.1 = alloca i32 ; <i32*> [#uses=2] %save_eptr.0 = alloca i8* ; <i8**> [#uses=2] @@ -10,12 +10,12 @@ entry: %eh_exception = alloca i8* ; <i8**> [#uses=5] %eh_selector = alloca i32 ; <i32*> [#uses=3] %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] - call arm_apcscc void @_ZN1AC1Ev(%struct.A* %a) - invoke arm_apcscc void @_Z3barv() + call void @_ZN1AC1Ev(%struct.A* %a) + invoke void @_Z3barv() to label %invcont unwind label %lpad invcont: ; preds = %entry - call arm_apcscc void @_ZN1AD1Ev(%struct.A* %a) nounwind + call void @_ZN1AD1Ev(%struct.A* %a) nounwind br label %return bb: ; preds = %ppad @@ -23,7 +23,7 @@ bb: ; preds = %ppad store i32 %eh_select, i32* %save_filt.1, align 4 %eh_value = load i8** %eh_exception ; <i8*> [#uses=1] store i8* %eh_value, i8** %save_eptr.0, align 4 - call arm_apcscc void @_ZN1AD1Ev(%struct.A* %a) nounwind + call void @_ZN1AD1Ev(%struct.A* %a) nounwind %0 = load i8** %save_eptr.0, align 4 ; <i8*> [#uses=1] store i8* %0, i8** %eh_exception, align 4 %1 = load i32* %save_filt.1, align 4 ; <i32> [#uses=1] @@ -46,16 +46,16 @@ ppad: ; preds = %lpad Unwind: ; preds = %bb %eh_ptr3 = load i8** %eh_exception ; <i8*> [#uses=1] - call arm_apcscc void @_Unwind_SjLj_Resume(i8* %eh_ptr3) + call void @_Unwind_SjLj_Resume(i8* %eh_ptr3) unreachable } -define linkonce_odr arm_apcscc void @_ZN1AC1Ev(%struct.A* %this) { +define linkonce_odr void @_ZN1AC1Ev(%struct.A* %this) { entry: %this_addr = alloca %struct.A* ; <%struct.A**> [#uses=2] %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] store %struct.A* %this, %struct.A** %this_addr - %0 = call arm_apcscc i8* @_Znwm(i32 4) ; <i8*> [#uses=1] + %0 = call i8* @_Znwm(i32 4) ; <i8*> [#uses=1] %1 = bitcast i8* %0 to i32* ; <i32*> [#uses=1] %2 = load %struct.A** %this_addr, align 4 ; <%struct.A*> [#uses=1] %3 = getelementptr inbounds %struct.A* %2, i32 0, i32 0 ; <i32**> [#uses=1] @@ -66,9 +66,9 @@ return: ; preds = %entry ret void } -declare arm_apcscc i8* @_Znwm(i32) +declare i8* @_Znwm(i32) -define linkonce_odr arm_apcscc void @_ZN1AD1Ev(%struct.A* %this) nounwind { +define linkonce_odr void @_ZN1AD1Ev(%struct.A* %this) nounwind { entry: %this_addr = alloca %struct.A* ; <%struct.A**> [#uses=2] %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] @@ -77,7 +77,7 @@ entry: %1 = getelementptr inbounds %struct.A* %0, i32 0, i32 0 ; <i32**> [#uses=1] %2 = load i32** %1, align 4 ; <i32*> [#uses=1] %3 = bitcast i32* %2 to i8* ; <i8*> [#uses=1] - call arm_apcscc void @_ZdlPv(i8* %3) nounwind + call void @_ZdlPv(i8* %3) nounwind br label %bb bb: ; preds = %entry @@ -88,9 +88,9 @@ return: ; preds = %bb } ;CHECK: L_LSDA_0: -declare arm_apcscc void @_ZdlPv(i8*) nounwind +declare void @_ZdlPv(i8*) nounwind -declare arm_apcscc void @_Z3barv() +declare void @_Z3barv() declare i8* @llvm.eh.exception() nounwind @@ -98,6 +98,6 @@ declare i32 @llvm.eh.selector.i32(i8*, i8*, ...) nounwind declare i32 @llvm.eh.typeid.for.i32(i8*) nounwind -declare arm_apcscc i32 @__gxx_personality_sj0(...) +declare i32 @__gxx_personality_sj0(...) -declare arm_apcscc void @_Unwind_SjLj_Resume(i8*) +declare void @_Unwind_SjLj_Resume(i8*) diff --git a/test/CodeGen/ARM/2009-09-01-PostRAProlog.ll b/test/CodeGen/ARM/2009-09-01-PostRAProlog.ll index bf91fe0..06a152d 100644 --- a/test/CodeGen/ARM/2009-09-01-PostRAProlog.ll +++ b/test/CodeGen/ARM/2009-09-01-PostRAProlog.ll @@ -30,11 +30,11 @@ target triple = "thumbv7-apple-darwin9" @.str218 = private constant [6 x i8] c"%7d%c\00", align 1 ; <[6 x i8]*> [#uses=1] @.str319 = private constant [30 x i8] c"Failed to allocate %u bytes.\0A\00", align 1 ; <[30 x i8]*> [#uses=1] -declare arm_apcscc i32 @puts(i8* nocapture) nounwind +declare i32 @puts(i8* nocapture) nounwind -declare arm_apcscc i32 @getchar() nounwind +declare i32 @getchar() nounwind -define internal arm_apcscc i32 @transpose() nounwind readonly { +define internal i32 @transpose() nounwind readonly { ; CHECK: push entry: %0 = load i32* getelementptr inbounds ([128 x i32]* @columns, i32 0, i32 1), align 4 ; <i32> [#uses=1] @@ -101,6 +101,6 @@ bb7: ; preds = %bb5 ret i32 -128 } -declare arm_apcscc noalias i8* @calloc(i32, i32) nounwind +declare noalias i8* @calloc(i32, i32) nounwind declare void @llvm.memset.i64(i8* nocapture, i8, i64, i32) nounwind diff --git a/test/CodeGen/ARM/2009-09-09-AllOnes.ll b/test/CodeGen/ARM/2009-09-09-AllOnes.ll index f654a16..8522a77 100644 --- a/test/CodeGen/ARM/2009-09-09-AllOnes.ll +++ b/test/CodeGen/ARM/2009-09-09-AllOnes.ll @@ -2,7 +2,7 @@ target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32" target triple = "thumbv7-elf" -define arm_apcscc void @foo() { +define void @foo() { entry: %0 = insertelement <4 x i32> undef, i32 -1, i32 3 store <4 x i32> %0, <4 x i32>* undef, align 16 diff --git a/test/CodeGen/ARM/2009-09-24-spill-align.ll b/test/CodeGen/ARM/2009-09-24-spill-align.ll index 5476d5f..8bfd026 100644 --- a/test/CodeGen/ARM/2009-09-24-spill-align.ll +++ b/test/CodeGen/ARM/2009-09-24-spill-align.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s ; pr4926 -define arm_apcscc void @test_vget_lanep16() nounwind { +define void @test_vget_lanep16() nounwind { entry: %arg0_poly16x4_t = alloca <4 x i16> ; <<4 x i16>*> [#uses=1] %out_poly16_t = alloca i16 ; <i16*> [#uses=1] diff --git a/test/CodeGen/ARM/2009-09-28-LdStOptiBug.ll b/test/CodeGen/ARM/2009-09-28-LdStOptiBug.ll index 53bd668..4aa879d 100644 --- a/test/CodeGen/ARM/2009-09-28-LdStOptiBug.ll +++ b/test/CodeGen/ARM/2009-09-28-LdStOptiBug.ll @@ -3,7 +3,7 @@ %0 = type { double, double } -define arm_aapcscc void @foo(%0* noalias nocapture sret %agg.result, double %x.0, double %y.0) nounwind { +define void @foo(%0* noalias nocapture sret %agg.result, double %x.0, double %y.0) nounwind { ; CHECK: foo: ; CHECK: bl __adddf3 ; CHECK-NOT: strd diff --git a/test/CodeGen/ARM/2009-10-27-double-align.ll b/test/CodeGen/ARM/2009-10-27-double-align.ll index f17d059..c31b116 100644 --- a/test/CodeGen/ARM/2009-10-27-double-align.ll +++ b/test/CodeGen/ARM/2009-10-27-double-align.ll @@ -2,13 +2,13 @@ @.str = private constant [1 x i8] zeroinitializer, align 1 -define arm_aapcscc void @g() { +define void @g() { entry: ;CHECK: [sp, #8] ;CHECK: [sp, #12] ;CHECK: [sp] - tail call arm_aapcscc void (i8*, ...)* @f(i8* getelementptr ([1 x i8]* @.str, i32 0, i32 0), i32 1, double 2.000000e+00, i32 3, double 4.000000e+00) + tail call void (i8*, ...)* @f(i8* getelementptr ([1 x i8]* @.str, i32 0, i32 0), i32 1, double 2.000000e+00, i32 3, double 4.000000e+00) ret void } -declare arm_aapcscc void @f(i8*, ...) +declare void @f(i8*, ...) diff --git a/test/CodeGen/ARM/2009-11-01-NeonMoves.ll b/test/CodeGen/ARM/2009-11-01-NeonMoves.ll index 62f3786..34f7519 100644 --- a/test/CodeGen/ARM/2009-11-01-NeonMoves.ll +++ b/test/CodeGen/ARM/2009-11-01-NeonMoves.ll @@ -11,11 +11,11 @@ entry: %0 = getelementptr inbounds %foo* %quat_addr, i32 0, i32 0 ; <<4 x float>*> [#uses=1] store <4 x float> %quat.0, <4 x float>* %0 %1 = call arm_aapcs_vfpcc <4 x float> @quux(%foo* %quat_addr) nounwind ; <<4 x float>> [#uses=3] -;CHECK: vmov.f32 -;CHECK: vmov.f32 %2 = fmul <4 x float> %1, %1 ; <<4 x float>> [#uses=2] %3 = shufflevector <4 x float> %2, <4 x float> undef, <2 x i32> <i32 0, i32 1> ; <<2 x float>> [#uses=1] %4 = shufflevector <4 x float> %2, <4 x float> undef, <2 x i32> <i32 2, i32 3> ; <<2 x float>> [#uses=1] +;CHECK-NOT: vmov +;CHECK: vpadd %5 = call <2 x float> @llvm.arm.neon.vpadd.v2f32(<2 x float> %3, <2 x float> %4) nounwind ; <<2 x float>> [#uses=2] %6 = call <2 x float> @llvm.arm.neon.vpadd.v2f32(<2 x float> %5, <2 x float> %5) nounwind ; <<2 x float>> [#uses=2] %7 = shufflevector <2 x float> %6, <2 x float> %6, <4 x i32> <i32 0, i32 1, i32 2, i32 3> ; <<4 x float>> [#uses=2] diff --git a/test/CodeGen/ARM/2009-12-02-vtrn-undef.ll b/test/CodeGen/ARM/2009-12-02-vtrn-undef.ll index a737591..198faeb 100644 --- a/test/CodeGen/ARM/2009-12-02-vtrn-undef.ll +++ b/test/CodeGen/ARM/2009-12-02-vtrn-undef.ll @@ -6,7 +6,7 @@ target triple = "armv7-apple-darwin10" %struct.int16x8_t = type { <8 x i16> } %struct.int16x8x2_t = type { [2 x %struct.int16x8_t] } -define arm_apcscc void @t(%struct.int16x8x2_t* noalias nocapture sret %agg.result, <8 x i16> %tmp.0, %struct.int16x8x2_t* nocapture %dst) nounwind { +define void @t(%struct.int16x8x2_t* noalias nocapture sret %agg.result, <8 x i16> %tmp.0, %struct.int16x8x2_t* nocapture %dst) nounwind { entry: ;CHECK: vtrn.16 %0 = shufflevector <8 x i16> %tmp.0, <8 x i16> undef, <8 x i32> <i32 0, i32 0, i32 2, i32 2, i32 4, i32 4, i32 6, i32 6> diff --git a/test/CodeGen/ARM/2010-04-09-NeonSelect.ll b/test/CodeGen/ARM/2010-04-09-NeonSelect.ll index 71e0b0a..89d6a68 100644 --- a/test/CodeGen/ARM/2010-04-09-NeonSelect.ll +++ b/test/CodeGen/ARM/2010-04-09-NeonSelect.ll @@ -1,7 +1,7 @@ ; RUN: llc -march=arm -mattr=+neon < %s ; Radar 7770501: Don't crash on SELECT and SELECT_CC with NEON vector values. -define arm_apcscc void @vDSP_FFT16_copv(float* nocapture %O, float* nocapture %I, i32 %Direction) nounwind { +define void @vDSP_FFT16_copv(float* nocapture %O, float* nocapture %I, i32 %Direction) nounwind { entry: %.22 = select i1 undef, <4 x float> undef, <4 x float> zeroinitializer ; <<4 x float>> [#uses=1] %0 = fadd <4 x float> undef, %.22 ; <<4 x float>> [#uses=1] diff --git a/test/CodeGen/ARM/2010-04-13-v2f64SplitArg.ll b/test/CodeGen/ARM/2010-04-13-v2f64SplitArg.ll index 4f71b83..1354c79 100644 --- a/test/CodeGen/ARM/2010-04-13-v2f64SplitArg.ll +++ b/test/CodeGen/ARM/2010-04-13-v2f64SplitArg.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -mtriple=arm-apple-darwin -mcpu=cortex-a8 ; Radar 7855014 -define arm_apcscc void @test1(i32 %f0, i32 %f1, i32 %f2, <4 x i32> %f3) nounwind { +define void @test1(i32 %f0, i32 %f1, i32 %f2, <4 x i32> %f3) nounwind { entry: unreachable } diff --git a/test/CodeGen/ARM/2010-04-14-SplitVector.ll b/test/CodeGen/ARM/2010-04-14-SplitVector.ll index 42f9852..5d0c3cf 100644 --- a/test/CodeGen/ARM/2010-04-14-SplitVector.ll +++ b/test/CodeGen/ARM/2010-04-14-SplitVector.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=arm -mcpu=arm1136jf-s ; Radar 7854640 -define arm_apcscc void @test() nounwind { +define void @test() nounwind { bb: br i1 undef, label %bb9, label %bb10 diff --git a/test/CodeGen/ARM/2010-04-15-ScavengerDebugValue.ll b/test/CodeGen/ARM/2010-04-15-ScavengerDebugValue.ll index ed7bca8..05581c3 100644 --- a/test/CodeGen/ARM/2010-04-15-ScavengerDebugValue.ll +++ b/test/CodeGen/ARM/2010-04-15-ScavengerDebugValue.ll @@ -3,7 +3,7 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64-n32" target triple = "armv4t-apple-darwin10" -define hidden arm_apcscc i32 @__addvsi3(i32 %a, i32 %b) nounwind { +define hidden i32 @__addvsi3(i32 %a, i32 %b) nounwind { entry: tail call void @llvm.dbg.value(metadata !{i32 %b}, i64 0, metadata !0) %0 = add nsw i32 %b, %a, !dbg !9 ; <i32> [#uses=1] diff --git a/test/CodeGen/ARM/2010-05-18-LocalAllocCrash.ll b/test/CodeGen/ARM/2010-05-18-LocalAllocCrash.ll index b158afd..9461643 100644 --- a/test/CodeGen/ARM/2010-05-18-LocalAllocCrash.ll +++ b/test/CodeGen/ARM/2010-05-18-LocalAllocCrash.ll @@ -1,4 +1,3 @@ -; RUN: llc < %s -O0 -verify-machineinstrs -regalloc=local ; RUN: llc < %s -O0 -verify-machineinstrs -regalloc=fast ; rdar://problem/7948106 ;; This test would spill %R4 before the call to zz, but it forgot to move the @@ -11,7 +10,7 @@ target triple = "armv6-apple-darwin" @.str = external constant [1 x i8] ; <[1 x i8]*> [#uses=1] -define arm_apcscc void @yy(%struct.q* %qq) nounwind { +define void @yy(%struct.q* %qq) nounwind { entry: %vla6 = alloca i8, i32 undef, align 1 ; <i8*> [#uses=1] %vla10 = alloca i8, i32 undef, align 1 ; <i8*> [#uses=1] @@ -20,18 +19,18 @@ entry: %tmp21 = load i32* undef ; <i32> [#uses=1] %0 = mul i32 1, %tmp21 ; <i32> [#uses=1] %vla22 = alloca i8, i32 %0, align 1 ; <i8*> [#uses=1] - call arm_apcscc void (...)* @zz(i8* getelementptr inbounds ([1 x i8]* @.str, i32 0, i32 0), i32 2, i32 1) + call void (...)* @zz(i8* getelementptr inbounds ([1 x i8]* @.str, i32 0, i32 0), i32 2, i32 1) br i1 undef, label %if.then, label %if.end36 if.then: ; preds = %entry - %call = call arm_apcscc i32 (...)* @x(%struct.q* undef, i8* undef, i8* %vla6, i8* %vla10, i32 undef) ; <i32> [#uses=0] - %call35 = call arm_apcscc i32 (...)* @x(%struct.q* undef, i8* %vla14, i8* %vla18, i8* %vla22, i32 undef) ; <i32> [#uses=0] + %call = call i32 (...)* @x(%struct.q* undef, i8* undef, i8* %vla6, i8* %vla10, i32 undef) ; <i32> [#uses=0] + %call35 = call i32 (...)* @x(%struct.q* undef, i8* %vla14, i8* %vla18, i8* %vla22, i32 undef) ; <i32> [#uses=0] unreachable if.end36: ; preds = %entry ret void } -declare arm_apcscc void @zz(...) +declare void @zz(...) -declare arm_apcscc i32 @x(...) +declare i32 @x(...) diff --git a/test/CodeGen/ARM/2010-05-18-PostIndexBug.ll b/test/CodeGen/ARM/2010-05-18-PostIndexBug.ll index 9907228..5ad1c09 100644 --- a/test/CodeGen/ARM/2010-05-18-PostIndexBug.ll +++ b/test/CodeGen/ARM/2010-05-18-PostIndexBug.ll @@ -4,7 +4,7 @@ %struct.foo = type { i64, i64 } -define arm_apcscc zeroext i8 @t(%struct.foo* %this) noreturn optsize { +define zeroext i8 @t(%struct.foo* %this) noreturn optsize { entry: ; ARM: t: ; ARM: str r0, [r1], r0 diff --git a/test/CodeGen/ARM/2010-05-20-NEONSpillCrash.ll b/test/CodeGen/ARM/2010-05-20-NEONSpillCrash.ll index b6fbf9b..ff60fa8 100644 --- a/test/CodeGen/ARM/2010-05-20-NEONSpillCrash.ll +++ b/test/CodeGen/ARM/2010-05-20-NEONSpillCrash.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+neon -O0 +; RUN: llc < %s -march=arm -mattr=+neon -O0 -regalloc=linearscan ; This test would crash the rewriter when trying to handle a spill after one of ; the @llvm.arm.neon.vld3.v8i8 defined three parts of a register. diff --git a/test/CodeGen/ARM/2010-05-21-BuildVector.ll b/test/CodeGen/ARM/2010-05-21-BuildVector.ll index 6b19490..ce959d1 100644 --- a/test/CodeGen/ARM/2010-05-21-BuildVector.ll +++ b/test/CodeGen/ARM/2010-05-21-BuildVector.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s ; Radar 7872877 -define arm_apcscc void @test(float* %fltp, i32 %packedValue, float* %table) nounwind { +define void @test(float* %fltp, i32 %packedValue, float* %table) nounwind { entry: %0 = load float* %fltp %1 = insertelement <4 x float> undef, float %0, i32 0 diff --git a/test/CodeGen/ARM/2010-06-11-vmovdrr-bitcast.ll b/test/CodeGen/ARM/2010-06-11-vmovdrr-bitcast.ll new file mode 100644 index 0000000..e4f2099 --- /dev/null +++ b/test/CodeGen/ARM/2010-06-11-vmovdrr-bitcast.ll @@ -0,0 +1,19 @@ +; RUN: llc < %s -march=arm -mattr=+neon +; Radar 8084742 + +%struct.__int8x8x2_t = type { [2 x <8 x i8>] } + +define void @foo(%struct.__int8x8x2_t* nocapture %a, i8* %b) nounwind { +entry: + %0 = bitcast %struct.__int8x8x2_t* %a to i128* ; <i128*> [#uses=1] + %srcval = load i128* %0, align 8 ; <i128> [#uses=2] + %tmp6 = trunc i128 %srcval to i64 ; <i64> [#uses=1] + %tmp8 = lshr i128 %srcval, 64 ; <i128> [#uses=1] + %tmp9 = trunc i128 %tmp8 to i64 ; <i64> [#uses=1] + %tmp16.i = bitcast i64 %tmp6 to <8 x i8> ; <<8 x i8>> [#uses=1] + %tmp20.i = bitcast i64 %tmp9 to <8 x i8> ; <<8 x i8>> [#uses=1] + tail call void @llvm.arm.neon.vst2.v8i8(i8* %b, <8 x i8> %tmp16.i, <8 x i8> %tmp20.i) nounwind + ret void +} + +declare void @llvm.arm.neon.vst2.v8i8(i8*, <8 x i8>, <8 x i8>) nounwind diff --git a/test/CodeGen/ARM/2010-06-21-LdStMultipleBug.ll b/test/CodeGen/ARM/2010-06-21-LdStMultipleBug.ll new file mode 100644 index 0000000..816a6d4 --- /dev/null +++ b/test/CodeGen/ARM/2010-06-21-LdStMultipleBug.ll @@ -0,0 +1,148 @@ +; RUN: llc < %s -mtriple=armv7-apple-darwin -O3 -mcpu=arm1136jf-s +; PR7421 + +%struct.CONTENTBOX = type { i32, i32, i32, i32, i32 } +%struct.FILE = type { i8* } +%struct.tilebox = type { %struct.tilebox*, double, double, double, double, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } +%struct.UNCOMBOX = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } +%struct.cellbox = type { i8*, i32, i32, i32, [9 x i32], i32, i32, i32, i32, i32, i32, i32, double, double, double, double, double, i32, i32, %struct.CONTENTBOX*, %struct.UNCOMBOX*, [8 x %struct.tilebox*] } +%struct.termbox = type { %struct.termbox*, i32, i32, i32, i32, i32 } + +@.str2708 = external constant [14 x i8], align 4 ; <[14 x i8]*> [#uses=1] + +define void @TW_oldinput(%struct.FILE* nocapture %fp) nounwind { +entry: + %xcenter = alloca i32, align 4 ; <i32*> [#uses=2] + %0 = call i32 (%struct.FILE*, i8*, ...)* @fscanf(%struct.FILE* %fp, i8* getelementptr inbounds ([14 x i8]* @.str2708, i32 0, i32 0), i32* undef, i32* undef, i32* %xcenter, i32* null) nounwind ; <i32> [#uses=1] + %1 = icmp eq i32 %0, 4 ; <i1> [#uses=1] + br i1 %1, label %bb, label %return + +bb: ; preds = %bb445, %entry + %2 = load %struct.cellbox** undef, align 4 ; <%struct.cellbox*> [#uses=2] + %3 = getelementptr inbounds %struct.cellbox* %2, i32 0, i32 3 ; <i32*> [#uses=1] + store i32 undef, i32* %3, align 4 + %4 = load i32* undef, align 4 ; <i32> [#uses=3] + %5 = icmp eq i32 undef, 1 ; <i1> [#uses=1] + br i1 %5, label %bb10, label %bb445 + +bb10: ; preds = %bb + br i1 undef, label %bb11, label %bb445 + +bb11: ; preds = %bb10 + %6 = load %struct.tilebox** undef, align 4 ; <%struct.tilebox*> [#uses=3] + %7 = load %struct.termbox** null, align 4 ; <%struct.termbox*> [#uses=1] + %8 = getelementptr inbounds %struct.tilebox* %6, i32 0, i32 13 ; <i32*> [#uses=1] + %9 = load i32* %8, align 4 ; <i32> [#uses=3] + %10 = getelementptr inbounds %struct.tilebox* %6, i32 0, i32 15 ; <i32*> [#uses=1] + %11 = load i32* %10, align 4 ; <i32> [#uses=1] + br i1 false, label %bb12, label %bb13 + +bb12: ; preds = %bb11 + unreachable + +bb13: ; preds = %bb11 + %iftmp.40.0.neg = sdiv i32 0, -2 ; <i32> [#uses=2] + %12 = sub nsw i32 0, %9 ; <i32> [#uses=1] + %13 = sitofp i32 %12 to double ; <double> [#uses=1] + %14 = fdiv double %13, 0.000000e+00 ; <double> [#uses=1] + %15 = fptosi double %14 to i32 ; <i32> [#uses=1] + %iftmp.41.0.in = add i32 0, %15 ; <i32> [#uses=1] + %iftmp.41.0.neg = sdiv i32 %iftmp.41.0.in, -2 ; <i32> [#uses=3] + br i1 undef, label %bb43.loopexit, label %bb21 + +bb21: ; preds = %bb13 + %16 = fptosi double undef to i32 ; <i32> [#uses=1] + %17 = fsub double undef, 0.000000e+00 ; <double> [#uses=1] + %not.460 = fcmp oge double %17, 5.000000e-01 ; <i1> [#uses=1] + %18 = zext i1 %not.460 to i32 ; <i32> [#uses=1] + %iftmp.42.0 = add i32 %16, %iftmp.41.0.neg ; <i32> [#uses=1] + %19 = add i32 %iftmp.42.0, %18 ; <i32> [#uses=1] + store i32 %19, i32* undef, align 4 + %20 = sub nsw i32 0, %9 ; <i32> [#uses=1] + %21 = sitofp i32 %20 to double ; <double> [#uses=1] + %22 = fdiv double %21, 0.000000e+00 ; <double> [#uses=2] + %23 = fptosi double %22 to i32 ; <i32> [#uses=1] + %24 = fsub double %22, undef ; <double> [#uses=1] + %not.461 = fcmp oge double %24, 5.000000e-01 ; <i1> [#uses=1] + %25 = zext i1 %not.461 to i32 ; <i32> [#uses=1] + %iftmp.43.0 = add i32 %23, %iftmp.41.0.neg ; <i32> [#uses=1] + %26 = add i32 %iftmp.43.0, %25 ; <i32> [#uses=1] + %27 = getelementptr inbounds %struct.tilebox* %6, i32 0, i32 10 ; <i32*> [#uses=1] + store i32 %26, i32* %27, align 4 + %28 = fptosi double undef to i32 ; <i32> [#uses=1] + %iftmp.45.0 = add i32 %28, %iftmp.40.0.neg ; <i32> [#uses=1] + %29 = add i32 %iftmp.45.0, 0 ; <i32> [#uses=1] + store i32 %29, i32* undef, align 4 + br label %bb43.loopexit + +bb36: ; preds = %bb43.loopexit, %bb36 + %termptr.0478 = phi %struct.termbox* [ %42, %bb36 ], [ %7, %bb43.loopexit ] ; <%struct.termbox*> [#uses=1] + %30 = load i32* undef, align 4 ; <i32> [#uses=1] + %31 = sub nsw i32 %30, %9 ; <i32> [#uses=1] + %32 = sitofp i32 %31 to double ; <double> [#uses=1] + %33 = fdiv double %32, 0.000000e+00 ; <double> [#uses=1] + %34 = fptosi double %33 to i32 ; <i32> [#uses=1] + %iftmp.46.0 = add i32 %34, %iftmp.41.0.neg ; <i32> [#uses=1] + %35 = add i32 %iftmp.46.0, 0 ; <i32> [#uses=1] + store i32 %35, i32* undef, align 4 + %36 = sub nsw i32 0, %11 ; <i32> [#uses=1] + %37 = sitofp i32 %36 to double ; <double> [#uses=1] + %38 = fmul double %37, 0.000000e+00 ; <double> [#uses=1] + %39 = fptosi double %38 to i32 ; <i32> [#uses=1] + %iftmp.47.0 = add i32 %39, %iftmp.40.0.neg ; <i32> [#uses=1] + %40 = add i32 %iftmp.47.0, 0 ; <i32> [#uses=1] + store i32 %40, i32* undef, align 4 + %41 = getelementptr inbounds %struct.termbox* %termptr.0478, i32 0, i32 0 ; <%struct.termbox**> [#uses=1] + %42 = load %struct.termbox** %41, align 4 ; <%struct.termbox*> [#uses=2] + %43 = icmp eq %struct.termbox* %42, null ; <i1> [#uses=1] + br i1 %43, label %bb52.loopexit, label %bb36 + +bb43.loopexit: ; preds = %bb21, %bb13 + br i1 undef, label %bb52.loopexit, label %bb36 + +bb52.loopexit: ; preds = %bb43.loopexit, %bb36 + %44 = icmp eq i32 %4, 0 ; <i1> [#uses=1] + br i1 %44, label %bb.nph485, label %bb54 + +bb54: ; preds = %bb52.loopexit + switch i32 %4, label %bb62 [ + i32 2, label %bb56 + i32 3, label %bb57 + ] + +bb56: ; preds = %bb54 + br label %bb62 + +bb57: ; preds = %bb54 + br label %bb62 + +bb62: ; preds = %bb57, %bb56, %bb54 + unreachable + +bb.nph485: ; preds = %bb52.loopexit + br label %bb248 + +bb248: ; preds = %bb322, %bb.nph485 + %45 = icmp eq i32 undef, %4 ; <i1> [#uses=1] + br i1 %45, label %bb322, label %bb249 + +bb249: ; preds = %bb248 + %46 = getelementptr inbounds %struct.cellbox* %2, i32 0, i32 21, i32 undef ; <%struct.tilebox**> [#uses=1] + %47 = load %struct.tilebox** %46, align 4 ; <%struct.tilebox*> [#uses=1] + %48 = getelementptr inbounds %struct.tilebox* %47, i32 0, i32 11 ; <i32*> [#uses=1] + store i32 undef, i32* %48, align 4 + unreachable + +bb322: ; preds = %bb248 + br i1 undef, label %bb248, label %bb445 + +bb445: ; preds = %bb322, %bb10, %bb + %49 = call i32 (%struct.FILE*, i8*, ...)* @fscanf(%struct.FILE* %fp, i8* getelementptr inbounds ([14 x i8]* @.str2708, i32 0, i32 0), i32* undef, i32* undef, i32* %xcenter, i32* null) nounwind ; <i32> [#uses=1] + %50 = icmp eq i32 %49, 4 ; <i1> [#uses=1] + br i1 %50, label %bb, label %return + +return: ; preds = %bb445, %entry + ret void +} + +declare i32 @fscanf(%struct.FILE* nocapture, i8* nocapture, ...) nounwind diff --git a/test/CodeGen/ARM/2010-06-21-nondarwin-tc.ll b/test/CodeGen/ARM/2010-06-21-nondarwin-tc.ll new file mode 100755 index 0000000..7650d88 --- /dev/null +++ b/test/CodeGen/ARM/2010-06-21-nondarwin-tc.ll @@ -0,0 +1,145 @@ +; RUN: llc < %s -march=arm -mtriple=armv4t-unknown-linux-gnueabi | FileCheck %s +; PR 7433 + +%0 = type { i8*, i8* } +%1 = type { i8*, i8*, i8* } +%"class.llvm::Record" = type { i32, %"class.std::basic_string", %"class.llvm::SMLoc", %"class.std::vector", %"class.std::vector", %"class.std::vector" } +%"class.llvm::RecordVal" = type { %"class.std::basic_string", %"struct.llvm::Init"*, i32, %"struct.llvm::Init"* } +%"class.llvm::SMLoc" = type { i8* } +%"class.llvm::StringInit" = type { [8 x i8], %"class.std::basic_string" } +%"class.std::basic_string" = type { %"class.llvm::SMLoc" } +%"class.std::vector" = type { [12 x i8] } +%"struct.llvm::Init" = type { i32 (...)** } + +@_ZTIN4llvm5RecTyE = external constant %0 ; <%0*> [#uses=1] +@_ZTIN4llvm4InitE = external constant %0 ; <%0*> [#uses=1] +@_ZTIN4llvm11RecordRecTyE = external constant %1 ; <%1*> [#uses=1] +@.str8 = external constant [47 x i8] ; <[47 x i8]*> [#uses=1] +@_ZTIN4llvm9UnsetInitE = external constant %1 ; <%1*> [#uses=1] +@.str51 = external constant [45 x i8] ; <[45 x i8]*> [#uses=1] +@__PRETTY_FUNCTION__._ZNK4llvm7VarInit12getFieldInitERNS_6RecordEPKNS_9RecordValERKSs = external constant [116 x i8] ; <[116 x i8]*> [#uses=1] + +@_ZN4llvm9RecordValC1ERKSsPNS_5RecTyEj = alias void (%"class.llvm::RecordVal"*, %"class.std::basic_string"*, %"struct.llvm::Init"*, i32)* @_ZN4llvm9RecordValC2ERKSsPNS_5RecTyEj ; <void (%"class.llvm::RecordVal"*, %"class.std::basic_string"*, %"struct.llvm::Init"*, i32)*> [#uses=0] + +declare i8* @__dynamic_cast(i8*, i8*, i8*, i32) + +declare void @__assert_fail(i8*, i8*, i32, i8*) noreturn + +declare void @_ZN4llvm9RecordValC2ERKSsPNS_5RecTyEj(%"class.llvm::RecordVal"*, %"class.std::basic_string"*, %"struct.llvm::Init"*, i32) align 2 + +define %"struct.llvm::Init"* @_ZNK4llvm7VarInit12getFieldInitERNS_6RecordEPKNS_9RecordValERKSs(%"class.llvm::StringInit"* %this, %"class.llvm::Record"* %R, %"class.llvm::RecordVal"* %RV, %"class.std::basic_string"* %FieldName) align 2 { +;CHECK: ldmia sp!, {r4, r5, r6, r7, r8, lr} +;CHECK: bx r12 @ TAILCALL +entry: + %.loc = alloca i32 ; <i32*> [#uses=2] + %tmp.i = getelementptr inbounds %"class.llvm::StringInit"* %this, i32 0, i32 0, i32 4 ; <i8*> [#uses=1] + %0 = bitcast i8* %tmp.i to %"struct.llvm::Init"** ; <%"struct.llvm::Init"**> [#uses=1] + %tmp2.i = load %"struct.llvm::Init"** %0 ; <%"struct.llvm::Init"*> [#uses=2] + %1 = icmp eq %"struct.llvm::Init"* %tmp2.i, null ; <i1> [#uses=1] + br i1 %1, label %entry.return_crit_edge, label %tmpbb + +entry.return_crit_edge: ; preds = %entry + br label %return + +tmpbb: ; preds = %entry + %2 = bitcast %"struct.llvm::Init"* %tmp2.i to i8* ; <i8*> [#uses=1] + %3 = tail call i8* @__dynamic_cast(i8* %2, i8* bitcast (%0* @_ZTIN4llvm5RecTyE to i8*), i8* bitcast (%1* @_ZTIN4llvm11RecordRecTyE to i8*), i32 -1) ; <i8*> [#uses=1] + %phitmp = icmp eq i8* %3, null ; <i1> [#uses=1] + br i1 %phitmp, label %.return_crit_edge, label %if.then + +.return_crit_edge: ; preds = %tmpbb + br label %return + +if.then: ; preds = %tmpbb + %tmp2.i.i.i.i = getelementptr inbounds %"class.llvm::StringInit"* %this, i32 0, i32 1, i32 0, i32 0 ; <i8**> [#uses=1] + %tmp3.i.i.i.i = load i8** %tmp2.i.i.i.i ; <i8*> [#uses=2] + %arrayidx.i.i.i.i = getelementptr inbounds i8* %tmp3.i.i.i.i, i32 -12 ; <i8*> [#uses=1] + %tmp.i.i.i = bitcast i8* %arrayidx.i.i.i.i to i32* ; <i32*> [#uses=1] + %tmp2.i.i.i = load i32* %tmp.i.i.i ; <i32> [#uses=1] + %tmp.i5 = getelementptr inbounds %"class.llvm::Record"* %R, i32 0, i32 4 ; <%"class.std::vector"*> [#uses=1] + %tmp2.i.i = getelementptr inbounds %"class.llvm::Record"* %R, i32 0, i32 4, i32 0, i32 4 ; <i8*> [#uses=1] + %4 = bitcast i8* %tmp2.i.i to %"class.llvm::RecordVal"** ; <%"class.llvm::RecordVal"**> [#uses=1] + %tmp3.i.i6 = load %"class.llvm::RecordVal"** %4 ; <%"class.llvm::RecordVal"*> [#uses=1] + %tmp5.i.i = bitcast %"class.std::vector"* %tmp.i5 to %"class.llvm::RecordVal"** ; <%"class.llvm::RecordVal"**> [#uses=1] + %tmp6.i.i = load %"class.llvm::RecordVal"** %tmp5.i.i ; <%"class.llvm::RecordVal"*> [#uses=5] + %sub.ptr.lhs.cast.i.i = ptrtoint %"class.llvm::RecordVal"* %tmp3.i.i6 to i32 ; <i32> [#uses=1] + %sub.ptr.rhs.cast.i.i = ptrtoint %"class.llvm::RecordVal"* %tmp6.i.i to i32 ; <i32> [#uses=1] + %sub.ptr.sub.i.i = sub i32 %sub.ptr.lhs.cast.i.i, %sub.ptr.rhs.cast.i.i ; <i32> [#uses=1] + %sub.ptr.div.i.i = ashr i32 %sub.ptr.sub.i.i, 4 ; <i32> [#uses=1] + br label %codeRepl + +codeRepl: ; preds = %if.then + %targetBlock = call i1 @_ZNK4llvm7VarInit12getFieldInitERNS_6RecordEPKNS_9RecordValERKSs_for.cond.i(i32 %sub.ptr.div.i.i, %"class.llvm::RecordVal"* %tmp6.i.i, i32 %tmp2.i.i.i, i8* %tmp3.i.i.i.i, i32* %.loc) ; <i1> [#uses=1] + %.reload = load i32* %.loc ; <i32> [#uses=3] + br i1 %targetBlock, label %for.cond.i.return_crit_edge, label %_ZN4llvm6Record8getValueENS_9StringRefE.exit + +for.cond.i.return_crit_edge: ; preds = %codeRepl + br label %return + +_ZN4llvm6Record8getValueENS_9StringRefE.exit: ; preds = %codeRepl + %add.ptr.i.i = getelementptr inbounds %"class.llvm::RecordVal"* %tmp6.i.i, i32 %.reload ; <%"class.llvm::RecordVal"*> [#uses=2] + %tobool5 = icmp eq %"class.llvm::RecordVal"* %add.ptr.i.i, null ; <i1> [#uses=1] + br i1 %tobool5, label %_ZN4llvm6Record8getValueENS_9StringRefE.exit.return_crit_edge, label %if.then6 + +_ZN4llvm6Record8getValueENS_9StringRefE.exit.return_crit_edge: ; preds = %_ZN4llvm6Record8getValueENS_9StringRefE.exit + br label %return + +if.then6: ; preds = %_ZN4llvm6Record8getValueENS_9StringRefE.exit + %cmp = icmp eq %"class.llvm::RecordVal"* %add.ptr.i.i, %RV ; <i1> [#uses=1] + br i1 %cmp, label %if.then6.if.end_crit_edge, label %land.lhs.true + +if.then6.if.end_crit_edge: ; preds = %if.then6 + br label %if.end + +land.lhs.true: ; preds = %if.then6 + %tobool10 = icmp eq %"class.llvm::RecordVal"* %RV, null ; <i1> [#uses=1] + br i1 %tobool10, label %lor.lhs.false, label %land.lhs.true.return_crit_edge + +land.lhs.true.return_crit_edge: ; preds = %land.lhs.true + br label %return + +lor.lhs.false: ; preds = %land.lhs.true + %tmp.i3 = getelementptr inbounds %"class.llvm::RecordVal"* %tmp6.i.i, i32 %.reload, i32 3 ; <%"struct.llvm::Init"**> [#uses=1] + %tmp2.i4 = load %"struct.llvm::Init"** %tmp.i3 ; <%"struct.llvm::Init"*> [#uses=2] + %5 = icmp eq %"struct.llvm::Init"* %tmp2.i4, null ; <i1> [#uses=1] + br i1 %5, label %lor.lhs.false.if.end_crit_edge, label %tmpbb1 + +lor.lhs.false.if.end_crit_edge: ; preds = %lor.lhs.false + br label %if.end + +tmpbb1: ; preds = %lor.lhs.false + %6 = bitcast %"struct.llvm::Init"* %tmp2.i4 to i8* ; <i8*> [#uses=1] + %7 = tail call i8* @__dynamic_cast(i8* %6, i8* bitcast (%0* @_ZTIN4llvm4InitE to i8*), i8* bitcast (%1* @_ZTIN4llvm9UnsetInitE to i8*), i32 -1) ; <i8*> [#uses=1] + %phitmp32 = icmp eq i8* %7, null ; <i1> [#uses=1] + br i1 %phitmp32, label %.if.end_crit_edge, label %.return_crit_edge1 + +.return_crit_edge1: ; preds = %tmpbb1 + br label %return + +.if.end_crit_edge: ; preds = %tmpbb1 + br label %if.end + +if.end: ; preds = %.if.end_crit_edge, %lor.lhs.false.if.end_crit_edge, %if.then6.if.end_crit_edge + %tmp.i1 = getelementptr inbounds %"class.llvm::RecordVal"* %tmp6.i.i, i32 %.reload, i32 3 ; <%"struct.llvm::Init"**> [#uses=1] + %tmp2.i2 = load %"struct.llvm::Init"** %tmp.i1 ; <%"struct.llvm::Init"*> [#uses=3] + %8 = bitcast %"class.llvm::StringInit"* %this to %"struct.llvm::Init"* ; <%"struct.llvm::Init"*> [#uses=1] + %cmp19 = icmp eq %"struct.llvm::Init"* %tmp2.i2, %8 ; <i1> [#uses=1] + br i1 %cmp19, label %cond.false, label %cond.end + +cond.false: ; preds = %if.end + tail call void @__assert_fail(i8* getelementptr inbounds ([45 x i8]* @.str51, i32 0, i32 0), i8* getelementptr inbounds ([47 x i8]* @.str8, i32 0, i32 0), i32 1141, i8* getelementptr inbounds ([116 x i8]* @__PRETTY_FUNCTION__._ZNK4llvm7VarInit12getFieldInitERNS_6RecordEPKNS_9RecordValERKSs, i32 0, i32 0)) noreturn + unreachable + +cond.end: ; preds = %if.end + %9 = bitcast %"struct.llvm::Init"* %tmp2.i2 to %"struct.llvm::Init"* (%"struct.llvm::Init"*, %"class.llvm::Record"*, %"class.llvm::RecordVal"*, %"class.std::basic_string"*)*** ; <%"struct.llvm::Init"* (%"struct.llvm::Init"*, %"class.llvm::Record"*, %"class.llvm::RecordVal"*, %"class.std::basic_string"*)***> [#uses=1] + %10 = load %"struct.llvm::Init"* (%"struct.llvm::Init"*, %"class.llvm::Record"*, %"class.llvm::RecordVal"*, %"class.std::basic_string"*)*** %9 ; <%"struct.llvm::Init"* (%"struct.llvm::Init"*, %"class.llvm::Record"*, %"class.llvm::RecordVal"*, %"class.std::basic_string"*)**> [#uses=1] + %vfn = getelementptr inbounds %"struct.llvm::Init"* (%"struct.llvm::Init"*, %"class.llvm::Record"*, %"class.llvm::RecordVal"*, %"class.std::basic_string"*)** %10, i32 8 ; <%"struct.llvm::Init"* (%"struct.llvm::Init"*, %"class.llvm::Record"*, %"class.llvm::RecordVal"*, %"class.std::basic_string"*)**> [#uses=1] + %11 = load %"struct.llvm::Init"* (%"struct.llvm::Init"*, %"class.llvm::Record"*, %"class.llvm::RecordVal"*, %"class.std::basic_string"*)** %vfn ; <%"struct.llvm::Init"* (%"struct.llvm::Init"*, %"class.llvm::Record"*, %"class.llvm::RecordVal"*, %"class.std::basic_string"*)*> [#uses=1] + %call25 = tail call %"struct.llvm::Init"* %11(%"struct.llvm::Init"* %tmp2.i2, %"class.llvm::Record"* %R, %"class.llvm::RecordVal"* %RV, %"class.std::basic_string"* %FieldName) ; <%"struct.llvm::Init"*> [#uses=1] + ret %"struct.llvm::Init"* %call25 + +return: ; preds = %.return_crit_edge1, %land.lhs.true.return_crit_edge, %_ZN4llvm6Record8getValueENS_9StringRefE.exit.return_crit_edge, %for.cond.i.return_crit_edge, %.return_crit_edge, %entry.return_crit_edge + ret %"struct.llvm::Init"* null +} + +declare i1 @_ZNK4llvm7VarInit12getFieldInitERNS_6RecordEPKNS_9RecordValERKSs_for.cond.i(i32, %"class.llvm::RecordVal"*, i32, i8*, i32*) diff --git a/test/CodeGen/ARM/2010-06-25-Thumb2ITInvalidIterator.ll b/test/CodeGen/ARM/2010-06-25-Thumb2ITInvalidIterator.ll new file mode 100644 index 0000000..cdb11c7 --- /dev/null +++ b/test/CodeGen/ARM/2010-06-25-Thumb2ITInvalidIterator.ll @@ -0,0 +1,75 @@ +; RUN: llc < %s + +target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32-n32" +target triple = "thumbv7-apple-darwin3.0.0-iphoneos" + +@length = common global i32 0, align 4 ; <i32*> [#uses=1] + +define void @x0(i8* nocapture %buf, i32 %nbytes) nounwind optsize { +entry: + tail call void @llvm.dbg.value(metadata !{i8* %buf}, i64 0, metadata !0), !dbg !15 + tail call void @llvm.dbg.value(metadata !{i32 %nbytes}, i64 0, metadata !8), !dbg !16 + %tmp = load i32* @length, !dbg !17 ; <i32> [#uses=3] + %cmp = icmp eq i32 %tmp, -1, !dbg !17 ; <i1> [#uses=1] + %cmp.not = xor i1 %cmp, true ; <i1> [#uses=1] + %cmp3 = icmp ult i32 %tmp, %nbytes, !dbg !17 ; <i1> [#uses=1] + %or.cond = and i1 %cmp.not, %cmp3 ; <i1> [#uses=1] + tail call void @llvm.dbg.value(metadata !{i32 %tmp}, i64 0, metadata !8), !dbg !17 + %nbytes.addr.0 = select i1 %or.cond, i32 %tmp, i32 %nbytes ; <i32> [#uses=1] + tail call void @llvm.dbg.value(metadata !18, i64 0, metadata !10), !dbg !19 + br label %while.cond, !dbg !20 + +while.cond: ; preds = %while.body, %entry + %0 = phi i32 [ 0, %entry ], [ %inc, %while.body ] ; <i32> [#uses=3] + %buf.addr.0 = getelementptr i8* %buf, i32 %0 ; <i8*> [#uses=1] + %cmp7 = icmp ult i32 %0, %nbytes.addr.0, !dbg !20 ; <i1> [#uses=1] + br i1 %cmp7, label %land.rhs, label %while.end, !dbg !20 + +land.rhs: ; preds = %while.cond + %call = tail call i32 @x1() nounwind optsize, !dbg !20 ; <i32> [#uses=2] + %cmp9 = icmp eq i32 %call, -1, !dbg !20 ; <i1> [#uses=1] + br i1 %cmp9, label %while.end, label %while.body, !dbg !20 + +while.body: ; preds = %land.rhs + %conv = trunc i32 %call to i8, !dbg !21 ; <i8> [#uses=1] + store i8 %conv, i8* %buf.addr.0, !dbg !21 + %inc = add i32 %0, 1, !dbg !23 ; <i32> [#uses=1] + br label %while.cond, !dbg !24 + +while.end: ; preds = %land.rhs, %while.cond + ret void, !dbg !25 +} + +declare i32 @x1() optsize + +declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone + +!llvm.dbg.lv.fn = !{!0, !8, !10, !12} +!llvm.dbg.gv = !{!14} + +!0 = metadata !{i32 524545, metadata !1, metadata !"buf", metadata !2, i32 4, metadata !6} ; [ DW_TAG_arg_variable ] +!1 = metadata !{i32 524334, i32 0, metadata !2, metadata !"x0", metadata !"x0", metadata !"x0", metadata !2, i32 5, metadata !4, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, null} ; [ DW_TAG_subprogram ] +!2 = metadata !{i32 524329, metadata !"t.c", metadata !"/private/tmp", metadata !3} ; [ DW_TAG_file_type ] +!3 = metadata !{i32 524305, i32 0, i32 12, metadata !"t.c", metadata !".", metadata !"clang 2.0", i1 true, i1 true, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!4 = metadata !{i32 524309, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !5, i32 0, null} ; [ DW_TAG_subroutine_type ] +!5 = metadata !{null} +!6 = metadata !{i32 524303, metadata !2, metadata !"", metadata !2, i32 0, i64 32, i64 32, i64 0, i32 0, metadata !7} ; [ DW_TAG_pointer_type ] +!7 = metadata !{i32 524324, metadata !2, metadata !"unsigned char", metadata !2, i32 0, i64 8, i64 8, i64 0, i32 0, i32 8} ; [ DW_TAG_base_type ] +!8 = metadata !{i32 524545, metadata !1, metadata !"nbytes", metadata !2, i32 4, metadata !9} ; [ DW_TAG_arg_variable ] +!9 = metadata !{i32 524324, metadata !2, metadata !"unsigned long", metadata !2, i32 0, i64 32, i64 32, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ] +!10 = metadata !{i32 524544, metadata !11, metadata !"nread", metadata !2, i32 6, metadata !9} ; [ DW_TAG_auto_variable ] +!11 = metadata !{i32 524299, metadata !1, i32 5, i32 1} ; [ DW_TAG_lexical_block ] +!12 = metadata !{i32 524544, metadata !11, metadata !"c", metadata !2, i32 7, metadata !13} ; [ DW_TAG_auto_variable ] +!13 = metadata !{i32 524324, metadata !2, metadata !"int", metadata !2, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!14 = metadata !{i32 524340, i32 0, metadata !2, metadata !"length", metadata !"length", metadata !"length", metadata !2, i32 1, metadata !13, i1 false, i1 true, i32* @length} ; [ DW_TAG_variable ] +!15 = metadata !{i32 4, i32 24, metadata !1, null} +!16 = metadata !{i32 4, i32 43, metadata !1, null} +!17 = metadata !{i32 9, i32 2, metadata !11, null} +!18 = metadata !{i32 0} +!19 = metadata !{i32 10, i32 2, metadata !11, null} +!20 = metadata !{i32 11, i32 2, metadata !11, null} +!21 = metadata !{i32 12, i32 3, metadata !22, null} +!22 = metadata !{i32 524299, metadata !11, i32 11, i32 45} ; [ DW_TAG_lexical_block ] +!23 = metadata !{i32 13, i32 3, metadata !22, null} +!24 = metadata !{i32 14, i32 2, metadata !22, null} +!25 = metadata !{i32 15, i32 1, metadata !11, null} diff --git a/test/CodeGen/ARM/2010-06-28-DAGCombineUndef.ll b/test/CodeGen/ARM/2010-06-28-DAGCombineUndef.ll new file mode 100644 index 0000000..ad2810b --- /dev/null +++ b/test/CodeGen/ARM/2010-06-28-DAGCombineUndef.ll @@ -0,0 +1,10 @@ +; RUN: llc < %s -march=arm -mattr=+neon + +define void @main() nounwind { +entry: + store <2 x i64> undef, <2 x i64>* undef, align 16 + %0 = load <16 x i8>* undef, align 16 ; <<16 x i8>> [#uses=1] + %1 = or <16 x i8> zeroinitializer, %0 ; <<16 x i8>> [#uses=1] + store <16 x i8> %1, <16 x i8>* undef, align 16 + ret void +} diff --git a/test/CodeGen/ARM/2010-06-29-PartialRedefFastAlloc.ll b/test/CodeGen/ARM/2010-06-29-PartialRedefFastAlloc.ll new file mode 100644 index 0000000..0c5b180 --- /dev/null +++ b/test/CodeGen/ARM/2010-06-29-PartialRedefFastAlloc.ll @@ -0,0 +1,25 @@ +; RUN: llc < %s -O0 -mcpu=cortex-a8 | FileCheck %s +target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:32:64-v128:32:128-a0:0:32-n32" +target triple = "thumbv7-apple-darwin10" + +; This tests the fast register allocator's handling of partial redefines: +; +; %reg1028:dsub_0<def>, %reg1028:dsub_1<def> = VLD1q64 %reg1025... +; %reg1030:dsub_1<def> = COPY %reg1028:dsub_0<kill> +; +; %reg1028 gets allocated %Q0, and if %reg1030 is reloaded for the partial +; redef, it cannot also get %Q0. + +; CHECK: vld1.64 {d0, d1}, [r{{.}}] +; CHECK-NOT: vld1.64 {d0, d1} +; CHECK: vmov.f64 d3, d0 + +define i32 @test(i8* %arg) nounwind { +entry: + %0 = call <2 x i64> @llvm.arm.neon.vld1.v2i64(i8* %arg) + %1 = shufflevector <2 x i64> undef, <2 x i64> %0, <2 x i32> <i32 1, i32 2> + store <2 x i64> %1, <2 x i64>* undef, align 16 + ret i32 undef +} + +declare <2 x i64> @llvm.arm.neon.vld1.v2i64(i8*) nounwind readonly diff --git a/test/CodeGen/ARM/2010-06-29-SubregImpDefs.ll b/test/CodeGen/ARM/2010-06-29-SubregImpDefs.ll new file mode 100644 index 0000000..984583e --- /dev/null +++ b/test/CodeGen/ARM/2010-06-29-SubregImpDefs.ll @@ -0,0 +1,15 @@ +; RUN: llc < %s -march=arm -mattr=+neon + +@.str271 = external constant [21 x i8], align 4 ; <[21 x i8]*> [#uses=1] +@llvm.used = appending global [1 x i8*] [i8* bitcast (i32 (i32, i8**)* @main to i8*)], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0] + +define i32 @main(i32 %argc, i8** %argv) nounwind { +entry: + %0 = shufflevector <2 x i64> undef, <2 x i64> zeroinitializer, <2 x i32> <i32 1, i32 2> ; <<2 x i64>> [#uses=1] + store <2 x i64> %0, <2 x i64>* undef, align 16 + %val4723 = load <8 x i16>* undef ; <<8 x i16>> [#uses=1] + call void @PrintShortX(i8* getelementptr inbounds ([21 x i8]* @.str271, i32 0, i32 0), <8 x i16> %val4723, i32 0) nounwind + ret i32 undef +} + +declare void @PrintShortX(i8*, <8 x i16>, i32) nounwind diff --git a/test/CodeGen/ARM/alloca.ll b/test/CodeGen/ARM/alloca.ll index 82a8c98..4a0835a 100644 --- a/test/CodeGen/ARM/alloca.ll +++ b/test/CodeGen/ARM/alloca.ll @@ -2,11 +2,11 @@ define void @f(i32 %a) { entry: -; CHECK: mov r11, sp +; CHECK: add r11, sp, #4 %tmp = alloca i8, i32 %a ; <i8*> [#uses=1] call void @g( i8* %tmp, i32 %a, i32 1, i32 2, i32 3 ) ret void -; CHECK: mov sp, r11 +; CHECK: sub sp, r11, #4 } declare void @g(i8*, i32, i32, i32, i32) diff --git a/test/CodeGen/ARM/arm-frameaddr.ll b/test/CodeGen/ARM/arm-frameaddr.ll index 1c7ac25..2cf1422 100644 --- a/test/CodeGen/ARM/arm-frameaddr.ll +++ b/test/CodeGen/ARM/arm-frameaddr.ll @@ -3,7 +3,7 @@ ; PR4344 ; PR4416 -define arm_aapcscc i8* @t() nounwind { +define i8* @t() nounwind { entry: ; DARWIN: t: ; DARWIN: mov r0, r7 diff --git a/test/CodeGen/ARM/arm-returnaddr.ll b/test/CodeGen/ARM/arm-returnaddr.ll index 2c8f2ab..382a183 100644 --- a/test/CodeGen/ARM/arm-returnaddr.ll +++ b/test/CodeGen/ARM/arm-returnaddr.ll @@ -1,19 +1,21 @@ ; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s -; RUN: llc < %s -mtriple=thumbv6-apple-darwin +; RUN: llc < %s -mtriple=thumbv6-apple-darwin | FileCheck %s ; rdar://8015977 ; rdar://8020118 -define arm_apcscc i8* @rt0(i32 %x) nounwind readnone { +define i8* @rt0(i32 %x) nounwind readnone { entry: ; CHECK: rt0: +; CHECK: {r7, lr} ; CHECK: mov r0, lr %0 = tail call i8* @llvm.returnaddress(i32 0) ret i8* %0 } -define arm_apcscc i8* @rt2() nounwind readnone { +define i8* @rt2() nounwind readnone { entry: ; CHECK: rt2: +; CHECK: {r7, lr} ; CHECK: ldr r0, [r7] ; CHECK: ldr r0, [r0] ; CHECK: ldr r0, [r0, #4] diff --git a/test/CodeGen/ARM/armv4.ll b/test/CodeGen/ARM/armv4.ll index 49b129da..ef722de 100644 --- a/test/CodeGen/ARM/armv4.ll +++ b/test/CodeGen/ARM/armv4.ll @@ -5,7 +5,7 @@ ; RUN: llc < %s -mtriple=armv4-unknown-eabi | FileCheck %s -check-prefix=ARM ; RUN: llc < %s -mtriple=armv4t-unknown-eabi | FileCheck %s -check-prefix=THUMB -define arm_aapcscc i32 @test(i32 %a) nounwind readnone { +define i32 @test(i32 %a) nounwind readnone { entry: ; ARM: mov pc ; THUMB: bx diff --git a/test/CodeGen/ARM/call-tc.ll b/test/CodeGen/ARM/call-tc.ll new file mode 100644 index 0000000..f1269d5 --- /dev/null +++ b/test/CodeGen/ARM/call-tc.ll @@ -0,0 +1,48 @@ +; RUN: llc < %s -mtriple=arm-apple-darwin -march=arm | FileCheck %s -check-prefix=CHECKV4 +; RUN: llc < %s -march=arm -mtriple=arm-apple-darwin -mattr=+v5t | FileCheck %s -check-prefix=CHECKV5 +; RUN: llc < %s -march=arm -mtriple=arm-linux-gnueabi\ +; RUN: -relocation-model=pic | FileCheck %s -check-prefix=CHECKELF + +@t = weak global i32 ()* null ; <i32 ()**> [#uses=1] + +declare void @g(i32, i32, i32, i32) + +define void @t1() { +; CHECKELF: t1: +; CHECKELF: PLT + call void @g( i32 1, i32 2, i32 3, i32 4 ) + ret void +} + +define void @t2() { +; CHECKV4: t2: +; CHECKV4: bx r0 @ TAILCALL +; CHECKV5: t2: +; CHECKV5: bx r0 @ TAILCALL + %tmp = load i32 ()** @t ; <i32 ()*> [#uses=1] + %tmp.upgrd.2 = tail call i32 %tmp( ) ; <i32> [#uses=0] + ret void +} + +define i32* @t3(i32, i32, i32*, i32*, i32*) nounwind { +; CHECKV4: t3: +; CHECKV4: bx r{{.*}} +BB0: + %5 = inttoptr i32 %0 to i32* ; <i32*> [#uses=1] + %t35 = volatile load i32* %5 ; <i32> [#uses=1] + %6 = inttoptr i32 %t35 to i32** ; <i32**> [#uses=1] + %7 = getelementptr i32** %6, i32 86 ; <i32**> [#uses=1] + %8 = load i32** %7 ; <i32*> [#uses=1] + %9 = bitcast i32* %8 to i32* (i32, i32*, i32, i32*, i32*, i32*)* ; <i32* (i32, i32*, i32, i32*, i32*, i32*)*> [#uses=1] + %10 = call i32* %9(i32 %0, i32* null, i32 %1, i32* %2, i32* %3, i32* %4) ; <i32*> [#uses=1] + ret i32* %10 +} + +define void @t4() { +; CHECKV4: t4: +; CHECKV4: b _t2 @ TAILCALL +; CHECKV5: t4: +; CHECKV5: b _t2 @ TAILCALL + tail call void @t2( ) ; <i32> [#uses=0] + ret void +} diff --git a/test/CodeGen/ARM/call.ll b/test/CodeGen/ARM/call.ll index c60b75b..c020b6f 100644 --- a/test/CodeGen/ARM/call.ll +++ b/test/CodeGen/ARM/call.ll @@ -8,16 +8,16 @@ declare void @g(i32, i32, i32, i32) define void @f() { -; CHECKV4: mov lr, pc -; CHECKV5: blx ; CHECKELF: PLT call void @g( i32 1, i32 2, i32 3, i32 4 ) ret void } define void @g.upgrd.1() { +; CHECKV4: mov lr, pc +; CHECKV5: blx %tmp = load i32 ()** @t ; <i32 ()*> [#uses=1] - %tmp.upgrd.2 = tail call i32 %tmp( ) ; <i32> [#uses=0] + %tmp.upgrd.2 = call i32 %tmp( ) ; <i32> [#uses=0] ret void } diff --git a/test/CodeGen/ARM/crash-O0.ll b/test/CodeGen/ARM/crash-O0.ll new file mode 100644 index 0000000..8bce4e0 --- /dev/null +++ b/test/CodeGen/ARM/crash-O0.ll @@ -0,0 +1,28 @@ +; RUN: llc < %s -O0 -relocation-model=pic -disable-fp-elim +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64-n32" +target triple = "armv6-apple-darwin10" + +%struct0 = type { i32, i32 } + +; This function would crash RegAllocFast because it tried to spill %CPSR. +define arm_apcscc void @clobber_cc() nounwind noinline ssp { +entry: + %asmtmp = call %struct0 asm sideeffect "...", "=&r,=&r,r,Ir,r,~{cc},~{memory}"(i32* undef, i32 undef, i32 1) nounwind ; <%0> [#uses=0] + unreachable +} + +@.str523 = private constant [256 x i8] c"<Unknown>\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00", align 4 ; <[256 x i8]*> [#uses=1] +declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32, i1) nounwind + +; This function uses the scavenger for an ADDri instruction. +; ARMBaseRegisterInfo::estimateRSStackSizeLimit must return a 255 limit. +define arm_apcscc void @scavence_ADDri() nounwind { +entry: + %letter = alloca i8 ; <i8*> [#uses=0] + %prodvers = alloca [256 x i8] ; <[256 x i8]*> [#uses=1] + %buildver = alloca [256 x i8] ; <[256 x i8]*> [#uses=0] + call void @llvm.memcpy.p0i8.p0i8.i32(i8* undef, i8* getelementptr inbounds ([256 x i8]* @.str523, i32 0, i32 0), i32 256, i32 1, i1 false) + %prodvers2 = bitcast [256 x i8]* %prodvers to i8* ; <i8*> [#uses=1] + call void @llvm.memcpy.p0i8.p0i8.i32(i8* %prodvers2, i8* getelementptr inbounds ([256 x i8]* @.str523, i32 0, i32 0), i32 256, i32 1, i1 false) + unreachable +} diff --git a/test/CodeGen/ARM/flag-crash.ll b/test/CodeGen/ARM/flag-crash.ll new file mode 100644 index 0000000..9c61944 --- /dev/null +++ b/test/CodeGen/ARM/flag-crash.ll @@ -0,0 +1,27 @@ +; RUN: llc < %s -O3 -mtriple=thumbv7-apple-darwin10 -mcpu=cortex-a8 -relocation-model=pic +; PR7484 + +%struct.gs_matrix = type { float, i32, float, i32, float, i32, float, i32, float, i32, float, i32 } + +define fastcc void @func(%struct.gs_matrix* nocapture %pm1) nounwind { +entry: + %0 = getelementptr inbounds %struct.gs_matrix* %pm1, i32 0, i32 6 + %1 = load float* %0, align 4 + %2 = getelementptr inbounds %struct.gs_matrix* %pm1, i32 0, i32 8 + %3 = load float* %2, align 4 + %4 = getelementptr inbounds %struct.gs_matrix* %pm1, i32 0, i32 2 + %5 = bitcast float* %4 to i32* + %6 = load i32* %5, align 4 + %7 = or i32 0, %6 + %.mask = and i32 %7, 2147483647 + %8 = icmp eq i32 %.mask, 0 + br i1 %8, label %bb, label %bb11 + +bb: + ret void + +bb11: + %9 = fmul float %1, undef + %10 = fmul float %3, undef + ret void +} diff --git a/test/CodeGen/ARM/fpcmp-opt.ll b/test/CodeGen/ARM/fpcmp-opt.ll new file mode 100644 index 0000000..8016033 --- /dev/null +++ b/test/CodeGen/ARM/fpcmp-opt.ll @@ -0,0 +1,29 @@ +; RUN: llc < %s -march=arm -mattr=+vfp2 -enable-unsafe-fp-math -enable-finite-only-fp-math | FileCheck %s +; rdar://7461510 + +define arm_apcscc i32 @t1(float* %a, float* %b) nounwind { +entry: +; CHECK: t1: +; CHECK-NOT: vldr +; CHECK: ldr +; CHECK: ldr +; CHECK: cmp r0, r1 +; CHECK-NOT: vcmpe.f32 +; CHECK-NOT: vmrs +; CHECK: beq + %0 = load float* %a + %1 = load float* %b + %2 = fcmp une float %0, %1 + br i1 %2, label %bb1, label %bb2 + +bb1: + %3 = call i32 @bar() + ret i32 %3 + +bb2: + %4 = call i32 @foo() + ret i32 %4 +} + +declare i32 @bar() +declare i32 @foo() diff --git a/test/CodeGen/ARM/fpconsts.ll b/test/CodeGen/ARM/fpconsts.ll index 710994d..f1d6a16 100644 --- a/test/CodeGen/ARM/fpconsts.ll +++ b/test/CodeGen/ARM/fpconsts.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -march=arm -mattr=+vfp3 | FileCheck %s -define arm_apcscc float @t1(float %x) nounwind readnone optsize { +define float @t1(float %x) nounwind readnone optsize { entry: ; CHECK: t1: ; CHECK: vmov.f32 s1, #4.000000e+00 @@ -8,7 +8,7 @@ entry: ret float %0 } -define arm_apcscc double @t2(double %x) nounwind readnone optsize { +define double @t2(double %x) nounwind readnone optsize { entry: ; CHECK: t2: ; CHECK: vmov.f64 d1, #3.000000e+00 @@ -16,7 +16,7 @@ entry: ret double %0 } -define arm_apcscc double @t3(double %x) nounwind readnone optsize { +define double @t3(double %x) nounwind readnone optsize { entry: ; CHECK: t3: ; CHECK: vmov.f64 d1, #-1.300000e+01 @@ -24,7 +24,7 @@ entry: ret double %0 } -define arm_apcscc float @t4(float %x) nounwind readnone optsize { +define float @t4(float %x) nounwind readnone optsize { entry: ; CHECK: t4: ; CHECK: vmov.f32 s1, #-2.400000e+01 diff --git a/test/CodeGen/ARM/ifcvt2.ll b/test/CodeGen/ARM/ifcvt2.ll index d9cac80..7b9d0cf 100644 --- a/test/CodeGen/ARM/ifcvt2.ll +++ b/test/CodeGen/ARM/ifcvt2.ll @@ -1,10 +1,8 @@ -; RUN: llc < %s -march=arm > %t -; RUN: grep bxlt %t | count 1 -; RUN: grep bxgt %t | count 1 -; RUN: not grep bxge %t -; RUN: not grep bxle %t +; RUN: llc < %s -march=arm | FileCheck %s define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) { +; CHECK: t1: +; CHECK: bxlt lr %tmp2 = icmp sgt i32 %c, 10 %tmp5 = icmp slt i32 %d, 4 %tmp8 = or i1 %tmp5, %tmp2 @@ -21,6 +19,13 @@ UnifiedReturnBlock: } define i32 @t2(i32 %a, i32 %b, i32 %c, i32 %d) { +; CHECK: t2: +; CHECK: bxgt lr +; CHECK: cmp +; CHECK: addge +; CHECK: subge +; CHECK-NOT: bxge lr +; CHECK: bx lr %tmp2 = icmp sgt i32 %c, 10 %tmp5 = icmp slt i32 %d, 4 %tmp8 = and i1 %tmp5, %tmp2 diff --git a/test/CodeGen/ARM/ifcvt6.ll b/test/CodeGen/ARM/ifcvt6.ll index 342208b..e2c0ba3 100644 --- a/test/CodeGen/ARM/ifcvt6.ll +++ b/test/CodeGen/ARM/ifcvt6.ll @@ -11,7 +11,7 @@ entry: br i1 %tmp7, label %cond_true, label %UnifiedReturnBlock cond_true: ; preds = %entry - %tmp10 = tail call i32 (...)* @bar( ) ; <i32> [#uses=0] + %tmp10 = call i32 (...)* @bar( ) ; <i32> [#uses=0] ret void UnifiedReturnBlock: ; preds = %entry diff --git a/test/CodeGen/ARM/indirectbr.ll b/test/CodeGen/ARM/indirectbr.ll index f898060..0aac9d1 100644 --- a/test/CodeGen/ARM/indirectbr.ll +++ b/test/CodeGen/ARM/indirectbr.ll @@ -5,7 +5,7 @@ @nextaddr = global i8* null ; <i8**> [#uses=2] @C.0.2070 = private constant [5 x i8*] [i8* blockaddress(@foo, %L1), i8* blockaddress(@foo, %L2), i8* blockaddress(@foo, %L3), i8* blockaddress(@foo, %L4), i8* blockaddress(@foo, %L5)] ; <[5 x i8*]*> [#uses=1] -define internal arm_apcscc i32 @foo(i32 %i) nounwind { +define internal i32 @foo(i32 %i) nounwind { ; ARM: foo: ; THUMB: foo: ; THUMB2: foo: diff --git a/test/CodeGen/ARM/inlineasm.ll b/test/CodeGen/ARM/inlineasm.ll index d522348..cca3c69 100644 --- a/test/CodeGen/ARM/inlineasm.ll +++ b/test/CodeGen/ARM/inlineasm.ll @@ -6,14 +6,6 @@ define i32 @test1(i32 %tmp54) { } define void @test2() { - %tmp1 = call i64 asm "ldmia $1!, {$0, ${0:H}}", "=r,=*r,1"( i32** null, i32* null ) ; <i64> [#uses=2] - %tmp2 = lshr i64 %tmp1, 32 ; <i64> [#uses=1] - %tmp3 = trunc i64 %tmp2 to i32 ; <i32> [#uses=1] - %tmp4 = call i32 asm "pkhbt $0, $1, $2, lsl #16", "=r,r,r"( i32 0, i32 %tmp3 ) ; <i32> [#uses=0] - ret void -} - -define void @test3() { tail call void asm sideeffect "/* number: ${0:c} */", "i"( i32 1 ) ret void } diff --git a/test/CodeGen/ARM/inlineasm3.ll b/test/CodeGen/ARM/inlineasm3.ll index f062772..687e138 100644 --- a/test/CodeGen/ARM/inlineasm3.ll +++ b/test/CodeGen/ARM/inlineasm3.ll @@ -3,7 +3,7 @@ ; Radar 7449043 %struct.int32x4_t = type { <4 x i32> } -define arm_apcscc void @t() nounwind { +define void @t() nounwind { entry: ; CHECK: vmov.I64 q15, #0 ; CHECK: vmov.32 d30[0], r0 @@ -16,7 +16,7 @@ entry: ; Radar 7457110 %struct.int32x2_t = type { <4 x i32> } -define arm_apcscc void @t2() nounwind { +define void @t2() nounwind { entry: ; CHECK: vmov d30, d0 ; CHECK: vmov.32 r0, d30[0] diff --git a/test/CodeGen/ARM/insn-sched1.ll b/test/CodeGen/ARM/insn-sched1.ll index 59f0d53..1d32322 100644 --- a/test/CodeGen/ARM/insn-sched1.ll +++ b/test/CodeGen/ARM/insn-sched1.ll @@ -4,7 +4,7 @@ define i32 @test(i32 %x) { %tmp = trunc i32 %x to i16 ; <i16> [#uses=1] - %tmp2 = tail call i32 @f( i32 1, i16 %tmp ) ; <i32> [#uses=1] + %tmp2 = call i32 @f( i32 1, i16 %tmp ) ; <i32> [#uses=1] ret i32 %tmp2 } diff --git a/test/CodeGen/ARM/ldm.ll b/test/CodeGen/ARM/ldm.ll index 9a2dc82..78201a6 100644 --- a/test/CodeGen/ARM/ldm.ll +++ b/test/CodeGen/ARM/ldm.ll @@ -28,7 +28,7 @@ define i32 @t3() { %tmp = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 1) ; <i32> [#uses=1] %tmp3 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 2) ; <i32> [#uses=1] %tmp5 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 3) ; <i32> [#uses=1] - %tmp6 = tail call i32 @f2( i32 %tmp, i32 %tmp3, i32 %tmp5 ) ; <i32> [#uses=1] + %tmp6 = call i32 @f2( i32 %tmp, i32 %tmp3, i32 %tmp5 ) ; <i32> [#uses=1] ret i32 %tmp6 } diff --git a/test/CodeGen/ARM/long_shift.ll b/test/CodeGen/ARM/long_shift.ll index 76332cc..688b7bc 100644 --- a/test/CodeGen/ARM/long_shift.ll +++ b/test/CodeGen/ARM/long_shift.ll @@ -23,10 +23,10 @@ define i32 @f1(i64 %x, i64 %y) { define i32 @f2(i64 %x, i64 %y) { ; CHECK: f2 ; CHECK: mov r0, r0, lsr r2 -; CHECK-NEXT: rsb r12, r2, #32 +; CHECK-NEXT: rsb r3, r2, #32 ; CHECK-NEXT: sub r2, r2, #32 ; CHECK-NEXT: cmp r2, #0 -; CHECK-NEXT: orr r0, r0, r1, lsl r12 +; CHECK-NEXT: orr r0, r0, r1, lsl r3 ; CHECK-NEXT: movge r0, r1, asr r2 %a = ashr i64 %x, %y %b = trunc i64 %a to i32 @@ -36,10 +36,10 @@ define i32 @f2(i64 %x, i64 %y) { define i32 @f3(i64 %x, i64 %y) { ; CHECK: f3 ; CHECK: mov r0, r0, lsr r2 -; CHECK-NEXT: rsb r12, r2, #32 +; CHECK-NEXT: rsb r3, r2, #32 ; CHECK-NEXT: sub r2, r2, #32 ; CHECK-NEXT: cmp r2, #0 -; CHECK-NEXT: orr r0, r0, r1, lsl r12 +; CHECK-NEXT: orr r0, r0, r1, lsl r3 ; CHECK-NEXT: movge r0, r1, lsr r2 %a = lshr i64 %x, %y %b = trunc i64 %a to i32 diff --git a/test/CodeGen/ARM/lsr-code-insertion.ll b/test/CodeGen/ARM/lsr-code-insertion.ll index 1bbb96d..b8c543b 100644 --- a/test/CodeGen/ARM/lsr-code-insertion.ll +++ b/test/CodeGen/ARM/lsr-code-insertion.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -stats |& grep {39.*Number of machine instrs printed} +; RUN: llc < %s -stats |& grep {38.*Number of machine instrs printed} ; RUN: llc < %s -stats |& not grep {.*Number of re-materialization} ; This test really wants to check that the resultant "cond_true" block only ; has a single store in it, and that cond_true55 only has code to materialize diff --git a/test/CodeGen/ARM/lsr-on-unrolled-loops.ll b/test/CodeGen/ARM/lsr-on-unrolled-loops.ll index 2ac4084..25cf135 100644 --- a/test/CodeGen/ARM/lsr-on-unrolled-loops.ll +++ b/test/CodeGen/ARM/lsr-on-unrolled-loops.ll @@ -4,14 +4,14 @@ ; constant offset addressing, so that each of the following stores ; uses the same register. -; CHECK: vstr.32 s0, [r12, #-128] -; CHECK: vstr.32 s0, [r12, #-96] -; CHECK: vstr.32 s0, [r12, #-64] -; CHECK: vstr.32 s0, [r12, #-32] -; CHECK: vstr.32 s0, [r12] -; CHECK: vstr.32 s0, [r12, #32] -; CHECK: vstr.32 s0, [r12, #64] -; CHECK: vstr.32 s0, [r12, #96] +; CHECK: vstr.32 s0, [r9, #-128] +; CHECK: vstr.32 s0, [r9, #-96] +; CHECK: vstr.32 s0, [r9, #-64] +; CHECK: vstr.32 s0, [r9, #-32] +; CHECK: vstr.32 s0, [r9] +; CHECK: vstr.32 s0, [r9, #32] +; CHECK: vstr.32 s0, [r9, #64] +; CHECK: vstr.32 s0, [r9, #96] target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32-n32" @@ -40,7 +40,7 @@ target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32- %22 = type { void (%0*)*, void (%0*, i8***, i32, i8**, i32)* } %23 = type { void (%0*, i32)*, void (%0*, i8**, i8**, i32)*, void (%0*)*, void (%0*)* } -define arm_apcscc void @test(%0* nocapture %a0, %11* nocapture %a1, i16* nocapture %a2, i8** nocapture %a3, i32 %a4) nounwind { +define void @test(%0* nocapture %a0, %11* nocapture %a1, i16* nocapture %a2, i8** nocapture %a3, i32 %a4) nounwind { bb: %t = alloca [64 x float], align 4 %t5 = getelementptr inbounds %0* %a0, i32 0, i32 65 @@ -393,7 +393,7 @@ bb295: %struct.z_stream = type { i8*, i32, i32, i8*, i32, i32, i8*, %struct.internal_state*, i8* (i8*, i32, i32)*, void (i8*, i8*)*, i8*, i32, i32, i32 } %union.anon = type { i16 } -define arm_apcscc i32 @longest_match(%struct.internal_state* %s, i32 %cur_match) nounwind optsize { +define i32 @longest_match(%struct.internal_state* %s, i32 %cur_match) nounwind optsize { entry: %0 = getelementptr inbounds %struct.internal_state* %s, i32 0, i32 31 ; <i32*> [#uses=1] %1 = load i32* %0, align 4 ; <i32> [#uses=2] @@ -626,9 +626,11 @@ bb24: ; preds = %bb23 ; LSR should use count-down iteration to avoid requiring the trip count ; in a register, and it shouldn't require any reloads here. -; CHECK: sub.w r9, r9, #1 -; CHECK-NEXT: cmp.w r9, #0 -; CHECK-NEXT: bne.w +; CHECK: @ %bb24 +; CHECK-NEXT: @ in Loop: Header=BB1_1 Depth=1 +; CHECK-NEXT: sub{{.*}} [[REGISTER:r[0-9]+]], #1 +; CHECK-NEXT: cmp{{.*}} [[REGISTER]], #0 +; CHECK-NEXT: bne.w %92 = icmp eq i32 %tmp81, %indvar78 ; <i1> [#uses=1] %indvar.next79 = add i32 %indvar78, 1 ; <i32> [#uses=1] diff --git a/test/CodeGen/ARM/machine-cse-cmp.ll b/test/CodeGen/ARM/machine-cse-cmp.ll new file mode 100644 index 0000000..c77402f --- /dev/null +++ b/test/CodeGen/ARM/machine-cse-cmp.ll @@ -0,0 +1,18 @@ +; RUN: llc < %s -march=arm | FileCheck %s +;rdar://8003725 + +@G1 = external global i32 +@G2 = external global i32 + +define i32 @f1(i32 %cond1, i32 %x1, i32 %x2, i32 %x3) { +entry: +; CHECK: cmp +; CHECK: moveq +; CHECK-NOT: cmp +; CHECK: moveq + %tmp1 = icmp eq i32 %cond1, 0 + %tmp2 = select i1 %tmp1, i32 %x1, i32 %x2 + %tmp3 = select i1 %tmp1, i32 %x2, i32 %x3 + %tmp4 = add i32 %tmp2, %tmp3 + ret i32 %tmp4 +} diff --git a/test/CodeGen/ARM/reg_sequence.ll b/test/CodeGen/ARM/reg_sequence.ll index 3ba82cc..9e365c9 100644 --- a/test/CodeGen/ARM/reg_sequence.ll +++ b/test/CodeGen/ARM/reg_sequence.ll @@ -8,7 +8,7 @@ %struct.__neon_int16x8x2_t = type { <8 x i16>, <8 x i16> } %struct.__neon_int32x4x2_t = type { <4 x i32>, <4 x i32> } -define arm_apcscc void @t1(i16* %i_ptr, i16* %o_ptr, %struct.int32x4_t* nocapture %vT0ptr, %struct.int32x4_t* nocapture %vT1ptr) nounwind { +define void @t1(i16* %i_ptr, i16* %o_ptr, %struct.int32x4_t* nocapture %vT0ptr, %struct.int32x4_t* nocapture %vT1ptr) nounwind { entry: ; CHECK: t1: ; CHECK: vld1.16 @@ -41,13 +41,13 @@ entry: ret void } -define arm_apcscc void @t2(i16* %i_ptr, i16* %o_ptr, %struct.int16x8_t* nocapture %vT0ptr, %struct.int16x8_t* nocapture %vT1ptr) nounwind { +define void @t2(i16* %i_ptr, i16* %o_ptr, %struct.int16x8_t* nocapture %vT0ptr, %struct.int16x8_t* nocapture %vT1ptr) nounwind { entry: ; CHECK: t2: ; CHECK: vld1.16 -; CHECK: vld1.16 -; CHECK-NOT: vmov ; CHECK: vmul.i16 +; CHECK-NOT: vmov +; CHECK: vld1.16 ; CHECK: vmul.i16 ; CHECK-NOT: vmov ; CHECK: vst1.16 @@ -88,7 +88,7 @@ define <8 x i8> @t3(i8* %A, i8* %B) nounwind { ret <8 x i8> %tmp4 } -define arm_apcscc void @t4(i32* %in, i32* %out) nounwind { +define void @t4(i32* %in, i32* %out) nounwind { entry: ; CHECK: t4: ; CHECK: vld2.32 @@ -163,7 +163,7 @@ define <8 x i8> @t6(i8* %A, <8 x i8>* %B) nounwind { ret <8 x i8> %tmp5 } -define arm_apcscc void @t7(i32* %iptr, i32* %optr) nounwind { +define void @t7(i32* %iptr, i32* %optr) nounwind { entry: ; CHECK: t7: ; CHECK: vld2.32 @@ -238,9 +238,10 @@ bb14: ; preds = %bb6 define arm_aapcs_vfpcc float @t9(%0* nocapture, %3* nocapture) nounwind { ; CHECK: t9: ; CHECK: vldr.64 +; CHECK-NOT: vmov d{{.*}}, d0 ; CHECK: vmov.i8 d1 -; CHECK-NEXT: vstmia r0, {d2,d3} -; CHECK-NEXT: vstmia r0, {d0,d1} +; CHECK-NEXT: vstmia r0, {d0, d1} +; CHECK-NEXT: vstmia r0, {d0, d1} %3 = bitcast double 0.000000e+00 to <2 x float> ; <<2 x float>> [#uses=2] %4 = shufflevector <2 x float> %3, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> ; <<4 x float>> [#uses=1] store <4 x float> %4, <4 x float>* undef, align 16 @@ -249,13 +250,13 @@ define arm_aapcs_vfpcc float @t9(%0* nocapture, %3* nocapture) nounwind { br label %8 ; <label>:6 ; preds = %8 - br i1 undef, label %7, label %10 + br label %7 ; <label>:7 ; preds = %6 br label %8 ; <label>:8 ; preds = %7, %2 - br i1 undef, label %6, label %9 + br label %6 ; <label>:9 ; preds = %8 ret float undef @@ -269,7 +270,6 @@ define arm_aapcs_vfpcc i32 @t10() nounwind { entry: ; CHECK: t10: ; CHECK: vmov.i32 q1, #0x3F000000 -; CHECK: vdup.32 q0, d0[0] ; CHECK: vmov d0, d1 ; CHECK: vmla.f32 q0, q0, d0[0] %0 = shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>> [#uses=1] diff --git a/test/CodeGen/ARM/remat.ll b/test/CodeGen/ARM/remat.ll index 92c1cf1..1e780e6 100644 --- a/test/CodeGen/ARM/remat.ll +++ b/test/CodeGen/ARM/remat.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -march=arm -mattr=+v6,+vfp2 -stats -info-output-file - | grep "Number of re-materialization" -define arm_apcscc i32 @main(i32 %argc, i8** nocapture %argv, double %d1, double %d2) nounwind { +define i32 @main(i32 %argc, i8** nocapture %argv, double %d1, double %d2) nounwind { entry: br i1 undef, label %smvp.exit, label %bb.i3 @@ -25,7 +25,7 @@ bb142: ; preds = %bb.nph218.bb.nph218 br i1 %14, label %phi1.exit, label %bb.i35 bb.i35: ; preds = %bb142 - %5 = call arm_apcscc double @sin(double %15) nounwind readonly ; <double> [#uses=1] + %5 = call double @sin(double %15) nounwind readonly ; <double> [#uses=1] %6 = fmul double %5, 0x4031740AFA84AD8A ; <double> [#uses=1] %7 = fsub double 1.000000e+00, undef ; <double> [#uses=1] %8 = fdiv double %7, 6.000000e-01 ; <double> [#uses=1] @@ -62,4 +62,4 @@ bb166: ; preds = %bb127 unreachable } -declare arm_apcscc double @sin(double) nounwind readonly +declare double @sin(double) nounwind readonly diff --git a/test/CodeGen/ARM/select-imm.ll b/test/CodeGen/ARM/select-imm.ll index 07edc91..6e15fde 100644 --- a/test/CodeGen/ARM/select-imm.ll +++ b/test/CodeGen/ARM/select-imm.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=arm | FileCheck %s --check-prefix=ARM ; RUN: llc < %s -march=arm -mattr=+thumb2 | FileCheck %s --check-prefix=T2 -define arm_apcscc i32 @t1(i32 %c) nounwind readnone { +define i32 @t1(i32 %c) nounwind readnone { entry: ; ARM: t1: ; ARM: mov r1, #101 @@ -17,7 +17,7 @@ entry: ret i32 %1 } -define arm_apcscc i32 @t2(i32 %c) nounwind readnone { +define i32 @t2(i32 %c) nounwind readnone { entry: ; ARM: t2: ; ARM: mov r1, #101 @@ -33,7 +33,7 @@ entry: ret i32 %1 } -define arm_apcscc i32 @t3(i32 %a) nounwind readnone { +define i32 @t3(i32 %a) nounwind readnone { entry: ; ARM: t3: ; ARM: mov r0, #0 diff --git a/test/CodeGen/ARM/spill-q.ll b/test/CodeGen/ARM/spill-q.ll index 03de0c8..792ef79 100644 --- a/test/CodeGen/ARM/spill-q.ll +++ b/test/CodeGen/ARM/spill-q.ll @@ -9,7 +9,7 @@ declare <4 x float> @llvm.arm.neon.vld1.v4f32(i8*) nounwind readonly -define arm_apcscc void @aaa(%quuz* %this, i8* %block) { +define void @aaa(%quuz* %this, i8* %block) { ; CHECK: aaa: ; CHECK: bic sp, sp, #15 ; CHECK: vst1.64 {{.*}}sp, :128 diff --git a/test/CodeGen/ARM/trap.ll b/test/CodeGen/ARM/trap.ll index 763dff3..b2f6b6e 100644 --- a/test/CodeGen/ARM/trap.ll +++ b/test/CodeGen/ARM/trap.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=arm | FileCheck %s ; rdar://7961298 -define arm_apcscc void @t() nounwind { +define void @t() nounwind { entry: ; CHECK: t: ; CHECK: trap diff --git a/test/CodeGen/ARM/unaligned_load_store.ll b/test/CodeGen/ARM/unaligned_load_store.ll index a4494f3..e279491 100644 --- a/test/CodeGen/ARM/unaligned_load_store.ll +++ b/test/CodeGen/ARM/unaligned_load_store.ll @@ -4,7 +4,7 @@ ; rdar://7113725 -define arm_apcscc void @t(i8* nocapture %a, i8* nocapture %b) nounwind { +define void @t(i8* nocapture %a, i8* nocapture %b) nounwind { entry: ; GENERIC: t: ; GENERIC: ldrb r2 diff --git a/test/CodeGen/ARM/va_arg.ll b/test/CodeGen/ARM/va_arg.ll new file mode 100644 index 0000000..7cb9762 --- /dev/null +++ b/test/CodeGen/ARM/va_arg.ll @@ -0,0 +1,41 @@ +; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi | FileCheck %s +; Test that we correctly align elements when using va_arg + +; CHECK: test1: +; CHECK-NOT: bfc +; CHECK: add r0, r0, #7 +; CHECK: bfc r0, #0, #3 +; CHECK-NOT: bfc + +define i64 @test1(i32 %i, ...) nounwind optsize { +entry: + %g = alloca i8*, align 4 + %g1 = bitcast i8** %g to i8* + call void @llvm.va_start(i8* %g1) + %0 = va_arg i8** %g, i64 + call void @llvm.va_end(i8* %g1) + ret i64 %0 +} + +; CHECK: test2: +; CHECK-NOT: bfc +; CHECK: add r0, r0, #7 +; CHECK: bfc r0, #0, #3 +; CHECK-NOT: bfc +; CHECK: bx lr + +define double @test2(i32 %a, i32 %b, ...) nounwind optsize { +entry: + %ap = alloca i8*, align 4 ; <i8**> [#uses=3] + %ap1 = bitcast i8** %ap to i8* ; <i8*> [#uses=2] + call void @llvm.va_start(i8* %ap1) + %0 = va_arg i8** %ap, i32 ; <i32> [#uses=0] + %1 = va_arg i8** %ap, double ; <double> [#uses=1] + call void @llvm.va_end(i8* %ap1) + ret double %1 +} + + +declare void @llvm.va_start(i8*) nounwind + +declare void @llvm.va_end(i8*) nounwind diff --git a/test/CodeGen/ARM/vdup.ll b/test/CodeGen/ARM/vdup.ll index c9a68ca..50e4df9 100644 --- a/test/CodeGen/ARM/vdup.ll +++ b/test/CodeGen/ARM/vdup.ll @@ -244,25 +244,25 @@ define <4 x float> @vduplaneQfloat(<2 x float>* %A) nounwind { ret <4 x float> %tmp2 } -define arm_apcscc <2 x i64> @foo(<2 x i64> %arg0_int64x1_t) nounwind readnone { +define <2 x i64> @foo(<2 x i64> %arg0_int64x1_t) nounwind readnone { entry: %0 = shufflevector <2 x i64> %arg0_int64x1_t, <2 x i64> undef, <2 x i32> <i32 1, i32 1> ret <2 x i64> %0 } -define arm_apcscc <2 x i64> @bar(<2 x i64> %arg0_int64x1_t) nounwind readnone { +define <2 x i64> @bar(<2 x i64> %arg0_int64x1_t) nounwind readnone { entry: %0 = shufflevector <2 x i64> %arg0_int64x1_t, <2 x i64> undef, <2 x i32> <i32 0, i32 0> ret <2 x i64> %0 } -define arm_apcscc <2 x double> @baz(<2 x double> %arg0_int64x1_t) nounwind readnone { +define <2 x double> @baz(<2 x double> %arg0_int64x1_t) nounwind readnone { entry: %0 = shufflevector <2 x double> %arg0_int64x1_t, <2 x double> undef, <2 x i32> <i32 1, i32 1> ret <2 x double> %0 } -define arm_apcscc <2 x double> @qux(<2 x double> %arg0_int64x1_t) nounwind readnone { +define <2 x double> @qux(<2 x double> %arg0_int64x1_t) nounwind readnone { entry: %0 = shufflevector <2 x double> %arg0_int64x1_t, <2 x double> undef, <2 x i32> <i32 0, i32 0> ret <2 x double> %0 diff --git a/test/CodeGen/ARM/vext.ll b/test/CodeGen/ARM/vext.ll index 20d953b..c11a67c 100644 --- a/test/CodeGen/ARM/vext.ll +++ b/test/CodeGen/ARM/vext.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -define arm_apcscc <8 x i8> @test_vextd(<8 x i8>* %A, <8 x i8>* %B) nounwind { +define <8 x i8> @test_vextd(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK: test_vextd: ;CHECK: vext %tmp1 = load <8 x i8>* %A @@ -9,7 +9,7 @@ define arm_apcscc <8 x i8> @test_vextd(<8 x i8>* %A, <8 x i8>* %B) nounwind { ret <8 x i8> %tmp3 } -define arm_apcscc <8 x i8> @test_vextRd(<8 x i8>* %A, <8 x i8>* %B) nounwind { +define <8 x i8> @test_vextRd(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK: test_vextRd: ;CHECK: vext %tmp1 = load <8 x i8>* %A @@ -18,7 +18,7 @@ define arm_apcscc <8 x i8> @test_vextRd(<8 x i8>* %A, <8 x i8>* %B) nounwind { ret <8 x i8> %tmp3 } -define arm_apcscc <16 x i8> @test_vextq(<16 x i8>* %A, <16 x i8>* %B) nounwind { +define <16 x i8> @test_vextq(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK: test_vextq: ;CHECK: vext %tmp1 = load <16 x i8>* %A @@ -27,7 +27,7 @@ define arm_apcscc <16 x i8> @test_vextq(<16 x i8>* %A, <16 x i8>* %B) nounwind { ret <16 x i8> %tmp3 } -define arm_apcscc <16 x i8> @test_vextRq(<16 x i8>* %A, <16 x i8>* %B) nounwind { +define <16 x i8> @test_vextRq(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK: test_vextRq: ;CHECK: vext %tmp1 = load <16 x i8>* %A @@ -36,7 +36,7 @@ define arm_apcscc <16 x i8> @test_vextRq(<16 x i8>* %A, <16 x i8>* %B) nounwind ret <16 x i8> %tmp3 } -define arm_apcscc <4 x i16> @test_vextd16(<4 x i16>* %A, <4 x i16>* %B) nounwind { +define <4 x i16> @test_vextd16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK: test_vextd16: ;CHECK: vext %tmp1 = load <4 x i16>* %A @@ -45,7 +45,7 @@ define arm_apcscc <4 x i16> @test_vextd16(<4 x i16>* %A, <4 x i16>* %B) nounwind ret <4 x i16> %tmp3 } -define arm_apcscc <4 x i32> @test_vextq32(<4 x i32>* %A, <4 x i32>* %B) nounwind { +define <4 x i32> @test_vextq32(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK: test_vextq32: ;CHECK: vext %tmp1 = load <4 x i32>* %A diff --git a/test/CodeGen/ARM/vget_lane.ll b/test/CodeGen/ARM/vget_lane.ll index 5dd87d6..05e7f50 100644 --- a/test/CodeGen/ARM/vget_lane.ll +++ b/test/CodeGen/ARM/vget_lane.ll @@ -204,8 +204,8 @@ define <4 x i32> @vsetQ_lane32(<4 x i32>* %A, i32 %B) nounwind { define arm_aapcs_vfpcc <2 x float> @test_vset_lanef32(float %arg0_float32_t, <2 x float> %arg1_float32x2_t) nounwind { ;CHECK: test_vset_lanef32: -;CHECK: vmov.f32 -;CHECK: vmov.f32 +;CHECK: vmov.f32 s3, s0 +;CHECK: vmov.f64 d0, d1 entry: %0 = insertelement <2 x float> %arg1_float32x2_t, float %arg0_float32_t, i32 1 ; <<2 x float>> [#uses=1] ret <2 x float> %0 diff --git a/test/CodeGen/ARM/vmov.ll b/test/CodeGen/ARM/vmov.ll index e4368d6..f803018 100644 --- a/test/CodeGen/ARM/vmov.ll +++ b/test/CodeGen/ARM/vmov.ll @@ -2,141 +2,127 @@ define <8 x i8> @v_movi8() nounwind { ;CHECK: v_movi8: -;CHECK: vmov.i8 +;CHECK: vmov.i8 d0, #0x8 ret <8 x i8> < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 > } define <4 x i16> @v_movi16a() nounwind { ;CHECK: v_movi16a: -;CHECK: vmov.i16 +;CHECK: vmov.i16 d0, #0x10 ret <4 x i16> < i16 16, i16 16, i16 16, i16 16 > } -; 0x1000 = 4096 define <4 x i16> @v_movi16b() nounwind { ;CHECK: v_movi16b: -;CHECK: vmov.i16 +;CHECK: vmov.i16 d0, #0x1000 ret <4 x i16> < i16 4096, i16 4096, i16 4096, i16 4096 > } define <2 x i32> @v_movi32a() nounwind { ;CHECK: v_movi32a: -;CHECK: vmov.i32 +;CHECK: vmov.i32 d0, #0x20 ret <2 x i32> < i32 32, i32 32 > } -; 0x2000 = 8192 define <2 x i32> @v_movi32b() nounwind { ;CHECK: v_movi32b: -;CHECK: vmov.i32 +;CHECK: vmov.i32 d0, #0x2000 ret <2 x i32> < i32 8192, i32 8192 > } -; 0x200000 = 2097152 define <2 x i32> @v_movi32c() nounwind { ;CHECK: v_movi32c: -;CHECK: vmov.i32 +;CHECK: vmov.i32 d0, #0x200000 ret <2 x i32> < i32 2097152, i32 2097152 > } -; 0x20000000 = 536870912 define <2 x i32> @v_movi32d() nounwind { ;CHECK: v_movi32d: -;CHECK: vmov.i32 +;CHECK: vmov.i32 d0, #0x20000000 ret <2 x i32> < i32 536870912, i32 536870912 > } -; 0x20ff = 8447 define <2 x i32> @v_movi32e() nounwind { ;CHECK: v_movi32e: -;CHECK: vmov.i32 +;CHECK: vmov.i32 d0, #0x20FF ret <2 x i32> < i32 8447, i32 8447 > } -; 0x20ffff = 2162687 define <2 x i32> @v_movi32f() nounwind { ;CHECK: v_movi32f: -;CHECK: vmov.i32 +;CHECK: vmov.i32 d0, #0x20FFFF ret <2 x i32> < i32 2162687, i32 2162687 > } -; 0xff0000ff0000ffff = 18374687574888349695 define <1 x i64> @v_movi64() nounwind { ;CHECK: v_movi64: -;CHECK: vmov.i64 +;CHECK: vmov.i64 d0, #0xFF0000FF0000FFFF ret <1 x i64> < i64 18374687574888349695 > } define <16 x i8> @v_movQi8() nounwind { ;CHECK: v_movQi8: -;CHECK: vmov.i8 +;CHECK: vmov.i8 q0, #0x8 ret <16 x i8> < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 > } define <8 x i16> @v_movQi16a() nounwind { ;CHECK: v_movQi16a: -;CHECK: vmov.i16 +;CHECK: vmov.i16 q0, #0x10 ret <8 x i16> < i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16 > } -; 0x1000 = 4096 define <8 x i16> @v_movQi16b() nounwind { ;CHECK: v_movQi16b: -;CHECK: vmov.i16 +;CHECK: vmov.i16 q0, #0x1000 ret <8 x i16> < i16 4096, i16 4096, i16 4096, i16 4096, i16 4096, i16 4096, i16 4096, i16 4096 > } define <4 x i32> @v_movQi32a() nounwind { ;CHECK: v_movQi32a: -;CHECK: vmov.i32 +;CHECK: vmov.i32 q0, #0x20 ret <4 x i32> < i32 32, i32 32, i32 32, i32 32 > } -; 0x2000 = 8192 define <4 x i32> @v_movQi32b() nounwind { ;CHECK: v_movQi32b: -;CHECK: vmov.i32 +;CHECK: vmov.i32 q0, #0x2000 ret <4 x i32> < i32 8192, i32 8192, i32 8192, i32 8192 > } -; 0x200000 = 2097152 define <4 x i32> @v_movQi32c() nounwind { ;CHECK: v_movQi32c: -;CHECK: vmov.i32 +;CHECK: vmov.i32 q0, #0x200000 ret <4 x i32> < i32 2097152, i32 2097152, i32 2097152, i32 2097152 > } -; 0x20000000 = 536870912 define <4 x i32> @v_movQi32d() nounwind { ;CHECK: v_movQi32d: -;CHECK: vmov.i32 +;CHECK: vmov.i32 q0, #0x20000000 ret <4 x i32> < i32 536870912, i32 536870912, i32 536870912, i32 536870912 > } -; 0x20ff = 8447 define <4 x i32> @v_movQi32e() nounwind { ;CHECK: v_movQi32e: -;CHECK: vmov.i32 +;CHECK: vmov.i32 q0, #0x20FF ret <4 x i32> < i32 8447, i32 8447, i32 8447, i32 8447 > } -; 0x20ffff = 2162687 define <4 x i32> @v_movQi32f() nounwind { ;CHECK: v_movQi32f: -;CHECK: vmov.i32 +;CHECK: vmov.i32 q0, #0x20FFFF ret <4 x i32> < i32 2162687, i32 2162687, i32 2162687, i32 2162687 > } -; 0xff0000ff0000ffff = 18374687574888349695 define <2 x i64> @v_movQi64() nounwind { ;CHECK: v_movQi64: -;CHECK: vmov.i64 +;CHECK: vmov.i64 q0, #0xFF0000FF0000FFFF ret <2 x i64> < i64 18374687574888349695, i64 18374687574888349695 > } ; Check for correct assembler printing for immediate values. %struct.int8x8_t = type { <8 x i8> } -define arm_apcscc void @vdupn128(%struct.int8x8_t* noalias nocapture sret %agg.result) nounwind { +define void @vdupn128(%struct.int8x8_t* noalias nocapture sret %agg.result) nounwind { entry: ;CHECK: vdupn128: ;CHECK: vmov.i8 d0, #0x80 @@ -145,7 +131,7 @@ entry: ret void } -define arm_apcscc void @vdupnneg75(%struct.int8x8_t* noalias nocapture sret %agg.result) nounwind { +define void @vdupnneg75(%struct.int8x8_t* noalias nocapture sret %agg.result) nounwind { entry: ;CHECK: vdupnneg75: ;CHECK: vmov.i8 d0, #0xB5 diff --git a/test/CodeGen/ARM/vrev.ll b/test/CodeGen/ARM/vrev.ll index f0a04a4..deed554 100644 --- a/test/CodeGen/ARM/vrev.ll +++ b/test/CodeGen/ARM/vrev.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -define arm_apcscc <8 x i8> @test_vrev64D8(<8 x i8>* %A) nounwind { +define <8 x i8> @test_vrev64D8(<8 x i8>* %A) nounwind { ;CHECK: test_vrev64D8: ;CHECK: vrev64.8 %tmp1 = load <8 x i8>* %A @@ -8,7 +8,7 @@ define arm_apcscc <8 x i8> @test_vrev64D8(<8 x i8>* %A) nounwind { ret <8 x i8> %tmp2 } -define arm_apcscc <4 x i16> @test_vrev64D16(<4 x i16>* %A) nounwind { +define <4 x i16> @test_vrev64D16(<4 x i16>* %A) nounwind { ;CHECK: test_vrev64D16: ;CHECK: vrev64.16 %tmp1 = load <4 x i16>* %A @@ -16,7 +16,7 @@ define arm_apcscc <4 x i16> @test_vrev64D16(<4 x i16>* %A) nounwind { ret <4 x i16> %tmp2 } -define arm_apcscc <2 x i32> @test_vrev64D32(<2 x i32>* %A) nounwind { +define <2 x i32> @test_vrev64D32(<2 x i32>* %A) nounwind { ;CHECK: test_vrev64D32: ;CHECK: vrev64.32 %tmp1 = load <2 x i32>* %A @@ -24,7 +24,7 @@ define arm_apcscc <2 x i32> @test_vrev64D32(<2 x i32>* %A) nounwind { ret <2 x i32> %tmp2 } -define arm_apcscc <2 x float> @test_vrev64Df(<2 x float>* %A) nounwind { +define <2 x float> @test_vrev64Df(<2 x float>* %A) nounwind { ;CHECK: test_vrev64Df: ;CHECK: vrev64.32 %tmp1 = load <2 x float>* %A @@ -32,7 +32,7 @@ define arm_apcscc <2 x float> @test_vrev64Df(<2 x float>* %A) nounwind { ret <2 x float> %tmp2 } -define arm_apcscc <16 x i8> @test_vrev64Q8(<16 x i8>* %A) nounwind { +define <16 x i8> @test_vrev64Q8(<16 x i8>* %A) nounwind { ;CHECK: test_vrev64Q8: ;CHECK: vrev64.8 %tmp1 = load <16 x i8>* %A @@ -40,7 +40,7 @@ define arm_apcscc <16 x i8> @test_vrev64Q8(<16 x i8>* %A) nounwind { ret <16 x i8> %tmp2 } -define arm_apcscc <8 x i16> @test_vrev64Q16(<8 x i16>* %A) nounwind { +define <8 x i16> @test_vrev64Q16(<8 x i16>* %A) nounwind { ;CHECK: test_vrev64Q16: ;CHECK: vrev64.16 %tmp1 = load <8 x i16>* %A @@ -48,7 +48,7 @@ define arm_apcscc <8 x i16> @test_vrev64Q16(<8 x i16>* %A) nounwind { ret <8 x i16> %tmp2 } -define arm_apcscc <4 x i32> @test_vrev64Q32(<4 x i32>* %A) nounwind { +define <4 x i32> @test_vrev64Q32(<4 x i32>* %A) nounwind { ;CHECK: test_vrev64Q32: ;CHECK: vrev64.32 %tmp1 = load <4 x i32>* %A @@ -56,7 +56,7 @@ define arm_apcscc <4 x i32> @test_vrev64Q32(<4 x i32>* %A) nounwind { ret <4 x i32> %tmp2 } -define arm_apcscc <4 x float> @test_vrev64Qf(<4 x float>* %A) nounwind { +define <4 x float> @test_vrev64Qf(<4 x float>* %A) nounwind { ;CHECK: test_vrev64Qf: ;CHECK: vrev64.32 %tmp1 = load <4 x float>* %A @@ -64,7 +64,7 @@ define arm_apcscc <4 x float> @test_vrev64Qf(<4 x float>* %A) nounwind { ret <4 x float> %tmp2 } -define arm_apcscc <8 x i8> @test_vrev32D8(<8 x i8>* %A) nounwind { +define <8 x i8> @test_vrev32D8(<8 x i8>* %A) nounwind { ;CHECK: test_vrev32D8: ;CHECK: vrev32.8 %tmp1 = load <8 x i8>* %A @@ -72,7 +72,7 @@ define arm_apcscc <8 x i8> @test_vrev32D8(<8 x i8>* %A) nounwind { ret <8 x i8> %tmp2 } -define arm_apcscc <4 x i16> @test_vrev32D16(<4 x i16>* %A) nounwind { +define <4 x i16> @test_vrev32D16(<4 x i16>* %A) nounwind { ;CHECK: test_vrev32D16: ;CHECK: vrev32.16 %tmp1 = load <4 x i16>* %A @@ -80,7 +80,7 @@ define arm_apcscc <4 x i16> @test_vrev32D16(<4 x i16>* %A) nounwind { ret <4 x i16> %tmp2 } -define arm_apcscc <16 x i8> @test_vrev32Q8(<16 x i8>* %A) nounwind { +define <16 x i8> @test_vrev32Q8(<16 x i8>* %A) nounwind { ;CHECK: test_vrev32Q8: ;CHECK: vrev32.8 %tmp1 = load <16 x i8>* %A @@ -88,7 +88,7 @@ define arm_apcscc <16 x i8> @test_vrev32Q8(<16 x i8>* %A) nounwind { ret <16 x i8> %tmp2 } -define arm_apcscc <8 x i16> @test_vrev32Q16(<8 x i16>* %A) nounwind { +define <8 x i16> @test_vrev32Q16(<8 x i16>* %A) nounwind { ;CHECK: test_vrev32Q16: ;CHECK: vrev32.16 %tmp1 = load <8 x i16>* %A @@ -96,7 +96,7 @@ define arm_apcscc <8 x i16> @test_vrev32Q16(<8 x i16>* %A) nounwind { ret <8 x i16> %tmp2 } -define arm_apcscc <8 x i8> @test_vrev16D8(<8 x i8>* %A) nounwind { +define <8 x i8> @test_vrev16D8(<8 x i8>* %A) nounwind { ;CHECK: test_vrev16D8: ;CHECK: vrev16.8 %tmp1 = load <8 x i8>* %A @@ -104,7 +104,7 @@ define arm_apcscc <8 x i8> @test_vrev16D8(<8 x i8>* %A) nounwind { ret <8 x i8> %tmp2 } -define arm_apcscc <16 x i8> @test_vrev16Q8(<16 x i8>* %A) nounwind { +define <16 x i8> @test_vrev16Q8(<16 x i8>* %A) nounwind { ;CHECK: test_vrev16Q8: ;CHECK: vrev16.8 %tmp1 = load <16 x i8>* %A |
