diff options
Diffstat (limited to 'sys')
237 files changed, 7910 insertions, 4707 deletions
diff --git a/sys/amd64/acpica/acpi_machdep.c b/sys/amd64/acpica/acpi_machdep.c index f57bdc2..e5dd4c3 100644 --- a/sys/amd64/acpica/acpi_machdep.c +++ b/sys/amd64/acpica/acpi_machdep.c @@ -122,7 +122,7 @@ table_map(vm_paddr_t pa, int offset, vm_offset_t length) void *data; off = pa & PAGE_MASK; - length = roundup(length + off, PAGE_SIZE); + length = round_page(length + off); pa = pa & PG_FRAME; va = (vm_offset_t)pmap_kenter_temporary(pa, offset) + (offset * PAGE_SIZE); @@ -146,7 +146,7 @@ table_unmap(void *data, vm_offset_t length) va = (vm_offset_t)data; off = va & PAGE_MASK; - length = roundup(length + off, PAGE_SIZE); + length = round_page(length + off); va &= ~PAGE_MASK; while (length > 0) { pmap_kremove(va); diff --git a/sys/amd64/amd64/pmap.c b/sys/amd64/amd64/pmap.c index 715865f..5636cfe 100644 --- a/sys/amd64/amd64/pmap.c +++ b/sys/amd64/amd64/pmap.c @@ -5078,7 +5078,7 @@ pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode) return ((void *)va); } offset = pa & PAGE_MASK; - size = roundup(offset + size, PAGE_SIZE); + size = round_page(offset + size); va = kmem_alloc_nofault(kernel_map, size); if (!va) panic("pmap_mapdev: Couldn't alloc kernel virtual memory"); @@ -5114,7 +5114,7 @@ pmap_unmapdev(vm_offset_t va, vm_size_t size) return; base = trunc_page(va); offset = va & PAGE_MASK; - size = roundup(offset + size, PAGE_SIZE); + size = round_page(offset + size); kmem_free(kernel_map, base, size); } @@ -5236,7 +5236,7 @@ pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode) PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED); base = trunc_page(va); offset = va & PAGE_MASK; - size = roundup(offset + size, PAGE_SIZE); + size = round_page(offset + size); /* * Only supported on kernel virtual addresses, including the direct diff --git a/sys/amd64/include/elf.h b/sys/amd64/include/elf.h index d69c6b4..f932377 100644 --- a/sys/amd64/include/elf.h +++ b/sys/amd64/include/elf.h @@ -1,124 +1,6 @@ /*- - * Copyright (c) 1996-1997 John D. Polstra. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * $FreeBSD$ + * This file is in the public domain. */ +/* $FreeBSD$ */ -#ifndef _MACHINE_ELF_H_ -#define _MACHINE_ELF_H_ 1 - -/* - * ELF definitions for the AMD64 architecture. - */ - - -#ifndef __ELF_WORD_SIZE -#define __ELF_WORD_SIZE 64 /* Used by <sys/elf_generic.h> */ -#endif -#include <sys/elf32.h> /* Definitions common to all 32 bit architectures. */ -#include <sys/elf64.h> /* Definitions common to all 64 bit architectures. */ -#include <sys/elf_generic.h> - -#define ELF_ARCH EM_X86_64 -#define ELF_ARCH32 EM_386 - -#define ELF_MACHINE_OK(x) ((x) == EM_X86_64) - -/* - * Auxiliary vector entries for passing information to the interpreter. - * - * The i386 supplement to the SVR4 ABI specification names this "auxv_t", - * but POSIX lays claim to all symbols ending with "_t". - */ -typedef struct { /* Auxiliary vector entry on initial stack */ - int a_type; /* Entry type. */ - union { - int a_val; /* Integer value. */ - } a_un; -} Elf32_Auxinfo; - - -typedef struct { /* Auxiliary vector entry on initial stack */ - long a_type; /* Entry type. */ - union { - long a_val; /* Integer value. */ - void *a_ptr; /* Address. */ - void (*a_fcn)(void); /* Function pointer (not used). */ - } a_un; -} Elf64_Auxinfo; - -__ElfType(Auxinfo); - -/* Values for a_type. */ -#define AT_NULL 0 /* Terminates the vector. */ -#define AT_IGNORE 1 /* Ignored entry. */ -#define AT_EXECFD 2 /* File descriptor of program to load. */ -#define AT_PHDR 3 /* Program header of program already loaded. */ -#define AT_PHENT 4 /* Size of each program header entry. */ -#define AT_PHNUM 5 /* Number of program header entries. */ -#define AT_PAGESZ 6 /* Page size in bytes. */ -#define AT_BASE 7 /* Interpreter's base address. */ -#define AT_FLAGS 8 /* Flags (unused for i386). */ -#define AT_ENTRY 9 /* Where interpreter should transfer control. */ -#define AT_NOTELF 10 /* Program is not ELF ?? */ -#define AT_UID 11 /* Real uid. */ -#define AT_EUID 12 /* Effective uid. */ -#define AT_GID 13 /* Real gid. */ -#define AT_EGID 14 /* Effective gid. */ -#define AT_EXECPATH 15 /* Path to the executable. */ -#define AT_CANARY 16 /* Canary for SSP */ -#define AT_CANARYLEN 17 /* Length of the canary. */ -#define AT_OSRELDATE 18 /* OSRELDATE. */ -#define AT_NCPUS 19 /* Number of CPUs. */ -#define AT_PAGESIZES 20 /* Pagesizes. */ -#define AT_PAGESIZESLEN 21 /* Number of pagesizes. */ -#define AT_TIMEKEEP 22 /* Pointer to timehands. */ -#define AT_STACKPROT 23 /* Initial stack protection. */ - -#define AT_COUNT 24 /* Count of defined aux entry types. */ - -/* - * Relocation types. - */ - -#define R_X86_64_COUNT 24 /* Count of defined relocation types. */ - -/* Define "machine" characteristics */ -#if __ELF_WORD_SIZE == 32 -#define ELF_TARG_CLASS ELFCLASS32 -#else -#define ELF_TARG_CLASS ELFCLASS64 -#endif -#define ELF_TARG_DATA ELFDATA2LSB -#define ELF_TARG_MACH EM_X86_64 -#define ELF_TARG_VER 1 - -#if __ELF_WORD_SIZE == 32 -#define ET_DYN_LOAD_ADDR 0x01001000 -#else -#define ET_DYN_LOAD_ADDR 0x01021000 -#endif - -#endif /* !_MACHINE_ELF_H_ */ +#include <x86/elf.h> diff --git a/sys/amd64/include/frame.h b/sys/amd64/include/frame.h index e171407..0953be7 100644 --- a/sys/amd64/include/frame.h +++ b/sys/amd64/include/frame.h @@ -1,87 +1,6 @@ /*- - * Copyright (c) 2003 Peter Wemm. - * Copyright (c) 1990 The Regents of the University of California. - * All rights reserved. - * - * This code is derived from software contributed to Berkeley by - * William Jolitz. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 4. Neither the name of the University nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * from: @(#)frame.h 5.2 (Berkeley) 1/18/91 - * $FreeBSD$ + * This file is in the public domain. */ +/* $FreeBSD$ */ -#ifndef _MACHINE_FRAME_H_ -#define _MACHINE_FRAME_H_ 1 - -/* - * System stack frames. - */ - -/* - * Exception/Trap Stack Frame - * - * The ordering of this is specifically so that we can take first 6 - * the syscall arguments directly from the beginning of the frame. - */ - -struct trapframe { - register_t tf_rdi; - register_t tf_rsi; - register_t tf_rdx; - register_t tf_rcx; - register_t tf_r8; - register_t tf_r9; - register_t tf_rax; - register_t tf_rbx; - register_t tf_rbp; - register_t tf_r10; - register_t tf_r11; - register_t tf_r12; - register_t tf_r13; - register_t tf_r14; - register_t tf_r15; - uint32_t tf_trapno; - uint16_t tf_fs; - uint16_t tf_gs; - register_t tf_addr; - uint32_t tf_flags; - uint16_t tf_es; - uint16_t tf_ds; - /* below portion defined in hardware */ - register_t tf_err; - register_t tf_rip; - register_t tf_cs; - register_t tf_rflags; - register_t tf_rsp; - register_t tf_ss; -}; - -#define TF_HASSEGS 0x1 -#define TF_HASBASES 0x2 -#define TF_HASFPXSTATE 0x4 - -#endif /* _MACHINE_FRAME_H_ */ +#include <x86/frame.h> diff --git a/sys/amd64/include/sigframe.h b/sys/amd64/include/sigframe.h index d104507..d5cdb56 100644 --- a/sys/amd64/include/sigframe.h +++ b/sys/amd64/include/sigframe.h @@ -1,46 +1,6 @@ /*- - * Copyright (c) 1999 Marcel Moolenaar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer - * in this position and unchanged. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * $FreeBSD$ + * This file is in the public domain. */ +/* $FreeBSD$ */ -#ifndef _MACHINE_SIGFRAME_H_ -#define _MACHINE_SIGFRAME_H_ - -/* - * Signal frames, arguments passed to application signal handlers. - */ -struct sigframe { - union { - __siginfohandler_t *sf_action; - __sighandler_t *sf_handler; - } sf_ahu; - ucontext_t sf_uc; /* = *sf_ucontext */ - siginfo_t sf_si; /* = *sf_siginfo (SA_SIGINFO case) */ -}; - -#endif /* !_MACHINE_SIGFRAME_H_ */ +#include <x86/sigframe.h> diff --git a/sys/amd64/include/signal.h b/sys/amd64/include/signal.h index 085d43a..db9fe6a 100644 --- a/sys/amd64/include/signal.h +++ b/sys/amd64/include/signal.h @@ -1,109 +1,6 @@ /*- - * Copyright (c) 2003 Peter Wemm. - * Copyright (c) 1986, 1989, 1991, 1993 - * The Regents of the University of California. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 4. Neither the name of the University nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @(#)signal.h 8.1 (Berkeley) 6/11/93 - * $FreeBSD$ + * This file is in the public domain. */ +/* $FreeBSD$ */ -#ifndef _MACHINE_SIGNAL_H_ -#define _MACHINE_SIGNAL_H_ - -#include <sys/cdefs.h> -#include <sys/_sigset.h> - -/* - * Machine-dependent signal definitions - */ - -typedef long sig_atomic_t; - -#if __BSD_VISIBLE -#include <machine/trap.h> /* codes for SIGILL, SIGFPE */ - -/* - * Information pushed on stack when a signal is delivered. - * This is used by the kernel to restore state following - * execution of the signal handler. It is also made available - * to the handler to allow it to restore state properly if - * a non-standard exit is performed. - * - * The sequence of the fields/registers after sc_mask in struct - * sigcontext must match those in mcontext_t and struct trapframe. - */ -struct sigcontext { - struct __sigset sc_mask; /* signal mask to restore */ - long sc_onstack; /* sigstack state to restore */ - long sc_rdi; /* machine state (struct trapframe) */ - long sc_rsi; - long sc_rdx; - long sc_rcx; - long sc_r8; - long sc_r9; - long sc_rax; - long sc_rbx; - long sc_rbp; - long sc_r10; - long sc_r11; - long sc_r12; - long sc_r13; - long sc_r14; - long sc_r15; - int sc_trapno; - short sc_fs; - short sc_gs; - long sc_addr; - int sc_flags; - short sc_es; - short sc_ds; - long sc_err; - long sc_rip; - long sc_cs; - long sc_rflags; - long sc_rsp; - long sc_ss; - long sc_len; /* sizeof(mcontext_t) */ - /* - * See <machine/ucontext.h> and <machine/fpu.h> for the following - * fields. - */ - long sc_fpformat; - long sc_ownedfp; - long sc_fpstate[64] __aligned(16); - - long sc_fsbase; - long sc_gsbase; - - long sc_xfpustate; - long sc_xfpustate_len; - - long sc_spare[4]; -}; -#endif /* __BSD_VISIBLE */ - -#endif /* !_MACHINE_SIGNAL_H_ */ +#include <x86/signal.h> diff --git a/sys/amd64/include/ucontext.h b/sys/amd64/include/ucontext.h index 5ab841e..aea80e3 100644 --- a/sys/amd64/include/ucontext.h +++ b/sys/amd64/include/ucontext.h @@ -1,103 +1,6 @@ /*- - * Copyright (c) 2003 Peter Wemm - * Copyright (c) 1999 Marcel Moolenaar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer - * in this position and unchanged. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * $FreeBSD$ + * This file is in the public domain. */ +/* $FreeBSD$ */ -#ifndef _MACHINE_UCONTEXT_H_ -#define _MACHINE_UCONTEXT_H_ - -/* - * mc_trapno bits. Shall be in sync with TF_XXX. - */ -#define _MC_HASSEGS 0x1 -#define _MC_HASBASES 0x2 -#define _MC_HASFPXSTATE 0x4 -#define _MC_FLAG_MASK (_MC_HASSEGS | _MC_HASBASES | _MC_HASFPXSTATE) - -typedef struct __mcontext { - /* - * The definition of mcontext_t must match the layout of - * struct sigcontext after the sc_mask member. This is so - * that we can support sigcontext and ucontext_t at the same - * time. - */ - __register_t mc_onstack; /* XXX - sigcontext compat. */ - __register_t mc_rdi; /* machine state (struct trapframe) */ - __register_t mc_rsi; - __register_t mc_rdx; - __register_t mc_rcx; - __register_t mc_r8; - __register_t mc_r9; - __register_t mc_rax; - __register_t mc_rbx; - __register_t mc_rbp; - __register_t mc_r10; - __register_t mc_r11; - __register_t mc_r12; - __register_t mc_r13; - __register_t mc_r14; - __register_t mc_r15; - __uint32_t mc_trapno; - __uint16_t mc_fs; - __uint16_t mc_gs; - __register_t mc_addr; - __uint32_t mc_flags; - __uint16_t mc_es; - __uint16_t mc_ds; - __register_t mc_err; - __register_t mc_rip; - __register_t mc_cs; - __register_t mc_rflags; - __register_t mc_rsp; - __register_t mc_ss; - - long mc_len; /* sizeof(mcontext_t) */ - -#define _MC_FPFMT_NODEV 0x10000 /* device not present or configured */ -#define _MC_FPFMT_XMM 0x10002 - long mc_fpformat; -#define _MC_FPOWNED_NONE 0x20000 /* FP state not used */ -#define _MC_FPOWNED_FPU 0x20001 /* FP state came from FPU */ -#define _MC_FPOWNED_PCB 0x20002 /* FP state came from PCB */ - long mc_ownedfp; - /* - * See <machine/fpu.h> for the internals of mc_fpstate[]. - */ - long mc_fpstate[64] __aligned(16); - - __register_t mc_fsbase; - __register_t mc_gsbase; - - __register_t mc_xfpustate; - __register_t mc_xfpustate_len; - - long mc_spare[4]; -} mcontext_t; - -#endif /* !_MACHINE_UCONTEXT_H_ */ +#include <x86/ucontext.h> diff --git a/sys/arm/allwinner/a10_clk.c b/sys/arm/allwinner/a10_clk.c index 275ec4b..64251fb 100644 --- a/sys/arm/allwinner/a10_clk.c +++ b/sys/arm/allwinner/a10_clk.c @@ -129,6 +129,7 @@ a10_clk_usb_activate(void) /* Gating AHB clock for USB */ reg_value = ccm_read_4(sc, CCM_AHB_GATING0); reg_value |= CCM_AHB_GATING_USB0; /* AHB clock gate usb0 */ + reg_value |= CCM_AHB_GATING_EHCI0; /* AHB clock gate ehci1 */ reg_value |= CCM_AHB_GATING_EHCI1; /* AHB clock gate ehci1 */ ccm_write_4(sc, CCM_AHB_GATING0, reg_value); diff --git a/sys/arm/allwinner/a10_clk.h b/sys/arm/allwinner/a10_clk.h index 7316a22..a2a6bc9 100644 --- a/sys/arm/allwinner/a10_clk.h +++ b/sys/arm/allwinner/a10_clk.h @@ -101,6 +101,7 @@ #define CCM_MALI400_CLK 0x0154 #define CCM_AHB_GATING_USB0 (1 << 0) +#define CCM_AHB_GATING_EHCI0 (1 << 1) #define CCM_AHB_GATING_EHCI1 (1 << 3) #define CCM_USB_PHY (1 << 8) diff --git a/sys/arm/allwinner/a10_ehci.c b/sys/arm/allwinner/a10_ehci.c index 0d1636b..4145a5c 100644 --- a/sys/arm/allwinner/a10_ehci.c +++ b/sys/arm/allwinner/a10_ehci.c @@ -75,6 +75,7 @@ __FBSDID("$FreeBSD$"); #define SW_AHB_INCRX_ALIGN (1 << 8) #define SW_AHB_INCR4 (1 << 9) #define SW_AHB_INCR8 (1 << 10) +#define GPIO_USB1_PWR 230 #define GPIO_USB2_PWR 227 #define A10_READ_4(sc, reg) \ @@ -182,6 +183,10 @@ a10_ehci_attach(device_t self) GPIO_PIN_SETFLAGS(sc_gpio_dev, GPIO_USB2_PWR, GPIO_PIN_OUTPUT); GPIO_PIN_SET(sc_gpio_dev, GPIO_USB2_PWR, GPIO_PIN_HIGH); + /* Give power to USB */ + GPIO_PIN_SETFLAGS(sc_gpio_dev, GPIO_USB1_PWR, GPIO_PIN_OUTPUT); + GPIO_PIN_SET(sc_gpio_dev, GPIO_USB1_PWR, GPIO_PIN_HIGH); + /* Enable passby */ reg_value = A10_READ_4(sc, SW_USB_PMU_IRQ_ENABLE); reg_value |= SW_AHB_INCR8; /* AHB INCR8 enable */ diff --git a/sys/arm/allwinner/a10_gpio.c b/sys/arm/allwinner/a10_gpio.c index b70d036..bc0d92a 100644 --- a/sys/arm/allwinner/a10_gpio.c +++ b/sys/arm/allwinner/a10_gpio.c @@ -66,6 +66,13 @@ __FBSDID("$FreeBSD$"); #define A10_GPIO_DEFAULT_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | \ GPIO_PIN_PULLUP | GPIO_PIN_PULLDOWN) +#define A10_GPIO_NONE 0 +#define A10_GPIO_PULLUP 1 +#define A10_GPIO_PULLDOWN 2 + +#define A10_GPIO_INPUT 0 +#define A10_GPIO_OUTPUT 1 + struct a10_gpio_softc { device_t sc_dev; struct mtx sc_mtx; @@ -78,17 +85,6 @@ struct a10_gpio_softc { struct gpio_pin sc_gpio_pins[A10_GPIO_PINS]; }; -enum a10_gpio_fsel { - A10_GPIO_INPUT, - A10_GPIO_OUTPUT, -}; - -enum a10_gpio_pud { - A10_GPIO_NONE, - A10_GPIO_PULLDOWN, - A10_GPIO_PULLUP, -}; - #define A10_GPIO_LOCK(_sc) mtx_lock(&_sc->sc_mtx) #define A10_GPIO_UNLOCK(_sc) mtx_unlock(&_sc->sc_mtx) #define A10_GPIO_LOCK_ASSERT(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED) diff --git a/sys/arm/arm/busdma_machdep-v6.c b/sys/arm/arm/busdma_machdep-v6.c index 0a0bdd8..c87f857 100644 --- a/sys/arm/arm/busdma_machdep-v6.c +++ b/sys/arm/arm/busdma_machdep-v6.c @@ -856,7 +856,7 @@ _bus_dmamap_addseg(bus_dma_tag_t dmat, bus_dmamap_t map, bus_addr_t curaddr, curaddr); if (dr == NULL) { _bus_dmamap_unload(dmat, map); - return (EINVAL); + return (0); } /* * In a valid DMA range. Translate the physical @@ -968,6 +968,8 @@ _bus_dmamap_load_buffer(bus_dma_tag_t dmat, if (segs == NULL) segs = dmat->segments; + map->pmap = pmap; + if ((dmat->flags & BUS_DMA_COULD_BOUNCE) != 0) { _bus_dmamap_count_pages(dmat, map, buf, buflen, flags); if (map->pagesneeded != 0) { @@ -979,7 +981,6 @@ _bus_dmamap_load_buffer(bus_dma_tag_t dmat, sl = NULL; vaddr = (vm_offset_t)buf; - map->pmap = pmap; while (buflen > 0) { /* diff --git a/sys/arm/arm/busdma_machdep.c b/sys/arm/arm/busdma_machdep.c index f31a7fe..10760b4 100644 --- a/sys/arm/arm/busdma_machdep.c +++ b/sys/arm/arm/busdma_machdep.c @@ -913,7 +913,7 @@ _bus_dmamap_addseg(bus_dma_tag_t dmat, bus_dmamap_t map, bus_addr_t curaddr, dr = _bus_dma_inrange(dmat->ranges, dmat->_nranges, curaddr); if (dr == NULL) - return (EINVAL); + return (0); /* * In a valid DMA range. Translate the physical * memory address to an address in the DMA window. @@ -935,12 +935,12 @@ _bus_dmamap_addseg(bus_dma_tag_t dmat, bus_dmamap_t map, bus_addr_t curaddr, segs[seg].ds_len += sgsize; } else { if (++seg >= dmat->nsegments) - return (EFBIG); + return (0); segs[seg].ds_addr = curaddr; segs[seg].ds_len = sgsize; } *segp = seg; - return (0); + return (sgsize); } /* diff --git a/sys/arm/arm/machdep.c b/sys/arm/arm/machdep.c index 5c4d92c..5262e71 100644 --- a/sys/arm/arm/machdep.c +++ b/sys/arm/arm/machdep.c @@ -45,6 +45,7 @@ #include "opt_compat.h" #include "opt_ddb.h" #include "opt_platform.h" +#include "opt_sched.h" #include "opt_timer.h" #include <sys/cdefs.h> @@ -70,6 +71,7 @@ __FBSDID("$FreeBSD$"); #include <sys/mutex.h> #include <sys/pcpu.h> #include <sys/ptrace.h> +#include <sys/sched.h> #include <sys/signalvar.h> #include <sys/syscallsubr.h> #include <sys/sysctl.h> @@ -433,19 +435,24 @@ void cpu_idle(int busy) { + CTR2(KTR_SPARE2, "cpu_idle(%d) at %d", + busy, curcpu); #ifndef NO_EVENTTIMERS if (!busy) { critical_enter(); cpu_idleclock(); } #endif - cpu_sleep(0); + if (!sched_runnable()) + cpu_sleep(0); #ifndef NO_EVENTTIMERS if (!busy) { cpu_activeclock(); critical_exit(); } #endif + CTR2(KTR_SPARE2, "cpu_idle(%d) at %d done", + busy, curcpu); } int @@ -1178,7 +1185,6 @@ initarm(struct arm_boot_params *abp) struct pv_addr kernel_l1pt; struct pv_addr dpcpu; vm_offset_t dtbp, freemempos, l2_start, lastaddr; - vm_offset_t pmap_bootstrap_lastaddr; uint32_t memsize, l2size; char *env; void *kmdp; @@ -1288,7 +1294,7 @@ initarm(struct arm_boot_params *abp) availmem_regions_sz = curr; /* Platform-specific initialisation */ - pmap_bootstrap_lastaddr = initarm_lastaddr(); + vm_max_kernel_address = initarm_lastaddr(); pcpu0_init(); @@ -1477,7 +1483,7 @@ initarm(struct arm_boot_params *abp) arm_intrnames_init(); arm_vector_init(ARM_VECTORS_HIGH, ARM_VEC_ALL); arm_dump_avail_init(memsize, sizeof(dump_avail) / sizeof(dump_avail[0])); - pmap_bootstrap(freemempos, pmap_bootstrap_lastaddr, &kernel_l1pt); + pmap_bootstrap(freemempos, &kernel_l1pt); msgbufp = (void *)msgbufpv.pv_va; msgbufinit(msgbufp, msgbufsize); mutex_init(); diff --git a/sys/arm/arm/pmap-v6.c b/sys/arm/arm/pmap-v6.c index d3e386d..72ef310 100644 --- a/sys/arm/arm/pmap-v6.c +++ b/sys/arm/arm/pmap-v6.c @@ -231,6 +231,8 @@ vm_paddr_t kernel_l1pa; vm_offset_t kernel_vm_end = 0; +vm_offset_t vm_max_kernel_address; + struct pmap kernel_pmap_store; static pt_entry_t *csrc_pte, *cdst_pte; @@ -1536,7 +1538,7 @@ pmap_alloc_specials(vm_offset_t *availp, int pages, vm_offset_t *vap, #define PMAP_STATIC_L2_SIZE 16 void -pmap_bootstrap(vm_offset_t firstaddr, vm_offset_t lastaddr, struct pv_addr *l1pt) +pmap_bootstrap(vm_offset_t firstaddr, struct pv_addr *l1pt) { static struct l1_ttable static_l1; static struct l2_dtable static_l2[PMAP_STATIC_L2_SIZE]; @@ -1552,7 +1554,7 @@ pmap_bootstrap(vm_offset_t firstaddr, vm_offset_t lastaddr, struct pv_addr *l1pt int l1idx, l2idx, l2next = 0; PDEBUG(1, printf("firstaddr = %08x, lastaddr = %08x\n", - firstaddr, lastaddr)); + firstaddr, vm_max_kernel_address)); virtual_avail = firstaddr; kernel_pmap->pm_l1 = l1; @@ -1668,7 +1670,8 @@ pmap_bootstrap(vm_offset_t firstaddr, vm_offset_t lastaddr, struct pv_addr *l1pt pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)csrc_pte); pmap_alloc_specials(&virtual_avail, 1, &cdstp, &cdst_pte); pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)cdst_pte); - size = ((lastaddr - pmap_curmaxkvaddr) + L1_S_OFFSET) / L1_S_SIZE; + size = ((vm_max_kernel_address - pmap_curmaxkvaddr) + L1_S_OFFSET) / + L1_S_SIZE; pmap_alloc_specials(&virtual_avail, round_page(size * L2_TABLE_SIZE_REAL) / PAGE_SIZE, &pmap_kernel_l2ptp_kva, NULL); @@ -1690,9 +1693,9 @@ pmap_bootstrap(vm_offset_t firstaddr, vm_offset_t lastaddr, struct pv_addr *l1pt cpu_l2cache_wbinv_all(); virtual_avail = round_page(virtual_avail); - virtual_end = lastaddr; + virtual_end = vm_max_kernel_address; kernel_vm_end = pmap_curmaxkvaddr; - arm_nocache_startaddr = lastaddr; + arm_nocache_startaddr = vm_max_kernel_address; mtx_init(&cmtx, "TMP mappings mtx", NULL, MTX_DEF); pmap_set_pcb_pagedir(kernel_pmap, thread0.td_pcb); diff --git a/sys/arm/arm/pmap.c b/sys/arm/arm/pmap.c index 7170a98..28b4912 100644 --- a/sys/arm/arm/pmap.c +++ b/sys/arm/arm/pmap.c @@ -220,6 +220,8 @@ vm_paddr_t kernel_l1pa; vm_offset_t kernel_vm_end = 0; +vm_offset_t vm_max_kernel_address; + struct pmap kernel_pmap_store; static pt_entry_t *csrc_pte, *cdst_pte; @@ -2252,7 +2254,7 @@ extern struct mtx smallalloc_mtx; #endif void -pmap_bootstrap(vm_offset_t firstaddr, vm_offset_t lastaddr, struct pv_addr *l1pt) +pmap_bootstrap(vm_offset_t firstaddr, struct pv_addr *l1pt) { static struct l1_ttable static_l1; static struct l2_dtable static_l2[PMAP_STATIC_L2_SIZE]; @@ -2268,7 +2270,7 @@ pmap_bootstrap(vm_offset_t firstaddr, vm_offset_t lastaddr, struct pv_addr *l1pt int l1idx, l2idx, l2next = 0; PDEBUG(1, printf("firstaddr = %08x, lastaddr = %08x\n", - firstaddr, lastaddr)); + firstaddr, vm_max_kernel_address)); virtual_avail = firstaddr; kernel_pmap->pm_l1 = l1; @@ -2386,7 +2388,8 @@ pmap_bootstrap(vm_offset_t firstaddr, vm_offset_t lastaddr, struct pv_addr *l1pt pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)csrc_pte); pmap_alloc_specials(&virtual_avail, 1, &cdstp, &cdst_pte); pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)cdst_pte); - size = ((lastaddr - pmap_curmaxkvaddr) + L1_S_OFFSET) / L1_S_SIZE; + size = ((vm_max_kernel_address - pmap_curmaxkvaddr) + L1_S_OFFSET) / + L1_S_SIZE; pmap_alloc_specials(&virtual_avail, round_page(size * L2_TABLE_SIZE_REAL) / PAGE_SIZE, &pmap_kernel_l2ptp_kva, NULL); @@ -2408,9 +2411,9 @@ pmap_bootstrap(vm_offset_t firstaddr, vm_offset_t lastaddr, struct pv_addr *l1pt cpu_l2cache_wbinv_all(); virtual_avail = round_page(virtual_avail); - virtual_end = lastaddr; + virtual_end = vm_max_kernel_address; kernel_vm_end = pmap_curmaxkvaddr; - arm_nocache_startaddr = lastaddr; + arm_nocache_startaddr = vm_max_kernel_address; mtx_init(&cmtx, "TMP mappings mtx", NULL, MTX_DEF); #ifdef ARM_USE_SMALL_ALLOC diff --git a/sys/arm/at91/at91_machdep.c b/sys/arm/at91/at91_machdep.c index f2b63cbd..3df922e 100644 --- a/sys/arm/at91/at91_machdep.c +++ b/sys/arm/at91/at91_machdep.c @@ -624,7 +624,8 @@ initarm(struct arm_boot_params *abp) pmap_curmaxkvaddr = afterkern + L1_S_SIZE * (KERNEL_PT_KERN_NUM - 1); arm_dump_avail_init(memsize, sizeof(dump_avail)/sizeof(dump_avail[0])); - pmap_bootstrap(freemempos, KERNVIRTADDR + 3 * memsize, &kernel_l1pt); + vm_max_kernel_address = KERNVIRTADDR + 3 * memsize; + pmap_bootstrap(freemempos, &kernel_l1pt); msgbufp = (void*)msgbufpv.pv_va; msgbufinit(msgbufp, msgbufsize); mutex_init(); diff --git a/sys/arm/broadcom/bcm2835/bcm2835_sdhci.c b/sys/arm/broadcom/bcm2835/bcm2835_sdhci.c index 14422e2..cfba2cd 100644 --- a/sys/arm/broadcom/bcm2835/bcm2835_sdhci.c +++ b/sys/arm/broadcom/bcm2835/bcm2835_sdhci.c @@ -78,6 +78,17 @@ __FBSDID("$FreeBSD$"); #define dprintf(fmt, args...) #endif +/* + * Arasan HC seems to have problem with Data CRC on lower frequencies. + * Use this tunable to cap initialization sequence frequency at higher + * value. Default is standard 400kHz + */ +static int bcm2835_sdhci_min_freq = 400000; +static int bcm2835_sdhci_hs = 1; + +TUNABLE_INT("hw.bcm2835.sdhci.min_freq", &bcm2835_sdhci_min_freq); +TUNABLE_INT("hw.bcm2835.sdhci.hs", &bcm2835_sdhci_hs); + struct bcm_sdhci_dmamap_arg { bus_addr_t sc_dma_busaddr; }; @@ -180,7 +191,9 @@ bcm_sdhci_attach(device_t dev) goto fail; } - sc->sc_slot.caps = SDHCI_CAN_VDD_330 | SDHCI_CAN_VDD_180 | SDHCI_CAN_DO_HISPD; + sc->sc_slot.caps = SDHCI_CAN_VDD_330 | SDHCI_CAN_VDD_180; + if (bcm2835_sdhci_hs) + sc->sc_slot.caps |= SDHCI_CAN_DO_HISPD; sc->sc_slot.caps |= (default_freq << SDHCI_CLOCK_BASE_SHIFT); sc->sc_slot.quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL @@ -334,6 +347,13 @@ bcm_sdhci_write_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, bus_space_write_multi_4(sc->sc_bst, sc->sc_bsh, off, data, count); } +static uint32_t +bcm_sdhci_min_freq(device_t dev, struct sdhci_slot *slot) +{ + + return bcm2835_sdhci_min_freq; +} + static device_method_t bcm_sdhci_methods[] = { /* Device interface */ DEVMETHOD(device_probe, bcm_sdhci_probe), @@ -353,6 +373,7 @@ static device_method_t bcm_sdhci_methods[] = { DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host), /* SDHCI registers accessors */ + DEVMETHOD(sdhci_min_freq, bcm_sdhci_min_freq), DEVMETHOD(sdhci_read_1, bcm_sdhci_read_1), DEVMETHOD(sdhci_read_2, bcm_sdhci_read_2), DEVMETHOD(sdhci_read_4, bcm_sdhci_read_4), diff --git a/sys/arm/broadcom/bcm2835/bcm2835_vcbus.h b/sys/arm/broadcom/bcm2835/bcm2835_vcbus.h index 1d91046..cb871f2 100644 --- a/sys/arm/broadcom/bcm2835/bcm2835_vcbus.h +++ b/sys/arm/broadcom/bcm2835/bcm2835_vcbus.h @@ -34,14 +34,28 @@ #define _BCM2835_VCBUS_H_ #define BCM2835_VCBUS_SDRAM_CACHED 0x40000000 +#define BCM2835_VCBUS_IO_BASE 0x7E000000 #define BCM2835_VCBUS_SDRAM_UNCACHED 0xC0000000 +#define BCM2835_ARM_IO_BASE 0x20000000 +#define BCM2835_ARM_IO_SIZE 0x02000000 + /* * Convert physical address to VC bus address. Should be used * when submitting address over mailbox interface */ #define PHYS_TO_VCBUS(pa) ((pa) + BCM2835_VCBUS_SDRAM_CACHED) +/* Check whether pa bellong top IO window */ +#define BCM2835_ARM_IS_IO(pa) (((pa) >= BCM2835_ARM_IO_BASE) && \ + ((pa) < BCM2835_ARM_IO_BASE + BCM2835_ARM_IO_SIZE)) + +/* + * Convert physical address in IO space to VC bus address. + */ +#define IO_TO_VCBUS(pa) ((pa - BCM2835_ARM_IO_BASE) + \ + BCM2835_VCBUS_IO_BASE) + /* * Convert address from VC bus space to physical. Should be used * when address is returned by VC over mailbox interface. e.g. diff --git a/sys/arm/econa/econa_machdep.c b/sys/arm/econa/econa_machdep.c index e9a98ee..177d45b 100644 --- a/sys/arm/econa/econa_machdep.c +++ b/sys/arm/econa/econa_machdep.c @@ -324,7 +324,8 @@ initarm(struct arm_boot_params *abp) pmap_curmaxkvaddr = afterkern + L1_S_SIZE * (KERNEL_PT_KERN_NUM - 1); arm_dump_avail_init(memsize, sizeof(dump_avail) / sizeof(dump_avail[0])); - pmap_bootstrap(freemempos, KERNVIRTADDR + 3 * memsize, &kernel_l1pt); + vm_max_kernel_address = KERNVIRTADDR + 3 * memsize; + pmap_bootstrap(freemempos, &kernel_l1pt); msgbufp = (void*)msgbufpv.pv_va; msgbufinit(msgbufp, msgbufsize); diff --git a/sys/arm/include/pmap.h b/sys/arm/include/pmap.h index 4f7566e..523499f 100644 --- a/sys/arm/include/pmap.h +++ b/sys/arm/include/pmap.h @@ -222,7 +222,7 @@ extern vm_paddr_t phys_avail[]; extern vm_offset_t virtual_avail; extern vm_offset_t virtual_end; -void pmap_bootstrap(vm_offset_t, vm_offset_t, struct pv_addr *); +void pmap_bootstrap(vm_offset_t firstaddr, struct pv_addr *l1pt); int pmap_change_attr(vm_offset_t, vm_size_t, int); void pmap_kenter(vm_offset_t va, vm_paddr_t pa); void pmap_kenter_nocache(vm_offset_t va, vm_paddr_t pa); diff --git a/sys/arm/include/vmparam.h b/sys/arm/include/vmparam.h index 267ba6e..94caeef 100644 --- a/sys/arm/include/vmparam.h +++ b/sys/arm/include/vmparam.h @@ -133,7 +133,7 @@ #define VM_MIN_KERNEL_ADDRESS KERNBASE #endif -#define VM_MAX_KERNEL_ADDRESS 0xffffffff +#define VM_MAX_KERNEL_ADDRESS (vm_max_kernel_address) /* * Virtual size (bytes) for various kernel submaps. @@ -145,6 +145,14 @@ #define VM_KMEM_SIZE_SCALE (2) #endif +/* + * Ceiling on the size of the kmem submap: 60% of the kernel map. + */ +#ifndef VM_KMEM_SIZE_MAX +#define VM_KMEM_SIZE_MAX ((vm_max_kernel_address - \ + VM_MIN_KERNEL_ADDRESS + 1) * 3 / 5) +#endif + #define MAXTSIZ (16*1024*1024) #ifndef DFLDSIZ #define DFLDSIZ (128*1024*1024) @@ -166,6 +174,8 @@ #define UMA_MD_SMALL_ALLOC #endif /* ARM_USE_SMALL_ALLOC */ +extern vm_offset_t vm_max_kernel_address; + #define ZERO_REGION_SIZE (64 * 1024) /* 64KB */ #endif /* _MACHINE_VMPARAM_H_ */ diff --git a/sys/arm/s3c2xx0/s3c24x0_machdep.c b/sys/arm/s3c2xx0/s3c24x0_machdep.c index 8d2538b..f19e3f2 100644 --- a/sys/arm/s3c2xx0/s3c24x0_machdep.c +++ b/sys/arm/s3c2xx0/s3c24x0_machdep.c @@ -386,7 +386,8 @@ initarm(struct arm_boot_params *abp) pmap_curmaxkvaddr = afterkern + 0x100000 * (KERNEL_PT_KERN_NUM - 1); arm_dump_avail_init(memsize, sizeof(dump_avail) / sizeof(dump_avail[0])); - pmap_bootstrap(freemempos, KERNVIRTADDR + 3 * memsize, &kernel_l1pt); + vm_max_kernel_address = KERNVIRTADDR + 3 * memsize; + pmap_bootstrap(freemempos, &kernel_l1pt); msgbufp = (void*)msgbufpv.pv_va; msgbufinit(msgbufp, msgbufsize); mutex_init(); diff --git a/sys/arm/sa11x0/assabet_machdep.c b/sys/arm/sa11x0/assabet_machdep.c index 9fd1633..9266939 100644 --- a/sys/arm/sa11x0/assabet_machdep.c +++ b/sys/arm/sa11x0/assabet_machdep.c @@ -381,7 +381,8 @@ initarm(struct arm_boot_params *abp) dump_avail[3] = phys_avail[3] = 0; mutex_init(); - pmap_bootstrap(freemempos, 0xd0000000, &kernel_l1pt); + vm_max_kernel_address = 0xd0000000; + pmap_bootstrap(freemempos, &kernel_l1pt); init_param2(physmem); kdb_init(); diff --git a/sys/arm/ti/ti_cpuid.c b/sys/arm/ti/ti_cpuid.c index 89046c4..027dd6d 100644 --- a/sys/arm/ti/ti_cpuid.c +++ b/sys/arm/ti/ti_cpuid.c @@ -109,8 +109,7 @@ omap4_get_revision(void) * STD_FUSE_PROD_ID_0 0x4A00 2214 * STD_FUSE_PROD_ID_1 0x4A00 2218 */ - // id_code = REG_READ32(OMAP44XX_L4_CORE_VBASE + OMAP4_ID_CODE); - //FIXME Should we map somewhere else? + /* FIXME Should we map somewhere else? */ bus_space_map(fdtbus_bs_tag,OMAP44XX_L4_CORE_HWBASE, 0x4000, 0, &bsh); id_code = bus_space_read_4(fdtbus_bs_tag, bsh, OMAP4_ID_CODE); bus_space_unmap(fdtbus_bs_tag, bsh, 0x4000); @@ -228,10 +227,9 @@ omap3_get_revision(void) * * */ - //id_code = REG_READ32(OMAP35XX_L4_WAKEUP_VBASE + OMAP3_ID_CODE); - bus_space_map(fdtbus_bs_tag,OMAP35XX_L4_WAKEUP_HWBASE, 0x10000, 0, &bsh); + bus_space_map(fdtbus_bs_tag, OMAP35XX_L4_WAKEUP_HWBASE, 0x10000, 0, &bsh); id_code = bus_space_read_4(fdtbus_bs_tag, bsh, OMAP3_ID_CODE); - bus_space_unmap(fdtbus_bs_tag, bsh, 0x4000); + bus_space_unmap(fdtbus_bs_tag, bsh, 0x10000); hawkeye = ((id_code >> 12) & 0xffff); revision = ((id_code >> 28) & 0xf); diff --git a/sys/arm/xscale/i80321/ep80219_machdep.c b/sys/arm/xscale/i80321/ep80219_machdep.c index b7621ca..d3c65b2 100644 --- a/sys/arm/xscale/i80321/ep80219_machdep.c +++ b/sys/arm/xscale/i80321/ep80219_machdep.c @@ -368,8 +368,8 @@ initarm(struct arm_boot_params *abp) dump_avail[2] = 0; dump_avail[3] = 0; - pmap_bootstrap(pmap_curmaxkvaddr, - 0xd0000000, &kernel_l1pt); + vm_max_kernel_address = 0xd0000000; + pmap_bootstrap(pmap_curmaxkvaddr, &kernel_l1pt); msgbufp = (void*)msgbufpv.pv_va; msgbufinit(msgbufp, msgbufsize); mutex_init(); diff --git a/sys/arm/xscale/i80321/iq31244_machdep.c b/sys/arm/xscale/i80321/iq31244_machdep.c index 869c248..e7f34f5 100644 --- a/sys/arm/xscale/i80321/iq31244_machdep.c +++ b/sys/arm/xscale/i80321/iq31244_machdep.c @@ -369,8 +369,8 @@ initarm(struct arm_boot_params *abp) dump_avail[2] = 0; dump_avail[3] = 0; - pmap_bootstrap(pmap_curmaxkvaddr, - 0xd0000000, &kernel_l1pt); + vm_max_kernel_address = 0xd0000000; + pmap_bootstrap(pmap_curmaxkvaddr, &kernel_l1pt); msgbufp = (void*)msgbufpv.pv_va; msgbufinit(msgbufp, msgbufsize); mutex_init(); diff --git a/sys/arm/xscale/i8134x/crb_machdep.c b/sys/arm/xscale/i8134x/crb_machdep.c index e0f21db..7c62c72 100644 --- a/sys/arm/xscale/i8134x/crb_machdep.c +++ b/sys/arm/xscale/i8134x/crb_machdep.c @@ -347,8 +347,8 @@ initarm(struct arm_boot_params *abp) dump_avail[2] = 0; dump_avail[3] = 0; - pmap_bootstrap(pmap_curmaxkvaddr, - 0xd0000000, &kernel_l1pt); + vm_max_kernel_address = 0xd0000000; + pmap_bootstrap(pmap_curmaxkvaddr, &kernel_l1pt); msgbufp = (void*)msgbufpv.pv_va; msgbufinit(msgbufp, msgbufsize); mutex_init(); diff --git a/sys/arm/xscale/ixp425/avila_machdep.c b/sys/arm/xscale/ixp425/avila_machdep.c index dde3be7..82b0e02 100644 --- a/sys/arm/xscale/ixp425/avila_machdep.c +++ b/sys/arm/xscale/ixp425/avila_machdep.c @@ -432,7 +432,8 @@ initarm(struct arm_boot_params *abp) pmap_curmaxkvaddr = afterkern + PAGE_SIZE; arm_dump_avail_init(memsize, sizeof(dump_avail) / sizeof(dump_avail[0])); - pmap_bootstrap(pmap_curmaxkvaddr, 0xd0000000, &kernel_l1pt); + vm_max_kernel_address = 0xd0000000; + pmap_bootstrap(pmap_curmaxkvaddr, &kernel_l1pt); msgbufp = (void*)msgbufpv.pv_va; msgbufinit(msgbufp, msgbufsize); mutex_init(); diff --git a/sys/arm/xscale/pxa/pxa_machdep.c b/sys/arm/xscale/pxa/pxa_machdep.c index 71f7785..440812f 100644 --- a/sys/arm/xscale/pxa/pxa_machdep.c +++ b/sys/arm/xscale/pxa/pxa_machdep.c @@ -365,7 +365,8 @@ initarm(struct arm_boot_params *abp) } dump_avail[i] = 0; dump_avail[i] = 0; - pmap_bootstrap(pmap_curmaxkvaddr, 0xd0000000, &kernel_l1pt); + vm_max_kernel_address = 0xd0000000; + pmap_bootstrap(pmap_curmaxkvaddr, &kernel_l1pt); msgbufp = (void*)msgbufpv.pv_va; msgbufinit(msgbufp, msgbufsize); mutex_init(); diff --git a/sys/boot/common/bootstrap.h b/sys/boot/common/bootstrap.h index 516b8a5..78b3895 100644 --- a/sys/boot/common/bootstrap.h +++ b/sys/boot/common/bootstrap.h @@ -237,6 +237,8 @@ void file_discard(struct preloaded_file *fp); void file_addmetadata(struct preloaded_file *fp, int type, size_t size, void *p); int file_addmodule(struct preloaded_file *fp, char *modname, int version, struct kernel_module **newmp); +/* Load from a buffer in memory. */ +struct preloaded_file *mem_load_raw(char *type, char *name, const void *p, size_t len); /* MI module loaders */ #ifdef __elfN diff --git a/sys/boot/common/module.c b/sys/boot/common/module.c index 96c0a58..3b74ab7 100644 --- a/sys/boot/common/module.c +++ b/sys/boot/common/module.c @@ -351,6 +351,7 @@ file_load_dependencies(struct preloaded_file *base_file) } return (error); } + /* * We've been asked to load (name) as (type), so just suck it in, * no arguments or anything. @@ -421,6 +422,42 @@ file_loadraw(char *type, char *name) } /* + * Load a chunk of data as if it had been read from a file. + */ +struct preloaded_file * +mem_load_raw(char *type, char *name, const void *p, size_t len) +{ + struct preloaded_file *fp; + + /* We can't load first */ + if ((file_findfile(NULL, NULL)) == NULL) { + command_errmsg = "can't load file before kernel"; + return(NULL); + } + + if (archsw.arch_loadaddr != NULL) + loadaddr = archsw.arch_loadaddr(LOAD_RAW, name, loadaddr); + archsw.arch_copyin(p, loadaddr, len); + + /* Looks OK so far; create & populate control structure */ + fp = file_alloc(); + fp->f_name = strdup(name); + fp->f_type = strdup(type); + fp->f_args = NULL; + fp->f_metadata = NULL; + fp->f_loader = -1; + fp->f_addr = loadaddr; + fp->f_size = len; + + /* recognise space consumption */ + loadaddr += len; + + /* Add to the list of loaded files */ + file_insert_tail(fp); + return fp; +} + +/* * Load the module (name), pass it (argc),(argv), add container file * to the list of loaded files. * If module is already loaded just assign new argc/argv. diff --git a/sys/boot/fdt/dts/bcm2835-rpi-b.dts b/sys/boot/fdt/dts/bcm2835-rpi-b.dts index d9357af..80bbef0 100644 --- a/sys/boot/fdt/dts/bcm2835-rpi-b.dts +++ b/sys/boot/fdt/dts/bcm2835-rpi-b.dts @@ -95,27 +95,6 @@ clock-frequency = <1000000>; }; - dma: dma { - compatible = "broadcom,bcm2835-dma", "broadcom,bcm2708-dma"; - reg = <0x7000 0x1000>, <0xE05000 0x1000>; - interrupts = < - 26 /* 2 */ - 27 /* 3 */ - >; - interrupt-parent = <&intc>; - - broadcom,channels = <0>; /* Set by VideoCore */ - }; - - sdhci { - compatible = "broadcom,bcm2835-sdhci", "broadcom,bcm2708-sdhci"; - reg = <0x300000 0x100>; - interrupts = <70>; - interrupt-parent = <&intc>; - - clock-frequency = <50000000>; /* Set by VideoCore */ - }; - armtimer { /* Not AMBA compatible */ compatible = "broadcom,bcm2835-sp804", "arm,sp804"; @@ -124,23 +103,6 @@ interrupt-parent = <&intc>; }; - vc_mbox: mbox { - compatible = "broadcom,bcm2835-mbox", "broadcom,bcm2708-mbox"; - reg = <0xB880 0x40>; - interrupts = <1>; - interrupt-parent = <&intc>; - - /* Channels - * 0: Power - * 1: Frame buffer - * 2: Virtual UART - * 3: VCHIQ - * 4: LEDs - * 5: Buttons - * 6: Touch screen - */ - }; - watchdog0 { compatible = "broadcom,bcm2835-wdt", "broadcom,bcm2708-wdt"; reg = <0x10001c 0x0c>; /* 0x1c, 0x20, 0x24 */ @@ -461,6 +423,41 @@ }; }; + dma: dma { + compatible = "broadcom,bcm2835-dma", "broadcom,bcm2708-dma"; + reg = <0x7000 0x1000>, <0xE05000 0x1000>; + interrupts = <24 25 26 27 28 29 30 31 32 33 34 35 36>; + interrupt-parent = <&intc>; + + broadcom,channels = <0>; /* Set by VideoCore */ + }; + + vc_mbox: mbox { + compatible = "broadcom,bcm2835-mbox", "broadcom,bcm2708-mbox"; + reg = <0xB880 0x40>; + interrupts = <1>; + interrupt-parent = <&intc>; + + /* Channels + * 0: Power + * 1: Frame buffer + * 2: Virtual UART + * 3: VCHIQ + * 4: LEDs + * 5: Buttons + * 6: Touch screen + */ + }; + + sdhci { + compatible = "broadcom,bcm2835-sdhci", "broadcom,bcm2708-sdhci"; + reg = <0x300000 0x100>; + interrupts = <70>; + interrupt-parent = <&intc>; + + clock-frequency = <50000000>; /* Set by VideoCore */ + }; + uart0: uart0 { compatible = "broadcom,bcm2835-uart", "broadcom,bcm2708-uart", "arm,pl011", "arm,primecell"; reg = <0x201000 0x1000>; diff --git a/sys/boot/fdt/dts/cubieboard.dts b/sys/boot/fdt/dts/cubieboard.dts index 1ef8b42..abb3f45 100644 --- a/sys/boot/fdt/dts/cubieboard.dts +++ b/sys/boot/fdt/dts/cubieboard.dts @@ -91,7 +91,14 @@ interrupt-parent = <&AINTC>; }; - usb1: usb@01c1c000 { + usb1: usb@01c14000 { + compatible = "allwinner,usb-ehci", "usb-ehci"; + reg = <0x01c14000 0x1000>; + interrupts = < 39 >; + interrupt-parent = <&AINTC>; + }; + + usb2: usb@01c1c000 { compatible = "allwinner,usb-ehci", "usb-ehci"; reg = <0x01c1c000 0x1000>; interrupts = < 40 >; diff --git a/sys/boot/fdt/fdt_loader_cmd.c b/sys/boot/fdt/fdt_loader_cmd.c index c7297f4..0417c52 100644 --- a/sys/boot/fdt/fdt_loader_cmd.c +++ b/sys/boot/fdt/fdt_loader_cmd.c @@ -62,7 +62,9 @@ __FBSDID("$FreeBSD$"); #define CMD_REQUIRES_BLOB 0x01 -/* Local copy of FDT */ +/* Location of FDT yet to be loaded. */ +static struct fdt_header *fdt_to_load = NULL; +/* Local copy of FDT on heap. */ static struct fdt_header *fdtp = NULL; /* Size of FDT blob */ static size_t fdtp_size = 0; @@ -235,26 +237,54 @@ fdt_load_dtb(vm_offset_t va) } static int -fdt_setup_fdtp() +fdt_load_dtb_addr(struct fdt_header *header) { struct preloaded_file *bfp; - vm_offset_t va; - bfp = file_findfile(NULL, "dtb"); + bfp = mem_load_raw("dtb", "memory.dtb", header, fdt_totalsize(header)); if (bfp == NULL) { - if ((va = fdt_find_static_dtb()) == 0) { - command_errmsg = "no device tree blob found!"; - return (1); - } - } else { - /* Dynamic blob has precedence over static. */ - va = bfp->f_addr; + command_errmsg = "unable to copy DTB into module directory"; + return (1); } + return fdt_load_dtb(bfp->f_addr); +} - if (fdt_load_dtb(va) != 0) - return (1); - - return (0); +static int +fdt_setup_fdtp() +{ + struct preloaded_file *bfp; + struct fdt_header *hdr; + const char *s; + char *p; + vm_offset_t va; + + if ((bfp = file_findfile(NULL, "dtb")) != NULL) { + printf("Using DTB from loaded file.\n"); + return fdt_load_dtb(bfp->f_addr); + } + + if (fdt_to_load != NULL) { + printf("Using DTB from memory address 0x%08X.\n", + (unsigned int)fdt_to_load); + return fdt_load_dtb_addr(fdt_to_load); + } + + s = ub_env_get("fdtaddr"); + if (s != NULL && *s != '\0') { + hdr = (struct fdt_header *)strtoul(s, &p, 16); + if (*p == '\0') { + printf("Using DTB provided by U-Boot.\n"); + return fdt_load_dtb_addr(hdr); + } + } + + if ((va = fdt_find_static_dtb()) != 0) { + printf("Using DTB compiled into kernel.\n"); + return (fdt_load_dtb(va)); + } + + command_errmsg = "no device tree blob found!"; + return (1); } #define fdt_strtovect(str, cellbuf, lim, cellsize) _fdt_strtovect((str), \ @@ -789,8 +819,12 @@ command_fdt_internal(int argc, char *argv[]) static int fdt_cmd_addr(int argc, char *argv[]) { - vm_offset_t va; - char *addr, *cp; + struct preloaded_file *fp; + struct fdt_header *hdr; + const char *addr; + char *cp; + + fdt_to_load = NULL; if (argc > 2) addr = argv[2]; @@ -799,15 +833,17 @@ fdt_cmd_addr(int argc, char *argv[]) return (CMD_ERROR); } - va = strtol(addr, &cp, 0); + hdr = (struct fdt_header *)strtoul(addr, &cp, 16); if (cp == addr) { sprintf(command_errbuf, "Invalid address: %s", addr); return (CMD_ERROR); } - if (fdt_load_dtb(va) != 0) - return (CMD_ERROR); + while ((fp = file_findfile(NULL, "dtb")) != NULL) { + file_discard(fp); + } + fdt_to_load = hdr; return (CMD_OK); } @@ -1484,6 +1520,7 @@ fdt_cmd_mkprop(int argc, char *argv[]) if (fdt_modprop(o, propname, value, 1)) return (CMD_ERROR); + COPYIN(fdtp, fdtp_va, fdtp_size); return (CMD_OK); } diff --git a/sys/boot/uboot/lib/copy.c b/sys/boot/uboot/lib/copy.c index 71b7a94..3adf7eb 100644 --- a/sys/boot/uboot/lib/copy.c +++ b/sys/boot/uboot/lib/copy.c @@ -66,7 +66,7 @@ uboot_vm_translate(vm_offset_t o) { */ } if (o > size) - panic("Address 0x%08jX bigger than size 0x%08X\n", + panic("Address offset 0x%08jX bigger than size 0x%08X\n", (intmax_t)o, size); return (void *)(start + o); } diff --git a/sys/boot/uboot/lib/elf_freebsd.c b/sys/boot/uboot/lib/elf_freebsd.c index 81407708..6b828d3 100644 --- a/sys/boot/uboot/lib/elf_freebsd.c +++ b/sys/boot/uboot/lib/elf_freebsd.c @@ -82,9 +82,9 @@ __elfN(uboot_exec)(struct preloaded_file *fp) entry = uboot_vm_translate(e->e_entry); printf("Kernel entry at 0x%x...\n", (unsigned)entry); - printf("Kernel args: %s\n", fp->f_args); dev_cleanup(); + printf("Kernel args: %s\n", fp->f_args); (*entry)((void *)mdp); panic("exec returned"); diff --git a/sys/boot/userboot/userboot/elf32_freebsd.c b/sys/boot/userboot/userboot/elf32_freebsd.c index 8489385..bb5b693 100644 --- a/sys/boot/userboot/userboot/elf32_freebsd.c +++ b/sys/boot/userboot/userboot/elf32_freebsd.c @@ -31,6 +31,7 @@ __FBSDID("$FreeBSD$"); #include <sys/exec.h> #include <sys/linker.h> #include <string.h> +#define _MACHINE_ELF_WANT_32BIT #include <i386/include/bootinfo.h> #include <i386/include/elf.h> #include <stand.h> diff --git a/sys/cam/ata/ata_pmp.c b/sys/cam/ata/ata_pmp.c index b2acdee..3c8bb51 100644 --- a/sys/cam/ata/ata_pmp.c +++ b/sys/cam/ata/ata_pmp.c @@ -595,7 +595,9 @@ pmpdone(struct cam_periph *periph, union ccb *done_ccb) * causes timeouts if external SEP is not connected * to PMP over I2C. */ - if (softc->pm_pid == 0x37261095 && softc->pm_ports == 6) + if ((softc->pm_pid == 0x37261095 || + softc->pm_pid == 0x38261095) && + softc->pm_ports == 6) softc->pm_ports = 5; /* diff --git a/sys/cam/scsi/scsi_da.c b/sys/cam/scsi/scsi_da.c index 7854215..0077997 100644 --- a/sys/cam/scsi/scsi_da.c +++ b/sys/cam/scsi/scsi_da.c @@ -607,6 +607,10 @@ static struct da_quirk_entry da_quirk_table[] = {T_DIRECT, SIP_MEDIA_REMOVABLE, "Sony", "Sony DSC", "*"}, /*quirks*/ DA_Q_NO_SYNC_CACHE | DA_Q_NO_PREVENT }, + { + {T_DIRECT, SIP_MEDIA_REMOVABLE, "Kingston", "DataTraveler G3", + "1.00"}, /*quirks*/ DA_Q_NO_PREVENT + }, /* ATA/SATA devices over SAS/USB/... */ { /* Hitachi Advanced Format (4k) drives */ diff --git a/sys/cddl/contrib/opensolaris/uts/common/dtrace/fasttrap.c b/sys/cddl/contrib/opensolaris/uts/common/dtrace/fasttrap.c index 4599a32..ad3b2d5 100644 --- a/sys/cddl/contrib/opensolaris/uts/common/dtrace/fasttrap.c +++ b/sys/cddl/contrib/opensolaris/uts/common/dtrace/fasttrap.c @@ -1124,14 +1124,12 @@ fasttrap_pid_disable(void *arg, dtrace_id_t id, void *parg) * provider lock as a point of mutual exclusion to prevent other * DTrace consumers from disabling this probe. */ - if ((p = pfind(probe->ftp_pid)) == NULL) { - mutex_exit(&provider->ftp_mtx); - return; - } + if ((p = pfind(probe->ftp_pid)) != NULL) { #ifdef __FreeBSD__ - _PHOLD(p); - PROC_UNLOCK(p); + _PHOLD(p); + PROC_UNLOCK(p); #endif + } /* * Disable all the associated tracepoints (for fully enabled probes). @@ -1168,7 +1166,8 @@ fasttrap_pid_disable(void *arg, dtrace_id_t id, void *parg) fasttrap_pid_cleanup(); #ifdef __FreeBSD__ - PRELE(p); + if (p != NULL) + PRELE(p); #endif if (!probe->ftp_enabled) return; diff --git a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/arc.c b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/arc.c index 202ec12..9081b95 100644 --- a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/arc.c +++ b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/arc.c @@ -3045,7 +3045,7 @@ arc_read(zio_t *pio, spa_t *spa, const blkptr_t *bp, arc_done_func_t *done, const zbookmark_t *zb) { arc_buf_hdr_t *hdr; - arc_buf_t *buf; + arc_buf_t *buf = NULL; kmutex_t *hash_lock; zio_t *rzio; uint64_t guid = spa_load_guid(spa); @@ -3127,7 +3127,7 @@ top: uint64_t size = BP_GET_LSIZE(bp); arc_callback_t *acb; vdev_t *vd = NULL; - uint64_t addr; + uint64_t addr = 0; boolean_t devw = B_FALSE; if (hdr == NULL) { @@ -3245,6 +3245,10 @@ top: cb->l2rcb_zb = *zb; cb->l2rcb_flags = zio_flags; + ASSERT(addr >= VDEV_LABEL_START_SIZE && + addr + size < vd->vdev_psize - + VDEV_LABEL_END_SIZE); + /* * l2arc read. The SCL_L2ARC lock will be * released by l2arc_read_done(). @@ -3440,8 +3444,8 @@ arc_release(arc_buf_t *buf, void *tag) if (l2hdr) { mutex_enter(&l2arc_buflist_mtx); hdr->b_l2hdr = NULL; - buf_size = hdr->b_size; } + buf_size = hdr->b_size; /* * Do we have more than one buf? @@ -4544,7 +4548,7 @@ l2arc_read_done(zio_t *zio) static list_t * l2arc_list_locked(int list_num, kmutex_t **lock) { - list_t *list; + list_t *list = NULL; int idx; ASSERT(list_num >= 0 && list_num < 2 * ARC_BUFC_NUMLISTS); diff --git a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/dmu.c b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/dmu.c index 3167d42..fc606d5 100644 --- a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/dmu.c +++ b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/dmu.c @@ -408,8 +408,7 @@ dmu_buf_hold_array_by_dnode(dnode_t *dn, uint64_t offset, uint64_t length, if (dn->dn_objset->os_dsl_dataset) dp = dn->dn_objset->os_dsl_dataset->ds_dir->dd_pool; - if (dp && dsl_pool_sync_context(dp)) - start = gethrtime(); + start = gethrtime(); zio = zio_root(dn->dn_objset->os_spa, NULL, NULL, ZIO_FLAG_CANFAIL); blkid = dbuf_whichblock(dn, offset); for (i = 0; i < nblks; i++) { diff --git a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/dmu_objset.c b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/dmu_objset.c index 06e08c9..3cc3c86 100644 --- a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/dmu_objset.c +++ b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/dmu_objset.c @@ -1323,7 +1323,8 @@ dmu_objset_userquota_get_ids(dnode_t *dn, boolean_t before, dmu_tx_t *tx) objset_t *os = dn->dn_objset; void *data = NULL; dmu_buf_impl_t *db = NULL; - uint64_t *user, *group; + uint64_t *user = NULL; + uint64_t *group = NULL; int flags = dn->dn_id_flags; int error; boolean_t have_spill = B_FALSE; diff --git a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/dsl_dataset.c b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/dsl_dataset.c index 2d71762..e8bf701 100644 --- a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/dsl_dataset.c +++ b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/dsl_dataset.c @@ -382,7 +382,7 @@ dsl_dataset_get_ref(dsl_pool_t *dp, uint64_t dsobj, void *tag, ds = dmu_buf_get_user(dbuf); if (ds == NULL) { - dsl_dataset_t *winner; + dsl_dataset_t *winner = NULL; ds = kmem_zalloc(sizeof (dsl_dataset_t), KM_SLEEP); ds->ds_dbuf = dbuf; @@ -467,11 +467,8 @@ dsl_dataset_get_ref(dsl_pool_t *dp, uint64_t dsobj, void *tag, ds->ds_reserved = ds->ds_quota = 0; } - if (err == 0) { - winner = dmu_buf_set_user_ie(dbuf, ds, &ds->ds_phys, - dsl_dataset_evict); - } - if (err || winner) { + if (err != 0 || (winner = dmu_buf_set_user_ie(dbuf, ds, + &ds->ds_phys, dsl_dataset_evict)) != NULL) { bplist_destroy(&ds->ds_pending_deadlist); dsl_deadlist_close(&ds->ds_deadlist); if (ds->ds_prev) diff --git a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/dsl_scan.c b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/dsl_scan.c index 05c1d80..8d7869f 100644 --- a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/dsl_scan.c +++ b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/dsl_scan.c @@ -1658,7 +1658,8 @@ dsl_scan_scrub_cb(dsl_pool_t *dp, zio_priority = ZIO_PRIORITY_SCRUB; needs_io = B_TRUE; scan_delay = zfs_scrub_delay; - } else if (scn->scn_phys.scn_func == POOL_SCAN_RESILVER) { + } else { + ASSERT3U(scn->scn_phys.scn_func, ==, POOL_SCAN_RESILVER); zio_flags |= ZIO_FLAG_RESILVER; zio_priority = ZIO_PRIORITY_RESILVER; needs_io = B_FALSE; diff --git a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/lzjb.c b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/lzjb.c index a2d9dab..f8d3061 100644 --- a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/lzjb.c +++ b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/lzjb.c @@ -38,6 +38,7 @@ #include <sys/zfs_context.h> #include <sys/types.h> +#include <sys/param.h> #define MATCH_BITS 6 #define MATCH_MIN 3 @@ -51,7 +52,8 @@ lzjb_compress(void *s_start, void *d_start, size_t s_len, size_t d_len, int n) { uchar_t *src = s_start; uchar_t *dst = d_start; - uchar_t *cpy, *copymap; + uchar_t *cpy; + uchar_t *copymap = NULL; int copymask = 1 << (NBBY - 1); int mlen, offset, hash; uint16_t *hp; @@ -100,7 +102,8 @@ lzjb_decompress(void *s_start, void *d_start, size_t s_len, size_t d_len, int n) uchar_t *src = s_start; uchar_t *dst = d_start; uchar_t *d_end = (uchar_t *)d_start + d_len; - uchar_t *cpy, copymap; + uchar_t *cpy; + uchar_t copymap = 0; int copymask = 1 << (NBBY - 1); while (dst < d_end) { diff --git a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/refcount.c b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/refcount.c index 6d8e2f2..860c8c6 100644 --- a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/refcount.c +++ b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/refcount.c @@ -110,7 +110,7 @@ refcount_count(refcount_t *rc) int64_t refcount_add_many(refcount_t *rc, uint64_t number, void *holder) { - reference_t *ref; + reference_t *ref = NULL; int64_t count; if (reference_tracking_enable) { diff --git a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/sa.c b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/sa.c index 7f209ea..1406d4d 100644 --- a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/sa.c +++ b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/sa.c @@ -660,7 +660,8 @@ sa_build_layouts(sa_handle_t *hdl, sa_bulk_attr_t *attr_desc, int attr_count, int buf_space; sa_attr_type_t *attrs, *attrs_start; int i, lot_count; - int hdrsize, spillhdrsize; + int hdrsize; + int spillhdrsize = 0; int used; dmu_object_type_t bonustype; sa_lot_t *lot; @@ -837,7 +838,7 @@ sa_attr_table_setup(objset_t *os, sa_attr_reg_t *reg_attrs, int count) { sa_os_t *sa = os->os_sa; uint64_t sa_attr_count = 0; - uint64_t sa_reg_count; + uint64_t sa_reg_count = 0; int error = 0; uint64_t attr_value; sa_attr_table_t *tb; @@ -1645,7 +1646,8 @@ sa_modify_attrs(sa_handle_t *hdl, sa_attr_type_t newattr, sa_bulk_attr_t *attr_desc; void *old_data[2]; int bonus_attr_count = 0; - int bonus_data_size, spill_data_size; + int bonus_data_size = 0; + int spill_data_size = 0; int spill_attr_count = 0; int error; uint16_t length; diff --git a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/spa.c b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/spa.c index c7ba961..bc73c9d 100644 --- a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/spa.c +++ b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/spa.c @@ -383,7 +383,7 @@ spa_prop_validate(spa_t *spa, nvlist_t *props) { nvpair_t *elem; int error = 0, reset_bootfs = 0; - uint64_t objnum; + uint64_t objnum = 0; boolean_t has_feature = B_FALSE; elem = NULL; @@ -1389,6 +1389,7 @@ spa_load_l2cache(spa_t *spa) newvdevs = kmem_alloc(nl2cache * sizeof (void *), KM_SLEEP); } else { nl2cache = 0; + newvdevs = NULL; } oldvdevs = sav->sav_vdevs; @@ -4702,7 +4703,7 @@ spa_vdev_detach(spa_t *spa, uint64_t guid, uint64_t pguid, int replace_done) vdev_t *rvd = spa->spa_root_vdev; vdev_t *vd, *pvd, *cvd, *tvd; boolean_t unspare = B_FALSE; - uint64_t unspare_guid; + uint64_t unspare_guid = 0; char *vdpath; ASSERT(spa_writeable(spa)); diff --git a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/vdev_raidz.c b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/vdev_raidz.c index 0e9fd6b..a157659 100644 --- a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/vdev_raidz.c +++ b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/vdev_raidz.c @@ -1198,7 +1198,8 @@ vdev_raidz_matrix_reconstruct(raidz_map_t *rm, int n, int nmissing, uint64_t ccount; uint8_t *dst[VDEV_RAIDZ_MAXPARITY]; uint64_t dcount[VDEV_RAIDZ_MAXPARITY]; - uint8_t log, val; + uint8_t log = 0; + uint8_t val; int ll; uint8_t *invlog[VDEV_RAIDZ_MAXPARITY]; uint8_t *p, *pp; diff --git a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zap_leaf.c b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zap_leaf.c index 19a795d..b867ac4 100644 --- a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zap_leaf.c +++ b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zap_leaf.c @@ -220,7 +220,7 @@ zap_leaf_array_create(zap_leaf_t *l, const char *buf, uint16_t chunk_head; uint16_t *chunkp = &chunk_head; int byten = 0; - uint64_t value; + uint64_t value = 0; int shift = (integer_size-1)*8; int len = num_integers; diff --git a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_byteswap.c b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_byteswap.c index acf632b..6048eb1 100644 --- a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_byteswap.c +++ b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_byteswap.c @@ -51,7 +51,7 @@ zfs_ace_byteswap(void *buf, size_t size, boolean_t zfs_layout) { caddr_t end; caddr_t ptr; - zfs_ace_t *zacep; + zfs_ace_t *zacep = NULL; ace_t *acep; uint16_t entry_type; size_t entry_size; diff --git a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_fuid.c b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_fuid.c index 5b54448..197e122 100644 --- a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_fuid.c +++ b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_fuid.c @@ -560,9 +560,9 @@ zfs_fuid_create(zfsvfs_t *zfsvfs, uint64_t id, cred_t *cr, uint32_t fuid_idx = FUID_INDEX(id); uint32_t rid; idmap_stat status; - uint64_t idx; + uint64_t idx = 0; zfs_fuid_t *zfuid = NULL; - zfs_fuid_info_t *fuidp; + zfs_fuid_info_t *fuidp = NULL; /* * If POSIX ID, or entry is already a FUID then @@ -587,6 +587,9 @@ zfs_fuid_create(zfsvfs_t *zfsvfs, uint64_t id, cred_t *cr, if (fuidp == NULL) return (UID_NOBODY); + VERIFY3U(type, >=, ZFS_OWNER); + VERIFY3U(type, <=, ZFS_ACE_GROUP); + switch (type) { case ZFS_ACE_USER: case ZFS_ACE_GROUP: @@ -603,7 +606,7 @@ zfs_fuid_create(zfsvfs_t *zfsvfs, uint64_t id, cred_t *cr, idx = FUID_INDEX(fuidp->z_fuid_group); break; }; - domain = fuidp->z_domain_table[idx -1]; + domain = fuidp->z_domain_table[idx - 1]; } else { if (type == ZFS_OWNER || type == ZFS_ACE_USER) status = kidmap_getsidbyuid(crgetzone(cr), id, diff --git a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_log.c b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_log.c index 29378d8..3c1a462 100644 --- a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_log.c +++ b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_log.c @@ -243,7 +243,7 @@ zfs_log_create(zilog_t *zilog, dmu_tx_t *tx, uint64_t txtype, itx_t *itx; lr_create_t *lr; lr_acl_create_t *lracl; - size_t aclsize; + size_t aclsize = (vsecp != NULL) ? vsecp->vsa_aclentsz : 0; size_t xvatsize = 0; size_t txsize; xvattr_t *xvap = (xvattr_t *)vap; @@ -273,7 +273,6 @@ zfs_log_create(zilog_t *zilog, dmu_tx_t *tx, uint64_t txtype, txsize = sizeof (*lr) + namesize + fuidsz + xvatsize; lrsize = sizeof (*lr); } else { - aclsize = (vsecp) ? vsecp->vsa_aclentsz : 0; txsize = sizeof (lr_acl_create_t) + namesize + fuidsz + ZIL_ACE_LENGTH(aclsize) + xvatsize; diff --git a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_rlock.c b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_rlock.c index 08f88b8..be56249 100644 --- a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_rlock.c +++ b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_rlock.c @@ -463,7 +463,7 @@ static void zfs_range_unlock_reader(znode_t *zp, rl_t *remove) { avl_tree_t *tree = &zp->z_range_avl; - rl_t *rl, *next; + rl_t *rl, *next = NULL; uint64_t len; /* diff --git a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_vfsops.c b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_vfsops.c index 456e5aa..92a4e6d 100644 --- a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_vfsops.c +++ b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_vfsops.c @@ -389,11 +389,18 @@ zfs_register_callbacks(vfs_t *vfsp) objset_t *os = NULL; zfsvfs_t *zfsvfs = NULL; uint64_t nbmand; - int readonly, do_readonly = B_FALSE; - int setuid, do_setuid = B_FALSE; - int exec, do_exec = B_FALSE; - int xattr, do_xattr = B_FALSE; - int atime, do_atime = B_FALSE; + boolean_t readonly = B_FALSE; + boolean_t do_readonly = B_FALSE; + boolean_t setuid = B_FALSE; + boolean_t do_setuid = B_FALSE; + boolean_t exec = B_FALSE; + boolean_t do_exec = B_FALSE; + boolean_t devices = B_FALSE; + boolean_t do_devices = B_FALSE; + boolean_t xattr = B_FALSE; + boolean_t do_xattr = B_FALSE; + boolean_t atime = B_FALSE; + boolean_t do_atime = B_FALSE; int error = 0; ASSERT(vfsp); diff --git a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_vnops.c b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_vnops.c index 9438266..7b060d8 100644 --- a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_vnops.c +++ b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_vnops.c @@ -644,7 +644,7 @@ zfs_read(vnode_t *vp, uio_t *uio, int ioflag, cred_t *cr, caller_context_t *ct) zfsvfs_t *zfsvfs = zp->z_zfsvfs; objset_t *os; ssize_t n, nbytes; - int error; + int error = 0; rl_t *rl; xuio_t *xuio = NULL; @@ -804,9 +804,9 @@ zfs_write(vnode_t *vp, uio_t *uio, int ioflag, cred_t *cr, caller_context_t *ct) ssize_t n, nbytes; rl_t *rl; int max_blksz = zfsvfs->z_max_blksz; - int error; + int error = 0; arc_buf_t *abuf; - iovec_t *aiov; + iovec_t *aiov = NULL; xuio_t *xuio = NULL; int i_iov = 0; int iovcnt = uio->uio_iovcnt; @@ -2476,6 +2476,7 @@ zfs_readdir(vnode_t *vp, uio_t *uio, cred_t *cr, int *eofp, int *ncookies, u_lon odp = (struct dirent64 *)outbuf; } else { bufsize = bytes_wanted; + outbuf = NULL; odp = (struct dirent64 *)iovp->iov_base; } eodp = (struct edirent *)odp; @@ -2959,7 +2960,7 @@ zfs_setattr(vnode_t *vp, vattr_t *vap, int flags, cred_t *cr, vattr_t oldva; xvattr_t tmpxvattr; uint_t mask = vap->va_mask; - uint_t saved_mask; + uint_t saved_mask = 0; uint64_t saved_mode; int trim_mask = 0; uint64_t new_mode; diff --git a/sys/conf/files b/sys/conf/files index 7790529..9015593 100644 --- a/sys/conf/files +++ b/sys/conf/files @@ -371,6 +371,7 @@ contrib/dev/acpica/components/hardware/hwxface.c optional acpi contrib/dev/acpica/components/hardware/hwxfsleep.c optional acpi contrib/dev/acpica/components/namespace/nsaccess.c optional acpi contrib/dev/acpica/components/namespace/nsalloc.c optional acpi +contrib/dev/acpica/components/namespace/nsconvert.c optional acpi contrib/dev/acpica/components/namespace/nsdump.c optional acpi contrib/dev/acpica/components/namespace/nseval.c optional acpi contrib/dev/acpica/components/namespace/nsinit.c optional acpi @@ -1741,7 +1742,6 @@ mwlboot.fw optional mwlfw \ no-obj no-implicit-rule \ clean "mwlboot.fw" dev/mxge/if_mxge.c optional mxge pci -dev/mxge/mxge_lro.c optional mxge pci dev/mxge/mxge_eth_z8e.c optional mxge pci dev/mxge/mxge_ethp_z8e.c optional mxge pci dev/mxge/mxge_rss_eth_z8e.c optional mxge pci diff --git a/sys/contrib/dev/acpica/changes.txt b/sys/contrib/dev/acpica/changes.txt index 5848335..cf247fa 100644 --- a/sys/contrib/dev/acpica/changes.txt +++ b/sys/contrib/dev/acpica/changes.txt @@ -1,6 +1,100 @@ ---------------------------------------- -17 January 2013. Summary of changes for version 20130117: +14 February 2013. Summary of changes for version 20130214: + +1) ACPICA Kernel-resident Subsystem: + +Fixed a possible regression on some hosts: Reinstated the safe return +macros (return_ACPI_STATUS, etc.) that ensure that the argument is +evaluated only once. Although these macros are not needed for the ACPICA +code itself, they are often used by ACPI-related host device drivers where +the safe feature may be necessary. + +Fixed several issues related to the ACPI 5.0 reduced hardware support +(SOC): Now ensure that if the platform declares itself as hardware-reduced +via the FADT, the following functions become NOOPs (and always return +AE_OK) because ACPI is always enabled by definition on these machines: + AcpiEnable + AcpiDisable + AcpiHwGetMode + AcpiHwSetMode + +Dynamic Object Repair: Implemented additional runtime repairs for +predefined name return values. Both of these repairs can simplify code in +the related device drivers that invoke these methods: +1) For the _STR and _MLS names, automatically repair/convert an ASCII +string to a Unicode buffer. +2) For the _CRS, _PRS, and _DMA names, return a resource descriptor with a +lone end tag descriptor in the following cases: A Return(0) was executed, +a null buffer was returned, or no object at all was returned (non-slack +mode only). Adds a new file, nsconvert.c +ACPICA BZ 998. Bob Moore, Lv Zheng. + +Resource Manager: Added additional code to prevent possible infinite loops +while traversing corrupted or ill-formed resource template buffers. Check +for zero-length resource descriptors in all code that loops through +resource templates (the length field is used to index through the +template). This change also hardens the external AcpiWalkResources and +AcpiWalkResourceBuffer interfaces. + +Local Cache Manager: Enhanced the main data structure to eliminate an +unnecessary mechanism to access the next object in the list. Actually +provides a small performance enhancement for hosts that use the local +ACPICA cache manager. Jung-uk Kim. + +Example Code and Data Size: These are the sizes for the OS-independent +acpica.lib produced by the Microsoft Visual C++ 9.0 32-bit compiler. The +debug version of the code includes the debug output trace mechanism and +has a much larger code and data size. + + Previous Release: + Non-Debug Version: 94.5K Code, 25.4K Data, 119.9K Total + Debug Version: 182.3K Code, 75.0K Data, 257.3K Total + Current Release: + Non-Debug Version: 95.0K Code, 25.9K Data, 120.9K Total + Debug Version: 182.9K Code, 75.6K Data, 258.5K Total + + +2) iASL Compiler/Disassembler and Tools: + +iASL/Disassembler: Fixed several issues with the definition of the ACPI +5.0 RASF table (RAS Feature Table). This change incorporates late changes +that were made to the ACPI 5.0 specification. + +iASL/Disassembler: Added full support for the following new ACPI tables: + 1) The MTMR table (MID Timer Table) + 2) The VRTC table (Virtual Real Time Clock Table). +Includes header file, disassembler, table compiler, and template support +for both tables. + +iASL: Implemented compile-time validation of package objects returned by +predefined names. This new feature validates static package objects +returned by the various predefined names defined to return packages. Both +object types and package lengths are validated, for both parent packages +and sub-packages, if any. The code is similar in structure and behavior to +the runtime repair mechanism within the AML interpreter and uses the +existing predefined name information table. Adds a new file, aslprepkg.c. +ACPICA BZ 938. +iASL: Implemented auto-detection of binary ACPI tables for disassembly. +This feature detects a binary file with a valid ACPI table header and +invokes the disassembler automatically. Eliminates the need to +specifically invoke the disassembler with the -d option. ACPICA BZ 862. + +iASL/Disassembler: Added several warnings for the case where there are +unresolved control methods during the disassembly. This can potentially +cause errors when the output file is compiled, because the disassembler +assumes zero method arguments in these cases (it cannot determine the +actual number of arguments without resolution/definition of the method). + +Debugger: Added support to display all resources with a single command. +Invocation of the resources command with no arguments will now display all +resources within the current namespace. + +AcpiHelp: Added descriptive text for each ACPICA exception code displayed +via the -e option. + +---------------------------------------- +17 January 2013. Summary of changes for version 20130117: 1) ACPICA Kernel-resident Subsystem: diff --git a/sys/contrib/dev/acpica/common/adisasm.c b/sys/contrib/dev/acpica/common/adisasm.c index 42befa8..dbef766 100644 --- a/sys/contrib/dev/acpica/common/adisasm.c +++ b/sys/contrib/dev/acpica/common/adisasm.c @@ -372,7 +372,7 @@ AdAmlDisassemble ( } /* - * Output: ASL code. Redirect to a file if requested + * Output: ASL code. Redirect to a file if requested */ if (OutToFile) { @@ -540,11 +540,6 @@ Cleanup: ACPI_FREE (Table); } - if (DisasmFilename) - { - ACPI_FREE (DisasmFilename); - } - if (OutToFile && File) { if (AslCompilerdebug) /* Display final namespace, with transforms */ @@ -667,7 +662,7 @@ AdCreateTableHeader ( AcpiOsPrintf (" * OEM Revision 0x%8.8X (%u)\n", Table->OemRevision, Table->OemRevision); AcpiOsPrintf (" * Compiler ID \"%.4s\"\n", Table->AslCompilerId); AcpiOsPrintf (" * Compiler Version 0x%8.8X (%u)\n", Table->AslCompilerRevision, Table->AslCompilerRevision); - AcpiOsPrintf (" */\n\n"); + AcpiOsPrintf (" */\n"); /* Create AML output filename based on input filename */ diff --git a/sys/contrib/dev/acpica/common/adwalk.c b/sys/contrib/dev/acpica/common/adwalk.c index f801f10..da790ed 100644 --- a/sys/contrib/dev/acpica/common/adwalk.c +++ b/sys/contrib/dev/acpica/common/adwalk.c @@ -837,7 +837,7 @@ AcpiDmXrefDescendingOp ( } } - AcpiDmAddToExternalList (Op, Path, (UINT8) ObjectType2, ParamCount); + AcpiDmAddToExternalList (Op, Path, (UINT8) ObjectType2, ParamCount | 0x80); Op->Common.Node = Node; } else diff --git a/sys/contrib/dev/acpica/common/dmextern.c b/sys/contrib/dev/acpica/common/dmextern.c index 67f13f7..e60924c 100644 --- a/sys/contrib/dev/acpica/common/dmextern.c +++ b/sys/contrib/dev/acpica/common/dmextern.c @@ -46,6 +46,7 @@ #include <contrib/dev/acpica/include/amlcode.h> #include <contrib/dev/acpica/include/acnamesp.h> #include <contrib/dev/acpica/include/acdisasm.h> +#include <stdio.h> /* @@ -373,6 +374,7 @@ AcpiDmAddToExternalList ( ACPI_EXTERNAL_LIST *NextExternal; ACPI_EXTERNAL_LIST *PrevExternal = NULL; ACPI_STATUS Status; + BOOLEAN Resolved = FALSE; if (!Path) @@ -380,6 +382,15 @@ AcpiDmAddToExternalList ( return; } + if (Type == ACPI_TYPE_METHOD) + { + if (Value & 0x80) + { + Resolved = TRUE; + } + Value &= 0x07; + } + /* * We don't want External() statements to contain a leading '\'. * This prevents duplicate external statements of the form: @@ -464,6 +475,7 @@ AcpiDmAddToExternalList ( NewExternal->Path = ExternalPath; NewExternal->Type = Type; NewExternal->Value = Value; + NewExternal->Resolved = Resolved; NewExternal->Length = (UINT16) ACPI_STRLEN (ExternalPath); /* Was the external path with parent prefix normalized to a fullpath? */ @@ -684,6 +696,29 @@ AcpiDmEmitExternals ( } /* + * Determine the number of control methods in the external list, and + * also how many of those externals were resolved via the namespace. + */ + NextExternal = AcpiGbl_ExternalList; + while (NextExternal) + { + if (NextExternal->Type == ACPI_TYPE_METHOD) + { + AcpiGbl_NumExternalMethods++; + if (NextExternal->Resolved) + { + AcpiGbl_ResolvedExternalMethods++; + } + } + + NextExternal = NextExternal->Next; + } + + /* Check if any control methods were unresolved */ + + AcpiDmUnresolvedWarning (1); + + /* * Walk the list of externals (unresolved references) * found during the AML parsing */ @@ -695,8 +730,17 @@ AcpiDmEmitExternals ( if (AcpiGbl_ExternalList->Type == ACPI_TYPE_METHOD) { - AcpiOsPrintf (") // %u Arguments\n", - AcpiGbl_ExternalList->Value); + if (AcpiGbl_ExternalList->Resolved) + { + AcpiOsPrintf (") // %u Arguments\n", + AcpiGbl_ExternalList->Value); + } + else + { + AcpiOsPrintf (") // Warning: unresolved Method, " + "assuming %u arguments (may be incorrect, see warning above)\n", + AcpiGbl_ExternalList->Value); + } } else { @@ -718,3 +762,173 @@ AcpiDmEmitExternals ( AcpiOsPrintf ("\n"); } + + +/******************************************************************************* + * + * FUNCTION: AcpiDmUnresolvedWarning + * + * PARAMETERS: Type - Where to output the warning. + * 0 means write to stderr + * 1 means write to AcpiOsPrintf + * + * RETURN: None + * + * DESCRIPTION: Issue warning message if there are unresolved external control + * methods within the disassembly. + * + ******************************************************************************/ + +#if 0 +Summary of the external control method problem: + +When the -e option is used with disassembly, the various SSDTs are simply +loaded into a global namespace for the disassembler to use in order to +resolve control method references (invocations). + +The disassembler tracks any such references, and will emit an External() +statement for these types of methods, with the proper number of arguments . + +Without the SSDTs, the AML does not contain enough information to properly +disassemble the control method invocation -- because the disassembler does +not know how many arguments to parse. + +An example: Assume we have two control methods. ABCD has one argument, and +EFGH has zero arguments. Further, we have two additional control methods +that invoke ABCD and EFGH, named T1 and T2: + + Method (ABCD, 1) + { + } + Method (EFGH, 0) + { + } + Method (T1) + { + ABCD (Add (2, 7, Local0)) + } + Method (T2) + { + EFGH () + Add (2, 7, Local0) + } + +Here is the AML code that is generated for T1 and T2: + + 185: Method (T1) + +0000034C: 14 10 54 31 5F 5F 00 ... "..T1__." + + 186: { + 187: ABCD (Add (2, 7, Local0)) + +00000353: 41 42 43 44 ............ "ABCD" +00000357: 72 0A 02 0A 07 60 ...... "r....`" + + 188: } + + 190: Method (T2) + +0000035D: 14 10 54 32 5F 5F 00 ... "..T2__." + + 191: { + 192: EFGH () + +00000364: 45 46 47 48 ............ "EFGH" + + 193: Add (2, 7, Local0) + +00000368: 72 0A 02 0A 07 60 ...... "r....`" + 194: } + +Note that the AML code for T1 and T2 is essentially identical. When +disassembling this code, the methods ABCD and EFGH must be known to the +disassembler, otherwise it does not know how to handle the method invocations. + +In other words, if ABCD and EFGH are actually external control methods +appearing in an SSDT, the disassembler does not know what to do unless +the owning SSDT has been loaded via the -e option. +#endif + +void +AcpiDmUnresolvedWarning ( + UINT8 Type) +{ + + if (!AcpiGbl_NumExternalMethods) + { + return; + } + + if (Type) + { + if (!AcpiGbl_ExternalFileList) + { + /* The -e option was not specified */ + + AcpiOsPrintf (" /*\n" + " * iASL Warning: There were %u external control methods found during\n" + " * disassembly, but additional ACPI tables to resolve these externals\n" + " * were not specified. This resulting disassembler output file may not\n" + " * compile because the disassembler did not know how many arguments\n" + " * to assign to these methods. To specify the tables needed to resolve\n" + " * external control method references, use the one of the following\n" + " * example iASL invocations:\n" + " * iasl -e <ssdt1.aml,ssdt2.aml...> -d <dsdt.aml>\n" + " * iasl -e <dsdt.aml,ssdt2.aml...> -d <ssdt1.aml>\n" + " */\n", + AcpiGbl_NumExternalMethods); + } + else if (AcpiGbl_NumExternalMethods != AcpiGbl_ResolvedExternalMethods) + { + /* The -e option was specified, but there are still some unresolved externals */ + + AcpiOsPrintf (" /*\n" + " * iASL Warning: There were %u external control methods found during\n" + " * disassembly, but only %u %s resolved (%u unresolved). Additional\n" + " * ACPI tables are required to properly disassemble the code. This\n" + " * resulting disassembler output file may not compile because the\n" + " * disassembler did not know how many arguments to assign to the\n" + " * unresolved methods.\n" + " */\n", + AcpiGbl_NumExternalMethods, AcpiGbl_ResolvedExternalMethods, + (AcpiGbl_ResolvedExternalMethods > 1 ? "were" : "was"), + (AcpiGbl_NumExternalMethods - AcpiGbl_ResolvedExternalMethods)); + } + } + else + { + if (!AcpiGbl_ExternalFileList) + { + /* The -e option was not specified */ + + fprintf (stderr, "\n" + "iASL Warning: There were %u external control methods found during\n" + "disassembly, but additional ACPI tables to resolve these externals\n" + "were not specified. The resulting disassembler output file may not\n" + "compile because the disassembler did not know how many arguments\n" + "to assign to these methods. To specify the tables needed to resolve\n" + "external control method references, use the one of the following\n" + "example iASL invocations:\n" + " iasl -e <ssdt1.aml,ssdt2.aml...> -d <dsdt.aml>\n" + " iasl -e <dsdt.aml,ssdt2.aml...> -d <ssdt1.aml>\n", + AcpiGbl_NumExternalMethods); + } + else if (AcpiGbl_NumExternalMethods != AcpiGbl_ResolvedExternalMethods) + { + /* The -e option was specified, but there are still some unresolved externals */ + + fprintf (stderr, "\n" + "iASL Warning: There were %u external control methods found during\n" + "disassembly, but only %u %s resolved (%u unresolved). Additional\n" + "ACPI tables are required to properly disassemble the code. The\n" + "resulting disassembler output file may not compile because the\n" + "disassembler did not know how many arguments to assign to the\n" + "unresolved methods.\n", + AcpiGbl_NumExternalMethods, AcpiGbl_ResolvedExternalMethods, + (AcpiGbl_ResolvedExternalMethods > 1 ? "were" : "was"), + (AcpiGbl_NumExternalMethods - AcpiGbl_ResolvedExternalMethods)); + } + } + +} diff --git a/sys/contrib/dev/acpica/common/dmtable.c b/sys/contrib/dev/acpica/common/dmtable.c index e569b63..297a3d5 100644 --- a/sys/contrib/dev/acpica/common/dmtable.c +++ b/sys/contrib/dev/acpica/common/dmtable.c @@ -299,6 +299,7 @@ ACPI_DMTABLE_DATA AcpiDmTableData[] = {ACPI_SIG_MCHI, AcpiDmTableInfoMchi, NULL, NULL, TemplateMchi, "Management Controller Host Interface table"}, {ACPI_SIG_MPST, AcpiDmTableInfoMpst, AcpiDmDumpMpst, DtCompileMpst, TemplateMpst, "Memory Power State Table"}, {ACPI_SIG_MSCT, NULL, AcpiDmDumpMsct, DtCompileMsct, TemplateMsct, "Maximum System Characteristics Table"}, + {ACPI_SIG_MTMR, NULL, AcpiDmDumpMtmr, DtCompileMtmr, TemplateMtmr, "MID Timer Table"}, {ACPI_SIG_PCCT, NULL, AcpiDmDumpPcct, NULL, NULL, "Platform Communications Channel Table"}, {ACPI_SIG_PMTT, NULL, AcpiDmDumpPmtt, DtCompilePmtt, TemplatePmtt, "Platform Memory Topology Table"}, {ACPI_SIG_RSDT, NULL, AcpiDmDumpRsdt, DtCompileRsdt, TemplateRsdt, "Root System Description Table"}, @@ -312,6 +313,7 @@ ACPI_DMTABLE_DATA AcpiDmTableData[] = {ACPI_SIG_TCPA, AcpiDmTableInfoTcpa, NULL, NULL, TemplateTcpa, "Trusted Computing Platform Alliance table"}, {ACPI_SIG_TPM2, AcpiDmTableInfoTpm2, NULL, NULL, TemplateTpm2, "Trusted Platform Module hardware interface table"}, {ACPI_SIG_UEFI, AcpiDmTableInfoUefi, NULL, DtCompileUefi, TemplateUefi, "UEFI Boot Optimization Table"}, + {ACPI_SIG_VRTC, AcpiDmTableInfoVrtc, AcpiDmDumpVrtc, DtCompileVrtc, TemplateVrtc, "Virtual Real-Time Clock Table"}, {ACPI_SIG_WAET, AcpiDmTableInfoWaet, NULL, NULL, TemplateWaet, "Windows ACPI Emulated Devices Table"}, {ACPI_SIG_WDAT, NULL, AcpiDmDumpWdat, DtCompileWdat, TemplateWdat, "Watchdog Action Table"}, {ACPI_SIG_WDDT, AcpiDmTableInfoWddt, NULL, NULL, TemplateWddt, "Watchdog Description Table"}, @@ -475,6 +477,8 @@ AcpiDmDumpDataTable ( { AcpiOsPrintf ("\n**** Unknown ACPI table type [%4.4s]\n\n", Table->Signature); + fprintf (stderr, "Unknown ACPI table signature [%4.4s], decoding header only\n", + Table->Signature); } } else if (TableData->TableHandler) diff --git a/sys/contrib/dev/acpica/common/dmtbdump.c b/sys/contrib/dev/acpica/common/dmtbdump.c index ac5ee90..7518810 100644 --- a/sys/contrib/dev/acpica/common/dmtbdump.c +++ b/sys/contrib/dev/acpica/common/dmtbdump.c @@ -1796,6 +1796,58 @@ AcpiDmDumpMsct ( /******************************************************************************* * + * FUNCTION: AcpiDmDumpMtmr + * + * PARAMETERS: Table - A MTMR table + * + * RETURN: None + * + * DESCRIPTION: Format the contents of a MTMR + * + ******************************************************************************/ + +void +AcpiDmDumpMtmr ( + ACPI_TABLE_HEADER *Table) +{ + ACPI_STATUS Status; + UINT32 Offset = sizeof (ACPI_TABLE_MTMR); + ACPI_MTMR_ENTRY *SubTable; + + + /* Main table */ + + Status = AcpiDmDumpTable (Table->Length, 0, Table, 0, AcpiDmTableInfoMtmr); + if (ACPI_FAILURE (Status)) + { + return; + } + + /* Sub-tables */ + + SubTable = ACPI_ADD_PTR (ACPI_MTMR_ENTRY, Table, Offset); + while (Offset < Table->Length) + { + /* Common sub-table header */ + + AcpiOsPrintf ("\n"); + Status = AcpiDmDumpTable (Table->Length, Offset, SubTable, + sizeof (ACPI_MTMR_ENTRY), AcpiDmTableInfoMtmr0); + if (ACPI_FAILURE (Status)) + { + return; + } + + /* Point to next sub-table */ + + Offset += sizeof (ACPI_MTMR_ENTRY); + SubTable = ACPI_ADD_PTR (ACPI_MTMR_ENTRY, SubTable, sizeof (ACPI_MTMR_ENTRY)); + } +} + + +/******************************************************************************* + * * FUNCTION: AcpiDmDumpPcct * * PARAMETERS: Table - A PCCT table @@ -2378,6 +2430,58 @@ NextSubTable: /******************************************************************************* * + * FUNCTION: AcpiDmDumpVrtc + * + * PARAMETERS: Table - A VRTC table + * + * RETURN: None + * + * DESCRIPTION: Format the contents of a VRTC + * + ******************************************************************************/ + +void +AcpiDmDumpVrtc ( + ACPI_TABLE_HEADER *Table) +{ + ACPI_STATUS Status; + UINT32 Offset = sizeof (ACPI_TABLE_VRTC); + ACPI_VRTC_ENTRY *SubTable; + + + /* Main table */ + + Status = AcpiDmDumpTable (Table->Length, 0, Table, 0, AcpiDmTableInfoVrtc); + if (ACPI_FAILURE (Status)) + { + return; + } + + /* Sub-tables */ + + SubTable = ACPI_ADD_PTR (ACPI_VRTC_ENTRY, Table, Offset); + while (Offset < Table->Length) + { + /* Common sub-table header */ + + AcpiOsPrintf ("\n"); + Status = AcpiDmDumpTable (Table->Length, Offset, SubTable, + sizeof (ACPI_VRTC_ENTRY), AcpiDmTableInfoVrtc0); + if (ACPI_FAILURE (Status)) + { + return; + } + + /* Point to next sub-table */ + + Offset += sizeof (ACPI_VRTC_ENTRY); + SubTable = ACPI_ADD_PTR (ACPI_VRTC_ENTRY, SubTable, sizeof (ACPI_VRTC_ENTRY)); + } +} + + +/******************************************************************************* + * * FUNCTION: AcpiDmDumpWdat * * PARAMETERS: Table - A WDAT table diff --git a/sys/contrib/dev/acpica/common/dmtbinfo.c b/sys/contrib/dev/acpica/common/dmtbinfo.c index 54bd5c2..dd67774 100644 --- a/sys/contrib/dev/acpica/common/dmtbinfo.c +++ b/sys/contrib/dev/acpica/common/dmtbinfo.c @@ -179,6 +179,7 @@ #define ACPI_MPST1_OFFSET(f) (UINT16) ACPI_OFFSET (ACPI_MPST_DATA_HDR,f) #define ACPI_MPST2_OFFSET(f) (UINT16) ACPI_OFFSET (ACPI_MPST_POWER_DATA,f) #define ACPI_MSCT0_OFFSET(f) (UINT16) ACPI_OFFSET (ACPI_MSCT_PROXIMITY,f) +#define ACPI_MTMR0_OFFSET(f) (UINT16) ACPI_OFFSET (ACPI_MTMR_ENTRY,f) #define ACPI_PCCT0_OFFSET(f) (UINT16) ACPI_OFFSET (ACPI_PCCT_SUBSPACE,f) #define ACPI_PMTT0_OFFSET(f) (UINT16) ACPI_OFFSET (ACPI_PMTT_SOCKET,f) #define ACPI_PMTT1_OFFSET(f) (UINT16) ACPI_OFFSET (ACPI_PMTT_CONTROLLER,f) @@ -195,6 +196,7 @@ #define ACPI_SRAT0_OFFSET(f) (UINT16) ACPI_OFFSET (ACPI_SRAT_CPU_AFFINITY,f) #define ACPI_SRAT1_OFFSET(f) (UINT16) ACPI_OFFSET (ACPI_SRAT_MEM_AFFINITY,f) #define ACPI_SRAT2_OFFSET(f) (UINT16) ACPI_OFFSET (ACPI_SRAT_X2APIC_CPU_AFFINITY,f) +#define ACPI_VRTC0_OFFSET(f) (UINT16) ACPI_OFFSET (ACPI_VRTC_ENTRY,f) #define ACPI_WDAT0_OFFSET(f) (UINT16) ACPI_OFFSET (ACPI_WDAT_ENTRY,f) /* @@ -1644,6 +1646,28 @@ ACPI_DMTABLE_INFO AcpiDmTableInfoMsct0[] = /******************************************************************************* * + * MTMR - MID Timer Table + * + ******************************************************************************/ + +ACPI_DMTABLE_INFO AcpiDmTableInfoMtmr[] = +{ + ACPI_DMT_TERMINATOR +}; + +/* MTMR Subtables - MTMR Entry */ + +ACPI_DMTABLE_INFO AcpiDmTableInfoMtmr0[] = +{ + {ACPI_DMT_GAS, ACPI_MTMR0_OFFSET (PhysicalAddress), "PhysicalAddress", 0}, + {ACPI_DMT_UINT32, ACPI_MTMR0_OFFSET (Frequency), "Frequency", 0}, + {ACPI_DMT_UINT32, ACPI_MTMR0_OFFSET (Irq), "IRQ", 0}, + ACPI_DMT_TERMINATOR +}; + + +/******************************************************************************* + * * PCCT - Platform Communications Channel Table (ACPI 5.0) * ******************************************************************************/ @@ -2035,6 +2059,27 @@ ACPI_DMTABLE_INFO AcpiDmTableInfoUefi[] = /******************************************************************************* * + * VRTC - Virtual Real Time Clock Table + * + ******************************************************************************/ + +ACPI_DMTABLE_INFO AcpiDmTableInfoVrtc[] = +{ + ACPI_DMT_TERMINATOR +}; + +/* VRTC Subtables - VRTC Entry */ + +ACPI_DMTABLE_INFO AcpiDmTableInfoVrtc0[] = +{ + {ACPI_DMT_GAS, ACPI_VRTC0_OFFSET (PhysicalAddress), "PhysicalAddress", 0}, + {ACPI_DMT_UINT32, ACPI_VRTC0_OFFSET (Irq), "IRQ", 0}, + ACPI_DMT_TERMINATOR +}; + + +/******************************************************************************* + * * WAET - Windows ACPI Emulated devices Table * ******************************************************************************/ diff --git a/sys/contrib/dev/acpica/compiler/aslcompile.c b/sys/contrib/dev/acpica/compiler/aslcompile.c index 6d4c466..23579dc 100644 --- a/sys/contrib/dev/acpica/compiler/aslcompile.c +++ b/sys/contrib/dev/acpica/compiler/aslcompile.c @@ -42,6 +42,7 @@ */ #include <contrib/dev/acpica/compiler/aslcompiler.h> +#include <contrib/dev/acpica/compiler/dtcompiler.h> #include <stdio.h> #include <time.h> @@ -343,6 +344,89 @@ FlConsumeNewComment ( /******************************************************************************* * + * FUNCTION: FlCheckForAcpiTable + * + * PARAMETERS: Handle - Open input file + * + * RETURN: Status + * + * DESCRIPTION: Determine if a file seems to be a binary ACPI table, via the + * following checks on what would be the table header: + * 0) File must be at least as long as an ACPI_TABLE_HEADER + * 1) The header length field must match the file size + * 2) Signature, OemId, OemTableId, AslCompilerId must be ASCII + * + ******************************************************************************/ + +ACPI_STATUS +FlCheckForAcpiTable ( + FILE *Handle) +{ + ACPI_TABLE_HEADER Table; + UINT32 FileSize; + size_t Actual; + UINT32 i; + + + /* Read a potential table header */ + + Actual = fread (&Table, 1, sizeof (ACPI_TABLE_HEADER), Handle); + fseek (Handle, 0, SEEK_SET); + + if (Actual < sizeof (ACPI_TABLE_HEADER)) + { + return (AE_ERROR); + } + + /* Header length field must match the file size */ + + FileSize = DtGetFileSize (Handle); + if (Table.Length != FileSize) + { + return (AE_ERROR); + } + + /* + * These fields must be ASCII: + * Signature, OemId, OemTableId, AslCompilerId. + * We allow a NULL terminator in OemId and OemTableId. + */ + for (i = 0; i < ACPI_NAME_SIZE; i++) + { + if (!ACPI_IS_ASCII ((UINT8) Table.Signature[i])) + { + return (AE_ERROR); + } + + if (!ACPI_IS_ASCII ((UINT8) Table.AslCompilerId[i])) + { + return (AE_ERROR); + } + } + + for (i = 0; (i < ACPI_OEM_ID_SIZE) && (Table.OemId[i]); i++) + { + if (!ACPI_IS_ASCII ((UINT8) Table.OemId[i])) + { + return (AE_ERROR); + } + } + + for (i = 0; (i < ACPI_OEM_TABLE_ID_SIZE) && (Table.OemTableId[i]); i++) + { + if (!ACPI_IS_ASCII ((UINT8) Table.OemTableId[i])) + { + return (AE_ERROR); + } + } + + printf ("Binary file appears to be a valid ACPI table, disassembling\n"); + return (AE_OK); +} + + +/******************************************************************************* + * * FUNCTION: FlCheckForAscii * * PARAMETERS: Handle - Open input file diff --git a/sys/contrib/dev/acpica/compiler/aslcompiler.h b/sys/contrib/dev/acpica/compiler/aslcompiler.h index d772e8f..92ee1ca 100644 --- a/sys/contrib/dev/acpica/compiler/aslcompiler.h +++ b/sys/contrib/dev/acpica/compiler/aslcompiler.h @@ -160,6 +160,10 @@ CmCleanupAndExit ( void); ACPI_STATUS +FlCheckForAcpiTable ( + FILE *Handle); + +ACPI_STATUS FlCheckForAscii ( FILE *Handle, char *Filename, @@ -509,12 +513,28 @@ ApCheckForPredefinedObject ( ACPI_PARSE_OBJECT *Op, char *Name); +ACPI_STATUS +ApCheckObjectType ( + const char *PredefinedName, + ACPI_PARSE_OBJECT *Op, + UINT32 ExpectedBtypes, + UINT32 PackageIndex); + void ApDisplayReservedNames ( void); /* + * aslprepkg - ACPI predefined names support for packages + */ +void +ApCheckPackage ( + ACPI_PARSE_OBJECT *ParentOp, + const ACPI_PREDEFINED_INFO *Predefined); + + +/* * asltransform - parse tree transformations */ ACPI_STATUS diff --git a/sys/contrib/dev/acpica/compiler/asldefine.h b/sys/contrib/dev/acpica/compiler/asldefine.h index 7c8bd66..75c8fad 100644 --- a/sys/contrib/dev/acpica/compiler/asldefine.h +++ b/sys/contrib/dev/acpica/compiler/asldefine.h @@ -125,8 +125,9 @@ /* Types for input files */ #define ASL_INPUT_TYPE_BINARY 0 -#define ASL_INPUT_TYPE_ASCII_ASL 1 -#define ASL_INPUT_TYPE_ASCII_DATA 2 +#define ASL_INPUT_TYPE_ACPI_TABLE 1 +#define ASL_INPUT_TYPE_ASCII_ASL 2 +#define ASL_INPUT_TYPE_ASCII_DATA 3 /* Misc */ diff --git a/sys/contrib/dev/acpica/compiler/aslfiles.c b/sys/contrib/dev/acpica/compiler/aslfiles.c index a525fc2..443b56c 100644 --- a/sys/contrib/dev/acpica/compiler/aslfiles.c +++ b/sys/contrib/dev/acpica/compiler/aslfiles.c @@ -513,6 +513,13 @@ FlOpenMiscOutputFiles ( char *Filename; + /* All done for disassembler */ + + if (Gbl_FileType == ASL_INPUT_TYPE_ACPI_TABLE) + { + return (AE_OK); + } + /* Create/Open a hex output file if asked */ if (Gbl_HexOutputFlag) diff --git a/sys/contrib/dev/acpica/compiler/aslmain.c b/sys/contrib/dev/acpica/compiler/aslmain.c index 1a05b9f..af89faa 100644 --- a/sys/contrib/dev/acpica/compiler/aslmain.c +++ b/sys/contrib/dev/acpica/compiler/aslmain.c @@ -111,7 +111,8 @@ AslDoResponseFile ( * * RETURN: None * - * DESCRIPTION: Display option help message + * DESCRIPTION: Display option help message. + * Optional items in square brackets. * ******************************************************************************/ @@ -132,7 +133,7 @@ Options ( ACPI_OPTION ("-P", "Preprocess only and create preprocessor output file (*.i)"); ACPI_OPTION ("-Pn", "Disable preprocessor"); - printf ("\nGeneral Output:\n"); + printf ("\nGeneral Processing:\n"); ACPI_OPTION ("-p <prefix>", "Specify path/filename prefix for all output files"); ACPI_OPTION ("-va", "Disable all errors and warnings (summary only)"); ACPI_OPTION ("-vi", "Less verbose errors and warnings for use with IDEs"); @@ -142,12 +143,7 @@ Options ( ACPI_OPTION ("-w1 -w2 -w3", "Set warning reporting level"); ACPI_OPTION ("-we", "Report warnings as errors"); - printf ("\nAML and Data Output Files:\n"); - ACPI_OPTION ("-sa -sc", "Create assembler or C source file (*.asm or *.c)"); - ACPI_OPTION ("-ia -ic", "Create assembler or C include file (*.inc or *.h)"); - ACPI_OPTION ("-ta -tc -ts", "Create assembler, C, or ASL hex table (*.hex)"); - - printf ("\nAML Code Generation:\n"); + printf ("\nAML Code Generation (*.aml):\n"); ACPI_OPTION ("-oa", "Disable all optimizations (compatibility mode)"); ACPI_OPTION ("-of", "Disable constant folding"); ACPI_OPTION ("-oi", "Disable integer optimization to Zero/One/Ones"); @@ -156,22 +152,28 @@ Options ( ACPI_OPTION ("-in", "Ignore NoOp operators"); ACPI_OPTION ("-r <revision>", "Override table header Revision (1-255)"); - printf ("\nASL Listing Files:\n"); + printf ("\nOptional Source Code Output Files:\n"); + ACPI_OPTION ("-sc -sa", "Create source file in C or assembler (*.c or *.asm)"); + ACPI_OPTION ("-ic -ia", "Create include file in C or assembler (*.h or *.inc)"); + ACPI_OPTION ("-tc -ta -ts", "Create hex AML table in C, assembler, or ASL (*.hex)"); + + printf ("\nOptional Listing Files:\n"); ACPI_OPTION ("-l", "Create mixed listing file (ASL source and AML) (*.lst)"); ACPI_OPTION ("-ln", "Create namespace file (*.nsp)"); ACPI_OPTION ("-ls", "Create combined source file (expanded includes) (*.src)"); - printf ("\nACPI Data Tables:\n"); - ACPI_OPTION ("-G", "Compile custom table containing generic operators"); - ACPI_OPTION ("-vt", "Create verbose templates (full disassembly)"); + printf ("\nData Table Compiler:\n"); + ACPI_OPTION ("-G", "Compile custom table that contains generic operators"); + ACPI_OPTION ("-vt", "Create verbose template files (full disassembly)"); printf ("\nAML Disassembler:\n"); - ACPI_OPTION ("-d [file]", "Disassemble or decode binary ACPI table to file (*.dsl)"); - ACPI_OPTION ("-da [f1,f2]", "Disassemble multiple tables from single namespace"); + ACPI_OPTION ("-d <f1,f2>", "Disassemble or decode binary ACPI tables to file (*.dsl)"); + ACPI_OPTION ("", " (Optional, file type is automatically detected)"); + ACPI_OPTION ("-da <f1,f2>", "Disassemble multiple tables from single namespace"); ACPI_OPTION ("-db", "Do not translate Buffers to Resource Templates"); - ACPI_OPTION ("-dc [file]", "Disassemble AML and immediately compile it"); - ACPI_OPTION ("", "(Obtain DSDT from current system if no input file)"); - ACPI_OPTION ("-e [f1,f2]", "Include ACPI table(s) for external symbol resolution"); + ACPI_OPTION ("-dc <f1,f2>", "Disassemble AML and immediately compile it"); + ACPI_OPTION ("", " (Obtain DSDT from current system if no input file)"); + ACPI_OPTION ("-e <f1,f2>", "Include ACPI table(s) for external symbol resolution"); ACPI_OPTION ("-g", "Get ACPI tables and write to files (*.dat)"); ACPI_OPTION ("-in", "Ignore NoOp opcodes"); ACPI_OPTION ("-vt", "Dump binary table data in hex format within output file"); @@ -186,6 +188,7 @@ Options ( printf ("\nDebug Options:\n"); ACPI_OPTION ("-bf -bt", "Create debug file (full or parse tree only) (*.txt)"); ACPI_OPTION ("-f", "Ignore errors, force creation of AML output file(s)"); + ACPI_OPTION ("-m <size>", "Set internal line buffer size (in Kbytes)"); ACPI_OPTION ("-n", "Parse only, no output generation"); ACPI_OPTION ("-ot", "Display compile times and statistics"); ACPI_OPTION ("-x <level>", "Set debug level for trace output"); diff --git a/sys/contrib/dev/acpica/compiler/aslmessages.h b/sys/contrib/dev/acpica/compiler/aslmessages.h index be7a3f9..102148d 100644 --- a/sys/contrib/dev/acpica/compiler/aslmessages.h +++ b/sys/contrib/dev/acpica/compiler/aslmessages.h @@ -166,6 +166,7 @@ typedef enum ASL_MSG_RESERVED_METHOD, ASL_MSG_RESERVED_NO_RETURN_VAL, ASL_MSG_RESERVED_OPERAND_TYPE, + ASL_MSG_RESERVED_PACKAGE_LENGTH, ASL_MSG_RESERVED_RETURN_VALUE, ASL_MSG_RESERVED_USE, ASL_MSG_RESERVED_WORD, @@ -343,6 +344,7 @@ char *AslMessages [] = { /* ASL_MSG_RESERVED_METHOD */ "Reserved name must be a control method", /* ASL_MSG_RESERVED_NO_RETURN_VAL */ "Reserved method should not return a value", /* ASL_MSG_RESERVED_OPERAND_TYPE */ "Invalid object type for reserved name", +/* ASL_MSG_RESERVED_PACKAGE_LENGTH */ "Invalid package length for reserved name", /* ASL_MSG_RESERVED_RETURN_VALUE */ "Reserved method must return a value", /* ASL_MSG_RESERVED_USE */ "Invalid use of reserved name", /* ASL_MSG_RESERVED_WORD */ "Use of reserved name", diff --git a/sys/contrib/dev/acpica/compiler/aslpredef.c b/sys/contrib/dev/acpica/compiler/aslpredef.c index dea0c83..4cc2312 100644 --- a/sys/contrib/dev/acpica/compiler/aslpredef.c +++ b/sys/contrib/dev/acpica/compiler/aslpredef.c @@ -46,6 +46,7 @@ #include <contrib/dev/acpica/compiler/aslcompiler.h> #include "aslcompiler.y.h" #include <contrib/dev/acpica/include/acpredef.h> +#include <contrib/dev/acpica/include/acnamesp.h> #define _COMPONENT ACPI_COMPILER @@ -65,12 +66,6 @@ ApCheckForSpecialName ( char *Name); static void -ApCheckObjectType ( - const char *PredefinedName, - ACPI_PARSE_OBJECT *Op, - UINT32 ExpectedBtypes); - -static void ApGetExpectedTypes ( char *Buffer, UINT32 ExpectedBtypes); @@ -386,7 +381,15 @@ ApCheckPredefinedReturnValue ( ApCheckObjectType (PredefinedNames[Index].Info.Name, ReturnValueOp, - PredefinedNames[Index].Info.ExpectedBtypes); + PredefinedNames[Index].Info.ExpectedBtypes, + ACPI_NOT_PACKAGE_ELEMENT); + + /* For packages, check the individual package elements */ + + if (ReturnValueOp->Asl.ParseOpcode == PARSEOP_PACKAGE) + { + ApCheckPackage (ReturnValueOp, &PredefinedNames[Index]); + } break; default: @@ -428,6 +431,7 @@ ApCheckForPredefinedObject ( char *Name) { UINT32 Index; + ACPI_PARSE_OBJECT *ObjectOp; /* @@ -456,39 +460,50 @@ ApCheckForPredefinedObject ( "with zero arguments"); return; - default: /* A standard predefined ACPI name */ - - /* - * If this predefined name requires input arguments, then - * it must be implemented as a control method - */ - if (PredefinedNames[Index].Info.ParamCount > 0) - { - AslError (ASL_ERROR, ASL_MSG_RESERVED_METHOD, Op, - "with arguments"); - return; - } + default: + break; + } - /* - * If no return value is expected from this predefined name, then - * it follows that it must be implemented as a control method - * (with zero args, because the args > 0 case was handled above) - * Examples are: _DIS, _INI, _IRC, _OFF, _ON, _PSx - */ - if (!PredefinedNames[Index].Info.ExpectedBtypes) - { - AslError (ASL_ERROR, ASL_MSG_RESERVED_METHOD, Op, - "with zero arguments"); - return; - } + /* A standard predefined ACPI name */ - /* Typecheck the actual object, it is the next argument */ + /* + * If this predefined name requires input arguments, then + * it must be implemented as a control method + */ + if (PredefinedNames[Index].Info.ParamCount > 0) + { + AslError (ASL_ERROR, ASL_MSG_RESERVED_METHOD, Op, + "with arguments"); + return; + } - ApCheckObjectType (PredefinedNames[Index].Info.Name, - Op->Asl.Child->Asl.Next, - PredefinedNames[Index].Info.ExpectedBtypes); + /* + * If no return value is expected from this predefined name, then + * it follows that it must be implemented as a control method + * (with zero args, because the args > 0 case was handled above) + * Examples are: _DIS, _INI, _IRC, _OFF, _ON, _PSx + */ + if (!PredefinedNames[Index].Info.ExpectedBtypes) + { + AslError (ASL_ERROR, ASL_MSG_RESERVED_METHOD, Op, + "with zero arguments"); return; } + + /* Typecheck the actual object, it is the next argument */ + + ObjectOp = Op->Asl.Child->Asl.Next; + ApCheckObjectType (PredefinedNames[Index].Info.Name, + Op->Asl.Child->Asl.Next, + PredefinedNames[Index].Info.ExpectedBtypes, + ACPI_NOT_PACKAGE_ELEMENT); + + /* For packages, check the individual package elements */ + + if (ObjectOp->Asl.ParseOpcode == PARSEOP_PACKAGE) + { + ApCheckPackage (ObjectOp, &PredefinedNames[Index]); + } } @@ -646,6 +661,9 @@ ApCheckForSpecialName ( * PARAMETERS: PredefinedName - Name of the predefined object we are checking * Op - Current parse node * ExpectedBtypes - Bitmap of expected return type(s) + * PackageIndex - Index of object within parent package (if + * applicable - ACPI_NOT_PACKAGE_ELEMENT + * otherwise) * * RETURN: None * @@ -655,14 +673,23 @@ ApCheckForSpecialName ( * ******************************************************************************/ -static void +ACPI_STATUS ApCheckObjectType ( const char *PredefinedName, ACPI_PARSE_OBJECT *Op, - UINT32 ExpectedBtypes) + UINT32 ExpectedBtypes, + UINT32 PackageIndex) { UINT32 ReturnBtype; + char *TypeName; + + + if (!Op) + { + return (AE_TYPE); + } + /* Map the parse opcode to a bitmapped return type (RTYPE) */ switch (Op->Asl.ParseOpcode) { @@ -671,24 +698,35 @@ ApCheckObjectType ( case PARSEOP_ONES: case PARSEOP_INTEGER: ReturnBtype = ACPI_RTYPE_INTEGER; - break; - - case PARSEOP_BUFFER: - ReturnBtype = ACPI_RTYPE_BUFFER; + TypeName = "Integer"; break; case PARSEOP_STRING_LITERAL: ReturnBtype = ACPI_RTYPE_STRING; + TypeName = "String"; + break; + + case PARSEOP_BUFFER: + ReturnBtype = ACPI_RTYPE_BUFFER; + TypeName = "Buffer"; break; case PARSEOP_PACKAGE: case PARSEOP_VAR_PACKAGE: ReturnBtype = ACPI_RTYPE_PACKAGE; + TypeName = "Package"; + break; + + case PARSEOP_NAMESEG: + case PARSEOP_NAMESTRING: + ReturnBtype = ACPI_RTYPE_REFERENCE; + TypeName = "Reference"; break; default: /* Not one of the supported object types */ + TypeName = UtGetOpName (Op->Asl.ParseOpcode); goto TypeErrorExit; } @@ -696,7 +734,7 @@ ApCheckObjectType ( if (ReturnBtype & ExpectedBtypes) { - return; + return (AE_OK); } @@ -706,11 +744,19 @@ TypeErrorExit: ApGetExpectedTypes (StringBuffer, ExpectedBtypes); - sprintf (MsgBuffer, "%s: found %s, requires %s", - PredefinedName, UtGetOpName (Op->Asl.ParseOpcode), StringBuffer); + if (PackageIndex == ACPI_NOT_PACKAGE_ELEMENT) + { + sprintf (MsgBuffer, "%s: found %s, %s required", + PredefinedName, TypeName, StringBuffer); + } + else + { + sprintf (MsgBuffer, "%s: found %s at index %u, %s required", + PredefinedName, TypeName, PackageIndex, StringBuffer); + } - AslError (ASL_ERROR, ASL_MSG_RESERVED_OPERAND_TYPE, Op, - MsgBuffer); + AslError (ASL_ERROR, ASL_MSG_RESERVED_OPERAND_TYPE, Op, MsgBuffer); + return (AE_TYPE); } diff --git a/sys/contrib/dev/acpica/compiler/aslprepkg.c b/sys/contrib/dev/acpica/compiler/aslprepkg.c new file mode 100644 index 0000000..ab52f44 --- /dev/null +++ b/sys/contrib/dev/acpica/compiler/aslprepkg.c @@ -0,0 +1,661 @@ +/****************************************************************************** + * + * Module Name: aslprepkg - support for ACPI predefined name package objects + * + *****************************************************************************/ + +/* + * Copyright (C) 2000 - 2013, Intel Corp. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions, and the following disclaimer, + * without modification. + * 2. Redistributions in binary form must reproduce at minimum a disclaimer + * substantially similar to the "NO WARRANTY" disclaimer below + * ("Disclaimer") and any redistribution must be conditioned upon + * including a substantially similar Disclaimer requirement for further + * binary redistribution. + * 3. Neither the names of the above-listed copyright holders nor the names + * of any contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * Alternatively, this software may be distributed under the terms of the + * GNU General Public License ("GPL") version 2 as published by the Free + * Software Foundation. + * + * NO WARRANTY + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGES. + */ + +#include <contrib/dev/acpica/compiler/aslcompiler.h> +#include "aslcompiler.y.h" +#include <contrib/dev/acpica/include/acpredef.h> + + +#define _COMPONENT ACPI_COMPILER + ACPI_MODULE_NAME ("aslprepkg") + + +/* Local prototypes */ + +static void +ApCheckPackageElements ( + const char *PredefinedName, + ACPI_PARSE_OBJECT *Op, + UINT8 Type1, + UINT32 Count1, + UINT8 Type2, + UINT32 Count2); + +static void +ApCheckPackageList ( + const char *PredefinedName, + ACPI_PARSE_OBJECT *ParentOp, + const ACPI_PREDEFINED_INFO *Package, + UINT32 StartIndex, + UINT32 Count); + +static void +ApPackageTooSmall ( + const char *PredefinedName, + ACPI_PARSE_OBJECT *Op, + UINT32 Count, + UINT32 ExpectedCount); + +static void +ApZeroLengthPackage ( + const char *PredefinedName, + ACPI_PARSE_OBJECT *Op); + +static void +ApPackageTooLarge ( + const char *PredefinedName, + ACPI_PARSE_OBJECT *Op, + UINT32 Count, + UINT32 ExpectedCount); + + +/******************************************************************************* + * + * FUNCTION: ApCheckPackage + * + * PARAMETERS: ParentOp - Parser op for the package + * Predefined - Pointer to package-specific info for method + * + * RETURN: None + * + * DESCRIPTION: Top-level validation for predefined name return package + * objects. + * + ******************************************************************************/ + +void +ApCheckPackage ( + ACPI_PARSE_OBJECT *ParentOp, + const ACPI_PREDEFINED_INFO *Predefined) +{ + ACPI_PARSE_OBJECT *Op; + const ACPI_PREDEFINED_INFO *Package; + ACPI_STATUS Status; + UINT32 ExpectedCount; + UINT32 Count; + UINT32 i; + + + /* The package info for this name is in the next table entry */ + + Package = Predefined + 1; + + /* First child is the package length */ + + Op = ParentOp->Asl.Child; + Count = (UINT32) Op->Asl.Value.Integer; + + /* + * Most packages must have at least one element. The only exception + * is the variable-length package (ACPI_PTYPE1_VAR). + */ + if (!Count) + { + if (Package->RetInfo.Type != ACPI_PTYPE1_VAR) + { + ApZeroLengthPackage (Predefined->Info.Name, ParentOp); + } + return; + } + + /* Get the first element of the package */ + + Op = Op->Asl.Next; + + /* Decode the package type */ + + switch (Package->RetInfo.Type) + { + case ACPI_PTYPE1_FIXED: + /* + * The package count is fixed and there are no sub-packages + * + * If package is too small, exit. + * If package is larger than expected, issue warning but continue + */ + ExpectedCount = Package->RetInfo.Count1 + Package->RetInfo.Count2; + if (Count < ExpectedCount) + { + goto PackageTooSmall; + } + else if (Count > ExpectedCount) + { + ApPackageTooLarge (Predefined->Info.Name, ParentOp, + Count, ExpectedCount); + } + + /* Validate all elements of the package */ + + ApCheckPackageElements (Predefined->Info.Name, Op, + Package->RetInfo.ObjectType1, Package->RetInfo.Count1, + Package->RetInfo.ObjectType2, Package->RetInfo.Count2); + break; + + case ACPI_PTYPE1_VAR: + /* + * The package count is variable, there are no sub-packages, and all + * elements must be of the same type + */ + for (i = 0; i < Count; i++) + { + ApCheckObjectType (Predefined->Info.Name, Op, + Package->RetInfo.ObjectType1, i); + Op = Op->Asl.Next; + } + break; + + case ACPI_PTYPE1_OPTION: + /* + * The package count is variable, there are no sub-packages. There are + * a fixed number of required elements, and a variable number of + * optional elements. + * + * Check if package is at least as large as the minimum required + */ + ExpectedCount = Package->RetInfo3.Count; + if (Count < ExpectedCount) + { + goto PackageTooSmall; + } + + /* Variable number of sub-objects */ + + for (i = 0; i < Count; i++) + { + if (i < Package->RetInfo3.Count) + { + /* These are the required package elements (0, 1, or 2) */ + + ApCheckObjectType (Predefined->Info.Name, Op, + Package->RetInfo3.ObjectType[i], i); + } + else + { + /* These are the optional package elements */ + + ApCheckObjectType (Predefined->Info.Name, Op, + Package->RetInfo3.TailObjectType, i); + } + Op = Op->Asl.Next; + } + break; + + case ACPI_PTYPE2_REV_FIXED: + + /* First element is the (Integer) revision */ + + ApCheckObjectType (Predefined->Info.Name, Op, + ACPI_RTYPE_INTEGER, 0); + + Op = Op->Asl.Next; + Count--; + + /* Examine the sub-packages */ + + ApCheckPackageList (Predefined->Info.Name, Op, + Package, 1, Count); + break; + + case ACPI_PTYPE2_PKG_COUNT: + + /* First element is the (Integer) count of sub-packages to follow */ + + Status = ApCheckObjectType (Predefined->Info.Name, Op, + ACPI_RTYPE_INTEGER, 0); + + /* We must have an integer count from above (otherwise, use Count) */ + + if (ACPI_SUCCESS (Status)) + { + /* + * Count cannot be larger than the parent package length, but allow it + * to be smaller. The >= accounts for the Integer above. + */ + ExpectedCount = (UINT32) Op->Asl.Value.Integer; + if (ExpectedCount >= Count) + { + goto PackageTooSmall; + } + + Count = ExpectedCount; + } + + Op = Op->Asl.Next; + + /* Examine the sub-packages */ + + ApCheckPackageList (Predefined->Info.Name, Op, + Package, 1, Count); + break; + + case ACPI_PTYPE2: + case ACPI_PTYPE2_FIXED: + case ACPI_PTYPE2_MIN: + case ACPI_PTYPE2_COUNT: + case ACPI_PTYPE2_FIX_VAR: + /* + * These types all return a single Package that consists of a + * variable number of sub-Packages. + */ + + /* Examine the sub-packages */ + + ApCheckPackageList (Predefined->Info.Name, Op, + Package, 0, Count); + break; + + default: + return; + } + + return; + +PackageTooSmall: + ApPackageTooSmall (Predefined->Info.Name, ParentOp, + Count, ExpectedCount); +} + + +/******************************************************************************* + * + * FUNCTION: ApCheckPackageElements + * + * PARAMETERS: PredefinedName - Pointer to validation data structure + * Op - Parser op for the package + * Type1 - Object type for first group + * Count1 - Count for first group + * Type2 - Object type for second group + * Count2 - Count for second group + * + * RETURN: None + * + * DESCRIPTION: Validate all elements of a package. Works with packages that + * are defined to contain up to two groups of different object + * types. + * + ******************************************************************************/ + +static void +ApCheckPackageElements ( + const char *PredefinedName, + ACPI_PARSE_OBJECT *Op, + UINT8 Type1, + UINT32 Count1, + UINT8 Type2, + UINT32 Count2) +{ + UINT32 i; + + + /* + * Up to two groups of package elements are supported by the data + * structure. All elements in each group must be of the same type. + * The second group can have a count of zero. + * + * Aborts check upon a NULL package element, as this means (at compile + * time) that the remainder of the package elements are also NULL + * (This is the only way to create NULL package elements.) + */ + for (i = 0; (i < Count1) && Op; i++) + { + ApCheckObjectType (PredefinedName, Op, Type1, i); + Op = Op->Asl.Next; + } + + for (i = 0; (i < Count2) && Op; i++) + { + ApCheckObjectType (PredefinedName, Op, Type2, (i + Count1)); + Op = Op->Asl.Next; + } +} + + +/******************************************************************************* + * + * FUNCTION: ApCheckPackageList + * + * PARAMETERS: PredefinedName - Name of the predefined object + * ParentOp - Parser op of the parent package + * Package - Package info for this predefined name + * StartIndex - Index in parent package where list begins + * ParentCount - Element count of parent package + * + * RETURN: None + * + * DESCRIPTION: Validate the individual package elements for a predefined name. + * Handles the cases where the predefined name is defined as a + * Package of Packages (subpackages). These are the types: + * + * ACPI_PTYPE2 + * ACPI_PTYPE2_FIXED + * ACPI_PTYPE2_MIN + * ACPI_PTYPE2_COUNT + * ACPI_PTYPE2_FIX_VAR + * + ******************************************************************************/ + +static void +ApCheckPackageList ( + const char *PredefinedName, + ACPI_PARSE_OBJECT *ParentOp, + const ACPI_PREDEFINED_INFO *Package, + UINT32 StartIndex, + UINT32 ParentCount) +{ + ACPI_PARSE_OBJECT *SubPackageOp = ParentOp; + ACPI_PARSE_OBJECT *Op; + ACPI_STATUS Status; + UINT32 Count; + UINT32 ExpectedCount; + UINT32 i; + UINT32 j; + + + /* + * Validate each subpackage in the parent Package + * + * Note: We ignore NULL package elements on the assumption that + * they will be initialized by the BIOS or other ASL code. + */ + for (i = 0; (i < ParentCount) && SubPackageOp; i++) + { + /* Each object in the list must be of type Package */ + + Status = ApCheckObjectType (PredefinedName, SubPackageOp, + ACPI_RTYPE_PACKAGE, i + StartIndex); + if (ACPI_FAILURE (Status)) + { + goto NextSubpackage; + } + + /* Examine the different types of expected subpackages */ + + Op = SubPackageOp->Asl.Child; + + /* First child is the package length */ + + Count = (UINT32) Op->Asl.Value.Integer; + Op = Op->Asl.Next; + + /* The subpackage must have at least one element */ + + if (!Count) + { + ApZeroLengthPackage (PredefinedName, SubPackageOp); + goto NextSubpackage; + } + + /* + * Decode the package type. + * PTYPE2 indicates that a "package of packages" is expected for + * this name. The various flavors of PTYPE2 indicate the number + * and format of the subpackages. + */ + switch (Package->RetInfo.Type) + { + case ACPI_PTYPE2: + case ACPI_PTYPE2_PKG_COUNT: + case ACPI_PTYPE2_REV_FIXED: + + /* Each subpackage has a fixed number of elements */ + + ExpectedCount = Package->RetInfo.Count1 + Package->RetInfo.Count2; + if (Count < ExpectedCount) + { + ApPackageTooSmall (PredefinedName, SubPackageOp, + Count, ExpectedCount); + break; + } + + ApCheckPackageElements (PredefinedName, Op, + Package->RetInfo.ObjectType1, Package->RetInfo.Count1, + Package->RetInfo.ObjectType2, Package->RetInfo.Count2); + break; + + case ACPI_PTYPE2_FIX_VAR: + /* + * Each subpackage has a fixed number of elements and an + * optional element + */ + ExpectedCount = Package->RetInfo.Count1 + Package->RetInfo.Count2; + if (Count < ExpectedCount) + { + ApPackageTooSmall (PredefinedName, SubPackageOp, + Count, ExpectedCount); + break; + } + + ApCheckPackageElements (PredefinedName, Op, + Package->RetInfo.ObjectType1, Package->RetInfo.Count1, + Package->RetInfo.ObjectType2, + Count - Package->RetInfo.Count1); + break; + + case ACPI_PTYPE2_FIXED: + + /* Each sub-package has a fixed length */ + + ExpectedCount = Package->RetInfo2.Count; + if (Count < ExpectedCount) + { + ApPackageTooSmall (PredefinedName, SubPackageOp, + Count, ExpectedCount); + break; + } + + /* Check each object/type combination */ + + for (j = 0; j < ExpectedCount; j++) + { + ApCheckObjectType (PredefinedName, Op, + Package->RetInfo2.ObjectType[j], j); + + Op = Op->Asl.Next; + } + break; + + case ACPI_PTYPE2_MIN: + + /* Each sub-package has a variable but minimum length */ + + ExpectedCount = Package->RetInfo.Count1; + if (Count < ExpectedCount) + { + ApPackageTooSmall (PredefinedName, SubPackageOp, + Count, ExpectedCount); + break; + } + + /* Check the type of each sub-package element */ + + ApCheckPackageElements (PredefinedName, Op, + Package->RetInfo.ObjectType1, Count, 0, 0); + break; + + case ACPI_PTYPE2_COUNT: + /* + * First element is the (Integer) count of elements, including + * the count field (the ACPI name is NumElements) + */ + Status = ApCheckObjectType (PredefinedName, Op, + ACPI_RTYPE_INTEGER, 0); + + /* We must have an integer count from above (otherwise, use Count) */ + + if (ACPI_SUCCESS (Status)) + { + /* + * Make sure package is large enough for the Count and is + * is as large as the minimum size + */ + ExpectedCount = (UINT32) Op->Asl.Value.Integer; + + if (Count < ExpectedCount) + { + ApPackageTooSmall (PredefinedName, SubPackageOp, + Count, ExpectedCount); + break; + } + else if (Count > ExpectedCount) + { + ApPackageTooLarge (PredefinedName, SubPackageOp, + Count, ExpectedCount); + } + + /* Some names of this type have a minimum length */ + + if (Count < Package->RetInfo.Count1) + { + ExpectedCount = Package->RetInfo.Count1; + ApPackageTooSmall (PredefinedName, SubPackageOp, + Count, ExpectedCount); + break; + } + + Count = ExpectedCount; + } + + /* Check the type of each sub-package element */ + + Op = Op->Asl.Next; + ApCheckPackageElements (PredefinedName, Op, + Package->RetInfo.ObjectType1, (Count - 1), 0, 0); + break; + + default: + break; + } + +NextSubpackage: + SubPackageOp = SubPackageOp->Asl.Next; + } +} + + +/******************************************************************************* + * + * FUNCTION: ApPackageTooSmall + * + * PARAMETERS: PredefinedName - Name of the predefined object + * Op - Current parser op + * Count - Actual package element count + * ExpectedCount - Expected package element count + * + * RETURN: None + * + * DESCRIPTION: Issue error message for a package that is smaller than + * required. + * + ******************************************************************************/ + +static void +ApPackageTooSmall ( + const char *PredefinedName, + ACPI_PARSE_OBJECT *Op, + UINT32 Count, + UINT32 ExpectedCount) +{ + + sprintf (MsgBuffer, "%s: length %u, required minimum is %u", + PredefinedName, Count, ExpectedCount); + + AslError (ASL_ERROR, ASL_MSG_RESERVED_PACKAGE_LENGTH, Op, MsgBuffer); +} + + +/******************************************************************************* + * + * FUNCTION: ApZeroLengthPackage + * + * PARAMETERS: PredefinedName - Name of the predefined object + * Op - Current parser op + * + * RETURN: None + * + * DESCRIPTION: Issue error message for a zero-length package (a package that + * is required to have a non-zero length). Variable length + * packages seem to be allowed to have zero length, however. + * Even if not allowed, BIOS code does it. + * + ******************************************************************************/ + +static void +ApZeroLengthPackage ( + const char *PredefinedName, + ACPI_PARSE_OBJECT *Op) +{ + + sprintf (MsgBuffer, "%s: length is zero", PredefinedName); + + AslError (ASL_ERROR, ASL_MSG_RESERVED_PACKAGE_LENGTH, Op, MsgBuffer); +} + + +/******************************************************************************* + * + * FUNCTION: ApPackageTooLarge + * + * PARAMETERS: PredefinedName - Name of the predefined object + * Op - Current parser op + * Count - Actual package element count + * ExpectedCount - Expected package element count + * + * RETURN: None + * + * DESCRIPTION: Issue a remark for a package that is larger than expected. + * + ******************************************************************************/ + +static void +ApPackageTooLarge ( + const char *PredefinedName, + ACPI_PARSE_OBJECT *Op, + UINT32 Count, + UINT32 ExpectedCount) +{ + + sprintf (MsgBuffer, "%s: length is %u, only %u required", + PredefinedName, Count, ExpectedCount); + + AslError (ASL_REMARK, ASL_MSG_RESERVED_PACKAGE_LENGTH, Op, MsgBuffer); +} diff --git a/sys/contrib/dev/acpica/compiler/aslstartup.c b/sys/contrib/dev/acpica/compiler/aslstartup.c index 8deb894..41a663d 100644 --- a/sys/contrib/dev/acpica/compiler/aslstartup.c +++ b/sys/contrib/dev/acpica/compiler/aslstartup.c @@ -44,6 +44,7 @@ #include <contrib/dev/acpica/compiler/aslcompiler.h> #include <contrib/dev/acpica/include/actables.h> +#include <contrib/dev/acpica/include/acdisasm.h> #include <contrib/dev/acpica/include/acapps.h> #define _COMPONENT ACPI_COMPILER @@ -66,6 +67,10 @@ static UINT8 AslDetectSourceFileType ( ASL_FILE_INFO *Info); +static ACPI_STATUS +AslDoDisassembly ( + void); + /******************************************************************************* * @@ -224,6 +229,15 @@ AslDetectSourceFileType ( ACPI_STATUS Status; + /* Check for a valid binary ACPI table */ + + Status = FlCheckForAcpiTable (Info->Handle); + if (ACPI_SUCCESS (Status)) + { + Type = ASL_INPUT_TYPE_ACPI_TABLE; + goto Cleanup; + } + /* Check for 100% ASCII source file (comments are ignored) */ Status = FlCheckForAscii (Info->Handle, Info->Filename, TRUE); @@ -279,6 +293,86 @@ Cleanup: /******************************************************************************* * + * FUNCTION: AslDoDisassembly + * + * PARAMETERS: None + * + * RETURN: Status + * + * DESCRIPTION: Initiate AML file disassembly. Uses ACPICA subsystem to build + * namespace. + * + ******************************************************************************/ + +static ACPI_STATUS +AslDoDisassembly ( + void) +{ + ACPI_STATUS Status; + + + /* ACPICA subsystem initialization */ + + Status = AdInitialize (); + if (ACPI_FAILURE (Status)) + { + return (Status); + } + + Status = AcpiAllocateRootTable (4); + if (ACPI_FAILURE (Status)) + { + AcpiOsPrintf ("Could not initialize ACPI Table Manager, %s\n", + AcpiFormatException (Status)); + return (Status); + } + + /* This is where the disassembly happens */ + + AcpiGbl_DbOpt_disasm = TRUE; + Status = AdAmlDisassemble (AslToFile, + Gbl_Files[ASL_FILE_INPUT].Filename, Gbl_OutputFilenamePrefix, + &Gbl_Files[ASL_FILE_INPUT].Filename, Gbl_GetAllTables); + if (ACPI_FAILURE (Status)) + { + return (Status); + } + + /* Check if any control methods were unresolved */ + + AcpiDmUnresolvedWarning (0); + +#if 0 + /* TBD: Handle additional output files for disassembler */ + + Status = FlOpenMiscOutputFiles (Gbl_OutputFilenamePrefix); + NsDisplayNamespace (); +#endif + + /* Shutdown compiler and ACPICA subsystem */ + + AeClearErrorLog (); + (void) AcpiTerminate (); + + /* + * Gbl_Files[ASL_FILE_INPUT].Filename was replaced with the + * .DSL disassembly file, which can now be compiled if requested + */ + if (Gbl_DoCompile) + { + AcpiOsPrintf ("\nCompiling \"%s\"\n", + Gbl_Files[ASL_FILE_INPUT].Filename); + return (AE_CTRL_CONTINUE); + } + + ACPI_FREE (Gbl_Files[ASL_FILE_INPUT].Filename); + Gbl_Files[ASL_FILE_INPUT].Filename = NULL; + return (AE_OK); +} + + +/******************************************************************************* + * * FUNCTION: AslDoOneFile * * PARAMETERS: Filename - Name of the file @@ -308,61 +402,11 @@ AslDoOneFile ( */ if (Gbl_DisasmFlag || Gbl_GetAllTables) { - /* ACPICA subsystem initialization */ - - Status = AdInitialize (); - if (ACPI_FAILURE (Status)) - { - return (Status); - } - - Status = AcpiAllocateRootTable (4); - if (ACPI_FAILURE (Status)) - { - AcpiOsPrintf ("Could not initialize ACPI Table Manager, %s\n", - AcpiFormatException (Status)); - return (Status); - } - - /* This is where the disassembly happens */ - - AcpiGbl_DbOpt_disasm = TRUE; - Status = AdAmlDisassemble (AslToFile, - Gbl_Files[ASL_FILE_INPUT].Filename, - Gbl_OutputFilenamePrefix, - &Gbl_Files[ASL_FILE_INPUT].Filename, - Gbl_GetAllTables); - if (ACPI_FAILURE (Status)) + Status = AslDoDisassembly (); + if (Status != AE_CTRL_CONTINUE) { return (Status); } - -#if 0 - /* TBD: Handle additional output files for disassembler */ - - Status = FlOpenMiscOutputFiles (Gbl_OutputFilenamePrefix); - NsDisplayNamespace (); -#endif - - /* Shutdown compiler and ACPICA subsystem */ - - AeClearErrorLog (); - (void) AcpiTerminate (); - - /* - * Gbl_Files[ASL_FILE_INPUT].Filename was replaced with the - * .DSL disassembly file, which can now be compiled if requested - */ - if (Gbl_DoCompile) - { - AcpiOsPrintf ("\nCompiling \"%s\"\n", - Gbl_Files[ASL_FILE_INPUT].Filename); - } - else - { - Gbl_Files[ASL_FILE_INPUT].Filename = NULL; - return (AE_OK); - } } /* @@ -469,6 +513,21 @@ AslDoOneFile ( PrTerminatePreprocessor (); return (AE_OK); + /* + * Binary ACPI table was auto-detected, disassemble it + */ + case ASL_INPUT_TYPE_ACPI_TABLE: + + /* We have what appears to be an ACPI table, disassemble it */ + + FlCloseFile (ASL_FILE_INPUT); + Gbl_DoCompile = FALSE; + Gbl_DisasmFlag = TRUE; + Status = AslDoDisassembly (); + return (Status); + + /* Unknown binary table */ + case ASL_INPUT_TYPE_BINARY: AePrintErrorLog (ASL_FILE_STDERR); diff --git a/sys/contrib/dev/acpica/compiler/aslsupport.l b/sys/contrib/dev/acpica/compiler/aslsupport.l index 90af049..52389ee 100644 --- a/sys/contrib/dev/acpica/compiler/aslsupport.l +++ b/sys/contrib/dev/acpica/compiler/aslsupport.l @@ -403,6 +403,9 @@ count ( TotalKeywords++; TotalExecutableOpcodes++; break; + + default: + break; } for (i = 0; (yytext[i] != 0) && (yytext[i] != EOF); i++) @@ -570,7 +573,6 @@ AslDoStringLiteral ( AslInsertLineBuffer (StringChar); DoCharacter: - switch (State) { case ASL_NORMAL_CHAR: @@ -590,6 +592,9 @@ DoCharacter: /* String terminator */ goto CompletedString; + + default: + break; } break; @@ -748,6 +753,9 @@ DoCharacter: ConvertBuffer[i] = StringChar; i++; continue; + + default: + break; } /* Save the finished character */ diff --git a/sys/contrib/dev/acpica/compiler/dtcompiler.h b/sys/contrib/dev/acpica/compiler/dtcompiler.h index e9bdf05..51fec6d 100644 --- a/sys/contrib/dev/acpica/compiler/dtcompiler.h +++ b/sys/contrib/dev/acpica/compiler/dtcompiler.h @@ -444,6 +444,10 @@ DtCompileMsct ( void **PFieldList); ACPI_STATUS +DtCompileMtmr ( + void **PFieldList); + +ACPI_STATUS DtCompilePmtt ( void **PFieldList); @@ -472,6 +476,10 @@ DtCompileUefi ( void **PFieldList); ACPI_STATUS +DtCompileVrtc ( + void **PFieldList); + +ACPI_STATUS DtCompileWdat ( void **PFieldList); @@ -511,6 +519,7 @@ extern const unsigned char TemplateMcfg[]; extern const unsigned char TemplateMchi[]; extern const unsigned char TemplateMpst[]; extern const unsigned char TemplateMsct[]; +extern const unsigned char TemplateMtmr[]; extern const unsigned char TemplatePmtt[]; extern const unsigned char TemplateRsdt[]; extern const unsigned char TemplateS3pt[]; @@ -523,6 +532,7 @@ extern const unsigned char TemplateSrat[]; extern const unsigned char TemplateTcpa[]; extern const unsigned char TemplateTpm2[]; extern const unsigned char TemplateUefi[]; +extern const unsigned char TemplateVrtc[]; extern const unsigned char TemplateWaet[]; extern const unsigned char TemplateWdat[]; extern const unsigned char TemplateWddt[]; diff --git a/sys/contrib/dev/acpica/compiler/dttable.c b/sys/contrib/dev/acpica/compiler/dttable.c index 1a8fd81..cd6a35f 100644 --- a/sys/contrib/dev/acpica/compiler/dttable.c +++ b/sys/contrib/dev/acpica/compiler/dttable.c @@ -1412,6 +1412,31 @@ DtCompileMsct ( /****************************************************************************** * + * FUNCTION: DtCompileMtmr + * + * PARAMETERS: List - Current field list pointer + * + * RETURN: Status + * + * DESCRIPTION: Compile MTMR. + * + *****************************************************************************/ + +ACPI_STATUS +DtCompileMtmr ( + void **List) +{ + ACPI_STATUS Status; + + + Status = DtCompileTwoSubtables (List, + AcpiDmTableInfoMtmr, AcpiDmTableInfoMtmr0); + return (Status); +} + + +/****************************************************************************** + * * FUNCTION: DtCompilePmtt * * PARAMETERS: List - Current field list pointer @@ -1974,6 +1999,31 @@ DtCompileUefi ( /****************************************************************************** * + * FUNCTION: DtCompileVrtc + * + * PARAMETERS: List - Current field list pointer + * + * RETURN: Status + * + * DESCRIPTION: Compile VRTC. + * + *****************************************************************************/ + +ACPI_STATUS +DtCompileVrtc ( + void **List) +{ + ACPI_STATUS Status; + + + Status = DtCompileTwoSubtables (List, + AcpiDmTableInfoVrtc, AcpiDmTableInfoVrtc0); + return (Status); +} + + +/****************************************************************************** + * * FUNCTION: DtCompileWdat * * PARAMETERS: List - Current field list pointer diff --git a/sys/contrib/dev/acpica/compiler/dttemplate.h b/sys/contrib/dev/acpica/compiler/dttemplate.h index 07d1f91..d3fadf5 100644 --- a/sys/contrib/dev/acpica/compiler/dttemplate.h +++ b/sys/contrib/dev/acpica/compiler/dttemplate.h @@ -632,6 +632,20 @@ const unsigned char TemplateMsct[] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 /* 00000088 "........" */ }; +const unsigned char TemplateMtmr[] = +{ + 0x4D,0x54,0x4D,0x52,0x4C,0x00,0x00,0x00, /* 00000000 "MTMRL..." */ + 0x01,0xB0,0x49,0x4E,0x54,0x45,0x4C,0x20, /* 00000008 "..INTEL " */ + 0x54,0x45,0x4D,0x50,0x4C,0x41,0x54,0x45, /* 00000010 "TEMPLATE" */ + 0x03,0x00,0x00,0x00,0x49,0x4E,0x54,0x4C, /* 00000018 "....INTL" */ + 0x17,0x01,0x13,0x20,0x00,0x20,0x00,0x03, /* 00000020 "... . .." */ + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 00000028 "........" */ + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 00000030 "........" */ + 0x00,0x20,0x00,0x03,0x00,0x00,0x00,0x00, /* 00000038 ". ......" */ + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 00000040 "........" */ + 0x00,0x00,0x00,0x00 /* 00000048 "...." */ +}; + const unsigned char TemplatePmtt[] = { 0x50,0x4D,0x54,0x54,0xB4,0x00,0x00,0x00, /* 00000000 "PMTT...." */ @@ -893,6 +907,19 @@ const unsigned char TemplateUefi[] = 0x0C,0x0D,0x0E,0x0F,0x00,0x00 /* 00000030 "......" */ }; +const unsigned char TemplateVrtc[] = +{ + 0x56,0x52,0x54,0x43,0x44,0x00,0x00,0x00, /* 00000000 "VRTCD..." */ + 0x01,0xEF,0x49,0x4E,0x54,0x45,0x4C,0x20, /* 00000008 "..INTEL " */ + 0x54,0x45,0x4D,0x50,0x4C,0x41,0x54,0x45, /* 00000010 "TEMPLATE" */ + 0x03,0x00,0x00,0x00,0x49,0x4E,0x54,0x4C, /* 00000018 "....INTL" */ + 0x17,0x01,0x13,0x20,0x00,0x08,0x00,0x00, /* 00000020 "... ...." */ + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 00000028 "........" */ + 0x00,0x00,0x00,0x00,0x00,0x08,0x00,0x00, /* 00000030 "........" */ + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 00000038 "........" */ + 0x00,0x00,0x00,0x00 /* 00000040 "...." */ +}; + const unsigned char TemplateWaet[] = { 0x57,0x41,0x45,0x54,0x28,0x00,0x00,0x00, /* 00000000 "WAET(..." */ diff --git a/sys/contrib/dev/acpica/components/debugger/dbcmds.c b/sys/contrib/dev/acpica/components/debugger/dbcmds.c index 64c299c..290b164 100644 --- a/sys/contrib/dev/acpica/components/debugger/dbcmds.c +++ b/sys/contrib/dev/acpica/components/debugger/dbcmds.c @@ -1024,6 +1024,8 @@ GetCrs: /* Execute _SRS with the resource list */ + AcpiOsPrintf ("Evaluating _SRS\n"); + Status = AcpiSetCurrentResources (Node, &ReturnBuffer); if (ACPI_FAILURE (Status)) { @@ -1114,8 +1116,8 @@ Cleanup: * FUNCTION: AcpiDbDisplayResources * * PARAMETERS: ObjectArg - String object name or object pointer. - * "*" means "display resources for all - * devices" + * NULL or "*" means "display resources for + * all devices" * * RETURN: None * @@ -1135,7 +1137,7 @@ AcpiDbDisplayResources ( /* Asterisk means "display resources for all devices" */ - if (!ACPI_STRCMP (ObjectArg, "*")) + if (!ObjectArg || (!ACPI_STRCMP (ObjectArg, "*"))) { (void) AcpiWalkNamespace (ACPI_TYPE_DEVICE, ACPI_ROOT_OBJECT, ACPI_UINT32_MAX, AcpiDbDeviceResources, NULL, NULL, NULL); diff --git a/sys/contrib/dev/acpica/components/debugger/dbinput.c b/sys/contrib/dev/acpica/components/debugger/dbinput.c index b5c46df..7cbc216 100644 --- a/sys/contrib/dev/acpica/components/debugger/dbinput.c +++ b/sys/contrib/dev/acpica/components/debugger/dbinput.c @@ -207,7 +207,7 @@ static const ACPI_DB_COMMAND_INFO AcpiGbl_DbCommands[] = {"PREFIX", 0}, {"QUIT", 0}, {"REFERENCES", 1}, - {"RESOURCES", 1}, + {"RESOURCES", 0}, {"RESULTS", 0}, {"SET", 3}, {"SLEEP", 0}, @@ -272,7 +272,7 @@ static const ACPI_DB_COMMAND_HELP AcpiGbl_DbCommandHelp[] = {1, " Predefined", "Check all predefined names\n"}, {1, " Prefix [<NamePath>]", "Set or Get current execution prefix\n"}, {1, " References <Addr>", "Find all references to object at addr\n"}, - {1, " Resources <DeviceName | *>", "Display Device resources (* = all devices)\n"}, + {1, " Resources [DeviceName]", "Display Device resources (no arg = all devices)\n"}, {1, " Set N <NamedObject> <Value>", "Set value for named integer\n"}, {1, " Sleep [SleepState]", "Simulate sleep/wake sequence(s) (0-5)\n"}, {1, " Template <Object>", "Format/dump a Buffer/ResourceTemplate\n"}, diff --git a/sys/contrib/dev/acpica/components/dispatcher/dsutils.c b/sys/contrib/dev/acpica/components/dispatcher/dsutils.c index 3b44c67..9995a20 100644 --- a/sys/contrib/dev/acpica/components/dispatcher/dsutils.c +++ b/sys/contrib/dev/acpica/components/dispatcher/dsutils.c @@ -201,7 +201,7 @@ AcpiDsIsResultUsed ( if (!Op) { ACPI_ERROR ((AE_INFO, "Null Op")); - return_VALUE (TRUE); + return_UINT8 (TRUE); } /* @@ -231,7 +231,7 @@ AcpiDsIsResultUsed ( ACPI_DEBUG_PRINT ((ACPI_DB_DISPATCH, "At Method level, result of [%s] not used\n", AcpiPsGetOpcodeName (Op->Common.AmlOpcode))); - return_VALUE (FALSE); + return_UINT8 (FALSE); } /* Get info on the parent. The RootOp is AML_SCOPE */ @@ -241,7 +241,7 @@ AcpiDsIsResultUsed ( { ACPI_ERROR ((AE_INFO, "Unknown parent opcode Op=%p", Op)); - return_VALUE (FALSE); + return_UINT8 (FALSE); } /* @@ -331,7 +331,7 @@ ResultUsed: AcpiPsGetOpcodeName (Op->Common.AmlOpcode), AcpiPsGetOpcodeName (Op->Common.Parent->Common.AmlOpcode), Op)); - return_VALUE (TRUE); + return_UINT8 (TRUE); ResultNotUsed: @@ -340,7 +340,7 @@ ResultNotUsed: AcpiPsGetOpcodeName (Op->Common.AmlOpcode), AcpiPsGetOpcodeName (Op->Common.Parent->Common.AmlOpcode), Op)); - return_VALUE (FALSE); + return_UINT8 (FALSE); } diff --git a/sys/contrib/dev/acpica/components/events/evevent.c b/sys/contrib/dev/acpica/components/events/evevent.c index adad8c8..6e63528 100644 --- a/sys/contrib/dev/acpica/components/events/evevent.c +++ b/sys/contrib/dev/acpica/components/events/evevent.c @@ -291,6 +291,8 @@ AcpiEvFixedEventDetect ( * * DESCRIPTION: Clears the status bit for the requested event, calls the * handler that previously registered for the event. + * NOTE: If there is no handler for the event, the event is + * disabled to prevent futher interrupts. * ******************************************************************************/ @@ -309,18 +311,18 @@ AcpiEvFixedEventDispatch ( ACPI_CLEAR_STATUS); /* - * Make sure we've got a handler. If not, report an error. The event is - * disabled to prevent further interrupts. + * Make sure that a handler exists. If not, report an error + * and disable the event to prevent further interrupts. */ - if (NULL == AcpiGbl_FixedEventHandlers[Event].Handler) + if (!AcpiGbl_FixedEventHandlers[Event].Handler) { (void) AcpiWriteBitRegister ( AcpiGbl_FixedEventInfo[Event].EnableRegisterId, ACPI_DISABLE_EVENT); ACPI_ERROR ((AE_INFO, - "No installed handler for fixed event [0x%08X]", - Event)); + "No installed handler for fixed event - %s (%u), disabling", + AcpiUtGetEventName (Event), Event)); return (ACPI_INTERRUPT_NOT_HANDLED); } diff --git a/sys/contrib/dev/acpica/components/events/evgpe.c b/sys/contrib/dev/acpica/components/events/evgpe.c index 75ad956..46b1179 100644 --- a/sys/contrib/dev/acpica/components/events/evgpe.c +++ b/sys/contrib/dev/acpica/components/events/evgpe.c @@ -770,7 +770,7 @@ AcpiEvGpeDispatch ( { ACPI_EXCEPTION ((AE_INFO, Status, "Unable to clear GPE%02X", GpeNumber)); - return_VALUE (ACPI_INTERRUPT_NOT_HANDLED); + return_UINT32 (ACPI_INTERRUPT_NOT_HANDLED); } } @@ -788,7 +788,7 @@ AcpiEvGpeDispatch ( { ACPI_EXCEPTION ((AE_INFO, Status, "Unable to disable GPE%02X", GpeNumber)); - return_VALUE (ACPI_INTERRUPT_NOT_HANDLED); + return_UINT32 (ACPI_INTERRUPT_NOT_HANDLED); } /* @@ -846,7 +846,7 @@ AcpiEvGpeDispatch ( break; } - return_VALUE (ACPI_INTERRUPT_HANDLED); + return_UINT32 (ACPI_INTERRUPT_HANDLED); } #endif /* !ACPI_REDUCED_HARDWARE */ diff --git a/sys/contrib/dev/acpica/components/events/evsci.c b/sys/contrib/dev/acpica/components/events/evsci.c index 340c400..ed87c63 100644 --- a/sys/contrib/dev/acpica/components/events/evsci.c +++ b/sys/contrib/dev/acpica/components/events/evsci.c @@ -101,7 +101,7 @@ AcpiEvSciXruptHandler ( InterruptHandled |= AcpiEvGpeDetect (GpeXruptList); AcpiSciCount++; - return_VALUE (InterruptHandled); + return_UINT32 (InterruptHandled); } @@ -137,7 +137,7 @@ AcpiEvGpeXruptHandler ( InterruptHandled |= AcpiEvGpeDetect (GpeXruptList); - return_VALUE (InterruptHandled); + return_UINT32 (InterruptHandled); } diff --git a/sys/contrib/dev/acpica/components/events/evxface.c b/sys/contrib/dev/acpica/components/events/evxface.c index dfc4790..cf5dbed 100644 --- a/sys/contrib/dev/acpica/components/events/evxface.c +++ b/sys/contrib/dev/acpica/components/events/evxface.c @@ -534,9 +534,9 @@ AcpiInstallFixedEventHandler ( return_ACPI_STATUS (Status); } - /* Don't allow two handlers. */ + /* Do not allow multiple handlers */ - if (NULL != AcpiGbl_FixedEventHandlers[Event].Handler) + if (AcpiGbl_FixedEventHandlers[Event].Handler) { Status = AE_ALREADY_EXISTS; goto Cleanup; @@ -550,7 +550,9 @@ AcpiInstallFixedEventHandler ( Status = AcpiEnableEvent (Event, 0); if (ACPI_FAILURE (Status)) { - ACPI_WARNING ((AE_INFO, "Could not enable fixed event 0x%X", Event)); + ACPI_WARNING ((AE_INFO, + "Could not enable fixed event - %s (%u)", + AcpiUtGetEventName (Event), Event)); /* Remove the handler */ @@ -560,7 +562,8 @@ AcpiInstallFixedEventHandler ( else { ACPI_DEBUG_PRINT ((ACPI_DB_INFO, - "Enabled fixed event %X, Handler=%p\n", Event, Handler)); + "Enabled fixed event %s (%X), Handler=%p\n", + AcpiUtGetEventName (Event), Event, Handler)); } @@ -621,11 +624,14 @@ AcpiRemoveFixedEventHandler ( if (ACPI_FAILURE (Status)) { ACPI_WARNING ((AE_INFO, - "Could not write to fixed event enable register 0x%X", Event)); + "Could not disable fixed event - %s (%u)", + AcpiUtGetEventName (Event), Event)); } else { - ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Disabled fixed event %X\n", Event)); + ACPI_DEBUG_PRINT ((ACPI_DB_INFO, + "Disabled fixed event - %s (%X)\n", + AcpiUtGetEventName (Event), Event)); } (void) AcpiUtReleaseMutex (ACPI_MTX_EVENTS); diff --git a/sys/contrib/dev/acpica/components/events/evxfevnt.c b/sys/contrib/dev/acpica/components/events/evxfevnt.c index e0f36e2..eb17a3f 100644 --- a/sys/contrib/dev/acpica/components/events/evxfevnt.c +++ b/sys/contrib/dev/acpica/components/events/evxfevnt.c @@ -82,6 +82,13 @@ AcpiEnable ( return_ACPI_STATUS (AE_NO_ACPI_TABLES); } + /* If the Hardware Reduced flag is set, machine is always in acpi mode */ + + if (AcpiGbl_ReducedHardware) + { + return_ACPI_STATUS (AE_OK); + } + /* Check current mode */ if (AcpiHwGetMode() == ACPI_SYS_MODE_ACPI) @@ -131,6 +138,13 @@ AcpiDisable ( ACPI_FUNCTION_TRACE (AcpiDisable); + /* If the Hardware Reduced flag is set, machine is always in acpi mode */ + + if (AcpiGbl_ReducedHardware) + { + return_ACPI_STATUS (AE_OK); + } + if (AcpiHwGetMode() == ACPI_SYS_MODE_LEGACY) { ACPI_DEBUG_PRINT ((ACPI_DB_INIT, diff --git a/sys/contrib/dev/acpica/components/executer/exprep.c b/sys/contrib/dev/acpica/components/executer/exprep.c index 97fe872..5932205 100644 --- a/sys/contrib/dev/acpica/components/executer/exprep.c +++ b/sys/contrib/dev/acpica/components/executer/exprep.c @@ -292,7 +292,7 @@ AcpiExDecodeFieldAccess ( ACPI_ERROR ((AE_INFO, "Unknown field access type 0x%X", Access)); - return_VALUE (0); + return_UINT32 (0); } if (ObjDesc->Common.Type == ACPI_TYPE_BUFFER_FIELD) @@ -306,7 +306,7 @@ AcpiExDecodeFieldAccess ( } *ReturnByteAlignment = ByteAlignment; - return_VALUE (BitLength); + return_UINT32 (BitLength); } diff --git a/sys/contrib/dev/acpica/components/executer/exutils.c b/sys/contrib/dev/acpica/components/executer/exutils.c index fb78123..29abfd1 100644 --- a/sys/contrib/dev/acpica/components/executer/exutils.c +++ b/sys/contrib/dev/acpica/components/executer/exutils.c @@ -391,7 +391,7 @@ AcpiExDigitsNeeded ( if (Value == 0) { - return_VALUE (1); + return_UINT32 (1); } CurrentValue = Value; @@ -405,7 +405,7 @@ AcpiExDigitsNeeded ( NumDigits++; } - return_VALUE (NumDigits); + return_UINT32 (NumDigits); } diff --git a/sys/contrib/dev/acpica/components/hardware/hwacpi.c b/sys/contrib/dev/acpica/components/hardware/hwacpi.c index 41830c3..f68e709 100644 --- a/sys/contrib/dev/acpica/components/hardware/hwacpi.c +++ b/sys/contrib/dev/acpica/components/hardware/hwacpi.c @@ -75,6 +75,14 @@ AcpiHwSetMode ( ACPI_FUNCTION_TRACE (HwSetMode); + + /* If the Hardware Reduced flag is set, machine is always in acpi mode */ + + if (AcpiGbl_ReducedHardware) + { + return_ACPI_STATUS (AE_OK); + } + /* * ACPI 2.0 clarified that if SMI_CMD in FADT is zero, * system does not support mode transition. @@ -180,28 +188,35 @@ AcpiHwGetMode ( ACPI_FUNCTION_TRACE (HwGetMode); + /* If the Hardware Reduced flag is set, machine is always in acpi mode */ + + if (AcpiGbl_ReducedHardware) + { + return_UINT32 (ACPI_SYS_MODE_ACPI); + } + /* * ACPI 2.0 clarified that if SMI_CMD in FADT is zero, * system does not support mode transition. */ if (!AcpiGbl_FADT.SmiCommand) { - return_VALUE (ACPI_SYS_MODE_ACPI); + return_UINT32 (ACPI_SYS_MODE_ACPI); } Status = AcpiReadBitRegister (ACPI_BITREG_SCI_ENABLE, &Value); if (ACPI_FAILURE (Status)) { - return_VALUE (ACPI_SYS_MODE_LEGACY); + return_UINT32 (ACPI_SYS_MODE_LEGACY); } if (Value) { - return_VALUE (ACPI_SYS_MODE_ACPI); + return_UINT32 (ACPI_SYS_MODE_ACPI); } else { - return_VALUE (ACPI_SYS_MODE_LEGACY); + return_UINT32 (ACPI_SYS_MODE_LEGACY); } } diff --git a/sys/contrib/dev/acpica/components/namespace/nsconvert.c b/sys/contrib/dev/acpica/components/namespace/nsconvert.c new file mode 100644 index 0000000..ed6f885 --- /dev/null +++ b/sys/contrib/dev/acpica/components/namespace/nsconvert.c @@ -0,0 +1,481 @@ +/****************************************************************************** + * + * Module Name: nsconvert - Object conversions for objects returned by + * predefined methods + * + *****************************************************************************/ + +/* + * Copyright (C) 2000 - 2013, Intel Corp. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions, and the following disclaimer, + * without modification. + * 2. Redistributions in binary form must reproduce at minimum a disclaimer + * substantially similar to the "NO WARRANTY" disclaimer below + * ("Disclaimer") and any redistribution must be conditioned upon + * including a substantially similar Disclaimer requirement for further + * binary redistribution. + * 3. Neither the names of the above-listed copyright holders nor the names + * of any contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * Alternatively, this software may be distributed under the terms of the + * GNU General Public License ("GPL") version 2 as published by the Free + * Software Foundation. + * + * NO WARRANTY + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGES. + */ + +#define __NSCONVERT_C__ + +#include <contrib/dev/acpica/include/acpi.h> +#include <contrib/dev/acpica/include/accommon.h> +#include <contrib/dev/acpica/include/acnamesp.h> +#include <contrib/dev/acpica/include/acinterp.h> +#include <contrib/dev/acpica/include/acpredef.h> +#include <contrib/dev/acpica/include/amlresrc.h> + +#define _COMPONENT ACPI_NAMESPACE + ACPI_MODULE_NAME ("nsconvert") + + +/******************************************************************************* + * + * FUNCTION: AcpiNsConvertToInteger + * + * PARAMETERS: OriginalObject - Object to be converted + * ReturnObject - Where the new converted object is returned + * + * RETURN: Status. AE_OK if conversion was successful. + * + * DESCRIPTION: Attempt to convert a String/Buffer object to an Integer. + * + ******************************************************************************/ + +ACPI_STATUS +AcpiNsConvertToInteger ( + ACPI_OPERAND_OBJECT *OriginalObject, + ACPI_OPERAND_OBJECT **ReturnObject) +{ + ACPI_OPERAND_OBJECT *NewObject; + ACPI_STATUS Status; + UINT64 Value = 0; + UINT32 i; + + + switch (OriginalObject->Common.Type) + { + case ACPI_TYPE_STRING: + + /* String-to-Integer conversion */ + + Status = AcpiUtStrtoul64 (OriginalObject->String.Pointer, + ACPI_ANY_BASE, &Value); + if (ACPI_FAILURE (Status)) + { + return (Status); + } + break; + + case ACPI_TYPE_BUFFER: + + /* Buffer-to-Integer conversion. Max buffer size is 64 bits. */ + + if (OriginalObject->Buffer.Length > 8) + { + return (AE_AML_OPERAND_TYPE); + } + + /* Extract each buffer byte to create the integer */ + + for (i = 0; i < OriginalObject->Buffer.Length; i++) + { + Value |= ((UINT64) OriginalObject->Buffer.Pointer[i] << (i * 8)); + } + break; + + default: + return (AE_AML_OPERAND_TYPE); + } + + NewObject = AcpiUtCreateIntegerObject (Value); + if (!NewObject) + { + return (AE_NO_MEMORY); + } + + *ReturnObject = NewObject; + return (AE_OK); +} + + +/******************************************************************************* + * + * FUNCTION: AcpiNsConvertToString + * + * PARAMETERS: OriginalObject - Object to be converted + * ReturnObject - Where the new converted object is returned + * + * RETURN: Status. AE_OK if conversion was successful. + * + * DESCRIPTION: Attempt to convert a Integer/Buffer object to a String. + * + ******************************************************************************/ + +ACPI_STATUS +AcpiNsConvertToString ( + ACPI_OPERAND_OBJECT *OriginalObject, + ACPI_OPERAND_OBJECT **ReturnObject) +{ + ACPI_OPERAND_OBJECT *NewObject; + ACPI_SIZE Length; + ACPI_STATUS Status; + + + switch (OriginalObject->Common.Type) + { + case ACPI_TYPE_INTEGER: + /* + * Integer-to-String conversion. Commonly, convert + * an integer of value 0 to a NULL string. The last element of + * _BIF and _BIX packages occasionally need this fix. + */ + if (OriginalObject->Integer.Value == 0) + { + /* Allocate a new NULL string object */ + + NewObject = AcpiUtCreateStringObject (0); + if (!NewObject) + { + return (AE_NO_MEMORY); + } + } + else + { + Status = AcpiExConvertToString (OriginalObject, &NewObject, + ACPI_IMPLICIT_CONVERT_HEX); + if (ACPI_FAILURE (Status)) + { + return (Status); + } + } + break; + + case ACPI_TYPE_BUFFER: + /* + * Buffer-to-String conversion. Use a ToString + * conversion, no transform performed on the buffer data. The best + * example of this is the _BIF method, where the string data from + * the battery is often (incorrectly) returned as buffer object(s). + */ + Length = 0; + while ((Length < OriginalObject->Buffer.Length) && + (OriginalObject->Buffer.Pointer[Length])) + { + Length++; + } + + /* Allocate a new string object */ + + NewObject = AcpiUtCreateStringObject (Length); + if (!NewObject) + { + return (AE_NO_MEMORY); + } + + /* + * Copy the raw buffer data with no transform. String is already NULL + * terminated at Length+1. + */ + ACPI_MEMCPY (NewObject->String.Pointer, + OriginalObject->Buffer.Pointer, Length); + break; + + default: + return (AE_AML_OPERAND_TYPE); + } + + *ReturnObject = NewObject; + return (AE_OK); +} + + +/******************************************************************************* + * + * FUNCTION: AcpiNsConvertToBuffer + * + * PARAMETERS: OriginalObject - Object to be converted + * ReturnObject - Where the new converted object is returned + * + * RETURN: Status. AE_OK if conversion was successful. + * + * DESCRIPTION: Attempt to convert a Integer/String/Package object to a Buffer. + * + ******************************************************************************/ + +ACPI_STATUS +AcpiNsConvertToBuffer ( + ACPI_OPERAND_OBJECT *OriginalObject, + ACPI_OPERAND_OBJECT **ReturnObject) +{ + ACPI_OPERAND_OBJECT *NewObject; + ACPI_STATUS Status; + ACPI_OPERAND_OBJECT **Elements; + UINT32 *DwordBuffer; + UINT32 Count; + UINT32 i; + + + switch (OriginalObject->Common.Type) + { + case ACPI_TYPE_INTEGER: + /* + * Integer-to-Buffer conversion. + * Convert the Integer to a packed-byte buffer. _MAT and other + * objects need this sometimes, if a read has been performed on a + * Field object that is less than or equal to the global integer + * size (32 or 64 bits). + */ + Status = AcpiExConvertToBuffer (OriginalObject, &NewObject); + if (ACPI_FAILURE (Status)) + { + return (Status); + } + break; + + case ACPI_TYPE_STRING: + + /* String-to-Buffer conversion. Simple data copy */ + + NewObject = AcpiUtCreateBufferObject (OriginalObject->String.Length); + if (!NewObject) + { + return (AE_NO_MEMORY); + } + + ACPI_MEMCPY (NewObject->Buffer.Pointer, + OriginalObject->String.Pointer, OriginalObject->String.Length); + break; + + case ACPI_TYPE_PACKAGE: + /* + * This case is often seen for predefined names that must return a + * Buffer object with multiple DWORD integers within. For example, + * _FDE and _GTM. The Package can be converted to a Buffer. + */ + + /* All elements of the Package must be integers */ + + Elements = OriginalObject->Package.Elements; + Count = OriginalObject->Package.Count; + + for (i = 0; i < Count; i++) + { + if ((!*Elements) || + ((*Elements)->Common.Type != ACPI_TYPE_INTEGER)) + { + return (AE_AML_OPERAND_TYPE); + } + Elements++; + } + + /* Create the new buffer object to replace the Package */ + + NewObject = AcpiUtCreateBufferObject (ACPI_MUL_4 (Count)); + if (!NewObject) + { + return (AE_NO_MEMORY); + } + + /* Copy the package elements (integers) to the buffer as DWORDs */ + + Elements = OriginalObject->Package.Elements; + DwordBuffer = ACPI_CAST_PTR (UINT32, NewObject->Buffer.Pointer); + + for (i = 0; i < Count; i++) + { + *DwordBuffer = (UINT32) (*Elements)->Integer.Value; + DwordBuffer++; + Elements++; + } + break; + + default: + return (AE_AML_OPERAND_TYPE); + } + + *ReturnObject = NewObject; + return (AE_OK); +} + + +/******************************************************************************* + * + * FUNCTION: AcpiNsConvertToUnicode + * + * PARAMETERS: OriginalObject - ASCII String Object to be converted + * ReturnObject - Where the new converted object is returned + * + * RETURN: Status. AE_OK if conversion was successful. + * + * DESCRIPTION: Attempt to convert a String object to a Unicode string Buffer. + * + ******************************************************************************/ + +ACPI_STATUS +AcpiNsConvertToUnicode ( + ACPI_OPERAND_OBJECT *OriginalObject, + ACPI_OPERAND_OBJECT **ReturnObject) +{ + ACPI_OPERAND_OBJECT *NewObject; + char *AsciiString; + UINT16 *UnicodeBuffer; + UINT32 UnicodeLength; + UINT32 i; + + + if (!OriginalObject) + { + return (AE_OK); + } + + /* If a Buffer was returned, it must be at least two bytes long */ + + if (OriginalObject->Common.Type == ACPI_TYPE_BUFFER) + { + if (OriginalObject->Buffer.Length < 2) + { + return (AE_AML_OPERAND_VALUE); + } + + *ReturnObject = NULL; + return (AE_OK); + } + + /* + * The original object is an ASCII string. Convert this string to + * a unicode buffer. + */ + AsciiString = OriginalObject->String.Pointer; + UnicodeLength = (OriginalObject->String.Length * 2) + 2; + + /* Create a new buffer object for the Unicode data */ + + NewObject = AcpiUtCreateBufferObject (UnicodeLength); + if (!NewObject) + { + return (AE_NO_MEMORY); + } + + UnicodeBuffer = ACPI_CAST_PTR (UINT16, NewObject->Buffer.Pointer); + + /* Convert ASCII to Unicode */ + + for (i = 0; i < OriginalObject->String.Length; i++) + { + UnicodeBuffer[i] = (UINT16) AsciiString[i]; + } + + *ReturnObject = NewObject; + return (AE_OK); +} + + +/******************************************************************************* + * + * FUNCTION: AcpiNsConvertToResource + * + * PARAMETERS: OriginalObject - Object to be converted + * ReturnObject - Where the new converted object is returned + * + * RETURN: Status. AE_OK if conversion was successful + * + * DESCRIPTION: Attempt to convert a Integer object to a ResourceTemplate + * Buffer. + * + ******************************************************************************/ + +ACPI_STATUS +AcpiNsConvertToResource ( + ACPI_OPERAND_OBJECT *OriginalObject, + ACPI_OPERAND_OBJECT **ReturnObject) +{ + ACPI_OPERAND_OBJECT *NewObject; + UINT8 *Buffer; + + + /* + * We can fix the following cases for an expected resource template: + * 1. No return value (interpreter slack mode is disabled) + * 2. A "Return (Zero)" statement + * 3. A "Return empty buffer" statement + * + * We will return a buffer containing a single EndTag + * resource descriptor. + */ + if (OriginalObject) + { + switch (OriginalObject->Common.Type) + { + case ACPI_TYPE_INTEGER: + + /* We can only repair an Integer==0 */ + + if (OriginalObject->Integer.Value) + { + return (AE_AML_OPERAND_TYPE); + } + break; + + case ACPI_TYPE_BUFFER: + + if (OriginalObject->Buffer.Length) + { + /* Additional checks can be added in the future */ + + *ReturnObject = NULL; + return (AE_OK); + } + break; + + case ACPI_TYPE_STRING: + default: + + return (AE_AML_OPERAND_TYPE); + } + } + + /* Create the new buffer object for the resource descriptor */ + + NewObject = AcpiUtCreateBufferObject (2); + if (!NewObject) + { + return (AE_NO_MEMORY); + } + + Buffer = ACPI_CAST_PTR (UINT8, NewObject->Buffer.Pointer); + + /* Initialize the Buffer with a single EndTag descriptor */ + + Buffer[0] = (ACPI_RESOURCE_NAME_END_TAG | ASL_RDESC_END_TAG_SIZE); + Buffer[1] = 0x00; + + *ReturnObject = NewObject; + return (AE_OK); +} diff --git a/sys/contrib/dev/acpica/components/namespace/nspredef.c b/sys/contrib/dev/acpica/components/namespace/nspredef.c index 8c65b84..b925896 100644 --- a/sys/contrib/dev/acpica/components/namespace/nspredef.c +++ b/sys/contrib/dev/acpica/components/namespace/nspredef.c @@ -87,6 +87,11 @@ AcpiNsGetExpectedTypes ( char *Buffer, UINT32 ExpectedBtypes); +static UINT32 +AcpiNsGetBitmappedType ( + ACPI_OPERAND_OBJECT *ReturnObject); + + /* * Names for the types that can be returned by the predefined objects. * Used for warning messages. Must be in the same order as the ACPI_RTYPEs @@ -124,7 +129,6 @@ AcpiNsCheckPredefinedNames ( ACPI_STATUS ReturnStatus, ACPI_OPERAND_OBJECT **ReturnObjectPtr) { - ACPI_OPERAND_OBJECT *ReturnObject = *ReturnObjectPtr; ACPI_STATUS Status = AE_OK; const ACPI_PREDEFINED_INFO *Predefined; char *Pathname; @@ -167,26 +171,6 @@ AcpiNsCheckPredefinedNames ( } /* - * If there is no return value, check if we require a return value for - * this predefined name. Either one return value is expected, or none, - * for both methods and other objects. - * - * Exit now if there is no return object. Warning if one was expected. - */ - if (!ReturnObject) - { - if ((Predefined->Info.ExpectedBtypes) && - (!(Predefined->Info.ExpectedBtypes & ACPI_RTYPE_NONE))) - { - ACPI_WARN_PREDEFINED ((AE_INFO, Pathname, ACPI_WARN_ALWAYS, - "Missing expected return value")); - - Status = AE_AML_NO_RETURN_VALUE; - } - goto Cleanup; - } - - /* * Return value validation and possible repair. * * 1) Don't perform return value validation/repair if this feature @@ -447,30 +431,13 @@ AcpiNsCheckObjectType ( { ACPI_OPERAND_OBJECT *ReturnObject = *ReturnObjectPtr; ACPI_STATUS Status = AE_OK; - UINT32 ReturnBtype; char TypeBuffer[48]; /* Room for 5 types */ - /* - * If we get a NULL ReturnObject here, it is a NULL package element. - * Since all extraneous NULL package elements were removed earlier by a - * call to AcpiNsRemoveNullElements, this is an unexpected NULL element. - * We will attempt to repair it. - */ - if (!ReturnObject) - { - Status = AcpiNsRepairNullElement (Data, ExpectedBtypes, - PackageIndex, ReturnObjectPtr); - if (ACPI_SUCCESS (Status)) - { - return (AE_OK); /* Repair was successful */ - } - goto TypeErrorExit; - } - /* A Namespace node should not get here, but make sure */ - if (ACPI_GET_DESCRIPTOR_TYPE (ReturnObject) == ACPI_DESC_TYPE_NAMED) + if (ReturnObject && + ACPI_GET_DESCRIPTOR_TYPE (ReturnObject) == ACPI_DESC_TYPE_NAMED) { ACPI_WARN_PREDEFINED ((AE_INFO, Data->Pathname, Data->NodeFlags, "Invalid return type - Found a Namespace node [%4.4s] type %s", @@ -487,56 +454,26 @@ AcpiNsCheckObjectType ( * from all of the predefined names (including elements of returned * packages) */ - switch (ReturnObject->Common.Type) + Data->ReturnBtype = AcpiNsGetBitmappedType (ReturnObject); + if (Data->ReturnBtype == ACPI_RTYPE_ANY) { - case ACPI_TYPE_INTEGER: - ReturnBtype = ACPI_RTYPE_INTEGER; - break; - - case ACPI_TYPE_BUFFER: - ReturnBtype = ACPI_RTYPE_BUFFER; - break; - - case ACPI_TYPE_STRING: - ReturnBtype = ACPI_RTYPE_STRING; - break; - - case ACPI_TYPE_PACKAGE: - ReturnBtype = ACPI_RTYPE_PACKAGE; - break; - - case ACPI_TYPE_LOCAL_REFERENCE: - ReturnBtype = ACPI_RTYPE_REFERENCE; - break; - - default: /* Not one of the supported objects, must be incorrect */ - goto TypeErrorExit; } - /* Is the object one of the expected types? */ + /* For reference objects, check that the reference type is correct */ - if (ReturnBtype & ExpectedBtypes) + if ((Data->ReturnBtype & ExpectedBtypes) == ACPI_RTYPE_REFERENCE) { - /* For reference objects, check that the reference type is correct */ - - if (ReturnObject->Common.Type == ACPI_TYPE_LOCAL_REFERENCE) - { - Status = AcpiNsCheckReference (Data, ReturnObject); - } - + Status = AcpiNsCheckReference (Data, ReturnObject); return (Status); } - /* Type mismatch -- attempt repair of the returned object */ + /* Attempt simple repair of the returned object if necessary */ - Status = AcpiNsRepairObject (Data, ExpectedBtypes, + Status = AcpiNsSimpleRepair (Data, ExpectedBtypes, PackageIndex, ReturnObjectPtr); - if (ACPI_SUCCESS (Status)) - { - return (AE_OK); /* Repair was successful */ - } + return (Status); TypeErrorExit: @@ -606,6 +543,67 @@ AcpiNsCheckReference ( /******************************************************************************* * + * FUNCTION: AcpiNsGetBitmappedType + * + * PARAMETERS: ReturnObject - Object returned from method/obj evaluation + * + * RETURN: Object return type. ACPI_RTYPE_ANY indicates that the object + * type is not supported. ACPI_RTYPE_NONE indicates that no + * object was returned (ReturnObject is NULL). + * + * DESCRIPTION: Convert object type into a bitmapped object return type. + * + ******************************************************************************/ + +static UINT32 +AcpiNsGetBitmappedType ( + ACPI_OPERAND_OBJECT *ReturnObject) +{ + UINT32 ReturnBtype; + + + if (!ReturnObject) + { + return (ACPI_RTYPE_NONE); + } + + /* Map ACPI_OBJECT_TYPE to internal bitmapped type */ + + switch (ReturnObject->Common.Type) + { + case ACPI_TYPE_INTEGER: + ReturnBtype = ACPI_RTYPE_INTEGER; + break; + + case ACPI_TYPE_BUFFER: + ReturnBtype = ACPI_RTYPE_BUFFER; + break; + + case ACPI_TYPE_STRING: + ReturnBtype = ACPI_RTYPE_STRING; + break; + + case ACPI_TYPE_PACKAGE: + ReturnBtype = ACPI_RTYPE_PACKAGE; + break; + + case ACPI_TYPE_LOCAL_REFERENCE: + ReturnBtype = ACPI_RTYPE_REFERENCE; + break; + + default: + /* Not one of the supported objects, must be incorrect */ + + ReturnBtype = ACPI_RTYPE_ANY; + break; + } + + return (ReturnBtype); +} + + +/******************************************************************************* + * * FUNCTION: AcpiNsGetExpectedTypes * * PARAMETERS: Buffer - Pointer to where the string is returned diff --git a/sys/contrib/dev/acpica/components/namespace/nsprepkg.c b/sys/contrib/dev/acpica/components/namespace/nsprepkg.c index 7b65b80..ef01d00 100644 --- a/sys/contrib/dev/acpica/components/namespace/nsprepkg.c +++ b/sys/contrib/dev/acpica/components/namespace/nsprepkg.c @@ -122,10 +122,17 @@ AcpiNsCheckPackage ( Elements = ReturnObject->Package.Elements; Count = ReturnObject->Package.Count; - /* The package must have at least one element, else invalid */ - + /* + * Most packages must have at least one element. The only exception + * is the variable-length package (ACPI_PTYPE1_VAR). + */ if (!Count) { + if (Package->RetInfo.Type == ACPI_PTYPE1_VAR) + { + return (AE_OK); + } + ACPI_WARN_PREDEFINED ((AE_INFO, Data->Pathname, Data->NodeFlags, "Return Package has no elements (empty)")); diff --git a/sys/contrib/dev/acpica/components/namespace/nsrepair.c b/sys/contrib/dev/acpica/components/namespace/nsrepair.c index c5c9309..1a152e7 100644 --- a/sys/contrib/dev/acpica/components/namespace/nsrepair.c +++ b/sys/contrib/dev/acpica/components/namespace/nsrepair.c @@ -48,6 +48,7 @@ #include <contrib/dev/acpica/include/acnamesp.h> #include <contrib/dev/acpica/include/acinterp.h> #include <contrib/dev/acpica/include/acpredef.h> +#include <contrib/dev/acpica/include/amlresrc.h> #define _COMPONENT ACPI_NAMESPACE ACPI_MODULE_NAME ("nsrepair") @@ -74,6 +75,11 @@ * Buffer -> String * Buffer -> Package of Integers * Package -> Package of one Package + * + * Additional conversions that are available: + * Convert a null return or zero return value to an EndTag descriptor + * Convert an ASCII string to a Unicode buffer + * * An incorrect standalone object is wrapped with required outer package * * Additional possible repairs: @@ -84,25 +90,46 @@ /* Local prototypes */ -static ACPI_STATUS -AcpiNsConvertToInteger ( - ACPI_OPERAND_OBJECT *OriginalObject, - ACPI_OPERAND_OBJECT **ReturnObject); +static const ACPI_SIMPLE_REPAIR_INFO * +AcpiNsMatchSimpleRepair ( + ACPI_NAMESPACE_NODE *Node, + UINT32 ReturnBtype, + UINT32 PackageIndex); -static ACPI_STATUS -AcpiNsConvertToString ( - ACPI_OPERAND_OBJECT *OriginalObject, - ACPI_OPERAND_OBJECT **ReturnObject); -static ACPI_STATUS -AcpiNsConvertToBuffer ( - ACPI_OPERAND_OBJECT *OriginalObject, - ACPI_OPERAND_OBJECT **ReturnObject); +/* + * Special but simple repairs for some names. + * + * 2nd argument: Unexpected types that can be repaired + */ +static const ACPI_SIMPLE_REPAIR_INFO AcpiObjectRepairInfo[] = +{ + /* Resource descriptor conversions */ + + { "_CRS", ACPI_RTYPE_INTEGER | ACPI_RTYPE_STRING | ACPI_RTYPE_BUFFER | ACPI_RTYPE_NONE, + ACPI_NOT_PACKAGE_ELEMENT, + AcpiNsConvertToResource }, + { "_DMA", ACPI_RTYPE_INTEGER | ACPI_RTYPE_STRING | ACPI_RTYPE_BUFFER | ACPI_RTYPE_NONE, + ACPI_NOT_PACKAGE_ELEMENT, + AcpiNsConvertToResource }, + { "_PRS", ACPI_RTYPE_INTEGER | ACPI_RTYPE_STRING | ACPI_RTYPE_BUFFER | ACPI_RTYPE_NONE, + ACPI_NOT_PACKAGE_ELEMENT, + AcpiNsConvertToResource }, + + /* Unicode conversions */ + + { "_MLS", ACPI_RTYPE_STRING, 1, + AcpiNsConvertToUnicode }, + { "_STR", ACPI_RTYPE_STRING | ACPI_RTYPE_BUFFER, + ACPI_NOT_PACKAGE_ELEMENT, + AcpiNsConvertToUnicode }, + { {0,0,0,0}, 0, 0, NULL } /* Table terminator */ +}; /******************************************************************************* * - * FUNCTION: AcpiNsRepairObject + * FUNCTION: AcpiNsSimpleRepair * * PARAMETERS: Data - Pointer to validation data structure * ExpectedBtypes - Object types expected @@ -120,19 +147,58 @@ AcpiNsConvertToBuffer ( ******************************************************************************/ ACPI_STATUS -AcpiNsRepairObject ( +AcpiNsSimpleRepair ( ACPI_PREDEFINED_DATA *Data, UINT32 ExpectedBtypes, UINT32 PackageIndex, ACPI_OPERAND_OBJECT **ReturnObjectPtr) { ACPI_OPERAND_OBJECT *ReturnObject = *ReturnObjectPtr; - ACPI_OPERAND_OBJECT *NewObject; + ACPI_OPERAND_OBJECT *NewObject = NULL; ACPI_STATUS Status; + const ACPI_SIMPLE_REPAIR_INFO *Predefined; + + + ACPI_FUNCTION_NAME (NsSimpleRepair); - ACPI_FUNCTION_NAME (NsRepairObject); + /* + * Special repairs for certain names that are in the repair table. + * Check if this name is in the list of repairable names. + */ + Predefined = AcpiNsMatchSimpleRepair (Data->Node, + Data->ReturnBtype, PackageIndex); + if (Predefined) + { + if (!ReturnObject) + { + ACPI_WARN_PREDEFINED ((AE_INFO, Data->Pathname, + ACPI_WARN_ALWAYS, "Missing expected return value")); + } + + Status = Predefined->ObjectConverter (ReturnObject, &NewObject); + if (ACPI_FAILURE (Status)) + { + /* A fatal error occurred during a conversion */ + + ACPI_EXCEPTION ((AE_INFO, Status, + "During return object analysis")); + return (Status); + } + if (NewObject) + { + goto ObjectRepaired; + } + } + /* + * Do not perform simple object repair unless the return type is not + * expected. + */ + if (Data->ReturnBtype & ExpectedBtypes) + { + return (AE_OK); + } /* * At this point, we know that the type of the returned object was not @@ -140,6 +206,25 @@ AcpiNsRepairObject ( * repair the object by converting it to one of the expected object * types for this predefined name. */ + + /* + * If there is no return value, check if we require a return value for + * this predefined name. Either one return value is expected, or none, + * for both methods and other objects. + * + * Exit now if there is no return object. Warning if one was expected. + */ + if (!ReturnObject) + { + if (ExpectedBtypes && (!(ExpectedBtypes & ACPI_RTYPE_NONE))) + { + ACPI_WARN_PREDEFINED ((AE_INFO, Data->Pathname, + ACPI_WARN_ALWAYS, "Missing expected return value")); + + return (AE_AML_NO_RETURN_VALUE); + } + } + if (ExpectedBtypes & ACPI_RTYPE_INTEGER) { Status = AcpiNsConvertToInteger (ReturnObject, &NewObject); @@ -240,273 +325,52 @@ ObjectRepaired: } -/******************************************************************************* - * - * FUNCTION: AcpiNsConvertToInteger - * - * PARAMETERS: OriginalObject - Object to be converted - * ReturnObject - Where the new converted object is returned - * - * RETURN: Status. AE_OK if conversion was successful. - * - * DESCRIPTION: Attempt to convert a String/Buffer object to an Integer. - * - ******************************************************************************/ - -static ACPI_STATUS -AcpiNsConvertToInteger ( - ACPI_OPERAND_OBJECT *OriginalObject, - ACPI_OPERAND_OBJECT **ReturnObject) -{ - ACPI_OPERAND_OBJECT *NewObject; - ACPI_STATUS Status; - UINT64 Value = 0; - UINT32 i; - - - switch (OriginalObject->Common.Type) - { - case ACPI_TYPE_STRING: - - /* String-to-Integer conversion */ - - Status = AcpiUtStrtoul64 (OriginalObject->String.Pointer, - ACPI_ANY_BASE, &Value); - if (ACPI_FAILURE (Status)) - { - return (Status); - } - break; - - case ACPI_TYPE_BUFFER: - - /* Buffer-to-Integer conversion. Max buffer size is 64 bits. */ - - if (OriginalObject->Buffer.Length > 8) - { - return (AE_AML_OPERAND_TYPE); - } - - /* Extract each buffer byte to create the integer */ - - for (i = 0; i < OriginalObject->Buffer.Length; i++) - { - Value |= ((UINT64) OriginalObject->Buffer.Pointer[i] << (i * 8)); - } - break; - - default: - return (AE_AML_OPERAND_TYPE); - } - - NewObject = AcpiUtCreateIntegerObject (Value); - if (!NewObject) - { - return (AE_NO_MEMORY); - } - - *ReturnObject = NewObject; - return (AE_OK); -} - - -/******************************************************************************* +/****************************************************************************** * - * FUNCTION: AcpiNsConvertToString + * FUNCTION: AcpiNsMatchSimpleRepair * - * PARAMETERS: OriginalObject - Object to be converted - * ReturnObject - Where the new converted object is returned + * PARAMETERS: Node - Namespace node for the method/object + * ReturnBtype - Object type that was returned + * PackageIndex - Index of object within parent package (if + * applicable - ACPI_NOT_PACKAGE_ELEMENT + * otherwise) * - * RETURN: Status. AE_OK if conversion was successful. + * RETURN: Pointer to entry in repair table. NULL indicates not found. * - * DESCRIPTION: Attempt to convert a Integer/Buffer object to a String. + * DESCRIPTION: Check an object name against the repairable object list. * - ******************************************************************************/ + *****************************************************************************/ -static ACPI_STATUS -AcpiNsConvertToString ( - ACPI_OPERAND_OBJECT *OriginalObject, - ACPI_OPERAND_OBJECT **ReturnObject) +static const ACPI_SIMPLE_REPAIR_INFO * +AcpiNsMatchSimpleRepair ( + ACPI_NAMESPACE_NODE *Node, + UINT32 ReturnBtype, + UINT32 PackageIndex) { - ACPI_OPERAND_OBJECT *NewObject; - ACPI_SIZE Length; - ACPI_STATUS Status; - - - switch (OriginalObject->Common.Type) - { - case ACPI_TYPE_INTEGER: - /* - * Integer-to-String conversion. Commonly, convert - * an integer of value 0 to a NULL string. The last element of - * _BIF and _BIX packages occasionally need this fix. - */ - if (OriginalObject->Integer.Value == 0) - { - /* Allocate a new NULL string object */ - - NewObject = AcpiUtCreateStringObject (0); - if (!NewObject) - { - return (AE_NO_MEMORY); - } - } - else - { - Status = AcpiExConvertToString (OriginalObject, &NewObject, - ACPI_IMPLICIT_CONVERT_HEX); - if (ACPI_FAILURE (Status)) - { - return (Status); - } - } - break; - - case ACPI_TYPE_BUFFER: - /* - * Buffer-to-String conversion. Use a ToString - * conversion, no transform performed on the buffer data. The best - * example of this is the _BIF method, where the string data from - * the battery is often (incorrectly) returned as buffer object(s). - */ - Length = 0; - while ((Length < OriginalObject->Buffer.Length) && - (OriginalObject->Buffer.Pointer[Length])) - { - Length++; - } - - /* Allocate a new string object */ - - NewObject = AcpiUtCreateStringObject (Length); - if (!NewObject) - { - return (AE_NO_MEMORY); - } - - /* - * Copy the raw buffer data with no transform. String is already NULL - * terminated at Length+1. - */ - ACPI_MEMCPY (NewObject->String.Pointer, - OriginalObject->Buffer.Pointer, Length); - break; - - default: - return (AE_AML_OPERAND_TYPE); - } - - *ReturnObject = NewObject; - return (AE_OK); -} - + const ACPI_SIMPLE_REPAIR_INFO *ThisName; -/******************************************************************************* - * - * FUNCTION: AcpiNsConvertToBuffer - * - * PARAMETERS: OriginalObject - Object to be converted - * ReturnObject - Where the new converted object is returned - * - * RETURN: Status. AE_OK if conversion was successful. - * - * DESCRIPTION: Attempt to convert a Integer/String/Package object to a Buffer. - * - ******************************************************************************/ - -static ACPI_STATUS -AcpiNsConvertToBuffer ( - ACPI_OPERAND_OBJECT *OriginalObject, - ACPI_OPERAND_OBJECT **ReturnObject) -{ - ACPI_OPERAND_OBJECT *NewObject; - ACPI_STATUS Status; - ACPI_OPERAND_OBJECT **Elements; - UINT32 *DwordBuffer; - UINT32 Count; - UINT32 i; + /* Search info table for a repairable predefined method/object name */ - switch (OriginalObject->Common.Type) + ThisName = AcpiObjectRepairInfo; + while (ThisName->ObjectConverter) { - case ACPI_TYPE_INTEGER: - /* - * Integer-to-Buffer conversion. - * Convert the Integer to a packed-byte buffer. _MAT and other - * objects need this sometimes, if a read has been performed on a - * Field object that is less than or equal to the global integer - * size (32 or 64 bits). - */ - Status = AcpiExConvertToBuffer (OriginalObject, &NewObject); - if (ACPI_FAILURE (Status)) - { - return (Status); - } - break; - - case ACPI_TYPE_STRING: - - /* String-to-Buffer conversion. Simple data copy */ - - NewObject = AcpiUtCreateBufferObject (OriginalObject->String.Length); - if (!NewObject) + if (ACPI_COMPARE_NAME (Node->Name.Ascii, ThisName->Name)) { - return (AE_NO_MEMORY); - } - - ACPI_MEMCPY (NewObject->Buffer.Pointer, - OriginalObject->String.Pointer, OriginalObject->String.Length); - break; - - case ACPI_TYPE_PACKAGE: - /* - * This case is often seen for predefined names that must return a - * Buffer object with multiple DWORD integers within. For example, - * _FDE and _GTM. The Package can be converted to a Buffer. - */ - - /* All elements of the Package must be integers */ - - Elements = OriginalObject->Package.Elements; - Count = OriginalObject->Package.Count; + /* Check if we can actually repair this name/type combination */ - for (i = 0; i < Count; i++) - { - if ((!*Elements) || - ((*Elements)->Common.Type != ACPI_TYPE_INTEGER)) + if ((ReturnBtype & ThisName->UnexpectedBtypes) && + (PackageIndex == ThisName->PackageIndex)) { - return (AE_AML_OPERAND_TYPE); + return (ThisName); } - Elements++; - } - - /* Create the new buffer object to replace the Package */ - NewObject = AcpiUtCreateBufferObject (ACPI_MUL_4 (Count)); - if (!NewObject) - { - return (AE_NO_MEMORY); - } - - /* Copy the package elements (integers) to the buffer as DWORDs */ - - Elements = OriginalObject->Package.Elements; - DwordBuffer = ACPI_CAST_PTR (UINT32, NewObject->Buffer.Pointer); - - for (i = 0; i < Count; i++) - { - *DwordBuffer = (UINT32) (*Elements)->Integer.Value; - DwordBuffer++; - Elements++; + return (NULL); } - break; - - default: - return (AE_AML_OPERAND_TYPE); + ThisName++; } - *ReturnObject = NewObject; - return (AE_OK); + return (NULL); /* Name was not found in the repair table */ } diff --git a/sys/contrib/dev/acpica/components/namespace/nsrepair2.c b/sys/contrib/dev/acpica/components/namespace/nsrepair2.c index a6559f4..76a9a64 100644 --- a/sys/contrib/dev/acpica/components/namespace/nsrepair2.c +++ b/sys/contrib/dev/acpica/components/namespace/nsrepair2.c @@ -72,7 +72,7 @@ typedef struct acpi_repair_info /* Local prototypes */ static const ACPI_REPAIR_INFO * -AcpiNsMatchRepairableName ( +AcpiNsMatchComplexRepair ( ACPI_NAMESPACE_NODE *Node); static ACPI_STATUS @@ -197,7 +197,7 @@ AcpiNsComplexRepairs ( /* Check if this name is in the list of repairable names */ - Predefined = AcpiNsMatchRepairableName (Node); + Predefined = AcpiNsMatchComplexRepair (Node); if (!Predefined) { return (ValidateStatus); @@ -210,7 +210,7 @@ AcpiNsComplexRepairs ( /****************************************************************************** * - * FUNCTION: AcpiNsMatchRepairableName + * FUNCTION: AcpiNsMatchComplexRepair * * PARAMETERS: Node - Namespace node for the method/object * @@ -221,7 +221,7 @@ AcpiNsComplexRepairs ( *****************************************************************************/ static const ACPI_REPAIR_INFO * -AcpiNsMatchRepairableName ( +AcpiNsMatchComplexRepair ( ACPI_NAMESPACE_NODE *Node) { const ACPI_REPAIR_INFO *ThisName; diff --git a/sys/contrib/dev/acpica/components/namespace/nsutils.c b/sys/contrib/dev/acpica/components/namespace/nsutils.c index 070ed26..31f9496 100644 --- a/sys/contrib/dev/acpica/components/namespace/nsutils.c +++ b/sys/contrib/dev/acpica/components/namespace/nsutils.c @@ -128,10 +128,10 @@ AcpiNsGetType ( if (!Node) { ACPI_WARNING ((AE_INFO, "Null Node parameter")); - return_VALUE (ACPI_TYPE_ANY); + return_UINT8 (ACPI_TYPE_ANY); } - return_VALUE (Node->Type); + return_UINT8 (Node->Type); } @@ -160,10 +160,10 @@ AcpiNsLocal ( /* Type code out of range */ ACPI_WARNING ((AE_INFO, "Invalid Object Type 0x%X", Type)); - return_VALUE (ACPI_NS_NORMAL); + return_UINT32 (ACPI_NS_NORMAL); } - return_VALUE (AcpiGbl_NsProperties[Type] & ACPI_NS_LOCAL); + return_UINT32 (AcpiGbl_NsProperties[Type] & ACPI_NS_LOCAL); } diff --git a/sys/contrib/dev/acpica/components/parser/psargs.c b/sys/contrib/dev/acpica/components/parser/psargs.c index c57f485..4b8a240 100644 --- a/sys/contrib/dev/acpica/components/parser/psargs.c +++ b/sys/contrib/dev/acpica/components/parser/psargs.c @@ -118,7 +118,7 @@ AcpiPsGetNextPackageLength ( /* Byte 0 is a special case, either bits [0:3] or [0:5] are used */ PackageLength |= (Aml[0] & ByteZeroMask); - return_VALUE (PackageLength); + return_UINT32 (PackageLength); } diff --git a/sys/contrib/dev/acpica/components/resources/rscalc.c b/sys/contrib/dev/acpica/components/resources/rscalc.c index 3b43775..9dd3321 100644 --- a/sys/contrib/dev/acpica/components/resources/rscalc.c +++ b/sys/contrib/dev/acpica/components/resources/rscalc.c @@ -230,6 +230,13 @@ AcpiRsGetAmlLength ( return_ACPI_STATUS (AE_AML_INVALID_RESOURCE_TYPE); } + /* Sanity check the length. It must not be zero, or we loop forever */ + + if (!Resource->Length) + { + return_ACPI_STATUS (AE_AML_BAD_RESOURCE_LENGTH); + } + /* Get the base size of the (external stream) resource descriptor */ TotalSize = AcpiGbl_AmlResourceSizes [Resource->Type]; diff --git a/sys/contrib/dev/acpica/components/resources/rsdump.c b/sys/contrib/dev/acpica/components/resources/rsdump.c index 20c1893..e89f467 100644 --- a/sys/contrib/dev/acpica/components/resources/rsdump.c +++ b/sys/contrib/dev/acpica/components/resources/rsdump.c @@ -438,6 +438,15 @@ AcpiRsDumpResourceList ( return; } + /* Sanity check the length. It must not be zero, or we loop forever */ + + if (!ResourceList->Length) + { + AcpiOsPrintf ( + "Invalid zero length descriptor in resource list\n"); + return; + } + /* Dump the resource descriptor */ if (Type == ACPI_RESOURCE_TYPE_SERIAL_BUS) diff --git a/sys/contrib/dev/acpica/components/resources/rslist.c b/sys/contrib/dev/acpica/components/resources/rslist.c index 2c69c349..81e7292 100644 --- a/sys/contrib/dev/acpica/components/resources/rslist.c +++ b/sys/contrib/dev/acpica/components/resources/rslist.c @@ -199,6 +199,15 @@ AcpiRsConvertResourcesToAml ( return_ACPI_STATUS (AE_BAD_DATA); } + /* Sanity check the length. It must not be zero, or we loop forever */ + + if (!Resource->Length) + { + ACPI_ERROR ((AE_INFO, + "Invalid zero length descriptor in resource list\n")); + return_ACPI_STATUS (AE_AML_BAD_RESOURCE_LENGTH); + } + /* Perform the conversion */ if (Resource->Type == ACPI_RESOURCE_TYPE_SERIAL_BUS) diff --git a/sys/contrib/dev/acpica/components/resources/rsxface.c b/sys/contrib/dev/acpica/components/resources/rsxface.c index f70d8f6..557fa2f 100644 --- a/sys/contrib/dev/acpica/components/resources/rsxface.c +++ b/sys/contrib/dev/acpica/components/resources/rsxface.c @@ -630,7 +630,7 @@ AcpiWalkResourceBuffer ( while (Resource < ResourceEnd) { - /* Sanity check the resource */ + /* Sanity check the resource type */ if (Resource->Type > ACPI_RESOURCE_TYPE_MAX) { @@ -638,6 +638,13 @@ AcpiWalkResourceBuffer ( break; } + /* Sanity check the length. It must not be zero, or we loop forever */ + + if (!Resource->Length) + { + return_ACPI_STATUS (AE_AML_BAD_RESOURCE_LENGTH); + } + /* Invoke the user function, abort on any error returned */ Status = UserFunction (Resource, Context); diff --git a/sys/contrib/dev/acpica/components/utilities/utaddress.c b/sys/contrib/dev/acpica/components/utilities/utaddress.c index 715c77b..da8b046 100644 --- a/sys/contrib/dev/acpica/components/utilities/utaddress.c +++ b/sys/contrib/dev/acpica/components/utilities/utaddress.c @@ -237,7 +237,7 @@ AcpiUtCheckAddressRange ( if ((SpaceId != ACPI_ADR_SPACE_SYSTEM_MEMORY) && (SpaceId != ACPI_ADR_SPACE_SYSTEM_IO)) { - return_VALUE (0); + return_UINT32 (0); } RangeInfo = AcpiGbl_AddressRangeList[SpaceId]; @@ -278,7 +278,7 @@ AcpiUtCheckAddressRange ( RangeInfo = RangeInfo->Next; } - return_VALUE (OverlapCount); + return_UINT32 (OverlapCount); } diff --git a/sys/contrib/dev/acpica/components/utilities/utexcep.c b/sys/contrib/dev/acpica/components/utilities/utexcep.c index 2d3ae17..84df77d 100644 --- a/sys/contrib/dev/acpica/components/utilities/utexcep.c +++ b/sys/contrib/dev/acpica/components/utilities/utexcep.c @@ -71,7 +71,7 @@ const char * AcpiFormatException ( ACPI_STATUS Status) { - const char *Exception = NULL; + const ACPI_EXCEPTION_INFO *Exception; ACPI_FUNCTION_ENTRY (); @@ -85,10 +85,10 @@ AcpiFormatException ( ACPI_ERROR ((AE_INFO, "Unknown exception code: 0x%8.8X", Status)); - Exception = "UNKNOWN_STATUS_CODE"; + return ("UNKNOWN_STATUS_CODE"); } - return (ACPI_CAST_PTR (const char, Exception)); + return (Exception->Name); } ACPI_EXPORT_SYMBOL (AcpiFormatException) @@ -108,12 +108,12 @@ ACPI_EXPORT_SYMBOL (AcpiFormatException) * ******************************************************************************/ -const char * +const ACPI_EXCEPTION_INFO * AcpiUtValidateException ( ACPI_STATUS Status) { - UINT32 SubStatus; - const char *Exception = NULL; + UINT32 SubStatus; + const ACPI_EXCEPTION_INFO *Exception = NULL; ACPI_FUNCTION_ENTRY (); @@ -130,7 +130,7 @@ AcpiUtValidateException ( if (SubStatus <= AE_CODE_ENV_MAX) { - Exception = AcpiGbl_ExceptionNames_Env [SubStatus]; + Exception = &AcpiGbl_ExceptionNames_Env [SubStatus]; } break; @@ -138,7 +138,7 @@ AcpiUtValidateException ( if (SubStatus <= AE_CODE_PGM_MAX) { - Exception = AcpiGbl_ExceptionNames_Pgm [SubStatus]; + Exception = &AcpiGbl_ExceptionNames_Pgm [SubStatus]; } break; @@ -146,7 +146,7 @@ AcpiUtValidateException ( if (SubStatus <= AE_CODE_TBL_MAX) { - Exception = AcpiGbl_ExceptionNames_Tbl [SubStatus]; + Exception = &AcpiGbl_ExceptionNames_Tbl [SubStatus]; } break; @@ -154,7 +154,7 @@ AcpiUtValidateException ( if (SubStatus <= AE_CODE_AML_MAX) { - Exception = AcpiGbl_ExceptionNames_Aml [SubStatus]; + Exception = &AcpiGbl_ExceptionNames_Aml [SubStatus]; } break; @@ -162,7 +162,7 @@ AcpiUtValidateException ( if (SubStatus <= AE_CODE_CTRL_MAX) { - Exception = AcpiGbl_ExceptionNames_Ctrl [SubStatus]; + Exception = &AcpiGbl_ExceptionNames_Ctrl [SubStatus]; } break; @@ -170,5 +170,10 @@ AcpiUtValidateException ( break; } - return (ACPI_CAST_PTR (const char, Exception)); + if (!Exception || !Exception->Name) + { + return (NULL); + } + + return (Exception); } diff --git a/sys/contrib/dev/acpica/components/utilities/utglobal.c b/sys/contrib/dev/acpica/components/utilities/utglobal.c index 6d2f906..d814aa0 100644 --- a/sys/contrib/dev/acpica/components/utilities/utglobal.c +++ b/sys/contrib/dev/acpica/components/utilities/utglobal.c @@ -343,6 +343,8 @@ AcpiUtInitGlobals ( #ifdef ACPI_DISASSEMBLER AcpiGbl_ExternalList = NULL; + AcpiGbl_NumExternalMethods = 0; + AcpiGbl_ResolvedExternalMethods = 0; #endif #ifdef ACPI_DEBUG_OUTPUT diff --git a/sys/contrib/dev/acpica/include/acdisasm.h b/sys/contrib/dev/acpica/include/acdisasm.h index eb6553b..ef41385 100644 --- a/sys/contrib/dev/acpica/include/acdisasm.h +++ b/sys/contrib/dev/acpica/include/acdisasm.h @@ -314,6 +314,8 @@ extern ACPI_DMTABLE_INFO AcpiDmTableInfoMpst1[]; extern ACPI_DMTABLE_INFO AcpiDmTableInfoMpst2[]; extern ACPI_DMTABLE_INFO AcpiDmTableInfoMsct[]; extern ACPI_DMTABLE_INFO AcpiDmTableInfoMsct0[]; +extern ACPI_DMTABLE_INFO AcpiDmTableInfoMtmr[]; +extern ACPI_DMTABLE_INFO AcpiDmTableInfoMtmr0[]; extern ACPI_DMTABLE_INFO AcpiDmTableInfoPmtt[]; extern ACPI_DMTABLE_INFO AcpiDmTableInfoPmtt0[]; extern ACPI_DMTABLE_INFO AcpiDmTableInfoPmtt1[]; @@ -343,6 +345,8 @@ extern ACPI_DMTABLE_INFO AcpiDmTableInfoSrat2[]; extern ACPI_DMTABLE_INFO AcpiDmTableInfoTcpa[]; extern ACPI_DMTABLE_INFO AcpiDmTableInfoTpm2[]; extern ACPI_DMTABLE_INFO AcpiDmTableInfoUefi[]; +extern ACPI_DMTABLE_INFO AcpiDmTableInfoVrtc[]; +extern ACPI_DMTABLE_INFO AcpiDmTableInfoVrtc0[]; extern ACPI_DMTABLE_INFO AcpiDmTableInfoWaet[]; extern ACPI_DMTABLE_INFO AcpiDmTableInfoWdat[]; extern ACPI_DMTABLE_INFO AcpiDmTableInfoWdat0[]; @@ -457,6 +461,10 @@ AcpiDmDumpMsct ( ACPI_TABLE_HEADER *Table); void +AcpiDmDumpMtmr ( + ACPI_TABLE_HEADER *Table); + +void AcpiDmDumpPcct ( ACPI_TABLE_HEADER *Table); @@ -489,6 +497,10 @@ AcpiDmDumpSrat ( ACPI_TABLE_HEADER *Table); void +AcpiDmDumpVrtc ( + ACPI_TABLE_HEADER *Table); + +void AcpiDmDumpWdat ( ACPI_TABLE_HEADER *Table); @@ -677,6 +689,10 @@ void AcpiDmEmitExternals ( void); +void +AcpiDmUnresolvedWarning ( + UINT8 Type); + /* * dmresrc diff --git a/sys/contrib/dev/acpica/include/acexcep.h b/sys/contrib/dev/acpica/include/acexcep.h index 110ef18..9961acc 100644 --- a/sys/contrib/dev/acpica/include/acexcep.h +++ b/sys/contrib/dev/acpica/include/acexcep.h @@ -45,55 +45,88 @@ #define __ACEXCEP_H__ +/* This module contains all possible exception codes for ACPI_STATUS */ + /* - * Exceptions returned by external ACPI interfaces + * Exception code classes */ -#define AE_CODE_ENVIRONMENTAL 0x0000 -#define AE_CODE_PROGRAMMER 0x1000 -#define AE_CODE_ACPI_TABLES 0x2000 -#define AE_CODE_AML 0x3000 -#define AE_CODE_CONTROL 0x4000 +#define AE_CODE_ENVIRONMENTAL 0x0000 /* General ACPICA environment */ +#define AE_CODE_PROGRAMMER 0x1000 /* External ACPICA interface caller */ +#define AE_CODE_ACPI_TABLES 0x2000 /* ACPI tables */ +#define AE_CODE_AML 0x3000 /* From executing AML code */ +#define AE_CODE_CONTROL 0x4000 /* Internal control codes */ + #define AE_CODE_MAX 0x4000 #define AE_CODE_MASK 0xF000 +/* + * Macros to insert the exception code classes + */ +#define EXCEP_ENV(code) ((ACPI_STATUS) (code | AE_CODE_ENVIRONMENTAL)) +#define EXCEP_PGM(code) ((ACPI_STATUS) (code | AE_CODE_PROGRAMMER)) +#define EXCEP_TBL(code) ((ACPI_STATUS) (code | AE_CODE_ACPI_TABLES)) +#define EXCEP_AML(code) ((ACPI_STATUS) (code | AE_CODE_AML)) +#define EXCEP_CTL(code) ((ACPI_STATUS) (code | AE_CODE_CONTROL)) + +/* + * Exception info table. The "Description" field is used only by the + * ACPICA help application (acpihelp). + */ +typedef struct acpi_exception_info +{ + char *Name; + +#ifdef ACPI_HELP_APP + char *Description; +#endif +} ACPI_EXCEPTION_INFO; + +#ifdef ACPI_HELP_APP +#define EXCEP_TXT(Name,Description) {Name, Description} +#else +#define EXCEP_TXT(Name,Description) {Name} +#endif + +/* + * Success is always zero, failure is non-zero + */ #define ACPI_SUCCESS(a) (!(a)) #define ACPI_FAILURE(a) (a) - #define AE_OK (ACPI_STATUS) 0x0000 /* * Environmental exceptions */ -#define AE_ERROR (ACPI_STATUS) (0x0001 | AE_CODE_ENVIRONMENTAL) -#define AE_NO_ACPI_TABLES (ACPI_STATUS) (0x0002 | AE_CODE_ENVIRONMENTAL) -#define AE_NO_NAMESPACE (ACPI_STATUS) (0x0003 | AE_CODE_ENVIRONMENTAL) -#define AE_NO_MEMORY (ACPI_STATUS) (0x0004 | AE_CODE_ENVIRONMENTAL) -#define AE_NOT_FOUND (ACPI_STATUS) (0x0005 | AE_CODE_ENVIRONMENTAL) -#define AE_NOT_EXIST (ACPI_STATUS) (0x0006 | AE_CODE_ENVIRONMENTAL) -#define AE_ALREADY_EXISTS (ACPI_STATUS) (0x0007 | AE_CODE_ENVIRONMENTAL) -#define AE_TYPE (ACPI_STATUS) (0x0008 | AE_CODE_ENVIRONMENTAL) -#define AE_NULL_OBJECT (ACPI_STATUS) (0x0009 | AE_CODE_ENVIRONMENTAL) -#define AE_NULL_ENTRY (ACPI_STATUS) (0x000A | AE_CODE_ENVIRONMENTAL) -#define AE_BUFFER_OVERFLOW (ACPI_STATUS) (0x000B | AE_CODE_ENVIRONMENTAL) -#define AE_STACK_OVERFLOW (ACPI_STATUS) (0x000C | AE_CODE_ENVIRONMENTAL) -#define AE_STACK_UNDERFLOW (ACPI_STATUS) (0x000D | AE_CODE_ENVIRONMENTAL) -#define AE_NOT_IMPLEMENTED (ACPI_STATUS) (0x000E | AE_CODE_ENVIRONMENTAL) -#define AE_SUPPORT (ACPI_STATUS) (0x000F | AE_CODE_ENVIRONMENTAL) -#define AE_LIMIT (ACPI_STATUS) (0x0010 | AE_CODE_ENVIRONMENTAL) -#define AE_TIME (ACPI_STATUS) (0x0011 | AE_CODE_ENVIRONMENTAL) -#define AE_ACQUIRE_DEADLOCK (ACPI_STATUS) (0x0012 | AE_CODE_ENVIRONMENTAL) -#define AE_RELEASE_DEADLOCK (ACPI_STATUS) (0x0013 | AE_CODE_ENVIRONMENTAL) -#define AE_NOT_ACQUIRED (ACPI_STATUS) (0x0014 | AE_CODE_ENVIRONMENTAL) -#define AE_ALREADY_ACQUIRED (ACPI_STATUS) (0x0015 | AE_CODE_ENVIRONMENTAL) -#define AE_NO_HARDWARE_RESPONSE (ACPI_STATUS) (0x0016 | AE_CODE_ENVIRONMENTAL) -#define AE_NO_GLOBAL_LOCK (ACPI_STATUS) (0x0017 | AE_CODE_ENVIRONMENTAL) -#define AE_ABORT_METHOD (ACPI_STATUS) (0x0018 | AE_CODE_ENVIRONMENTAL) -#define AE_SAME_HANDLER (ACPI_STATUS) (0x0019 | AE_CODE_ENVIRONMENTAL) -#define AE_NO_HANDLER (ACPI_STATUS) (0x001A | AE_CODE_ENVIRONMENTAL) -#define AE_OWNER_ID_LIMIT (ACPI_STATUS) (0x001B | AE_CODE_ENVIRONMENTAL) -#define AE_NOT_CONFIGURED (ACPI_STATUS) (0x001C | AE_CODE_ENVIRONMENTAL) +#define AE_ERROR EXCEP_ENV (0x0001) +#define AE_NO_ACPI_TABLES EXCEP_ENV (0x0002) +#define AE_NO_NAMESPACE EXCEP_ENV (0x0003) +#define AE_NO_MEMORY EXCEP_ENV (0x0004) +#define AE_NOT_FOUND EXCEP_ENV (0x0005) +#define AE_NOT_EXIST EXCEP_ENV (0x0006) +#define AE_ALREADY_EXISTS EXCEP_ENV (0x0007) +#define AE_TYPE EXCEP_ENV (0x0008) +#define AE_NULL_OBJECT EXCEP_ENV (0x0009) +#define AE_NULL_ENTRY EXCEP_ENV (0x000A) +#define AE_BUFFER_OVERFLOW EXCEP_ENV (0x000B) +#define AE_STACK_OVERFLOW EXCEP_ENV (0x000C) +#define AE_STACK_UNDERFLOW EXCEP_ENV (0x000D) +#define AE_NOT_IMPLEMENTED EXCEP_ENV (0x000E) +#define AE_SUPPORT EXCEP_ENV (0x000F) +#define AE_LIMIT EXCEP_ENV (0x0010) +#define AE_TIME EXCEP_ENV (0x0011) +#define AE_ACQUIRE_DEADLOCK EXCEP_ENV (0x0012) +#define AE_RELEASE_DEADLOCK EXCEP_ENV (0x0013) +#define AE_NOT_ACQUIRED EXCEP_ENV (0x0014) +#define AE_ALREADY_ACQUIRED EXCEP_ENV (0x0015) +#define AE_NO_HARDWARE_RESPONSE EXCEP_ENV (0x0016) +#define AE_NO_GLOBAL_LOCK EXCEP_ENV (0x0017) +#define AE_ABORT_METHOD EXCEP_ENV (0x0018) +#define AE_SAME_HANDLER EXCEP_ENV (0x0019) +#define AE_NO_HANDLER EXCEP_ENV (0x001A) +#define AE_OWNER_ID_LIMIT EXCEP_ENV (0x001B) +#define AE_NOT_CONFIGURED EXCEP_ENV (0x001C) #define AE_CODE_ENV_MAX 0x001C @@ -101,15 +134,15 @@ /* * Programmer exceptions */ -#define AE_BAD_PARAMETER (ACPI_STATUS) (0x0001 | AE_CODE_PROGRAMMER) -#define AE_BAD_CHARACTER (ACPI_STATUS) (0x0002 | AE_CODE_PROGRAMMER) -#define AE_BAD_PATHNAME (ACPI_STATUS) (0x0003 | AE_CODE_PROGRAMMER) -#define AE_BAD_DATA (ACPI_STATUS) (0x0004 | AE_CODE_PROGRAMMER) -#define AE_BAD_HEX_CONSTANT (ACPI_STATUS) (0x0005 | AE_CODE_PROGRAMMER) -#define AE_BAD_OCTAL_CONSTANT (ACPI_STATUS) (0x0006 | AE_CODE_PROGRAMMER) -#define AE_BAD_DECIMAL_CONSTANT (ACPI_STATUS) (0x0007 | AE_CODE_PROGRAMMER) -#define AE_MISSING_ARGUMENTS (ACPI_STATUS) (0x0008 | AE_CODE_PROGRAMMER) -#define AE_BAD_ADDRESS (ACPI_STATUS) (0x0009 | AE_CODE_PROGRAMMER) +#define AE_BAD_PARAMETER EXCEP_PGM (0x0001) +#define AE_BAD_CHARACTER EXCEP_PGM (0x0002) +#define AE_BAD_PATHNAME EXCEP_PGM (0x0003) +#define AE_BAD_DATA EXCEP_PGM (0x0004) +#define AE_BAD_HEX_CONSTANT EXCEP_PGM (0x0005) +#define AE_BAD_OCTAL_CONSTANT EXCEP_PGM (0x0006) +#define AE_BAD_DECIMAL_CONSTANT EXCEP_PGM (0x0007) +#define AE_MISSING_ARGUMENTS EXCEP_PGM (0x0008) +#define AE_BAD_ADDRESS EXCEP_PGM (0x0009) #define AE_CODE_PGM_MAX 0x0009 @@ -117,11 +150,11 @@ /* * Acpi table exceptions */ -#define AE_BAD_SIGNATURE (ACPI_STATUS) (0x0001 | AE_CODE_ACPI_TABLES) -#define AE_BAD_HEADER (ACPI_STATUS) (0x0002 | AE_CODE_ACPI_TABLES) -#define AE_BAD_CHECKSUM (ACPI_STATUS) (0x0003 | AE_CODE_ACPI_TABLES) -#define AE_BAD_VALUE (ACPI_STATUS) (0x0004 | AE_CODE_ACPI_TABLES) -#define AE_INVALID_TABLE_LENGTH (ACPI_STATUS) (0x0005 | AE_CODE_ACPI_TABLES) +#define AE_BAD_SIGNATURE EXCEP_TBL (0x0001) +#define AE_BAD_HEADER EXCEP_TBL (0x0002) +#define AE_BAD_CHECKSUM EXCEP_TBL (0x0003) +#define AE_BAD_VALUE EXCEP_TBL (0x0004) +#define AE_INVALID_TABLE_LENGTH EXCEP_TBL (0x0005) #define AE_CODE_TBL_MAX 0x0005 @@ -130,39 +163,39 @@ * AML exceptions. These are caused by problems with * the actual AML byte stream */ -#define AE_AML_BAD_OPCODE (ACPI_STATUS) (0x0001 | AE_CODE_AML) -#define AE_AML_NO_OPERAND (ACPI_STATUS) (0x0002 | AE_CODE_AML) -#define AE_AML_OPERAND_TYPE (ACPI_STATUS) (0x0003 | AE_CODE_AML) -#define AE_AML_OPERAND_VALUE (ACPI_STATUS) (0x0004 | AE_CODE_AML) -#define AE_AML_UNINITIALIZED_LOCAL (ACPI_STATUS) (0x0005 | AE_CODE_AML) -#define AE_AML_UNINITIALIZED_ARG (ACPI_STATUS) (0x0006 | AE_CODE_AML) -#define AE_AML_UNINITIALIZED_ELEMENT (ACPI_STATUS) (0x0007 | AE_CODE_AML) -#define AE_AML_NUMERIC_OVERFLOW (ACPI_STATUS) (0x0008 | AE_CODE_AML) -#define AE_AML_REGION_LIMIT (ACPI_STATUS) (0x0009 | AE_CODE_AML) -#define AE_AML_BUFFER_LIMIT (ACPI_STATUS) (0x000A | AE_CODE_AML) -#define AE_AML_PACKAGE_LIMIT (ACPI_STATUS) (0x000B | AE_CODE_AML) -#define AE_AML_DIVIDE_BY_ZERO (ACPI_STATUS) (0x000C | AE_CODE_AML) -#define AE_AML_BAD_NAME (ACPI_STATUS) (0x000D | AE_CODE_AML) -#define AE_AML_NAME_NOT_FOUND (ACPI_STATUS) (0x000E | AE_CODE_AML) -#define AE_AML_INTERNAL (ACPI_STATUS) (0x000F | AE_CODE_AML) -#define AE_AML_INVALID_SPACE_ID (ACPI_STATUS) (0x0010 | AE_CODE_AML) -#define AE_AML_STRING_LIMIT (ACPI_STATUS) (0x0011 | AE_CODE_AML) -#define AE_AML_NO_RETURN_VALUE (ACPI_STATUS) (0x0012 | AE_CODE_AML) -#define AE_AML_METHOD_LIMIT (ACPI_STATUS) (0x0013 | AE_CODE_AML) -#define AE_AML_NOT_OWNER (ACPI_STATUS) (0x0014 | AE_CODE_AML) -#define AE_AML_MUTEX_ORDER (ACPI_STATUS) (0x0015 | AE_CODE_AML) -#define AE_AML_MUTEX_NOT_ACQUIRED (ACPI_STATUS) (0x0016 | AE_CODE_AML) -#define AE_AML_INVALID_RESOURCE_TYPE (ACPI_STATUS) (0x0017 | AE_CODE_AML) -#define AE_AML_INVALID_INDEX (ACPI_STATUS) (0x0018 | AE_CODE_AML) -#define AE_AML_REGISTER_LIMIT (ACPI_STATUS) (0x0019 | AE_CODE_AML) -#define AE_AML_NO_WHILE (ACPI_STATUS) (0x001A | AE_CODE_AML) -#define AE_AML_ALIGNMENT (ACPI_STATUS) (0x001B | AE_CODE_AML) -#define AE_AML_NO_RESOURCE_END_TAG (ACPI_STATUS) (0x001C | AE_CODE_AML) -#define AE_AML_BAD_RESOURCE_VALUE (ACPI_STATUS) (0x001D | AE_CODE_AML) -#define AE_AML_CIRCULAR_REFERENCE (ACPI_STATUS) (0x001E | AE_CODE_AML) -#define AE_AML_BAD_RESOURCE_LENGTH (ACPI_STATUS) (0x001F | AE_CODE_AML) -#define AE_AML_ILLEGAL_ADDRESS (ACPI_STATUS) (0x0020 | AE_CODE_AML) -#define AE_AML_INFINITE_LOOP (ACPI_STATUS) (0x0021 | AE_CODE_AML) +#define AE_AML_BAD_OPCODE EXCEP_AML (0x0001) +#define AE_AML_NO_OPERAND EXCEP_AML (0x0002) +#define AE_AML_OPERAND_TYPE EXCEP_AML (0x0003) +#define AE_AML_OPERAND_VALUE EXCEP_AML (0x0004) +#define AE_AML_UNINITIALIZED_LOCAL EXCEP_AML (0x0005) +#define AE_AML_UNINITIALIZED_ARG EXCEP_AML (0x0006) +#define AE_AML_UNINITIALIZED_ELEMENT EXCEP_AML (0x0007) +#define AE_AML_NUMERIC_OVERFLOW EXCEP_AML (0x0008) +#define AE_AML_REGION_LIMIT EXCEP_AML (0x0009) +#define AE_AML_BUFFER_LIMIT EXCEP_AML (0x000A) +#define AE_AML_PACKAGE_LIMIT EXCEP_AML (0x000B) +#define AE_AML_DIVIDE_BY_ZERO EXCEP_AML (0x000C) +#define AE_AML_BAD_NAME EXCEP_AML (0x000D) +#define AE_AML_NAME_NOT_FOUND EXCEP_AML (0x000E) +#define AE_AML_INTERNAL EXCEP_AML (0x000F) +#define AE_AML_INVALID_SPACE_ID EXCEP_AML (0x0010) +#define AE_AML_STRING_LIMIT EXCEP_AML (0x0011) +#define AE_AML_NO_RETURN_VALUE EXCEP_AML (0x0012) +#define AE_AML_METHOD_LIMIT EXCEP_AML (0x0013) +#define AE_AML_NOT_OWNER EXCEP_AML (0x0014) +#define AE_AML_MUTEX_ORDER EXCEP_AML (0x0015) +#define AE_AML_MUTEX_NOT_ACQUIRED EXCEP_AML (0x0016) +#define AE_AML_INVALID_RESOURCE_TYPE EXCEP_AML (0x0017) +#define AE_AML_INVALID_INDEX EXCEP_AML (0x0018) +#define AE_AML_REGISTER_LIMIT EXCEP_AML (0x0019) +#define AE_AML_NO_WHILE EXCEP_AML (0x001A) +#define AE_AML_ALIGNMENT EXCEP_AML (0x001B) +#define AE_AML_NO_RESOURCE_END_TAG EXCEP_AML (0x001C) +#define AE_AML_BAD_RESOURCE_VALUE EXCEP_AML (0x001D) +#define AE_AML_CIRCULAR_REFERENCE EXCEP_AML (0x001E) +#define AE_AML_BAD_RESOURCE_LENGTH EXCEP_AML (0x001F) +#define AE_AML_ILLEGAL_ADDRESS EXCEP_AML (0x0020) +#define AE_AML_INFINITE_LOOP EXCEP_AML (0x0021) #define AE_CODE_AML_MAX 0x0021 @@ -170,19 +203,19 @@ /* * Internal exceptions used for control */ -#define AE_CTRL_RETURN_VALUE (ACPI_STATUS) (0x0001 | AE_CODE_CONTROL) -#define AE_CTRL_PENDING (ACPI_STATUS) (0x0002 | AE_CODE_CONTROL) -#define AE_CTRL_TERMINATE (ACPI_STATUS) (0x0003 | AE_CODE_CONTROL) -#define AE_CTRL_TRUE (ACPI_STATUS) (0x0004 | AE_CODE_CONTROL) -#define AE_CTRL_FALSE (ACPI_STATUS) (0x0005 | AE_CODE_CONTROL) -#define AE_CTRL_DEPTH (ACPI_STATUS) (0x0006 | AE_CODE_CONTROL) -#define AE_CTRL_END (ACPI_STATUS) (0x0007 | AE_CODE_CONTROL) -#define AE_CTRL_TRANSFER (ACPI_STATUS) (0x0008 | AE_CODE_CONTROL) -#define AE_CTRL_BREAK (ACPI_STATUS) (0x0009 | AE_CODE_CONTROL) -#define AE_CTRL_CONTINUE (ACPI_STATUS) (0x000A | AE_CODE_CONTROL) -#define AE_CTRL_SKIP (ACPI_STATUS) (0x000B | AE_CODE_CONTROL) -#define AE_CTRL_PARSE_CONTINUE (ACPI_STATUS) (0x000C | AE_CODE_CONTROL) -#define AE_CTRL_PARSE_PENDING (ACPI_STATUS) (0x000D | AE_CODE_CONTROL) +#define AE_CTRL_RETURN_VALUE EXCEP_CTL (0x0001) +#define AE_CTRL_PENDING EXCEP_CTL (0x0002) +#define AE_CTRL_TERMINATE EXCEP_CTL (0x0003) +#define AE_CTRL_TRUE EXCEP_CTL (0x0004) +#define AE_CTRL_FALSE EXCEP_CTL (0x0005) +#define AE_CTRL_DEPTH EXCEP_CTL (0x0006) +#define AE_CTRL_END EXCEP_CTL (0x0007) +#define AE_CTRL_TRANSFER EXCEP_CTL (0x0008) +#define AE_CTRL_BREAK EXCEP_CTL (0x0009) +#define AE_CTRL_CONTINUE EXCEP_CTL (0x000A) +#define AE_CTRL_SKIP EXCEP_CTL (0x000B) +#define AE_CTRL_PARSE_CONTINUE EXCEP_CTL (0x000C) +#define AE_CTRL_PARSE_PENDING EXCEP_CTL (0x000D) #define AE_CODE_CTRL_MAX 0x000D @@ -195,117 +228,117 @@ * String versions of the exception codes above * These strings must match the corresponding defines exactly */ -char const *AcpiGbl_ExceptionNames_Env[] = +static const ACPI_EXCEPTION_INFO AcpiGbl_ExceptionNames_Env[] = { - "AE_OK", - "AE_ERROR", - "AE_NO_ACPI_TABLES", - "AE_NO_NAMESPACE", - "AE_NO_MEMORY", - "AE_NOT_FOUND", - "AE_NOT_EXIST", - "AE_ALREADY_EXISTS", - "AE_TYPE", - "AE_NULL_OBJECT", - "AE_NULL_ENTRY", - "AE_BUFFER_OVERFLOW", - "AE_STACK_OVERFLOW", - "AE_STACK_UNDERFLOW", - "AE_NOT_IMPLEMENTED", - "AE_SUPPORT", - "AE_LIMIT", - "AE_TIME", - "AE_ACQUIRE_DEADLOCK", - "AE_RELEASE_DEADLOCK", - "AE_NOT_ACQUIRED", - "AE_ALREADY_ACQUIRED", - "AE_NO_HARDWARE_RESPONSE", - "AE_NO_GLOBAL_LOCK", - "AE_ABORT_METHOD", - "AE_SAME_HANDLER", - "AE_NO_HANDLER", - "AE_OWNER_ID_LIMIT", - "AE_NOT_CONFIGURED" + EXCEP_TXT ("AE_OK", "No error"), + EXCEP_TXT ("AE_ERROR", "Unspecified error"), + EXCEP_TXT ("AE_NO_ACPI_TABLES", "ACPI tables could not be found"), + EXCEP_TXT ("AE_NO_NAMESPACE", "A namespace has not been loaded"), + EXCEP_TXT ("AE_NO_MEMORY", "Insufficient dynamic memory"), + EXCEP_TXT ("AE_NOT_FOUND", "The name was not found in the namespace"), + EXCEP_TXT ("AE_NOT_EXIST", "A required entity does not exist"), + EXCEP_TXT ("AE_ALREADY_EXISTS", "An entity already exists"), + EXCEP_TXT ("AE_TYPE", "The object type is incorrect"), + EXCEP_TXT ("AE_NULL_OBJECT", "A required object was missing"), + EXCEP_TXT ("AE_NULL_ENTRY", "The requested object does not exist"), + EXCEP_TXT ("AE_BUFFER_OVERFLOW", "The buffer provided is too small"), + EXCEP_TXT ("AE_STACK_OVERFLOW", "An internal stack overflowed"), + EXCEP_TXT ("AE_STACK_UNDERFLOW", "An internal stack underflowed"), + EXCEP_TXT ("AE_NOT_IMPLEMENTED", "The feature is not implemented"), + EXCEP_TXT ("AE_SUPPORT", "The feature is not supported"), + EXCEP_TXT ("AE_LIMIT", "A predefined limit was exceeded"), + EXCEP_TXT ("AE_TIME", "A time limit or timeout expired"), + EXCEP_TXT ("AE_ACQUIRE_DEADLOCK", "Internal error, attempt was made to acquire a mutex in improper order"), + EXCEP_TXT ("AE_RELEASE_DEADLOCK", "Internal error, attempt was made to release a mutex in improper order"), + EXCEP_TXT ("AE_NOT_ACQUIRED", "An attempt to release a mutex or Global Lock without a previous acquire"), + EXCEP_TXT ("AE_ALREADY_ACQUIRED", "Internal error, attempt was made to acquire a mutex twice"), + EXCEP_TXT ("AE_NO_HARDWARE_RESPONSE", "Hardware did not respond after an I/O operation"), + EXCEP_TXT ("AE_NO_GLOBAL_LOCK", "There is no FACS Global Lock"), + EXCEP_TXT ("AE_ABORT_METHOD", "A control method was aborted"), + EXCEP_TXT ("AE_SAME_HANDLER", "Attempt was made to install the same handler that is already installed"), + EXCEP_TXT ("AE_NO_HANDLER", "A handler for the operation is not installed"), + EXCEP_TXT ("AE_OWNER_ID_LIMIT", "There are no more Owner IDs available for ACPI tables or control methods"), + EXCEP_TXT ("AE_NOT_CONFIGURED", "The interface is not part of the current subsystem configuration") }; -char const *AcpiGbl_ExceptionNames_Pgm[] = +static const ACPI_EXCEPTION_INFO AcpiGbl_ExceptionNames_Pgm[] = { - NULL, - "AE_BAD_PARAMETER", - "AE_BAD_CHARACTER", - "AE_BAD_PATHNAME", - "AE_BAD_DATA", - "AE_BAD_HEX_CONSTANT", - "AE_BAD_OCTAL_CONSTANT", - "AE_BAD_DECIMAL_CONSTANT", - "AE_MISSING_ARGUMENTS", - "AE_BAD_ADDRESS" + EXCEP_TXT (NULL, NULL), + EXCEP_TXT ("AE_BAD_PARAMETER", "A parameter is out of range or invalid"), + EXCEP_TXT ("AE_BAD_CHARACTER", "An invalid character was found in a name"), + EXCEP_TXT ("AE_BAD_PATHNAME", "An invalid character was found in a pathname"), + EXCEP_TXT ("AE_BAD_DATA", "A package or buffer contained incorrect data"), + EXCEP_TXT ("AE_BAD_HEX_CONSTANT", "Invalid character in a Hex constant"), + EXCEP_TXT ("AE_BAD_OCTAL_CONSTANT", "Invalid character in an Octal constant"), + EXCEP_TXT ("AE_BAD_DECIMAL_CONSTANT", "Invalid character in a Decimal constant"), + EXCEP_TXT ("AE_MISSING_ARGUMENTS", "Too few arguments were passed to a control method"), + EXCEP_TXT ("AE_BAD_ADDRESS", "An illegal null I/O address") }; -char const *AcpiGbl_ExceptionNames_Tbl[] = +static const ACPI_EXCEPTION_INFO AcpiGbl_ExceptionNames_Tbl[] = { - NULL, - "AE_BAD_SIGNATURE", - "AE_BAD_HEADER", - "AE_BAD_CHECKSUM", - "AE_BAD_VALUE", - "AE_INVALID_TABLE_LENGTH" + EXCEP_TXT (NULL, NULL), + EXCEP_TXT ("AE_BAD_SIGNATURE", "An ACPI table has an invalid signature"), + EXCEP_TXT ("AE_BAD_HEADER", "Invalid field in an ACPI table header"), + EXCEP_TXT ("AE_BAD_CHECKSUM", "An ACPI table checksum is not correct"), + EXCEP_TXT ("AE_BAD_VALUE", "An invalid value was found in a table"), + EXCEP_TXT ("AE_INVALID_TABLE_LENGTH", "The FADT or FACS has improper length") }; -char const *AcpiGbl_ExceptionNames_Aml[] = +static const ACPI_EXCEPTION_INFO AcpiGbl_ExceptionNames_Aml[] = { - NULL, - "AE_AML_BAD_OPCODE", - "AE_AML_NO_OPERAND", - "AE_AML_OPERAND_TYPE", - "AE_AML_OPERAND_VALUE", - "AE_AML_UNINITIALIZED_LOCAL", - "AE_AML_UNINITIALIZED_ARG", - "AE_AML_UNINITIALIZED_ELEMENT", - "AE_AML_NUMERIC_OVERFLOW", - "AE_AML_REGION_LIMIT", - "AE_AML_BUFFER_LIMIT", - "AE_AML_PACKAGE_LIMIT", - "AE_AML_DIVIDE_BY_ZERO", - "AE_AML_BAD_NAME", - "AE_AML_NAME_NOT_FOUND", - "AE_AML_INTERNAL", - "AE_AML_INVALID_SPACE_ID", - "AE_AML_STRING_LIMIT", - "AE_AML_NO_RETURN_VALUE", - "AE_AML_METHOD_LIMIT", - "AE_AML_NOT_OWNER", - "AE_AML_MUTEX_ORDER", - "AE_AML_MUTEX_NOT_ACQUIRED", - "AE_AML_INVALID_RESOURCE_TYPE", - "AE_AML_INVALID_INDEX", - "AE_AML_REGISTER_LIMIT", - "AE_AML_NO_WHILE", - "AE_AML_ALIGNMENT", - "AE_AML_NO_RESOURCE_END_TAG", - "AE_AML_BAD_RESOURCE_VALUE", - "AE_AML_CIRCULAR_REFERENCE", - "AE_AML_BAD_RESOURCE_LENGTH", - "AE_AML_ILLEGAL_ADDRESS", - "AE_AML_INFINITE_LOOP" + EXCEP_TXT (NULL, NULL), + EXCEP_TXT ("AE_AML_BAD_OPCODE", "Invalid AML opcode encountered"), + EXCEP_TXT ("AE_AML_NO_OPERAND", "A required operand is missing"), + EXCEP_TXT ("AE_AML_OPERAND_TYPE", "An operand of an incorrect type was encountered"), + EXCEP_TXT ("AE_AML_OPERAND_VALUE", "The operand had an inappropriate or invalid value"), + EXCEP_TXT ("AE_AML_UNINITIALIZED_LOCAL", "Method tried to use an uninitialized local variable"), + EXCEP_TXT ("AE_AML_UNINITIALIZED_ARG", "Method tried to use an uninitialized argument"), + EXCEP_TXT ("AE_AML_UNINITIALIZED_ELEMENT", "Method tried to use an empty package element"), + EXCEP_TXT ("AE_AML_NUMERIC_OVERFLOW", "Overflow during BCD conversion or other"), + EXCEP_TXT ("AE_AML_REGION_LIMIT", "Tried to access beyond the end of an Operation Region"), + EXCEP_TXT ("AE_AML_BUFFER_LIMIT", "Tried to access beyond the end of a buffer"), + EXCEP_TXT ("AE_AML_PACKAGE_LIMIT", "Tried to access beyond the end of a package"), + EXCEP_TXT ("AE_AML_DIVIDE_BY_ZERO", "During execution of AML Divide operator"), + EXCEP_TXT ("AE_AML_BAD_NAME", "An ACPI name contains invalid character(s)"), + EXCEP_TXT ("AE_AML_NAME_NOT_FOUND", "Could not resolve a named reference"), + EXCEP_TXT ("AE_AML_INTERNAL", "An internal error within the interprete"), + EXCEP_TXT ("AE_AML_INVALID_SPACE_ID", "An Operation Region SpaceID is invalid"), + EXCEP_TXT ("AE_AML_STRING_LIMIT", "String is longer than 200 characters"), + EXCEP_TXT ("AE_AML_NO_RETURN_VALUE", "A method did not return a required value"), + EXCEP_TXT ("AE_AML_METHOD_LIMIT", "A control method reached the maximum reentrancy limit of 255"), + EXCEP_TXT ("AE_AML_NOT_OWNER", "A thread tried to release a mutex that it does not own"), + EXCEP_TXT ("AE_AML_MUTEX_ORDER", "Mutex SyncLevel release mismatch"), + EXCEP_TXT ("AE_AML_MUTEX_NOT_ACQUIRED", "Attempt to release a mutex that was not previously acquired"), + EXCEP_TXT ("AE_AML_INVALID_RESOURCE_TYPE", "Invalid resource type in resource list"), + EXCEP_TXT ("AE_AML_INVALID_INDEX", "Invalid Argx or Localx (x too large)"), + EXCEP_TXT ("AE_AML_REGISTER_LIMIT", "Bank value or Index value beyond range of register"), + EXCEP_TXT ("AE_AML_NO_WHILE", "Break or Continue without a While"), + EXCEP_TXT ("AE_AML_ALIGNMENT", "Non-aligned memory transfer on platform that does not support this"), + EXCEP_TXT ("AE_AML_NO_RESOURCE_END_TAG", "No End Tag in a resource list"), + EXCEP_TXT ("AE_AML_BAD_RESOURCE_VALUE", "Invalid value of a resource element"), + EXCEP_TXT ("AE_AML_CIRCULAR_REFERENCE", "Two references refer to each other"), + EXCEP_TXT ("AE_AML_BAD_RESOURCE_LENGTH", "The length of a Resource Descriptor in the AML is incorrect"), + EXCEP_TXT ("AE_AML_ILLEGAL_ADDRESS", "A memory, I/O, or PCI configuration address is invalid"), + EXCEP_TXT ("AE_AML_INFINITE_LOOP", "An apparent infinite AML While loop, method was aborted") }; -char const *AcpiGbl_ExceptionNames_Ctrl[] = +static const ACPI_EXCEPTION_INFO AcpiGbl_ExceptionNames_Ctrl[] = { - NULL, - "AE_CTRL_RETURN_VALUE", - "AE_CTRL_PENDING", - "AE_CTRL_TERMINATE", - "AE_CTRL_TRUE", - "AE_CTRL_FALSE", - "AE_CTRL_DEPTH", - "AE_CTRL_END", - "AE_CTRL_TRANSFER", - "AE_CTRL_BREAK", - "AE_CTRL_CONTINUE", - "AE_CTRL_SKIP", - "AE_CTRL_PARSE_CONTINUE", - "AE_CTRL_PARSE_PENDING" + EXCEP_TXT (NULL, NULL), + EXCEP_TXT ("AE_CTRL_RETURN_VALUE", "A Method returned a value"), + EXCEP_TXT ("AE_CTRL_PENDING", "Method is calling another method"), + EXCEP_TXT ("AE_CTRL_TERMINATE", "Terminate the executing method"), + EXCEP_TXT ("AE_CTRL_TRUE", "An If or While predicate result"), + EXCEP_TXT ("AE_CTRL_FALSE", "An If or While predicate result"), + EXCEP_TXT ("AE_CTRL_DEPTH", "Maximum search depth has been reached"), + EXCEP_TXT ("AE_CTRL_END", "An If or While predicate is false"), + EXCEP_TXT ("AE_CTRL_TRANSFER", "Transfer control to called method"), + EXCEP_TXT ("AE_CTRL_BREAK", "A Break has been executed"), + EXCEP_TXT ("AE_CTRL_CONTINUE", "A Continue has been executed"), + EXCEP_TXT ("AE_CTRL_SKIP", "Not currently used"), + EXCEP_TXT ("AE_CTRL_PARSE_CONTINUE", "Used to skip over bad opcodes"), + EXCEP_TXT ("AE_CTRL_PARSE_PENDING", "Used to implement AML While loops") }; #endif /* EXCEPTION_TABLE */ diff --git a/sys/contrib/dev/acpica/include/acglobal.h b/sys/contrib/dev/acpica/include/acglobal.h index 83547e6..987fc61 100644 --- a/sys/contrib/dev/acpica/include/acglobal.h +++ b/sys/contrib/dev/acpica/include/acglobal.h @@ -420,10 +420,12 @@ ACPI_EXTERN UINT8 AcpiGbl_DbOutputFlags; #ifdef ACPI_DISASSEMBLER -ACPI_EXTERN BOOLEAN ACPI_INIT_GLOBAL (AcpiGbl_IgnoreNoopOperator, FALSE); +ACPI_EXTERN BOOLEAN ACPI_INIT_GLOBAL (AcpiGbl_IgnoreNoopOperator, FALSE); ACPI_EXTERN BOOLEAN AcpiGbl_DbOpt_disasm; ACPI_EXTERN BOOLEAN AcpiGbl_DbOpt_verbose; +ACPI_EXTERN BOOLEAN AcpiGbl_NumExternalMethods; +ACPI_EXTERN UINT32 AcpiGbl_ResolvedExternalMethods; ACPI_EXTERN ACPI_EXTERNAL_LIST *AcpiGbl_ExternalList; ACPI_EXTERN ACPI_EXTERNAL_FILE *AcpiGbl_ExternalFileList; #endif diff --git a/sys/contrib/dev/acpica/include/aclocal.h b/sys/contrib/dev/acpica/include/aclocal.h index 798c4cb..ab03935 100644 --- a/sys/contrib/dev/acpica/include/aclocal.h +++ b/sys/contrib/dev/acpica/include/aclocal.h @@ -417,6 +417,7 @@ typedef struct acpi_predefined_data union acpi_operand_object *ParentPackage; ACPI_NAMESPACE_NODE *Node; UINT32 Flags; + UINT32 ReturnBtype; UINT8 NodeFlags; } ACPI_PREDEFINED_DATA; @@ -427,6 +428,22 @@ typedef struct acpi_predefined_data #define ACPI_OBJECT_WRAPPED 2 +/* Return object auto-repair info */ + +typedef ACPI_STATUS (*ACPI_OBJECT_CONVERTER) ( + union acpi_operand_object *OriginalObject, + union acpi_operand_object **ConvertedObject); + +typedef struct acpi_simple_repair_info +{ + char Name[ACPI_NAME_SIZE]; + UINT32 UnexpectedBtypes; + UINT32 PackageIndex; + ACPI_OBJECT_CONVERTER ObjectConverter; + +} ACPI_SIMPLE_REPAIR_INFO; + + /* * Bitmapped return value types * Note: the actual data types must be contiguous, a loop in nspredef.c @@ -1217,6 +1234,7 @@ typedef struct acpi_external_list UINT16 Length; UINT8 Type; UINT8 Flags; + BOOLEAN Resolved; } ACPI_EXTERNAL_LIST; diff --git a/sys/contrib/dev/acpica/include/acnamesp.h b/sys/contrib/dev/acpica/include/acnamesp.h index 7a92143..4009c2d 100644 --- a/sys/contrib/dev/acpica/include/acnamesp.h +++ b/sys/contrib/dev/acpica/include/acnamesp.h @@ -204,6 +204,35 @@ AcpiNsCompareNames ( /* + * nsconvert - Dynamic object conversion routines + */ +ACPI_STATUS +AcpiNsConvertToInteger ( + ACPI_OPERAND_OBJECT *OriginalObject, + ACPI_OPERAND_OBJECT **ReturnObject); + +ACPI_STATUS +AcpiNsConvertToString ( + ACPI_OPERAND_OBJECT *OriginalObject, + ACPI_OPERAND_OBJECT **ReturnObject); + +ACPI_STATUS +AcpiNsConvertToBuffer ( + ACPI_OPERAND_OBJECT *OriginalObject, + ACPI_OPERAND_OBJECT **ReturnObject); + +ACPI_STATUS +AcpiNsConvertToUnicode ( + ACPI_OPERAND_OBJECT *OriginalObject, + ACPI_OPERAND_OBJECT **ReturnObject); + +ACPI_STATUS +AcpiNsConvertToResource ( + ACPI_OPERAND_OBJECT *OriginalObject, + ACPI_OPERAND_OBJECT **ReturnObject); + + +/* * nsdump - Namespace dump/print utilities */ void @@ -377,7 +406,7 @@ AcpiNsGetAttachedData ( * predefined methods/objects */ ACPI_STATUS -AcpiNsRepairObject ( +AcpiNsSimpleRepair ( ACPI_PREDEFINED_DATA *Data, UINT32 ExpectedBtypes, UINT32 PackageIndex, diff --git a/sys/contrib/dev/acpica/include/acoutput.h b/sys/contrib/dev/acpica/include/acoutput.h index 4b5ca9c..371ce7f 100644 --- a/sys/contrib/dev/acpica/include/acoutput.h +++ b/sys/contrib/dev/acpica/include/acoutput.h @@ -409,6 +409,11 @@ #define return_VALUE(Value) \ ACPI_TRACE_EXIT (AcpiUtValueExit, UINT64, Value) +#define return_UINT32(Value) \ + ACPI_TRACE_EXIT (AcpiUtValueExit, UINT32, Value) + +#define return_UINT8(Value) \ + ACPI_TRACE_EXIT (AcpiUtValueExit, UINT8, Value) /* Conditional execution */ @@ -457,8 +462,10 @@ #define return_VOID return #define return_ACPI_STATUS(s) return(s) -#define return_VALUE(s) return(s) #define return_PTR(s) return(s) +#define return_VALUE(s) return(s) +#define return_UINT8(s) return(s) +#define return_UINT32(s) return(s) #endif /* ACPI_DEBUG_OUTPUT */ diff --git a/sys/contrib/dev/acpica/include/acpixf.h b/sys/contrib/dev/acpica/include/acpixf.h index 1cd6cb9..26e43a0 100644 --- a/sys/contrib/dev/acpica/include/acpixf.h +++ b/sys/contrib/dev/acpica/include/acpixf.h @@ -47,7 +47,7 @@ /* Current ACPICA subsystem version in YYYYMMDD format */ -#define ACPI_CA_VERSION 0x20130117 +#define ACPI_CA_VERSION 0x20130214 #include <contrib/dev/acpica/include/acconfig.h> #include <contrib/dev/acpica/include/actypes.h> diff --git a/sys/contrib/dev/acpica/include/actbl2.h b/sys/contrib/dev/acpica/include/actbl2.h index 49b9578..327a810 100644 --- a/sys/contrib/dev/acpica/include/actbl2.h +++ b/sys/contrib/dev/acpica/include/actbl2.h @@ -74,11 +74,13 @@ #define ACPI_SIG_IVRS "IVRS" /* I/O Virtualization Reporting Structure */ #define ACPI_SIG_MCFG "MCFG" /* PCI Memory Mapped Configuration table */ #define ACPI_SIG_MCHI "MCHI" /* Management Controller Host Interface table */ +#define ACPI_SIG_MTMR "MTMR" /* MID Timer table */ #define ACPI_SIG_SLIC "SLIC" /* Software Licensing Description Table */ #define ACPI_SIG_SPCR "SPCR" /* Serial Port Console Redirection table */ #define ACPI_SIG_SPMI "SPMI" /* Server Platform Management Interface table */ #define ACPI_SIG_TCPA "TCPA" /* Trusted Computing Platform Alliance table */ #define ACPI_SIG_UEFI "UEFI" /* Uefi Boot Optimization Table */ +#define ACPI_SIG_VRTC "VRTC" /* Virtual Real Time Clock Table */ #define ACPI_SIG_WAET "WAET" /* Windows ACPI Emulated devices Table */ #define ACPI_SIG_WDAT "WDAT" /* Watchdog Action Table */ #define ACPI_SIG_WDDT "WDDT" /* Watchdog Timer Description Table */ @@ -983,6 +985,34 @@ typedef struct acpi_table_mchi /******************************************************************************* * + * MTMR - MID Timer Table + * Version 1 + * + * Conforms to "Simple Firmware Interface Specification", + * Draft 0.8.2, Oct 19, 2010 + * NOTE: The ACPI MTMR is equivalent to the SFI MTMR table. + * + ******************************************************************************/ + +typedef struct acpi_table_mtmr +{ + ACPI_TABLE_HEADER Header; /* Common ACPI table header */ + +} ACPI_TABLE_MTMR; + +/* MTMR entry */ + +typedef struct acpi_mtmr_entry +{ + ACPI_GENERIC_ADDRESS PhysicalAddress; + UINT32 Frequency; + UINT32 Irq; + +} ACPI_MTMR_ENTRY; + + +/******************************************************************************* + * * SLIC - Software Licensing Description Table * Version 1 * @@ -1182,6 +1212,33 @@ typedef struct acpi_table_uefi /******************************************************************************* * + * VRTC - Virtual Real Time Clock Table + * Version 1 + * + * Conforms to "Simple Firmware Interface Specification", + * Draft 0.8.2, Oct 19, 2010 + * NOTE: The ACPI VRTC is equivalent to The SFI MRTC table. + * + ******************************************************************************/ + +typedef struct acpi_table_vrtc +{ + ACPI_TABLE_HEADER Header; /* Common ACPI table header */ + +} ACPI_TABLE_VRTC; + +/* VRTC entry */ + +typedef struct acpi_vrtc_entry +{ + ACPI_GENERIC_ADDRESS PhysicalAddress; + UINT32 Irq; + +} ACPI_VRTC_ENTRY; + + +/******************************************************************************* + * * WAET - Windows ACPI Emulated devices Table * Version 1 * diff --git a/sys/contrib/dev/acpica/include/actbl3.h b/sys/contrib/dev/acpica/include/actbl3.h index 46c3c6d..acf2e13 100644 --- a/sys/contrib/dev/acpica/include/actbl3.h +++ b/sys/contrib/dev/acpica/include/actbl3.h @@ -195,7 +195,7 @@ typedef struct acpi_fpdt_header enum AcpiFpdtType { ACPI_FPDT_TYPE_BOOT = 0, - ACPI_FPDT_TYPE_S3PERF = 1, + ACPI_FPDT_TYPE_S3PERF = 1 }; @@ -257,7 +257,7 @@ typedef struct acpi_s3pt_header enum AcpiS3ptType { ACPI_S3PT_TYPE_RESUME = 0, - ACPI_S3PT_TYPE_SUSPEND = 1, + ACPI_S3PT_TYPE_SUSPEND = 1 }; typedef struct acpi_s3pt_resume @@ -599,28 +599,67 @@ typedef struct acpi_rasf_shared_memory UINT32 Signature; UINT16 Command; UINT16 Status; - UINT64 RequestedAddress; - UINT64 RequestedLength; - UINT64 ActualAddress; - UINT64 ActualLength; - UINT16 Flags; - UINT8 Speed; + UINT16 Version; + UINT8 Capabilities[16]; + UINT8 SetCapabilities[16]; + UINT16 NumParameterBlocks; + UINT32 SetCapabilitiesStatus; } ACPI_RASF_SHARED_MEMORY; +/* RASF Parameter Block Structure Header */ + +typedef struct acpi_rasf_parameter_block +{ + UINT16 Type; + UINT16 Version; + UINT16 Length; + +} ACPI_RASF_PARAMETER_BLOCK; + +/* RASF Parameter Block Structure for PATROL_SCRUB */ + +typedef struct acpi_rasf_patrol_scrub_parameter +{ + ACPI_RASF_PARAMETER_BLOCK Header; + UINT16 PatrolScrubCommand; + UINT64 RequestedAddressRange[2]; + UINT64 ActualAddressRange[2]; + UINT16 Flags; + UINT8 RequestedSpeed; + +} ACPI_RASF_PATROL_SCRUB_PARAMETER; + /* Masks for Flags and Speed fields above */ #define ACPI_RASF_SCRUBBER_RUNNING 1 #define ACPI_RASF_SPEED (7<<1) +#define ACPI_RASF_SPEED_SLOW (0<<1) +#define ACPI_RASF_SPEED_MEDIUM (4<<1) +#define ACPI_RASF_SPEED_FAST (7<<1) /* Channel Commands */ enum AcpiRasfCommands { - ACPI_RASF_GET_RAS_CAPABILITIES = 1, - ACPI_RASF_GET_PATROL_PARAMETERS = 2, - ACPI_RASF_START_PATROL_SCRUBBER = 3, - ACPI_RASF_STOP_PATROL_SCRUBBER = 4 + ACPI_RASF_EXECUTE_RASF_COMMAND = 1 +}; + +/* Platform RAS Capabilities */ + +enum AcpiRasfCapabiliities +{ + ACPI_HW_PATROL_SCRUB_SUPPORTED = 0, + ACPI_SW_PATROL_SCRUB_EXPOSED = 1 +}; + +/* Patrol Scrub Commands */ + +enum AcpiRasfPatrolScrubCommands +{ + ACPI_RASF_GET_PATROL_PARAMETERS = 1, + ACPI_RASF_START_PATROL_SCRUBBER = 2, + ACPI_RASF_STOP_PATROL_SCRUBBER = 3 }; /* Channel Command flags */ diff --git a/sys/contrib/dev/acpica/include/acutils.h b/sys/contrib/dev/acpica/include/acutils.h index e75e248..165a158 100644 --- a/sys/contrib/dev/acpica/include/acutils.h +++ b/sys/contrib/dev/acpica/include/acutils.h @@ -706,10 +706,11 @@ AcpiUtShortDivide ( UINT64 *OutQuotient, UINT32 *OutRemainder); + /* * utmisc */ -const char * +const ACPI_EXCEPTION_INFO * AcpiUtValidateException ( ACPI_STATUS Status); diff --git a/sys/crypto/aesni/aesni_wrap.c b/sys/crypto/aesni/aesni_wrap.c index 787c1a9..3340b1f 100644 --- a/sys/crypto/aesni/aesni_wrap.c +++ b/sys/crypto/aesni/aesni_wrap.c @@ -1,4 +1,5 @@ /*- + * Copyright (C) 2008 Damien Miller <djm@mindrot.org> * Copyright (c) 2010 Konstantin Belousov <kib@FreeBSD.org> * Copyright (c) 2010-2011 Pawel Jakub Dawidek <pawel@dawidek.net> * All rights reserved. diff --git a/sys/dev/ata/ata-all.c b/sys/dev/ata/ata-all.c index 440db71..bfd49c7 100644 --- a/sys/dev/ata/ata-all.c +++ b/sys/dev/ata/ata-all.c @@ -1532,6 +1532,7 @@ ata_cam_begin_transaction(device_t dev, union ccb *ccb) request->timeout = (ccb->ccb_h.timeout + 999) / 1000; callout_init_mtx(&request->callout, &ch->state_mtx, CALLOUT_RETURNUNLOCKED); request->ccb = ccb; + request->flags |= ATA_R_DATA_IN_CCB; ch->running = request; ch->state = ATA_ACTIVE; diff --git a/sys/dev/ata/ata-all.h b/sys/dev/ata/ata-all.h index 28c93f9..be166df 100644 --- a/sys/dev/ata/ata-all.h +++ b/sys/dev/ata/ata-all.h @@ -398,6 +398,7 @@ struct ata_request { #define ATA_R_THREAD 0x00000800 #define ATA_R_DIRECT 0x00001000 #define ATA_R_NEEDRESULT 0x00002000 +#define ATA_R_DATA_IN_CCB 0x00004000 #define ATA_R_ATAPI16 0x00010000 #define ATA_R_ATAPI_INTR 0x00020000 diff --git a/sys/dev/ata/ata-dma.c b/sys/dev/ata/ata-dma.c index 9aea845..5695bc8 100644 --- a/sys/dev/ata/ata-dma.c +++ b/sys/dev/ata/ata-dma.c @@ -305,7 +305,7 @@ ata_dmaload(struct ata_request *request, void *addr, int *entries) dspa.dmatab = request->dma->sg; #ifdef ATA_CAM - if (request->ccb) + if (request->flags & ATA_R_DATA_IN_CCB) error = bus_dmamap_load_ccb(request->dma->data_tag, request->dma->data_map, request->ccb, ch->dma.setprd, &dspa, BUS_DMA_NOWAIT); diff --git a/sys/dev/ath/ath_hal/ar5416/ar5416_attach.c b/sys/dev/ath/ath_hal/ar5416/ar5416_attach.c index d165540..c26ca4b 100644 --- a/sys/dev/ath/ath_hal/ar5416/ar5416_attach.c +++ b/sys/dev/ath/ath_hal/ar5416/ar5416_attach.c @@ -241,8 +241,37 @@ ar5416InitState(struct ath_hal_5416 *ahp5416, uint16_t devid, HAL_SOFTC sc, /* Enable all ANI functions to begin with */ AH5416(ah)->ah_ani_function = 0xffffffff; - /* Set overridable ANI methods */ - AH5212(ah)->ah_aniControl = ar5416AniControl; + /* Set overridable ANI methods */ + AH5212(ah)->ah_aniControl = ar5416AniControl; + + /* + * Default FIFO Trigger levels + * + * These define how filled the TX FIFO needs to be before + * the baseband begins to be given some data. + * + * To be paranoid, we ensure that the TX trigger level always + * has at least enough space for two TX DMA to occur. + * The TX DMA size is currently hard-coded to AR_TXCFG_DMASZ_128B. + * That means we need to leave at least 256 bytes available in + * the TX DMA FIFO. + */ +#define AR_FTRIG_512B 0x00000080 // 5 bits total + /* + * AR9285/AR9271 have half the size TX FIFO compared to + * other devices + */ + if (AR_SREV_KITE(ah) || AR_SREV_9271(ah)) { + AH5212(ah)->ah_txTrigLev = (AR_FTRIG_256B >> AR_FTRIG_S); + AH5212(ah)->ah_maxTxTrigLev = ((2048 / 64) - 1); + } else { + AH5212(ah)->ah_txTrigLev = (AR_FTRIG_512B >> AR_FTRIG_S); + AH5212(ah)->ah_maxTxTrigLev = ((4096 / 64) - 1); + } +#undef AR_FTRIG_512B + + /* And now leave some headspace - 256 bytes */ + AH5212(ah)->ah_maxTxTrigLev -= 4; } uint32_t diff --git a/sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c b/sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c index 29aed1f..631ca2f 100644 --- a/sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c +++ b/sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c @@ -307,6 +307,8 @@ ar5416SetInterrupts(struct ath_hal *ah, HAL_INT ints) mask |= AR_IMR_TXDESC; if (ahp->ah_txEolInterruptMask) mask |= AR_IMR_TXEOL; + if (ahp->ah_txUrnInterruptMask) + mask |= AR_IMR_TXURN; } if (ints & (HAL_INT_BMISC)) { mask |= AR_IMR_BCNMISC; diff --git a/sys/dev/ath/ath_hal/ar5416/ar5416_reset.c b/sys/dev/ath/ath_hal/ar5416/ar5416_reset.c index 51ac0a1..75df5e9 100644 --- a/sys/dev/ath/ath_hal/ar5416/ar5416_reset.c +++ b/sys/dev/ath/ath_hal/ar5416/ar5416_reset.c @@ -570,6 +570,10 @@ ar5416InitDMA(struct ath_hal *ah) /* * let mac dma writes be in 128 byte chunks */ + /* + * XXX If you change this, you must change the headroom + * assigned in ah_maxTxTrigLev - see ar5416InitState(). + */ OS_REG_WRITE(ah, AR_RXCFG, (OS_REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK) | AR_RXCFG_DMASZ_128B); diff --git a/sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c b/sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c index 36f968f..945c766 100644 --- a/sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c +++ b/sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c @@ -669,6 +669,26 @@ ar5416GetGlobalTxTimeout(struct ath_hal *ah) return MS(OS_REG_READ(ah, AR_GTXTO), AR_GTXTO_TIMEOUT_LIMIT); } +#define HT_RC_2_MCS(_rc) ((_rc) & 0x0f) +static const u_int8_t baDurationDelta[] = { + 24, // 0: BPSK + 12, // 1: QPSK 1/2 + 12, // 2: QPSK 3/4 + 4, // 3: 16-QAM 1/2 + 4, // 4: 16-QAM 3/4 + 4, // 5: 64-QAM 2/3 + 4, // 6: 64-QAM 3/4 + 4, // 7: 64-QAM 5/6 + 24, // 8: BPSK + 12, // 9: QPSK 1/2 + 12, // 10: QPSK 3/4 + 4, // 11: 16-QAM 1/2 + 4, // 12: 16-QAM 3/4 + 4, // 13: 64-QAM 2/3 + 4, // 14: 64-QAM 3/4 + 4, // 15: 64-QAM 5/6 +}; + void ar5416Set11nRateScenario(struct ath_hal *ah, struct ath_desc *ds, u_int durUpdateEn, u_int rtsctsRate, @@ -740,17 +760,44 @@ ar5416Set11nRateScenario(struct ath_hal *ah, struct ath_desc *ds, | SM(rtsctsRate, AR_RTSCTSRate); } +/* + * Note: this should be called before calling ar5416SetBurstDuration() + * (if it is indeed called) in order to ensure that the burst duration + * is correctly updated with the BA delta workaround. + */ void ar5416Set11nAggrFirst(struct ath_hal *ah, struct ath_desc *ds, u_int aggrLen, u_int numDelims) { struct ar5416_desc *ads = AR5416DESC(ds); + uint32_t flags; + uint32_t burstDur; + uint8_t rate; ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr); ads->ds_ctl6 &= ~(AR_AggrLen | AR_PadDelim); ads->ds_ctl6 |= SM(aggrLen, AR_AggrLen); ads->ds_ctl6 |= SM(numDelims, AR_PadDelim); + + if (! AR_SREV_MERLIN_10_OR_LATER(ah)) { + /* + * XXX It'd be nice if I were passed in the rate scenario + * at this point.. + */ + rate = MS(ads->ds_ctl3, AR_XmitRate0); + flags = ads->ds_ctl0 & (AR_CTSEnable | AR_RTSEnable); + /* + * WAR - MAC assumes normal ACK time instead of + * block ACK while computing packet duration. + * Add this delta to the burst duration in the descriptor. + */ + if (flags && (ads->ds_ctl1 & AR_IsAggr)) { + burstDur = baDurationDelta[HT_RC_2_MCS(rate)]; + ads->ds_ctl2 &= ~(AR_BurstDur); + ads->ds_ctl2 |= SM(burstDur, AR_BurstDur); + } + } } void @@ -792,14 +839,36 @@ ar5416Clr11nAggr(struct ath_hal *ah, struct ath_desc *ds) ads->ds_ctl6 &= ~AR_AggrLen; } +/* + * Program the burst duration, with the included BA delta if it's + * applicable. + */ void ar5416Set11nBurstDuration(struct ath_hal *ah, struct ath_desc *ds, u_int burstDuration) { struct ar5416_desc *ads = AR5416DESC(ds); + uint32_t burstDur = 0; + uint8_t rate; + + if (! AR_SREV_MERLIN_10_OR_LATER(ah)) { + /* + * XXX It'd be nice if I were passed in the rate scenario + * at this point.. + */ + rate = MS(ads->ds_ctl3, AR_XmitDataTries0); + /* + * WAR - MAC assumes normal ACK time instead of + * block ACK while computing packet duration. + * Add this delta to the burst duration in the descriptor. + */ + if (ads->ds_ctl1 & AR_IsAggr) { + burstDur = baDurationDelta[HT_RC_2_MCS(rate)]; + } + } ads->ds_ctl2 &= ~AR_BurstDur; - ads->ds_ctl2 |= SM(burstDuration, AR_BurstDur); + ads->ds_ctl2 |= SM(burstDur + burstDuration, AR_BurstDur); } /* diff --git a/sys/dev/ath/if_ath.c b/sys/dev/ath/if_ath.c index b6b4217..2ea3909 100644 --- a/sys/dev/ath/if_ath.c +++ b/sys/dev/ath/if_ath.c @@ -799,6 +799,8 @@ ath_attach(u_int16_t devid, struct ath_softc *sc) sc->sc_hwq_limit = ATH_AGGR_MIN_QDEPTH; sc->sc_tid_hwq_lo = ATH_AGGR_SCHED_LOW; sc->sc_tid_hwq_hi = ATH_AGGR_SCHED_HIGH; + sc->sc_aggr_limit = ATH_AGGR_MAXSIZE; + sc->sc_delim_min_pad = 0; /* * Check if the hardware requires PCI register serialisation. @@ -1588,6 +1590,10 @@ ath_intr(void *arg) ath_hal_getisr(ah, &status); /* NB: clears ISR too */ DPRINTF(sc, ATH_DEBUG_INTR, "%s: status 0x%x\n", __func__, status); ATH_KTR(sc, ATH_KTR_INTERRUPTS, 1, "ath_intr: mask=0x%.8x", status); +#ifdef ATH_DEBUG_ALQ + if_ath_alq_post_intr(&sc->sc_alq, status, ah->ah_intrstate, + ah->ah_syncstate); +#endif /* ATH_DEBUG_ALQ */ #ifdef ATH_KTR_INTR_DEBUG ATH_KTR(sc, ATH_KTR_INTERRUPTS, 5, "ath_intr: ISR=0x%.8x, ISR_S0=0x%.8x, ISR_S1=0x%.8x, ISR_S2=0x%.8x, ISR_S5=0x%.8x", @@ -1979,6 +1985,7 @@ ath_init(void *arg) */ sc->sc_imask = HAL_INT_RX | HAL_INT_TX | HAL_INT_RXEOL | HAL_INT_RXORN + | HAL_INT_TXURN | HAL_INT_FATAL | HAL_INT_GLOBAL; /* @@ -3581,17 +3588,24 @@ ath_tx_update_stats(struct ath_softc *sc, struct ath_tx_status *ts, if (ts->ts_status & HAL_TXERR_TIMER_EXPIRED) sc->sc_stats.ast_tx_timerexpired++; - if (ts->ts_status & HAL_TX_DATA_UNDERRUN) - sc->sc_stats.ast_tx_data_underrun++; - if (ts->ts_status & HAL_TX_DELIM_UNDERRUN) - sc->sc_stats.ast_tx_delim_underrun++; - if (bf->bf_m->m_flags & M_FF) sc->sc_stats.ast_ff_txerr++; } /* XXX when is this valid? */ - if (ts->ts_status & HAL_TX_DESC_CFG_ERR) + if (ts->ts_flags & HAL_TX_DESC_CFG_ERR) sc->sc_stats.ast_tx_desccfgerr++; + /* + * This can be valid for successful frame transmission! + * If there's a TX FIFO underrun during aggregate transmission, + * the MAC will pad the rest of the aggregate with delimiters. + * If a BA is returned, the frame is marked as "OK" and it's up + * to the TX completion code to notice which frames weren't + * successfully transmitted. + */ + if (ts->ts_flags & HAL_TX_DATA_UNDERRUN) + sc->sc_stats.ast_tx_data_underrun++; + if (ts->ts_flags & HAL_TX_DELIM_UNDERRUN) + sc->sc_stats.ast_tx_delim_underrun++; sr = ts->ts_shortretry; lr = ts->ts_longretry; @@ -3617,12 +3631,14 @@ ath_tx_default_comp(struct ath_softc *sc, struct ath_buf *bf, int fail) st = ((bf->bf_state.bfs_txflags & HAL_TXDESC_NOACK) == 0) ? ts->ts_status : HAL_TXERR_XRETRY; +#if 0 if (bf->bf_state.bfs_dobaw) device_printf(sc->sc_dev, "%s: bf %p: seqno %d: dobaw should've been cleared!\n", __func__, bf, SEQNO(bf->bf_state.bfs_seqno)); +#endif if (bf->bf_next != NULL) device_printf(sc->sc_dev, "%s: bf %p: seqno %d: bf_next not NULL!\n", diff --git a/sys/dev/ath/if_ath_alq.h b/sys/dev/ath/if_ath_alq.h index 3748d50..541f2d7 100644 --- a/sys/dev/ath/if_ath_alq.h +++ b/sys/dev/ath/if_ath_alq.h @@ -92,6 +92,13 @@ struct if_ath_alq_tdma_timer_set { uint32_t sc_tdmaswbaprep; }; +#define ATH_ALQ_INTR_STATUS 10 +struct if_ath_alq_interrupt { + uint32_t intr_status; + uint32_t intr_state[8]; + uint32_t intr_syncstate; +}; + /* * These will always be logged, regardless. */ @@ -144,6 +151,27 @@ extern int if_ath_alq_start(struct if_ath_alq *alq); extern int if_ath_alq_stop(struct if_ath_alq *alq); extern void if_ath_alq_post(struct if_ath_alq *alq, uint16_t op, uint16_t len, const char *buf); + +/* XXX maybe doesn't belong here? */ +static inline void +if_ath_alq_post_intr(struct if_ath_alq *alq, uint32_t status, + uint32_t *state, uint32_t sync_state) +{ + int i; + struct if_ath_alq_interrupt intr; + + if (! if_ath_alq_checkdebug(alq, ATH_ALQ_INTR_STATUS)) + return; + + intr.intr_status = htobe32(status); + for (i = 0; i < 8; i++) + intr.intr_state[i] = htobe32(state[i]); + intr.intr_syncstate = htobe32(sync_state); + + if_ath_alq_post(alq, ATH_ALQ_INTR_STATUS, sizeof(intr), + (const char *) &intr); +} + #endif /* _KERNEL */ #endif diff --git a/sys/dev/ath/if_ath_rx.c b/sys/dev/ath/if_ath_rx.c index c8d9536..139e894 100644 --- a/sys/dev/ath/if_ath_rx.c +++ b/sys/dev/ath/if_ath_rx.c @@ -954,17 +954,32 @@ rx_proc_next: * need to be handled, kick the PCU if there's * been an RXEOL condition. */ - ATH_PCU_LOCK(sc); - if (resched && sc->sc_kickpcu) { + if (resched && kickpcu) { + ATH_PCU_LOCK(sc); ATH_KTR(sc, ATH_KTR_ERROR, 0, "ath_rx_proc: kickpcu"); device_printf(sc->sc_dev, "%s: kickpcu; handled %d packets\n", __func__, npkts); - /* XXX rxslink? */ -#if 0 + /* + * Go through the process of fully tearing down + * the RX buffers and reinitialising them. + * + * There's a hardware bug that causes the RX FIFO + * to get confused under certain conditions and + * constantly write over the same frame, leading + * the RX driver code here to get heavily confused. + */ +#if 1 ath_startrecv(sc); #else /* + * Disabled for now - it'd be nice to be able to do + * this in order to limit the amount of CPU time spent + * reinitialising the RX side (and thus minimise RX + * drops) however there's a hardware issue that + * causes things to get too far out of whack. + */ + /* * XXX can we hold the PCU lock here? * Are there any net80211 buffer calls involved? */ @@ -977,8 +992,8 @@ rx_proc_next: ath_hal_intrset(ah, sc->sc_imask); sc->sc_kickpcu = 0; + ATH_PCU_UNLOCK(sc); } - ATH_PCU_UNLOCK(sc); /* XXX check this inside of IF_LOCK? */ if (resched && (ifp->if_drv_flags & IFF_DRV_OACTIVE) == 0) { diff --git a/sys/dev/ath/if_ath_sysctl.c b/sys/dev/ath/if_ath_sysctl.c index abb180b..bbd1fe8 100644 --- a/sys/dev/ath/if_ath_sysctl.c +++ b/sys/dev/ath/if_ath_sysctl.c @@ -704,7 +704,7 @@ ath_sysctlattach(struct ath_softc *sc) SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "hwq_limit", CTLFLAG_RW, &sc->sc_hwq_limit, 0, - ""); + "Hardware queue depth before software-queuing TX frames"); SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "tid_hwq_lo", CTLFLAG_RW, &sc->sc_tid_hwq_lo, 0, ""); @@ -712,6 +712,19 @@ ath_sysctlattach(struct ath_softc *sc) "tid_hwq_hi", CTLFLAG_RW, &sc->sc_tid_hwq_hi, 0, ""); + /* Aggregate length twiddles */ + SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, + "aggr_limit", CTLFLAG_RW, &sc->sc_aggr_limit, 0, + "Maximum A-MPDU size, or 0 for 'default'"); + SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, + "rts_aggr_limit", CTLFLAG_RW, &sc->sc_rts_aggr_limit, 0, + "Maximum A-MPDU size for RTS-protected frames, or '0' " + "for default"); + SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, + "delim_min_pad", CTLFLAG_RW, &sc->sc_delim_min_pad, 0, + "Enforce a minimum number of delimiters per A-MPDU " + " sub-frame"); + SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "txq_data_minfree", CTLFLAG_RW, &sc->sc_txq_data_minfree, 0, "Minimum free buffers before adding a data frame" diff --git a/sys/dev/ath/if_ath_tx.c b/sys/dev/ath/if_ath_tx.c index 64c4378..92b28c6 100644 --- a/sys/dev/ath/if_ath_tx.c +++ b/sys/dev/ath/if_ath_tx.c @@ -473,11 +473,6 @@ ath_tx_chaindesclist(struct ath_softc *sc, struct ath_desc *ds0, bf->bf_state.bfs_ndelim); } isFirstDesc = 0; -#ifdef ATH_DEBUG - if (sc->sc_debug & ATH_DEBUG_XMIT) - ath_printtxbuf(sc, bf, bf->bf_state.bfs_tx_queue, - 0, 0); -#endif bf->bf_lastds = (struct ath_desc *) ds; /* @@ -3154,7 +3149,7 @@ ath_tx_tid_filt_comp_aggr(struct ath_softc *sc, struct ath_tid *tid, * Don't allow a filtered frame to live forever. */ if (bf->bf_state.bfs_retries > SWMAX_RETRIES) { - sc->sc_stats.ast_tx_swretrymax++; + sc->sc_stats.ast_tx_swretrymax++; DPRINTF(sc, ATH_DEBUG_SW_TX_FILT, "%s: bf=%p, seqno=%d, exceeded retries\n", __func__, @@ -3378,6 +3373,7 @@ ath_tx_tid_drain_pkt(struct ath_softc *sc, struct ath_node *an, ath_tx_update_baw(sc, an, tid, bf); bf->bf_state.bfs_dobaw = 0; } +#if 0 /* * This has become a non-fatal error now */ @@ -3385,6 +3381,7 @@ ath_tx_tid_drain_pkt(struct ath_softc *sc, struct ath_node *an, device_printf(sc->sc_dev, "%s: wasn't added: seqno %d\n", __func__, SEQNO(bf->bf_state.bfs_seqno)); +#endif } TAILQ_INSERT_TAIL(bf_cq, bf, bf_list); } diff --git a/sys/dev/ath/if_ath_tx.h b/sys/dev/ath/if_ath_tx.h index 1397faa..1437d7f 100644 --- a/sys/dev/ath/if_ath_tx.h +++ b/sys/dev/ath/if_ath_tx.h @@ -79,6 +79,11 @@ #define BAW_WITHIN(_start, _bawsz, _seqno) \ ((((_seqno) - (_start)) & 4095) < (_bawsz)) +/* + * Maximum aggregate size + */ +#define ATH_AGGR_MAXSIZE 65530 + extern void ath_freetx(struct mbuf *m); extern void ath_tx_node_flush(struct ath_softc *sc, struct ath_node *an); extern void ath_tx_txq_drain(struct ath_softc *sc, struct ath_txq *txq); diff --git a/sys/dev/ath/if_ath_tx_ht.c b/sys/dev/ath/if_ath_tx_ht.c index 60a1863..7245d06 100644 --- a/sys/dev/ath/if_ath_tx_ht.c +++ b/sys/dev/ath/if_ath_tx_ht.c @@ -346,17 +346,31 @@ ath_compute_num_delims(struct ath_softc *sc, struct ath_buf *first_bf, * crypto hardware catch up. This could be tuned per-MAC and * per-rate, but for now we'll simply assume encryption is * always enabled. + * + * Also note that the Atheros reference driver inserts two + * delimiters by default for pre-AR9380 peers. This will + * include "that" required delimiter. */ ndelim += ATH_AGGR_ENCRYPTDELIM; /* * For AR9380, there's a minimum number of delimeters * required when doing RTS. + * + * XXX TODO: this is only needed if (a) RTS/CTS is enabled, and + * XXX (b) this is the first sub-frame in the aggregate. */ if (sc->sc_use_ent && (sc->sc_ent_cfg & AH_ENT_RTSCTS_DELIM_WAR) && ndelim < AH_FIRST_DESC_NDELIMS) ndelim = AH_FIRST_DESC_NDELIMS; + /* + * If sc_delim_min_pad is non-zero, enforce it as the minimum + * pad delimiter count. + */ + if (sc->sc_delim_min_pad != 0) + ndelim = MAX(ndelim, sc->sc_delim_min_pad); + DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, "%s: pktlen=%d, ndelim=%d, mpdudensity=%d\n", __func__, pktlen, ndelim, mpdudensity); @@ -420,9 +434,12 @@ ath_compute_num_delims(struct ath_softc *sc, struct ath_buf *first_bf, static int ath_get_aggr_limit(struct ath_softc *sc, struct ath_buf *bf) { - int amin = 65530; + int amin = ATH_AGGR_MAXSIZE; int i; + if (sc->sc_aggr_limit > 0 && sc->sc_aggr_limit < ATH_AGGR_MAXSIZE) + amin = sc->sc_aggr_limit; + for (i = 0; i < ATH_RC_NUM; i++) { if (bf->bf_state.bfs_rc[i].tries == 0) continue; @@ -488,6 +505,13 @@ ath_rateseries_setup(struct ath_softc *sc, struct ieee80211_node *ni, * XXX It's overridden in the HAL rate scenario function * XXX for now. */ + /* + * XXX TODO: When the NIC is capable of three stream TX, + * transmit 1/2 stream rates on two streams. + * + * This reduces the power consumption of the NIC and + * keeps it within the PCIe slot power limits. + */ series[i].ChSel = sc->sc_txchainmask; if (flags & (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA)) diff --git a/sys/dev/ath/if_athvar.h b/sys/dev/ath/if_athvar.h index 36923cc..1b6e160 100644 --- a/sys/dev/ath/if_athvar.h +++ b/sys/dev/ath/if_athvar.h @@ -718,6 +718,8 @@ struct ath_softc { int sc_txchainmask; /* currently configured TX chainmask */ int sc_rxchainmask; /* currently configured RX chainmask */ int sc_rts_aggr_limit; /* TX limit on RTS aggregates */ + int sc_aggr_limit; /* TX limit on all aggregates */ + int sc_delim_min_pad; /* Minimum delimiter count */ /* Queue limits */ diff --git a/sys/dev/coretemp/coretemp.c b/sys/dev/coretemp/coretemp.c index 55efca2..a7d5fdc 100644 --- a/sys/dev/coretemp/coretemp.c +++ b/sys/dev/coretemp/coretemp.c @@ -274,23 +274,23 @@ coretemp_attach(device_t dev) * Add the MIBs to dev.cpu.N and dev.cpu.N.coretemp. */ SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(device_get_sysctl_tree(pdev)), - OID_AUTO, "temperature", CTLTYPE_INT | CTLFLAG_RD, dev, - CORETEMP_TEMP, coretemp_get_val_sysctl, "IK", + OID_AUTO, "temperature", CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, + dev, CORETEMP_TEMP, coretemp_get_val_sysctl, "IK", "Current temperature"); SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(oid), OID_AUTO, "delta", - CTLTYPE_INT | CTLFLAG_RD, dev, CORETEMP_DELTA, + CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, dev, CORETEMP_DELTA, coretemp_get_val_sysctl, "I", "Delta between TCC activation and current temperature"); SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(oid), OID_AUTO, "resolution", - CTLTYPE_INT | CTLFLAG_RD, dev, CORETEMP_RESOLUTION, + CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, dev, CORETEMP_RESOLUTION, coretemp_get_val_sysctl, "I", "Resolution of CPU thermal sensor"); SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(oid), OID_AUTO, "tjmax", - CTLTYPE_INT | CTLFLAG_RD, dev, CORETEMP_TJMAX, + CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, dev, CORETEMP_TJMAX, coretemp_get_val_sysctl, "IK", "TCC activation temperature"); SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(oid), OID_AUTO, - "throttle_log", CTLTYPE_INT | CTLFLAG_RW, dev, 0, + "throttle_log", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, dev, 0, coretemp_throttle_log_sysctl, "I", "Set to 1 if the thermal sensor has tripped"); diff --git a/sys/dev/cxgbe/common/t4_hw.h b/sys/dev/cxgbe/common/t4_hw.h index 256a7d5..acc383a 100644 --- a/sys/dev/cxgbe/common/t4_hw.h +++ b/sys/dev/cxgbe/common/t4_hw.h @@ -58,6 +58,7 @@ enum { CIM_PIFLA_SIZE = 64, /* # of 192-bit words in CIM PIF LA */ CIM_MALA_SIZE = 64, /* # of 160-bit words in CIM MA LA */ CIM_IBQ_SIZE = 128, /* # of 128-bit words in a CIM IBQ */ + CIM_OBQ_SIZE = 128, /* # of 128-bit words in a CIM OBQ */ TPLA_SIZE = 128, /* # of 64-bit words in TP LA */ ULPRX_LA_SIZE = 512, /* # of 256-bit words in ULP_RX LA */ }; diff --git a/sys/dev/cxgbe/t4_main.c b/sys/dev/cxgbe/t4_main.c index 96246a6..0e24c7c 100644 --- a/sys/dev/cxgbe/t4_main.c +++ b/sys/dev/cxgbe/t4_main.c @@ -317,6 +317,9 @@ static int sysctl_qsize_txq(SYSCTL_HANDLER_ARGS); static int sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS); #ifdef SBUF_DRAIN static int sysctl_cctrl(SYSCTL_HANDLER_ARGS); +static int sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS); +static int sysctl_cim_la(SYSCTL_HANDLER_ARGS); +static int sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS); static int sysctl_cpl_stats(SYSCTL_HANDLER_ARGS); static int sysctl_ddp_stats(SYSCTL_HANDLER_ARGS); static int sysctl_devlog(SYSCTL_HANDLER_ARGS); @@ -3171,6 +3174,62 @@ t4_sysctls(struct adapter *sc) CTLTYPE_STRING | CTLFLAG_RD, sc, 0, sysctl_cctrl, "A", "congestion control"); + SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp0", + CTLTYPE_STRING | CTLFLAG_RD, sc, 0, + sysctl_cim_ibq_obq, "A", "CIM IBQ 0 (TP0)"); + + SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp1", + CTLTYPE_STRING | CTLFLAG_RD, sc, 1, + sysctl_cim_ibq_obq, "A", "CIM IBQ 1 (TP1)"); + + SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ulp", + CTLTYPE_STRING | CTLFLAG_RD, sc, 2, + sysctl_cim_ibq_obq, "A", "CIM IBQ 2 (ULP)"); + + SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge0", + CTLTYPE_STRING | CTLFLAG_RD, sc, 3, + sysctl_cim_ibq_obq, "A", "CIM IBQ 3 (SGE0)"); + + SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge1", + CTLTYPE_STRING | CTLFLAG_RD, sc, 4, + sysctl_cim_ibq_obq, "A", "CIM IBQ 4 (SGE1)"); + + SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ncsi", + CTLTYPE_STRING | CTLFLAG_RD, sc, 5, + sysctl_cim_ibq_obq, "A", "CIM IBQ 5 (NCSI)"); + + SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_la", + CTLTYPE_STRING | CTLFLAG_RD, sc, 0, + sysctl_cim_la, "A", "CIM logic analyzer"); + + SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp0", + CTLTYPE_STRING | CTLFLAG_RD, sc, 0 + CIM_NUM_IBQ, + sysctl_cim_ibq_obq, "A", "CIM OBQ 0 (ULP0)"); + + SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp1", + CTLTYPE_STRING | CTLFLAG_RD, sc, 1 + CIM_NUM_IBQ, + sysctl_cim_ibq_obq, "A", "CIM OBQ 1 (ULP1)"); + + SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp2", + CTLTYPE_STRING | CTLFLAG_RD, sc, 2 + CIM_NUM_IBQ, + sysctl_cim_ibq_obq, "A", "CIM OBQ 2 (ULP2)"); + + SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp3", + CTLTYPE_STRING | CTLFLAG_RD, sc, 3 + CIM_NUM_IBQ, + sysctl_cim_ibq_obq, "A", "CIM OBQ 3 (ULP3)"); + + SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge", + CTLTYPE_STRING | CTLFLAG_RD, sc, 4 + CIM_NUM_IBQ, + sysctl_cim_ibq_obq, "A", "CIM OBQ 4 (SGE)"); + + SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ncsi", + CTLTYPE_STRING | CTLFLAG_RD, sc, 5 + CIM_NUM_IBQ, + sysctl_cim_ibq_obq, "A", "CIM OBQ 5 (NCSI)"); + + SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_qcfg", + CTLTYPE_STRING | CTLFLAG_RD, sc, 0, + sysctl_cim_qcfg, "A", "CIM queue configuration"); + SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cpl_stats", CTLTYPE_STRING | CTLFLAG_RD, sc, 0, sysctl_cpl_stats, "A", "CPL statistics"); @@ -3694,6 +3753,176 @@ sysctl_cctrl(SYSCTL_HANDLER_ARGS) return (rc); } +static const char *qname[CIM_NUM_IBQ + CIM_NUM_OBQ] = { + "TP0", "TP1", "ULP", "SGE0", "SGE1", "NC-SI", /* ibq's */ + "ULP0", "ULP1", "ULP2", "ULP3", "SGE", "NC-SI" /* obq's */ +}; + +static int +sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS) +{ + struct adapter *sc = arg1; + struct sbuf *sb; + int rc, i, n, qid = arg2; + uint32_t *buf, *p; + char *qtype; + + KASSERT(qid >= 0 && qid < nitems(qname), + ("%s: bad qid %d\n", __func__, qid)); + + if (qid < CIM_NUM_IBQ) { + /* inbound queue */ + qtype = "IBQ"; + n = 4 * CIM_IBQ_SIZE; + buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK); + rc = t4_read_cim_ibq(sc, qid, buf, n); + } else { + /* outbound queue */ + qtype = "OBQ"; + qid -= CIM_NUM_IBQ; + n = 4 * 6 * CIM_OBQ_SIZE; + buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK); + rc = t4_read_cim_obq(sc, qid, buf, n); + } + + if (rc < 0) { + rc = -rc; + goto done; + } + n = rc * sizeof(uint32_t); /* rc has # of words actually read */ + + rc = sysctl_wire_old_buffer(req, 0); + if (rc != 0) + goto done; + + sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); + if (sb == NULL) { + rc = ENOMEM; + goto done; + } + + sbuf_printf(sb, "%s%d %s", qtype , qid, qname[arg2]); + for (i = 0, p = buf; i < n; i += 16, p += 4) + sbuf_printf(sb, "\n%#06x: %08x %08x %08x %08x", i, p[0], p[1], + p[2], p[3]); + + rc = sbuf_finish(sb); + sbuf_delete(sb); +done: + free(buf, M_CXGBE); + return (rc); +} + +static int +sysctl_cim_la(SYSCTL_HANDLER_ARGS) +{ + struct adapter *sc = arg1; + u_int cfg; + struct sbuf *sb; + uint32_t *buf, *p; + int rc; + + rc = -t4_cim_read(sc, A_UP_UP_DBG_LA_CFG, 1, &cfg); + if (rc != 0) + return (rc); + + rc = sysctl_wire_old_buffer(req, 0); + if (rc != 0) + return (rc); + + sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); + if (sb == NULL) + return (ENOMEM); + + buf = malloc(sc->params.cim_la_size * sizeof(uint32_t), M_CXGBE, + M_ZERO | M_WAITOK); + + rc = -t4_cim_read_la(sc, buf, NULL); + if (rc != 0) + goto done; + + sbuf_printf(sb, "Status Data PC%s", + cfg & F_UPDBGLACAPTPCONLY ? "" : + " LS0Stat LS0Addr LS0Data"); + + KASSERT((sc->params.cim_la_size & 7) == 0, + ("%s: p will walk off the end of buf", __func__)); + + for (p = buf; p < &buf[sc->params.cim_la_size]; p += 8) { + if (cfg & F_UPDBGLACAPTPCONLY) { + sbuf_printf(sb, "\n %02x %08x %08x", p[5] & 0xff, + p[6], p[7]); + sbuf_printf(sb, "\n %02x %02x%06x %02x%06x", + (p[3] >> 8) & 0xff, p[3] & 0xff, p[4] >> 8, + p[4] & 0xff, p[5] >> 8); + sbuf_printf(sb, "\n %02x %x%07x %x%07x", + (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4, + p[1] & 0xf, p[2] >> 4); + } else { + sbuf_printf(sb, + "\n %02x %x%07x %x%07x %08x %08x " + "%08x%08x%08x%08x", + (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4, + p[1] & 0xf, p[2] >> 4, p[2] & 0xf, p[3], p[4], p[5], + p[6], p[7]); + } + } + + rc = sbuf_finish(sb); + sbuf_delete(sb); +done: + free(buf, M_CXGBE); + return (rc); +} + +static int +sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS) +{ + struct adapter *sc = arg1; + struct sbuf *sb; + int rc, i; + uint16_t base[CIM_NUM_IBQ + CIM_NUM_OBQ]; + uint16_t size[CIM_NUM_IBQ + CIM_NUM_OBQ]; + uint16_t thres[CIM_NUM_IBQ]; + uint32_t obq_wr[2 * CIM_NUM_OBQ], *wr = obq_wr; + uint32_t stat[4 * (CIM_NUM_IBQ + CIM_NUM_OBQ)], *p = stat; + + rc = -t4_cim_read(sc, A_UP_IBQ_0_RDADDR, nitems(stat), stat); + if (rc == 0) + rc = -t4_cim_read(sc, A_UP_OBQ_0_REALADDR, nitems(obq_wr), + obq_wr); + if (rc != 0) + return (rc); + + t4_read_cimq_cfg(sc, base, size, thres); + + rc = sysctl_wire_old_buffer(req, 0); + if (rc != 0) + return (rc); + + sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); + if (sb == NULL) + return (ENOMEM); + + sbuf_printf(sb, "Queue Base Size Thres RdPtr WrPtr SOP EOP Avail"); + + for (i = 0; i < CIM_NUM_IBQ; i++, p += 4) + sbuf_printf(sb, "\n%5s %5x %5u %4u %6x %4x %4u %4u %5u", + qname[i], base[i], size[i], thres[i], G_IBQRDADDR(p[0]), + G_IBQWRADDR(p[1]), G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]), + G_QUEREMFLITS(p[2]) * 16); + for ( ; i < CIM_NUM_IBQ + CIM_NUM_OBQ; i++, p += 4, wr += 2) + sbuf_printf(sb, "\n%5s %5x %5u %11x %4x %4u %4u %5u", qname[i], + base[i], size[i], G_QUERDADDR(p[0]) & 0x3fff, + wr[0] - base[i], G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]), + G_QUEREMFLITS(p[2]) * 16); + + rc = sbuf_finish(sb); + sbuf_delete(sb); + + return (rc); +} + static int sysctl_cpl_stats(SYSCTL_HANDLER_ARGS) { diff --git a/sys/dev/cxgbe/t4_sge.c b/sys/dev/cxgbe/t4_sge.c index 62ceec4..94dca53 100644 --- a/sys/dev/cxgbe/t4_sge.c +++ b/sys/dev/cxgbe/t4_sge.c @@ -2950,13 +2950,13 @@ write_txpkt_wr(struct port_info *pi, struct sge_txq *txq, struct mbuf *m, /* Checksum offload */ ctrl1 = 0; - if (!(m->m_pkthdr.csum_flags & CSUM_IP)) + if (!(m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TSO))) ctrl1 |= F_TXPKT_IPCSUM_DIS; if (!(m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP | CSUM_UDP_IPV6 | - CSUM_TCP_IPV6))) + CSUM_TCP_IPV6 | CSUM_TSO))) ctrl1 |= F_TXPKT_L4CSUM_DIS; if (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | - CSUM_UDP_IPV6 | CSUM_TCP_IPV6)) + CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO)) txq->txcsum++; /* some hardware assistance provided */ /* VLAN tag insertion */ @@ -3152,11 +3152,13 @@ write_ulp_cpl_sgl(struct port_info *pi, struct sge_txq *txq, /* Checksum offload */ ctrl = 0; - if (!(m->m_pkthdr.csum_flags & CSUM_IP)) + if (!(m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TSO))) ctrl |= F_TXPKT_IPCSUM_DIS; - if (!(m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))) + if (!(m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP | CSUM_UDP_IPV6 | + CSUM_TCP_IPV6 | CSUM_TSO))) ctrl |= F_TXPKT_L4CSUM_DIS; - if (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP)) + if (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | + CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO)) txq->txcsum++; /* some hardware assistance provided */ /* VLAN tag insertion */ diff --git a/sys/dev/dcons/dcons_os.c b/sys/dev/dcons/dcons_os.c index a37d64c..bf0be0b 100644 --- a/sys/dev/dcons/dcons_os.c +++ b/sys/dev/dcons/dcons_os.c @@ -74,6 +74,10 @@ #define DCONS_POLL_HZ 25 #endif +#ifndef DCONS_POLL_IDLE +#define DCONS_POLL_IDLE 256 +#endif + #ifndef DCONS_BUF_SIZE #define DCONS_BUF_SIZE (16*1024) #endif @@ -90,6 +94,7 @@ static char bssbuf[DCONS_BUF_SIZE]; /* buf in bss */ static struct dcons_global dg; struct dcons_global *dcons_conf; static int poll_hz = DCONS_POLL_HZ; +static u_int poll_idle = DCONS_POLL_HZ * DCONS_POLL_IDLE; static struct dcons_softc sc[DCONS_NPORT]; @@ -214,14 +219,17 @@ dcons_timeout(void *v) tp = dc->tty; tty_lock(tp); - while ((c = dcons_os_checkc_nopoll(dc)) != -1) + while ((c = dcons_os_checkc_nopoll(dc)) != -1) { ttydisc_rint(tp, c, 0); + poll_idle = 0; + } ttydisc_rint_done(tp); tty_unlock(tp); } - polltime = hz / poll_hz; - if (polltime < 1) - polltime = 1; + poll_idle++; + polltime = hz; + if (poll_idle <= (poll_hz * DCONS_POLL_IDLE)) + polltime /= poll_hz; callout_reset(&dcons_callout, polltime, dcons_timeout, tp); } @@ -368,8 +376,6 @@ dcons_attach(void) dcons_attach_port(DCONS_GDB, "dgdb", DC_GDB); callout_init(&dcons_callout, CALLOUT_MPSAFE); polltime = hz / poll_hz; - if (polltime < 1) - polltime = 1; callout_reset(&dcons_callout, polltime, dcons_timeout, NULL); return(0); } diff --git a/sys/dev/e1000/e1000_82571.c b/sys/dev/e1000/e1000_82571.c index 30015c1..ca7a1d0 100644 --- a/sys/dev/e1000/e1000_82571.c +++ b/sys/dev/e1000/e1000_82571.c @@ -1,6 +1,6 @@ /****************************************************************************** - Copyright (c) 2001-2011, Intel Corporation + Copyright (c) 2001-2013, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without @@ -32,8 +32,7 @@ ******************************************************************************/ /*$FreeBSD$*/ -/* - * 82571EB Gigabit Ethernet Controller +/* 82571EB Gigabit Ethernet Controller * 82571EB Gigabit Ethernet Controller (Copper) * 82571EB Gigabit Ethernet Controller (Fiber) * 82571EB Dual Port Gigabit Mezzanine Adapter @@ -51,9 +50,6 @@ #include "e1000_api.h" -static s32 e1000_init_phy_params_82571(struct e1000_hw *hw); -static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw); -static s32 e1000_init_mac_params_82571(struct e1000_hw *hw); static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw); static void e1000_release_nvm_82571(struct e1000_hw *hw); static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, @@ -78,7 +74,6 @@ static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw); static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw); static s32 e1000_get_phy_id_82571(struct e1000_hw *hw); static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw); -static s32 e1000_get_hw_semaphore_82573(struct e1000_hw *hw); static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw); static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw); static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw); @@ -99,13 +94,13 @@ static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw); static s32 e1000_init_phy_params_82571(struct e1000_hw *hw) { struct e1000_phy_info *phy = &hw->phy; - s32 ret_val = E1000_SUCCESS; + s32 ret_val; DEBUGFUNC("e1000_init_phy_params_82571"); if (hw->phy.media_type != e1000_media_type_copper) { phy->type = e1000_phy_none; - goto out; + return E1000_SUCCESS; } phy->addr = 1; @@ -165,8 +160,7 @@ static s32 e1000_init_phy_params_82571(struct e1000_hw *hw) phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82574; break; default: - ret_val = -E1000_ERR_PHY; - goto out; + return -E1000_ERR_PHY; break; } @@ -174,7 +168,7 @@ static s32 e1000_init_phy_params_82571(struct e1000_hw *hw) ret_val = e1000_get_phy_id_82571(hw); if (ret_val) { DEBUGOUT("Error getting PHY ID\n"); - goto out; + return ret_val; } /* Verify phy id */ @@ -201,7 +195,6 @@ static s32 e1000_init_phy_params_82571(struct e1000_hw *hw) if (ret_val) DEBUGOUT1("PHY ID unknown: type = 0x%08x\n", phy->id); -out: return ret_val; } @@ -241,8 +234,7 @@ static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw) if (((eecd >> 15) & 0x3) == 0x3) { nvm->type = e1000_nvm_flash_hw; nvm->word_size = 2048; - /* - * Autonomous Flash update bit must be cleared due + /* Autonomous Flash update bit must be cleared due * to Flash update issue. */ eecd &= ~E1000_EECD_AUPDEN; @@ -254,8 +246,7 @@ static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw) nvm->type = e1000_nvm_eeprom_spi; size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> E1000_EECD_SIZE_EX_SHIFT); - /* - * Added to a constant, "size" becomes the left-shift value + /* Added to a constant, "size" becomes the left-shift value * for setting word_size. */ size += NVM_WORD_SIZE_BASE_SHIFT; @@ -382,12 +373,11 @@ static s32 e1000_init_mac_params_82571(struct e1000_hw *hw) /* FWSM register */ mac->has_fwsm = TRUE; - /* - * ARC supported; valid only if manageability features are + /* ARC supported; valid only if manageability features are * enabled. */ - mac->arc_subsystem_valid = (E1000_READ_REG(hw, E1000_FWSM) & - E1000_FWSM_MODE_MASK) ? TRUE : FALSE; + mac->arc_subsystem_valid = !!(E1000_READ_REG(hw, E1000_FWSM) & + E1000_FWSM_MODE_MASK); break; case e1000_82574: case e1000_82583: @@ -405,8 +395,7 @@ static s32 e1000_init_mac_params_82571(struct e1000_hw *hw) break; } - /* - * Ensure that the inter-port SWSM.SMBI lock bit is clear before + /* Ensure that the inter-port SWSM.SMBI lock bit is clear before * first NVM or PHY acess. This should be done for single-port * devices, and for one port only on dual-port devices so that * for those devices we can still use the SMBI lock to synchronize @@ -422,8 +411,9 @@ static s32 e1000_init_mac_params_82571(struct e1000_hw *hw) E1000_WRITE_REG(hw, E1000_SWSM2, swsm2 | E1000_SWSM2_LOCK); force_clear_smbi = TRUE; - } else + } else { force_clear_smbi = FALSE; + } break; default: force_clear_smbi = TRUE; @@ -443,10 +433,7 @@ static s32 e1000_init_mac_params_82571(struct e1000_hw *hw) E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_SMBI); } - /* - * Initialze device specific counter of SMBI acquisition - * timeouts. - */ + /* Initialze device specific counter of SMBI acquisition timeouts. */ hw->dev_spec._82571.smb_counter = 0; return E1000_SUCCESS; @@ -477,7 +464,7 @@ void e1000_init_function_pointers_82571(struct e1000_hw *hw) static s32 e1000_get_phy_id_82571(struct e1000_hw *hw) { struct e1000_phy_info *phy = &hw->phy; - s32 ret_val = E1000_SUCCESS; + s32 ret_val; u16 phy_id = 0; DEBUGFUNC("e1000_get_phy_id_82571"); @@ -485,8 +472,7 @@ static s32 e1000_get_phy_id_82571(struct e1000_hw *hw) switch (hw->mac.type) { case e1000_82571: case e1000_82572: - /* - * The 82571 firmware may still be configuring the PHY. + /* The 82571 firmware may still be configuring the PHY. * In this case, we cannot access the PHY until the * configuration is done. So we explicitly set the * PHY ID. @@ -494,29 +480,29 @@ static s32 e1000_get_phy_id_82571(struct e1000_hw *hw) phy->id = IGP01E1000_I_PHY_ID; break; case e1000_82573: - ret_val = e1000_get_phy_id(hw); + return e1000_get_phy_id(hw); break; case e1000_82574: case e1000_82583: ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id); if (ret_val) - goto out; + return ret_val; phy->id = (u32)(phy_id << 16); usec_delay(20); ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id); if (ret_val) - goto out; + return ret_val; phy->id |= (u32)(phy_id); phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); break; default: - ret_val = -E1000_ERR_PHY; + return -E1000_ERR_PHY; break; } -out: - return ret_val; + + return E1000_SUCCESS; } /** @@ -528,15 +514,13 @@ out: static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw) { u32 swsm; - s32 ret_val = E1000_SUCCESS; s32 sw_timeout = hw->nvm.word_size + 1; s32 fw_timeout = hw->nvm.word_size + 1; s32 i = 0; DEBUGFUNC("e1000_get_hw_semaphore_82571"); - /* - * If we have timedout 3 times on trying to acquire + /* If we have timedout 3 times on trying to acquire * the inter-port SMBI semaphore, there is old code * operating on the other port, and it is not * releasing SMBI. Modify the number of times that @@ -576,12 +560,10 @@ static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw) /* Release semaphores */ e1000_put_hw_semaphore_82571(hw); DEBUGOUT("Driver can't access the NVM\n"); - ret_val = -E1000_ERR_NVM; - goto out; + return -E1000_ERR_NVM; } -out: - return ret_val; + return E1000_SUCCESS; } /** @@ -613,22 +595,19 @@ static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw) static s32 e1000_get_hw_semaphore_82573(struct e1000_hw *hw) { u32 extcnf_ctrl; - s32 ret_val = E1000_SUCCESS; s32 i = 0; DEBUGFUNC("e1000_get_hw_semaphore_82573"); extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); - extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; do { + extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP) break; - extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; - msec_delay(2); i++; } while (i < MDIO_OWNERSHIP_TIMEOUT); @@ -637,12 +616,10 @@ static s32 e1000_get_hw_semaphore_82573(struct e1000_hw *hw) /* Release semaphores */ e1000_put_hw_semaphore_82573(hw); DEBUGOUT("Driver can't access the PHY\n"); - ret_val = -E1000_ERR_PHY; - goto out; + return -E1000_ERR_PHY; } -out: - return ret_val; + return E1000_SUCCESS; } /** @@ -712,7 +689,7 @@ static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw) **/ static s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw, bool active) { - u16 data = E1000_READ_REG(hw, E1000_POEMB); + u32 data = E1000_READ_REG(hw, E1000_POEMB); DEBUGFUNC("e1000_set_d0_lplu_state_82574"); @@ -738,7 +715,7 @@ static s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw, bool active) **/ static s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw, bool active) { - u16 data = E1000_READ_REG(hw, E1000_POEMB); + u32 data = E1000_READ_REG(hw, E1000_POEMB); DEBUGFUNC("e1000_set_d3_lplu_state_82574"); @@ -771,7 +748,7 @@ static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw) ret_val = e1000_get_hw_semaphore_82571(hw); if (ret_val) - goto out; + return ret_val; switch (hw->mac.type) { case e1000_82573: @@ -784,7 +761,6 @@ static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw) if (ret_val) e1000_put_hw_semaphore_82571(hw); -out: return ret_val; } @@ -817,7 +793,7 @@ static void e1000_release_nvm_82571(struct e1000_hw *hw) static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) { - s32 ret_val = E1000_SUCCESS; + s32 ret_val; DEBUGFUNC("e1000_write_nvm_82571"); @@ -857,31 +833,27 @@ static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw) ret_val = e1000_update_nvm_checksum_generic(hw); if (ret_val) - goto out; + return ret_val; - /* - * If our nvm is an EEPROM, then we're done + /* If our nvm is an EEPROM, then we're done * otherwise, commit the checksum to the flash NVM. */ if (hw->nvm.type != e1000_nvm_flash_hw) - goto out; + return E1000_SUCCESS; /* Check for pending operations. */ for (i = 0; i < E1000_FLASH_UPDATES; i++) { msec_delay(1); - if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD) == 0) + if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD)) break; } - if (i == E1000_FLASH_UPDATES) { - ret_val = -E1000_ERR_NVM; - goto out; - } + if (i == E1000_FLASH_UPDATES) + return -E1000_ERR_NVM; /* Reset the firmware if using STM opcode. */ if ((E1000_READ_REG(hw, E1000_FLOP) & 0xFF00) == E1000_STM_OPCODE) { - /* - * The enabling of and the actual reset must be done + /* The enabling of and the actual reset must be done * in two write cycles. */ E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET_ENABLE); @@ -895,17 +867,14 @@ static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw) for (i = 0; i < E1000_FLASH_UPDATES; i++) { msec_delay(1); - if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD) == 0) + if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD)) break; } - if (i == E1000_FLASH_UPDATES) { - ret_val = -E1000_ERR_NVM; - goto out; - } + if (i == E1000_FLASH_UPDATES) + return -E1000_ERR_NVM; -out: - return ret_val; + return E1000_SUCCESS; } /** @@ -944,19 +913,17 @@ static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, { struct e1000_nvm_info *nvm = &hw->nvm; u32 i, eewr = 0; - s32 ret_val = 0; + s32 ret_val = E1000_SUCCESS; DEBUGFUNC("e1000_write_nvm_eewr_82571"); - /* - * A check for invalid values: offset too large, too many words, + /* A check for invalid values: offset too large, too many words, * and not enough words. */ if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || (words == 0)) { DEBUGOUT("nvm parameter(s) out of bounds\n"); - ret_val = -E1000_ERR_NVM; - goto out; + return -E1000_ERR_NVM; } for (i = 0; i < words; i++) { @@ -975,7 +942,6 @@ static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, break; } -out: return ret_val; } @@ -988,7 +954,6 @@ out: static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw) { s32 timeout = PHY_CFG_TIMEOUT; - s32 ret_val = E1000_SUCCESS; DEBUGFUNC("e1000_get_cfg_done_82571"); @@ -1001,12 +966,10 @@ static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw) } if (!timeout) { DEBUGOUT("MNG configuration cycle has not completed.\n"); - ret_val = -E1000_ERR_RESET; - goto out; + return -E1000_ERR_RESET; } -out: - return ret_val; + return E1000_SUCCESS; } /** @@ -1023,39 +986,40 @@ out: static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active) { struct e1000_phy_info *phy = &hw->phy; - s32 ret_val = E1000_SUCCESS; + s32 ret_val; u16 data; DEBUGFUNC("e1000_set_d0_lplu_state_82571"); if (!(phy->ops.read_reg)) - goto out; + return E1000_SUCCESS; ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); if (ret_val) - goto out; + return ret_val; if (active) { data |= IGP02E1000_PM_D0_LPLU; ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, data); if (ret_val) - goto out; + return ret_val; /* When LPLU is enabled, we should disable SmartSpeed */ ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &data); + if (ret_val) + return ret_val; data &= ~IGP01E1000_PSCFR_SMART_SPEED; ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, data); if (ret_val) - goto out; + return ret_val; } else { data &= ~IGP02E1000_PM_D0_LPLU; ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, data); - /* - * LPLU and SmartSpeed are mutually exclusive. LPLU is used + /* LPLU and SmartSpeed are mutually exclusive. LPLU is used * during Dx states where the power conservation is most * important. During driver activity we should enable * SmartSpeed, so performance is maintained. @@ -1065,32 +1029,31 @@ static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active) IGP01E1000_PHY_PORT_CONFIG, &data); if (ret_val) - goto out; + return ret_val; data |= IGP01E1000_PSCFR_SMART_SPEED; ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, data); if (ret_val) - goto out; + return ret_val; } else if (phy->smart_speed == e1000_smart_speed_off) { ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &data); if (ret_val) - goto out; + return ret_val; data &= ~IGP01E1000_PSCFR_SMART_SPEED; ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, data); if (ret_val) - goto out; + return ret_val; } } -out: - return ret_val; + return E1000_SUCCESS; } /** @@ -1101,13 +1064,12 @@ out: **/ static s32 e1000_reset_hw_82571(struct e1000_hw *hw) { - u32 ctrl, ctrl_ext; + u32 ctrl, ctrl_ext, eecd, tctl; s32 ret_val; DEBUGFUNC("e1000_reset_hw_82571"); - /* - * Prevent the PCI-E bus from sticking if there is no TLP connection + /* Prevent the PCI-E bus from sticking if there is no TLP connection * on the last TLP read/write transaction when MAC is reset. */ ret_val = e1000_disable_pcie_master_generic(hw); @@ -1118,13 +1080,14 @@ static s32 e1000_reset_hw_82571(struct e1000_hw *hw) E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); E1000_WRITE_REG(hw, E1000_RCTL, 0); - E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); + tctl = E1000_READ_REG(hw, E1000_TCTL); + tctl &= ~E1000_TCTL_EN; + E1000_WRITE_REG(hw, E1000_TCTL, tctl); E1000_WRITE_FLUSH(hw); msec_delay(10); - /* - * Must acquire the MDIO ownership before MAC reset. + /* Must acquire the MDIO ownership before MAC reset. * Ownership defaults to firmware after a reset. */ switch (hw->mac.type) { @@ -1167,15 +1130,23 @@ static s32 e1000_reset_hw_82571(struct e1000_hw *hw) ret_val = e1000_get_auto_rd_done_generic(hw); if (ret_val) /* We don't want to continue accessing MAC registers. */ - goto out; + return ret_val; - /* - * Phy configuration from NVM just starts after EECD_AUTO_RD is set. + /* Phy configuration from NVM just starts after EECD_AUTO_RD is set. * Need to wait for Phy configuration completion before accessing * NVM and Phy. */ switch (hw->mac.type) { + case e1000_82571: + case e1000_82572: + /* REQ and GNT bits need to be cleared when using AUTO_RD + * to access the EEPROM. + */ + eecd = E1000_READ_REG(hw, E1000_EECD); + eecd &= ~(E1000_EECD_REQ | E1000_EECD_GNT); + E1000_WRITE_REG(hw, E1000_EECD, eecd); + break; case e1000_82573: case e1000_82574: case e1000_82583: @@ -1193,7 +1164,7 @@ static s32 e1000_reset_hw_82571(struct e1000_hw *hw) /* Install any alternate MAC address into RAR0 */ ret_val = e1000_check_alt_mac_addr_generic(hw); if (ret_val) - goto out; + return ret_val; e1000_set_laa_state_82571(hw, TRUE); } @@ -1202,8 +1173,7 @@ static s32 e1000_reset_hw_82571(struct e1000_hw *hw) if (hw->phy.media_type == e1000_media_type_internal_serdes) hw->mac.serdes_link_state = e1000_serdes_link_down; -out: - return ret_val; + return E1000_SUCCESS; } /** @@ -1225,16 +1195,15 @@ static s32 e1000_init_hw_82571(struct e1000_hw *hw) /* Initialize identification LED */ ret_val = mac->ops.id_led_init(hw); + /* An error is not fatal and we should not stop init due to this */ if (ret_val) DEBUGOUT("Error initializing identification LED\n"); - /* This is not fatal and we should not stop init due to this */ /* Disabling VLAN filtering */ DEBUGOUT("Initializing the IEEE VLAN\n"); mac->ops.clear_vfta(hw); - /* Setup the receive address. */ - /* + /* Setup the receive address. * If, however, a locally administered address was assigned to the * 82571, we must reserve a RAR for it to work around an issue where * resetting one port will reload the MAC on the other port. @@ -1277,8 +1246,7 @@ static s32 e1000_init_hw_82571(struct e1000_hw *hw) break; } - /* - * Clear all of the statistics registers (clear on read). It is + /* Clear all of the statistics registers (clear on read). It is * important that we do this after we have tried to establish link * because the symbol error count will increment wildly if there * is no link. @@ -1377,8 +1345,7 @@ static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw) E1000_WRITE_REG(hw, E1000_PBA_ECC, reg); } - /* - * Workaround for hardware errata. + /* Workaround for hardware errata. * Ensure that DMA Dynamic Clock gating is disabled on 82571 and 82572 */ if ((hw->mac.type == e1000_82571) || @@ -1388,6 +1355,15 @@ static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw) E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); } + /* Disable IPv6 extension header parsing because some malformed + * IPv6 headers can hang the Rx. + */ + if (hw->mac.type <= e1000_82573) { + reg = E1000_READ_REG(hw, E1000_RFCTL); + reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS); + E1000_WRITE_REG(hw, E1000_RFCTL, reg); + } + /* PCI-Ex Control Registers */ switch (hw->mac.type) { case e1000_82574: @@ -1396,8 +1372,7 @@ static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw) reg |= (1 << 22); E1000_WRITE_REG(hw, E1000_GCR, reg); - /* - * Workaround for hardware errata. + /* Workaround for hardware errata. * apply workaround for hardware errata documented in errata * docs Fixes issue where some error prone or unreliable PCIe * completions are occurring, particularly with ASPM enabled. @@ -1435,25 +1410,25 @@ static void e1000_clear_vfta_82571(struct e1000_hw *hw) case e1000_82574: case e1000_82583: if (hw->mng_cookie.vlan_id != 0) { - /* - * The VFTA is a 4096b bit-field, each identifying + /* The VFTA is a 4096b bit-field, each identifying * a single VLAN ID. The following operations * determine which 32b entry (i.e. offset) into the * array we want to set the VLAN ID (i.e. bit) of * the manageability unit. */ vfta_offset = (hw->mng_cookie.vlan_id >> - E1000_VFTA_ENTRY_SHIFT) & E1000_VFTA_ENTRY_MASK; - vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id & - E1000_VFTA_ENTRY_BIT_SHIFT_MASK); + E1000_VFTA_ENTRY_SHIFT) & + E1000_VFTA_ENTRY_MASK; + vfta_bit_in_reg = + 1 << (hw->mng_cookie.vlan_id & + E1000_VFTA_ENTRY_BIT_SHIFT_MASK); } break; default: break; } for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { - /* - * If the offset we want to clear is the same offset of the + /* If the offset we want to clear is the same offset of the * manageability VLAN ID, then clear all bits except that of * the manageability unit. */ @@ -1495,8 +1470,7 @@ static s32 e1000_led_on_82574(struct e1000_hw *hw) ctrl = hw->mac.ledctl_mode2; if (!(E1000_STATUS_LU & E1000_READ_REG(hw, E1000_STATUS))) { - /* - * If no link, then turn LED on by setting the invert bit + /* If no link, then turn LED on by setting the invert bit * for each LED that's "on" (0x0E) in ledctl_mode2. */ for (i = 0; i < 4; i++) @@ -1519,30 +1493,28 @@ bool e1000_check_phy_82574(struct e1000_hw *hw) { u16 status_1kbt = 0; u16 receive_errors = 0; - bool phy_hung = FALSE; - s32 ret_val = E1000_SUCCESS; + s32 ret_val; DEBUGFUNC("e1000_check_phy_82574"); - /* - * Read PHY Receive Error counter first, if its is max - all F's then + /* Read PHY Receive Error counter first, if its is max - all F's then * read the Base1000T status register If both are max then PHY is hung. */ ret_val = hw->phy.ops.read_reg(hw, E1000_RECEIVE_ERROR_COUNTER, &receive_errors); if (ret_val) - goto out; + return FALSE; if (receive_errors == E1000_RECEIVE_ERROR_MAX) { ret_val = hw->phy.ops.read_reg(hw, E1000_BASE1000T_STATUS, &status_1kbt); if (ret_val) - goto out; + return FALSE; if ((status_1kbt & E1000_IDLE_ERROR_COUNT_MASK) == E1000_IDLE_ERROR_COUNT_MASK) - phy_hung = TRUE; + return TRUE; } -out: - return phy_hung; + + return FALSE; } @@ -1560,8 +1532,7 @@ static s32 e1000_setup_link_82571(struct e1000_hw *hw) { DEBUGFUNC("e1000_setup_link_82571"); - /* - * 82573 does not have a word in the NVM to determine + /* 82573 does not have a word in the NVM to determine * the default flow control setting, so we explicitly * set it to full. */ @@ -1608,17 +1579,14 @@ static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw) ret_val = e1000_copper_link_setup_igp(hw); break; default: - ret_val = -E1000_ERR_PHY; + return -E1000_ERR_PHY; break; } if (ret_val) - goto out; - - ret_val = e1000_setup_copper_link_generic(hw); + return ret_val; -out: - return ret_val; + return e1000_setup_copper_link_generic(hw); } /** @@ -1635,8 +1603,7 @@ static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw) switch (hw->mac.type) { case e1000_82571: case e1000_82572: - /* - * If SerDes loopback mode is entered, there is no form + /* If SerDes loopback mode is entered, there is no form * of reset to take the adapter out of that mode. So we * have to explicitly take the adapter out of loopback * mode. This prevents drivers from twiddling their thumbs @@ -1685,16 +1652,17 @@ static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw) ctrl = E1000_READ_REG(hw, E1000_CTRL); status = E1000_READ_REG(hw, E1000_STATUS); + E1000_READ_REG(hw, E1000_RXCW); + /* SYNCH bit and IV bit are sticky */ + usec_delay(10); rxcw = E1000_READ_REG(hw, E1000_RXCW); if ((rxcw & E1000_RXCW_SYNCH) && !(rxcw & E1000_RXCW_IV)) { - /* Receiver is synchronized with no invalid bits. */ switch (mac->serdes_link_state) { case e1000_serdes_link_autoneg_complete: if (!(status & E1000_STATUS_LU)) { - /* - * We have lost link, retry autoneg before + /* We have lost link, retry autoneg before * reporting link failure */ mac->serdes_link_state = @@ -1707,15 +1675,12 @@ static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw) break; case e1000_serdes_link_forced_up: - /* - * If we are receiving /C/ ordered sets, re-enable + /* If we are receiving /C/ ordered sets, re-enable * auto-negotiation in the TXCW register and disable * forced link in the Device Control register in an * attempt to auto-negotiate with our link partner. - * If the partner code word is null, stop forcing - * and restart auto negotiation. */ - if ((rxcw & E1000_RXCW_C) || !(rxcw & E1000_RXCW_CW)) { + if (rxcw & E1000_RXCW_C) { /* Enable autoneg, and unforce link up */ E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); E1000_WRITE_REG(hw, E1000_CTRL, @@ -1731,8 +1696,7 @@ static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw) case e1000_serdes_link_autoneg_progress: if (rxcw & E1000_RXCW_C) { - /* - * We received /C/ ordered sets, meaning the + /* We received /C/ ordered sets, meaning the * link partner has autonegotiated, and we can * trust the Link Up (LU) status bit. */ @@ -1748,8 +1712,7 @@ static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw) DEBUGOUT("AN_PROG -> DOWN\n"); } } else { - /* - * The link partner did not autoneg. + /* The link partner did not autoneg. * Force link up and full duplex, and change * state to forced. */ @@ -1774,8 +1737,7 @@ static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw) case e1000_serdes_link_down: default: - /* - * The link was down but the receiver has now gained + /* The link was down but the receiver has now gained * valid sync, so lets see if we can bring the link * up. */ @@ -1794,17 +1756,18 @@ static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw) mac->serdes_link_state = e1000_serdes_link_down; DEBUGOUT("ANYSTATE -> DOWN\n"); } else { - /* - * Check several times, if Sync and Config - * both are consistently 1 then simply ignore - * the Invalid bit and restart Autoneg + /* Check several times, if SYNCH bit and CONFIG + * bit both are consistently 1 then simply ignore + * the IV bit and restart Autoneg */ for (i = 0; i < AN_RETRY_COUNT; i++) { usec_delay(10); rxcw = E1000_READ_REG(hw, E1000_RXCW); - if ((rxcw & E1000_RXCW_IV) && - !((rxcw & E1000_RXCW_SYNCH) && - (rxcw & E1000_RXCW_C))) { + if ((rxcw & E1000_RXCW_SYNCH) && + (rxcw & E1000_RXCW_C)) + continue; + + if (rxcw & E1000_RXCW_IV) { mac->serdes_has_link = FALSE; mac->serdes_link_state = e1000_serdes_link_down; @@ -1845,7 +1808,7 @@ static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data) ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); if (ret_val) { DEBUGOUT("NVM Read Error\n"); - goto out; + return ret_val; } switch (hw->mac.type) { @@ -1862,8 +1825,7 @@ static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data) break; } -out: - return ret_val; + return E1000_SUCCESS; } /** @@ -1900,15 +1862,14 @@ void e1000_set_laa_state_82571(struct e1000_hw *hw, bool state) /* If workaround is activated... */ if (state) - /* - * Hold a copy of the LAA in RAR[14] This is done so that + /* Hold a copy of the LAA in RAR[14] This is done so that * between the time RAR[0] gets clobbered and the time it * gets fixed, the actual LAA is in one of the RARs and no * incoming packets directed to this port are dropped. * Eventually the LAA will be in RAR[0] and RAR[14]. */ hw->mac.ops.rar_set(hw, hw->mac.addr, - hw->mac.rar_entry_count - 1); + hw->mac.rar_entry_count - 1); return; } @@ -1925,25 +1886,23 @@ void e1000_set_laa_state_82571(struct e1000_hw *hw, bool state) static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw) { struct e1000_nvm_info *nvm = &hw->nvm; - s32 ret_val = E1000_SUCCESS; + s32 ret_val; u16 data; DEBUGFUNC("e1000_fix_nvm_checksum_82571"); if (nvm->type != e1000_nvm_flash_hw) - goto out; + return E1000_SUCCESS; - /* - * Check bit 4 of word 10h. If it is 0, firmware is done updating + /* Check bit 4 of word 10h. If it is 0, firmware is done updating * 10h-12h. Checksum may need to be fixed. */ ret_val = nvm->ops.read(hw, 0x10, 1, &data); if (ret_val) - goto out; + return ret_val; if (!(data & 0x10)) { - /* - * Read 0x23 and check bit 15. This bit is a 1 + /* Read 0x23 and check bit 15. This bit is a 1 * when the checksum has already been fixed. If * the checksum is still wrong and this bit is a * 1, we need to return bad checksum. Otherwise, @@ -1952,19 +1911,20 @@ static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw) */ ret_val = nvm->ops.read(hw, 0x23, 1, &data); if (ret_val) - goto out; + return ret_val; if (!(data & 0x8000)) { data |= 0x8000; ret_val = nvm->ops.write(hw, 0x23, 1, &data); if (ret_val) - goto out; + return ret_val; ret_val = nvm->ops.update(hw); + if (ret_val) + return ret_val; } } -out: - return ret_val; + return E1000_SUCCESS; } @@ -1974,25 +1934,21 @@ out: **/ static s32 e1000_read_mac_addr_82571(struct e1000_hw *hw) { - s32 ret_val = E1000_SUCCESS; - DEBUGFUNC("e1000_read_mac_addr_82571"); if (hw->mac.type == e1000_82571) { - /* - * If there's an alternate MAC address place it in RAR0 + s32 ret_val; + + /* If there's an alternate MAC address place it in RAR0 * so that it will override the Si installed default perm * address. */ ret_val = e1000_check_alt_mac_addr_generic(hw); if (ret_val) - goto out; + return ret_val; } - ret_val = e1000_read_mac_addr_generic(hw); - -out: - return ret_val; + return e1000_read_mac_addr_generic(hw); } /** @@ -2007,7 +1963,7 @@ static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw) struct e1000_phy_info *phy = &hw->phy; struct e1000_mac_info *mac = &hw->mac; - if (!(phy->ops.check_reset_block)) + if (!phy->ops.check_reset_block) return; /* If the management interface is not enabled, then power down */ diff --git a/sys/dev/e1000/e1000_82575.c b/sys/dev/e1000/e1000_82575.c index a0d48b3..5722f46 100644 --- a/sys/dev/e1000/e1000_82575.c +++ b/sys/dev/e1000/e1000_82575.c @@ -1,6 +1,6 @@ /****************************************************************************** - Copyright (c) 2001-2012, Intel Corporation + Copyright (c) 2001-2013, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without @@ -144,6 +144,8 @@ static bool e1000_sgmii_uses_mdio_82575(struct e1000_hw *hw) break; case e1000_82580: case e1000_i350: + case e1000_i210: + case e1000_i211: reg = E1000_READ_REG(hw, E1000_MDICNFG); ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO); break; @@ -332,6 +334,7 @@ s32 e1000_init_nvm_params_82575(struct e1000_hw *hw) } else { nvm->type = e1000_nvm_flash_hw; } + /* Function Pointers */ nvm->ops.acquire = e1000_acquire_nvm_82575; nvm->ops.release = e1000_release_nvm_82575; @@ -385,11 +388,16 @@ static s32 e1000_init_mac_params_82575(struct e1000_hw *hw) mac->rar_entry_count = E1000_RAR_ENTRIES_82576; if (mac->type == e1000_82580) mac->rar_entry_count = E1000_RAR_ENTRIES_82580; - if (mac->type == e1000_i350) { + if (mac->type == e1000_i350) mac->rar_entry_count = E1000_RAR_ENTRIES_I350; - /* Enable EEE default settings for i350 */ + + /* Enable EEE default settings for EEE supported devices */ + if (mac->type >= e1000_i350) dev_spec->eee_disable = FALSE; - } + + /* Allow a single clear of the SW semaphore on I210 and newer */ + if (mac->type >= e1000_i210) + dev_spec->clear_semaphore_once = TRUE; /* Set if part includes ASF firmware */ mac->asf_firmware_present = TRUE; @@ -428,7 +436,7 @@ static s32 e1000_init_mac_params_82575(struct e1000_hw *hw) mac->ops.config_collision_dist = e1000_config_collision_dist_82575; /* multicast address update */ mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic; - if (hw->mac.type == e1000_i350) { + if (mac->type == e1000_i350) { /* writing VFTA */ mac->ops.write_vfta = e1000_write_vfta_i350; /* clearing VFTA */ @@ -439,6 +447,9 @@ static s32 e1000_init_mac_params_82575(struct e1000_hw *hw) /* clearing VFTA */ mac->ops.clear_vfta = e1000_clear_vfta_generic; } + if (hw->mac.type >= e1000_82580) + mac->ops.validate_mdi_setting = + e1000_validate_mdi_setting_crossover_generic; /* ID LED init */ mac->ops.id_led_init = e1000_id_led_init_generic; /* blink LED */ @@ -634,6 +645,8 @@ static s32 e1000_get_phy_id_82575(struct e1000_hw *hw) break; case e1000_82580: case e1000_i350: + case e1000_i210: + case e1000_i211: mdic = E1000_READ_REG(hw, E1000_MDICNFG); mdic &= E1000_MDICNFG_PHY_MASK; phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT; @@ -1143,6 +1156,15 @@ static s32 e1000_check_for_link_82575(struct e1000_hw *hw) */ hw->mac.get_link_status = !hw->mac.serdes_has_link; + /* + * Configure Flow Control now that Auto-Neg has completed. + * First, we need to restore the desired flow control + * settings because we may have had to re-autoneg with a + * different link partner. + */ + ret_val = e1000_config_fc_after_link_up_generic(hw); + if (ret_val) + DEBUGOUT("Error configuring flow control\n"); } else { ret_val = e1000_check_for_copper_link_generic(hw); } @@ -1222,6 +1244,7 @@ static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, *duplex = FULL_DUPLEX; else *duplex = HALF_DUPLEX; + } else { mac->serdes_has_link = FALSE; *speed = 0; @@ -1397,7 +1420,8 @@ static s32 e1000_init_hw_82575(struct e1000_hw *hw) static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw) { u32 ctrl; - s32 ret_val; + s32 ret_val; + u32 phpm_reg; DEBUGFUNC("e1000_setup_copper_link_82575"); @@ -1406,6 +1430,13 @@ static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw) ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); E1000_WRITE_REG(hw, E1000_CTRL, ctrl); + /* Clear Go Link Disconnect bit */ + if (hw->mac.type >= e1000_82580) { + phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT); + phpm_reg &= ~E1000_82580_PM_GO_LINKD; + E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg); + } + ret_val = e1000_setup_serdes_link_82575(hw); if (ret_val) goto out; @@ -1423,12 +1454,17 @@ static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw) switch (hw->phy.type) { case e1000_phy_i210: case e1000_phy_m88: - if (hw->phy.id == I347AT4_E_PHY_ID || - hw->phy.id == M88E1112_E_PHY_ID || - hw->phy.id == M88E1340M_E_PHY_ID) + switch (hw->phy.id) { + case I347AT4_E_PHY_ID: + case M88E1112_E_PHY_ID: + case M88E1340M_E_PHY_ID: + case I210_I_PHY_ID: ret_val = e1000_copper_link_setup_m88_gen2(hw); - else + break; + default: ret_val = e1000_copper_link_setup_m88(hw); + break; + } break; case e1000_phy_igp_3: ret_val = e1000_copper_link_setup_igp(hw); @@ -1460,7 +1496,7 @@ out: **/ static s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw) { - u32 ctrl_ext, ctrl_reg, reg; + u32 ctrl_ext, ctrl_reg, reg, anadv_reg; bool pcs_autoneg; s32 ret_val = E1000_SUCCESS; u16 data; @@ -1544,26 +1580,47 @@ static s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw) reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP | E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK); - /* - * We force flow control to prevent the CTRL register values from being - * overwritten by the autonegotiated flow control values - */ - reg |= E1000_PCS_LCTL_FORCE_FCTRL; - if (pcs_autoneg) { /* Set PCS register for autoneg */ reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */ E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */ + + /* Disable force flow control for autoneg */ + reg &= ~E1000_PCS_LCTL_FORCE_FCTRL; + + /* Configure flow control advertisement for autoneg */ + anadv_reg = E1000_READ_REG(hw, E1000_PCS_ANADV); + anadv_reg &= ~(E1000_TXCW_ASM_DIR | E1000_TXCW_PAUSE); + + switch (hw->fc.requested_mode) { + case e1000_fc_full: + case e1000_fc_rx_pause: + anadv_reg |= E1000_TXCW_ASM_DIR; + anadv_reg |= E1000_TXCW_PAUSE; + break; + case e1000_fc_tx_pause: + anadv_reg |= E1000_TXCW_ASM_DIR; + break; + default: + break; + } + + E1000_WRITE_REG(hw, E1000_PCS_ANADV, anadv_reg); + DEBUGOUT1("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg); } else { /* Set PCS register for forced link */ reg |= E1000_PCS_LCTL_FSD; /* Force Speed */ + + /* Force flow control for forced link */ + reg |= E1000_PCS_LCTL_FORCE_FCTRL; + DEBUGOUT1("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg); } E1000_WRITE_REG(hw, E1000_PCS_LCTL, reg); - if (!e1000_sgmii_active_82575(hw)) + if (!pcs_autoneg && !e1000_sgmii_active_82575(hw)) e1000_force_mac_fc_generic(hw); return ret_val; @@ -1582,137 +1639,70 @@ static s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw) **/ static s32 e1000_get_media_type_82575(struct e1000_hw *hw) { - u32 lan_id = 0; - s32 ret_val = E1000_ERR_CONFIG; struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; + s32 ret_val = E1000_SUCCESS; u32 ctrl_ext = 0; - u32 current_link_mode = 0; - u16 init_ctrl_wd_3 = 0; - u8 init_ctrl_wd_3_offset = 0; - u8 init_ctrl_wd_3_bit_offset = 0; + u32 link_mode = 0; /* Set internal phy as default */ dev_spec->sgmii_active = FALSE; dev_spec->module_plugged = FALSE; - /* - * Check if NVM access method is attached already. - * If it is then Init Control Word #3 is considered - * otherwise runtime CSR register content is taken. - */ - /* Get CSR setting */ ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); - /* Get link mode setting */ - if ((hw->nvm.ops.read) && (hw->nvm.ops.read != e1000_null_read_nvm)) { - /* Take link mode from EEPROM */ - - /* - * Get LAN port ID to derive its - * adequate Init Control Word #3 - */ - lan_id = ((E1000_READ_REG(hw, E1000_STATUS) & - E1000_STATUS_LAN_ID_MASK) >> E1000_STATUS_LAN_ID_OFFSET); - /* - * Derive Init Control Word #3 offset - * and mask to pick up link mode setting. - */ - if (hw->mac.type < e1000_82580) { - init_ctrl_wd_3_offset = lan_id ? - NVM_INIT_CONTROL3_PORT_A : NVM_INIT_CONTROL3_PORT_B; - init_ctrl_wd_3_bit_offset = NVM_WORD24_LNK_MODE_OFFSET; - } else { - init_ctrl_wd_3_offset = - NVM_82580_LAN_FUNC_OFFSET(lan_id) + - NVM_INIT_CONTROL3_PORT_A; - init_ctrl_wd_3_bit_offset = - NVM_WORD24_82580_LNK_MODE_OFFSET; - } - /* Read Init Control Word #3*/ - hw->nvm.ops.read(hw, init_ctrl_wd_3_offset, 1, &init_ctrl_wd_3); - - /* - * Align link mode bits to - * their CTRL_EXT location. - */ - current_link_mode = init_ctrl_wd_3; - current_link_mode <<= (E1000_CTRL_EXT_LINK_MODE_OFFSET - - init_ctrl_wd_3_bit_offset); - current_link_mode &= E1000_CTRL_EXT_LINK_MODE_MASK; - - /* - * Switch to CSR for all but internal PHY. - */ - if (current_link_mode != E1000_CTRL_EXT_LINK_MODE_GMII) - /* Take link mode from CSR */ - current_link_mode = ctrl_ext & - E1000_CTRL_EXT_LINK_MODE_MASK; - } else { - /* Take link mode from CSR */ - current_link_mode = ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK; - } - - switch (current_link_mode) { + /* extract link mode setting */ + link_mode = ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK; + switch (link_mode) { case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX: hw->phy.media_type = e1000_media_type_internal_serdes; - current_link_mode = E1000_CTRL_EXT_LINK_MODE_1000BASE_KX; break; case E1000_CTRL_EXT_LINK_MODE_GMII: hw->phy.media_type = e1000_media_type_copper; - current_link_mode = E1000_CTRL_EXT_LINK_MODE_GMII; break; case E1000_CTRL_EXT_LINK_MODE_SGMII: - case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES: /* Get phy control interface type set (MDIO vs. I2C)*/ if (e1000_sgmii_uses_mdio_82575(hw)) { hw->phy.media_type = e1000_media_type_copper; dev_spec->sgmii_active = TRUE; - current_link_mode = E1000_CTRL_EXT_LINK_MODE_SGMII; - } else { - ret_val = e1000_set_sfp_media_type_82575(hw); - if (ret_val != E1000_SUCCESS) - goto out; - if (hw->phy.media_type == - e1000_media_type_internal_serdes) { - current_link_mode = - E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; - } else if (hw->phy.media_type == - e1000_media_type_copper) { - current_link_mode = - E1000_CTRL_EXT_LINK_MODE_SGMII; + break; + } + /* fall through for I2C based SGMII */ + case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES: + /* read media type from SFP EEPROM */ + ret_val = e1000_set_sfp_media_type_82575(hw); + if ((ret_val != E1000_SUCCESS) || + (hw->phy.media_type == e1000_media_type_unknown)) { + /* + * If media type was not identified then return media + * type defined by the CTRL_EXT settings. + */ + hw->phy.media_type = e1000_media_type_internal_serdes; + + if (link_mode == E1000_CTRL_EXT_LINK_MODE_SGMII) { + hw->phy.media_type = e1000_media_type_copper; + dev_spec->sgmii_active = TRUE; } + + break; } - break; - default: - DEBUGOUT("Link mode mask doesn't fit bit field size\n"); - goto out; - } - /* - * Do not change current link mode setting - * if media type is fibre or has not been - * recognized. - */ - if ((hw->phy.media_type != e1000_media_type_unknown) && - (hw->phy.media_type != e1000_media_type_fiber)) { - /* Update link mode */ + + /* do not change link mode for 100BaseFX */ + if (dev_spec->eth_flags.e100_base_fx) + break; + + /* change current link mode setting */ ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK; - E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | - current_link_mode); - } - ret_val = E1000_SUCCESS; -out: - /* - * If media type was not identified then return media type - * defined by the CTRL_EXT settings. - */ - if (hw->phy.media_type == e1000_media_type_unknown) { - if (current_link_mode == E1000_CTRL_EXT_LINK_MODE_SGMII) - hw->phy.media_type = e1000_media_type_copper; + if (hw->phy.media_type == e1000_media_type_copper) + ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_SGMII; else - hw->phy.media_type = e1000_media_type_internal_serdes; + ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; + + E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); + + break; } return ret_val; @@ -1730,40 +1720,52 @@ static s32 e1000_set_sfp_media_type_82575(struct e1000_hw *hw) s32 ret_val = E1000_ERR_CONFIG; u32 ctrl_ext = 0; struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; - struct sfp_e1000_flags eth_flags = {0}; + struct sfp_e1000_flags *eth_flags = &dev_spec->eth_flags; u8 tranceiver_type = 0; + s32 timeout = 3; - /* Turn I2C interface ON */ + /* Turn I2C interface ON and power on sfp cage */ ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); + ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA; E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_I2C_ENA); + E1000_WRITE_FLUSH(hw); + /* Read SFP module data */ - ret_val = e1000_read_sfp_data_byte(hw, + while (timeout) { + ret_val = e1000_read_sfp_data_byte(hw, E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_IDENTIFIER_OFFSET), &tranceiver_type); + if (ret_val == E1000_SUCCESS) + break; + msec_delay(100); + timeout--; + } if (ret_val != E1000_SUCCESS) goto out; + ret_val = e1000_read_sfp_data_byte(hw, E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_ETH_FLAGS_OFFSET), - (u8 *)ð_flags); + (u8 *)eth_flags); if (ret_val != E1000_SUCCESS) goto out; - /* - * Check if there is some SFP - * module plugged and powered - */ + + /* Check if there is some SFP module plugged and powered */ if ((tranceiver_type == E1000_SFF_IDENTIFIER_SFP) || (tranceiver_type == E1000_SFF_IDENTIFIER_SFF)) { dev_spec->module_plugged = TRUE; - if (eth_flags.e1000_base_lx || eth_flags.e1000_base_sx) { + if (eth_flags->e1000_base_lx || eth_flags->e1000_base_sx) { hw->phy.media_type = e1000_media_type_internal_serdes; - } else if (eth_flags.e1000_base_t) { + } else if (eth_flags->e100_base_fx) { + dev_spec->sgmii_active = TRUE; + hw->phy.media_type = e1000_media_type_internal_serdes; + } else if (eth_flags->e1000_base_t) { dev_spec->sgmii_active = TRUE; hw->phy.media_type = e1000_media_type_copper; } else { - hw->phy.media_type = e1000_media_type_unknown; - DEBUGOUT("PHY module has not been recognized\n"); - goto out; + hw->phy.media_type = e1000_media_type_unknown; + DEBUGOUT("PHY module has not been recognized\n"); + goto out; } } else { hw->phy.media_type = e1000_media_type_unknown; @@ -2280,7 +2282,7 @@ out: * e1000_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits * @hw: pointer to the HW structure * - * This resets the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on + * This resets the the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on * the values found in the EEPROM. This addresses an issue in which these * bits are not restored from EEPROM after reset. **/ @@ -2334,6 +2336,10 @@ static s32 e1000_reset_hw_82580(struct e1000_hw *hw) hw->dev_spec._82575.global_device_reset = FALSE; + /* 82580 does not reliably do global_device_reset due to hw errata */ + if (hw->mac.type == e1000_82580) + global_device_reset = FALSE; + /* Get current control state. */ ctrl = E1000_READ_REG(hw, E1000_CTRL); @@ -2660,10 +2666,15 @@ s32 e1000_set_eee_i350(struct e1000_hw *hw) /* enable or disable per user setting */ if (!(hw->dev_spec._82575.eee_disable)) { + u32 eee_su = E1000_READ_REG(hw, E1000_EEE_SU); + ipcnfg |= (E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN); eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN | E1000_EEER_LPI_FC); + /* This bit should not be set in normal operation. */ + if (eee_su & E1000_EEE_SU_LPI_CLK_STP) + DEBUGOUT("LPI Clock Stop Bit should not be set!\n"); } else { ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN); eeer &= ~(E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN | @@ -3275,3 +3286,4 @@ void e1000_i2c_bus_clear(struct e1000_hw *hw) e1000_i2c_stop(hw); } + diff --git a/sys/dev/e1000/e1000_82575.h b/sys/dev/e1000/e1000_82575.h index 4b2b245..c6bbe18 100644 --- a/sys/dev/e1000/e1000_82575.h +++ b/sys/dev/e1000/e1000_82575.h @@ -1,6 +1,6 @@ /****************************************************************************** - Copyright (c) 2001-2011, Intel Corporation + Copyright (c) 2001-2013, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without @@ -360,10 +360,13 @@ struct e1000_adv_tx_context_desc { #define E1000_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* DCA Rx Desc enable */ #define E1000_DCA_RXCTRL_HEAD_DCA_EN (1 << 6) /* DCA Rx Desc header ena */ #define E1000_DCA_RXCTRL_DATA_DCA_EN (1 << 7) /* DCA Rx Desc payload ena */ +#define E1000_DCA_RXCTRL_DESC_RRO_EN (1 << 9) /* DCA Rx Desc Relax Order */ #define E1000_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */ #define E1000_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */ +#define E1000_DCA_TXCTRL_DESC_RRO_EN (1 << 9) /* Tx rd Desc Relax Order */ #define E1000_DCA_TXCTRL_TX_WB_RO_EN (1 << 11) /* Tx Desc writeback RO bit */ +#define E1000_DCA_TXCTRL_DATA_RRO_EN (1 << 13) /* Tx rd data Relax Order */ #define E1000_DCA_TXCTRL_CPUID_MASK_82576 0xFF000000 /* Tx CPUID Mask */ #define E1000_DCA_RXCTRL_CPUID_MASK_82576 0xFF000000 /* Rx CPUID Mask */ diff --git a/sys/dev/e1000/e1000_api.c b/sys/dev/e1000/e1000_api.c index 4b2a43d..1581913 100644 --- a/sys/dev/e1000/e1000_api.c +++ b/sys/dev/e1000/e1000_api.c @@ -1,6 +1,6 @@ /****************************************************************************** - Copyright (c) 2001-2012, Intel Corporation + Copyright (c) 2001-2013, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without @@ -289,6 +289,12 @@ s32 e1000_set_mac_type(struct e1000_hw *hw) case E1000_DEV_ID_PCH2_LV_V: mac->type = e1000_pch2lan; break; + case E1000_DEV_ID_PCH_LPT_I217_LM: + case E1000_DEV_ID_PCH_LPT_I217_V: + case E1000_DEV_ID_PCH_LPTLP_I218_LM: + case E1000_DEV_ID_PCH_LPTLP_I218_V: + mac->type = e1000_pch_lpt; + break; case E1000_DEV_ID_82575EB_COPPER: case E1000_DEV_ID_82575EB_FIBER_SERDES: case E1000_DEV_ID_82575GB_QUAD_COPPER: @@ -323,6 +329,9 @@ s32 e1000_set_mac_type(struct e1000_hw *hw) case E1000_DEV_ID_I350_DA4: mac->type = e1000_i350; break; +#if defined(QV_RELEASE) && defined(SPRINGVILLE_FLASHLESS_HW) + case E1000_DEV_ID_I210_NVMLESS: +#endif /* QV_RELEASE && SPRINGVILLE_FLASHLESS_HW */ case E1000_DEV_ID_I210_COPPER: case E1000_DEV_ID_I210_COPPER_OEM1: case E1000_DEV_ID_I210_COPPER_IT: @@ -332,14 +341,17 @@ s32 e1000_set_mac_type(struct e1000_hw *hw) mac->type = e1000_i210; break; case E1000_DEV_ID_I211_COPPER: - mac->type = e1000_i211; - break; + mac->type = e1000_i211; + break; case E1000_DEV_ID_82576_VF: + case E1000_DEV_ID_82576_VF_HV: mac->type = e1000_vfadapt; break; case E1000_DEV_ID_I350_VF: + case E1000_DEV_ID_I350_VF_HV: mac->type = e1000_vfadapt_i350; break; + default: /* Should never have loaded on this device */ ret_val = -E1000_ERR_MAC_INIT; @@ -428,6 +440,7 @@ s32 e1000_setup_init_funcs(struct e1000_hw *hw, bool init_device) case e1000_ich10lan: case e1000_pchlan: case e1000_pch2lan: + case e1000_pch_lpt: e1000_init_function_pointers_ich8lan(hw); break; case e1000_82575: @@ -873,11 +886,7 @@ bool e1000_enable_tx_pkt_filtering(struct e1000_hw *hw) s32 e1000_mng_host_if_write(struct e1000_hw *hw, u8 *buffer, u16 length, u16 offset, u8 *sum) { - if (hw->mac.ops.mng_host_if_write) - return hw->mac.ops.mng_host_if_write(hw, buffer, length, - offset, sum); - - return E1000_NOT_IMPLEMENTED; + return e1000_mng_host_if_write_generic(hw, buffer, length, offset, sum); } /** @@ -890,10 +899,7 @@ s32 e1000_mng_host_if_write(struct e1000_hw *hw, u8 *buffer, u16 length, s32 e1000_mng_write_cmd_header(struct e1000_hw *hw, struct e1000_host_mng_command_header *hdr) { - if (hw->mac.ops.mng_write_cmd_header) - return hw->mac.ops.mng_write_cmd_header(hw, hdr); - - return E1000_NOT_IMPLEMENTED; + return e1000_mng_write_cmd_header_generic(hw, hdr); } /** @@ -908,23 +914,20 @@ s32 e1000_mng_write_cmd_header(struct e1000_hw *hw, **/ s32 e1000_mng_enable_host_if(struct e1000_hw *hw) { - if (hw->mac.ops.mng_enable_host_if) - return hw->mac.ops.mng_enable_host_if(hw); - - return E1000_NOT_IMPLEMENTED; + return e1000_mng_enable_host_if_generic(hw); } /** - * e1000_wait_autoneg - Waits for autonegotiation completion + * e1000_set_obff_timer - Set Optimized Buffer Flush/Fill timer * @hw: pointer to the HW structure + * @itr: u32 indicating itr value * - * Waits for autoneg to complete. Currently no func pointer exists and all - * implementations are handled in the generic version of this function. + * Set the OBFF timer based on the given interrupt rate. **/ -s32 e1000_wait_autoneg(struct e1000_hw *hw) +s32 e1000_set_obff_timer(struct e1000_hw *hw, u32 itr) { - if (hw->mac.ops.wait_autoneg) - return hw->mac.ops.wait_autoneg(hw); + if (hw->mac.ops.set_obff_timer) + return hw->mac.ops.set_obff_timer(hw, itr); return E1000_SUCCESS; } diff --git a/sys/dev/e1000/e1000_api.h b/sys/dev/e1000/e1000_api.h index 4c061c0..69db1be 100644 --- a/sys/dev/e1000/e1000_api.h +++ b/sys/dev/e1000/e1000_api.h @@ -1,6 +1,6 @@ /****************************************************************************** - Copyright (c) 2001-2012, Intel Corporation + Copyright (c) 2001-2013, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without @@ -51,6 +51,7 @@ extern void e1000_power_up_fiber_serdes_link(struct e1000_hw *hw); extern void e1000_shutdown_fiber_serdes_link(struct e1000_hw *hw); extern void e1000_init_function_pointers_i210(struct e1000_hw *hw); +s32 e1000_set_obff_timer(struct e1000_hw *hw, u32 itr); s32 e1000_set_mac_type(struct e1000_hw *hw); s32 e1000_setup_init_funcs(struct e1000_hw *hw, bool init_device); s32 e1000_init_mac_params(struct e1000_hw *hw); @@ -105,7 +106,6 @@ s32 e1000_read_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data); s32 e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data); s32 e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data); s32 e1000_write_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data); -s32 e1000_wait_autoneg(struct e1000_hw *hw); s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active); s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active); bool e1000_check_mng_mode(struct e1000_hw *hw); @@ -162,4 +162,6 @@ u32 e1000_translate_register_82542(u32 reg); (((length) > min_frame_size) && \ ((length) <= (max_frame_size + VLAN_TAG_SIZE + 1))))) -#endif +#define E1000_MAX(a, b) ((a) > (b) ? (a) : (b)) +#define E1000_DIVIDE_ROUND_UP(a, b) (((a) + (b) - 1) / (b)) /* ceil(a/b) */ +#endif /* _E1000_API_H_ */ diff --git a/sys/dev/e1000/e1000_defines.h b/sys/dev/e1000/e1000_defines.h index a4a0ed0..48c04b0 100644 --- a/sys/dev/e1000/e1000_defines.h +++ b/sys/dev/e1000/e1000_defines.h @@ -1,6 +1,6 @@ /****************************************************************************** - Copyright (c) 2001-2012, Intel Corporation + Copyright (c) 2001-2013, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without @@ -43,15 +43,7 @@ /* Wake Up Control */ #define E1000_WUC_APME 0x00000001 /* APM Enable */ #define E1000_WUC_PME_EN 0x00000002 /* PME Enable */ -#define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */ -#define E1000_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */ -#define E1000_WUC_LSCWE 0x00000010 /* Link Status wake up enable */ -#define E1000_WUC_PPROXYE 0x00000010 /* Protocol Proxy Enable */ -#define E1000_WUC_LSCWO 0x00000020 /* Link Status wake up override */ -#define E1000_WUC_SPM 0x80000000 /* Enable SPM */ #define E1000_WUC_PHY_WAKE 0x00000100 /* if PHY supports wakeup */ -#define E1000_WUC_FLX6_PHY 0x4000 /* Flexible Filter 6 Enable */ -#define E1000_WUC_FLX7_PHY 0x8000 /* Flexible Filter 7 Enable */ /* Wake Up Filter Control */ #define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */ @@ -61,41 +53,7 @@ #define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ #define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */ #define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */ -#define E1000_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */ -#define E1000_WUFC_IGNORE_TCO_PHY 0x00000800 /* Ignore WakeOn TCO packets */ -#define E1000_WUFC_FLX0_PHY 0x00001000 /* Flexible Filter 0 Enable */ -#define E1000_WUFC_FLX1_PHY 0x00002000 /* Flexible Filter 1 Enable */ -#define E1000_WUFC_FLX2_PHY 0x00004000 /* Flexible Filter 2 Enable */ -#define E1000_WUFC_FLX3_PHY 0x00008000 /* Flexible Filter 3 Enable */ -#define E1000_WUFC_FLX4_PHY 0x00000200 /* Flexible Filter 4 Enable */ -#define E1000_WUFC_FLX5_PHY 0x00000400 /* Flexible Filter 5 Enable */ -#define E1000_WUFC_IGNORE_TCO 0x00008000 /* Ignore WakeOn TCO packets */ #define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */ -#define E1000_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */ -#define E1000_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */ -#define E1000_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */ -#define E1000_WUFC_FLX4 0x00100000 /* Flexible Filter 4 Enable */ -#define E1000_WUFC_FLX5 0x00200000 /* Flexible Filter 5 Enable */ -#define E1000_WUFC_FLX6 0x00400000 /* Flexible Filter 6 Enable */ -#define E1000_WUFC_FLX7 0x00800000 /* Flexible Filter 7 Enable */ -#define E1000_WUFC_FW_RST 0x80000000 /* Wake on FW Reset Enable */ -#define E1000_WUFC_ALL_FILTERS_PHY_4 0x0000F0FF /* wakeup filters mask */ -#define E1000_WUFC_FLX_OFFSET_PHY 12 /* Flexible Filters bits offset */ -#define E1000_WUFC_FLX_FILTERS_PHY_4 0x0000F000 /* 4 flexible filters mask */ -#define E1000_WUFC_ALL_FILTERS_PHY_6 0x0000F6FF /* 6 wakeup filters mask */ -#define E1000_WUFC_FLX_FILTERS_PHY_6 0x0000F600 /* 6 flexible filters mask */ -#define E1000_WUFC_ALL_FILTERS 0x000F00FF /* all wakeup filters mask */ -#define E1000_WUFC_ALL_FILTERS_6 0x003F00FF /* Mask all 6 wu filters */ -#define E1000_WUFC_ALL_FILTERS_8 0x00FF00FF /* Mask all 8 wu filters */ -#define E1000_WUFC_FLX_OFFSET 16 /* Flexible Filters bits offset */ -#define E1000_WUFC_FLX_FILTERS 0x000F0000 /* 4 flexible filters mask */ -#define E1000_WUFC_FLX_FILTERS_6 0x003F0000 /* 6 flexible filters mask */ -#define E1000_WUFC_FLX_FILTERS_8 0x00FF0000 /* 8 flexible filters mask */ -/* - * For 82576 to utilize Extended filter masks in addition to - * existing (filter) masks - */ -#define E1000_WUFC_EXT_FLX_FILTERS 0x00300000 /* Ext. FLX filter mask */ /* Wake Up Status */ #define E1000_WUS_LNKC E1000_WUFC_LNKC @@ -103,74 +61,18 @@ #define E1000_WUS_EX E1000_WUFC_EX #define E1000_WUS_MC E1000_WUFC_MC #define E1000_WUS_BC E1000_WUFC_BC -#define E1000_WUS_ARP E1000_WUFC_ARP -#define E1000_WUS_IPV4 E1000_WUFC_IPV4 -#define E1000_WUS_IPV6 E1000_WUFC_IPV6 -#define E1000_WUS_FLX0_PHY E1000_WUFC_FLX0_PHY -#define E1000_WUS_FLX1_PHY E1000_WUFC_FLX1_PHY -#define E1000_WUS_FLX2_PHY E1000_WUFC_FLX2_PHY -#define E1000_WUS_FLX3_PHY E1000_WUFC_FLX3_PHY -#define E1000_WUS_FLX_FILTERS_PHY_4 E1000_WUFC_FLX_FILTERS_PHY_4 -#define E1000_WUS_FLX0 E1000_WUFC_FLX0 -#define E1000_WUS_FLX1 E1000_WUFC_FLX1 -#define E1000_WUS_FLX2 E1000_WUFC_FLX2 -#define E1000_WUS_FLX3 E1000_WUFC_FLX3 -#define E1000_WUS_FLX4 E1000_WUFC_FLX4 -#define E1000_WUS_FLX5 E1000_WUFC_FLX5 -#define E1000_WUS_FLX6 E1000_WUFC_FLX6 -#define E1000_WUS_FLX7 E1000_WUFC_FLX7 -#define E1000_WUS_FLX4_PHY E1000_WUFC_FLX4_PHY -#define E1000_WUS_FLX5_PHY E1000_WUFC_FLX5_PHY -#define E1000_WUS_FLX6_PHY 0x0400 -#define E1000_WUS_FLX7_PHY 0x0800 -#define E1000_WUS_FLX_FILTERS E1000_WUFC_FLX_FILTERS -#define E1000_WUS_FLX_FILTERS_6 E1000_WUFC_FLX_FILTERS_6 -#define E1000_WUS_FLX_FILTERS_8 E1000_WUFC_FLX_FILTERS_8 -#define E1000_WUS_FLX_FILTERS_PHY_6 E1000_WUFC_FLX_FILTERS_PHY_6 - -/* Wake Up Packet Length */ -#define E1000_WUPL_LENGTH_MASK 0x0FFF /* Only the lower 12 bits are valid */ - -/* Four Flexible Filters are supported */ -#define E1000_FLEXIBLE_FILTER_COUNT_MAX 4 -/* Six Flexible Filters are supported */ -#define E1000_FLEXIBLE_FILTER_COUNT_MAX_6 6 -/* Eight Flexible Filters are supported */ -#define E1000_FLEXIBLE_FILTER_COUNT_MAX_8 8 -/* Two Extended Flexible Filters are supported (82576) */ -#define E1000_EXT_FLEXIBLE_FILTER_COUNT_MAX 2 -#define E1000_FHFT_LENGTH_OFFSET 0xFC /* Length byte in FHFT */ -#define E1000_FHFT_LENGTH_MASK 0x0FF /* Length in lower byte */ - -/* Each Flexible Filter is at most 128 (0x80) bytes in length */ -#define E1000_FLEXIBLE_FILTER_SIZE_MAX 128 - -#define E1000_FFLT_SIZE E1000_FLEXIBLE_FILTER_COUNT_MAX -#define E1000_FFLT_SIZE_6 E1000_FLEXIBLE_FILTER_COUNT_MAX_6 -#define E1000_FFLT_SIZE_8 E1000_FLEXIBLE_FILTER_COUNT_MAX_8 -#define E1000_FFMT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX -#define E1000_FFVT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX /* Extended Device Control */ -#define E1000_CTRL_EXT_GPI0_EN 0x00000001 /* Maps SDP4 to GPI0 */ -#define E1000_CTRL_EXT_GPI1_EN 0x00000002 /* Maps SDP5 to GPI1 */ -#define E1000_CTRL_EXT_PHYINT_EN E1000_CTRL_EXT_GPI1_EN -#define E1000_CTRL_EXT_GPI2_EN 0x00000004 /* Maps SDP6 to GPI2 */ -#define E1000_CTRL_EXT_GPI3_EN 0x00000008 /* Maps SDP7 to GPI3 */ -/* Reserved (bits 4,5) in >= 82575 */ +#define E1000_CTRL_EXT_LPCD 0x00000004 /* LCD Power Cycle Done */ #define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* SW Definable Pin 4 data */ -#define E1000_CTRL_EXT_SDP5_DATA 0x00000020 /* SW Definable Pin 5 data */ -#define E1000_CTRL_EXT_PHY_INT E1000_CTRL_EXT_SDP5_DATA #define E1000_CTRL_EXT_SDP6_DATA 0x00000040 /* SW Definable Pin 6 data */ #define E1000_CTRL_EXT_SDP3_DATA 0x00000080 /* SW Definable Pin 3 data */ /* SDP 4/5 (bits 8,9) are reserved in >= 82575 */ #define E1000_CTRL_EXT_SDP4_DIR 0x00000100 /* Direction of SDP4 0=in 1=out */ -#define E1000_CTRL_EXT_SDP5_DIR 0x00000200 /* Direction of SDP5 0=in 1=out */ #define E1000_CTRL_EXT_SDP6_DIR 0x00000400 /* Direction of SDP6 0=in 1=out */ #define E1000_CTRL_EXT_SDP3_DIR 0x00000800 /* Direction of SDP3 0=in 1=out */ -#define E1000_CTRL_EXT_ASDCHK 0x00001000 /* Initiate an ASD sequence */ +#define E1000_CTRL_EXT_FORCE_SMBUS 0x00000800 /* Force SMBus mode */ #define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */ -#define E1000_CTRL_EXT_IPS 0x00004000 /* Invert Power State */ /* Physical Func Reset Done Indication */ #define E1000_CTRL_EXT_PFRSTD 0x00004000 #define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */ @@ -179,42 +81,22 @@ #define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000 /* Offset of the link mode field in Ctrl Ext register */ #define E1000_CTRL_EXT_LINK_MODE_OFFSET 22 -#define E1000_CTRL_EXT_LINK_MODE_82580_MASK 0x01C00000 /*82580 bit 24:22*/ #define E1000_CTRL_EXT_LINK_MODE_1000BASE_KX 0x00400000 #define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000 -#define E1000_CTRL_EXT_LINK_MODE_TBI 0x00C00000 -#define E1000_CTRL_EXT_LINK_MODE_KMRN 0x00000000 #define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000 -#define E1000_CTRL_EXT_LINK_MODE_PCIX_SERDES 0x00800000 #define E1000_CTRL_EXT_LINK_MODE_SGMII 0x00800000 #define E1000_CTRL_EXT_EIAME 0x01000000 #define E1000_CTRL_EXT_IRCA 0x00000001 -#define E1000_CTRL_EXT_WR_WMARK_MASK 0x03000000 -#define E1000_CTRL_EXT_WR_WMARK_256 0x00000000 -#define E1000_CTRL_EXT_WR_WMARK_320 0x01000000 -#define E1000_CTRL_EXT_WR_WMARK_384 0x02000000 -#define E1000_CTRL_EXT_WR_WMARK_448 0x03000000 -#define E1000_CTRL_EXT_CANC 0x04000000 /* Int delay cancellation */ #define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Drv loaded bit for FW */ -/* IAME enable bit (27) was removed in >= 82575 */ #define E1000_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */ -/* packet buffer parity error detection enabled */ -#define E1000_CRTL_EXT_PB_PAREN 0x01000000 -/* descriptor FIFO parity error detection enable */ -#define E1000_CTRL_EXT_DF_PAREN 0x02000000 -#define E1000_CTRL_EXT_GHOST_PAREN 0x40000000 #define E1000_CTRL_EXT_PBA_CLR 0x80000000 /* PBA Clear */ #define E1000_CTRL_EXT_LSECCK 0x00001000 #define E1000_CTRL_EXT_PHYPDEN 0x00100000 #define E1000_I2CCMD_REG_ADDR_SHIFT 16 -#define E1000_I2CCMD_REG_ADDR 0x00FF0000 #define E1000_I2CCMD_PHY_ADDR_SHIFT 24 -#define E1000_I2CCMD_PHY_ADDR 0x07000000 #define E1000_I2CCMD_OPCODE_READ 0x08000000 #define E1000_I2CCMD_OPCODE_WRITE 0x00000000 -#define E1000_I2CCMD_RESET 0x10000000 #define E1000_I2CCMD_READY 0x20000000 -#define E1000_I2CCMD_INTERRUPT_ENA 0x40000000 #define E1000_I2CCMD_ERROR 0x80000000 #define E1000_I2CCMD_SFP_DATA_ADDR(a) (0x0000 + (a)) #define E1000_I2CCMD_SFP_DIAG_ADDR(a) (0x0100 + (a)) @@ -235,11 +117,9 @@ #define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */ #define E1000_RXD_STAT_IPCS 0x40 /* IP xsum calculated */ #define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */ -#define E1000_RXD_STAT_CRCV 0x100 /* Speculative CRC Valid */ #define E1000_RXD_STAT_IPIDV 0x200 /* IP identification valid */ #define E1000_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */ #define E1000_RXD_STAT_DYNINT 0x800 /* Pkt caused INT via DYNINT */ -#define E1000_RXD_STAT_ACK 0x8000 /* ACK Packet indication */ #define E1000_RXD_ERR_CE 0x01 /* CRC Error */ #define E1000_RXD_ERR_SE 0x02 /* Symbol Error */ #define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */ @@ -248,11 +128,8 @@ #define E1000_RXD_ERR_IPE 0x40 /* IP Checksum Error */ #define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */ #define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */ -#define E1000_RXD_SPC_PRI_MASK 0xE000 /* Priority is in upper 3 bits */ -#define E1000_RXD_SPC_PRI_SHIFT 13 -#define E1000_RXD_SPC_CFI_MASK 0x1000 /* CFI is bit 12 */ -#define E1000_RXD_SPC_CFI_SHIFT 12 +#define E1000_RXDEXT_STATERR_TST 0x00000100 /* Time Stamp taken */ #define E1000_RXDEXT_STATERR_LB 0x00040000 #define E1000_RXDEXT_STATERR_CE 0x01000000 #define E1000_RXDEXT_STATERR_SE 0x02000000 @@ -262,13 +139,6 @@ #define E1000_RXDEXT_STATERR_IPE 0x40000000 #define E1000_RXDEXT_STATERR_RXE 0x80000000 -#define E1000_RXDEXT_LSECH 0x01000000 -#define E1000_RXDEXT_LSECE_MASK 0x60000000 -#define E1000_RXDEXT_LSECE_NO_ERROR 0x00000000 -#define E1000_RXDEXT_LSECE_NO_SA_MATCH 0x20000000 -#define E1000_RXDEXT_LSECE_REPLAY_DETECT 0x40000000 -#define E1000_RXDEXT_LSECE_BAD_SIG 0x60000000 - /* mask to determine if packets should be dropped due to frame errors */ #define E1000_RXD_ERR_FRAME_ERR_MASK ( \ E1000_RXD_ERR_CE | \ @@ -285,57 +155,25 @@ E1000_RXDEXT_STATERR_CXE | \ E1000_RXDEXT_STATERR_RXE) -#define E1000_MRQC_ENABLE_MASK 0x00000007 -#define E1000_MRQC_ENABLE_RSS_2Q 0x00000001 -#define E1000_MRQC_ENABLE_RSS_INT 0x00000004 #define E1000_MRQC_RSS_FIELD_MASK 0xFFFF0000 #define E1000_MRQC_RSS_FIELD_IPV4_TCP 0x00010000 #define E1000_MRQC_RSS_FIELD_IPV4 0x00020000 #define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX 0x00040000 -#define E1000_MRQC_RSS_FIELD_IPV6_EX 0x00080000 #define E1000_MRQC_RSS_FIELD_IPV6 0x00100000 #define E1000_MRQC_RSS_FIELD_IPV6_TCP 0x00200000 #define E1000_RXDPS_HDRSTAT_HDRSP 0x00008000 -#define E1000_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF /* Management Control */ #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */ #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */ -#define E1000_MANC_R_ON_FORCE 0x00000004 /* Reset on Force TCO - RO */ -#define E1000_MANC_RMCP_EN 0x00000100 /* Enable RCMP 026Fh Filtering */ -#define E1000_MANC_0298_EN 0x00000200 /* Enable RCMP 0298h Filtering */ -#define E1000_MANC_IPV4_EN 0x00000400 /* Enable IPv4 */ -#define E1000_MANC_IPV6_EN 0x00000800 /* Enable IPv6 */ -#define E1000_MANC_SNAP_EN 0x00001000 /* Accept LLC/SNAP */ #define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */ -/* Enable Neighbor Discovery Filtering */ -#define E1000_MANC_NEIGHBOR_EN 0x00004000 -#define E1000_MANC_ARP_RES_EN 0x00008000 /* Enable ARP response Filtering */ -#define E1000_MANC_TCO_RESET 0x00010000 /* TCO Reset Occurred */ #define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */ -#define E1000_MANC_REPORT_STATUS 0x00040000 /* Status Reporting Enabled */ -#define E1000_MANC_RCV_ALL 0x00080000 /* Receive All Enabled */ #define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */ /* Enable MAC address filtering */ #define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000 /* Enable MNG packets to host memory */ #define E1000_MANC_EN_MNG2HOST 0x00200000 -/* Enable IP address filtering */ -#define E1000_MANC_EN_IP_ADDR_FILTER 0x00400000 -#define E1000_MANC_EN_XSUM_FILTER 0x00800000 /* Ena checksum filtering */ -#define E1000_MANC_BR_EN 0x01000000 /* Ena broadcast filtering */ -#define E1000_MANC_SMB_REQ 0x01000000 /* SMBus Request */ -#define E1000_MANC_SMB_GNT 0x02000000 /* SMBus Grant */ -#define E1000_MANC_SMB_CLK_IN 0x04000000 /* SMBus Clock In */ -#define E1000_MANC_SMB_DATA_IN 0x08000000 /* SMBus Data In */ -#define E1000_MANC_SMB_DATA_OUT 0x10000000 /* SMBus Data Out */ -#define E1000_MANC_SMB_CLK_OUT 0x20000000 /* SMBus Clock Out */ -#define E1000_MANC_MPROXYE 0x40000000 /* Mngment Proxy Enable */ -#define E1000_MANC_EN_BMC2OS 0x10000000 /* OS2BMC is enabld or not */ - -#define E1000_MANC_SMB_DATA_OUT_SHIFT 28 /* SMBus Data Out Shift */ -#define E1000_MANC_SMB_CLK_OUT_SHIFT 29 /* SMBus Clock Out Shift */ #define E1000_MANC2H_PORT_623 0x00000020 /* Port 0x26f */ #define E1000_MANC2H_PORT_664 0x00000040 /* Port 0x298 */ @@ -351,19 +189,11 @@ #define E1000_RCTL_LPE 0x00000020 /* long packet enable */ #define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */ #define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */ -#define E1000_RCTL_LBM_SLP 0x00000080 /* serial link loopback mode */ #define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */ -#define E1000_RCTL_DTYP_MASK 0x00000C00 /* Descriptor type mask */ #define E1000_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */ #define E1000_RCTL_RDMTS_HALF 0x00000000 /* Rx desc min thresh size */ -#define E1000_RCTL_RDMTS_QUAT 0x00000100 /* Rx desc min thresh size */ -#define E1000_RCTL_RDMTS_EIGTH 0x00000200 /* Rx desc min thresh size */ #define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */ -#define E1000_RCTL_MO_0 0x00000000 /* multicast offset 11:0 */ -#define E1000_RCTL_MO_1 0x00001000 /* multicast offset 12:1 */ -#define E1000_RCTL_MO_2 0x00002000 /* multicast offset 13:2 */ #define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */ -#define E1000_RCTL_MDR 0x00004000 /* multicast desc ring 0 */ #define E1000_RCTL_BAM 0x00008000 /* broadcast enable */ /* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */ #define E1000_RCTL_SZ_2048 0x00000000 /* Rx buffer size 2048 */ @@ -381,11 +211,8 @@ #define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */ #define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */ #define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */ -#define E1000_RCTL_FLXBUF_MASK 0x78000000 /* Flexible buffer size */ -#define E1000_RCTL_FLXBUF_SHIFT 27 /* Flexible buffer shift */ -/* - * Use byte values for the following shift parameters +/* Use byte values for the following shift parameters * Usage: * psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) & * E1000_PSRCTL_BSIZE0_MASK) | @@ -420,16 +247,11 @@ #define E1000_SWFW_PHY3_SM 0x40 #define E1000_SWFW_SW_MNG_SM 0x400 -/* FACTPS Definitions */ -#define E1000_FACTPS_LFS 0x40000000 /* LAN Function Select */ /* Device Control */ #define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */ -#define E1000_CTRL_BEM 0x00000002 /* Endian Mode.0=little,1=big */ #define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */ #define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master reqs */ #define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */ -#define E1000_CTRL_TME 0x00000010 /* Test mode. 0=normal,1=test */ -#define E1000_CTRL_SLE 0x00000020 /* Serial Link on 0=dis,1=en */ #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */ #define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */ #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */ @@ -437,50 +259,35 @@ #define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */ #define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */ #define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */ -#define E1000_CTRL_BEM32 0x00000400 /* Big Endian 32 mode */ #define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */ #define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */ -#define E1000_CTRL_D_UD_EN 0x00002000 /* Dock/Undock enable */ -/* Defined polarity of Dock/Undock indication in SDP[0] */ -#define E1000_CTRL_D_UD_POLARITY 0x00004000 -/* Reset both PHY ports, through PHYRST_N pin */ -#define E1000_CTRL_FORCE_PHY_RESET 0x00008000 -/* enable link status from external LINK_0 and LINK_1 pins */ -#define E1000_CTRL_EXT_LINK_EN 0x00010000 #define E1000_CTRL_LANPHYPC_OVERRIDE 0x00010000 /* SW control of LANPHYPC */ #define E1000_CTRL_LANPHYPC_VALUE 0x00020000 /* SW value of LANPHYPC */ +#define E1000_CTRL_MEHE 0x00080000 /* Memory Error Handling Enable */ #define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */ #define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */ #define E1000_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */ #define E1000_CTRL_ADVD3WUC 0x00100000 /* D3 WUC */ +#define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000 /* PHY PM enable */ #define E1000_CTRL_SWDPIN3 0x00200000 /* SWDPIN 3 value */ #define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */ -#define E1000_CTRL_SWDPIO1 0x00800000 /* SWDPIN 1 input or output */ #define E1000_CTRL_SWDPIO2 0x01000000 /* SWDPIN 2 input or output */ #define E1000_CTRL_SWDPIO3 0x02000000 /* SWDPIN 3 input or output */ #define E1000_CTRL_RST 0x04000000 /* Global reset */ #define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */ #define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */ -#define E1000_CTRL_RTE 0x20000000 /* Routing tag enable */ #define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */ #define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */ -#define E1000_CTRL_SW2FW_INT 0x02000000 /* Initiate an interrupt to ME */ #define E1000_CTRL_I2C_ENA 0x02000000 /* I2C enable */ -/* - * Bit definitions for the Management Data IO (MDIO) and Management Data - * Clock (MDC) pins in the Device Control Register. - */ -#define E1000_CTRL_PHY_RESET_DIR E1000_CTRL_SWDPIO0 -#define E1000_CTRL_PHY_RESET E1000_CTRL_SWDPIN0 #define E1000_CTRL_MDIO_DIR E1000_CTRL_SWDPIO2 #define E1000_CTRL_MDIO E1000_CTRL_SWDPIN2 #define E1000_CTRL_MDC_DIR E1000_CTRL_SWDPIO3 #define E1000_CTRL_MDC E1000_CTRL_SWDPIN3 -#define E1000_CTRL_PHY_RESET_DIR4 E1000_CTRL_EXT_SDP4_DIR -#define E1000_CTRL_PHY_RESET4 E1000_CTRL_EXT_SDP4_DATA #define E1000_CONNSW_ENRGSRC 0x4 +#define E1000_CONNSW_PHYSD 0x400 +#define E1000_CONNSW_SERDESD 0x200 #define E1000_PCS_CFG_PCS_EN 8 #define E1000_PCS_LCTL_FLV_LINK_UP 1 #define E1000_PCS_LCTL_FSV_10 0 @@ -489,65 +296,37 @@ #define E1000_PCS_LCTL_FDV_FULL 8 #define E1000_PCS_LCTL_FSD 0x10 #define E1000_PCS_LCTL_FORCE_LINK 0x20 -#define E1000_PCS_LCTL_LOW_LINK_LATCH 0x40 #define E1000_PCS_LCTL_FORCE_FCTRL 0x80 #define E1000_PCS_LCTL_AN_ENABLE 0x10000 #define E1000_PCS_LCTL_AN_RESTART 0x20000 #define E1000_PCS_LCTL_AN_TIMEOUT 0x40000 -#define E1000_PCS_LCTL_AN_SGMII_BYPASS 0x80000 -#define E1000_PCS_LCTL_AN_SGMII_TRIGGER 0x100000 -#define E1000_PCS_LCTL_FAST_LINK_TIMER 0x1000000 -#define E1000_PCS_LCTL_LINK_OK_FIX 0x2000000 -#define E1000_PCS_LCTL_CRS_ON_NI 0x4000000 #define E1000_ENABLE_SERDES_LOOPBACK 0x0410 #define E1000_PCS_LSTS_LINK_OK 1 -#define E1000_PCS_LSTS_SPEED_10 0 #define E1000_PCS_LSTS_SPEED_100 2 #define E1000_PCS_LSTS_SPEED_1000 4 #define E1000_PCS_LSTS_DUPLEX_FULL 8 #define E1000_PCS_LSTS_SYNK_OK 0x10 #define E1000_PCS_LSTS_AN_COMPLETE 0x10000 -#define E1000_PCS_LSTS_AN_PAGE_RX 0x20000 -#define E1000_PCS_LSTS_AN_TIMED_OUT 0x40000 -#define E1000_PCS_LSTS_AN_REMOTE_FAULT 0x80000 -#define E1000_PCS_LSTS_AN_ERROR_RWS 0x100000 /* Device Status */ #define E1000_STATUS_FD 0x00000001 /* Duplex 0=half 1=full */ #define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */ #define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */ #define E1000_STATUS_FUNC_SHIFT 2 -#define E1000_STATUS_FUNC_0 0x00000000 /* Function 0 */ #define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */ #define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */ -#define E1000_STATUS_TBIMODE 0x00000020 /* TBI mode */ -#define E1000_STATUS_SPEED_MASK 0x000000C0 +#define E1000_STATUS_SPEED_MASK 0x000000C0 #define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */ #define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */ #define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */ #define E1000_STATUS_LAN_INIT_DONE 0x00000200 /* Lan Init Compltn by NVM */ -#define E1000_STATUS_ASDV 0x00000300 /* Auto speed detect value */ #define E1000_STATUS_PHYRA 0x00000400 /* PHY Reset Asserted */ -/* Change in Dock/Undock state clear on write '0'. */ -#define E1000_STATUS_DOCK_CI 0x00000800 #define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Master request status */ -#define E1000_STATUS_MTXCKOK 0x00000400 /* MTX clock running OK */ #define E1000_STATUS_PCI66 0x00000800 /* In 66Mhz slot */ #define E1000_STATUS_BUS64 0x00001000 /* In 64 bit slot */ #define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */ #define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */ -#define E1000_STATUS_BMC_SKU_0 0x00100000 /* BMC USB redirect disbld */ -#define E1000_STATUS_BMC_SKU_1 0x00200000 /* BMC SRAM disabled */ -#define E1000_STATUS_BMC_SKU_2 0x00400000 /* BMC SDRAM disabled */ -#define E1000_STATUS_BMC_CRYPTO 0x00800000 /* BMC crypto disabled */ -/* BMC external code execution disabled */ -#define E1000_STATUS_BMC_LITE 0x01000000 -#define E1000_STATUS_RGMII_ENABLE 0x02000000 /* RGMII disabled */ -#define E1000_STATUS_FUSE_8 0x04000000 -#define E1000_STATUS_FUSE_9 0x08000000 -#define E1000_STATUS_SERDES0_DIS 0x10000000 /* SERDES disbld on port 0 */ -#define E1000_STATUS_SERDES1_DIS 0x20000000 /* SERDES disbld on port 1 */ /* Constants used to interpret the masked PCI-X bus speed. */ #define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus spd 50-66MHz */ @@ -578,8 +357,6 @@ ADVERTISE_100_FULL) #define E1000_ALL_100_SPEED (ADVERTISE_100_HALF | ADVERTISE_100_FULL) #define E1000_ALL_10_SPEED (ADVERTISE_10_HALF | ADVERTISE_10_FULL) -#define E1000_ALL_FULL_DUPLEX ( \ - ADVERTISE_10_FULL | ADVERTISE_100_FULL | ADVERTISE_1000_FULL) #define E1000_ALL_HALF_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_100_HALF) #define AUTONEG_ADVERTISE_SPEED_DEFAULT E1000_ALL_SPEED_DUPLEX @@ -587,51 +364,20 @@ /* LED Control */ #define E1000_PHY_LED0_MODE_MASK 0x00000007 #define E1000_PHY_LED0_IVRT 0x00000008 -#define E1000_PHY_LED0_BLINK 0x00000010 #define E1000_PHY_LED0_MASK 0x0000001F #define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F #define E1000_LEDCTL_LED0_MODE_SHIFT 0 -#define E1000_LEDCTL_LED0_BLINK_RATE 0x00000020 #define E1000_LEDCTL_LED0_IVRT 0x00000040 #define E1000_LEDCTL_LED0_BLINK 0x00000080 -#define E1000_LEDCTL_LED1_MODE_MASK 0x00000F00 -#define E1000_LEDCTL_LED1_MODE_SHIFT 8 -#define E1000_LEDCTL_LED1_BLINK_RATE 0x00002000 -#define E1000_LEDCTL_LED1_IVRT 0x00004000 -#define E1000_LEDCTL_LED1_BLINK 0x00008000 -#define E1000_LEDCTL_LED2_MODE_MASK 0x000F0000 -#define E1000_LEDCTL_LED2_MODE_SHIFT 16 -#define E1000_LEDCTL_LED2_BLINK_RATE 0x00200000 -#define E1000_LEDCTL_LED2_IVRT 0x00400000 -#define E1000_LEDCTL_LED2_BLINK 0x00800000 -#define E1000_LEDCTL_LED3_MODE_MASK 0x0F000000 -#define E1000_LEDCTL_LED3_MODE_SHIFT 24 -#define E1000_LEDCTL_LED3_BLINK_RATE 0x20000000 -#define E1000_LEDCTL_LED3_IVRT 0x40000000 -#define E1000_LEDCTL_LED3_BLINK 0x80000000 - -#define E1000_LEDCTL_MODE_LINK_10_1000 0x0 -#define E1000_LEDCTL_MODE_LINK_100_1000 0x1 + #define E1000_LEDCTL_MODE_LINK_UP 0x2 -#define E1000_LEDCTL_MODE_ACTIVITY 0x3 -#define E1000_LEDCTL_MODE_LINK_ACTIVITY 0x4 -#define E1000_LEDCTL_MODE_LINK_10 0x5 -#define E1000_LEDCTL_MODE_LINK_100 0x6 -#define E1000_LEDCTL_MODE_LINK_1000 0x7 -#define E1000_LEDCTL_MODE_PCIX_MODE 0x8 -#define E1000_LEDCTL_MODE_FULL_DUPLEX 0x9 -#define E1000_LEDCTL_MODE_COLLISION 0xA -#define E1000_LEDCTL_MODE_BUS_SPEED 0xB -#define E1000_LEDCTL_MODE_BUS_SIZE 0xC -#define E1000_LEDCTL_MODE_PAUSED 0xD #define E1000_LEDCTL_MODE_LED_ON 0xE #define E1000_LEDCTL_MODE_LED_OFF 0xF /* Transmit Descriptor bit definitions */ #define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */ #define E1000_TXD_DTYP_C 0x00000000 /* Context Descriptor */ -#define E1000_TXD_POPTS_SHIFT 8 /* POPTS shift */ #define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ #define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ #define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */ @@ -650,21 +396,14 @@ #define E1000_TXD_CMD_IP 0x02000000 /* IP packet */ #define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */ #define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */ -/* Extended desc bits for Linksec and timesync */ -#define E1000_TXD_CMD_LINKSEC 0x10000000 /* Apply LinkSec on packet */ #define E1000_TXD_EXTCMD_TSTAMP 0x00000010 /* IEEE1588 Timestamp packet */ /* Transmit Control */ -#define E1000_TCTL_RST 0x00000001 /* software reset */ #define E1000_TCTL_EN 0x00000002 /* enable Tx */ -#define E1000_TCTL_BCE 0x00000004 /* busy check enable */ #define E1000_TCTL_PSP 0x00000008 /* pad short packets */ #define E1000_TCTL_CT 0x00000ff0 /* collision threshold */ #define E1000_TCTL_COLD 0x003ff000 /* collision distance */ -#define E1000_TCTL_SWXOFF 0x00400000 /* SW Xoff transmission */ -#define E1000_TCTL_PBE 0x00800000 /* Packet Burst Enable */ #define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */ -#define E1000_TCTL_NRTU 0x02000000 /* No Re-transmit on underrun */ #define E1000_TCTL_MULR 0x10000000 /* Multiple request support */ /* Transmit Arbitration Count */ @@ -672,29 +411,19 @@ /* SerDes Control */ #define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400 +#define E1000_SCTL_ENABLE_SERDES_LOOPBACK 0x0410 /* Receive Checksum Control */ -#define E1000_RXCSUM_PCSS_MASK 0x000000FF /* Packet Checksum Start */ #define E1000_RXCSUM_IPOFL 0x00000100 /* IPv4 checksum offload */ #define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */ -#define E1000_RXCSUM_IPV6OFL 0x00000400 /* IPv6 checksum offload */ #define E1000_RXCSUM_CRCOFL 0x00000800 /* CRC32 offload enable */ #define E1000_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */ #define E1000_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */ /* Header split receive */ -#define E1000_RFCTL_ISCSI_DIS 0x00000001 -#define E1000_RFCTL_ISCSI_DWC_MASK 0x0000003E -#define E1000_RFCTL_ISCSI_DWC_SHIFT 1 #define E1000_RFCTL_NFSW_DIS 0x00000040 #define E1000_RFCTL_NFSR_DIS 0x00000080 -#define E1000_RFCTL_NFS_VER_MASK 0x00000300 -#define E1000_RFCTL_NFS_VER_SHIFT 8 -#define E1000_RFCTL_IPV6_DIS 0x00000400 -#define E1000_RFCTL_IPV6_XSUM_DIS 0x00000800 #define E1000_RFCTL_ACK_DIS 0x00001000 -#define E1000_RFCTL_ACKD_DIS 0x00002000 -#define E1000_RFCTL_IPFRSP_DIS 0x00004000 #define E1000_RFCTL_EXTEN 0x00008000 #define E1000_RFCTL_IPV6_EX_DIS 0x00010000 #define E1000_RFCTL_NEW_IPV6_EXT_DIS 0x00020000 @@ -712,8 +441,6 @@ #define DEFAULT_82543_TIPG_IPGT_COPPER 8 #define E1000_TIPG_IPGT_MASK 0x000003FF -#define E1000_TIPG_IPGR1_MASK 0x000FFC00 -#define E1000_TIPG_IPGR2_MASK 0x3FF00000 #define DEFAULT_82542_TIPG_IPGR1 2 #define DEFAULT_82543_TIPG_IPGR1 8 @@ -741,7 +468,6 @@ #define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK 0x0FFF0000 #define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT 16 -#define E1000_PHY_CTRL_SPD_EN 0x00000001 #define E1000_PHY_CTRL_D0A_LPLU 0x00000002 #define E1000_PHY_CTRL_NOND0A_LPLU 0x00000004 #define E1000_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008 @@ -749,8 +475,10 @@ #define E1000_KABGTXD_BGSQLBIAS 0x00050000 +/* Low Power IDLE Control */ +#define E1000_LPIC_LPIET_SHIFT 24 /* Low Power Idle Entry Time */ + /* PBA constants */ -#define E1000_PBA_6K 0x0006 /* 6KB */ #define E1000_PBA_8K 0x0008 /* 8KB */ #define E1000_PBA_10K 0x000A /* 10KB */ #define E1000_PBA_12K 0x000C /* 12KB */ @@ -770,10 +498,15 @@ #define E1000_PBA_48K 0x0030 /* 48KB */ #define E1000_PBA_64K 0x0040 /* 64KB */ -#define E1000_PBA_RXA_MASK 0xFFFF; +#define E1000_PBA_RXA_MASK 0xFFFF #define E1000_PBS_16K E1000_PBA_16K -#define E1000_PBS_24K E1000_PBA_24K + +/* Uncorrectable/correctable ECC Error counts and enable bits */ +#define E1000_PBECCSTS_CORR_ERR_CNT_MASK 0x000000FF +#define E1000_PBECCSTS_UNCORR_ERR_CNT_MASK 0x0000FF00 +#define E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT 8 +#define E1000_PBECCSTS_ECC_ENABLE 0x00010000 #define IFS_MAX 80 #define IFS_MIN 40 @@ -784,7 +517,6 @@ /* SW Semaphore Register */ #define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */ #define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */ -#define E1000_SWSM_WMNG 0x00000004 /* Wake MNG Clock */ #define E1000_SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */ #define E1000_SWSM2_LOCK 0x00000002 /* Secondary driver semaphore bit */ @@ -798,33 +530,19 @@ #define E1000_ICR_RXO 0x00000040 /* Rx overrun */ #define E1000_ICR_RXT0 0x00000080 /* Rx timer intr (ring 0) */ #define E1000_ICR_VMMB 0x00000100 /* VM MB event */ -#define E1000_ICR_MDAC 0x00000200 /* MDIO access complete */ #define E1000_ICR_RXCFG 0x00000400 /* Rx /c/ ordered set */ #define E1000_ICR_GPI_EN0 0x00000800 /* GP Int 0 */ #define E1000_ICR_GPI_EN1 0x00001000 /* GP Int 1 */ #define E1000_ICR_GPI_EN2 0x00002000 /* GP Int 2 */ #define E1000_ICR_GPI_EN3 0x00004000 /* GP Int 3 */ #define E1000_ICR_TXD_LOW 0x00008000 -#define E1000_ICR_SRPD 0x00010000 -#define E1000_ICR_ACK 0x00020000 /* Receive Ack frame */ #define E1000_ICR_MNG 0x00040000 /* Manageability event */ -#define E1000_ICR_DOCK 0x00080000 /* Dock/Undock */ +#define E1000_ICR_ECCER 0x00400000 /* Uncorrectable ECC Error */ +#define E1000_ICR_TS 0x00080000 /* Time Sync Interrupt */ #define E1000_ICR_DRSTA 0x40000000 /* Device Reset Asserted */ /* If this bit asserted, the driver should claim the interrupt */ #define E1000_ICR_INT_ASSERTED 0x80000000 -#define E1000_ICR_RXD_FIFO_PAR0 0x00100000 /* Q0 Rx desc FIFO parity error */ -#define E1000_ICR_TXD_FIFO_PAR0 0x00200000 /* Q0 Tx desc FIFO parity error */ -#define E1000_ICR_HOST_ARB_PAR 0x00400000 /* host arb read buffer parity err */ -#define E1000_ICR_PB_PAR 0x00800000 /* packet buffer parity error */ -#define E1000_ICR_RXD_FIFO_PAR1 0x01000000 /* Q1 Rx desc FIFO parity error */ -#define E1000_ICR_TXD_FIFO_PAR1 0x02000000 /* Q1 Tx desc FIFO parity error */ -#define E1000_ICR_ALL_PARITY 0x03F00000 /* all parity error bits */ -/* FW changed the status of DISSW bit in the FWSM */ -#define E1000_ICR_DSW 0x00000020 -/* LAN connected device generates an interrupt */ -#define E1000_ICR_PHYINT 0x00001000 #define E1000_ICR_DOUTSYNC 0x10000000 /* NIC DMA out of sync */ -#define E1000_ICR_EPRST 0x00100000 /* ME hardware reset occurs */ #define E1000_ICR_RXQ0 0x00100000 /* Rx Queue 0 Interrupt */ #define E1000_ICR_RXQ1 0x00200000 /* Rx Queue 1 Interrupt */ #define E1000_ICR_TXQ0 0x00400000 /* Tx Queue 0 Interrupt */ @@ -862,18 +580,7 @@ #define E1000_TCPTIMER_COUNT_FINISH 0x00000400 /* Count finish */ #define E1000_TCPTIMER_LOOP 0x00000800 /* Loop */ -/* - * This defines the bits that are set in the Interrupt Mask - * Set/Read Register. Each bit is documented below: - * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0) - * o RXSEQ = Receive Sequence Error - */ -#define POLL_IMS_ENABLE_MASK ( \ - E1000_IMS_RXDMT0 | \ - E1000_IMS_RXSEQ) - -/* - * This defines the bits that are set in the Interrupt Mask +/* This defines the bits that are set in the Interrupt Mask * Set/Read Register. Each bit is documented below: * o RXT0 = Receiver Timer Interrupt (ring 0) * o TXDW = Transmit Descriptor Written Back @@ -897,34 +604,11 @@ #define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* Rx desc min. threshold */ #define E1000_IMS_RXO E1000_ICR_RXO /* Rx overrun */ #define E1000_IMS_RXT0 E1000_ICR_RXT0 /* Rx timer intr */ -#define E1000_IMS_MDAC E1000_ICR_MDAC /* MDIO access complete */ -#define E1000_IMS_RXCFG E1000_ICR_RXCFG /* Rx /c/ ordered set */ -#define E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ -#define E1000_IMS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */ -#define E1000_IMS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */ -#define E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ #define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW -#define E1000_IMS_SRPD E1000_ICR_SRPD -#define E1000_IMS_ACK E1000_ICR_ACK /* Receive Ack frame */ -#define E1000_IMS_MNG E1000_ICR_MNG /* Manageability event */ -#define E1000_IMS_DOCK E1000_ICR_DOCK /* Dock/Undock */ +#define E1000_IMS_ECCER E1000_ICR_ECCER /* Uncorrectable ECC Error */ +#define E1000_IMS_TS E1000_ICR_TS /* Time Sync Interrupt */ #define E1000_IMS_DRSTA E1000_ICR_DRSTA /* Device Reset Asserted */ -/* Q0 Rx desc FIFO parity error */ -#define E1000_IMS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 -/* Q0 Tx desc FIFO parity error */ -#define E1000_IMS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 -/* host arb read buffer parity error */ -#define E1000_IMS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR -/* packet buffer parity error */ -#define E1000_IMS_PB_PAR E1000_ICR_PB_PAR -/* Q1 Rx desc FIFO parity error */ -#define E1000_IMS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 -/* Q1 Tx desc FIFO parity error */ -#define E1000_IMS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 -#define E1000_IMS_DSW E1000_ICR_DSW -#define E1000_IMS_PHYINT E1000_ICR_PHYINT #define E1000_IMS_DOUTSYNC E1000_ICR_DOUTSYNC /* NIC DMA out of sync */ -#define E1000_IMS_EPRST E1000_ICR_EPRST #define E1000_IMS_RXQ0 E1000_ICR_RXQ0 /* Rx Queue 0 Interrupt */ #define E1000_IMS_RXQ1 E1000_ICR_RXQ1 /* Rx Queue 1 Interrupt */ #define E1000_IMS_TXQ0 E1000_ICR_TXQ0 /* Tx Queue 0 Interrupt */ @@ -947,41 +631,9 @@ #define E1000_EIMS_OTHER E1000_EICR_OTHER /* Interrupt Cause Active */ /* Interrupt Cause Set */ -#define E1000_ICS_TXDW E1000_ICR_TXDW /* Tx desc written back */ -#define E1000_ICS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ #define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */ #define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* Rx sequence error */ #define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* Rx desc min. threshold */ -#define E1000_ICS_RXO E1000_ICR_RXO /* Rx overrun */ -#define E1000_ICS_RXT0 E1000_ICR_RXT0 /* Rx timer intr */ -#define E1000_ICS_MDAC E1000_ICR_MDAC /* MDIO access complete */ -#define E1000_ICS_RXCFG E1000_ICR_RXCFG /* Rx /c/ ordered set */ -#define E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ -#define E1000_ICS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */ -#define E1000_ICS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */ -#define E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ -#define E1000_ICS_TXD_LOW E1000_ICR_TXD_LOW -#define E1000_ICS_SRPD E1000_ICR_SRPD -#define E1000_ICS_ACK E1000_ICR_ACK /* Receive Ack frame */ -#define E1000_ICS_MNG E1000_ICR_MNG /* Manageability event */ -#define E1000_ICS_DOCK E1000_ICR_DOCK /* Dock/Undock */ -#define E1000_ICS_DRSTA E1000_ICR_DRSTA /* Device Reset Aserted */ -/* Q0 Rx desc FIFO parity error */ -#define E1000_ICS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 -/* Q0 Tx desc FIFO parity error */ -#define E1000_ICS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 -/* host arb read buffer parity error */ -#define E1000_ICS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR -/* packet buffer parity error */ -#define E1000_ICS_PB_PAR E1000_ICR_PB_PAR -/* Q1 Rx desc FIFO parity error */ -#define E1000_ICS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 -/* Q1 Tx desc FIFO parity error */ -#define E1000_ICS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 -#define E1000_ICS_DSW E1000_ICR_DSW -#define E1000_ICS_DOUTSYNC E1000_ICR_DOUTSYNC /* NIC DMA out of sync */ -#define E1000_ICS_PHYINT E1000_ICR_PHYINT -#define E1000_ICS_EPRST E1000_ICR_EPRST /* Extended Interrupt Cause Set */ #define E1000_EICS_RX_QUEUE0 E1000_EICR_RX_QUEUE0 /* Rx Queue 0 Interrupt */ @@ -1004,7 +656,6 @@ #define E1000_TXDCTL_HTHRESH 0x00003F00 /* TXDCTL Host Threshold */ #define E1000_TXDCTL_WTHRESH 0x003F0000 /* TXDCTL Writeback Threshold */ #define E1000_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */ -#define E1000_TXDCTL_LWTHRESH 0xFE000000 /* TXDCTL Low Threshold */ #define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */ #define E1000_TXDCTL_MAX_TX_DESC_PREFETCH 0x0100001F /* GRAN=1, PTHRESH=31 */ /* Enable the counting of descriptors still to be processed. */ @@ -1019,8 +670,7 @@ #define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMA'd) */ #define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */ -/* Receive Address */ -/* +/* Receive Address * Number of high/low register pairs in the RAR. The RAR (Receive Address * Registers) holds the directed and multicast addresses that we monitor. * Technically, we have 16 spots. However, we reserve one of these spots @@ -1032,8 +682,6 @@ #define E1000_RAL_MAC_ADDR_LEN 4 #define E1000_RAH_MAC_ADDR_LEN 2 #define E1000_RAH_QUEUE_MASK_82575 0x000C0000 -#define E1000_RAH_POOL_MASK 0x03FC0000 -#define E1000_RAH_POOL_SHIFT 18 #define E1000_RAH_POOL_1 0x00040000 /* Error Codes */ @@ -1073,30 +721,21 @@ /* Flow Control */ #define E1000_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */ -#define E1000_FCRTH_XFCE 0x80000000 /* External Flow Control Enable */ #define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */ #define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */ /* Transmit Configuration Word */ #define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */ -#define E1000_TXCW_HD 0x00000040 /* TXCW half duplex */ #define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */ #define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */ #define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */ -#define E1000_TXCW_RF 0x00003000 /* TXCW remote fault */ -#define E1000_TXCW_NP 0x00008000 /* TXCW next page */ -#define E1000_TXCW_CW 0x0000ffff /* TxConfigWord mask */ -#define E1000_TXCW_TXC 0x40000000 /* Transmit Config control */ #define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */ /* Receive Configuration Word */ #define E1000_RXCW_CW 0x0000ffff /* RxConfigWord mask */ -#define E1000_RXCW_NC 0x04000000 /* Receive config no carrier */ #define E1000_RXCW_IV 0x08000000 /* Receive config invalid */ -#define E1000_RXCW_CC 0x10000000 /* Receive config change */ #define E1000_RXCW_C 0x20000000 /* Receive config */ #define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */ -#define E1000_RXCW_ANC 0x80000000 /* Auto-neg complete */ #define E1000_TSYNCTXCTL_VALID 0x00000001 /* Tx timestamp valid */ #define E1000_TSYNCTXCTL_ENABLED 0x00000010 /* enable Tx timestamping */ @@ -1109,6 +748,13 @@ #define E1000_TSYNCRXCTL_TYPE_ALL 0x08 #define E1000_TSYNCRXCTL_TYPE_EVENT_V2 0x0A #define E1000_TSYNCRXCTL_ENABLED 0x00000010 /* enable Rx timestamping */ +#define E1000_TSYNCRXCTL_SYSCFI 0x00000020 /* Sys clock frequency */ + +#define E1000_RXMTRL_PTP_V1_SYNC_MESSAGE 0x00000000 +#define E1000_RXMTRL_PTP_V1_DELAY_REQ_MESSAGE 0x00010000 + +#define E1000_RXMTRL_PTP_V2_SYNC_MESSAGE 0x00000000 +#define E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE 0x01000000 #define E1000_TSYNCRXCFG_PTP_V1_CTRLT_MASK 0x000000FF #define E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE 0x00 @@ -1130,6 +776,11 @@ #define E1000_TSYNCRXCFG_PTP_V2_MANAGEMENT_MESSAGE 0x0D00 #define E1000_TIMINCA_16NS_SHIFT 24 +#define E1000_TIMINCA_INCPERIOD_SHIFT 24 +#define E1000_TIMINCA_INCVALUE_MASK 0x00FFFFFF + +#define E1000_TSICR_TXTS 0x00000002 +#define E1000_TSIM_TXTS 0x00000002 /* TUPLE Filtering Configuration */ #define E1000_TTQF_DISABLE_MASK 0xF0008000 /* TTQF Disable Mask */ #define E1000_TTQF_QUEUE_ENABLE 0x100 /* TTQF Queue Enable Bit */ @@ -1170,7 +821,7 @@ #define E1000_EEER_EEE_NEG 0x20000000 /* EEE capability nego */ #define E1000_EEER_RX_LPI_STATUS 0x40000000 /* Rx in LPI state */ #define E1000_EEER_TX_LPI_STATUS 0x80000000 /* Tx in LPI state */ - +#define E1000_EEE_SU_LPI_CLK_STP 0x00800000 /* EEE LPI Clock Stop */ /* PCI Express Control */ #define E1000_GCR_RXD_NO_SNOOP 0x00000001 #define E1000_GCR_RXDSCW_NO_SNOOP 0x00000002 @@ -1314,10 +965,6 @@ #define E1000_EECD_CS 0x00000002 /* NVM Chip Select */ #define E1000_EECD_DI 0x00000004 /* NVM Data In */ #define E1000_EECD_DO 0x00000008 /* NVM Data Out */ -#define E1000_EECD_FWE_MASK 0x00000030 -#define E1000_EECD_FWE_DIS 0x00000010 /* Disable FLASH writes */ -#define E1000_EECD_FWE_EN 0x00000020 /* Enable FLASH writes */ -#define E1000_EECD_FWE_SHIFT 4 #define E1000_EECD_REQ 0x00000040 /* NVM Access Request */ #define E1000_EECD_GNT 0x00000080 /* NVM Access Grant */ #define E1000_EECD_PRES 0x00000100 /* NVM Present */ @@ -1335,28 +982,28 @@ #define E1000_EECD_AUTO_RD 0x00000200 /* NVM Auto Read done */ #define E1000_EECD_SIZE_EX_MASK 0x00007800 /* NVM Size */ #define E1000_EECD_SIZE_EX_SHIFT 11 -#define E1000_EECD_NVADDS 0x00018000 /* NVM Address Size */ -#define E1000_EECD_SELSHAD 0x00020000 /* Select Shadow RAM */ -#define E1000_EECD_INITSRAM 0x00040000 /* Initialize Shadow RAM */ #define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */ #define E1000_EECD_AUPDEN 0x00100000 /* Ena Auto FLASH update */ -#define E1000_EECD_SHADV 0x00200000 /* Shadow RAM Data Valid */ #define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */ -#define E1000_EECD_SECVAL_SHIFT 22 #define E1000_EECD_SEC1VAL_VALID_MASK (E1000_EECD_AUTO_RD | E1000_EECD_PRES) #define E1000_EECD_FLUPD_I210 0x00800000 /* Update FLASH */ #define E1000_EECD_FLUDONE_I210 0x04000000 /* Update FLASH done */ #define E1000_EECD_FLASH_DETECTED_I210 0x00080000 /* FLASH detected */ +#define E1000_EECD_SEC1VAL_I210 0x02000000 /* Sector One Valid */ #define E1000_FLUDONE_ATTEMPTS 20000 #define E1000_EERD_EEWR_MAX_COUNT 512 /* buffered EEPROM words rw */ -#define E1000_I210_FIFO_SEL_RX 0x00 +#define E1000_I210_FIFO_SEL_RX 0x00 #define E1000_I210_FIFO_SEL_TX_QAV(_i) (0x02 + (_i)) #define E1000_I210_FIFO_SEL_TX_LEGACY E1000_I210_FIFO_SEL_TX_QAV(0) #define E1000_I210_FIFO_SEL_BMC2OS_TX 0x06 #define E1000_I210_FIFO_SEL_BMC2OS_RX 0x01 -#define E1000_NVM_SWDPIN0 0x0001 /* SWDPIN 0 NVM Value */ -#define E1000_NVM_LED_LOGIC 0x0020 /* Led Logic Word */ +#define E1000_I210_FLASH_SECTOR_SIZE 0x1000 /* 4KB FLASH sector unit size */ +/* Secure FLASH mode requires removing MSb */ +#define E1000_I210_FW_PTR_MASK 0x7FFF +/* Firmware code revision field word offset*/ +#define E1000_I210_FW_VER_OFFSET 328 + #define E1000_NVM_RW_REG_DATA 16 /* Offset to data in NVM read/write regs */ #define E1000_NVM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */ #define E1000_NVM_RW_REG_START 1 /* Start operation */ @@ -1368,13 +1015,11 @@ /* NVM Word Offsets */ #define NVM_COMPAT 0x0003 #define NVM_ID_LED_SETTINGS 0x0004 -#define NVM_VERSION 0x0005 #define NVM_SERDES_AMPLITUDE 0x0006 /* SERDES output amplitude */ #define NVM_PHY_CLASS_WORD 0x0007 -#define NVM_ETRACK_WORD 0x0042 -#define NVM_COMB_VER_OFF 0x0083 -#define NVM_COMB_VER_PTR 0x003d - +#define E1000_I210_NVM_FW_MODULE_PTR 0x0010 +#define E1000_I350_NVM_FW_MODULE_PTR 0x0051 +#define NVM_FUTURE_INIT_WORD1 0x0019 #define NVM_MAC_ADDR 0x0000 #define NVM_SUB_DEV_ID 0x000B #define NVM_SUB_VEN_ID 0x000C @@ -1385,15 +1030,15 @@ #define NVM_LED_1_CFG 0x001C #define NVM_LED_0_2_CFG 0x001F -#define NVM_INIT_CONTROL1_REG 0x000A +#define NVM_COMPAT_VALID_CSUM 0x0001 +#define NVM_FUTURE_INIT_WORD1_VALID_CSUM 0x0040 + #define NVM_INIT_CONTROL2_REG 0x000F -#define NVM_SWDEF_PINS_CTRL_PORT_1 0x0010 #define NVM_INIT_CONTROL3_PORT_B 0x0014 #define NVM_INIT_3GIO_3 0x001A #define NVM_SWDEF_PINS_CTRL_PORT_0 0x0020 #define NVM_INIT_CONTROL3_PORT_A 0x0024 #define NVM_CFG 0x0012 -#define NVM_FLASH_VERSION 0x0032 #define NVM_ALT_MAC_ADDR_PTR 0x0037 #define NVM_CHECKSUM_REG 0x003F #define NVM_COMPATIBILITY_REG_3 0x0003 @@ -1419,9 +1064,7 @@ #define NVM_WORD0F_PAUSE_MASK 0x3000 #define NVM_WORD0F_PAUSE 0x1000 #define NVM_WORD0F_ASM_DIR 0x2000 -#define NVM_WORD0F_ANE 0x0800 #define NVM_WORD0F_SWPDIO_EXT_MASK 0x00F0 -#define NVM_WORD0F_LPLU 0x0001 /* Mask bits for fields in Word 0x1a of the NVM */ #define NVM_WORD1A_ASPM_MASK 0x000C @@ -1435,7 +1078,7 @@ /* For checksumming, the sum of all words in the NVM should equal 0xBABA. */ #define NVM_SUM 0xBABA -#define NVM_MAC_ADDR_OFFSET 0 +/* PBA (printed board assembly) number words */ #define NVM_PBA_OFFSET_0 8 #define NVM_PBA_OFFSET_1 9 #define NVM_PBA_PTR_GUARD 0xFAFA @@ -1460,16 +1103,10 @@ #define NVM_WRITE_OPCODE_SPI 0x02 /* NVM write opcode */ #define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */ #define NVM_WREN_OPCODE_SPI 0x06 /* NVM set Write Enable latch */ -#define NVM_WRDI_OPCODE_SPI 0x04 /* NVM reset Write Enable latch */ #define NVM_RDSR_OPCODE_SPI 0x05 /* NVM read Status register */ -#define NVM_WRSR_OPCODE_SPI 0x01 /* NVM write Status register */ /* SPI NVM Status Register */ #define NVM_STATUS_RDY_SPI 0x01 -#define NVM_STATUS_WEN_SPI 0x02 -#define NVM_STATUS_BP0_SPI 0x04 -#define NVM_STATUS_BP1_SPI 0x08 -#define NVM_STATUS_WPEN_SPI 0x80 /* Word definitions for ID LED Settings */ #define ID_LED_RESERVED_0000 0x0000 @@ -1523,8 +1160,7 @@ #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */ #define MAX_PHY_MULTI_PAGE_REG 0xF -/* Bit definitions for valid PHY IDs. */ -/* +/* Bit definitions for valid PHY IDs. * I = Integrated * E = External */ @@ -1532,7 +1168,6 @@ #define M88E1000_I_PHY_ID 0x01410C30 #define M88E1011_I_PHY_ID 0x01410C20 #define IGP01E1000_I_PHY_ID 0x02A80380 -#define M88E1011_I_REV_4 0x04 #define M88E1111_I_PHY_ID 0x01410CC0 #define M88E1112_E_PHY_ID 0x01410C90 #define I347AT4_E_PHY_ID 0x01410DC0 @@ -1547,6 +1182,7 @@ #define I82577_E_PHY_ID 0x01540050 #define I82578_E_PHY_ID 0x004DD040 #define I82579_E_PHY_ID 0x01540090 +#define I217_E_PHY_ID 0x015400A0 #define I82580_I_PHY_ID 0x015403A0 #define I350_I_PHY_ID 0x015403B0 #define I210_I_PHY_ID 0x01410C00 @@ -1556,8 +1192,6 @@ /* M88E1000 Specific Registers */ #define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Reg */ #define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Reg */ -#define M88E1000_INT_ENABLE 0x12 /* Interrupt Enable Reg */ -#define M88E1000_INT_STATUS 0x13 /* Interrupt Status Reg */ #define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Cntrl */ #define M88E1000_RX_ERR_CNTR 0x15 /* Receive Error Counter */ @@ -1568,11 +1202,7 @@ #define M88E1000_PHY_VCO_REG_BIT11 0x800 /* improved BER performance */ /* M88E1000 PHY Specific Control Register */ -#define M88E1000_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */ #define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reverse enabled */ -#define M88E1000_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */ -/* 1=CLK125 low, 0=CLK125 toggling */ -#define M88E1000_PSCR_CLK125_DISABLE 0x0010 /* MDI Crossover Mode bits 6:5 Manual MDI configuration */ #define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 #define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */ @@ -1580,24 +1210,13 @@ #define M88E1000_PSCR_AUTO_X_1000T 0x0040 /* Auto crossover enabled all speeds */ #define M88E1000_PSCR_AUTO_X_MODE 0x0060 -/* - * 1=Enable Extended 10BASE-T distance (Lower 10BASE-T Rx Threshold - * 0=Normal 10BASE-T Rx Threshold - */ -#define M88E1000_PSCR_EN_10BT_EXT_DIST 0x0080 -/* 1=5-bit interface in 100BASE-TX, 0=MII interface in 100BASE-TX */ -#define M88E1000_PSCR_MII_5BIT_ENABLE 0x0100 -#define M88E1000_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler disable */ -#define M88E1000_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */ #define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Tx */ /* M88E1000 PHY Specific Status Register */ -#define M88E1000_PSSR_JABBER 0x0001 /* 1=Jabber */ #define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */ #define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */ #define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */ -/* - * 0 = <50M +/* 0 = <50M * 1 = 50-80M * 2 = 80-110M * 3 = 110-140M @@ -1606,64 +1225,33 @@ #define M88E1000_PSSR_CABLE_LENGTH 0x0380 #define M88E1000_PSSR_LINK 0x0400 /* 1=Link up, 0=Link down */ #define M88E1000_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */ -#define M88E1000_PSSR_PAGE_RCVD 0x1000 /* 1=Page received */ #define M88E1000_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */ #define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */ -#define M88E1000_PSSR_10MBS 0x0000 /* 00=10Mbs */ #define M88E1000_PSSR_100MBS 0x4000 /* 01=100Mbs */ #define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */ #define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7 -/* M88E1000 Extended PHY Specific Control Register */ -#define M88E1000_EPSCR_FIBER_LOOPBACK 0x4000 /* 1=Fiber loopback */ -/* - * 1 = Lost lock detect enabled. - * Will assert lost lock and bring - * link down if idle not seen - * within 1ms in 1000BASE-T - */ -#define M88E1000_EPSCR_DOWN_NO_IDLE 0x8000 -/* - * Number of times we will attempt to autonegotiate before downshifting if we +/* Number of times we will attempt to autonegotiate before downshifting if we * are the master */ #define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000 -#define M88E1000_EPSCR_MASTER_DOWNSHIFT_2X 0x0400 -#define M88E1000_EPSCR_MASTER_DOWNSHIFT_3X 0x0800 -#define M88E1000_EPSCR_MASTER_DOWNSHIFT_4X 0x0C00 -/* - * Number of times we will attempt to autonegotiate before downshifting if we +/* Number of times we will attempt to autonegotiate before downshifting if we * are the slave */ #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300 -#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_DIS 0x0000 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100 -#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_2X 0x0200 -#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_3X 0x0300 -#define M88E1000_EPSCR_TX_CLK_2_5 0x0060 /* 2.5 MHz TX_CLK */ #define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */ -#define M88E1000_EPSCR_TX_CLK_0 0x0000 /* NO TX_CLK */ - -/* M88E1111 Specific Registers */ -#define M88E1111_PHY_PAGE_SELECT1 0x16 /* for registers 0-28 */ -#define M88E1111_PHY_PAGE_SELECT2 0x1D /* for registers 30-31 */ - -/* M88E1111 page select register mask */ -#define M88E1111_PHY_PAGE_SELECT_MASK1 0xFF -#define M88E1111_PHY_PAGE_SELECT_MASK2 0x3F /* Intel I347AT4 Registers */ - #define I347AT4_PCDL 0x10 /* PHY Cable Diagnostics Length */ #define I347AT4_PCDC 0x15 /* PHY Cable Diagnostics Control */ #define I347AT4_PAGE_SELECT 0x16 /* I347AT4 Extended PHY Specific Control Register */ -/* - * Number of times we will attempt to autonegotiate before downshifting if we +/* Number of times we will attempt to autonegotiate before downshifting if we * are the master */ #define I347AT4_PSCR_DOWNSHIFT_ENABLE 0x0800 @@ -1685,14 +1273,7 @@ /* M88EC018 Rev 2 specific DownShift settings */ #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00 -#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_1X 0x0000 -#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_2X 0x0200 -#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_3X 0x0400 -#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_4X 0x0600 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800 -#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_6X 0x0A00 -#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_7X 0x0C00 -#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_8X 0x0E00 #define I82578_EPSCR_DOWNSHIFT_ENABLE 0x0020 #define I82578_EPSCR_DOWNSHIFT_COUNTER_MASK 0x001C @@ -1700,8 +1281,7 @@ /* BME1000 PHY Specific Control Register */ #define BME1000_PSCR_ENABLE_DOWNSHIFT 0x0800 /* 1 = enable downshift */ -/* - * Bits... +/* Bits... * 15-5: page * 4-0: register offset */ @@ -1712,49 +1292,24 @@ /* GG82563 Specific Registers */ #define GG82563_PHY_SPEC_CTRL GG82563_REG(0, 16) /* PHY Spec Cntrl */ -#define GG82563_PHY_SPEC_STATUS GG82563_REG(0, 17) /* PHY Spec Status */ -#define GG82563_PHY_INT_ENABLE GG82563_REG(0, 18) /* Interrupt Ena */ -#define GG82563_PHY_SPEC_STATUS_2 GG82563_REG(0, 19) /* PHY Spec Stat2 */ -#define GG82563_PHY_RX_ERR_CNTR GG82563_REG(0, 21) /* Rx Err Counter */ #define GG82563_PHY_PAGE_SELECT GG82563_REG(0, 22) /* Page Select */ #define GG82563_PHY_SPEC_CTRL_2 GG82563_REG(0, 26) /* PHY Spec Cntrl2 */ #define GG82563_PHY_PAGE_SELECT_ALT GG82563_REG(0, 29) /* Alt Page Select */ -/* Test Clock Control (use reg. 29 to select) */ -#define GG82563_PHY_TEST_CLK_CTRL GG82563_REG(0, 30) /* MAC Specific Control Register */ #define GG82563_PHY_MAC_SPEC_CTRL GG82563_REG(2, 21) -#define GG82563_PHY_MAC_SPEC_CTRL_2 GG82563_REG(2, 26) /* MAC Spec Ctrl 2 */ #define GG82563_PHY_DSP_DISTANCE GG82563_REG(5, 26) /* DSP Distance */ /* Page 193 - Port Control Registers */ /* Kumeran Mode Control */ #define GG82563_PHY_KMRN_MODE_CTRL GG82563_REG(193, 16) -#define GG82563_PHY_PORT_RESET GG82563_REG(193, 17) /* Port Reset */ -#define GG82563_PHY_REVISION_ID GG82563_REG(193, 18) /* Revision ID */ -#define GG82563_PHY_DEVICE_ID GG82563_REG(193, 19) /* Device ID */ #define GG82563_PHY_PWR_MGMT_CTRL GG82563_REG(193, 20) /* Pwr Mgt Ctrl */ -/* Rate Adaptation Control */ -#define GG82563_PHY_RATE_ADAPT_CTRL GG82563_REG(193, 25) /* Page 194 - KMRN Registers */ -/* FIFO's Control/Status */ -#define GG82563_PHY_KMRN_FIFO_CTRL_STAT GG82563_REG(194, 16) -#define GG82563_PHY_KMRN_CTRL GG82563_REG(194, 17) /* Control */ #define GG82563_PHY_INBAND_CTRL GG82563_REG(194, 18) /* Inband Ctrl */ -#define GG82563_PHY_KMRN_DIAGNOSTIC GG82563_REG(194, 19) /* Diagnostic */ -#define GG82563_PHY_ACK_TIMEOUTS GG82563_REG(194, 20) /* Ack Timeouts */ -#define GG82563_PHY_ADV_ABILITY GG82563_REG(194, 21) /* Adver Ability */ -/* Link Partner Advertised Ability */ -#define GG82563_PHY_LINK_PARTNER_ADV_ABILITY GG82563_REG(194, 23) -#define GG82563_PHY_ADV_NEXT_PAGE GG82563_REG(194, 24) /* Adver Next Pg */ -/* Link Partner Advertised Next page */ -#define GG82563_PHY_LINK_PARTNER_ADV_NEXT_PAGE GG82563_REG(194, 25) -#define GG82563_PHY_KMRN_MISC GG82563_REG(194, 26) /* Misc. */ /* MDI Control */ -#define E1000_MDIC_DATA_MASK 0x0000FFFF #define E1000_MDIC_REG_MASK 0x001F0000 #define E1000_MDIC_REG_SHIFT 16 #define E1000_MDIC_PHY_MASK 0x03E00000 @@ -1762,7 +1317,6 @@ #define E1000_MDIC_OP_WRITE 0x04000000 #define E1000_MDIC_OP_READ 0x08000000 #define E1000_MDIC_READY 0x10000000 -#define E1000_MDIC_INT_EN 0x20000000 #define E1000_MDIC_ERROR 0x40000000 #define E1000_MDIC_DEST 0x80000000 @@ -1834,38 +1388,13 @@ /* Lx power decision based on DMA coal */ #define E1000_PCIEMISC_LX_DECISION 0x00000080 +#define E1000_RXPBS_CFG_TS_EN 0x80000000 /* Timestamp in Rx buffer */ #define E1000_RXPBS_SIZE_I210_MASK 0x0000003F /* Rx packet buffer size */ #define E1000_TXPB0S_SIZE_I210_MASK 0x0000003F /* Tx packet buffer 0 size */ -#define E1000_LTRC_EEEMS_EN 0x00000020 /* Enable EEE LTR max send */ -/* Minimum time for 1000BASE-T where no data will be transmit following move out - * of EEE LPI Tx state - */ -#define E1000_TW_SYSTEM_1000_MASK 0x000000FF -/* Minimum time for 100BASE-T where no data will be transmit following move out - * of EEE LPI Tx state - */ -#define E1000_TW_SYSTEM_100_MASK 0x0000FF00 -#define E1000_TW_SYSTEM_100_SHIFT 8 -#define E1000_LTRMINV_LTRV_MASK 0x000003FF /* LTR minimum value */ -#define E1000_LTRMAXV_LTRV_MASK 0x000003FF /* LTR maximum value */ -#define E1000_LTRMINV_SCALE_MASK 0x00001C00 /* LTR minimum scale */ -#define E1000_LTRMINV_SCALE_SHIFT 10 -/* Reg val to set scale to 1024 nsec */ -#define E1000_LTRMINV_SCALE_1024 2 -/* Reg val to set scale to 32768 nsec */ -#define E1000_LTRMINV_SCALE_32768 3 -#define E1000_LTRMINV_LSNP_REQ 0x00008000 /* LTR Snoop Requirement */ -#define E1000_LTRMAXV_SCALE_MASK 0x00001C00 /* LTR maximum scale */ -#define E1000_LTRMAXV_SCALE_SHIFT 10 -/* Reg val to set scale to 1024 nsec */ -#define E1000_LTRMAXV_SCALE_1024 2 -/* Reg val to set scale to 32768 nsec */ -#define E1000_LTRMAXV_SCALE_32768 3 -#define E1000_LTRMAXV_LSNP_REQ 0x00008000 /* LTR Snoop Requirement */ #define E1000_DOBFFCTL_OBFFTHR_MASK 0x000000FF /* OBFF threshold */ #define E1000_DOBFFCTL_EXIT_ACT_MASK 0x01000000 /* Exit active CB */ -/* Proxy Filer Control */ +/* Proxy Filter Control */ #define E1000_PROXYFC_D0 0x00000001 /* Enable offload in D0 */ #define E1000_PROXYFC_EX 0x00000004 /* Directed exact proxy */ #define E1000_PROXYFC_MC 0x00000008 /* Directed MC Proxy */ @@ -1873,7 +1402,7 @@ #define E1000_PROXYFC_ARP_DIRECTED 0x00000020 /* Directed ARP Proxy Ena */ #define E1000_PROXYFC_IPV4 0x00000040 /* Directed IPv4 Enable */ #define E1000_PROXYFC_IPV6 0x00000080 /* Directed IPv6 Enable */ -#define E1000_PROXYFC_NS 0x00000200 /* IPv4 NBRHD Solicitation */ +#define E1000_PROXYFC_NS 0x00000200 /* IPv6 Neighbor Solicitation */ #define E1000_PROXYFC_ARP 0x00000800 /* ARP Request Proxy Ena */ /* Proxy Status */ #define E1000_PROXYS_CLEAR 0xFFFFFFFF /* Clear */ diff --git a/sys/dev/e1000/e1000_hw.h b/sys/dev/e1000/e1000_hw.h index 50a5ce2..e8a8c17 100644 --- a/sys/dev/e1000/e1000_hw.h +++ b/sys/dev/e1000/e1000_hw.h @@ -1,6 +1,6 @@ /****************************************************************************** - Copyright (c) 2001-2012, Intel Corporation + Copyright (c) 2001-2013, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without @@ -123,13 +123,16 @@ struct e1000_hw; #define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE #define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF #define E1000_DEV_ID_ICH10_D_BM_V 0x1525 - #define E1000_DEV_ID_PCH_M_HV_LM 0x10EA #define E1000_DEV_ID_PCH_M_HV_LC 0x10EB #define E1000_DEV_ID_PCH_D_HV_DM 0x10EF #define E1000_DEV_ID_PCH_D_HV_DC 0x10F0 #define E1000_DEV_ID_PCH2_LV_LM 0x1502 #define E1000_DEV_ID_PCH2_LV_V 0x1503 +#define E1000_DEV_ID_PCH_LPT_I217_LM 0x153A +#define E1000_DEV_ID_PCH_LPT_I217_V 0x153B +#define E1000_DEV_ID_PCH_LPTLP_I218_LM 0x155A +#define E1000_DEV_ID_PCH_LPTLP_I218_V 0x1559 #define E1000_DEV_ID_82576 0x10C9 #define E1000_DEV_ID_82576_FIBER 0x10E6 #define E1000_DEV_ID_82576_SERDES 0x10E7 @@ -139,7 +142,9 @@ struct e1000_hw; #define E1000_DEV_ID_82576_NS_SERDES 0x1518 #define E1000_DEV_ID_82576_SERDES_QUAD 0x150D #define E1000_DEV_ID_82576_VF 0x10CA +#define E1000_DEV_ID_82576_VF_HV 0x152D #define E1000_DEV_ID_I350_VF 0x1520 +#define E1000_DEV_ID_I350_VF_HV 0x152F #define E1000_DEV_ID_82575EB_COPPER 0x10A7 #define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9 #define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6 @@ -165,6 +170,7 @@ struct e1000_hw; #define E1000_DEV_ID_DH89XXCC_SERDES 0x043A #define E1000_DEV_ID_DH89XXCC_BACKPLANE 0x043C #define E1000_DEV_ID_DH89XXCC_SFP 0x0440 + #define E1000_REVISION_0 0 #define E1000_REVISION_1 1 #define E1000_REVISION_2 2 @@ -206,6 +212,7 @@ enum e1000_mac_type { e1000_ich10lan, e1000_pchlan, e1000_pch2lan, + e1000_pch_lpt, e1000_82575, e1000_82576, e1000_82580, @@ -255,6 +262,7 @@ enum e1000_phy_type { e1000_phy_82578, e1000_phy_82577, e1000_phy_82579, + e1000_phy_i217, e1000_phy_82580, e1000_phy_vf, e1000_phy_i210, @@ -651,13 +659,13 @@ struct e1000_host_mng_command_info { #include "e1000_manage.h" #include "e1000_mbx.h" +/* Function pointers for the MAC. */ struct e1000_mac_operations { - /* Function pointers for the MAC. */ s32 (*init_params)(struct e1000_hw *); s32 (*id_led_init)(struct e1000_hw *); s32 (*blink_led)(struct e1000_hw *); + bool (*check_mng_mode)(struct e1000_hw *); s32 (*check_for_link)(struct e1000_hw *); - bool (*check_mng_mode)(struct e1000_hw *hw); s32 (*cleanup_led)(struct e1000_hw *); void (*clear_hw_cntrs)(struct e1000_hw *); void (*clear_vfta)(struct e1000_hw *); @@ -679,17 +687,12 @@ struct e1000_mac_operations { void (*rar_set)(struct e1000_hw *, u8*, u32); s32 (*read_mac_addr)(struct e1000_hw *); s32 (*validate_mdi_setting)(struct e1000_hw *); - s32 (*mng_host_if_write)(struct e1000_hw *, u8*, u16, u16, u8*); - s32 (*mng_write_cmd_header)(struct e1000_hw *hw, - struct e1000_host_mng_command_header*); - s32 (*mng_enable_host_if)(struct e1000_hw *); - s32 (*wait_autoneg)(struct e1000_hw *); + s32 (*set_obff_timer)(struct e1000_hw *, u32); s32 (*acquire_swfw_sync)(struct e1000_hw *, u16); void (*release_swfw_sync)(struct e1000_hw *, u16); }; -/* - * When to use various PHY register access functions: +/* When to use various PHY register access functions: * * Func Caller * Function Does Does When to use @@ -731,6 +734,7 @@ struct e1000_phy_operations { s32 (*write_i2c_byte)(struct e1000_hw *, u8, u8, u8); }; +/* Function pointers for the NVM. */ struct e1000_nvm_operations { s32 (*init_params)(struct e1000_hw *); s32 (*acquire)(struct e1000_hw *); @@ -785,6 +789,7 @@ struct e1000_mac_info { enum e1000_serdes_link_state serdes_link_state; bool serdes_has_link; bool tx_pkt_filtering; + u32 max_frame_size; }; struct e1000_phy_info { @@ -915,7 +920,7 @@ struct e1000_shadow_ram { bool modified; }; -#define E1000_SHADOW_RAM_WORDS 2048 +#define E1000_SHADOW_RAM_WORDS 2048 struct e1000_dev_spec_ich8lan { bool kmrn_lock_loss_workaround_enabled; @@ -924,6 +929,7 @@ struct e1000_dev_spec_ich8lan { E1000_MUTEX swflag_mutex; bool nvm_k1_enabled; bool eee_disable; + u16 eee_lp_ability; }; struct e1000_dev_spec_82575 { @@ -931,7 +937,9 @@ struct e1000_dev_spec_82575 { bool global_device_reset; bool eee_disable; bool module_plugged; + bool clear_semaphore_once; u32 mtu; + struct sfp_e1000_flags eth_flags; }; struct e1000_dev_spec_vf { diff --git a/sys/dev/e1000/e1000_i210.c b/sys/dev/e1000/e1000_i210.c index f8e8bad..63302c0 100644 --- a/sys/dev/e1000/e1000_i210.c +++ b/sys/dev/e1000/e1000_i210.c @@ -1,6 +1,6 @@ /****************************************************************************** - Copyright (c) 2001-2012, Intel Corporation + Copyright (c) 2001-2013, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without @@ -38,7 +38,6 @@ static s32 e1000_acquire_nvm_i210(struct e1000_hw *hw); static void e1000_release_nvm_i210(struct e1000_hw *hw); static s32 e1000_get_hw_semaphore_i210(struct e1000_hw *hw); -static void e1000_put_hw_semaphore_i210(struct e1000_hw *hw); static s32 e1000_write_nvm_srwr(struct e1000_hw *hw, u16 offset, u16 words, u16 *data); static s32 e1000_pool_flash_update_done_i210(struct e1000_hw *hw); @@ -105,13 +104,14 @@ s32 e1000_acquire_swfw_sync_i210(struct e1000_hw *hw, u16 mask) } swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC); - if (!(swfw_sync & fwmask)) + if (!(swfw_sync & (fwmask | swmask))) break; /* * Firmware currently using resource (fwmask) + * or other software thread using resource (swmask) */ - e1000_put_hw_semaphore_i210(hw); + e1000_put_hw_semaphore_generic(hw); msec_delay_irq(5); i++; } @@ -125,7 +125,7 @@ s32 e1000_acquire_swfw_sync_i210(struct e1000_hw *hw, u16 mask) swfw_sync |= swmask; E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync); - e1000_put_hw_semaphore_i210(hw); + e1000_put_hw_semaphore_generic(hw); out: return ret_val; @@ -152,7 +152,7 @@ void e1000_release_swfw_sync_i210(struct e1000_hw *hw, u16 mask) swfw_sync &= ~mask; E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync); - e1000_put_hw_semaphore_i210(hw); + e1000_put_hw_semaphore_generic(hw); } /** @@ -164,12 +164,45 @@ void e1000_release_swfw_sync_i210(struct e1000_hw *hw, u16 mask) static s32 e1000_get_hw_semaphore_i210(struct e1000_hw *hw) { u32 swsm; - s32 ret_val = E1000_SUCCESS; s32 timeout = hw->nvm.word_size + 1; s32 i = 0; DEBUGFUNC("e1000_get_hw_semaphore_i210"); + /* Get the SW semaphore */ + while (i < timeout) { + swsm = E1000_READ_REG(hw, E1000_SWSM); + if (!(swsm & E1000_SWSM_SMBI)) + break; + + usec_delay(50); + i++; + } + + if (i == timeout) { + /* + * In rare circumstances, the driver may not have released the + * SW semaphore. Clear the semaphore once before giving up. + */ + if (hw->dev_spec._82575.clear_semaphore_once) { + hw->dev_spec._82575.clear_semaphore_once = FALSE; + e1000_put_hw_semaphore_generic(hw); + for (i = 0; i < timeout; i++) { + swsm = E1000_READ_REG(hw, E1000_SWSM); + if (!(swsm & E1000_SWSM_SMBI)) + break; + + usec_delay(50); + } + } + + /* If we do not have the semaphore here, we have to give up. */ + if (i == timeout) { + DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); + return -E1000_ERR_NVM; + } + } + /* Get the FW semaphore. */ for (i = 0; i < timeout; i++) { swsm = E1000_READ_REG(hw, E1000_SWSM); @@ -186,31 +219,10 @@ static s32 e1000_get_hw_semaphore_i210(struct e1000_hw *hw) /* Release semaphores */ e1000_put_hw_semaphore_generic(hw); DEBUGOUT("Driver can't access the NVM\n"); - ret_val = -E1000_ERR_NVM; - goto out; + return -E1000_ERR_NVM; } -out: - return ret_val; -} - -/** - * e1000_put_hw_semaphore_i210 - Release hardware semaphore - * @hw: pointer to the HW structure - * - * Release hardware semaphore used to access the PHY or NVM - **/ -static void e1000_put_hw_semaphore_i210(struct e1000_hw *hw) -{ - u32 swsm; - - DEBUGFUNC("e1000_put_hw_semaphore_i210"); - - swsm = E1000_READ_REG(hw, E1000_SWSM); - - swsm &= ~E1000_SWSM_SWESMBI; - - E1000_WRITE_REG(hw, E1000_SWSM, swsm); + return E1000_SUCCESS; } /** @@ -364,8 +376,8 @@ out: * * Wrapper function to return data formerly found in the NVM. **/ -static s32 e1000_read_nvm_i211(struct e1000_hw *hw, u16 offset, u16 words, - u16 *data) +static s32 e1000_read_nvm_i211(struct e1000_hw *hw, u16 offset, + u16 words, u16 *data) { s32 ret_val = E1000_SUCCESS; @@ -380,15 +392,40 @@ static s32 e1000_read_nvm_i211(struct e1000_hw *hw, u16 offset, u16 words, if (ret_val != E1000_SUCCESS) DEBUGOUT("MAC Addr not found in iNVM\n"); break; - case NVM_ID_LED_SETTINGS: case NVM_INIT_CTRL_2: + ret_val = e1000_read_invm_i211(hw, (u8)offset, data); + if (ret_val != E1000_SUCCESS) { + *data = NVM_INIT_CTRL_2_DEFAULT_I211; + ret_val = E1000_SUCCESS; + } + break; case NVM_INIT_CTRL_4: + ret_val = e1000_read_invm_i211(hw, (u8)offset, data); + if (ret_val != E1000_SUCCESS) { + *data = NVM_INIT_CTRL_4_DEFAULT_I211; + ret_val = E1000_SUCCESS; + } + break; case NVM_LED_1_CFG: + ret_val = e1000_read_invm_i211(hw, (u8)offset, data); + if (ret_val != E1000_SUCCESS) { + *data = NVM_LED_1_CFG_DEFAULT_I211; + ret_val = E1000_SUCCESS; + } + break; case NVM_LED_0_2_CFG: - e1000_read_invm_i211(hw, (u8)offset, data); + ret_val = e1000_read_invm_i211(hw, (u8)offset, data); + if (ret_val != E1000_SUCCESS) { + *data = NVM_LED_0_2_CFG_DEFAULT_I211; + ret_val = E1000_SUCCESS; + } break; - case NVM_COMPAT: - *data = ID_LED_DEFAULT_I210; + case NVM_ID_LED_SETTINGS: + ret_val = e1000_read_invm_i211(hw, (u8)offset, data); + if (ret_val != E1000_SUCCESS) { + *data = ID_LED_RESERVED_FFFF; + ret_val = E1000_SUCCESS; + } break; case NVM_SUB_DEV_ID: *data = hw->subsystem_device_id; @@ -555,26 +592,6 @@ out: } /** - * e1000_get_flash_presence_i210 - Check if flash device is detected. - * @hw: pointer to the HW structure - * - **/ -static bool e1000_get_flash_presence_i210(struct e1000_hw *hw) -{ - u32 eec = 0; - bool ret_val = FALSE; - - DEBUGFUNC("e1000_get_flash_presence_i210"); - - eec = E1000_READ_REG(hw, E1000_EECD); - - if (eec & E1000_EECD_FLASH_DETECTED_I210) - ret_val = TRUE; - - return ret_val; -} - -/** * e1000_update_flash_i210 - Commit EEPROM to the flash * @hw: pointer to the HW structure * @@ -690,10 +707,7 @@ void e1000_init_function_pointers_i210(struct e1000_hw *hw) switch (hw->mac.type) { case e1000_i210: - if (e1000_get_flash_presence_i210(hw)) - hw->nvm.ops.init_params = e1000_init_nvm_params_i210; - else - hw->nvm.ops.init_params = e1000_init_nvm_params_i211; + hw->nvm.ops.init_params = e1000_init_nvm_params_i210; break; case e1000_i211: hw->nvm.ops.init_params = e1000_init_nvm_params_i211; diff --git a/sys/dev/e1000/e1000_i210.h b/sys/dev/e1000/e1000_i210.h index a0cd935..d7711fe 100644 --- a/sys/dev/e1000/e1000_i210.h +++ b/sys/dev/e1000/e1000_i210.h @@ -1,6 +1,6 @@ /****************************************************************************** - Copyright (c) 2001-2012, Intel Corporation + Copyright (c) 2001-2013, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without @@ -43,8 +43,6 @@ s32 e1000_write_nvm_srwr_i210(struct e1000_hw *hw, u16 offset, s32 e1000_read_nvm_srrd_i210(struct e1000_hw *hw, u16 offset, u16 words, u16 *data); s32 e1000_read_invm_i211(struct e1000_hw *hw, u8 address, u16 *data); -s32 e1000_check_for_copper_link_i210(struct e1000_hw *hw); -s32 e1000_set_ltr_i210(struct e1000_hw *hw, bool link); s32 e1000_acquire_swfw_sync_i210(struct e1000_hw *hw, u16 mask); void e1000_release_swfw_sync_i210(struct e1000_hw *hw, u16 mask); @@ -69,6 +67,15 @@ enum E1000_INVM_STRUCTURE_TYPE { #define E1000_INVM_RSA_KEY_SHA256_DATA_SIZE_IN_DWORDS 8 #define E1000_INVM_CSR_AUTOLOAD_DATA_SIZE_IN_DWORDS 1 +#define E1000_INVM_ULT_BYTES_SIZE 8 +#define E1000_INVM_RECORD_SIZE_IN_BYTES 4 +#define E1000_INVM_VER_FIELD_ONE 0x1FF8 +#define E1000_INVM_VER_FIELD_TWO 0x7FE000 +#define E1000_INVM_IMGTYPE_FIELD 0x1F800000 + +#define E1000_INVM_MAJOR_MASK 0x3F0 +#define E1000_INVM_MINOR_MASK 0xF +#define E1000_INVM_MAJOR_SHIFT 4 #define ID_LED_DEFAULT_I210 ((ID_LED_OFF1_ON2 << 8) | \ (ID_LED_DEF1_DEF2 << 4) | \ @@ -77,4 +84,9 @@ enum E1000_INVM_STRUCTURE_TYPE { (ID_LED_DEF1_DEF2 << 4) | \ (ID_LED_DEF1_DEF2)) +/* NVM offset defaults for I211 devices */ +#define NVM_INIT_CTRL_2_DEFAULT_I211 0X7243 +#define NVM_INIT_CTRL_4_DEFAULT_I211 0x00C1 +#define NVM_LED_1_CFG_DEFAULT_I211 0x0184 +#define NVM_LED_0_2_CFG_DEFAULT_I211 0x200C #endif diff --git a/sys/dev/e1000/e1000_ich8lan.c b/sys/dev/e1000/e1000_ich8lan.c index 906ce85..bd94355 100644 --- a/sys/dev/e1000/e1000_ich8lan.c +++ b/sys/dev/e1000/e1000_ich8lan.c @@ -1,6 +1,6 @@ /****************************************************************************** - Copyright (c) 2001-2011, Intel Corporation + Copyright (c) 2001-2013, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without @@ -32,8 +32,7 @@ ******************************************************************************/ /*$FreeBSD$*/ -/* - * 82562G 10/100 Network Connection +/* 82562G 10/100 Network Connection * 82562G-2 10/100 Network Connection * 82562GT 10/100 Network Connection * 82562GT-2 10/100 Network Connection @@ -64,10 +63,6 @@ #include "e1000_api.h" -static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw); -static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw); -static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw); -static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw); static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw); static void e1000_release_swflag_ich8lan(struct e1000_hw *hw); static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw); @@ -75,6 +70,7 @@ static void e1000_release_nvm_ich8lan(struct e1000_hw *hw); static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw); static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw); static void e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index); +static void e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index); static void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw, u8 *mc_addr_list, u32 mc_addr_count); @@ -99,6 +95,7 @@ static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw); static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw); static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw); static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw); +static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw); static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed, u16 *duplex); static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw); @@ -111,8 +108,6 @@ static s32 e1000_led_on_pchlan(struct e1000_hw *hw); static s32 e1000_led_off_pchlan(struct e1000_hw *hw); static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw); static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank); -static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout); -static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw); static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw); static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw); static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, @@ -123,21 +118,13 @@ static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset, u16 *data); static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, u8 byte); -static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, - u32 offset, u8 data); -static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, - u8 size, u16 data); static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw); static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw); static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw); -static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw); -static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw); static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw); static s32 e1000_k1_workaround_lv(struct e1000_hw *hw); static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate); -#if defined(NAHUM6_HW) && (defined(LTR_SUPPORT) || defined(OBFF_SUPPORT)) - -#endif /* NAHUM6_HW && (LTR_SUPPORT || OBFF_SUPPORT) */ +static s32 e1000_set_obff_timer_pch_lpt(struct e1000_hw *hw, u32 itr); /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */ /* Offset 04h HSFSTS */ @@ -180,20 +167,190 @@ union ich8_hws_flash_regacc { u16 regval; }; -static void e1000_toggle_lanphypc_value_ich8lan(struct e1000_hw *hw) +/** + * e1000_phy_is_accessible_pchlan - Check if able to access PHY registers + * @hw: pointer to the HW structure + * + * Test access to the PHY registers by reading the PHY ID registers. If + * the PHY ID is already known (e.g. resume path) compare it with known ID, + * otherwise assume the read PHY ID is correct if it is valid. + * + * Assumes the sw/fw/hw semaphore is already acquired. + **/ +static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw) { - u32 ctrl; + u16 phy_reg = 0; + u32 phy_id = 0; + s32 ret_val; + u16 retry_count; - DEBUGFUNC("e1000_toggle_lanphypc_value_ich8lan"); + for (retry_count = 0; retry_count < 2; retry_count++) { + ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID1, &phy_reg); + if (ret_val || (phy_reg == 0xFFFF)) + continue; + phy_id = (u32)(phy_reg << 16); - ctrl = E1000_READ_REG(hw, E1000_CTRL); - ctrl |= E1000_CTRL_LANPHYPC_OVERRIDE; - ctrl &= ~E1000_CTRL_LANPHYPC_VALUE; - E1000_WRITE_REG(hw, E1000_CTRL, ctrl); - E1000_WRITE_FLUSH(hw); - usec_delay(10); - ctrl &= ~E1000_CTRL_LANPHYPC_OVERRIDE; - E1000_WRITE_REG(hw, E1000_CTRL, ctrl); + ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID2, &phy_reg); + if (ret_val || (phy_reg == 0xFFFF)) { + phy_id = 0; + continue; + } + phy_id |= (u32)(phy_reg & PHY_REVISION_MASK); + break; + } + + if (hw->phy.id) { + if (hw->phy.id == phy_id) + return TRUE; + } else if (phy_id) { + hw->phy.id = phy_id; + hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK); + return TRUE; + } + + /* In case the PHY needs to be in mdio slow mode, + * set slow mode and try to get the PHY id again. + */ + hw->phy.ops.release(hw); + ret_val = e1000_set_mdio_slow_mode_hv(hw); + if (!ret_val) + ret_val = e1000_get_phy_id(hw); + hw->phy.ops.acquire(hw); + + return !ret_val; +} + +/** + * e1000_init_phy_workarounds_pchlan - PHY initialization workarounds + * @hw: pointer to the HW structure + * + * Workarounds/flow necessary for PHY initialization during driver load + * and resume paths. + **/ +static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw) +{ + u32 mac_reg, fwsm = E1000_READ_REG(hw, E1000_FWSM); + s32 ret_val; + u16 phy_reg; + + DEBUGFUNC("e1000_init_phy_workarounds_pchlan"); + + /* Gate automatic PHY configuration by hardware on managed and + * non-managed 82579 and newer adapters. + */ + e1000_gate_hw_phy_config_ich8lan(hw, TRUE); + + ret_val = hw->phy.ops.acquire(hw); + if (ret_val) { + DEBUGOUT("Failed to initialize PHY flow\n"); + goto out; + } + + /* The MAC-PHY interconnect may be in SMBus mode. If the PHY is + * inaccessible and resetting the PHY is not blocked, toggle the + * LANPHYPC Value bit to force the interconnect to PCIe mode. + */ + switch (hw->mac.type) { + case e1000_pch_lpt: + if (e1000_phy_is_accessible_pchlan(hw)) + break; + + /* Before toggling LANPHYPC, see if PHY is accessible by + * forcing MAC to SMBus mode first. + */ + mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT); + mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS; + E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg); + + /* fall-through */ + case e1000_pch2lan: + if (e1000_phy_is_accessible_pchlan(hw)) { + if (hw->mac.type == e1000_pch_lpt) { + /* Unforce SMBus mode in PHY */ + hw->phy.ops.read_reg_locked(hw, CV_SMB_CTRL, + &phy_reg); + phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS; + hw->phy.ops.write_reg_locked(hw, CV_SMB_CTRL, + phy_reg); + + /* Unforce SMBus mode in MAC */ + mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT); + mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS; + E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg); + } + break; + } + + /* fall-through */ + case e1000_pchlan: + if ((hw->mac.type == e1000_pchlan) && + (fwsm & E1000_ICH_FWSM_FW_VALID)) + break; + + if (hw->phy.ops.check_reset_block(hw)) { + DEBUGOUT("Required LANPHYPC toggle blocked by ME\n"); + break; + } + + DEBUGOUT("Toggling LANPHYPC\n"); + + /* Set Phy Config Counter to 50msec */ + mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM3); + mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK; + mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC; + E1000_WRITE_REG(hw, E1000_FEXTNVM3, mac_reg); + + if (hw->mac.type == e1000_pch_lpt) { + /* Toggling LANPHYPC brings the PHY out of SMBus mode + * So ensure that the MAC is also out of SMBus mode + */ + mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT); + mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS; + E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg); + } + + /* Toggle LANPHYPC Value bit */ + mac_reg = E1000_READ_REG(hw, E1000_CTRL); + mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE; + mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE; + E1000_WRITE_REG(hw, E1000_CTRL, mac_reg); + E1000_WRITE_FLUSH(hw); + usec_delay(10); + mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE; + E1000_WRITE_REG(hw, E1000_CTRL, mac_reg); + E1000_WRITE_FLUSH(hw); + if (hw->mac.type < e1000_pch_lpt) { + msec_delay(50); + } else { + u16 count = 20; + do { + msec_delay(5); + } while (!(E1000_READ_REG(hw, E1000_CTRL_EXT) & + E1000_CTRL_EXT_LPCD) && count--); + } + break; + default: + break; + } + + hw->phy.ops.release(hw); + + /* Reset the PHY before any access to it. Doing so, ensures + * that the PHY is in a known good state before we read/write + * PHY registers. The generic reset is sufficient here, + * because we haven't determined the PHY type yet. + */ + ret_val = e1000_phy_hw_reset_generic(hw); + +out: + /* Ungate automatic PHY configuration on non-managed 82579 */ + if ((hw->mac.type == e1000_pch2lan) && + !(fwsm & E1000_ICH_FWSM_FW_VALID)) { + msec_delay(10); + e1000_gate_hw_phy_config_ich8lan(hw, FALSE); + } + + return ret_val; } /** @@ -205,7 +362,7 @@ static void e1000_toggle_lanphypc_value_ich8lan(struct e1000_hw *hw) static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw) { struct e1000_phy_info *phy = &hw->phy; - s32 ret_val = E1000_SUCCESS; + s32 ret_val; DEBUGFUNC("e1000_init_phy_params_pchlan"); @@ -230,70 +387,40 @@ static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw) phy->ops.power_down = e1000_power_down_phy_copper_ich8lan; phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; - if (!hw->phy.ops.check_reset_block(hw)) { - u32 fwsm = E1000_READ_REG(hw, E1000_FWSM); - - /* - * The MAC-PHY interconnect may still be in SMBus mode after - * Sx->S0. If resetting the PHY is not blocked, toggle the - * LANPHYPC Value bit to force the interconnect to PCIe mode. - */ - e1000_toggle_lanphypc_value_ich8lan(hw); - msec_delay(50); - - /* - * Gate automatic PHY configuration by hardware on - * non-managed 82579 - */ - if ((hw->mac.type == e1000_pch2lan) && - !(fwsm & E1000_ICH_FWSM_FW_VALID)) - e1000_gate_hw_phy_config_ich8lan(hw, TRUE); - - /* - * Reset the PHY before any access to it. Doing so, ensures - * that the PHY is in a known good state before we read/write - * PHY registers. The generic reset is sufficient here, - * because we haven't determined the PHY type yet. - */ - ret_val = e1000_phy_hw_reset_generic(hw); - if (ret_val) - goto out; + phy->id = e1000_phy_unknown; - /* Ungate automatic PHY configuration on non-managed 82579 */ - if ((hw->mac.type == e1000_pch2lan) && - !(fwsm & E1000_ICH_FWSM_FW_VALID)) { - msec_delay(10); - e1000_gate_hw_phy_config_ich8lan(hw, FALSE); - } - } + ret_val = e1000_init_phy_workarounds_pchlan(hw); + if (ret_val) + return ret_val; - phy->id = e1000_phy_unknown; - switch (hw->mac.type) { - default: - ret_val = e1000_get_phy_id(hw); - if (ret_val) - goto out; - if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK)) + if (phy->id == e1000_phy_unknown) + switch (hw->mac.type) { + default: + ret_val = e1000_get_phy_id(hw); + if (ret_val) + return ret_val; + if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK)) + break; + /* fall-through */ + case e1000_pch2lan: + case e1000_pch_lpt: + /* In case the PHY needs to be in mdio slow mode, + * set slow mode and try to get the PHY id again. + */ + ret_val = e1000_set_mdio_slow_mode_hv(hw); + if (ret_val) + return ret_val; + ret_val = e1000_get_phy_id(hw); + if (ret_val) + return ret_val; break; - /* fall-through */ - case e1000_pch2lan: - /* - * In case the PHY needs to be in mdio slow mode, - * set slow mode and try to get the PHY id again. - */ - ret_val = e1000_set_mdio_slow_mode_hv(hw); - if (ret_val) - goto out; - ret_val = e1000_get_phy_id(hw); - if (ret_val) - goto out; - break; - } + } phy->type = e1000_get_phy_type_from_id(phy->id); switch (phy->type) { case e1000_phy_82577: case e1000_phy_82579: + case e1000_phy_i217: phy->ops.check_polarity = e1000_check_polarity_82577; phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_82577; @@ -312,7 +439,6 @@ static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw) break; } -out: return ret_val; } @@ -325,7 +451,7 @@ out: static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw) { struct e1000_phy_info *phy = &hw->phy; - s32 ret_val = E1000_SUCCESS; + s32 ret_val; u16 i = 0; DEBUGFUNC("e1000_init_phy_params_ich8lan"); @@ -346,8 +472,7 @@ static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw) phy->ops.power_up = e1000_power_up_phy_copper; phy->ops.power_down = e1000_power_down_phy_copper_ich8lan; - /* - * We may need to do this twice - once for IGP and if that fails, + /* We may need to do this twice - once for IGP and if that fails, * we'll set BM func pointers and try again */ ret_val = e1000_determine_phy_address(hw); @@ -357,7 +482,7 @@ static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw) ret_val = e1000_determine_phy_address(hw); if (ret_val) { DEBUGOUT("Cannot determine PHY addr. Erroring out\n"); - goto out; + return ret_val; } } @@ -367,7 +492,7 @@ static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw) msec_delay(1); ret_val = e1000_get_phy_id(hw); if (ret_val) - goto out; + return ret_val; } /* Verify phy id */ @@ -401,12 +526,11 @@ static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw) phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88; break; default: - ret_val = -E1000_ERR_PHY; - goto out; + return -E1000_ERR_PHY; + break; } -out: - return ret_val; + return E1000_SUCCESS; } /** @@ -421,7 +545,6 @@ static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw) struct e1000_nvm_info *nvm = &hw->nvm; struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; u32 gfpreg, sector_base_addr, sector_end_addr; - s32 ret_val = E1000_SUCCESS; u16 i; DEBUGFUNC("e1000_init_nvm_params_ich8lan"); @@ -429,16 +552,14 @@ static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw) /* Can't read flash registers if the register set isn't mapped. */ if (!hw->flash_address) { DEBUGOUT("ERROR: Flash registers not mapped\n"); - ret_val = -E1000_ERR_CONFIG; - goto out; + return -E1000_ERR_CONFIG; } nvm->type = e1000_nvm_flash_sw; gfpreg = E1000_READ_FLASH_REG(hw, ICH_FLASH_GFPREG); - /* - * sector_X_addr is a "sector"-aligned address (4096 bytes) + /* sector_X_addr is a "sector"-aligned address (4096 bytes) * Add 1 to sector_end_addr since this sector is included in * the overall size. */ @@ -448,8 +569,7 @@ static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw) /* flash_base_addr is byte-aligned */ nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT; - /* - * find total size of the NVM, then cut in half since the total + /* find total size of the NVM, then cut in half since the total * size represents two separate NVM banks. */ nvm->flash_bank_size = (sector_end_addr - sector_base_addr) @@ -478,8 +598,7 @@ static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw) nvm->ops.validate = e1000_validate_nvm_checksum_ich8lan; nvm->ops.write = e1000_write_nvm_ich8lan; -out: - return ret_val; + return E1000_SUCCESS; } /** @@ -536,7 +655,7 @@ static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw) /* clear hardware counters */ mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan; - /* LED operations */ + /* LED and other operations */ switch (mac->type) { case e1000_ich8lan: case e1000_ich9lan: @@ -558,10 +677,11 @@ static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw) case e1000_pch2lan: mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES; mac->ops.rar_set = e1000_rar_set_pch2lan; + /* fall-through */ + case e1000_pch_lpt: /* multicast address update for pch2 */ mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_pch2lan; - /* fall-through */ case e1000_pchlan: /* check management mode */ mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan; @@ -579,55 +699,385 @@ static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw) break; } -#if defined(NAHUM6_HW) && (defined(LTR_SUPPORT) || defined(OBFF_SUPPORT)) if (mac->type == e1000_pch_lpt) { + mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES; + mac->ops.rar_set = e1000_rar_set_pch_lpt; + mac->ops.setup_physical_interface = e1000_setup_copper_link_pch_lpt; + mac->ops.set_obff_timer = e1000_set_obff_timer_pch_lpt; } -#endif /* NAHUM6_HW && (LTR_SUPPORT || OBFF_SUPPORT) */ /* Enable PCS Lock-loss workaround for ICH8 */ if (mac->type == e1000_ich8lan) e1000_set_kmrn_lock_loss_workaround_ich8lan(hw, TRUE); - /* Gate automatic PHY configuration by hardware on managed 82579 */ - if ((mac->type == e1000_pch2lan) && - (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID)) - e1000_gate_hw_phy_config_ich8lan(hw, TRUE); - return E1000_SUCCESS; } /** + * __e1000_access_emi_reg_locked - Read/write EMI register + * @hw: pointer to the HW structure + * @addr: EMI address to program + * @data: pointer to value to read/write from/to the EMI address + * @read: boolean flag to indicate read or write + * + * This helper function assumes the SW/FW/HW Semaphore is already acquired. + **/ +static s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address, + u16 *data, bool read) +{ + s32 ret_val; + + DEBUGFUNC("__e1000_access_emi_reg_locked"); + + ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR, address); + if (ret_val) + return ret_val; + + if (read) + ret_val = hw->phy.ops.read_reg_locked(hw, I82579_EMI_DATA, + data); + else + ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA, + *data); + + return ret_val; +} + +/** + * e1000_read_emi_reg_locked - Read Extended Management Interface register + * @hw: pointer to the HW structure + * @addr: EMI address to program + * @data: value to be read from the EMI address + * + * Assumes the SW/FW/HW Semaphore is already acquired. + **/ +s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data) +{ + DEBUGFUNC("e1000_read_emi_reg_locked"); + + return __e1000_access_emi_reg_locked(hw, addr, data, TRUE); +} + +/** + * e1000_write_emi_reg_locked - Write Extended Management Interface register + * @hw: pointer to the HW structure + * @addr: EMI address to program + * @data: value to be written to the EMI address + * + * Assumes the SW/FW/HW Semaphore is already acquired. + **/ +static s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data) +{ + DEBUGFUNC("e1000_read_emi_reg_locked"); + + return __e1000_access_emi_reg_locked(hw, addr, &data, FALSE); +} + +/** * e1000_set_eee_pchlan - Enable/disable EEE support * @hw: pointer to the HW structure * - * Enable/disable EEE based on setting in dev_spec structure. The bits in - * the LPI Control register will remain set only if/when link is up. + * Enable/disable EEE based on setting in dev_spec structure, the duplex of + * the link and the EEE capabilities of the link partner. The LPI Control + * register bits will remain set only if/when link is up. **/ static s32 e1000_set_eee_pchlan(struct e1000_hw *hw) { struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; - s32 ret_val = E1000_SUCCESS; - u16 phy_reg; + s32 ret_val; + u16 lpi_ctrl; DEBUGFUNC("e1000_set_eee_pchlan"); - if (hw->phy.type != e1000_phy_82579) - goto out; + if ((hw->phy.type != e1000_phy_82579) && + (hw->phy.type != e1000_phy_i217)) + return E1000_SUCCESS; - ret_val = hw->phy.ops.read_reg(hw, I82579_LPI_CTRL, &phy_reg); + ret_val = hw->phy.ops.acquire(hw); if (ret_val) - goto out; + return ret_val; - if (dev_spec->eee_disable) - phy_reg &= ~I82579_LPI_CTRL_ENABLE_MASK; - else - phy_reg |= I82579_LPI_CTRL_ENABLE_MASK; + ret_val = hw->phy.ops.read_reg_locked(hw, I82579_LPI_CTRL, &lpi_ctrl); + if (ret_val) + goto release; + + /* Clear bits that enable EEE in various speeds */ + lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK; + + /* Enable EEE if not disabled by user */ + if (!dev_spec->eee_disable) { + u16 lpa, pcs_status, data; + + /* Save off link partner's EEE ability */ + switch (hw->phy.type) { + case e1000_phy_82579: + lpa = I82579_EEE_LP_ABILITY; + pcs_status = I82579_EEE_PCS_STATUS; + break; + case e1000_phy_i217: + lpa = I217_EEE_LP_ABILITY; + pcs_status = I217_EEE_PCS_STATUS; + break; + default: + ret_val = -E1000_ERR_PHY; + goto release; + } + ret_val = e1000_read_emi_reg_locked(hw, lpa, + &dev_spec->eee_lp_ability); + if (ret_val) + goto release; + + /* Enable EEE only for speeds in which the link partner is + * EEE capable. + */ + if (dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED) + lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE; + + if (dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) { + hw->phy.ops.read_reg_locked(hw, PHY_LP_ABILITY, &data); + if (data & NWAY_LPAR_100TX_FD_CAPS) + lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE; + else + /* EEE is not supported in 100Half, so ignore + * partner's EEE in 100 ability if full-duplex + * is not advertised. + */ + dev_spec->eee_lp_ability &= + ~I82579_EEE_100_SUPPORTED; + } + + /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */ + ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data); + if (ret_val) + goto release; + } + + ret_val = hw->phy.ops.write_reg_locked(hw, I82579_LPI_CTRL, lpi_ctrl); +release: + hw->phy.ops.release(hw); + + return ret_val; +} + +/** + * e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP + * @hw: pointer to the HW structure + * @link: link up bool flag + * + * When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications + * preventing further DMA write requests. Workaround the issue by disabling + * the de-assertion of the clock request when in 1Gpbs mode. + **/ +static s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link) +{ + u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6); + s32 ret_val = E1000_SUCCESS; + + if (link && (E1000_READ_REG(hw, E1000_STATUS) & + E1000_STATUS_SPEED_1000)) { + u16 kmrn_reg; + + ret_val = hw->phy.ops.acquire(hw); + if (ret_val) + return ret_val; + + ret_val = + e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG, + &kmrn_reg); + if (ret_val) + goto release; + + ret_val = + e1000_write_kmrn_reg_locked(hw, + E1000_KMRNCTRLSTA_K1_CONFIG, + kmrn_reg & + ~E1000_KMRNCTRLSTA_K1_ENABLE); + if (ret_val) + goto release; + + usec_delay(10); + + E1000_WRITE_REG(hw, E1000_FEXTNVM6, + fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK); + + ret_val = + e1000_write_kmrn_reg_locked(hw, + E1000_KMRNCTRLSTA_K1_CONFIG, + kmrn_reg); +release: + hw->phy.ops.release(hw); + } else { + /* clear FEXTNVM6 bit 8 on link down or 10/100 */ + E1000_WRITE_REG(hw, E1000_FEXTNVM6, + fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK); + } - ret_val = hw->phy.ops.write_reg(hw, I82579_LPI_CTRL, phy_reg); -out: return ret_val; } +static u64 e1000_ltr2ns(u16 ltr) +{ + u32 value, scale; + + /* Determine the latency in nsec based on the LTR value & scale */ + value = ltr & E1000_LTRV_VALUE_MASK; + scale = (ltr & E1000_LTRV_SCALE_MASK) >> E1000_LTRV_SCALE_SHIFT; + + return value * (1 << (scale * E1000_LTRV_SCALE_FACTOR)); +} + +/** + * e1000_platform_pm_pch_lpt - Set platform power management values + * @hw: pointer to the HW structure + * @link: bool indicating link status + * + * Set the Latency Tolerance Reporting (LTR) values for the "PCIe-like" + * GbE MAC in the Lynx Point PCH based on Rx buffer size and link speed + * when link is up (which must not exceed the maximum latency supported + * by the platform), otherwise specify there is no LTR requirement. + * Unlike TRUE-PCIe devices which set the LTR maximum snoop/no-snoop + * latencies in the LTR Extended Capability Structure in the PCIe Extended + * Capability register set, on this device LTR is set by writing the + * equivalent snoop/no-snoop latencies in the LTRV register in the MAC and + * set the SEND bit to send an Intel On-chip System Fabric sideband (IOSF-SB) + * message to the PMC. + * + * Use the LTR value to calculate the Optimized Buffer Flush/Fill (OBFF) + * high-water mark. + **/ +static s32 e1000_platform_pm_pch_lpt(struct e1000_hw *hw, bool link) +{ + u32 reg = link << (E1000_LTRV_REQ_SHIFT + E1000_LTRV_NOSNOOP_SHIFT) | + link << E1000_LTRV_REQ_SHIFT | E1000_LTRV_SEND; + u16 lat_enc = 0; /* latency encoded */ + s32 obff_hwm = 0; + + DEBUGFUNC("e1000_platform_pm_pch_lpt"); + + if (link) { + u16 speed, duplex, scale = 0; + u16 max_snoop, max_nosnoop; + u16 max_ltr_enc; /* max LTR latency encoded */ + s64 lat_ns; /* latency (ns) */ + s64 value; + u32 rxa; + + if (!hw->mac.max_frame_size) { + DEBUGOUT("max_frame_size not set.\n"); + return -E1000_ERR_CONFIG; + } + + hw->mac.ops.get_link_up_info(hw, &speed, &duplex); + if (!speed) { + DEBUGOUT("Speed not set.\n"); + return -E1000_ERR_CONFIG; + } + + /* Rx Packet Buffer Allocation size (KB) */ + rxa = E1000_READ_REG(hw, E1000_PBA) & E1000_PBA_RXA_MASK; + + /* Determine the maximum latency tolerated by the device. + * + * Per the PCIe spec, the tolerated latencies are encoded as + * a 3-bit encoded scale (only 0-5 are valid) multiplied by + * a 10-bit value (0-1023) to provide a range from 1 ns to + * 2^25*(2^10-1) ns. The scale is encoded as 0=2^0ns, + * 1=2^5ns, 2=2^10ns,...5=2^25ns. + */ + lat_ns = ((s64)rxa * 1024 - + (2 * (s64)hw->mac.max_frame_size)) * 8 * 1000; + if (lat_ns < 0) + lat_ns = 0; + else + lat_ns /= speed; + + value = lat_ns; + while (value > E1000_LTRV_VALUE_MASK) { + scale++; + value = E1000_DIVIDE_ROUND_UP(value, (1 << 5)); + } + if (scale > E1000_LTRV_SCALE_MAX) { + DEBUGOUT1("Invalid LTR latency scale %d\n", scale); + return -E1000_ERR_CONFIG; + } + lat_enc = (u16)((scale << E1000_LTRV_SCALE_SHIFT) | value); + + /* Determine the maximum latency tolerated by the platform */ + e1000_read_pci_cfg(hw, E1000_PCI_LTR_CAP_LPT, &max_snoop); + e1000_read_pci_cfg(hw, E1000_PCI_LTR_CAP_LPT + 2, &max_nosnoop); + max_ltr_enc = E1000_MAX(max_snoop, max_nosnoop); + + if (lat_enc > max_ltr_enc) { + lat_enc = max_ltr_enc; + lat_ns = e1000_ltr2ns(max_ltr_enc); + } + + if (lat_ns) { + lat_ns *= speed * 1000; + lat_ns /= 8; + lat_ns /= 1000000000; + obff_hwm = (s32)(rxa - lat_ns); + } + + if ((obff_hwm < 0) || (obff_hwm > E1000_SVT_OFF_HWM_MASK)) { + DEBUGOUT1("Invalid high water mark %d\n", obff_hwm); + return -E1000_ERR_CONFIG; + } + } + + /* Set Snoop and No-Snoop latencies the same */ + reg |= lat_enc | (lat_enc << E1000_LTRV_NOSNOOP_SHIFT); + E1000_WRITE_REG(hw, E1000_LTRV, reg); + + /* Set OBFF high water mark */ + reg = E1000_READ_REG(hw, E1000_SVT) & ~E1000_SVT_OFF_HWM_MASK; + reg |= obff_hwm; + E1000_WRITE_REG(hw, E1000_SVT, reg); + + /* Enable OBFF */ + reg = E1000_READ_REG(hw, E1000_SVCR); + reg |= E1000_SVCR_OFF_EN; + /* Always unblock interrupts to the CPU even when the system is + * in OBFF mode. This ensures that small round-robin traffic + * (like ping) does not get dropped or experience long latency. + */ + reg |= E1000_SVCR_OFF_MASKINT; + E1000_WRITE_REG(hw, E1000_SVCR, reg); + + return E1000_SUCCESS; +} + +/** + * e1000_set_obff_timer_pch_lpt - Update Optimized Buffer Flush/Fill timer + * @hw: pointer to the HW structure + * @itr: interrupt throttling rate + * + * Configure OBFF with the updated interrupt rate. + **/ +static s32 e1000_set_obff_timer_pch_lpt(struct e1000_hw *hw, u32 itr) +{ + u32 svcr; + s32 timer; + + DEBUGFUNC("e1000_set_obff_timer_pch_lpt"); + + /* Convert ITR value into microseconds for OBFF timer */ + timer = itr & E1000_ITR_MASK; + timer = (timer * E1000_ITR_MULT) / 1000; + + if ((timer < 0) || (timer > E1000_ITR_MASK)) { + DEBUGOUT1("Invalid OBFF timer %d\n", timer); + return -E1000_ERR_CONFIG; + } + + svcr = E1000_READ_REG(hw, E1000_SVCR); + svcr &= ~E1000_SVCR_OFF_TIMER_MASK; + svcr |= timer << E1000_SVCR_OFF_TIMER_SHIFT; + E1000_WRITE_REG(hw, E1000_SVCR, svcr); + + return E1000_SUCCESS; +} + /** * e1000_check_for_copper_link_ich8lan - Check for link (Copper) * @hw: pointer to the HW structure @@ -645,39 +1095,77 @@ static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw) DEBUGFUNC("e1000_check_for_copper_link_ich8lan"); - /* - * We only want to go out to the PHY registers to see if Auto-Neg + /* We only want to go out to the PHY registers to see if Auto-Neg * has completed and/or if our link status has changed. The * get_link_status flag is set upon receiving a Link Status * Change or Rx Sequence Error interrupt. */ - if (!mac->get_link_status) { - ret_val = E1000_SUCCESS; - goto out; - } + if (!mac->get_link_status) + return E1000_SUCCESS; - /* - * First we want to see if the MII Status Register reports + /* First we want to see if the MII Status Register reports * link. If so, then we want to get the current speed/duplex * of the PHY. */ ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); if (ret_val) - goto out; + return ret_val; if (hw->mac.type == e1000_pchlan) { ret_val = e1000_k1_gig_workaround_hv(hw, link); if (ret_val) - goto out; + return ret_val; + } + + /* When connected at 10Mbps half-duplex, 82579 parts are excessively + * aggressive resulting in many collisions. To avoid this, increase + * the IPG and reduce Rx latency in the PHY. + */ + if ((hw->mac.type == e1000_pch2lan) && link) { + u32 reg; + reg = E1000_READ_REG(hw, E1000_STATUS); + if (!(reg & (E1000_STATUS_FD | E1000_STATUS_SPEED_MASK))) { + reg = E1000_READ_REG(hw, E1000_TIPG); + reg &= ~E1000_TIPG_IPGT_MASK; + reg |= 0xFF; + E1000_WRITE_REG(hw, E1000_TIPG, reg); + + /* Reduce Rx latency in analog PHY */ + ret_val = hw->phy.ops.acquire(hw); + if (ret_val) + return ret_val; + + ret_val = e1000_write_emi_reg_locked(hw, I82579_RX_CONFIG, 0); + + hw->phy.ops.release(hw); + + if (ret_val) + return ret_val; + } + } + + /* Work-around I218 hang issue */ + if ((hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) || + (hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_V)) { + ret_val = e1000_k1_workaround_lpt_lp(hw, link); + if (ret_val) + return ret_val; } -#if defined(NAHUM6_HW) && (defined(LTR_SUPPORT) || defined(OBFF_SUPPORT)) if (hw->mac.type == e1000_pch_lpt) { + /* Set platform power management values for Latency Tolerance + * Reporting (LTR) and Optimized Buffer Flush/Fill (OBFF). + */ + ret_val = e1000_platform_pm_pch_lpt(hw, link); + if (ret_val) + return ret_val; } -#endif /* NAHUM6_HW && (LTR_SUPPORT || OBFF_SUPPORT) */ + /* Clear link partner's EEE ability */ + hw->dev_spec.ich8lan.eee_lp_ability = 0; + if (!link) - goto out; /* No link detected */ + return E1000_SUCCESS; /* No link detected */ mac->get_link_status = FALSE; @@ -685,17 +1173,16 @@ static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw) case e1000_pch2lan: ret_val = e1000_k1_workaround_lv(hw); if (ret_val) - goto out; + return ret_val; /* fall-thru */ case e1000_pchlan: if (hw->phy.type == e1000_phy_82578) { ret_val = e1000_link_stall_workaround_hv(hw); if (ret_val) - goto out; + return ret_val; } - /* - * Workaround for PCHx parts in half-duplex: + /* Workaround for PCHx parts in half-duplex: * Set the number of preambles removed from the packet * when it is passed from the PHY to the MAC to prevent * the MAC from misinterpreting the packet type. @@ -713,8 +1200,7 @@ static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw) break; } - /* - * Check if there was DownShift, must be checked + /* Check if there was DownShift, must be checked * immediately after link-up */ e1000_check_downshift_generic(hw); @@ -722,26 +1208,21 @@ static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw) /* Enable/Disable EEE after link up */ ret_val = e1000_set_eee_pchlan(hw); if (ret_val) - goto out; + return ret_val; - /* - * If we are forcing speed/duplex, then we simply return since + /* If we are forcing speed/duplex, then we simply return since * we have already determined whether we have link or not. */ - if (!mac->autoneg) { - ret_val = -E1000_ERR_CONFIG; - goto out; - } + if (!mac->autoneg) + return -E1000_ERR_CONFIG; - /* - * Auto-Neg is enabled. Auto Speed Detection takes care + /* Auto-Neg is enabled. Auto Speed Detection takes care * of MAC speed/duplex configuration. So we only need to * configure Collision Distance in the MAC. */ - hw->mac.ops.config_collision_dist(hw); + mac->ops.config_collision_dist(hw); - /* - * Configure Flow Control now that Auto-Neg has completed. + /* Configure Flow Control now that Auto-Neg has completed. * First, we need to restore the desired flow control * settings because we may have had to re-autoneg with a * different link partner. @@ -750,7 +1231,6 @@ static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw) if (ret_val) DEBUGOUT("Error configuring flow control\n"); -out: return ret_val; } @@ -774,6 +1254,7 @@ void e1000_init_function_pointers_ich8lan(struct e1000_hw *hw) break; case e1000_pchlan: case e1000_pch2lan: + case e1000_pch_lpt: hw->phy.ops.init_params = e1000_init_phy_params_pchlan; break; default: @@ -957,8 +1438,7 @@ static void e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index) DEBUGFUNC("e1000_rar_set_pch2lan"); - /* - * HW expects these in little endian so we reverse the byte order + /* HW expects these in little endian so we reverse the byte order * from network order (big endian) to little endian */ rar_low = ((u32) addr[0] | @@ -980,11 +1460,19 @@ static void e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index) } if (index < hw->mac.rar_entry_count) { + s32 ret_val; + + ret_val = e1000_acquire_swflag_ich8lan(hw); + if (ret_val) + goto out; + E1000_WRITE_REG(hw, E1000_SHRAL(index - 1), rar_low); E1000_WRITE_FLUSH(hw); E1000_WRITE_REG(hw, E1000_SHRAH(index - 1), rar_high); E1000_WRITE_FLUSH(hw); + e1000_release_swflag_ich8lan(hw); + /* verify the register updates */ if ((E1000_READ_REG(hw, E1000_SHRAL(index - 1)) == rar_low) && (E1000_READ_REG(hw, E1000_SHRAH(index - 1)) == rar_high)) @@ -994,6 +1482,85 @@ static void e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index) (index - 1), E1000_READ_REG(hw, E1000_FWSM)); } +out: + DEBUGOUT1("Failed to write receive address at index %d\n", index); +} + +/** + * e1000_rar_set_pch_lpt - Set receive address registers + * @hw: pointer to the HW structure + * @addr: pointer to the receive address + * @index: receive address array register + * + * Sets the receive address register array at index to the address passed + * in by addr. For LPT, RAR[0] is the base address register that is to + * contain the MAC address. SHRA[0-10] are the shared receive address + * registers that are shared between the Host and manageability engine (ME). + **/ +static void e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index) +{ + u32 rar_low, rar_high; + u32 wlock_mac; + + DEBUGFUNC("e1000_rar_set_pch_lpt"); + + /* HW expects these in little endian so we reverse the byte order + * from network order (big endian) to little endian + */ + rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) | + ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); + + rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); + + /* If MAC address zero, no need to set the AV bit */ + if (rar_low || rar_high) + rar_high |= E1000_RAH_AV; + + if (index == 0) { + E1000_WRITE_REG(hw, E1000_RAL(index), rar_low); + E1000_WRITE_FLUSH(hw); + E1000_WRITE_REG(hw, E1000_RAH(index), rar_high); + E1000_WRITE_FLUSH(hw); + return; + } + + /* The manageability engine (ME) can lock certain SHRAR registers that + * it is using - those registers are unavailable for use. + */ + if (index < hw->mac.rar_entry_count) { + wlock_mac = E1000_READ_REG(hw, E1000_FWSM) & + E1000_FWSM_WLOCK_MAC_MASK; + wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT; + + /* Check if all SHRAR registers are locked */ + if (wlock_mac == 1) + goto out; + + if ((wlock_mac == 0) || (index <= wlock_mac)) { + s32 ret_val; + + ret_val = e1000_acquire_swflag_ich8lan(hw); + + if (ret_val) + goto out; + + E1000_WRITE_REG(hw, E1000_SHRAL_PCH_LPT(index - 1), + rar_low); + E1000_WRITE_FLUSH(hw); + E1000_WRITE_REG(hw, E1000_SHRAH_PCH_LPT(index - 1), + rar_high); + E1000_WRITE_FLUSH(hw); + + e1000_release_swflag_ich8lan(hw); + + /* verify the register updates */ + if ((E1000_READ_REG(hw, E1000_SHRAL_PCH_LPT(index - 1)) == rar_low) && + (E1000_READ_REG(hw, E1000_SHRAH_PCH_LPT(index - 1)) == rar_high)) + return; + } + } + +out: DEBUGOUT1("Failed to write receive address at index %d\n", index); } @@ -1072,21 +1639,34 @@ static s32 e1000_write_smbus_addr(struct e1000_hw *hw) { u16 phy_data; u32 strap = E1000_READ_REG(hw, E1000_STRAP); - s32 ret_val = E1000_SUCCESS; + u32 freq = (strap & E1000_STRAP_SMT_FREQ_MASK) >> + E1000_STRAP_SMT_FREQ_SHIFT; + s32 ret_val; strap &= E1000_STRAP_SMBUS_ADDRESS_MASK; ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data); if (ret_val) - goto out; + return ret_val; phy_data &= ~HV_SMB_ADDR_MASK; phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT); phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID; - ret_val = e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data); -out: - return ret_val; + if (hw->phy.type == e1000_phy_i217) { + /* Restore SMBus frequency */ + if (freq--) { + phy_data &= ~HV_SMB_ADDR_FREQ_MASK; + phy_data |= (freq & (1 << 0)) << + HV_SMB_ADDR_FREQ_LOW_SHIFT; + phy_data |= (freq & (1 << 1)) << + (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1); + } else { + DEBUGOUT("Unsupported SMB frequency in PHY\n"); + } + } + + return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data); } /** @@ -1105,8 +1685,7 @@ static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw) DEBUGFUNC("e1000_sw_lcd_config_ich8lan"); - /* - * Initialize the PHY from the NVM on ICH platforms. This + /* Initialize the PHY from the NVM on ICH platforms. This * is needed due to an issue where the NVM configuration is * not properly autoloaded after power transitions. * Therefore, after each PHY reset, we will load the @@ -1125,6 +1704,7 @@ static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw) /* Fall-thru */ case e1000_pchlan: case e1000_pch2lan: + case e1000_pch_lpt: sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M; break; default: @@ -1137,45 +1717,42 @@ static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw) data = E1000_READ_REG(hw, E1000_FEXTNVM); if (!(data & sw_cfg_mask)) - goto out; + goto release; - /* - * Make sure HW does not configure LCD from PHY + /* Make sure HW does not configure LCD from PHY * extended configuration before SW configuration */ data = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); - if (!(hw->mac.type == e1000_pch2lan)) { - if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE) - goto out; - } + if ((hw->mac.type < e1000_pch2lan) && + (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)) + goto release; cnf_size = E1000_READ_REG(hw, E1000_EXTCNF_SIZE); cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK; cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT; if (!cnf_size) - goto out; + goto release; cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK; cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT; - if ((!(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) && - (hw->mac.type == e1000_pchlan)) || - (hw->mac.type == e1000_pch2lan)) { - /* - * HW configures the SMBus address and LEDs when the + if (((hw->mac.type == e1000_pchlan) && + !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) || + (hw->mac.type > e1000_pchlan)) { + /* HW configures the SMBus address and LEDs when the * OEM and LCD Write Enable bits are set in the NVM. * When both NVM bits are cleared, SW will configure * them instead. */ ret_val = e1000_write_smbus_addr(hw); if (ret_val) - goto out; + goto release; data = E1000_READ_REG(hw, E1000_LEDCTL); ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG, (u16)data); if (ret_val) - goto out; + goto release; } /* Configure LCD from extended configuration region. */ @@ -1187,12 +1764,12 @@ static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw) ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2), 1, ®_data); if (ret_val) - goto out; + goto release; ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2 + 1), 1, ®_addr); if (ret_val) - goto out; + goto release; /* Save off the PHY page for future writes. */ if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) { @@ -1206,10 +1783,10 @@ static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw) ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr, reg_data); if (ret_val) - goto out; + goto release; } -out: +release: hw->phy.ops.release(hw); return ret_val; } @@ -1233,12 +1810,12 @@ static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link) DEBUGFUNC("e1000_k1_gig_workaround_hv"); if (hw->mac.type != e1000_pchlan) - goto out; + return E1000_SUCCESS; /* Wrap the whole flow with the sw flag */ ret_val = hw->phy.ops.acquire(hw); if (ret_val) - goto out; + return ret_val; /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */ if (link) { @@ -1292,7 +1869,7 @@ static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link) release: hw->phy.ops.release(hw); -out: + return ret_val; } @@ -1308,7 +1885,7 @@ out: **/ s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable) { - s32 ret_val = E1000_SUCCESS; + s32 ret_val; u32 ctrl_reg = 0; u32 ctrl_ext = 0; u32 reg = 0; @@ -1319,7 +1896,7 @@ s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable) ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG, &kmrn_reg); if (ret_val) - goto out; + return ret_val; if (k1_enable) kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE; @@ -1329,7 +1906,7 @@ s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable) ret_val = e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG, kmrn_reg); if (ret_val) - goto out; + return ret_val; usec_delay(20); ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); @@ -1347,8 +1924,7 @@ s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable) E1000_WRITE_FLUSH(hw); usec_delay(20); -out: - return ret_val; + return E1000_SUCCESS; } /** @@ -1368,28 +1944,28 @@ static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state) DEBUGFUNC("e1000_oem_bits_config_ich8lan"); - if ((hw->mac.type != e1000_pch2lan) && (hw->mac.type != e1000_pchlan)) + if (hw->mac.type < e1000_pchlan) return ret_val; ret_val = hw->phy.ops.acquire(hw); if (ret_val) return ret_val; - if (!(hw->mac.type == e1000_pch2lan)) { + if (hw->mac.type == e1000_pchlan) { mac_reg = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) - goto out; + goto release; } mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM); if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M)) - goto out; + goto release; mac_reg = E1000_READ_REG(hw, E1000_PHY_CTRL); ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg); if (ret_val) - goto out; + goto release; oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU); @@ -1399,10 +1975,6 @@ static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state) if (mac_reg & E1000_PHY_CTRL_D0A_LPLU) oem_reg |= HV_OEM_BITS_LPLU; - - /* Set Restart auto-neg to activate the bits */ - if (!hw->phy.ops.check_reset_block(hw)) - oem_reg |= HV_OEM_BITS_RESTART_AN; } else { if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE | E1000_PHY_CTRL_NOND0A_GBE_DISABLE)) @@ -1413,9 +1985,14 @@ static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state) oem_reg |= HV_OEM_BITS_LPLU; } + /* Set Restart auto-neg to activate the bits */ + if ((d0_state || (hw->mac.type != e1000_pchlan)) && + !hw->phy.ops.check_reset_block(hw)) + oem_reg |= HV_OEM_BITS_RESTART_AN; + ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg); -out: +release: hw->phy.ops.release(hw); return ret_val; @@ -1456,13 +2033,13 @@ static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw) DEBUGFUNC("e1000_hv_phy_workarounds_ich8lan"); if (hw->mac.type != e1000_pchlan) - goto out; + return E1000_SUCCESS; /* Set MDIO slow mode before any other MDIO access */ if (hw->phy.type == e1000_phy_82577) { ret_val = e1000_set_mdio_slow_mode_hv(hw); if (ret_val) - goto out; + return ret_val; } if (((hw->phy.type == e1000_phy_82577) && @@ -1471,18 +2048,17 @@ static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw) /* Disable generation of early preamble */ ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 25), 0x4431); if (ret_val) - goto out; + return ret_val; /* Preamble tuning for SSC */ ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA, 0xA204); if (ret_val) - goto out; + return ret_val; } if (hw->phy.type == e1000_phy_82578) { - /* - * Return registers to default by doing a soft reset then + /* Return registers to default by doing a soft reset then * writing 0x3140 to the control register. */ if (hw->phy.revision < 2) { @@ -1495,34 +2071,38 @@ static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw) /* Select page 0 */ ret_val = hw->phy.ops.acquire(hw); if (ret_val) - goto out; + return ret_val; hw->phy.addr = 1; ret_val = e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0); hw->phy.ops.release(hw); if (ret_val) - goto out; + return ret_val; - /* - * Configure the K1 Si workaround during phy reset assuming there is + /* Configure the K1 Si workaround during phy reset assuming there is * link so that it disables K1 if link is in 1Gbps. */ ret_val = e1000_k1_gig_workaround_hv(hw, TRUE); if (ret_val) - goto out; + return ret_val; /* Workaround for link disconnects on a busy hub in half duplex */ ret_val = hw->phy.ops.acquire(hw); if (ret_val) - goto out; + return ret_val; ret_val = hw->phy.ops.read_reg_locked(hw, BM_PORT_GEN_CFG, &phy_data); if (ret_val) goto release; ret_val = hw->phy.ops.write_reg_locked(hw, BM_PORT_GEN_CFG, phy_data & 0x00FF); + if (ret_val) + goto release; + + /* set MSE higher to enable link to stay up when noise is high */ + ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034); release: hw->phy.ops.release(hw); -out: + return ret_val; } @@ -1600,19 +2180,18 @@ s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable) DEBUGFUNC("e1000_lv_jumbo_workaround_ich8lan"); - if (hw->mac.type != e1000_pch2lan) - goto out; + if (hw->mac.type < e1000_pch2lan) + return E1000_SUCCESS; /* disable Rx path while enabling/disabling workaround */ hw->phy.ops.read_reg(hw, PHY_REG(769, 20), &phy_reg); ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 20), phy_reg | (1 << 14)); if (ret_val) - goto out; + return ret_val; if (enable) { - /* - * Write Rx addresses (rar_entry_count for RAL/H, +4 for + /* Write Rx addresses (rar_entry_count for RAL/H, +4 for * SHRAL/H) and initial CRC values to the MAC */ for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) { @@ -1651,24 +2230,24 @@ s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable) E1000_KMRNCTRLSTA_CTRL_OFFSET, &data); if (ret_val) - goto out; + return ret_val; ret_val = e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_CTRL_OFFSET, data | (1 << 0)); if (ret_val) - goto out; + return ret_val; ret_val = e1000_read_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_HD_CTRL, &data); if (ret_val) - goto out; + return ret_val; data &= ~(0xF << 8); data |= (0xB << 8); ret_val = e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_HD_CTRL, data); if (ret_val) - goto out; + return ret_val; /* Enable jumbo frame workaround in the PHY */ hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data); @@ -1676,26 +2255,26 @@ s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable) data |= (0x37 << 5); ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data); if (ret_val) - goto out; + return ret_val; hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data); data &= ~(1 << 13); ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data); if (ret_val) - goto out; + return ret_val; hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data); data &= ~(0x3FF << 2); data |= (0x1A << 2); ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data); if (ret_val) - goto out; + return ret_val; ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0xF100); if (ret_val) - goto out; + return ret_val; hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data); ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data | (1 << 10)); if (ret_val) - goto out; + return ret_val; } else { /* Write MAC register values back to h/w defaults */ mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG); @@ -1710,58 +2289,55 @@ s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable) E1000_KMRNCTRLSTA_CTRL_OFFSET, &data); if (ret_val) - goto out; + return ret_val; ret_val = e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_CTRL_OFFSET, data & ~(1 << 0)); if (ret_val) - goto out; + return ret_val; ret_val = e1000_read_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_HD_CTRL, &data); if (ret_val) - goto out; + return ret_val; data &= ~(0xF << 8); data |= (0xB << 8); ret_val = e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_HD_CTRL, data); if (ret_val) - goto out; + return ret_val; /* Write PHY register values back to h/w defaults */ hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data); data &= ~(0x7F << 5); ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data); if (ret_val) - goto out; + return ret_val; hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data); data |= (1 << 13); ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data); if (ret_val) - goto out; + return ret_val; hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data); data &= ~(0x3FF << 2); data |= (0x8 << 2); ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data); if (ret_val) - goto out; + return ret_val; ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0x7E00); if (ret_val) - goto out; + return ret_val; hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data); ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data & ~(1 << 10)); if (ret_val) - goto out; + return ret_val; } /* re-enable Rx path after enabling/disabling workaround */ - ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 20), phy_reg & - ~(1 << 14)); - -out: - return ret_val; + return hw->phy.ops.write_reg(hw, PHY_REG(769, 20), phy_reg & + ~(1 << 14)); } /** @@ -1775,34 +2351,25 @@ static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw) DEBUGFUNC("e1000_lv_phy_workarounds_ich8lan"); if (hw->mac.type != e1000_pch2lan) - goto out; + return E1000_SUCCESS; /* Set MDIO slow mode before any other MDIO access */ ret_val = e1000_set_mdio_slow_mode_hv(hw); + if (ret_val) + return ret_val; ret_val = hw->phy.ops.acquire(hw); if (ret_val) - goto out; - ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR, - I82579_MSE_THRESHOLD); - if (ret_val) - goto release; + return ret_val; /* set MSE higher to enable link to stay up when noise is high */ - ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA, - 0x0034); - if (ret_val) - goto release; - ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR, - I82579_MSE_LINK_DOWN); + ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034); if (ret_val) goto release; /* drop link after 5 times MSE threshold was reached */ - ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA, - 0x0005); + ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005); release: hw->phy.ops.release(hw); -out: return ret_val; } @@ -1822,12 +2389,12 @@ static s32 e1000_k1_workaround_lv(struct e1000_hw *hw) DEBUGFUNC("e1000_k1_workaround_lv"); if (hw->mac.type != e1000_pch2lan) - goto out; + return E1000_SUCCESS; /* Set K1 beacon duration based on 1Gbps speed or otherwise */ ret_val = hw->phy.ops.read_reg(hw, HV_M_STATUS, &status_reg); if (ret_val) - goto out; + return ret_val; if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) { @@ -1836,11 +2403,23 @@ static s32 e1000_k1_workaround_lv(struct e1000_hw *hw) ret_val = hw->phy.ops.read_reg(hw, I82579_LPI_CTRL, &phy_reg); if (ret_val) - goto out; + return ret_val; if (status_reg & HV_M_STATUS_SPEED_1000) { + u16 pm_phy_reg; + mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC; phy_reg &= ~I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT; + /* LV 1G Packet drop issue wa */ + ret_val = hw->phy.ops.read_reg(hw, HV_PM_CTRL, + &pm_phy_reg); + if (ret_val) + return ret_val; + pm_phy_reg &= ~HV_PM_CTRL_PLL_STOP_IN_K1_GIGA; + ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, + pm_phy_reg); + if (ret_val) + return ret_val; } else { mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC; phy_reg |= I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT; @@ -1849,7 +2428,6 @@ static s32 e1000_k1_workaround_lv(struct e1000_hw *hw) ret_val = hw->phy.ops.write_reg(hw, I82579_LPI_CTRL, phy_reg); } -out: return ret_val; } @@ -1867,7 +2445,7 @@ static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate) DEBUGFUNC("e1000_gate_hw_phy_config_ich8lan"); - if (hw->mac.type != e1000_pch2lan) + if (hw->mac.type < e1000_pch2lan) return; extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); @@ -1878,7 +2456,6 @@ static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate) extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG; E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); - return; } /** @@ -1901,8 +2478,7 @@ static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw) usec_delay(100); } while ((!data) && --loop); - /* - * If basic configuration is incomplete before the above loop + /* If basic configuration is incomplete before the above loop * count reaches 0, loading the configuration from NVM will * leave the PHY in a bad state possibly resulting in no link. */ @@ -1927,7 +2503,7 @@ static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw) DEBUGFUNC("e1000_post_phy_reset_ich8lan"); if (hw->phy.ops.check_reset_block(hw)) - goto out; + return E1000_SUCCESS; /* Allow time for h/w to get to quiescent state after reset */ msec_delay(10); @@ -1937,12 +2513,12 @@ static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw) case e1000_pchlan: ret_val = e1000_hv_phy_workarounds_ich8lan(hw); if (ret_val) - goto out; + return ret_val; break; case e1000_pch2lan: ret_val = e1000_lv_phy_workarounds_ich8lan(hw); if (ret_val) - goto out; + return ret_val; break; default: break; @@ -1958,7 +2534,7 @@ static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw) /* Configure the LCD with the extended configuration region in NVM */ ret_val = e1000_sw_lcd_config_ich8lan(hw); if (ret_val) - goto out; + return ret_val; /* Configure the LCD with the OEM bits in NVM */ ret_val = e1000_oem_bits_config_ich8lan(hw, TRUE); @@ -1974,18 +2550,13 @@ static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw) /* Set EEE LPI Update Timer to 200usec */ ret_val = hw->phy.ops.acquire(hw); if (ret_val) - goto out; - ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR, - I82579_LPI_UPDATE_TIMER); - if (ret_val) - goto release; - ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA, - 0x1387); -release: + return ret_val; + ret_val = e1000_write_emi_reg_locked(hw, + I82579_LPI_UPDATE_TIMER, + 0x1387); hw->phy.ops.release(hw); } -out: return ret_val; } @@ -2010,12 +2581,9 @@ static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw) ret_val = e1000_phy_hw_reset_generic(hw); if (ret_val) - goto out; - - ret_val = e1000_post_phy_reset_ich8lan(hw); + return ret_val; -out: - return ret_val; + return e1000_post_phy_reset_ich8lan(hw); } /** @@ -2031,14 +2599,14 @@ out: **/ static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active) { - s32 ret_val = E1000_SUCCESS; + s32 ret_val; u16 oem_reg; DEBUGFUNC("e1000_set_lplu_state_pchlan"); ret_val = hw->phy.ops.read_reg(hw, HV_OEM_BITS, &oem_reg); if (ret_val) - goto out; + return ret_val; if (active) oem_reg |= HV_OEM_BITS_LPLU; @@ -2048,10 +2616,7 @@ static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active) if (!hw->phy.ops.check_reset_block(hw)) oem_reg |= HV_OEM_BITS_RESTART_AN; - ret_val = hw->phy.ops.write_reg(hw, HV_OEM_BITS, oem_reg); - -out: - return ret_val; + return hw->phy.ops.write_reg(hw, HV_OEM_BITS, oem_reg); } /** @@ -2077,7 +2642,7 @@ static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active) DEBUGFUNC("e1000_set_d0_lplu_state_ich8lan"); if (phy->type == e1000_phy_ife) - goto out; + return E1000_SUCCESS; phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL); @@ -2086,10 +2651,9 @@ static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active) E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); if (phy->type != e1000_phy_igp_3) - goto out; + return E1000_SUCCESS; - /* - * Call gig speed drop workaround on LPLU before accessing + /* Call gig speed drop workaround on LPLU before accessing * any PHY registers */ if (hw->mac.type == e1000_ich8lan) @@ -2099,21 +2663,22 @@ static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active) ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &data); + if (ret_val) + return ret_val; data &= ~IGP01E1000_PSCFR_SMART_SPEED; ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, data); if (ret_val) - goto out; + return ret_val; } else { phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); if (phy->type != e1000_phy_igp_3) - goto out; + return E1000_SUCCESS; - /* - * LPLU and SmartSpeed are mutually exclusive. LPLU is used + /* LPLU and SmartSpeed are mutually exclusive. LPLU is used * during Dx states where the power conservation is most * important. During driver activity we should enable * SmartSpeed, so performance is maintained. @@ -2123,32 +2688,31 @@ static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active) IGP01E1000_PHY_PORT_CONFIG, &data); if (ret_val) - goto out; + return ret_val; data |= IGP01E1000_PSCFR_SMART_SPEED; ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, data); if (ret_val) - goto out; + return ret_val; } else if (phy->smart_speed == e1000_smart_speed_off) { ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &data); if (ret_val) - goto out; + return ret_val; data &= ~IGP01E1000_PSCFR_SMART_SPEED; ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, data); if (ret_val) - goto out; + return ret_val; } } -out: - return ret_val; + return E1000_SUCCESS; } /** @@ -2180,10 +2744,9 @@ static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active) E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); if (phy->type != e1000_phy_igp_3) - goto out; + return E1000_SUCCESS; - /* - * LPLU and SmartSpeed are mutually exclusive. LPLU is used + /* LPLU and SmartSpeed are mutually exclusive. LPLU is used * during Dx states where the power conservation is most * important. During driver activity we should enable * SmartSpeed, so performance is maintained. @@ -2193,27 +2756,27 @@ static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active) IGP01E1000_PHY_PORT_CONFIG, &data); if (ret_val) - goto out; + return ret_val; data |= IGP01E1000_PSCFR_SMART_SPEED; ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, data); if (ret_val) - goto out; + return ret_val; } else if (phy->smart_speed == e1000_smart_speed_off) { ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &data); if (ret_val) - goto out; + return ret_val; data &= ~IGP01E1000_PSCFR_SMART_SPEED; ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, data); if (ret_val) - goto out; + return ret_val; } } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || @@ -2222,10 +2785,9 @@ static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active) E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); if (phy->type != e1000_phy_igp_3) - goto out; + return E1000_SUCCESS; - /* - * Call gig speed drop workaround on LPLU before accessing + /* Call gig speed drop workaround on LPLU before accessing * any PHY registers */ if (hw->mac.type == e1000_ich8lan) @@ -2236,7 +2798,7 @@ static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active) IGP01E1000_PHY_PORT_CONFIG, &data); if (ret_val) - goto out; + return ret_val; data &= ~IGP01E1000_PSCFR_SMART_SPEED; ret_val = phy->ops.write_reg(hw, @@ -2244,7 +2806,6 @@ static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active) data); } -out: return ret_val; } @@ -2263,7 +2824,7 @@ static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank) u32 bank1_offset = nvm->flash_bank_size * sizeof(u16); u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1; u8 sig_byte = 0; - s32 ret_val = E1000_SUCCESS; + s32 ret_val; DEBUGFUNC("e1000_valid_nvm_bank_detect_ich8lan"); @@ -2278,7 +2839,7 @@ static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank) else *bank = 0; - goto out; + return E1000_SUCCESS; } DEBUGOUT("Unable to determine valid NVM bank via EEC - reading flash signature\n"); /* fall-thru */ @@ -2290,11 +2851,11 @@ static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank) ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset, &sig_byte); if (ret_val) - goto out; + return ret_val; if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == E1000_ICH_NVM_SIG_VALUE) { *bank = 0; - goto out; + return E1000_SUCCESS; } /* Check bank 1 */ @@ -2302,19 +2863,16 @@ static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank) bank1_offset, &sig_byte); if (ret_val) - goto out; + return ret_val; if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == E1000_ICH_NVM_SIG_VALUE) { *bank = 1; - goto out; + return E1000_SUCCESS; } DEBUGOUT("ERROR: No valid NVM bank present\n"); - ret_val = -E1000_ERR_NVM; - break; + return -E1000_ERR_NVM; } -out: - return ret_val; } /** @@ -2396,9 +2954,9 @@ static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw) hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS); /* Check if the flash descriptor is valid */ - if (hsfsts.hsf_status.fldesvalid == 0) { + if (!hsfsts.hsf_status.fldesvalid) { DEBUGOUT("Flash descriptor invalid. SW Sequencing must be used.\n"); - goto out; + return -E1000_ERR_NVM; } /* Clear FCERR and DAEL in hw status by writing 1 */ @@ -2407,8 +2965,7 @@ static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw) E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval); - /* - * Either we should have a hardware SPI cycle in progress + /* Either we should have a hardware SPI cycle in progress * bit to check against, in order to start a new cycle or * FDONE bit should be changed in the hardware so that it * is 1 after hardware reset, which can then be used as an @@ -2416,9 +2973,8 @@ static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw) * completed. */ - if (hsfsts.hsf_status.flcinprog == 0) { - /* - * There is no cycle running at present, + if (!hsfsts.hsf_status.flcinprog) { + /* There is no cycle running at present, * so we can start a cycle. * Begin by setting Flash Cycle Done. */ @@ -2428,22 +2984,20 @@ static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw) } else { s32 i; - /* - * Otherwise poll for sometime so the current + /* Otherwise poll for sometime so the current * cycle has a chance to end before giving up. */ for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) { hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS); - if (hsfsts.hsf_status.flcinprog == 0) { + if (!hsfsts.hsf_status.flcinprog) { ret_val = E1000_SUCCESS; break; } usec_delay(1); } if (ret_val == E1000_SUCCESS) { - /* - * Successful in waiting for previous cycle to timeout, + /* Successful in waiting for previous cycle to timeout, * now set the Flash Cycle Done. */ hsfsts.hsf_status.flcdone = 1; @@ -2454,7 +3008,6 @@ static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw) } } -out: return ret_val; } @@ -2469,7 +3022,6 @@ static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout) { union ich8_hws_flash_ctrl hsflctl; union ich8_hws_flash_status hsfsts; - s32 ret_val = -E1000_ERR_NVM; u32 i = 0; DEBUGFUNC("e1000_flash_cycle_ich8lan"); @@ -2482,15 +3034,15 @@ static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout) /* wait till FDONE bit is set to 1 */ do { hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS); - if (hsfsts.hsf_status.flcdone == 1) + if (hsfsts.hsf_status.flcdone) break; usec_delay(1); } while (i++ < timeout); - if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0) - ret_val = E1000_SUCCESS; + if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr) + return E1000_SUCCESS; - return ret_val; + return -E1000_ERR_NVM; } /** @@ -2505,22 +3057,15 @@ static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout) static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset, u16 *data) { - s32 ret_val; - DEBUGFUNC("e1000_read_flash_word_ich8lan"); - if (!data) { - ret_val = -E1000_ERR_NVM; - goto out; - } + if (!data) + return -E1000_ERR_NVM; /* Must convert offset into bytes. */ offset <<= 1; - ret_val = e1000_read_flash_data_ich8lan(hw, offset, 2, data); - -out: - return ret_val; + return e1000_read_flash_data_ich8lan(hw, offset, 2, data); } /** @@ -2534,17 +3079,16 @@ out: static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, u8 *data) { - s32 ret_val = E1000_SUCCESS; + s32 ret_val; u16 word = 0; ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word); if (ret_val) - goto out; + return ret_val; *data = (u8)word; -out: - return ret_val; + return E1000_SUCCESS; } /** @@ -2569,7 +3113,7 @@ static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, DEBUGFUNC("e1000_read_flash_data_ich8lan"); if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK) - goto out; + return -E1000_ERR_NVM; flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) + hw->nvm.flash_base_addr; @@ -2592,8 +3136,7 @@ static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, ret_val = e1000_flash_cycle_ich8lan(hw, ICH_FLASH_READ_COMMAND_TIMEOUT); - /* - * Check if FCERR is set to 1, if set to 1, clear it + /* Check if FCERR is set to 1, if set to 1, clear it * and try the whole sequence a few more times, else * read in (shift in) the Flash Data0, the order is * least significant byte first msb to lsb @@ -2606,25 +3149,23 @@ static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, *data = (u16)(flash_data & 0x0000FFFF); break; } else { - /* - * If we've gotten here, then things are probably + /* If we've gotten here, then things are probably * completely hosed, but if the error condition is * detected, it won't hurt to give it another try... * ICH_FLASH_CYCLE_REPEAT_COUNT times. */ hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS); - if (hsfsts.hsf_status.flcerr == 1) { + if (hsfsts.hsf_status.flcerr) { /* Repeat for some time before giving up. */ continue; - } else if (hsfsts.hsf_status.flcdone == 0) { + } else if (!hsfsts.hsf_status.flcdone) { DEBUGOUT("Timeout error - flash cycle did not complete.\n"); break; } } } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); -out: return ret_val; } @@ -2642,7 +3183,6 @@ static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, { struct e1000_nvm_info *nvm = &hw->nvm; struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; - s32 ret_val = E1000_SUCCESS; u16 i; DEBUGFUNC("e1000_write_nvm_ich8lan"); @@ -2650,8 +3190,7 @@ static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || (words == 0)) { DEBUGOUT("nvm parameter(s) out of bounds\n"); - ret_val = -E1000_ERR_NVM; - goto out; + return -E1000_ERR_NVM; } nvm->ops.acquire(hw); @@ -2663,8 +3202,7 @@ static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, nvm->ops.release(hw); -out: - return ret_val; + return E1000_SUCCESS; } /** @@ -2697,8 +3235,7 @@ static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw) nvm->ops.acquire(hw); - /* - * We're writing to the opposite bank so if we're on bank 1, + /* We're writing to the opposite bank so if we're on bank 1, * write to bank 0 etc. We also need to erase the segment that * is going to be written */ @@ -2723,8 +3260,7 @@ static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw) } for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { - /* - * Determine whether to write the value stored + /* Determine whether to write the value stored * in the other NVM bank or a modified value stored * in the shadow RAM */ @@ -2738,8 +3274,7 @@ static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw) break; } - /* - * If the word is 0x13, then make sure the signature bits + /* If the word is 0x13, then make sure the signature bits * (15:14) are 11b until the commit has completed. * This will allow us to write 10b which indicates the * signature is valid. We want to do this after the write @@ -2768,8 +3303,7 @@ static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw) break; } - /* - * Don't bother writing the segment valid bits if sector + /* Don't bother writing the segment valid bits if sector * programming failed. */ if (ret_val) { @@ -2777,8 +3311,7 @@ static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw) goto release; } - /* - * Finally validate the new segment by setting bit 15:14 + /* Finally validate the new segment by setting bit 15:14 * to 10b in word 0x13 , this can be done without an * erase as well since these bits are 11 to start with * and we need to change bit 14 to 0b @@ -2795,8 +3328,7 @@ static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw) if (ret_val) goto release; - /* - * And invalidate the previously valid segment by setting + /* And invalidate the previously valid segment by setting * its signature word (0x13) high_byte to 0b. This can be * done without an erase because flash erase sets all bits * to 1's. We can write 1's to 0's without an erase @@ -2815,8 +3347,7 @@ static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw) release: nvm->ops.release(hw); - /* - * Reload the EEPROM, or else modifications will not appear + /* Reload the EEPROM, or else modifications will not appear * until after the next adapter reset. */ if (!ret_val) { @@ -2841,35 +3372,44 @@ out: **/ static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw) { - s32 ret_val = E1000_SUCCESS; + s32 ret_val; u16 data; + u16 word; + u16 valid_csum_mask; DEBUGFUNC("e1000_validate_nvm_checksum_ich8lan"); - /* - * Read 0x19 and check bit 6. If this bit is 0, the checksum - * needs to be fixed. This bit is an indication that the NVM - * was prepared by OEM software and did not calculate the - * checksum...a likely scenario. + /* Read NVM and check Invalid Image CSUM bit. If this bit is 0, + * the checksum needs to be fixed. This bit is an indication that + * the NVM was prepared by OEM software and did not calculate + * the checksum...a likely scenario. */ - ret_val = hw->nvm.ops.read(hw, 0x19, 1, &data); + switch (hw->mac.type) { + case e1000_pch_lpt: + word = NVM_COMPAT; + valid_csum_mask = NVM_COMPAT_VALID_CSUM; + break; + default: + word = NVM_FUTURE_INIT_WORD1; + valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM; + break; + } + + ret_val = hw->nvm.ops.read(hw, word, 1, &data); if (ret_val) - goto out; + return ret_val; - if ((data & 0x40) == 0) { - data |= 0x40; - ret_val = hw->nvm.ops.write(hw, 0x19, 1, &data); + if (!(data & valid_csum_mask)) { + data |= valid_csum_mask; + ret_val = hw->nvm.ops.write(hw, word, 1, &data); if (ret_val) - goto out; + return ret_val; ret_val = hw->nvm.ops.update(hw); if (ret_val) - goto out; + return ret_val; } - ret_val = e1000_validate_nvm_checksum_generic(hw); - -out: - return ret_val; + return e1000_validate_nvm_checksum_generic(hw); } /** @@ -2888,14 +3428,14 @@ static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, union ich8_hws_flash_ctrl hsflctl; u32 flash_linear_addr; u32 flash_data = 0; - s32 ret_val = -E1000_ERR_NVM; + s32 ret_val; u8 count = 0; DEBUGFUNC("e1000_write_ich8_data"); if (size < 1 || size > 2 || data > size * 0xff || offset > ICH_FLASH_LINEAR_ADDR_MASK) - goto out; + return -E1000_ERR_NVM; flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) + hw->nvm.flash_base_addr; @@ -2922,8 +3462,7 @@ static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data); - /* - * check if FCERR is set to 1 , if set to 1, clear it + /* check if FCERR is set to 1 , if set to 1, clear it * and try the whole sequence a few more times else done */ ret_val = e1000_flash_cycle_ich8lan(hw, @@ -2931,23 +3470,21 @@ static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, if (ret_val == E1000_SUCCESS) break; - /* - * If we're here, then things are most likely + /* If we're here, then things are most likely * completely hosed, but if the error condition * is detected, it won't hurt to give it another * try...ICH_FLASH_CYCLE_REPEAT_COUNT times. */ hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS); - if (hsfsts.hsf_status.flcerr == 1) + if (hsfsts.hsf_status.flcerr) /* Repeat for some time before giving up. */ continue; - if (hsfsts.hsf_status.flcdone == 0) { + if (!hsfsts.hsf_status.flcdone) { DEBUGOUT("Timeout error - flash cycle did not complete.\n"); break; } } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); -out: return ret_val; } @@ -2987,8 +3524,8 @@ static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, DEBUGFUNC("e1000_retry_write_flash_byte_ich8lan"); ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); - if (ret_val == E1000_SUCCESS) - goto out; + if (!ret_val) + return ret_val; for (program_retries = 0; program_retries < 100; program_retries++) { DEBUGOUT2("Retrying Byte %2.2X at offset %u\n", byte, offset); @@ -2997,13 +3534,10 @@ static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, if (ret_val == E1000_SUCCESS) break; } - if (program_retries == 100) { - ret_val = -E1000_ERR_NVM; - goto out; - } + if (program_retries == 100) + return -E1000_ERR_NVM; -out: - return ret_val; + return E1000_SUCCESS; } /** @@ -3022,7 +3556,7 @@ static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank) u32 flash_linear_addr; /* bank size is in 16bit words - adjust to bytes */ u32 flash_bank_size = nvm->flash_bank_size * 2; - s32 ret_val = E1000_SUCCESS; + s32 ret_val; s32 count = 0; s32 j, iteration, sector_size; @@ -3030,8 +3564,7 @@ static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank) hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS); - /* - * Determine HW Sector size: Read BERASE bits of hw flash status + /* Determine HW Sector size: Read BERASE bits of hw flash status * register * 00: The Hw sector is 256 bytes, hence we need to erase 16 * consecutive sectors. The start index for the nth Hw sector @@ -3062,8 +3595,7 @@ static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank) iteration = 1; break; default: - ret_val = -E1000_ERR_NVM; - goto out; + return -E1000_ERR_NVM; } /* Start with the base address, then add the sector offset. */ @@ -3075,10 +3607,9 @@ static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank) /* Steps */ ret_val = e1000_flash_cycle_init_ich8lan(hw); if (ret_val) - goto out; + return ret_val; - /* - * Write a value 11 (block Erase) in Flash + /* Write a value 11 (block Erase) in Flash * Cycle field in hw flash control */ hsflctl.regval = E1000_READ_FLASH_REG16(hw, @@ -3087,8 +3618,7 @@ static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank) E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); - /* - * Write the last 24 bits of an index within the + /* Write the last 24 bits of an index within the * block into Flash Linear address field in Flash * Address. */ @@ -3101,23 +3631,21 @@ static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank) if (ret_val == E1000_SUCCESS) break; - /* - * Check if FCERR is set to 1. If 1, + /* Check if FCERR is set to 1. If 1, * clear it and try the whole sequence * a few more times else Done */ hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS); - if (hsfsts.hsf_status.flcerr == 1) + if (hsfsts.hsf_status.flcerr) /* repeat for some time before giving up */ continue; - else if (hsfsts.hsf_status.flcdone == 0) - goto out; + else if (!hsfsts.hsf_status.flcdone) + return ret_val; } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT); } -out: - return ret_val; + return E1000_SUCCESS; } /** @@ -3138,14 +3666,13 @@ static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data) ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); if (ret_val) { DEBUGOUT("NVM Read Error\n"); - goto out; + return ret_val; } if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) *data = ID_LED_DEFAULT_ICH8LAN; -out: - return ret_val; + return E1000_SUCCESS; } /** @@ -3174,7 +3701,7 @@ static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw) /* Get default ID LED modes */ ret_val = hw->nvm.ops.valid_led_default(hw, &data); if (ret_val) - goto out; + return ret_val; mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL); mac->ledctl_mode1 = mac->ledctl_default; @@ -3219,8 +3746,7 @@ static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw) } } -out: - return ret_val; + return E1000_SUCCESS; } /** @@ -3228,7 +3754,7 @@ out: * @hw: pointer to the HW structure * * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability - * register, so the bus width is hard coded. + * register, so the the bus width is hard coded. **/ static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw) { @@ -3239,8 +3765,7 @@ static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw) ret_val = e1000_get_bus_info_pcie_generic(hw); - /* - * ICH devices are "PCI Express"-ish. They have + /* ICH devices are "PCI Express"-ish. They have * a configuration space, but do not contain * PCI Express Capability registers, so bus width * must be hardcoded. @@ -3261,14 +3786,13 @@ static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw) static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw) { struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; - u16 reg; - u32 ctrl, kab; + u16 kum_cfg; + u32 ctrl, reg; s32 ret_val; DEBUGFUNC("e1000_reset_hw_ich8lan"); - /* - * Prevent the PCI-E bus from sticking if there is no TLP connection + /* Prevent the PCI-E bus from sticking if there is no TLP connection * on the last TLP read/write transaction when MAC is reset. */ ret_val = e1000_disable_pcie_master_generic(hw); @@ -3278,8 +3802,7 @@ static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw) DEBUGOUT("Masking off all interrupts\n"); E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); - /* - * Disable the Transmit and Receive units. Then delay to allow + /* Disable the Transmit and Receive units. Then delay to allow * any pending transactions to complete before we hit the MAC * with the global reset. */ @@ -3299,11 +3822,11 @@ static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw) if (hw->mac.type == e1000_pchlan) { /* Save the NVM K1 bit setting*/ - ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, ®); + ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg); if (ret_val) return ret_val; - if (reg & E1000_NVM_K1_ENABLE) + if (kum_cfg & E1000_NVM_K1_ENABLE) dev_spec->nvm_k1_enabled = TRUE; else dev_spec->nvm_k1_enabled = FALSE; @@ -3312,15 +3835,13 @@ static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw) ctrl = E1000_READ_REG(hw, E1000_CTRL); if (!hw->phy.ops.check_reset_block(hw)) { - /* - * Full-chip reset requires MAC and PHY reset at the same + /* Full-chip reset requires MAC and PHY reset at the same * time to make sure the interface between MAC and the * external PHY is reset. */ ctrl |= E1000_CTRL_PHY_RST; - /* - * Gate automatic PHY configuration by hardware on + /* Gate automatic PHY configuration by hardware on * non-managed 82579 */ if ((hw->mac.type == e1000_pch2lan) && @@ -3333,21 +3854,28 @@ static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw) /* cannot issue a flush here because it hangs the hardware */ msec_delay(20); + /* Set Phy Config Counter to 50msec */ + if (hw->mac.type == e1000_pch2lan) { + reg = E1000_READ_REG(hw, E1000_FEXTNVM3); + reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK; + reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC; + E1000_WRITE_REG(hw, E1000_FEXTNVM3, reg); + } + if (!ret_val) E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex); if (ctrl & E1000_CTRL_PHY_RST) { ret_val = hw->phy.ops.get_cfg_done(hw); if (ret_val) - goto out; + return ret_val; ret_val = e1000_post_phy_reset_ich8lan(hw); if (ret_val) - goto out; + return ret_val; } - /* - * For PCH, this write will make sure that any noise + /* For PCH, this write will make sure that any noise * will be detected as a CRC error and be dropped rather than show up * as a bad packet to the DMA engine. */ @@ -3357,12 +3885,11 @@ static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw) E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); E1000_READ_REG(hw, E1000_ICR); - kab = E1000_READ_REG(hw, E1000_KABGTXD); - kab |= E1000_KABGTXD_BGSQLBIAS; - E1000_WRITE_REG(hw, E1000_KABGTXD, kab); + reg = E1000_READ_REG(hw, E1000_KABGTXD); + reg |= E1000_KABGTXD_BGSQLBIAS; + E1000_WRITE_REG(hw, E1000_KABGTXD, reg); -out: - return ret_val; + return E1000_SUCCESS; } /** @@ -3390,9 +3917,9 @@ static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw) /* Initialize identification LED */ ret_val = mac->ops.id_led_init(hw); + /* An error is not fatal and we should not stop init due to this */ if (ret_val) DEBUGOUT("Error initializing identification LED\n"); - /* This is not fatal and we should not stop init due to this */ /* Setup the receive address. */ e1000_init_rx_addrs_generic(hw, mac->rar_entry_count); @@ -3402,8 +3929,7 @@ static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw) for (i = 0; i < mac->mta_reg_count; i++) E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); - /* - * The 82578 Rx buffer will stall if wakeup is enabled in host and + /* The 82578 Rx buffer will stall if wakeup is enabled in host and * the ME. Disable wakeup by clearing the host wakeup bit. * Reset the phy after disabling host wakeup to reset the Rx buffer. */ @@ -3433,8 +3959,7 @@ static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw) E1000_TXDCTL_MAX_TX_DESC_PREFETCH; E1000_WRITE_REG(hw, E1000_TXDCTL(1), txdctl); - /* - * ICH8 has opposite polarity of no_snoop bits. + /* ICH8 has opposite polarity of no_snoop bits. * By default, we should use snoop behavior. */ if (mac->type == e1000_ich8lan) @@ -3447,8 +3972,7 @@ static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw) ctrl_ext |= E1000_CTRL_EXT_RO_DIS; E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); - /* - * Clear all of the statistics registers (clear on read). It is + /* Clear all of the statistics registers (clear on read). It is * important that we do this after we have tried to establish link * because the symbol error count will increment wildly if there * is no link. @@ -3457,6 +3981,7 @@ static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw) return ret_val; } + /** * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits * @hw: pointer to the HW structure @@ -3511,14 +4036,29 @@ static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw) E1000_WRITE_REG(hw, E1000_STATUS, reg); } - /* - * work-around descriptor data corruption issue during nfs v2 udp + /* work-around descriptor data corruption issue during nfs v2 udp * traffic, just disable the nfs filtering capability */ reg = E1000_READ_REG(hw, E1000_RFCTL); reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS); + /* Disable IPv6 extension header parsing because some malformed + * IPv6 headers can hang the Rx. + */ + if (hw->mac.type == e1000_ich8lan) + reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS); E1000_WRITE_REG(hw, E1000_RFCTL, reg); + /* Enable ECC on Lynxpoint */ + if (hw->mac.type == e1000_pch_lpt) { + reg = E1000_READ_REG(hw, E1000_PBECCSTS); + reg |= E1000_PBECCSTS_ECC_ENABLE; + E1000_WRITE_REG(hw, E1000_PBECCSTS, reg); + + reg = E1000_READ_REG(hw, E1000_CTRL); + reg |= E1000_CTRL_MEHE; + E1000_WRITE_REG(hw, E1000_CTRL, reg); + } + return; } @@ -3534,23 +4074,21 @@ static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw) **/ static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw) { - s32 ret_val = E1000_SUCCESS; + s32 ret_val; DEBUGFUNC("e1000_setup_link_ich8lan"); if (hw->phy.ops.check_reset_block(hw)) - goto out; + return E1000_SUCCESS; - /* - * ICH parts do not have a word in the NVM to determine + /* ICH parts do not have a word in the NVM to determine * the default flow control setting, so we explicitly * set it to full. */ if (hw->fc.requested_mode == e1000_fc_default) hw->fc.requested_mode = e1000_fc_full; - /* - * Save off the requested flow control mode for use later. Depending + /* Save off the requested flow control mode for use later. Depending * on the link partner's capabilities, we may or may not use this mode. */ hw->fc.current_mode = hw->fc.requested_mode; @@ -3561,11 +4099,12 @@ static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw) /* Continue to configure the copper link. */ ret_val = hw->mac.ops.setup_physical_interface(hw); if (ret_val) - goto out; + return ret_val; E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time); if ((hw->phy.type == e1000_phy_82578) || (hw->phy.type == e1000_phy_82579) || + (hw->phy.type == e1000_phy_i217) || (hw->phy.type == e1000_phy_82577)) { E1000_WRITE_REG(hw, E1000_FCRTV_PCH, hw->fc.refresh_time); @@ -3573,13 +4112,10 @@ static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw) PHY_REG(BM_PORT_CTRL_PAGE, 27), hw->fc.pause_time); if (ret_val) - goto out; + return ret_val; } - ret_val = e1000_set_fc_watermarks_generic(hw); - -out: - return ret_val; + return e1000_set_fc_watermarks_generic(hw); } /** @@ -3603,50 +4139,49 @@ static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw) ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); E1000_WRITE_REG(hw, E1000_CTRL, ctrl); - /* - * Set the mac to wait the maximum time between each iteration + /* Set the mac to wait the maximum time between each iteration * and increase the max iterations when polling the phy; * this fixes erroneous timeouts at 10Mbps. */ ret_val = e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF); if (ret_val) - goto out; + return ret_val; ret_val = e1000_read_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_INBAND_PARAM, ®_data); if (ret_val) - goto out; + return ret_val; reg_data |= 0x3F; ret_val = e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_INBAND_PARAM, reg_data); if (ret_val) - goto out; + return ret_val; switch (hw->phy.type) { case e1000_phy_igp_3: ret_val = e1000_copper_link_setup_igp(hw); if (ret_val) - goto out; + return ret_val; break; case e1000_phy_bm: case e1000_phy_82578: ret_val = e1000_copper_link_setup_m88(hw); if (ret_val) - goto out; + return ret_val; break; case e1000_phy_82577: case e1000_phy_82579: ret_val = e1000_copper_link_setup_82577(hw); if (ret_val) - goto out; + return ret_val; break; case e1000_phy_ife: ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, ®_data); if (ret_val) - goto out; + return ret_val; reg_data &= ~IFE_PMC_AUTO_MDIX; @@ -3665,15 +4200,40 @@ static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw) ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL, reg_data); if (ret_val) - goto out; + return ret_val; break; default: break; } - ret_val = e1000_setup_copper_link_generic(hw); -out: - return ret_val; + return e1000_setup_copper_link_generic(hw); +} + +/** + * e1000_setup_copper_link_pch_lpt - Configure MAC/PHY interface + * @hw: pointer to the HW structure + * + * Calls the PHY specific link setup function and then calls the + * generic setup_copper_link to finish configuring the link for + * Lynxpoint PCH devices + **/ +static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw) +{ + u32 ctrl; + s32 ret_val; + + DEBUGFUNC("e1000_setup_copper_link_pch_lpt"); + + ctrl = E1000_READ_REG(hw, E1000_CTRL); + ctrl |= E1000_CTRL_SLU; + ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); + E1000_WRITE_REG(hw, E1000_CTRL, ctrl); + + ret_val = e1000_copper_link_setup_82577(hw); + if (ret_val) + return ret_val; + + return e1000_setup_copper_link_generic(hw); } /** @@ -3695,7 +4255,7 @@ static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed, ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex); if (ret_val) - goto out; + return ret_val; if ((hw->mac.type == e1000_ich8lan) && (hw->phy.type == e1000_phy_igp_3) && @@ -3703,7 +4263,6 @@ static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed, ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw); } -out: return ret_val; } @@ -3726,41 +4285,36 @@ static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw) { struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; u32 phy_ctrl; - s32 ret_val = E1000_SUCCESS; + s32 ret_val; u16 i, data; bool link; DEBUGFUNC("e1000_kmrn_lock_loss_workaround_ich8lan"); if (!dev_spec->kmrn_lock_loss_workaround_enabled) - goto out; + return E1000_SUCCESS; - /* - * Make sure link is up before proceeding. If not just return. + /* Make sure link is up before proceeding. If not just return. * Attempting this while link is negotiating fouled up link * stability */ ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); - if (!link) { - ret_val = E1000_SUCCESS; - goto out; - } + if (!link) + return E1000_SUCCESS; for (i = 0; i < 10; i++) { /* read once to clear */ ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data); if (ret_val) - goto out; + return ret_val; /* and again to get new status */ ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data); if (ret_val) - goto out; + return ret_val; /* check for PCS lock */ - if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS)) { - ret_val = E1000_SUCCESS; - goto out; - } + if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS)) + return E1000_SUCCESS; /* Issue PHY reset */ hw->phy.ops.reset(hw); @@ -3772,17 +4326,13 @@ static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw) E1000_PHY_CTRL_NOND0A_GBE_DISABLE); E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); - /* - * Call gig speed drop workaround on Gig disable before accessing + /* Call gig speed drop workaround on Gig disable before accessing * any PHY registers */ e1000_gig_downshift_workaround_ich8lan(hw); /* unable to acquire PCS lock */ - ret_val = -E1000_ERR_PHY; - -out: - return ret_val; + return -E1000_ERR_PHY; } /** @@ -3829,7 +4379,7 @@ void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw) DEBUGFUNC("e1000_igp3_phy_powerdown_workaround_ich8lan"); if (hw->phy.type != e1000_phy_igp_3) - goto out; + return; /* Try the workaround twice (if needed) */ do { @@ -3839,8 +4389,7 @@ void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw) E1000_PHY_CTRL_NOND0A_GBE_DISABLE); E1000_WRITE_REG(hw, E1000_PHY_CTRL, reg); - /* - * Call gig speed drop workaround on Gig disable before + /* Call gig speed drop workaround on Gig disable before * accessing any PHY registers */ if (hw->mac.type == e1000_ich8lan) @@ -3863,9 +4412,6 @@ void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw) E1000_WRITE_REG(hw, E1000_CTRL, reg | E1000_CTRL_PHY_RST); retry++; } while (retry); - -out: - return; } /** @@ -3880,31 +4426,28 @@ out: **/ void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw) { - s32 ret_val = E1000_SUCCESS; + s32 ret_val; u16 reg_data; DEBUGFUNC("e1000_gig_downshift_workaround_ich8lan"); if ((hw->mac.type != e1000_ich8lan) || (hw->phy.type == e1000_phy_ife)) - goto out; + return; ret_val = e1000_read_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, ®_data); if (ret_val) - goto out; + return; reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK; ret_val = e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, reg_data); if (ret_val) - goto out; + return; reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK; - ret_val = e1000_write_kmrn_reg_generic(hw, - E1000_KMRNCTRLSTA_DIAG_OFFSET, - reg_data); -out: - return; + e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, + reg_data); } /** @@ -3917,9 +4460,13 @@ out: * the LPLU setting in the NVM or custom setting. For PCH and newer parts, * the OEM bits PHY register (LED, GbE disable and LPLU configurations) also * needs to be written. + * Parts that support (and are linked to a partner which support) EEE in + * 100Mbps should disable LPLU since 100Mbps w/ EEE requires less power + * than 10Mbps w/o EEE. **/ void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw) { + struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; u32 phy_ctrl; s32 ret_val; @@ -3927,13 +4474,96 @@ void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw) phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL); phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE; + + if (hw->phy.type == e1000_phy_i217) { + u16 phy_reg, device_id = hw->device_id; + + if ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) || + (device_id == E1000_DEV_ID_PCH_LPTLP_I218_V)) { + u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6); + + E1000_WRITE_REG(hw, E1000_FEXTNVM6, + fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK); + } + + ret_val = hw->phy.ops.acquire(hw); + if (ret_val) + goto out; + + if (!dev_spec->eee_disable) { + u16 eee_advert; + + ret_val = + e1000_read_emi_reg_locked(hw, + I217_EEE_ADVERTISEMENT, + &eee_advert); + if (ret_val) + goto release; + + /* Disable LPLU if both link partners support 100BaseT + * EEE and 100Full is advertised on both ends of the + * link. + */ + if ((eee_advert & I82579_EEE_100_SUPPORTED) && + (dev_spec->eee_lp_ability & + I82579_EEE_100_SUPPORTED) && + (hw->phy.autoneg_advertised & ADVERTISE_100_FULL)) + phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU | + E1000_PHY_CTRL_NOND0A_LPLU); + } + + /* For i217 Intel Rapid Start Technology support, + * when the system is going into Sx and no manageability engine + * is present, the driver must configure proxy to reset only on + * power good. LPI (Low Power Idle) state must also reset only + * on power good, as well as the MTA (Multicast table array). + * The SMBus release must also be disabled on LCD reset. + */ + if (!(E1000_READ_REG(hw, E1000_FWSM) & + E1000_ICH_FWSM_FW_VALID)) { + /* Enable proxy to reset only on power good. */ + hw->phy.ops.read_reg_locked(hw, I217_PROXY_CTRL, + &phy_reg); + phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE; + hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL, + phy_reg); + + /* Set bit enable LPI (EEE) to reset only on + * power good. + */ + hw->phy.ops.read_reg_locked(hw, I217_SxCTRL, &phy_reg); + phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET; + hw->phy.ops.write_reg_locked(hw, I217_SxCTRL, phy_reg); + + /* Disable the SMB release on LCD reset. */ + hw->phy.ops.read_reg_locked(hw, I217_MEMPWR, &phy_reg); + phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE; + hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg); + } + + /* Enable MTA to reset for Intel Rapid Start Technology + * Support + */ + hw->phy.ops.read_reg_locked(hw, I217_CGFREG, &phy_reg); + phy_reg |= I217_CGFREG_ENABLE_MTA_RESET; + hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg); + +release: + hw->phy.ops.release(hw); + } +out: E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); + if (hw->mac.type == e1000_ich8lan) e1000_gig_downshift_workaround_ich8lan(hw); if (hw->mac.type >= e1000_pchlan) { e1000_oem_bits_config_ich8lan(hw, FALSE); - e1000_phy_hw_reset_ich8lan(hw); + + /* Reset PHY to activate OEM bits on 82577/8 */ + if (hw->mac.type == e1000_pchlan) + e1000_phy_hw_reset_generic(hw); + ret_val = hw->phy.ops.acquire(hw); if (ret_val) return; @@ -3952,48 +4582,64 @@ void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw) * on which PHY resets are not blocked, if the PHY registers cannot be * accessed properly by the s/w toggle the LANPHYPC value to power cycle * the PHY. + * On i217, setup Intel Rapid Start Technology. **/ void e1000_resume_workarounds_pchlan(struct e1000_hw *hw) { - u16 phy_id1, phy_id2; s32 ret_val; DEBUGFUNC("e1000_resume_workarounds_pchlan"); - if ((hw->mac.type != e1000_pch2lan) || - hw->phy.ops.check_reset_block(hw)) + if (hw->mac.type < e1000_pch2lan) return; - ret_val = hw->phy.ops.acquire(hw); + ret_val = e1000_init_phy_workarounds_pchlan(hw); if (ret_val) { - DEBUGOUT("Failed to acquire PHY semaphore in resume\n"); + DEBUGOUT1("Failed to init PHY flow ret_val=%d\n", ret_val); return; } - /* Test access to the PHY registers by reading the ID regs */ - ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID1, &phy_id1); - if (ret_val) - goto release; - ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID2, &phy_id2); - if (ret_val) - goto release; - - if (hw->phy.id == ((u32)(phy_id1 << 16) | - (u32)(phy_id2 & PHY_REVISION_MASK))) - goto release; + /* For i217 Intel Rapid Start Technology support when the system + * is transitioning from Sx and no manageability engine is present + * configure SMBus to restore on reset, disable proxy, and enable + * the reset on MTA (Multicast table array). + */ + if (hw->phy.type == e1000_phy_i217) { + u16 phy_reg; - e1000_toggle_lanphypc_value_ich8lan(hw); + ret_val = hw->phy.ops.acquire(hw); + if (ret_val) { + DEBUGOUT("Failed to setup iRST\n"); + return; + } - hw->phy.ops.release(hw); - msec_delay(50); - hw->phy.ops.reset(hw); - msec_delay(50); - return; + if (!(E1000_READ_REG(hw, E1000_FWSM) & + E1000_ICH_FWSM_FW_VALID)) { + /* Restore clear on SMB if no manageability engine + * is present + */ + ret_val = hw->phy.ops.read_reg_locked(hw, I217_MEMPWR, + &phy_reg); + if (ret_val) + goto release; + phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE; + hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg); + /* Disable Proxy */ + hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL, 0); + } + /* Enable reset on MTA */ + ret_val = hw->phy.ops.read_reg_locked(hw, I217_CGFREG, + &phy_reg); + if (ret_val) + goto release; + phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET; + hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg); release: - hw->phy.ops.release(hw); - - return; + if (ret_val) + DEBUGOUT1("Error %d in resume workarounds\n", ret_val); + hw->phy.ops.release(hw); + } } /** @@ -4091,8 +4737,7 @@ static s32 e1000_led_on_pchlan(struct e1000_hw *hw) DEBUGFUNC("e1000_led_on_pchlan"); - /* - * If no link, then turn LED on by setting the invert bit + /* If no link, then turn LED on by setting the invert bit * for each LED that's mode is "link_up" in ledctl_mode2. */ if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) { @@ -4124,8 +4769,7 @@ static s32 e1000_led_off_pchlan(struct e1000_hw *hw) DEBUGFUNC("e1000_led_off_pchlan"); - /* - * If no link, then turn LED off by clearing the invert bit + /* If no link, then turn LED off by clearing the invert bit * for each LED that's mode is "link_up" in ledctl_mode1. */ if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) { @@ -4172,8 +4816,7 @@ static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw) } else { ret_val = e1000_get_auto_rd_done_generic(hw); if (ret_val) { - /* - * When auto config read does not complete, do not + /* When auto config read does not complete, do not * return with an error. This can happen in situations * where there is no eeprom and prevents getting link. */ @@ -4191,7 +4834,7 @@ static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw) /* If EEPROM is not marked present, init the IGP 3 PHY manually */ if (hw->mac.type <= e1000_ich9lan) { - if (((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0) && + if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) && (hw->phy.type == e1000_phy_igp_3)) { e1000_phy_init_script_igp3(hw); } @@ -4256,6 +4899,7 @@ static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw) /* Clear PHY statistics registers */ if ((hw->phy.type == e1000_phy_82578) || (hw->phy.type == e1000_phy_82579) || + (hw->phy.type == e1000_phy_i217) || (hw->phy.type == e1000_phy_82577)) { ret_val = hw->phy.ops.acquire(hw); if (ret_val) diff --git a/sys/dev/e1000/e1000_ich8lan.h b/sys/dev/e1000/e1000_ich8lan.h index 2eccb30..bf92898 100644 --- a/sys/dev/e1000/e1000_ich8lan.h +++ b/sys/dev/e1000/e1000_ich8lan.h @@ -1,6 +1,6 @@ /****************************************************************************** - Copyright (c) 2001-2011, Intel Corporation + Copyright (c) 2001-2013, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without @@ -59,12 +59,8 @@ #define ICH_FLASH_SEG_SIZE_4K 4096 #define ICH_FLASH_SEG_SIZE_8K 8192 #define ICH_FLASH_SEG_SIZE_64K 65536 -#define ICH_FLASH_SECTOR_SIZE 4096 - -#define ICH_FLASH_REG_MAPSIZE 0x00A0 #define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */ -#define E1000_ICH_FWSM_DISSW 0x10000000 /* FW Disables SW Writes */ /* FW established a valid mode */ #define E1000_ICH_FWSM_FW_VALID 0x00008000 #define E1000_ICH_FWSM_PCIM2PCI 0x01000000 /* ME PCIm-to-PCI active */ @@ -72,23 +68,12 @@ #define E1000_ICH_MNG_IAMT_MODE 0x2 -#define E1000_FWSM_PROXY_MODE 0x00000008 /* FW is in proxy mode */ -#define E1000_FWSM_MEMC 0x00000010 /* ME Messaging capable */ +#define E1000_FWSM_WLOCK_MAC_MASK 0x0380 +#define E1000_FWSM_WLOCK_MAC_SHIFT 7 /* Shared Receive Address Registers */ -#define E1000_SHRAL(_i) (0x05438 + ((_i) * 8)) -#define E1000_SHRAH(_i) (0x0543C + ((_i) * 8)) -#define E1000_SHRAH_AV 0x80000000 /* Addr Valid bit */ -#define E1000_SHRAH_MAV 0x40000000 /* Multicast Addr Valid bit */ - -#define E1000_H2ME 0x05B50 /* Host to ME */ -#define E1000_H2ME_LSECREQ 0x00000001 /* Linksec Request */ -#define E1000_H2ME_LSECA 0x00000002 /* Linksec Active */ -#define E1000_H2ME_LSECSF 0x00000004 /* Linksec Failed */ -#define E1000_H2ME_LSECD 0x00000008 /* Linksec Disabled */ -#define E1000_H2ME_SLCAPD 0x00000010 /* Start LCAPD */ -#define E1000_H2ME_IPV4_ARP_EN 0x00000020 /* Arp Offload enable bit */ -#define E1000_H2ME_IPV6_NS_EN 0x00000040 /* NS Offload enable bit */ +#define E1000_SHRAL_PCH_LPT(_i) (0x05408 + ((_i) * 8)) +#define E1000_SHRAH_PCH_LPT(_i) (0x0540C + ((_i) * 8)) #define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \ (ID_LED_OFF1_OFF2 << 8) | \ @@ -105,27 +90,30 @@ #define E1000_FEXTNVM_SW_CONFIG 1 #define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M */ +#define E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK 0x0C000000 +#define E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC 0x08000000 + #define E1000_FEXTNVM4_BEACON_DURATION_MASK 0x7 #define E1000_FEXTNVM4_BEACON_DURATION_8USEC 0x7 #define E1000_FEXTNVM4_BEACON_DURATION_16USEC 0x3 +#define E1000_FEXTNVM6_REQ_PLL_CLK 0x00000100 + #define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL #define E1000_ICH_RAR_ENTRIES 7 #define E1000_PCH2_RAR_ENTRIES 5 /* RAR[0], SHRA[0-3] */ +#define E1000_PCH_LPT_RAR_ENTRIES 12 /* RAR[0], SHRA[0-10] */ #define PHY_PAGE_SHIFT 5 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \ ((reg) & MAX_PHY_REG_ADDRESS)) #define IGP3_KMRN_DIAG PHY_REG(770, 19) /* KMRN Diagnostic */ #define IGP3_VR_CTRL PHY_REG(776, 18) /* Voltage Regulator Control */ -#define IGP3_CAPABILITY PHY_REG(776, 19) /* Capability */ -#define IGP3_PM_CTRL PHY_REG(769, 20) /* Power Management Control */ #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002 #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300 #define IGP3_VR_CTRL_MODE_SHUTDOWN 0x0200 -#define IGP3_PM_CTRL_FORCE_PWR_DOWN 0x0020 /* PHY Wakeup Registers and defines */ #define BM_PORT_GEN_CFG PHY_REG(BM_PORT_CTRL_PAGE, 17) @@ -138,14 +126,6 @@ #define BM_RAR_H(_i) (BM_PHY_REG(BM_WUC_PAGE, 18 + ((_i) << 2))) #define BM_RAR_CTRL(_i) (BM_PHY_REG(BM_WUC_PAGE, 19 + ((_i) << 2))) #define BM_MTA(_i) (BM_PHY_REG(BM_WUC_PAGE, 128 + ((_i) << 1))) -#define BM_IPAV (BM_PHY_REG(BM_WUC_PAGE, 64)) -#define BM_IP4AT_L(_i) (BM_PHY_REG(BM_WUC_PAGE, 82 + ((_i) * 2))) -#define BM_IP4AT_H(_i) (BM_PHY_REG(BM_WUC_PAGE, 83 + ((_i) * 2))) - -#define BM_SHRAL_LOWER(_i) (BM_PHY_REG(BM_WUC_PAGE, 44 + ((_i) * 4))) -#define BM_SHRAL_UPPER(_i) (BM_PHY_REG(BM_WUC_PAGE, 45 + ((_i) * 4))) -#define BM_SHRAH_LOWER(_i) (BM_PHY_REG(BM_WUC_PAGE, 46 + ((_i) * 4))) -#define BM_SHRAH_UPPER(_i) (BM_PHY_REG(BM_WUC_PAGE, 47 + ((_i) * 4))) #define BM_RCTL_UPE 0x0001 /* Unicast Promiscuous Mode */ #define BM_RCTL_MPE 0x0002 /* Multicast Promiscuous Mode */ @@ -177,28 +157,28 @@ #define E1000_FCRTV_PCH 0x05F40 /* PCH Flow Control Refresh Timer Value */ -/* - * For ICH, the name used for NVM word 17h is LED1 Config. - * For PCH, the word was re-named to OEM Config. - */ -#define E1000_NVM_LED1_CONFIG 0x17 /* NVM LED1/LPLU Config Word */ -#define E1000_NVM_LED1_CONFIG_LPLU_NONDOA 0x0400 /* NVM LPLU in non-D0a Bit */ -#define E1000_NVM_OEM_CONFIG E1000_NVM_LED1_CONFIG -#define E1000_NVM_OEM_CONFIG_LPLU_NONDOA E1000_NVM_LED1_CONFIG_LPLU_NONDOA - #define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */ #define E1000_NVM_K1_ENABLE 0x1 /* NVM Enable K1 bit */ +/* SMBus Control Phy Register */ +#define CV_SMB_CTRL PHY_REG(769, 23) +#define CV_SMB_CTRL_FORCE_SMBUS 0x0001 + /* SMBus Address Phy Register */ #define HV_SMB_ADDR PHY_REG(768, 26) #define HV_SMB_ADDR_MASK 0x007F #define HV_SMB_ADDR_PEC_EN 0x0200 #define HV_SMB_ADDR_VALID 0x0080 +#define HV_SMB_ADDR_FREQ_MASK 0x1100 +#define HV_SMB_ADDR_FREQ_LOW_SHIFT 8 +#define HV_SMB_ADDR_FREQ_HIGH_SHIFT 12 /* Strapping Option Register - RO */ #define E1000_STRAP 0x0000C #define E1000_STRAP_SMBUS_ADDRESS_MASK 0x00FE0000 #define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17 +#define E1000_STRAP_SMT_FREQ_MASK 0x00003000 +#define E1000_STRAP_SMT_FREQ_SHIFT 12 /* OEM Bits Phy Register */ #define HV_OEM_BITS PHY_REG(768, 25) @@ -206,8 +186,6 @@ #define HV_OEM_BITS_GBE_DIS 0x0040 /* Gigabit Disable */ #define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */ -#define LCD_CFG_PHY_ADDR_BIT 0x0020 /* Phy addr bit from LCD Config word */ - /* KMRN Mode Control */ #define HV_KMRN_MODE_CTRL PHY_REG(769, 16) #define HV_KMRN_MDIO_SLOW 0x0400 @@ -219,47 +197,73 @@ /* PHY Power Management Control */ #define HV_PM_CTRL PHY_REG(770, 17) +#define HV_PM_CTRL_PLL_STOP_IN_K1_GIGA 0x100 #define SW_FLAG_TIMEOUT 1000 /* SW Semaphore flag timeout in ms */ /* PHY Low Power Idle Control */ #define I82579_LPI_CTRL PHY_REG(772, 20) +#define I82579_LPI_CTRL_100_ENABLE 0x2000 +#define I82579_LPI_CTRL_1000_ENABLE 0x4000 #define I82579_LPI_CTRL_ENABLE_MASK 0x6000 #define I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT 0x80 -/* EMI Registers */ +/* Extended Management Interface (EMI) Registers */ #define I82579_EMI_ADDR 0x10 #define I82579_EMI_DATA 0x11 #define I82579_LPI_UPDATE_TIMER 0x4805 /* in 40ns units + 40 ns base value */ -#define I82579_MSE_THRESHOLD 0x084F /* Mean Square Error Threshold */ +#define I82579_MSE_THRESHOLD 0x084F /* 82579 Mean Square Error Threshold */ +#define I82577_MSE_THRESHOLD 0x0887 /* 82577 Mean Square Error Threshold */ #define I82579_MSE_LINK_DOWN 0x2411 /* MSE count before dropping link */ - -/* - * Additional interrupts need to be handled for ICH family: - * DSW = The FW changed the status of the DISSW bit in FWSM - * PHYINT = The LAN connected device generates an interrupt - * EPRST = Manageability reset event - */ -#define IMS_ICH_ENABLE_MASK (\ - E1000_IMS_DSW | \ - E1000_IMS_PHYINT | \ - E1000_IMS_EPRST) - -/* Additional interrupt register bit definitions */ -#define E1000_ICR_LSECPNC 0x00004000 /* PN threshold - client */ -#define E1000_IMS_LSECPNC E1000_ICR_LSECPNC /* PN threshold - client */ -#define E1000_ICS_LSECPNC E1000_ICR_LSECPNC /* PN threshold - client */ - -/* Security Processing bit Indication */ -#define E1000_RXDEXT_LINKSEC_STATUS_LSECH 0x01000000 -#define E1000_RXDEXT_LINKSEC_ERROR_BIT_MASK 0x60000000 -#define E1000_RXDEXT_LINKSEC_ERROR_NO_SA_MATCH 0x20000000 -#define E1000_RXDEXT_LINKSEC_ERROR_REPLAY_ERROR 0x40000000 -#define E1000_RXDEXT_LINKSEC_ERROR_BAD_SIG 0x60000000 +#define I82579_RX_CONFIG 0x3412 /* Receive configuration */ +#define I82579_EEE_PCS_STATUS 0x182D /* IEEE MMD Register 3.1 >> 8 */ +#define I82579_EEE_CAPABILITY 0x0410 /* IEEE MMD Register 3.20 */ +#define I82579_EEE_ADVERTISEMENT 0x040E /* IEEE MMD Register 7.60 */ +#define I82579_EEE_LP_ABILITY 0x040F /* IEEE MMD Register 7.61 */ +#define I82579_EEE_100_SUPPORTED (1 << 1) /* 100BaseTx EEE supported */ +#define I82579_EEE_1000_SUPPORTED (1 << 2) /* 1000BaseTx EEE supported */ +#define I217_EEE_PCS_STATUS 0x9401 /* IEEE MMD Register 3.1 */ +#define I217_EEE_CAPABILITY 0x8000 /* IEEE MMD Register 3.20 */ +#define I217_EEE_ADVERTISEMENT 0x8001 /* IEEE MMD Register 7.60 */ +#define I217_EEE_LP_ABILITY 0x8002 /* IEEE MMD Register 7.61 */ + +#define E1000_EEE_RX_LPI_RCVD 0x0400 /* Tx LP idle received */ +#define E1000_EEE_TX_LPI_RCVD 0x0800 /* Rx LP idle received */ + +/* Intel Rapid Start Technology Support */ +#define I217_PROXY_CTRL BM_PHY_REG(BM_WUC_PAGE, 70) +#define I217_PROXY_CTRL_AUTO_DISABLE 0x0080 +#define I217_SxCTRL PHY_REG(BM_PORT_CTRL_PAGE, 28) +#define I217_SxCTRL_ENABLE_LPI_RESET 0x1000 +#define I217_CGFREG PHY_REG(772, 29) +#define I217_CGFREG_ENABLE_MTA_RESET 0x0002 +#define I217_MEMPWR PHY_REG(772, 26) +#define I217_MEMPWR_DISABLE_SMB_RELEASE 0x0010 /* Receive Address Initial CRC Calculation */ #define E1000_PCH_RAICC(_n) (0x05F50 + ((_n) * 4)) +/* Latency Tolerance Reporting */ +#define E1000_LTRV 0x000F8 +#define E1000_LTRV_VALUE_MASK 0x000003FF +#define E1000_LTRV_SCALE_MAX 5 +#define E1000_LTRV_SCALE_FACTOR 5 +#define E1000_LTRV_SCALE_SHIFT 10 +#define E1000_LTRV_SCALE_MASK 0x00001C00 +#define E1000_LTRV_REQ_SHIFT 15 +#define E1000_LTRV_NOSNOOP_SHIFT 16 +#define E1000_LTRV_SEND (1 << 30) + +/* Proprietary Latency Tolerance Reporting PCI Capability */ +#define E1000_PCI_LTR_CAP_LPT 0xA8 + +/* OBFF Control & Threshold Defines */ +#define E1000_SVCR_OFF_EN 0x00000001 +#define E1000_SVCR_OFF_MASKINT 0x00001000 +#define E1000_SVCR_OFF_TIMER_MASK 0xFFFF0000 +#define E1000_SVCR_OFF_TIMER_SHIFT 16 +#define E1000_SVT_OFF_HWM_MASK 0x0000001F + void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw, bool state); void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw); @@ -269,4 +273,5 @@ void e1000_resume_workarounds_pchlan(struct e1000_hw *hw); s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable); void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw); s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable); -#endif +s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data); +#endif /* _E1000_ICH8LAN_H_ */ diff --git a/sys/dev/e1000/e1000_mac.c b/sys/dev/e1000/e1000_mac.c index 95d6873..9e6b30c 100644 --- a/sys/dev/e1000/e1000_mac.c +++ b/sys/dev/e1000/e1000_mac.c @@ -1,6 +1,6 @@ /****************************************************************************** - Copyright (c) 2001-2012, Intel Corporation + Copyright (c) 2001-2013, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without @@ -70,12 +70,9 @@ void e1000_init_mac_ops_generic(struct e1000_hw *hw) mac->ops.setup_link = e1000_null_ops_generic; mac->ops.get_link_up_info = e1000_null_link_info; mac->ops.check_for_link = e1000_null_ops_generic; - mac->ops.wait_autoneg = e1000_wait_autoneg_generic; + mac->ops.set_obff_timer = e1000_null_set_obff_timer; /* Management */ mac->ops.check_mng_mode = e1000_null_mng_mode; - mac->ops.mng_host_if_write = e1000_mng_host_if_write_generic; - mac->ops.mng_write_cmd_header = e1000_mng_write_cmd_header_generic; - mac->ops.mng_enable_host_if = e1000_mng_enable_host_if_generic; /* VLAN, MC, etc. */ mac->ops.update_mc_addr_list = e1000_null_update_mc; mac->ops.clear_vfta = e1000_null_mac_generic; @@ -118,8 +115,7 @@ s32 e1000_null_link_info(struct e1000_hw *hw, u16 *s, u16 *d) * e1000_null_mng_mode - No-op function, return FALSE * @hw: pointer to the HW structure **/ -bool e1000_null_mng_mode(struct e1000_hw *hw) -{ +bool e1000_null_mng_mode(struct e1000_hw *hw) { DEBUGFUNC("e1000_null_mng_mode"); return FALSE; } @@ -155,6 +151,16 @@ void e1000_null_rar_set(struct e1000_hw *hw, u8 *h, u32 a) } /** + * e1000_null_set_obff_timer - No-op function, return 0 + * @hw: pointer to the HW structure + **/ +s32 e1000_null_set_obff_timer(struct e1000_hw *hw, u32 a) +{ + DEBUGFUNC("e1000_null_set_obff_timer"); + return E1000_SUCCESS; +} + +/** * e1000_get_bus_info_pci_generic - Get PCI(x) bus information * @hw: pointer to the HW structure * @@ -268,8 +274,7 @@ static void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw) struct e1000_bus_info *bus = &hw->bus; u32 reg; - /* - * The status register reports the correct function number + /* The status register reports the correct function number * for the device regardless of function swap state. */ reg = E1000_READ_REG(hw, E1000_STATUS); @@ -389,7 +394,7 @@ void e1000_init_rx_addrs_generic(struct e1000_hw *hw, u16 rar_count) s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw) { u32 i; - s32 ret_val = E1000_SUCCESS; + s32 ret_val; u16 offset, nvm_alt_mac_addr_offset, nvm_data; u8 alt_mac_addr[ETH_ADDR_LEN]; @@ -403,8 +408,7 @@ s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw) if ((hw->mac.type < e1000_82571) || (hw->mac.type == e1000_82573)) return E1000_SUCCESS; - /* - * Alternate MAC address is handled by the option ROM for 82580 + /* Alternate MAC address is handled by the option ROM for 82580 * and newer. SW support not required. */ if (hw->mac.type >= e1000_82580) @@ -447,8 +451,7 @@ s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw) return E1000_SUCCESS; } - /* - * We have a valid alternate MAC address, and we want to treat it the + /* We have a valid alternate MAC address, and we want to treat it the * same as the normal permanent MAC address stored by the HW into the * RAR. Do this by mapping this address into RAR0. */ @@ -472,8 +475,7 @@ static void e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index) DEBUGFUNC("e1000_rar_set_generic"); - /* - * HW expects these in little endian so we reverse the byte order + /* HW expects these in little endian so we reverse the byte order * from network order (big endian) to little endian */ rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) | @@ -485,8 +487,7 @@ static void e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index) if (rar_low || rar_high) rar_high |= E1000_RAH_AV; - /* - * Some bridges will combine consecutive 32-bit writes into + /* Some bridges will combine consecutive 32-bit writes into * a single burst write, which will malfunction on some parts. * The flushes avoid this. */ @@ -514,15 +515,13 @@ u32 e1000_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr) /* Register count multiplied by bits per register */ hash_mask = (hw->mac.mta_reg_count * 32) - 1; - /* - * For a mc_filter_type of 0, bit_shift is the number of left-shifts + /* For a mc_filter_type of 0, bit_shift is the number of left-shifts * where 0xFF would still fall within the hash mask. */ while (hash_mask >> bit_shift != 0xFF) bit_shift++; - /* - * The portion of the address that is used for the hash table + /* The portion of the address that is used for the hash table * is determined by the mc_filter_type setting. * The algorithm is such that there is a total of 8 bits of shifting. * The bit_shift for a mc_filter_type of 0 represents the number of @@ -707,8 +706,7 @@ s32 e1000_check_for_copper_link_generic(struct e1000_hw *hw) DEBUGFUNC("e1000_check_for_copper_link"); - /* - * We only want to go out to the PHY registers to see if Auto-Neg + /* We only want to go out to the PHY registers to see if Auto-Neg * has completed and/or if our link status has changed. The * get_link_status flag is set upon receiving a Link Status * Change or Rx Sequence Error interrupt. @@ -716,8 +714,7 @@ s32 e1000_check_for_copper_link_generic(struct e1000_hw *hw) if (!mac->get_link_status) return E1000_SUCCESS; - /* - * First we want to see if the MII Status Register reports + /* First we want to see if the MII Status Register reports * link. If so, then we want to get the current speed/duplex * of the PHY. */ @@ -730,28 +727,24 @@ s32 e1000_check_for_copper_link_generic(struct e1000_hw *hw) mac->get_link_status = FALSE; - /* - * Check if there was DownShift, must be checked + /* Check if there was DownShift, must be checked * immediately after link-up */ e1000_check_downshift_generic(hw); - /* - * If we are forcing speed/duplex, then we simply return since + /* If we are forcing speed/duplex, then we simply return since * we have already determined whether we have link or not. */ if (!mac->autoneg) return -E1000_ERR_CONFIG; - /* - * Auto-Neg is enabled. Auto Speed Detection takes care + /* Auto-Neg is enabled. Auto Speed Detection takes care * of MAC speed/duplex configuration. So we only need to * configure Collision Distance in the MAC. */ mac->ops.config_collision_dist(hw); - /* - * Configure Flow Control now that Auto-Neg has completed. + /* Configure Flow Control now that Auto-Neg has completed. * First, we need to restore the desired flow control * settings because we may have had to re-autoneg with a * different link partner. @@ -784,8 +777,7 @@ s32 e1000_check_for_fiber_link_generic(struct e1000_hw *hw) status = E1000_READ_REG(hw, E1000_STATUS); rxcw = E1000_READ_REG(hw, E1000_RXCW); - /* - * If we don't have link (auto-negotiation failed or link partner + /* If we don't have link (auto-negotiation failed or link partner * cannot auto-negotiate), the cable is plugged in (we have signal), * and our link partner is not trying to auto-negotiate with us (we * are receiving idles or data), we need to force link up. We also @@ -816,8 +808,7 @@ s32 e1000_check_for_fiber_link_generic(struct e1000_hw *hw) return ret_val; } } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { - /* - * If we are forcing link and we are receiving /C/ ordered + /* If we are forcing link and we are receiving /C/ ordered * sets, re-enable auto-negotiation in the TXCW register * and disable forced link in the Device Control register * in an attempt to auto-negotiate with our link partner. @@ -853,8 +844,7 @@ s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw) status = E1000_READ_REG(hw, E1000_STATUS); rxcw = E1000_READ_REG(hw, E1000_RXCW); - /* - * If we don't have link (auto-negotiation failed or link partner + /* If we don't have link (auto-negotiation failed or link partner * cannot auto-negotiate), and our link partner is not trying to * auto-negotiate with us (we are receiving idles or data), * we need to force link up. We also need to give auto-negotiation @@ -883,8 +873,7 @@ s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw) return ret_val; } } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { - /* - * If we are forcing link and we are receiving /C/ ordered + /* If we are forcing link and we are receiving /C/ ordered * sets, re-enable auto-negotiation in the TXCW register * and disable forced link in the Device Control register * in an attempt to auto-negotiate with our link partner. @@ -895,8 +884,7 @@ s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw) mac->serdes_has_link = TRUE; } else if (!(E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW))) { - /* - * If we force link for non-auto-negotiation switch, check + /* If we force link for non-auto-negotiation switch, check * link status based on MAC synchronization for internal * serdes media type. */ @@ -955,8 +943,7 @@ s32 e1000_set_default_fc_generic(struct e1000_hw *hw) DEBUGFUNC("e1000_set_default_fc_generic"); - /* - * Read and store word 0x0F of the EEPROM. This word contains bits + /* Read and store word 0x0F of the EEPROM. This word contains bits * that determine the hardware's default PAUSE (flow control) mode, * a bit that determines whether the HW defaults to enabling or * disabling auto-negotiation, and the direction of the @@ -998,15 +985,13 @@ s32 e1000_setup_link_generic(struct e1000_hw *hw) DEBUGFUNC("e1000_setup_link_generic"); - /* - * In the case of the phy reset being blocked, we already have a link. + /* In the case of the phy reset being blocked, we already have a link. * We do not need to set it up again. */ if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw)) return E1000_SUCCESS; - /* - * If requested flow control is set to default, set flow control + /* If requested flow control is set to default, set flow control * based on the EEPROM flow control settings. */ if (hw->fc.requested_mode == e1000_fc_default) { @@ -1015,8 +1000,7 @@ s32 e1000_setup_link_generic(struct e1000_hw *hw) return ret_val; } - /* - * Save off the requested flow control mode for use later. Depending + /* Save off the requested flow control mode for use later. Depending * on the link partner's capabilities, we may or may not use this mode. */ hw->fc.current_mode = hw->fc.requested_mode; @@ -1029,8 +1013,7 @@ s32 e1000_setup_link_generic(struct e1000_hw *hw) if (ret_val) return ret_val; - /* - * Initialize the flow control address, type, and PAUSE timer + /* Initialize the flow control address, type, and PAUSE timer * registers to their default values. This is done even if flow * control is disabled, because it does not hurt anything to * initialize these registers. @@ -1059,8 +1042,7 @@ s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw) DEBUGFUNC("e1000_commit_fc_settings_generic"); - /* - * Check for a software override of the flow control settings, and + /* Check for a software override of the flow control settings, and * setup the device accordingly. If auto-negotiation is enabled, then * software will have to set the "PAUSE" bits to the correct value in * the Transmit Config Word Register (TXCW) and re-start auto- @@ -1082,8 +1064,7 @@ s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw) txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); break; case e1000_fc_rx_pause: - /* - * Rx Flow control is enabled and Tx Flow control is disabled + /* Rx Flow control is enabled and Tx Flow control is disabled * by a software over-ride. Since there really isn't a way to * advertise that we are capable of Rx Pause ONLY, we will * advertise that we support both symmetric and asymmetric Rx @@ -1093,15 +1074,13 @@ s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw) txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); break; case e1000_fc_tx_pause: - /* - * Tx Flow control is enabled, and Rx Flow control is disabled, + /* Tx Flow control is enabled, and Rx Flow control is disabled, * by a software over-ride. */ txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); break; case e1000_fc_full: - /* - * Flow control (both Rx and Tx) is enabled by a software + /* Flow control (both Rx and Tx) is enabled by a software * over-ride. */ txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); @@ -1133,8 +1112,7 @@ s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw) DEBUGFUNC("e1000_poll_fiber_serdes_link_generic"); - /* - * If we have a signal (the cable is plugged in, or assumed TRUE for + /* If we have a signal (the cable is plugged in, or assumed TRUE for * serdes media) then poll for a "Link-Up" indication in the Device * Status Register. Time-out if a link isn't seen in 500 milliseconds * seconds (Auto-negotiation should complete in less than 500 @@ -1149,8 +1127,7 @@ s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw) if (i == FIBER_LINK_UP_LIMIT) { DEBUGOUT("Never got a valid link from auto-neg!!!\n"); mac->autoneg_failed = TRUE; - /* - * AutoNeg failed to achieve a link, so we'll call + /* AutoNeg failed to achieve a link, so we'll call * mac->check_for_link. This routine will force the * link up if we detect a signal. This will allow us to * communicate with non-autonegotiating link partners. @@ -1194,8 +1171,7 @@ s32 e1000_setup_fiber_serdes_link_generic(struct e1000_hw *hw) if (ret_val) return ret_val; - /* - * Since auto-negotiation is enabled, take the link out of reset (the + /* Since auto-negotiation is enabled, take the link out of reset (the * link will be in reset, because we previously reset the chip). This * will restart auto-negotiation. If auto-negotiation is successful * then the link-up status bit will be set and the flow control enable @@ -1207,8 +1183,7 @@ s32 e1000_setup_fiber_serdes_link_generic(struct e1000_hw *hw) E1000_WRITE_FLUSH(hw); msec_delay(1); - /* - * For these adapters, the SW definable pin 1 is set when the optics + /* For these adapters, the SW definable pin 1 is set when the optics * detect a signal. If we have a signal, then poll for a "Link-Up" * indication. */ @@ -1258,16 +1233,14 @@ s32 e1000_set_fc_watermarks_generic(struct e1000_hw *hw) DEBUGFUNC("e1000_set_fc_watermarks_generic"); - /* - * Set the flow control receive threshold registers. Normally, + /* Set the flow control receive threshold registers. Normally, * these registers will be set to a default threshold that may be * adjusted later by the driver's runtime code. However, if the * ability to transmit pause frames is not enabled, then these * registers will be set to 0. */ if (hw->fc.current_mode & e1000_fc_tx_pause) { - /* - * We need to set up the Receive Threshold high and low water + /* We need to set up the Receive Threshold high and low water * marks as well as (optionally) enabling the transmission of * XON frames. */ @@ -1301,8 +1274,7 @@ s32 e1000_force_mac_fc_generic(struct e1000_hw *hw) ctrl = E1000_READ_REG(hw, E1000_CTRL); - /* - * Because we didn't get link via the internal auto-negotiation + /* Because we didn't get link via the internal auto-negotiation * mechanism (we either forced link or we got link via PHY * auto-neg), we have to manually enable/disable transmit an * receive flow control. @@ -1360,13 +1332,13 @@ s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw) { struct e1000_mac_info *mac = &hw->mac; s32 ret_val = E1000_SUCCESS; + u32 pcs_status_reg, pcs_adv_reg, pcs_lp_ability_reg, pcs_ctrl_reg; u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg; u16 speed, duplex; DEBUGFUNC("e1000_config_fc_after_link_up_generic"); - /* - * Check for the case where we have fiber media and auto-neg failed + /* Check for the case where we have fiber media and auto-neg failed * so we had to force link. In this case, we need to force the * configuration of the MAC to match the "fc" parameter. */ @@ -1384,15 +1356,13 @@ s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw) return ret_val; } - /* - * Check for the case where we have copper media and auto-neg is + /* Check for the case where we have copper media and auto-neg is * enabled. In this case, we need to check and see if Auto-Neg * has completed, and if so, how the PHY and link partner has * flow control configured. */ if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) { - /* - * Read the MII Status Register and check to see if AutoNeg + /* Read the MII Status Register and check to see if AutoNeg * has completed. We read this twice because this reg has * some "sticky" (latched) bits. */ @@ -1408,8 +1378,7 @@ s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw) return ret_val; } - /* - * The AutoNeg process has completed, so we now need to + /* The AutoNeg process has completed, so we now need to * read both the Auto Negotiation Advertisement * Register (Address 4) and the Auto_Negotiation Base * Page Ability Register (Address 5) to determine how @@ -1424,8 +1393,7 @@ s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw) if (ret_val) return ret_val; - /* - * Two bits in the Auto Negotiation Advertisement Register + /* Two bits in the Auto Negotiation Advertisement Register * (Address 4) and two bits in the Auto Negotiation Base * Page Ability Register (Address 5) determine flow control * for both the PHY and the link partner. The following @@ -1460,8 +1428,7 @@ s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw) */ if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { - /* - * Now we need to check if the user selected Rx ONLY + /* Now we need to check if the user selected Rx ONLY * of pause frames. In this case, we had to advertise * FULL flow control because we could not advertise Rx * ONLY. Hence, we must now check to see if we need to @@ -1475,8 +1442,7 @@ s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw) DEBUGOUT("Flow Control = Rx PAUSE frames only.\n"); } } - /* - * For receiving PAUSE frames ONLY. + /* For receiving PAUSE frames ONLY. * * LOCAL DEVICE | LINK PARTNER * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result @@ -1490,8 +1456,7 @@ s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw) hw->fc.current_mode = e1000_fc_tx_pause; DEBUGOUT("Flow Control = Tx PAUSE frames only.\n"); } - /* - * For transmitting PAUSE frames ONLY. + /* For transmitting PAUSE frames ONLY. * * LOCAL DEVICE | LINK PARTNER * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result @@ -1505,16 +1470,14 @@ s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw) hw->fc.current_mode = e1000_fc_rx_pause; DEBUGOUT("Flow Control = Rx PAUSE frames only.\n"); } else { - /* - * Per the IEEE spec, at this point flow control + /* Per the IEEE spec, at this point flow control * should be disabled. */ hw->fc.current_mode = e1000_fc_none; DEBUGOUT("Flow Control = NONE.\n"); } - /* - * Now we need to do one last check... If we auto- + /* Now we need to do one last check... If we auto- * negotiated to HALF DUPLEX, flow control should not be * enabled per IEEE 802.3 spec. */ @@ -1527,8 +1490,7 @@ s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw) if (duplex == HALF_DUPLEX) hw->fc.current_mode = e1000_fc_none; - /* - * Now we call a subroutine to actually force the MAC + /* Now we call a subroutine to actually force the MAC * controller to use the correct flow control settings. */ ret_val = e1000_force_mac_fc_generic(hw); @@ -1538,6 +1500,130 @@ s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw) } } + /* Check for the case where we have SerDes media and auto-neg is + * enabled. In this case, we need to check and see if Auto-Neg + * has completed, and if so, how the PHY and link partner has + * flow control configured. + */ + if ((hw->phy.media_type == e1000_media_type_internal_serdes) && + mac->autoneg) { + /* Read the PCS_LSTS and check to see if AutoNeg + * has completed. + */ + pcs_status_reg = E1000_READ_REG(hw, E1000_PCS_LSTAT); + + if (!(pcs_status_reg & E1000_PCS_LSTS_AN_COMPLETE)) { + DEBUGOUT("PCS Auto Neg has not completed.\n"); + return ret_val; + } + + /* The AutoNeg process has completed, so we now need to + * read both the Auto Negotiation Advertisement + * Register (PCS_ANADV) and the Auto_Negotiation Base + * Page Ability Register (PCS_LPAB) to determine how + * flow control was negotiated. + */ + pcs_adv_reg = E1000_READ_REG(hw, E1000_PCS_ANADV); + pcs_lp_ability_reg = E1000_READ_REG(hw, E1000_PCS_LPAB); + + /* Two bits in the Auto Negotiation Advertisement Register + * (PCS_ANADV) and two bits in the Auto Negotiation Base + * Page Ability Register (PCS_LPAB) determine flow control + * for both the PHY and the link partner. The following + * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, + * 1999, describes these PAUSE resolution bits and how flow + * control is determined based upon these settings. + * NOTE: DC = Don't Care + * + * LOCAL DEVICE | LINK PARTNER + * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution + *-------|---------|-------|---------|-------------------- + * 0 | 0 | DC | DC | e1000_fc_none + * 0 | 1 | 0 | DC | e1000_fc_none + * 0 | 1 | 1 | 0 | e1000_fc_none + * 0 | 1 | 1 | 1 | e1000_fc_tx_pause + * 1 | 0 | 0 | DC | e1000_fc_none + * 1 | DC | 1 | DC | e1000_fc_full + * 1 | 1 | 0 | 0 | e1000_fc_none + * 1 | 1 | 0 | 1 | e1000_fc_rx_pause + * + * Are both PAUSE bits set to 1? If so, this implies + * Symmetric Flow Control is enabled at both ends. The + * ASM_DIR bits are irrelevant per the spec. + * + * For Symmetric Flow Control: + * + * LOCAL DEVICE | LINK PARTNER + * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result + *-------|---------|-------|---------|-------------------- + * 1 | DC | 1 | DC | e1000_fc_full + * + */ + if ((pcs_adv_reg & E1000_TXCW_PAUSE) && + (pcs_lp_ability_reg & E1000_TXCW_PAUSE)) { + /* Now we need to check if the user selected Rx ONLY + * of pause frames. In this case, we had to advertise + * FULL flow control because we could not advertise Rx + * ONLY. Hence, we must now check to see if we need to + * turn OFF the TRANSMISSION of PAUSE frames. + */ + if (hw->fc.requested_mode == e1000_fc_full) { + hw->fc.current_mode = e1000_fc_full; + DEBUGOUT("Flow Control = FULL.\n"); + } else { + hw->fc.current_mode = e1000_fc_rx_pause; + DEBUGOUT("Flow Control = Rx PAUSE frames only.\n"); + } + } + /* For receiving PAUSE frames ONLY. + * + * LOCAL DEVICE | LINK PARTNER + * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result + *-------|---------|-------|---------|-------------------- + * 0 | 1 | 1 | 1 | e1000_fc_tx_pause + */ + else if (!(pcs_adv_reg & E1000_TXCW_PAUSE) && + (pcs_adv_reg & E1000_TXCW_ASM_DIR) && + (pcs_lp_ability_reg & E1000_TXCW_PAUSE) && + (pcs_lp_ability_reg & E1000_TXCW_ASM_DIR)) { + hw->fc.current_mode = e1000_fc_tx_pause; + DEBUGOUT("Flow Control = Tx PAUSE frames only.\n"); + } + /* For transmitting PAUSE frames ONLY. + * + * LOCAL DEVICE | LINK PARTNER + * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result + *-------|---------|-------|---------|-------------------- + * 1 | 1 | 0 | 1 | e1000_fc_rx_pause + */ + else if ((pcs_adv_reg & E1000_TXCW_PAUSE) && + (pcs_adv_reg & E1000_TXCW_ASM_DIR) && + !(pcs_lp_ability_reg & E1000_TXCW_PAUSE) && + (pcs_lp_ability_reg & E1000_TXCW_ASM_DIR)) { + hw->fc.current_mode = e1000_fc_rx_pause; + DEBUGOUT("Flow Control = Rx PAUSE frames only.\n"); + } else { + /* Per the IEEE spec, at this point flow control + * should be disabled. + */ + hw->fc.current_mode = e1000_fc_none; + DEBUGOUT("Flow Control = NONE.\n"); + } + + /* Now we call a subroutine to actually force the MAC + * controller to use the correct flow control settings. + */ + pcs_ctrl_reg = E1000_READ_REG(hw, E1000_PCS_LCTL); + pcs_ctrl_reg |= E1000_PCS_LCTL_FORCE_FCTRL; + E1000_WRITE_REG(hw, E1000_PCS_LCTL, pcs_ctrl_reg); + + ret_val = e1000_force_mac_fc_generic(hw); + if (ret_val) { + DEBUGOUT("Error forcing flow control settings\n"); + return ret_val; + } + } + return E1000_SUCCESS; } @@ -1854,16 +1940,28 @@ s32 e1000_blink_led_generic(struct e1000_hw *hw) ledctl_blink = E1000_LEDCTL_LED0_BLINK | (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT); } else { - /* - * set the blink bit for each LED that's "on" (0x0E) - * in ledctl_mode2 + /* Set the blink bit for each LED that's "on" (0x0E) + * (or "off" if inverted) in ledctl_mode2. The blink + * logic in hardware only works when mode is set to "on" + * so it must be changed accordingly when the mode is + * "off" and inverted. */ ledctl_blink = hw->mac.ledctl_mode2; - for (i = 0; i < 4; i++) - if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) == - E1000_LEDCTL_MODE_LED_ON) - ledctl_blink |= (E1000_LEDCTL_LED0_BLINK << - (i * 8)); + for (i = 0; i < 32; i += 8) { + u32 mode = (hw->mac.ledctl_mode2 >> i) & + E1000_LEDCTL_LED0_MODE_MASK; + u32 led_default = hw->mac.ledctl_default >> i; + + if ((!(led_default & E1000_LEDCTL_LED0_IVRT) && + (mode == E1000_LEDCTL_MODE_LED_ON)) || + ((led_default & E1000_LEDCTL_LED0_IVRT) && + (mode == E1000_LEDCTL_MODE_LED_OFF))) { + ledctl_blink &= + ~(E1000_LEDCTL_LED0_MODE_MASK << i); + ledctl_blink |= (E1000_LEDCTL_LED0_BLINK | + E1000_LEDCTL_MODE_LED_ON) << i; + } + } } E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl_blink); @@ -2083,6 +2181,20 @@ static s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw) } /** + * e1000_validate_mdi_setting_crossover_generic - Verify MDI/MDIx settings + * @hw: pointer to the HW structure + * + * Validate the MDI/MDIx setting, allowing for auto-crossover during forced + * operation. + **/ +s32 e1000_validate_mdi_setting_crossover_generic(struct e1000_hw *hw) +{ + DEBUGFUNC("e1000_validate_mdi_setting_crossover_generic"); + + return E1000_SUCCESS; +} + +/** * e1000_write_8bit_ctrl_reg_generic - Write a 8bit CTRL register * @hw: pointer to the HW structure * @reg: 32bit register offset such as E1000_SCTL diff --git a/sys/dev/e1000/e1000_mac.h b/sys/dev/e1000/e1000_mac.h index c18a7ec..3e2ccde 100644 --- a/sys/dev/e1000/e1000_mac.h +++ b/sys/dev/e1000/e1000_mac.h @@ -1,6 +1,6 @@ /****************************************************************************** - Copyright (c) 2001-2012, Intel Corporation + Copyright (c) 2001-2013, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without @@ -35,10 +35,6 @@ #ifndef _E1000_MAC_H_ #define _E1000_MAC_H_ -/* - * Functions that should not be called directly from drivers but can be used - * by other files in this 'shared code' - */ void e1000_init_mac_ops_generic(struct e1000_hw *hw); void e1000_null_mac_generic(struct e1000_hw *hw); s32 e1000_null_ops_generic(struct e1000_hw *hw); @@ -47,6 +43,7 @@ bool e1000_null_mng_mode(struct e1000_hw *hw); void e1000_null_update_mc(struct e1000_hw *hw, u8 *h, u32 a); void e1000_null_write_vfta(struct e1000_hw *hw, u32 a, u32 b); void e1000_null_rar_set(struct e1000_hw *hw, u8 *h, u32 a); +s32 e1000_null_set_obff_timer(struct e1000_hw *hw, u32 a); s32 e1000_blink_led_generic(struct e1000_hw *hw); s32 e1000_check_for_copper_link_generic(struct e1000_hw *hw); s32 e1000_check_for_fiber_link_generic(struct e1000_hw *hw); @@ -77,6 +74,7 @@ s32 e1000_set_fc_watermarks_generic(struct e1000_hw *hw); s32 e1000_setup_fiber_serdes_link_generic(struct e1000_hw *hw); s32 e1000_setup_led_generic(struct e1000_hw *hw); s32 e1000_setup_link_generic(struct e1000_hw *hw); +s32 e1000_validate_mdi_setting_crossover_generic(struct e1000_hw *hw); s32 e1000_write_8bit_ctrl_reg_generic(struct e1000_hw *hw, u32 reg, u32 offset, u8 data); diff --git a/sys/dev/e1000/e1000_manage.c b/sys/dev/e1000/e1000_manage.c index f11b18d..c58d32d 100644 --- a/sys/dev/e1000/e1000_manage.c +++ b/sys/dev/e1000/e1000_manage.c @@ -1,6 +1,6 @@ /****************************************************************************** - Copyright (c) 2001-2012, Intel Corporation + Copyright (c) 2001-2013, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without @@ -145,11 +145,10 @@ bool e1000_enable_tx_pkt_filtering_generic(struct e1000_hw *hw) return hw->mac.tx_pkt_filtering; } - /* - * If we can't read from the host interface for whatever + /* If we can't read from the host interface for whatever * reason, disable filtering. */ - ret_val = hw->mac.ops.mng_enable_host_if(hw); + ret_val = e1000_mng_enable_host_if_generic(hw); if (ret_val != E1000_SUCCESS) { hw->mac.tx_pkt_filtering = FALSE; return hw->mac.tx_pkt_filtering; @@ -165,8 +164,7 @@ bool e1000_enable_tx_pkt_filtering_generic(struct e1000_hw *hw) hdr->checksum = 0; csum = e1000_calculate_checksum((u8 *)hdr, E1000_MNG_DHCP_COOKIE_LENGTH); - /* - * If either the checksums or signature don't match, then + /* If either the checksums or signature don't match, then * the cookie area isn't considered valid, in which case we * take the safe route of assuming Tx filtering is enabled. */ @@ -259,8 +257,7 @@ s32 e1000_mng_host_if_write_generic(struct e1000_hw *hw, u8 *buffer, /* Calculate length in DWORDs */ length >>= 2; - /* - * The device driver writes the relevant command block into the + /* The device driver writes the relevant command block into the * ram area. */ for (i = 0; i < length; i++) { @@ -312,18 +309,18 @@ s32 e1000_mng_write_dhcp_info_generic(struct e1000_hw *hw, u8 *buffer, hdr.checksum = 0; /* Enable the host interface */ - ret_val = hw->mac.ops.mng_enable_host_if(hw); + ret_val = e1000_mng_enable_host_if_generic(hw); if (ret_val) return ret_val; /* Populate the host interface with the contents of "buffer". */ - ret_val = hw->mac.ops.mng_host_if_write(hw, buffer, length, - sizeof(hdr), &(hdr.checksum)); + ret_val = e1000_mng_host_if_write_generic(hw, buffer, length, + sizeof(hdr), &(hdr.checksum)); if (ret_val) return ret_val; /* Write the manageability command header */ - ret_val = hw->mac.ops.mng_write_cmd_header(hw, &hdr); + ret_val = e1000_mng_write_cmd_header_generic(hw, &hdr); if (ret_val) return ret_val; @@ -424,8 +421,7 @@ s32 e1000_host_interface_command(struct e1000_hw *hw, u8 *buffer, u32 length) /* Calculate length in DWORDs */ length >>= 2; - /* - * The device driver writes the relevant command block + /* The device driver writes the relevant command block * into the ram area. */ for (i = 0; i < length; i++) @@ -537,8 +533,7 @@ s32 e1000_load_firmware(struct e1000_hw *hw, u8 *buffer, u32 length) /* Calculate length in DWORDs */ length >>= 2; - /* - * The device driver writes the relevant FW code block + /* The device driver writes the relevant FW code block * into the ram area in DWORDs via 1kB ram addressing window. */ for (i = 0; i < length; i++) { diff --git a/sys/dev/e1000/e1000_nvm.c b/sys/dev/e1000/e1000_nvm.c index d8df089..a39b847 100644 --- a/sys/dev/e1000/e1000_nvm.c +++ b/sys/dev/e1000/e1000_nvm.c @@ -1,6 +1,6 @@ /****************************************************************************** - Copyright (c) 2001-2011, Intel Corporation + Copyright (c) 2001-2013, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without @@ -227,7 +227,6 @@ s32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg) { u32 attempts = 100000; u32 i, reg = 0; - s32 ret_val = -E1000_ERR_NVM; DEBUGFUNC("e1000_poll_eerd_eewr_done"); @@ -237,15 +236,13 @@ s32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg) else reg = E1000_READ_REG(hw, E1000_EEWR); - if (reg & E1000_NVM_RW_REG_DONE) { - ret_val = E1000_SUCCESS; - break; - } + if (reg & E1000_NVM_RW_REG_DONE) + return E1000_SUCCESS; usec_delay(5); } - return ret_val; + return -E1000_ERR_NVM; } /** @@ -260,7 +257,6 @@ s32 e1000_acquire_nvm_generic(struct e1000_hw *hw) { u32 eecd = E1000_READ_REG(hw, E1000_EECD); s32 timeout = E1000_NVM_GRANT_ATTEMPTS; - s32 ret_val = E1000_SUCCESS; DEBUGFUNC("e1000_acquire_nvm_generic"); @@ -279,10 +275,10 @@ s32 e1000_acquire_nvm_generic(struct e1000_hw *hw) eecd &= ~E1000_EECD_REQ; E1000_WRITE_REG(hw, E1000_EECD, eecd); DEBUGOUT("Could not acquire NVM grant\n"); - ret_val = -E1000_ERR_NVM; + return -E1000_ERR_NVM; } - return ret_val; + return E1000_SUCCESS; } /** @@ -381,7 +377,6 @@ static s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw) { struct e1000_nvm_info *nvm = &hw->nvm; u32 eecd = E1000_READ_REG(hw, E1000_EECD); - s32 ret_val = E1000_SUCCESS; u8 spi_stat_reg; DEBUGFUNC("e1000_ready_nvm_eeprom"); @@ -402,8 +397,7 @@ static s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw) E1000_WRITE_FLUSH(hw); usec_delay(1); - /* - * Read "Status Register" repeatedly until the LSB is cleared. + /* Read "Status Register" repeatedly until the LSB is cleared. * The EEPROM will signal that the command has been completed * by clearing bit 0 of the internal status register. If it's * not cleared within 'timeout', then error out. @@ -422,13 +416,11 @@ static s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw) if (!timeout) { DEBUGOUT("SPI NVM Status error\n"); - ret_val = -E1000_ERR_NVM; - goto out; + return -E1000_ERR_NVM; } } -out: - return ret_val; + return E1000_SUCCESS; } /** @@ -450,20 +442,18 @@ s32 e1000_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) DEBUGFUNC("e1000_read_nvm_spi"); - /* - * A check for invalid values: offset too large, too many words, + /* A check for invalid values: offset too large, too many words, * and not enough words. */ if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || (words == 0)) { DEBUGOUT("nvm parameter(s) out of bounds\n"); - ret_val = -E1000_ERR_NVM; - goto out; + return -E1000_ERR_NVM; } ret_val = nvm->ops.acquire(hw); if (ret_val) - goto out; + return ret_val; ret_val = e1000_ready_nvm_eeprom(hw); if (ret_val) @@ -478,8 +468,7 @@ s32 e1000_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits); e1000_shift_out_eec_bits(hw, (u16)(offset*2), nvm->address_bits); - /* - * Read the data. SPI NVMs increment the address with each byte + /* Read the data. SPI NVMs increment the address with each byte * read and will roll over if reading beyond the end. This allows * us to read the whole NVM from any offset */ @@ -491,7 +480,6 @@ s32 e1000_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) release: nvm->ops.release(hw); -out: return ret_val; } @@ -514,20 +502,18 @@ s32 e1000_read_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words, DEBUGFUNC("e1000_read_nvm_microwire"); - /* - * A check for invalid values: offset too large, too many words, + /* A check for invalid values: offset too large, too many words, * and not enough words. */ if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || (words == 0)) { DEBUGOUT("nvm parameter(s) out of bounds\n"); - ret_val = -E1000_ERR_NVM; - goto out; + return -E1000_ERR_NVM; } ret_val = nvm->ops.acquire(hw); if (ret_val) - goto out; + return ret_val; ret_val = e1000_ready_nvm_eeprom(hw); if (ret_val) @@ -539,8 +525,7 @@ s32 e1000_read_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words, e1000_shift_out_eec_bits(hw, (u16)(offset + i), nvm->address_bits); - /* - * Read the data. For microwire, each word requires the + /* Read the data. For microwire, each word requires the * overhead of setup and tear-down. */ data[i] = e1000_shift_in_eec_bits(hw, 16); @@ -550,7 +535,6 @@ s32 e1000_read_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words, release: nvm->ops.release(hw); -out: return ret_val; } @@ -571,15 +555,13 @@ s32 e1000_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) DEBUGFUNC("e1000_read_nvm_eerd"); - /* - * A check for invalid values: offset too large, too many words, + /* A check for invalid values: offset too large, too many words, * too many words for the offset, and not enough words. */ if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || (words == 0)) { DEBUGOUT("nvm parameter(s) out of bounds\n"); - ret_val = -E1000_ERR_NVM; - goto out; + return -E1000_ERR_NVM; } for (i = 0; i < words; i++) { @@ -595,7 +577,6 @@ s32 e1000_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) E1000_NVM_RW_REG_DATA); } -out: return ret_val; } @@ -614,32 +595,32 @@ out: s32 e1000_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) { struct e1000_nvm_info *nvm = &hw->nvm; - s32 ret_val; + s32 ret_val = -E1000_ERR_NVM; u16 widx = 0; DEBUGFUNC("e1000_write_nvm_spi"); - /* - * A check for invalid values: offset too large, too many words, + /* A check for invalid values: offset too large, too many words, * and not enough words. */ if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || (words == 0)) { DEBUGOUT("nvm parameter(s) out of bounds\n"); - ret_val = -E1000_ERR_NVM; - goto out; + return -E1000_ERR_NVM; } - ret_val = nvm->ops.acquire(hw); - if (ret_val) - goto out; - while (widx < words) { u8 write_opcode = NVM_WRITE_OPCODE_SPI; - ret_val = e1000_ready_nvm_eeprom(hw); + ret_val = nvm->ops.acquire(hw); if (ret_val) - goto release; + return ret_val; + + ret_val = e1000_ready_nvm_eeprom(hw); + if (ret_val) { + nvm->ops.release(hw); + return ret_val; + } e1000_standby_nvm(hw); @@ -649,8 +630,7 @@ s32 e1000_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) e1000_standby_nvm(hw); - /* - * Some SPI eeproms use the 8th address bit embedded in the + /* Some SPI eeproms use the 8th address bit embedded in the * opcode */ if ((nvm->address_bits == 8) && (offset >= 128)) @@ -673,13 +653,10 @@ s32 e1000_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) break; } } + msec_delay(10); + nvm->ops.release(hw); } - msec_delay(10); -release: - nvm->ops.release(hw); - -out: return ret_val; } @@ -706,20 +683,18 @@ s32 e1000_write_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words, DEBUGFUNC("e1000_write_nvm_microwire"); - /* - * A check for invalid values: offset too large, too many words, + /* A check for invalid values: offset too large, too many words, * and not enough words. */ if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || (words == 0)) { DEBUGOUT("nvm parameter(s) out of bounds\n"); - ret_val = -E1000_ERR_NVM; - goto out; + return -E1000_ERR_NVM; } ret_val = nvm->ops.acquire(hw); if (ret_val) - goto out; + return ret_val; ret_val = e1000_ready_nvm_eeprom(hw); if (ret_val) @@ -769,7 +744,6 @@ s32 e1000_write_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words, release: nvm->ops.release(hw); -out: return ret_val; } @@ -795,32 +769,30 @@ s32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num, if (pba_num == NULL) { DEBUGOUT("PBA string buffer was null\n"); - ret_val = E1000_ERR_INVALID_ARGUMENT; - goto out; + return -E1000_ERR_INVALID_ARGUMENT; } ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data); if (ret_val) { DEBUGOUT("NVM Read Error\n"); - goto out; + return ret_val; } ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr); if (ret_val) { DEBUGOUT("NVM Read Error\n"); - goto out; + return ret_val; } - /* - * if nvm_data is not ptr guard the PBA must be in legacy format which + /* if nvm_data is not ptr guard the PBA must be in legacy format which * means pba_ptr is actually our second data word for the PBA number * and we can decode it into an ascii string */ if (nvm_data != NVM_PBA_PTR_GUARD) { DEBUGOUT("NVM PBA number is not stored as string\n"); - /* we will need 11 characters to store the PBA */ - if (pba_num_size < 11) { + /* make sure callers buffer is big enough to store the PBA */ + if (pba_num_size < E1000_PBANUM_LENGTH) { DEBUGOUT("PBA string buffer too small\n"); return E1000_ERR_NO_SPACE; } @@ -848,25 +820,23 @@ s32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num, pba_num[offset] += 'A' - 0xA; } - goto out; + return E1000_SUCCESS; } ret_val = hw->nvm.ops.read(hw, pba_ptr, 1, &length); if (ret_val) { DEBUGOUT("NVM Read Error\n"); - goto out; + return ret_val; } if (length == 0xFFFF || length == 0) { DEBUGOUT("NVM PBA number section invalid length\n"); - ret_val = E1000_ERR_NVM_PBA_SECTION; - goto out; + return -E1000_ERR_NVM_PBA_SECTION; } /* check if pba_num buffer is big enough */ if (pba_num_size < (((u32)length * 2) - 1)) { DEBUGOUT("PBA string buffer too small\n"); - ret_val = E1000_ERR_NO_SPACE; - goto out; + return -E1000_ERR_NO_SPACE; } /* trim pba length from start of string */ @@ -877,15 +847,14 @@ s32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num, ret_val = hw->nvm.ops.read(hw, pba_ptr + offset, 1, &nvm_data); if (ret_val) { DEBUGOUT("NVM Read Error\n"); - goto out; + return ret_val; } pba_num[offset * 2] = (u8)(nvm_data >> 8); pba_num[(offset * 2) + 1] = (u8)(nvm_data & 0xFF); } pba_num[offset * 2] = '\0'; -out: - return ret_val; + return E1000_SUCCESS; } /** @@ -907,48 +876,233 @@ s32 e1000_read_pba_length_generic(struct e1000_hw *hw, u32 *pba_num_size) if (pba_num_size == NULL) { DEBUGOUT("PBA buffer size was null\n"); - ret_val = E1000_ERR_INVALID_ARGUMENT; - goto out; + return -E1000_ERR_INVALID_ARGUMENT; } ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data); if (ret_val) { DEBUGOUT("NVM Read Error\n"); - goto out; + return ret_val; } ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr); if (ret_val) { DEBUGOUT("NVM Read Error\n"); - goto out; + return ret_val; } /* if data is not ptr guard the PBA must be in legacy format */ if (nvm_data != NVM_PBA_PTR_GUARD) { - *pba_num_size = 11; - goto out; + *pba_num_size = E1000_PBANUM_LENGTH; + return E1000_SUCCESS; } ret_val = hw->nvm.ops.read(hw, pba_ptr, 1, &length); if (ret_val) { DEBUGOUT("NVM Read Error\n"); - goto out; + return ret_val; } if (length == 0xFFFF || length == 0) { DEBUGOUT("NVM PBA number section invalid length\n"); - ret_val = E1000_ERR_NVM_PBA_SECTION; - goto out; + return -E1000_ERR_NVM_PBA_SECTION; } - /* - * Convert from length in u16 values to u8 chars, add 1 for NULL, + /* Convert from length in u16 values to u8 chars, add 1 for NULL, * and subtract 2 because length field is included in length. */ *pba_num_size = ((u32)length * 2) - 1; -out: - return ret_val; + return E1000_SUCCESS; +} + + +/** + * e1000_read_pba_raw + * @hw: pointer to the HW structure + * @eeprom_buf: optional pointer to EEPROM image + * @eeprom_buf_size: size of EEPROM image in words + * @max_pba_block_size: PBA block size limit + * @pba: pointer to output PBA structure + * + * Reads PBA from EEPROM image when eeprom_buf is not NULL. + * Reads PBA from physical EEPROM device when eeprom_buf is NULL. + * + **/ +s32 e1000_read_pba_raw(struct e1000_hw *hw, u16 *eeprom_buf, + u32 eeprom_buf_size, u16 max_pba_block_size, + struct e1000_pba *pba) +{ + s32 ret_val; + u16 pba_block_size; + + if (pba == NULL) + return -E1000_ERR_PARAM; + + if (eeprom_buf == NULL) { + ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_0, 2, + &pba->word[0]); + if (ret_val) + return ret_val; + } else { + if (eeprom_buf_size > NVM_PBA_OFFSET_1) { + pba->word[0] = eeprom_buf[NVM_PBA_OFFSET_0]; + pba->word[1] = eeprom_buf[NVM_PBA_OFFSET_1]; + } else { + return -E1000_ERR_PARAM; + } + } + + if (pba->word[0] == NVM_PBA_PTR_GUARD) { + if (pba->pba_block == NULL) + return -E1000_ERR_PARAM; + + ret_val = e1000_get_pba_block_size(hw, eeprom_buf, + eeprom_buf_size, + &pba_block_size); + if (ret_val) + return ret_val; + + if (pba_block_size > max_pba_block_size) + return -E1000_ERR_PARAM; + + if (eeprom_buf == NULL) { + ret_val = e1000_read_nvm(hw, pba->word[1], + pba_block_size, + pba->pba_block); + if (ret_val) + return ret_val; + } else { + if (eeprom_buf_size > (u32)(pba->word[1] + + pba->pba_block[0])) { + memcpy(pba->pba_block, + &eeprom_buf[pba->word[1]], + pba_block_size * sizeof(u16)); + } else { + return -E1000_ERR_PARAM; + } + } + } + + return E1000_SUCCESS; +} + +/** + * e1000_write_pba_raw + * @hw: pointer to the HW structure + * @eeprom_buf: optional pointer to EEPROM image + * @eeprom_buf_size: size of EEPROM image in words + * @pba: pointer to PBA structure + * + * Writes PBA to EEPROM image when eeprom_buf is not NULL. + * Writes PBA to physical EEPROM device when eeprom_buf is NULL. + * + **/ +s32 e1000_write_pba_raw(struct e1000_hw *hw, u16 *eeprom_buf, + u32 eeprom_buf_size, struct e1000_pba *pba) +{ + s32 ret_val; + + if (pba == NULL) + return -E1000_ERR_PARAM; + + if (eeprom_buf == NULL) { + ret_val = e1000_write_nvm(hw, NVM_PBA_OFFSET_0, 2, + &pba->word[0]); + if (ret_val) + return ret_val; + } else { + if (eeprom_buf_size > NVM_PBA_OFFSET_1) { + eeprom_buf[NVM_PBA_OFFSET_0] = pba->word[0]; + eeprom_buf[NVM_PBA_OFFSET_1] = pba->word[1]; + } else { + return -E1000_ERR_PARAM; + } + } + + if (pba->word[0] == NVM_PBA_PTR_GUARD) { + if (pba->pba_block == NULL) + return -E1000_ERR_PARAM; + + if (eeprom_buf == NULL) { + ret_val = e1000_write_nvm(hw, pba->word[1], + pba->pba_block[0], + pba->pba_block); + if (ret_val) + return ret_val; + } else { + if (eeprom_buf_size > (u32)(pba->word[1] + + pba->pba_block[0])) { + memcpy(&eeprom_buf[pba->word[1]], + pba->pba_block, + pba->pba_block[0] * sizeof(u16)); + } else { + return -E1000_ERR_PARAM; + } + } + } + + return E1000_SUCCESS; +} + +/** + * e1000_get_pba_block_size + * @hw: pointer to the HW structure + * @eeprom_buf: optional pointer to EEPROM image + * @eeprom_buf_size: size of EEPROM image in words + * @pba_data_size: pointer to output variable + * + * Returns the size of the PBA block in words. Function operates on EEPROM + * image if the eeprom_buf pointer is not NULL otherwise it accesses physical + * EEPROM device. + * + **/ +s32 e1000_get_pba_block_size(struct e1000_hw *hw, u16 *eeprom_buf, + u32 eeprom_buf_size, u16 *pba_block_size) +{ + s32 ret_val; + u16 pba_word[2]; + u16 length; + + DEBUGFUNC("e1000_get_pba_block_size"); + + if (eeprom_buf == NULL) { + ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_0, 2, &pba_word[0]); + if (ret_val) + return ret_val; + } else { + if (eeprom_buf_size > NVM_PBA_OFFSET_1) { + pba_word[0] = eeprom_buf[NVM_PBA_OFFSET_0]; + pba_word[1] = eeprom_buf[NVM_PBA_OFFSET_1]; + } else { + return -E1000_ERR_PARAM; + } + } + + if (pba_word[0] == NVM_PBA_PTR_GUARD) { + if (eeprom_buf == NULL) { + ret_val = e1000_read_nvm(hw, pba_word[1] + 0, 1, + &length); + if (ret_val) + return ret_val; + } else { + if (eeprom_buf_size > pba_word[1]) + length = eeprom_buf[pba_word[1] + 0]; + else + return -E1000_ERR_PARAM; + } + + if (length == 0xFFFF || length == 0) + return -E1000_ERR_NVM_PBA_SECTION; + } else { + /* PBA number in legacy format, there is no PBA Block. */ + length = 0; + } + + if (pba_block_size != NULL) + *pba_block_size = length; + + return E1000_SUCCESS; } /** @@ -989,7 +1143,7 @@ s32 e1000_read_mac_addr_generic(struct e1000_hw *hw) **/ s32 e1000_validate_nvm_checksum_generic(struct e1000_hw *hw) { - s32 ret_val = E1000_SUCCESS; + s32 ret_val; u16 checksum = 0; u16 i, nvm_data; @@ -999,19 +1153,17 @@ s32 e1000_validate_nvm_checksum_generic(struct e1000_hw *hw) ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data); if (ret_val) { DEBUGOUT("NVM Read Error\n"); - goto out; + return ret_val; } checksum += nvm_data; } if (checksum != (u16) NVM_SUM) { DEBUGOUT("NVM Checksum Invalid\n"); - ret_val = -E1000_ERR_NVM; - goto out; + return -E1000_ERR_NVM; } -out: - return ret_val; + return E1000_SUCCESS; } /** @@ -1034,7 +1186,7 @@ s32 e1000_update_nvm_checksum_generic(struct e1000_hw *hw) ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data); if (ret_val) { DEBUGOUT("NVM Read Error while updating checksum.\n"); - goto out; + return ret_val; } checksum += nvm_data; } @@ -1043,7 +1195,6 @@ s32 e1000_update_nvm_checksum_generic(struct e1000_hw *hw) if (ret_val) DEBUGOUT("NVM Write Error while updating checksum.\n"); -out: return ret_val; } @@ -1067,3 +1218,4 @@ static void e1000_reload_nvm_generic(struct e1000_hw *hw) E1000_WRITE_FLUSH(hw); } + diff --git a/sys/dev/e1000/e1000_nvm.h b/sys/dev/e1000/e1000_nvm.h index ed23eb3..34077b2 100644 --- a/sys/dev/e1000/e1000_nvm.h +++ b/sys/dev/e1000/e1000_nvm.h @@ -1,6 +1,6 @@ /****************************************************************************** - Copyright (c) 2001-2011, Intel Corporation + Copyright (c) 2001-2013, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without @@ -35,6 +35,14 @@ #ifndef _E1000_NVM_H_ #define _E1000_NVM_H_ +#if !defined(NO_READ_PBA_RAW) || !defined(NO_WRITE_PBA_RAW) +struct e1000_pba { + u16 word[2]; + u16 *pba_block; +}; +#endif + + void e1000_init_nvm_ops_generic(struct e1000_hw *hw); s32 e1000_null_read_nvm(struct e1000_hw *hw, u16 a, u16 b, u16 *c); void e1000_null_nvm_generic(struct e1000_hw *hw); @@ -47,6 +55,13 @@ s32 e1000_read_mac_addr_generic(struct e1000_hw *hw); s32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num, u32 pba_num_size); s32 e1000_read_pba_length_generic(struct e1000_hw *hw, u32 *pba_num_size); +s32 e1000_read_pba_raw(struct e1000_hw *hw, u16 *eeprom_buf, + u32 eeprom_buf_size, u16 max_pba_block_size, + struct e1000_pba *pba); +s32 e1000_write_pba_raw(struct e1000_hw *hw, u16 *eeprom_buf, + u32 eeprom_buf_size, struct e1000_pba *pba); +s32 e1000_get_pba_block_size(struct e1000_hw *hw, u16 *eeprom_buf, + u32 eeprom_buf_size, u16 *pba_block_size); s32 e1000_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data); s32 e1000_read_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words, u16 *data); diff --git a/sys/dev/e1000/e1000_osdep.h b/sys/dev/e1000/e1000_osdep.h index e6d131a..dd19613 100644 --- a/sys/dev/e1000/e1000_osdep.h +++ b/sys/dev/e1000/e1000_osdep.h @@ -1,6 +1,6 @@ /****************************************************************************** - Copyright (c) 2001-2010, Intel Corporation + Copyright (c) 2001-2013, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without @@ -66,7 +66,8 @@ #define MSGOUT(S, A, B) printf(S "\n", A, B) #define DEBUGFUNC(F) DEBUGOUT(F); #define DEBUGOUT(S) do {} while (0) -#define DEBUGOUT1(S,A) do {} while (0) +/* This define is needed or shared code will not build */ +#define DEBUGOUT1(S,A) if (0) printf(S,A); #define DEBUGOUT2(S,A,B) do {} while (0) #define DEBUGOUT3(S,A,B,C) do {} while (0) #define DEBUGOUT7(S,A,B,C,D,E,F,G) do {} while (0) diff --git a/sys/dev/e1000/e1000_phy.c b/sys/dev/e1000/e1000_phy.c index fd253ba..241c1d5 100644 --- a/sys/dev/e1000/e1000_phy.c +++ b/sys/dev/e1000/e1000_phy.c @@ -1,6 +1,6 @@ /****************************************************************************** - Copyright (c) 2001-2012, Intel Corporation + Copyright (c) 2001-2013, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without @@ -34,7 +34,7 @@ #include "e1000_api.h" -static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg); +static s32 e1000_wait_autoneg(struct e1000_hw *hw); static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data, bool read, bool page_set); static u32 e1000_get_phy_addr_for_hv_page(u32 page); @@ -173,8 +173,10 @@ s32 e1000_read_i2c_byte_null(struct e1000_hw *hw, u8 byte_offset, * @data: data value to write * **/ -s32 e1000_write_i2c_byte_null(struct e1000_hw *hw, u8 byte_offset, - u8 dev_addr, u8 data) +s32 e1000_write_i2c_byte_null(struct e1000_hw *hw, + u8 byte_offset, + u8 dev_addr, + u8 data) { DEBUGFUNC("e1000_write_i2c_byte_null"); return E1000_SUCCESS; @@ -285,8 +287,7 @@ s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data) return -E1000_ERR_PARAM; } - /* - * Set up Op-code, Phy Address, and register offset in the MDI + /* Set up Op-code, Phy Address, and register offset in the MDI * Control register. The MAC will take care of interfacing with the * PHY to retrieve the desired data. */ @@ -296,8 +297,7 @@ s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data) E1000_WRITE_REG(hw, E1000_MDIC, mdic); - /* - * Poll the ready bit to see if the MDI read completed + /* Poll the ready bit to see if the MDI read completed * Increasing the time out as testing showed failures with * the lower time out */ @@ -315,10 +315,15 @@ s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data) DEBUGOUT("MDI Error\n"); return -E1000_ERR_PHY; } + if (((mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT) != offset) { + DEBUGOUT2("MDI Read offset error - requested %d, returned %d\n", + offset, + (mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT); + return -E1000_ERR_PHY; + } *data = (u16) mdic; - /* - * Allow some time after each MDIC transaction to avoid + /* Allow some time after each MDIC transaction to avoid * reading duplicate data in the next MDIC transaction. */ if (hw->mac.type == e1000_pch2lan) @@ -347,8 +352,7 @@ s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data) return -E1000_ERR_PARAM; } - /* - * Set up Op-code, Phy Address, and register offset in the MDI + /* Set up Op-code, Phy Address, and register offset in the MDI * Control register. The MAC will take care of interfacing with the * PHY to retrieve the desired data. */ @@ -359,8 +363,7 @@ s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data) E1000_WRITE_REG(hw, E1000_MDIC, mdic); - /* - * Poll the ready bit to see if the MDI read completed + /* Poll the ready bit to see if the MDI read completed * Increasing the time out as testing showed failures with * the lower time out */ @@ -378,9 +381,14 @@ s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data) DEBUGOUT("MDI Error\n"); return -E1000_ERR_PHY; } + if (((mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT) != offset) { + DEBUGOUT2("MDI Write offset error - requested %d, returned %d\n", + offset, + (mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT); + return -E1000_ERR_PHY; + } - /* - * Allow some time after each MDIC transaction to avoid + /* Allow some time after each MDIC transaction to avoid * reading duplicate data in the next MDIC transaction. */ if (hw->mac.type == e1000_pch2lan) @@ -405,8 +413,7 @@ s32 e1000_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data) DEBUGFUNC("e1000_read_phy_reg_i2c"); - /* - * Set up Op-code, Phy Address, and register address in the I2CCMD + /* Set up Op-code, Phy Address, and register address in the I2CCMD * register. The MAC will take care of interfacing with the * PHY to retrieve the desired data. */ @@ -464,8 +471,7 @@ s32 e1000_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data) /* Swap the data bytes for the I2C interface */ phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00); - /* - * Set up Op-code, Phy Address, and register address in the I2CCMD + /* Set up Op-code, Phy Address, and register address in the I2CCMD * register. The MAC will take care of interfacing with the * PHY to retrieve the desired data. */ @@ -521,8 +527,7 @@ s32 e1000_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data) return -E1000_ERR_PHY; } - /* - * Set up Op-code, EEPROM Address,in the I2CCMD + /* Set up Op-code, EEPROM Address,in the I2CCMD * register. The MAC will take care of interfacing with the * EEPROM to retrieve the desired data. */ @@ -576,14 +581,12 @@ s32 e1000_write_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 data) DEBUGOUT("I2CCMD command address exceeds upper limit\n"); return -E1000_ERR_PHY; } - /* - * The programming interface is 16 bits wide + /* The programming interface is 16 bits wide * so we need to read the whole word first * then update appropriate byte lane and write * the updated word back. */ - /* - * Set up Op-code, EEPROM Address,in the I2CCMD + /* Set up Op-code, EEPROM Address,in the I2CCMD * register. The MAC will take care of interfacing * with an EEPROM to write the data given. */ @@ -593,8 +596,7 @@ s32 e1000_write_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 data) E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd); for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { usec_delay(50); - /* - * Poll the ready bit to see if lastly + /* Poll the ready bit to see if lastly * launched I2C operation completed */ i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD); @@ -602,8 +604,7 @@ s32 e1000_write_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 data) /* Check if this is READ or WRITE phase */ if ((i2ccmd & E1000_I2CCMD_OPCODE_READ) == E1000_I2CCMD_OPCODE_READ) { - /* - * Write the selected byte + /* Write the selected byte * lane and update whole word */ data_local = i2ccmd & 0xFF00; @@ -1053,12 +1054,16 @@ s32 e1000_copper_link_setup_82577(struct e1000_hw *hw) } } - /* Enable CRS on Tx. This must be set for half-duplex operation. */ + /* Enable CRS on Tx. This must be set for half-duplex operation. + * Not required on some PHYs. + */ ret_val = hw->phy.ops.read_reg(hw, I82577_CFG_REG, &phy_data); if (ret_val) return ret_val; - phy_data |= I82577_CFG_ASSERT_CRS_ON_TX; + if ((hw->phy.type != e1000_phy_82579) && + (hw->phy.type != e1000_phy_i217)) + phy_data |= I82577_CFG_ASSERT_CRS_ON_TX; /* Enable downshift */ phy_data |= I82577_CFG_ENABLE_DOWNSHIFT; @@ -1072,8 +1077,7 @@ s32 e1000_copper_link_setup_82577(struct e1000_hw *hw) if (ret_val) return ret_val; phy_data &= ~I82577_PHY_CTRL2_MDIX_CFG_MASK; - /* - * Options: + /* Options: * 0 - Auto (default) * 1 - MDI mode * 2 - MDI-X mode @@ -1121,8 +1125,7 @@ s32 e1000_copper_link_setup_m88(struct e1000_hw *hw) if (phy->type != e1000_phy_bm) phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; - /* - * Options: + /* Options: * MDI/MDI-X = 0 (default) * 0 - Auto for all speeds * 1 - MDI mode @@ -1147,8 +1150,7 @@ s32 e1000_copper_link_setup_m88(struct e1000_hw *hw) break; } - /* - * Options: + /* Options: * disable_polarity_correction = 0 (default) * Automatic Correction for Reversed Cable Polarity * 0 - Disabled @@ -1185,8 +1187,7 @@ s32 e1000_copper_link_setup_m88(struct e1000_hw *hw) if ((phy->type == e1000_phy_m88) && (phy->revision < E1000_REVISION_4) && (phy->id != BME1000_E_PHY_ID_R2)) { - /* - * Force TX_CLK in the Extended PHY Specific Control Register + /* Force TX_CLK in the Extended PHY Specific Control Register * to 25MHz clock. */ ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, @@ -1278,8 +1279,7 @@ s32 e1000_copper_link_setup_m88_gen2(struct e1000_hw *hw) if (ret_val) return ret_val; - /* - * Options: + /* Options: * MDI/MDI-X = 0 (default) * 0 - Auto for all speeds * 1 - MDI mode @@ -1307,8 +1307,7 @@ s32 e1000_copper_link_setup_m88_gen2(struct e1000_hw *hw) break; } - /* - * Options: + /* Options: * disable_polarity_correction = 0 (default) * Automatic Correction for Reversed Cable Polarity * 0 - Disabled @@ -1359,14 +1358,12 @@ s32 e1000_copper_link_setup_igp(struct e1000_hw *hw) return ret_val; } - /* - * Wait 100ms for MAC to configure PHY from NVM settings, to avoid + /* Wait 100ms for MAC to configure PHY from NVM settings, to avoid * timeout issues when LFS is enabled. */ msec_delay(100); - /* - * The NVM settings will configure LPLU in D3 for + /* The NVM settings will configure LPLU in D3 for * non-IGP1 PHYs. */ if (phy->type == e1000_phy_igp) { @@ -1411,8 +1408,7 @@ s32 e1000_copper_link_setup_igp(struct e1000_hw *hw) /* set auto-master slave resolution settings */ if (hw->mac.autoneg) { - /* - * when autonegotiation advertisement is only 1000Mbps then we + /* when autonegotiation advertisement is only 1000Mbps then we * should disable SmartSpeed and enable Auto MasterSlave * resolution as hardware default. */ @@ -1481,16 +1477,14 @@ s32 e1000_phy_setup_autoneg(struct e1000_hw *hw) return ret_val; } - /* - * Need to parse both autoneg_advertised and fc and set up + /* Need to parse both autoneg_advertised and fc and set up * the appropriate PHY registers. First we will parse for * autoneg_advertised software override. Since we can advertise * a plethora of combinations, we need to check each bit * individually. */ - /* - * First we clear all the 10/100 mb speed bits in the Auto-Neg + /* First we clear all the 10/100 mb speed bits in the Auto-Neg * Advertisement Register (Address 4) and the 1000 mb speed bits in * the 1000Base-T Control Register (Address 9). */ @@ -1536,8 +1530,7 @@ s32 e1000_phy_setup_autoneg(struct e1000_hw *hw) mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; } - /* - * Check for a software override of the flow control settings, and + /* Check for a software override of the flow control settings, and * setup the PHY advertisement registers accordingly. If * auto-negotiation is enabled, then software will have to set the * "PAUSE" bits to the correct value in the Auto-Negotiation @@ -1556,15 +1549,13 @@ s32 e1000_phy_setup_autoneg(struct e1000_hw *hw) */ switch (hw->fc.current_mode) { case e1000_fc_none: - /* - * Flow control (Rx & Tx) is completely disabled by a + /* Flow control (Rx & Tx) is completely disabled by a * software over-ride. */ mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); break; case e1000_fc_rx_pause: - /* - * Rx Flow control is enabled, and Tx Flow control is + /* Rx Flow control is enabled, and Tx Flow control is * disabled, by a software over-ride. * * Since there really isn't a way to advertise that we are @@ -1576,16 +1567,14 @@ s32 e1000_phy_setup_autoneg(struct e1000_hw *hw) mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); break; case e1000_fc_tx_pause: - /* - * Tx Flow control is enabled, and Rx Flow control is + /* Tx Flow control is enabled, and Rx Flow control is * disabled, by a software over-ride. */ mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; break; case e1000_fc_full: - /* - * Flow control (both Rx and Tx) is enabled by a software + /* Flow control (both Rx and Tx) is enabled by a software * over-ride. */ mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); @@ -1625,14 +1614,12 @@ s32 e1000_copper_link_autoneg(struct e1000_hw *hw) DEBUGFUNC("e1000_copper_link_autoneg"); - /* - * Perform some bounds checking on the autoneg advertisement + /* Perform some bounds checking on the autoneg advertisement * parameter. */ phy->autoneg_advertised &= phy->autoneg_mask; - /* - * If autoneg_advertised is zero, we assume it was not defaulted + /* If autoneg_advertised is zero, we assume it was not defaulted * by the calling code so we set to advertise full capability. */ if (!phy->autoneg_advertised) @@ -1646,8 +1633,7 @@ s32 e1000_copper_link_autoneg(struct e1000_hw *hw) } DEBUGOUT("Restarting Auto-Neg\n"); - /* - * Restart auto-negotiation by setting the Auto Neg Enable bit and + /* Restart auto-negotiation by setting the Auto Neg Enable bit and * the Auto Neg Restart bit in the PHY control register. */ ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl); @@ -1659,12 +1645,11 @@ s32 e1000_copper_link_autoneg(struct e1000_hw *hw) if (ret_val) return ret_val; - /* - * Does the user want to wait for Auto-Neg to complete here, or + /* Does the user want to wait for Auto-Neg to complete here, or * check at a later time (for example, callback routine). */ if (phy->autoneg_wait_to_complete) { - ret_val = hw->mac.ops.wait_autoneg(hw); + ret_val = e1000_wait_autoneg(hw); if (ret_val) { DEBUGOUT("Error while waiting for autoneg to complete\n"); return ret_val; @@ -1693,16 +1678,14 @@ s32 e1000_setup_copper_link_generic(struct e1000_hw *hw) DEBUGFUNC("e1000_setup_copper_link_generic"); if (hw->mac.autoneg) { - /* - * Setup autoneg and flow control advertisement and perform + /* Setup autoneg and flow control advertisement and perform * autonegotiation. */ ret_val = e1000_copper_link_autoneg(hw); if (ret_val) return ret_val; } else { - /* - * PHY will be set to 10H, 10F, 100H or 100F + /* PHY will be set to 10H, 10F, 100H or 100F * depending on user settings. */ DEBUGOUT("Forcing Speed and Duplex\n"); @@ -1713,8 +1696,7 @@ s32 e1000_setup_copper_link_generic(struct e1000_hw *hw) } } - /* - * Check link status. Wait up to 100 microseconds for link to become + /* Check link status. Wait up to 100 microseconds for link to become * valid. */ ret_val = e1000_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10, @@ -1760,8 +1742,7 @@ s32 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw) if (ret_val) return ret_val; - /* - * Clear Auto-Crossover to force MDI manually. IGP requires MDI + /* Clear Auto-Crossover to force MDI manually. IGP requires MDI * forced whenever speed and duplex are forced. */ ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); @@ -1817,18 +1798,22 @@ s32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw) DEBUGFUNC("e1000_phy_force_speed_duplex_m88"); - /* - * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI - * forced whenever speed and duplex are forced. - */ - ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); - if (ret_val) - return ret_val; + /* I210 and I211 devices support Auto-Crossover in forced operation. */ + if (phy->type != e1000_phy_i210) { + /* Clear Auto-Crossover to force MDI manually. M88E1000 + * requires MDI forced whenever speed and duplex are forced. + */ + ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, + &phy_data); + if (ret_val) + return ret_val; - phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; - ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); - if (ret_val) - return ret_val; + phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; + ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, + phy_data); + if (ret_val) + return ret_val; + } DEBUGOUT1("M88E1000 PSCR: %X\n", phy_data); @@ -1874,8 +1859,7 @@ s32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw) if (!reset_dsp) { DEBUGOUT("Link taking longer than expected.\n"); } else { - /* - * We didn't get link. + /* We didn't get link. * Reset the DSP and cross our fingers. */ ret_val = phy->ops.write_reg(hw, @@ -1909,8 +1893,7 @@ s32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw) if (ret_val) return ret_val; - /* - * Resetting the phy means we need to re-force TX_CLK in the + /* Resetting the phy means we need to re-force TX_CLK in the * Extended PHY Specific Control Register to 25MHz clock from * the reset value of 2.5MHz. */ @@ -1919,8 +1902,7 @@ s32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw) if (ret_val) return ret_val; - /* - * In addition, we must re-enable CRS on Tx for both half and full + /* In addition, we must re-enable CRS on Tx for both half and full * duplex. */ ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); @@ -2045,11 +2027,10 @@ void e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl) if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) { ctrl |= E1000_CTRL_SPD_100; *phy_ctrl |= MII_CR_SPEED_100; - *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10); + *phy_ctrl &= ~MII_CR_SPEED_1000; DEBUGOUT("Forcing 100mb\n"); } else { ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); - *phy_ctrl |= MII_CR_SPEED_10; *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); DEBUGOUT("Forcing 10mb\n"); } @@ -2094,8 +2075,7 @@ s32 e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active) data); if (ret_val) return ret_val; - /* - * LPLU and SmartSpeed are mutually exclusive. LPLU is used + /* LPLU and SmartSpeed are mutually exclusive. LPLU is used * during Dx states where the power conservation is most * important. During driver activity we should enable * SmartSpeed, so performance is maintained. @@ -2238,8 +2218,7 @@ s32 e1000_check_polarity_igp(struct e1000_hw *hw) DEBUGFUNC("e1000_check_polarity_igp"); - /* - * Polarity is determined based on the speed of + /* Polarity is determined based on the speed of * our connection. */ ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data); @@ -2251,8 +2230,7 @@ s32 e1000_check_polarity_igp(struct e1000_hw *hw) offset = IGP01E1000_PHY_PCS_INIT_REG; mask = IGP01E1000_PHY_POLARITY_MASK; } else { - /* - * This really only applies to 10Mbps since + /* This really only applies to 10Mbps since * there is no polarity for 100Mbps (always 0). */ offset = IGP01E1000_PHY_PORT_STATUS; @@ -2283,8 +2261,7 @@ s32 e1000_check_polarity_ife(struct e1000_hw *hw) DEBUGFUNC("e1000_check_polarity_ife"); - /* - * Polarity is determined based on the reversal feature being enabled. + /* Polarity is determined based on the reversal feature being enabled. */ if (phy->polarity_correction) { offset = IFE_PHY_EXTENDED_STATUS_CONTROL; @@ -2305,18 +2282,18 @@ s32 e1000_check_polarity_ife(struct e1000_hw *hw) } /** - * e1000_wait_autoneg_generic - Wait for auto-neg completion + * e1000_wait_autoneg - Wait for auto-neg completion * @hw: pointer to the HW structure * * Waits for auto-negotiation to complete or for the auto-negotiation time * limit to expire, which ever happens first. **/ -s32 e1000_wait_autoneg_generic(struct e1000_hw *hw) +static s32 e1000_wait_autoneg(struct e1000_hw *hw) { s32 ret_val = E1000_SUCCESS; u16 i, phy_status; - DEBUGFUNC("e1000_wait_autoneg_generic"); + DEBUGFUNC("e1000_wait_autoneg"); if (!hw->phy.ops.read_reg) return E1000_SUCCESS; @@ -2334,8 +2311,7 @@ s32 e1000_wait_autoneg_generic(struct e1000_hw *hw) msec_delay(100); } - /* - * PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation + /* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation * has completed. */ return ret_val; @@ -2362,15 +2338,13 @@ s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations, return E1000_SUCCESS; for (i = 0; i < iterations; i++) { - /* - * Some PHYs require the PHY_STATUS register to be read + /* Some PHYs require the PHY_STATUS register to be read * twice due to the link bit being sticky. No harm doing * it across the board. */ ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); if (ret_val) - /* - * If the first read fails, another entity may have + /* If the first read fails, another entity may have * ownership of the resources, wait and try again to * see if they have relinquished the resources yet. */ @@ -2436,7 +2410,8 @@ s32 e1000_get_cable_length_m88_gen2(struct e1000_hw *hw) { struct e1000_phy_info *phy = &hw->phy; s32 ret_val; - u16 phy_data, phy_data2, index, default_page, is_cm; + u16 phy_data, phy_data2, is_cm; + u16 index, default_page; DEBUGFUNC("e1000_get_cable_length_m88_gen2"); @@ -2574,8 +2549,7 @@ s32 e1000_get_cable_length_igp_2(struct e1000_hw *hw) if (ret_val) return ret_val; - /* - * Getting bits 15:9, which represent the combination of + /* Getting bits 15:9, which represent the combination of * coarse and fine gain values. The result is a number * that can be put into the lookup table to obtain the * approximate cable length. @@ -2961,15 +2935,13 @@ s32 e1000_phy_init_script_igp3(struct e1000_hw *hw) hw->phy.ops.write_reg(hw, 0x1796, 0x0008); /* Change cg_icount + enable integbp for channels BCD */ hw->phy.ops.write_reg(hw, 0x1798, 0xD008); - /* - * Change cg_icount + enable integbp + change prop_factor_master + /* Change cg_icount + enable integbp + change prop_factor_master * to 8 for channel A */ hw->phy.ops.write_reg(hw, 0x1898, 0xD918); /* Disable AHT in Slave mode on channel A */ hw->phy.ops.write_reg(hw, 0x187A, 0x0800); - /* - * Enable LPLU and disable AN to 1000 in non-D0a states, + /* Enable LPLU and disable AN to 1000 in non-D0a states, * Enable SPD+B2B */ hw->phy.ops.write_reg(hw, 0x0019, 0x008D); @@ -3030,6 +3002,9 @@ enum e1000_phy_type e1000_get_phy_type_from_id(u32 phy_id) case I82579_E_PHY_ID: phy_type = e1000_phy_82579; break; + case I217_E_PHY_ID: + phy_type = e1000_phy_i217; + break; case I82580_I_PHY_ID: phy_type = e1000_phy_82580; break; @@ -3067,8 +3042,7 @@ s32 e1000_determine_phy_address(struct e1000_hw *hw) e1000_get_phy_id(hw); phy_type = e1000_get_phy_type_from_id(hw->phy.id); - /* - * If phy_type is valid, break - we found our + /* If phy_type is valid, break - we found our * PHY address */ if (phy_type != e1000_phy_unknown) @@ -3130,8 +3104,7 @@ s32 e1000_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data) if (offset > MAX_PHY_MULTI_PAGE_REG) { u32 page_shift, page_select; - /* - * Page select is register 31 for phy address 1 and 22 for + /* Page select is register 31 for phy address 1 and 22 for * phy address 2 and 3. Page select is shifted only for * phy address 1. */ @@ -3191,8 +3164,7 @@ s32 e1000_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data) if (offset > MAX_PHY_MULTI_PAGE_REG) { u32 page_shift, page_select; - /* - * Page select is register 31 for phy address 1 and 22 for + /* Page select is register 31 for phy address 1 and 22 for * phy address 2 and 3. Page select is shifted only for * phy address 1. */ @@ -3249,7 +3221,6 @@ s32 e1000_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data) hw->phy.addr = 1; if (offset > MAX_PHY_MULTI_PAGE_REG) { - /* Page is shifted left, PHY expects (page x 32) */ ret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT, page); @@ -3346,8 +3317,7 @@ s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg) return ret_val; } - /* - * Enable both PHY wakeup mode and Wakeup register page writes. + /* Enable both PHY wakeup mode and Wakeup register page writes. * Prevent a power state change by disabling ME and Host PHY wakeup. */ temp = *phy_reg; @@ -3361,8 +3331,7 @@ s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg) return ret_val; } - /* - * Select Host Wakeup Registers page - caller now able to write + /* Select Host Wakeup Registers page - caller now able to write * registers on the Wakeup registers page */ return e1000_set_page_igp(hw, (BM_WUC_PAGE << IGP_PAGE_SHIFT)); @@ -3381,7 +3350,7 @@ s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg) **/ s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg) { - s32 ret_val = E1000_SUCCESS; + s32 ret_val; DEBUGFUNC("e1000_disable_phy_wakeup_reg_access_bm"); @@ -3434,6 +3403,7 @@ static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset, { s32 ret_val; u16 reg = BM_PHY_REG_NUM(offset); + u16 page = BM_PHY_REG_PAGE(offset); u16 phy_reg = 0; DEBUGFUNC("e1000_access_phy_wakeup_reg_bm"); @@ -3687,8 +3657,7 @@ static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data, if (page == HV_INTC_FC_PAGE_START) page = 0; - /* - * Workaround MDIO accesses being disabled after entering IEEE + /* Workaround MDIO accesses being disabled after entering IEEE * Power Down (when bit 11 of the PHY Control register is set) */ if ((hw->phy.type == e1000_phy_82578) && @@ -3801,8 +3770,8 @@ static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset, u16 *data, bool read) { s32 ret_val; - u32 addr_reg = 0; - u32 data_reg = 0; + u32 addr_reg; + u32 data_reg; DEBUGFUNC("e1000_access_phy_debug_regs_hv"); @@ -3875,8 +3844,8 @@ s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw) /* flush the packets in the fifo buffer */ ret_val = hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL, - HV_MUX_DATA_CTRL_GEN_TO_MAC | - HV_MUX_DATA_CTRL_FORCE_SPEED); + (HV_MUX_DATA_CTRL_GEN_TO_MAC | + HV_MUX_DATA_CTRL_FORCE_SPEED)); if (ret_val) return ret_val; @@ -4044,7 +4013,7 @@ s32 e1000_get_cable_length_82577(struct e1000_hw *hw) I82577_DSTATUS_CABLE_LENGTH_SHIFT; if (length == E1000_CABLE_LENGTH_UNDEFINED) - ret_val = -E1000_ERR_PHY; + return -E1000_ERR_PHY; phy->cable_length = length; @@ -4113,3 +4082,4 @@ release: hw->phy.ops.release(hw); return ret_val; } + diff --git a/sys/dev/e1000/e1000_phy.h b/sys/dev/e1000/e1000_phy.h index edcbcab..9911df77 100644 --- a/sys/dev/e1000/e1000_phy.h +++ b/sys/dev/e1000/e1000_phy.h @@ -1,6 +1,6 @@ /****************************************************************************** - Copyright (c) 2001-2012, Intel Corporation + Copyright (c) 2001-2013, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without @@ -78,13 +78,11 @@ s32 e1000_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data); s32 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data); s32 e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active); s32 e1000_setup_copper_link_generic(struct e1000_hw *hw); -s32 e1000_wait_autoneg_generic(struct e1000_hw *hw); s32 e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data); s32 e1000_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data); s32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data); s32 e1000_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data); s32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data); -s32 e1000_phy_reset_dsp(struct e1000_hw *hw); s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations, u32 usec_interval, bool *success); s32 e1000_phy_init_script_igp3(struct e1000_hw *hw); @@ -127,7 +125,6 @@ s32 e1000_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data); #define IGP01E1000_PHY_PORT_CTRL 0x12 /* Control */ #define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health */ #define IGP01E1000_GMII_FIFO 0x14 /* GMII FIFO */ -#define IGP01E1000_PHY_CHANNEL_QUALITY 0x15 /* PHY Channel Quality */ #define IGP02E1000_PHY_POWER_MGMT 0x19 /* Power Management */ #define IGP01E1000_PHY_PAGE_SELECT 0x1F /* Page Select */ #define BM_PHY_PAGE_SELECT 22 /* Page Select for BM */ @@ -147,7 +144,6 @@ s32 e1000_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data); /* BM/HV Specific Registers */ #define BM_PORT_CTRL_PAGE 769 -#define BM_PCIE_PAGE 770 #define BM_WUC_PAGE 800 #define BM_WUC_ADDRESS_OPCODE 0x11 #define BM_WUC_DATA_OPCODE 0x12 @@ -188,7 +184,6 @@ s32 e1000_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data); #define I82577_PHY_STATUS2_MDIX 0x0800 #define I82577_PHY_STATUS2_SPEED_MASK 0x0300 #define I82577_PHY_STATUS2_SPEED_1000MBPS 0x0200 -#define I82577_PHY_STATUS2_SPEED_100MBPS 0x0100 /* I82577 PHY Control 2 */ #define I82577_PHY_CTRL2_MANUAL_MDIX 0x0200 @@ -204,14 +199,13 @@ s32 e1000_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data); #define E1000_82580_PM_SPD 0x0001 /* Smart Power Down */ #define E1000_82580_PM_D0_LPLU 0x0002 /* For D0a states */ #define E1000_82580_PM_D3_LPLU 0x0004 /* For all other states */ +#define E1000_82580_PM_GO_LINKD 0x0020 /* Go Link Disconnect */ /* BM PHY Copper Specific Control 1 */ #define BM_CS_CTRL1 16 -#define BM_CS_CTRL1_ENERGY_DETECT 0x0300 /* Enable Energy Detect */ /* BM PHY Copper Specific Status */ #define BM_CS_STATUS 17 -#define BM_CS_STATUS_ENERGY_DETECT 0x0010 /* Energy Detect Status */ #define BM_CS_STATUS_LINK_UP 0x0400 #define BM_CS_STATUS_RESOLVED 0x0800 #define BM_CS_STATUS_SPEED_MASK 0xC000 @@ -257,9 +251,6 @@ s32 e1000_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data); #define IGP02E1000_AGC_LENGTH_MASK 0x7F #define IGP02E1000_AGC_RANGE 15 -#define IGP03E1000_PHY_MISC_CTRL 0x1B -#define IGP03E1000_PHY_MISC_DUPLEX_MANUAL_SET 0x1000 /* Manually Set Duplex */ - #define E1000_CABLE_LENGTH_UNDEFINED 0xFF #define E1000_KMRNCTRLSTA_OFFSET 0x001F0000 @@ -272,7 +263,7 @@ s32 e1000_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data); #define E1000_KMRNCTRLSTA_IBIST_DISABLE 0x0200 /* Kumeran IBIST Disable */ #define E1000_KMRNCTRLSTA_DIAG_NELPBK 0x1000 /* Nearend Loopback mode */ #define E1000_KMRNCTRLSTA_K1_CONFIG 0x7 -#define E1000_KMRNCTRLSTA_K1_ENABLE 0x0002 +#define E1000_KMRNCTRLSTA_K1_ENABLE 0x0002 /* enable K1 */ #define E1000_KMRNCTRLSTA_HD_CTRL 0x10 /* Kumeran HD Control */ #define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10 @@ -286,7 +277,6 @@ s32 e1000_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data); /* IFE PHY Special Control */ #define IFE_PSC_AUTO_POLARITY_DISABLE 0x0010 #define IFE_PSC_FORCE_POLARITY 0x0020 -#define IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN 0x0100 /* IFE PHY Special Control and LED Control */ #define IFE_PSCL_PROBE_MODE 0x0020 diff --git a/sys/dev/e1000/e1000_regs.h b/sys/dev/e1000/e1000_regs.h index 8c4e4af..516d377 100644 --- a/sys/dev/e1000/e1000_regs.h +++ b/sys/dev/e1000/e1000_regs.h @@ -1,6 +1,6 @@ /****************************************************************************** - Copyright (c) 2001-2012, Intel Corporation + Copyright (c) 2001-2013, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without @@ -55,9 +55,11 @@ #define E1000_SCTL 0x00024 /* SerDes Control - RW */ #define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */ #define E1000_FCAH 0x0002C /* Flow Control Address High -RW */ -#define E1000_FEXT 0x0002C /* Future Extended - RW */ -#define E1000_FEXTNVM4 0x00024 /* Future Extended NVM 4 - RW */ #define E1000_FEXTNVM 0x00028 /* Future Extended NVM - RW */ +#define E1000_FEXTNVM3 0x0003C /* Future Extended NVM 3 - RW */ +#define E1000_FEXTNVM4 0x00024 /* Future Extended NVM 4 - RW */ +#define E1000_FEXTNVM6 0x00010 /* Future Extended NVM 6 - RW */ +#define E1000_FEXTNVM7 0x000E4 /* Future Extended NVM 7 - RW */ #define E1000_FCT 0x00030 /* Flow Control Type - RW */ #define E1000_CONNSW 0x00034 /* Copper/Fiber switch control - RW */ #define E1000_VET 0x00038 /* VLAN Ether Type - RW */ @@ -70,6 +72,7 @@ #define E1000_IVAR 0x000E4 /* Interrupt Vector Allocation Register - RW */ #define E1000_SVCR 0x000F0 #define E1000_SVT 0x000F4 +#define E1000_LPIC 0x000FC /* Low Power IDLE control */ #define E1000_RCTL 0x00100 /* Rx Control - RW */ #define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */ #define E1000_TXCW 0x00178 /* Tx Configuration Word - RW */ @@ -97,6 +100,7 @@ #define E1000_POEMB E1000_PHY_CTRL /* PHY OEM Bits */ #define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */ #define E1000_PBS 0x01008 /* Packet Buffer Size */ +#define E1000_PBECCSTS 0x0100C /* Packet Buffer ECC Status - RW */ #define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */ #define E1000_EEARBC 0x01024 /* EEPROM Auto Read Bus Control */ #define E1000_FLASHT 0x01028 /* FLASH Timer Register */ @@ -129,7 +133,11 @@ #define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */ #define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */ #define E1000_PSRCTL 0x02170 /* Packet Split Receive Control - RW */ -#define E1000_RDFPCQ(_n) (0x02430 + (0x4 * (_n))) +#define E1000_RDFH 0x02410 /* Rx Data FIFO Head - RW */ +#define E1000_RDFT 0x02418 /* Rx Data FIFO Tail - RW */ +#define E1000_RDFHS 0x02420 /* Rx Data FIFO Head Saved - RW */ +#define E1000_RDFTS 0x02428 /* Rx Data FIFO Tail Saved - RW */ +#define E1000_RDFPC 0x02430 /* Rx Data FIFO Packet Count - RW */ #define E1000_PBRTH 0x02458 /* PB Rx Arbitration Threshold - RW */ #define E1000_FCRTV 0x02460 /* Flow Control Refresh Timer Value - RW */ /* Split and Replication Rx Control - RW */ @@ -200,8 +208,7 @@ /* Queues packet buffer size masks where _n can be 0-3 and _s 0-63 [kB] */ #define E1000_I210_TXPBS_SIZE(_n, _s) ((_s) << (6 * _n)) -/* - * Convenience macros +/* Convenience macros * * Note: "_n" is the queue number of the register to be written to. * @@ -413,8 +420,7 @@ #define E1000_LSECTXKEY1(_n) (0x0B030 + (0x04 * (_n))) #define E1000_LSECRXSA(_n) (0x0B310 + (0x04 * (_n))) /* Rx SAs - RW */ #define E1000_LSECRXPN(_n) (0x0B330 + (0x04 * (_n))) /* Rx SAs - RW */ -/* - * LinkSec Rx Keys - where _n is the SA no. and _m the 4 dwords of the 128 bit +/* LinkSec Rx Keys - where _n is the SA no. and _m the 4 dwords of the 128 bit * key - RW. */ #define E1000_LSECRXKEY(_n, _m) (0x0B350 + (0x10 * (_n)) + (0x04 * (_m))) @@ -454,7 +460,6 @@ #define E1000_PCS_LPAB 0x0421C /* Link Partner Ability - RW */ #define E1000_PCS_NPTX 0x04220 /* AN Next Page Transmit - RW */ #define E1000_PCS_LPABNP 0x04224 /* Link Partner Ability Next Pg - RW */ -#define E1000_1GSTAT_RCV 0x04228 /* 1GSTAT Code Violation Pkt Cnt - RW */ #define E1000_RXCSUM 0x05000 /* Rx Checksum Control - RW */ #define E1000_RLPML 0x05004 /* Rx Long Packet Max Length */ #define E1000_RFCTL 0x05008 /* Receive Filter Control*/ @@ -489,7 +494,6 @@ #define E1000_KMRNCTRLSTA 0x00034 /* MAC-PHY interface - RW */ -#define E1000_MDPHYA 0x0003C /* PHY address - RW */ #define E1000_MANC2H 0x05860 /* Management Control To Host - RW */ /* Management Decision Filters */ #define E1000_MDEF(_n) (0x05890 + (4 * (_n))) @@ -522,15 +526,6 @@ #define E1000_IMIREXT(_i) (0x05AA0 + ((_i) * 4)) /* Immediate INTR Ext*/ #define E1000_IMIRVP 0x05AC0 /* Immediate INT Rx VLAN Priority -RW */ #define E1000_MSIXBM(_i) (0x01600 + ((_i) * 4)) /* MSI-X Alloc Reg -RW */ -/* MSI-X Table entry addr low reg - RW */ -#define E1000_MSIXTADD(_i) (0x0C000 + ((_i) * 0x10)) -/* MSI-X Table entry addr upper reg - RW */ -#define E1000_MSIXTUADD(_i) (0x0C004 + ((_i) * 0x10)) -/* MSI-X Table entry message reg - RW */ -#define E1000_MSIXTMSG(_i) (0x0C008 + ((_i) * 0x10)) -/* MSI-X Table entry vector ctrl reg - RW */ -#define E1000_MSIXVCTRL(_i) (0x0C00C + ((_i) * 0x10)) -#define E1000_MSIXPBA 0x0E000 /* MSI-X Pending bit array */ #define E1000_RETA(_i) (0x05C00 + ((_i) * 4)) /* Redirection Table - RW */ #define E1000_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* RSS Random Key - RW */ #define E1000_RSSIM 0x05864 /* RSS Interrupt Mask */ @@ -580,8 +575,12 @@ #define E1000_SYSTIML 0x0B600 /* System time register Low - RO */ #define E1000_SYSTIMH 0x0B604 /* System time register High - RO */ #define E1000_TIMINCA 0x0B608 /* Increment attributes register - RW */ +#define E1000_TIMADJL 0x0B60C /* Time sync time adjustment offset Low - RW */ +#define E1000_TIMADJH 0x0B610 /* Time sync time adjustment offset High - RW */ #define E1000_TSAUXC 0x0B640 /* Timesync Auxiliary Control register */ #define E1000_SYSTIMR 0x0B6F8 /* System time register Residue */ +#define E1000_TSICR 0x0B66C /* Interrupt Cause Register */ +#define E1000_TSIM 0x0B674 /* Interrupt Mask Register */ #define E1000_RXMTRL 0x0B634 /* Time sync Rx EtherType and Msg Type - RW */ #define E1000_RXUDP 0x0B638 /* Time Sync Rx UDP Port - RW */ @@ -671,8 +670,6 @@ #define E1000_O2BGPTC 0x08FE4 /* OS2BMC packets received by BMC */ #define E1000_O2BSPC 0x0415C /* OS2BMC packets transmitted by host */ -#define E1000_LTRMINV 0x5BB0 /* LTR Minimum Value */ -#define E1000_LTRMAXV 0x5BB4 /* LTR Maximum Value */ #define E1000_DOBFFCTL 0x3F24 /* DMA OBFF Control Register */ diff --git a/sys/dev/e1000/if_em.c b/sys/dev/e1000/if_em.c index a431266..64be42d 100644 --- a/sys/dev/e1000/if_em.c +++ b/sys/dev/e1000/if_em.c @@ -1,6 +1,6 @@ /****************************************************************************** - Copyright (c) 2001-2011, Intel Corporation + Copyright (c) 2001-2013, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without @@ -94,7 +94,7 @@ int em_display_debug_stats = 0; /********************************************************************* * Driver version: *********************************************************************/ -char em_driver_version[] = "7.3.2"; +char em_driver_version[] = "7.3.7"; /********************************************************************* * PCI Device ID Table @@ -172,6 +172,12 @@ static em_vendor_info_t em_vendor_info_array[] = { 0x8086, E1000_DEV_ID_PCH_D_HV_DC, PCI_ANY_ID, PCI_ANY_ID, 0}, { 0x8086, E1000_DEV_ID_PCH2_LV_LM, PCI_ANY_ID, PCI_ANY_ID, 0}, { 0x8086, E1000_DEV_ID_PCH2_LV_V, PCI_ANY_ID, PCI_ANY_ID, 0}, + { 0x8086, E1000_DEV_ID_PCH_LPT_I217_LM, PCI_ANY_ID, PCI_ANY_ID, 0}, + { 0x8086, E1000_DEV_ID_PCH_LPT_I217_V, PCI_ANY_ID, PCI_ANY_ID, 0}, + { 0x8086, E1000_DEV_ID_PCH_LPTLP_I218_LM, + PCI_ANY_ID, PCI_ANY_ID, 0}, + { 0x8086, E1000_DEV_ID_PCH_LPTLP_I218_V, + PCI_ANY_ID, PCI_ANY_ID, 0}, /* required last entry */ { 0, 0, 0, 0, 0} }; @@ -520,7 +526,8 @@ em_attach(device_t dev) (hw->mac.type == e1000_ich9lan) || (hw->mac.type == e1000_ich10lan) || (hw->mac.type == e1000_pchlan) || - (hw->mac.type == e1000_pch2lan)) { + (hw->mac.type == e1000_pch2lan) || + (hw->mac.type == e1000_pch_lpt)) { int rid = EM_BAR_TYPE_FLASH; adapter->flash = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); @@ -605,8 +612,8 @@ em_attach(device_t dev) * Set the frame limits assuming * standard ethernet sized frames. */ - adapter->max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHERNET_FCS_SIZE; - adapter->min_frame_size = ETH_ZLEN + ETHERNET_FCS_SIZE; + adapter->hw.mac.max_frame_size = + ETHERMTU + ETHER_HDR_LEN + ETHERNET_FCS_SIZE; /* * This controls when hardware reports transmit completion @@ -907,19 +914,17 @@ em_mq_start_locked(struct ifnet *ifp, struct tx_ring *txr, struct mbuf *m) enq = 0; if (m != NULL) { err = drbr_enqueue(ifp, txr->br, m); - if (err) { + if (err) return (err); - } } /* Process the queue */ while ((next = drbr_peek(ifp, txr->br)) != NULL) { if ((err = em_xmit(txr, &next)) != 0) { - if (next == NULL) { + if (next == NULL) drbr_advance(ifp, txr->br); - } else { + else drbr_putback(ifp, txr->br, next); - } break; } drbr_advance(ifp, txr->br); @@ -1108,6 +1113,7 @@ em_ioctl(struct ifnet *ifp, u_long command, caddr_t data) case e1000_ich9lan: case e1000_ich10lan: case e1000_pch2lan: + case e1000_pch_lpt: case e1000_82574: case e1000_82583: case e1000_80003es2lan: /* 9K Jumbo Frame size */ @@ -1131,7 +1137,7 @@ em_ioctl(struct ifnet *ifp, u_long command, caddr_t data) } ifp->if_mtu = ifr->ifr_mtu; - adapter->max_frame_size = + adapter->hw.mac.max_frame_size = ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; em_init_locked(adapter); EM_CORE_UNLOCK(adapter); @@ -1326,9 +1332,9 @@ em_init_locked(struct adapter *adapter) ** Figure out the desired mbuf ** pool for doing jumbos */ - if (adapter->max_frame_size <= 2048) + if (adapter->hw.mac.max_frame_size <= 2048) adapter->rx_mbuf_sz = MCLBYTES; - else if (adapter->max_frame_size <= 4096) + else if (adapter->hw.mac.max_frame_size <= 4096) adapter->rx_mbuf_sz = MJUMPAGESIZE; else adapter->rx_mbuf_sz = MJUM9BYTES; @@ -2817,17 +2823,18 @@ em_reset(struct adapter *adapter) case e1000_ich9lan: case e1000_ich10lan: /* Boost Receive side for jumbo frames */ - if (adapter->max_frame_size > 4096) + if (adapter->hw.mac.max_frame_size > 4096) pba = E1000_PBA_14K; else pba = E1000_PBA_10K; break; case e1000_pchlan: case e1000_pch2lan: + case e1000_pch_lpt: pba = E1000_PBA_26K; break; default: - if (adapter->max_frame_size > 8192) + if (adapter->hw.mac.max_frame_size > 8192) pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ else pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ @@ -2850,7 +2857,7 @@ em_reset(struct adapter *adapter) */ rx_buffer_size = ((E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10 ); hw->fc.high_water = rx_buffer_size - - roundup2(adapter->max_frame_size, 1024); + roundup2(adapter->hw.mac.max_frame_size, 1024); hw->fc.low_water = hw->fc.high_water - 1500; if (adapter->fc) /* locally set flow control value? */ @@ -2881,6 +2888,7 @@ em_reset(struct adapter *adapter) hw->fc.refresh_time = 0x1000; break; case e1000_pch2lan: + case e1000_pch_lpt: hw->fc.high_water = 0x5C20; hw->fc.low_water = 0x5048; hw->fc.pause_time = 0x0650; @@ -4341,7 +4349,7 @@ em_initialize_receive_unit(struct adapter *adapter) E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl | 3); } - if (adapter->hw.mac.type == e1000_pch2lan) { + if (adapter->hw.mac.type >= e1000_pch2lan) { if (ifp->if_mtu > ETHERMTU) e1000_lv_jumbo_workaround_ich8lan(hw, TRUE); else @@ -4475,7 +4483,7 @@ em_rxeof(struct rx_ring *rxr, int count, int *done) ifp->if_ipackets++; em_receive_checksum(cur, sendmp); #ifndef __NO_STRICT_ALIGNMENT - if (adapter->max_frame_size > + if (adapter->hw.mac.max_frame_size > (MCLBYTES - ETHER_ALIGN) && em_fixup_rx(rxr) != 0) goto skip; diff --git a/sys/dev/e1000/if_igb.c b/sys/dev/e1000/if_igb.c index 8c6b429..30bb052 100644 --- a/sys/dev/e1000/if_igb.c +++ b/sys/dev/e1000/if_igb.c @@ -1,6 +1,6 @@ /****************************************************************************** - Copyright (c) 2001-2012, Intel Corporation + Copyright (c) 2001-2013, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without @@ -100,7 +100,7 @@ int igb_display_debug_stats = 0; /********************************************************************* * Driver version: *********************************************************************/ -char igb_driver_version[] = "version - 2.3.5"; +char igb_driver_version[] = "version - 2.3.9"; /********************************************************************* @@ -949,7 +949,8 @@ igb_start(struct ifnet *ifp) #else /* __FreeBSD_version >= 800000 */ /* -** Multiqueue Transmit driver +** Multiqueue Transmit Entry: +** quick turnaround to the stack ** */ static int @@ -965,25 +966,11 @@ igb_mq_start(struct ifnet *ifp, struct mbuf *m) i = m->m_pkthdr.flowid % adapter->num_queues; else i = curcpu % adapter->num_queues; - txr = &adapter->tx_rings[i]; que = &adapter->queues[i]; - if (((txr->queue_status & IGB_QUEUE_DEPLETED) == 0) && - IGB_TX_TRYLOCK(txr)) { - /* - ** Try to queue first to avoid - ** out-of-order delivery, but - ** settle for it if that fails - */ - if (m != NULL) - drbr_enqueue(ifp, txr->br, m); - err = igb_mq_start_locked(ifp, txr); - IGB_TX_UNLOCK(txr); - } else { - if (m != NULL) - err = drbr_enqueue(ifp, txr->br, m); - taskqueue_enqueue(que->tq, &txr->txq_task); - } + + err = drbr_enqueue(ifp, txr->br, m); + taskqueue_enqueue(que->tq, &txr->txq_task); return (err); } @@ -998,9 +985,8 @@ igb_mq_start_locked(struct ifnet *ifp, struct tx_ring *txr) IGB_TX_LOCK_ASSERT(txr); if (((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) || - (txr->queue_status & IGB_QUEUE_DEPLETED) || adapter->link_active == 0) - return (err); + return (ENETDOWN); enq = 0; @@ -1702,7 +1688,6 @@ static void igb_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) { struct adapter *adapter = ifp->if_softc; - u_char fiber_type = IFM_1000_SX; INIT_DEBUGOUT("igb_media_status: begin"); @@ -1719,26 +1704,31 @@ igb_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) ifmr->ifm_status |= IFM_ACTIVE; - if ((adapter->hw.phy.media_type == e1000_media_type_fiber) || - (adapter->hw.phy.media_type == e1000_media_type_internal_serdes)) - ifmr->ifm_active |= fiber_type | IFM_FDX; - else { - switch (adapter->link_speed) { - case 10: - ifmr->ifm_active |= IFM_10_T; - break; - case 100: - ifmr->ifm_active |= IFM_100_TX; - break; - case 1000: - ifmr->ifm_active |= IFM_1000_T; - break; - } - if (adapter->link_duplex == FULL_DUPLEX) - ifmr->ifm_active |= IFM_FDX; + switch (adapter->link_speed) { + case 10: + ifmr->ifm_active |= IFM_10_T; + break; + case 100: + /* + ** Support for 100Mb SFP - these are Fiber + ** but the media type appears as serdes + */ + if (adapter->hw.phy.media_type == + e1000_media_type_internal_serdes) + ifmr->ifm_active |= IFM_100_FX; else - ifmr->ifm_active |= IFM_HDX; + ifmr->ifm_active |= IFM_100_TX; + break; + case 1000: + ifmr->ifm_active |= IFM_1000_T; + break; } + + if (adapter->link_duplex == FULL_DUPLEX) + ifmr->ifm_active |= IFM_FDX; + else + ifmr->ifm_active |= IFM_HDX; + IGB_CORE_UNLOCK(adapter); } @@ -2241,11 +2231,13 @@ timeout: static void igb_update_link_status(struct adapter *adapter) { - struct e1000_hw *hw = &adapter->hw; - struct ifnet *ifp = adapter->ifp; - device_t dev = adapter->dev; - struct tx_ring *txr = adapter->tx_rings; - u32 link_check, thstat, ctrl; + struct e1000_hw *hw = &adapter->hw; + struct e1000_fc_info *fc = &hw->fc; + struct ifnet *ifp = adapter->ifp; + device_t dev = adapter->dev; + struct tx_ring *txr = adapter->tx_rings; + u32 link_check, thstat, ctrl; + char *flowctl = NULL; link_check = thstat = ctrl = 0; @@ -2283,15 +2275,33 @@ igb_update_link_status(struct adapter *adapter) ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT); } + /* Get the flow control for display */ + switch (fc->current_mode) { + case e1000_fc_rx_pause: + flowctl = "RX"; + break; + case e1000_fc_tx_pause: + flowctl = "TX"; + break; + case e1000_fc_full: + flowctl = "Full"; + break; + case e1000_fc_none: + default: + flowctl = "None"; + break; + } + /* Now we check if a transition has happened */ if (link_check && (adapter->link_active == 0)) { e1000_get_speed_and_duplex(&adapter->hw, &adapter->link_speed, &adapter->link_duplex); if (bootverbose) - device_printf(dev, "Link is up %d Mbps %s\n", + device_printf(dev, "Link is up %d Mbps %s," + " Flow Control: %s\n", adapter->link_speed, ((adapter->link_duplex == FULL_DUPLEX) ? - "Full Duplex" : "Half Duplex")); + "Full Duplex" : "Half Duplex"), flowctl); adapter->link_active = 1; ifp->if_baudrate = adapter->link_speed * 1000000; if ((ctrl & E1000_CTRL_EXT_LINK_MODE_GMII) && diff --git a/sys/dev/e1000/if_lem.c b/sys/dev/e1000/if_lem.c index 6b2b4f7..b7d2359 100644 --- a/sys/dev/e1000/if_lem.c +++ b/sys/dev/e1000/if_lem.c @@ -3782,10 +3782,6 @@ lem_setup_vlan_hw_support(struct adapter *adapter) reg &= ~E1000_RCTL_CFIEN; reg |= E1000_RCTL_VFE; E1000_WRITE_REG(hw, E1000_RCTL, reg); - - /* Update the frame size */ - E1000_WRITE_REG(&adapter->hw, E1000_RLPML, - adapter->max_frame_size + VLAN_TAG_SIZE); } static void diff --git a/sys/dev/fdt/fdt_common.h b/sys/dev/fdt/fdt_common.h index 68e3708..d244a17 100644 --- a/sys/dev/fdt/fdt_common.h +++ b/sys/dev/fdt/fdt_common.h @@ -39,7 +39,7 @@ #define FDT_MEM_REGIONS 8 -#define DI_MAX_INTR_NUM 8 +#define DI_MAX_INTR_NUM 32 struct fdt_pci_range { u_long base_pci; diff --git a/sys/dev/firewire/sbp.c b/sys/dev/firewire/sbp.c index 8089d99..5efc5eb 100644 --- a/sys/dev/firewire/sbp.c +++ b/sys/dev/firewire/sbp.c @@ -2488,16 +2488,14 @@ printf("ORB %08x %08x %08x %08x\n", ntohl(ocb->orb[0]), ntohl(ocb->orb[1]), ntoh printf("ORB %08x %08x %08x %08x\n", ntohl(ocb->orb[4]), ntohl(ocb->orb[5]), ntohl(ocb->orb[6]), ntohl(ocb->orb[7])); */ if (ccb->csio.dxfer_len > 0) { - int s, error; + int error; - s = splsoftvm(); error = bus_dmamap_load_ccb(/*dma tag*/sbp->dmat, /*dma map*/ocb->dmamap, ccb, sbp_execute_ocb, ocb, /*flags*/0); - splx(s); if (error) printf("sbp: bus_dmamap_load error %d\n", error); } else diff --git a/sys/dev/led/led.c b/sys/dev/led/led.c index e2a4370..fe0b66b 100644 --- a/sys/dev/led/led.c +++ b/sys/dev/led/led.c @@ -43,6 +43,7 @@ static struct mtx led_mtx; static struct sx led_sx; static LIST_HEAD(, ledsc) led_list = LIST_HEAD_INITIALIZER(led_list); static struct callout led_ch; +static int blinkers = 0; static MALLOC_DEFINE(M_LED, "LED", "LED driver"); @@ -51,7 +52,6 @@ led_timeout(void *p) { struct ledsc *sc; - mtx_lock(&led_mtx); LIST_FOREACH(sc, &led_list, list) { if (sc->ptr == NULL) continue; @@ -61,6 +61,7 @@ led_timeout(void *p) } if (*sc->ptr == '.') { sc->ptr = NULL; + blinkers--; continue; } else if (*sc->ptr == 'U' || *sc->ptr == 'u') { if (sc->last_second == time_second) @@ -78,9 +79,8 @@ led_timeout(void *p) if (*sc->ptr == '\0') sc->ptr = sc->str; } - mtx_unlock(&led_mtx); - callout_reset(&led_ch, hz / 10, led_timeout, p); - return; + if (blinkers > 0) + callout_reset(&led_ch, hz / 10, led_timeout, p); } static int @@ -92,9 +92,15 @@ led_state(struct ledsc *sc, struct sbuf **sb, int state) sc->spec = *sb; if (*sb != NULL) { sc->str = sbuf_data(*sb); + if (sc->ptr == NULL) { + blinkers++; + callout_reset(&led_ch, hz / 10, led_timeout, NULL); + } sc->ptr = sc->str; } else { sc->str = NULL; + if (sc->ptr != NULL) + blinkers--; sc->ptr = NULL; sc->func(sc->private, state); } @@ -286,8 +292,6 @@ led_create_state(led_t *func, void *priv, char const *name, int state) mtx_lock(&led_mtx); sc->dev->si_drv1 = sc; - if (LIST_EMPTY(&led_list)) - callout_reset(&led_ch, hz / 10, led_timeout, NULL); LIST_INSERT_HEAD(&led_list, sc, list); sc->func(sc->private, state != 0); mtx_unlock(&led_mtx); @@ -303,7 +307,8 @@ led_destroy(struct cdev *dev) mtx_lock(&led_mtx); sc = dev->si_drv1; dev->si_drv1 = NULL; - + if (sc->ptr != NULL) + blinkers--; LIST_REMOVE(sc, list); if (LIST_EMPTY(&led_list)) callout_stop(&led_ch); @@ -326,7 +331,7 @@ led_drvinit(void *unused) led_unit = new_unrhdr(0, INT_MAX, NULL); mtx_init(&led_mtx, "LED mtx", NULL, MTX_DEF); sx_init(&led_sx, "LED sx"); - callout_init(&led_ch, CALLOUT_MPSAFE); + callout_init_mtx(&led_ch, &led_mtx, 0); } SYSINIT(leddev, SI_SUB_DRIVERS, SI_ORDER_MIDDLE, led_drvinit, NULL); diff --git a/sys/dev/mcd/mcd.c b/sys/dev/mcd/mcd.c index 86e40c4..3e9617d 100644 --- a/sys/dev/mcd/mcd.c +++ b/sys/dev/mcd/mcd.c @@ -289,7 +289,6 @@ static void mcdstrategy(struct bio *bp) { struct mcd_softc *sc; - int s; sc = (struct mcd_softc *)bp->bio_dev->si_drv1; @@ -318,9 +317,7 @@ mcdstrategy(struct bio *bp) bp->bio_resid = 0; /* queue it */ - s = splbio(); bioq_disksort(&sc->data.head, bp); - splx(s); /* now check whether we can perform processing */ mcd_start(sc); @@ -338,10 +335,8 @@ static void mcd_start(struct mcd_softc *sc) { struct bio *bp; - int s = splbio(); if (sc->data.flags & MCDMBXBSY) { - splx(s); return; } @@ -350,10 +345,8 @@ mcd_start(struct mcd_softc *sc) /* block found to process, dequeue */ /*MCD_TRACE("mcd_start: found block bp=0x%x\n",bp,0,0,0);*/ sc->data.flags |= MCDMBXBSY; - splx(s); } else { /* nothing to do */ - splx(s); return; } diff --git a/sys/dev/mxge/if_mxge.c b/sys/dev/mxge/if_mxge.c index feefc3b..245c139 100644 --- a/sys/dev/mxge/if_mxge.c +++ b/sys/dev/mxge/if_mxge.c @@ -1,6 +1,6 @@ /****************************************************************************** -Copyright (c) 2006-2009, Myricom Inc. +Copyright (c) 2006-2013, Myricom Inc. All rights reserved. Redistribution and use in source and binary forms, with or without @@ -62,7 +62,10 @@ __FBSDID("$FreeBSD$"); #include <netinet/in_systm.h> #include <netinet/in.h> #include <netinet/ip.h> +#include <netinet/ip6.h> #include <netinet/tcp.h> +#include <netinet/tcp_lro.h> +#include <netinet6/ip6_var.h> #include <machine/bus.h> #include <machine/in_cksum.h> @@ -91,6 +94,7 @@ __FBSDID("$FreeBSD$"); #endif #include "opt_inet.h" +#include "opt_inet6.h" /* tunable params */ static int mxge_nvidia_ecrc_enable = 1; @@ -99,7 +103,6 @@ static int mxge_intr_coal_delay = 30; static int mxge_deassert_wait = 1; static int mxge_flow_control = 1; static int mxge_verbose = 0; -static int mxge_lro_cnt = 8; static int mxge_ticks; static int mxge_max_slices = 1; static int mxge_rss_hash_type = MXGEFW_RSS_HASH_TYPE_SRC_DST_PORT; @@ -288,11 +291,12 @@ mxge_parse_strings(mxge_softc_t *sc) #define MXGE_NEXT_STRING(p) while(ptr < limit && *ptr++) char *ptr, *limit; - int i, found_mac; + int i, found_mac, found_sn2; ptr = sc->eeprom_strings; limit = sc->eeprom_strings + MXGE_EEPROM_STRINGS_SIZE; found_mac = 0; + found_sn2 = 0; while (ptr < limit && *ptr != '\0') { if (memcmp(ptr, "MAC=", 4) == 0) { ptr += 1; @@ -308,10 +312,16 @@ mxge_parse_strings(mxge_softc_t *sc) ptr += 3; strncpy(sc->product_code_string, ptr, sizeof (sc->product_code_string) - 1); - } else if (memcmp(ptr, "SN=", 3) == 0) { + } else if (!found_sn2 && (memcmp(ptr, "SN=", 3) == 0)) { ptr += 3; strncpy(sc->serial_number_string, ptr, sizeof (sc->serial_number_string) - 1); + } else if (memcmp(ptr, "SN2=", 4) == 0) { + /* SN2 takes precedence over SN */ + ptr += 4; + found_sn2 = 1; + strncpy(sc->serial_number_string, ptr, + sizeof (sc->serial_number_string) - 1); } MXGE_NEXT_STRING(ptr); } @@ -578,9 +588,10 @@ mxge_firmware_probe(mxge_softc_t *sc) /* * Run a DMA test which watches for unaligned completions and - * aborts on the first one seen. + * aborts on the first one seen. Not required on Z8ES or newer. */ - + if (pci_get_revid(sc->dev) >= MXGE_PCI_REV_Z8ES) + return 0; status = mxge_dma_test(sc, MXGEFW_CMD_UNALIGNED_TEST); if (status == 0) return 0; /* keep the aligned firmware */ @@ -1308,9 +1319,9 @@ mxge_reset(mxge_softc_t *sc, int interrupts_setup) ss->tx.stall = 0; ss->rx_big.cnt = 0; ss->rx_small.cnt = 0; - ss->lro_bad_csum = 0; - ss->lro_queued = 0; - ss->lro_flushed = 0; + ss->lc.lro_bad_csum = 0; + ss->lc.lro_queued = 0; + ss->lc.lro_flushed = 0; if (ss->fw_stats != NULL) { bzero(ss->fw_stats, sizeof *ss->fw_stats); } @@ -1411,50 +1422,6 @@ mxge_change_flow_control(SYSCTL_HANDLER_ARGS) } static int -mxge_change_lro_locked(mxge_softc_t *sc, int lro_cnt) -{ - struct ifnet *ifp; - int err = 0; - - ifp = sc->ifp; - if (lro_cnt == 0) - ifp->if_capenable &= ~IFCAP_LRO; - else - ifp->if_capenable |= IFCAP_LRO; - sc->lro_cnt = lro_cnt; - if (ifp->if_drv_flags & IFF_DRV_RUNNING) { - mxge_close(sc, 0); - err = mxge_open(sc); - } - return err; -} - -static int -mxge_change_lro(SYSCTL_HANDLER_ARGS) -{ - mxge_softc_t *sc; - unsigned int lro_cnt; - int err; - - sc = arg1; - lro_cnt = sc->lro_cnt; - err = sysctl_handle_int(oidp, &lro_cnt, arg2, req); - if (err != 0) - return err; - - if (lro_cnt == sc->lro_cnt) - return 0; - - if (lro_cnt > 128) - return EINVAL; - - mtx_lock(&sc->driver_mtx); - err = mxge_change_lro_locked(sc, lro_cnt); - mtx_unlock(&sc->driver_mtx); - return err; -} - -static int mxge_handle_be32(SYSCTL_HANDLER_ARGS) { int err; @@ -1650,14 +1617,6 @@ mxge_add_sysctls(mxge_softc_t *sc) CTLFLAG_RW, &mxge_verbose, 0, "verbose printing"); - /* lro */ - SYSCTL_ADD_PROC(ctx, children, OID_AUTO, - "lro_cnt", - CTLTYPE_INT|CTLFLAG_RW, sc, - 0, mxge_change_lro, - "I", "number of lro merge queues"); - - /* add counters exported for debugging from all slices */ sysctl_ctx_init(&sc->slice_sysctl_ctx); sc->slice_sysctl_tree = @@ -1683,11 +1642,15 @@ mxge_add_sysctls(mxge_softc_t *sc) CTLFLAG_RD, &ss->rx_big.cnt, 0, "rx_small_cnt"); SYSCTL_ADD_INT(ctx, children, OID_AUTO, - "lro_flushed", CTLFLAG_RD, &ss->lro_flushed, + "lro_flushed", CTLFLAG_RD, &ss->lc.lro_flushed, 0, "number of lro merge queues flushed"); SYSCTL_ADD_INT(ctx, children, OID_AUTO, - "lro_queued", CTLFLAG_RD, &ss->lro_queued, + "lro_bad_csum", CTLFLAG_RD, &ss->lc.lro_bad_csum, + 0, "number of bad csums preventing LRO"); + + SYSCTL_ADD_INT(ctx, children, OID_AUTO, + "lro_queued", CTLFLAG_RD, &ss->lc.lro_queued, 0, "number of frames appended to lro merge" "queues"); @@ -1810,21 +1773,99 @@ mxge_submit_req(mxge_tx_ring_t *tx, mcp_kreq_ether_send_t *src, wmb(); } +static int +mxge_parse_tx(struct mxge_slice_state *ss, struct mbuf *m, + struct mxge_pkt_info *pi) +{ + struct ether_vlan_header *eh; + uint16_t etype; + int tso = m->m_pkthdr.csum_flags & (CSUM_TSO); +#if IFCAP_TSO6 && defined(INET6) + int nxt; +#endif + + eh = mtod(m, struct ether_vlan_header *); + if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { + etype = ntohs(eh->evl_proto); + pi->ip_off = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; + } else { + etype = ntohs(eh->evl_encap_proto); + pi->ip_off = ETHER_HDR_LEN; + } + + switch (etype) { + case ETHERTYPE_IP: + /* + * ensure ip header is in first mbuf, copy it to a + * scratch buffer if not + */ + pi->ip = (struct ip *)(m->m_data + pi->ip_off); + pi->ip6 = NULL; + if (__predict_false(m->m_len < pi->ip_off + sizeof(*pi->ip))) { + m_copydata(m, 0, pi->ip_off + sizeof(*pi->ip), + ss->scratch); + pi->ip = (struct ip *)(ss->scratch + pi->ip_off); + } + pi->ip_hlen = pi->ip->ip_hl << 2; + if (!tso) + return 0; + + if (__predict_false(m->m_len < pi->ip_off + pi->ip_hlen + + sizeof(struct tcphdr))) { + m_copydata(m, 0, pi->ip_off + pi->ip_hlen + + sizeof(struct tcphdr), ss->scratch); + pi->ip = (struct ip *)(ss->scratch + pi->ip_off); + } + pi->tcp = (struct tcphdr *)((char *)pi->ip + pi->ip_hlen); + break; +#if IFCAP_TSO6 && defined(INET6) + case ETHERTYPE_IPV6: + pi->ip6 = (struct ip6_hdr *)(m->m_data + pi->ip_off); + if (__predict_false(m->m_len < pi->ip_off + sizeof(*pi->ip6))) { + m_copydata(m, 0, pi->ip_off + sizeof(*pi->ip6), + ss->scratch); + pi->ip6 = (struct ip6_hdr *)(ss->scratch + pi->ip_off); + } + nxt = 0; + pi->ip_hlen = ip6_lasthdr(m, pi->ip_off, IPPROTO_IPV6, &nxt); + pi->ip_hlen -= pi->ip_off; + if (nxt != IPPROTO_TCP && nxt != IPPROTO_UDP) + return EINVAL; + + if (!tso) + return 0; + + if (pi->ip_off + pi->ip_hlen > ss->sc->max_tso6_hlen) + return EINVAL; + + if (__predict_false(m->m_len < pi->ip_off + pi->ip_hlen + + sizeof(struct tcphdr))) { + m_copydata(m, 0, pi->ip_off + pi->ip_hlen + + sizeof(struct tcphdr), ss->scratch); + pi->ip6 = (struct ip6_hdr *)(ss->scratch + pi->ip_off); + } + pi->tcp = (struct tcphdr *)((char *)pi->ip6 + pi->ip_hlen); + break; +#endif + default: + return EINVAL; + } + return 0; +} + #if IFCAP_TSO4 static void mxge_encap_tso(struct mxge_slice_state *ss, struct mbuf *m, - int busdma_seg_cnt, int ip_off) + int busdma_seg_cnt, struct mxge_pkt_info *pi) { mxge_tx_ring_t *tx; mcp_kreq_ether_send_t *req; bus_dma_segment_t *seg; - struct ip *ip; - struct tcphdr *tcp; uint32_t low, high_swapped; int len, seglen, cum_len, cum_len_next; int next_is_first, chop, cnt, rdma_count, small; - uint16_t pseudo_hdr_offset, cksum_offset, mss; + uint16_t pseudo_hdr_offset, cksum_offset, mss, sum; uint8_t flags, flags_next; static int once; @@ -1835,38 +1876,35 @@ mxge_encap_tso(struct mxge_slice_state *ss, struct mbuf *m, * header portion of the TSO packet. */ - /* ensure we have the ethernet, IP and TCP - header together in the first mbuf, copy - it to a scratch buffer if not */ - if (__predict_false(m->m_len < ip_off + sizeof (*ip))) { - m_copydata(m, 0, ip_off + sizeof (*ip), - ss->scratch); - ip = (struct ip *)(ss->scratch + ip_off); - } else { - ip = (struct ip *)(mtod(m, char *) + ip_off); - } - if (__predict_false(m->m_len < ip_off + (ip->ip_hl << 2) - + sizeof (*tcp))) { - m_copydata(m, 0, ip_off + (ip->ip_hl << 2) - + sizeof (*tcp), ss->scratch); - ip = (struct ip *)(mtod(m, char *) + ip_off); - } - - tcp = (struct tcphdr *)((char *)ip + (ip->ip_hl << 2)); - cum_len = -(ip_off + ((ip->ip_hl + tcp->th_off) << 2)); - cksum_offset = ip_off + (ip->ip_hl << 2); + cksum_offset = pi->ip_off + pi->ip_hlen; + cum_len = -(cksum_offset + (pi->tcp->th_off << 2)); /* TSO implies checksum offload on this hardware */ - if (__predict_false((m->m_pkthdr.csum_flags & (CSUM_TCP)) == 0)) { + if (__predict_false((m->m_pkthdr.csum_flags & (CSUM_TCP|CSUM_TCP_IPV6)) == 0)) { /* * If packet has full TCP csum, replace it with pseudo hdr * sum that the NIC expects, otherwise the NIC will emit * packets with bad TCP checksums. */ - m->m_pkthdr.csum_flags = CSUM_TCP; m->m_pkthdr.csum_data = offsetof(struct tcphdr, th_sum); - tcp->th_sum = in_pseudo(ip->ip_src.s_addr, ip->ip_dst.s_addr, - htons(IPPROTO_TCP + (m->m_pkthdr.len - cksum_offset))); + if (pi->ip6) { +#if (CSUM_TCP_IPV6 != 0) && defined(INET6) + m->m_pkthdr.csum_flags |= CSUM_TCP_IPV6; + sum = in6_cksum_pseudo(pi->ip6, + m->m_pkthdr.len - cksum_offset, + IPPROTO_TCP, 0); +#endif + } else { +#ifdef INET + m->m_pkthdr.csum_flags |= CSUM_TCP; + sum = in_pseudo(pi->ip->ip_src.s_addr, + pi->ip->ip_dst.s_addr, + htons(IPPROTO_TCP + (m->m_pkthdr.len - + cksum_offset))); +#endif + } + m_copyback(m, offsetof(struct tcphdr, th_sum) + + cksum_offset, sizeof(sum), (caddr_t)&sum); } flags = MXGEFW_FLAGS_TSO_HDR | MXGEFW_FLAGS_FIRST; @@ -1876,6 +1914,14 @@ mxge_encap_tso(struct mxge_slice_state *ss, struct mbuf *m, * the checksum by parsing the header. */ pseudo_hdr_offset = htobe16(mss); + if (pi->ip6) { + /* + * for IPv6 TSO, the "checksum offset" is re-purposed + * to store the TCP header len + */ + cksum_offset = (pi->tcp->th_off << 2); + } + tx = &ss->tx; req = tx->req_list; seg = tx->seg_list; @@ -1947,10 +1993,12 @@ mxge_encap_tso(struct mxge_slice_state *ss, struct mbuf *m, req++; cnt++; rdma_count++; - if (__predict_false(cksum_offset > seglen)) - cksum_offset -= seglen; - else - cksum_offset = 0; + if (cksum_offset != 0 && !pi->ip6) { + if (__predict_false(cksum_offset > seglen)) + cksum_offset -= seglen; + else + cksum_offset = 0; + } if (__predict_false(cnt > tx->max_desc)) goto drop; } @@ -2030,14 +2078,14 @@ mxge_vlan_tag_insert(struct mbuf *m) static void mxge_encap(struct mxge_slice_state *ss, struct mbuf *m) { + struct mxge_pkt_info pi = {0,0,0,0}; mxge_softc_t *sc; mcp_kreq_ether_send_t *req; bus_dma_segment_t *seg; struct mbuf *m_tmp; struct ifnet *ifp; mxge_tx_ring_t *tx; - struct ip *ip; - int cnt, cum_len, err, i, idx, odd_flag, ip_off; + int cnt, cum_len, err, i, idx, odd_flag; uint16_t pseudo_hdr_offset; uint8_t flags, cksum_offset; @@ -2046,15 +2094,19 @@ mxge_encap(struct mxge_slice_state *ss, struct mbuf *m) ifp = sc->ifp; tx = &ss->tx; - ip_off = sizeof (struct ether_header); #ifdef MXGE_NEW_VLAN_API if (m->m_flags & M_VLANTAG) { m = mxge_vlan_tag_insert(m); if (__predict_false(m == NULL)) - goto drop; - ip_off += ETHER_VLAN_ENCAP_LEN; + goto drop_without_m; } #endif + if (m->m_pkthdr.csum_flags & + (CSUM_TSO | CSUM_DELAY_DATA | CSUM_DELAY_DATA_IPV6)) { + if (mxge_parse_tx(ss, m, &pi)) + goto drop; + } + /* (try to) map the frame for DMA */ idx = tx->req & tx->mask; err = bus_dmamap_load_mbuf_sg(tx->dmat, tx->info[idx].map, @@ -2086,7 +2138,7 @@ mxge_encap(struct mxge_slice_state *ss, struct mbuf *m) #if IFCAP_TSO4 /* TSO is different enough, we handle it in another routine */ if (m->m_pkthdr.csum_flags & (CSUM_TSO)) { - mxge_encap_tso(ss, m, cnt, ip_off); + mxge_encap_tso(ss, m, cnt, &pi); return; } #endif @@ -2097,17 +2149,11 @@ mxge_encap(struct mxge_slice_state *ss, struct mbuf *m) flags = MXGEFW_FLAGS_NO_TSO; /* checksum offloading? */ - if (m->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { + if (m->m_pkthdr.csum_flags & + (CSUM_DELAY_DATA | CSUM_DELAY_DATA_IPV6)) { /* ensure ip header is in first mbuf, copy it to a scratch buffer if not */ - if (__predict_false(m->m_len < ip_off + sizeof (*ip))) { - m_copydata(m, 0, ip_off + sizeof (*ip), - ss->scratch); - ip = (struct ip *)(ss->scratch + ip_off); - } else { - ip = (struct ip *)(mtod(m, char *) + ip_off); - } - cksum_offset = ip_off + (ip->ip_hl << 2); + cksum_offset = pi.ip_off + pi.ip_hlen; pseudo_hdr_offset = cksum_offset + m->m_pkthdr.csum_data; pseudo_hdr_offset = htobe16(pseudo_hdr_offset); req->cksum_offset = cksum_offset; @@ -2190,6 +2236,7 @@ mxge_encap(struct mxge_slice_state *ss, struct mbuf *m) drop: m_freem(m); +drop_without_m: ss->oerrors++; return; } @@ -2449,6 +2496,62 @@ done: return err; } +#ifdef INET6 + +static uint16_t +mxge_csum_generic(uint16_t *raw, int len) +{ + uint32_t csum; + + + csum = 0; + while (len > 0) { + csum += *raw; + raw++; + len -= 2; + } + csum = (csum >> 16) + (csum & 0xffff); + csum = (csum >> 16) + (csum & 0xffff); + return (uint16_t)csum; +} + +static inline uint16_t +mxge_rx_csum6(void *p, struct mbuf *m, uint32_t csum) +{ + uint32_t partial; + int nxt, cksum_offset; + struct ip6_hdr *ip6 = p; + uint16_t c; + + nxt = ip6->ip6_nxt; + cksum_offset = sizeof (*ip6) + ETHER_HDR_LEN; + if (nxt != IPPROTO_TCP && nxt != IPPROTO_UDP) { + cksum_offset = ip6_lasthdr(m, ETHER_HDR_LEN, + IPPROTO_IPV6, &nxt); + if (nxt != IPPROTO_TCP && nxt != IPPROTO_UDP) + return (1); + } + + /* + * IPv6 headers do not contain a checksum, and hence + * do not checksum to zero, so they don't "fall out" + * of the partial checksum calculation like IPv4 + * headers do. We need to fix the partial checksum by + * subtracting the checksum of the IPv6 header. + */ + + partial = mxge_csum_generic((uint16_t *)ip6, cksum_offset - + ETHER_HDR_LEN); + csum += ~partial; + csum += (csum < ~partial); + csum = (csum >> 16) + (csum & 0xFFFF); + csum = (csum >> 16) + (csum & 0xFFFF); + c = in6_cksum_pseudo(ip6, m->m_pkthdr.len - cksum_offset, nxt, + csum); + c ^= 0xffff; + return (c); +} +#endif /* INET6 */ /* * Myri10GE hardware checksums are not valid if the sender * padded the frame with non-zero padding. This is because @@ -2462,26 +2565,41 @@ static inline uint16_t mxge_rx_csum(struct mbuf *m, int csum) { struct ether_header *eh; +#ifdef INET struct ip *ip; - uint16_t c; +#endif +#if defined(INET) || defined(INET6) + int cap = m->m_pkthdr.rcvif->if_capenable; +#endif + uint16_t c, etype; - eh = mtod(m, struct ether_header *); - /* only deal with IPv4 TCP & UDP for now */ - if (__predict_false(eh->ether_type != htons(ETHERTYPE_IP))) - return 1; - ip = (struct ip *)(eh + 1); - if (__predict_false(ip->ip_p != IPPROTO_TCP && - ip->ip_p != IPPROTO_UDP)) - return 1; + eh = mtod(m, struct ether_header *); + etype = ntohs(eh->ether_type); + switch (etype) { #ifdef INET - c = in_pseudo(ip->ip_src.s_addr, ip->ip_dst.s_addr, - htonl(ntohs(csum) + ntohs(ip->ip_len) + - - (ip->ip_hl << 2) + ip->ip_p)); -#else - c = 1; + case ETHERTYPE_IP: + if ((cap & IFCAP_RXCSUM) == 0) + return (1); + ip = (struct ip *)(eh + 1); + if (ip->ip_p != IPPROTO_TCP && ip->ip_p != IPPROTO_UDP) + return (1); + c = in_pseudo(ip->ip_src.s_addr, ip->ip_dst.s_addr, + htonl(ntohs(csum) + ntohs(ip->ip_len) - + (ip->ip_hl << 2) + ip->ip_p)); + c ^= 0xffff; + break; #endif - c ^= 0xffff; +#ifdef INET6 + case ETHERTYPE_IPV6: + if ((cap & IFCAP_RXCSUM_IPV6) == 0) + return (1); + c = mxge_rx_csum6((eh + 1), m, csum); + break; +#endif + default: + c = 1; + } return (c); } @@ -2543,7 +2661,8 @@ mxge_vlan_tag_remove(struct mbuf *m, uint32_t *csum) static inline void -mxge_rx_done_big(struct mxge_slice_state *ss, uint32_t len, uint32_t csum) +mxge_rx_done_big(struct mxge_slice_state *ss, uint32_t len, + uint32_t csum, int lro) { mxge_softc_t *sc; struct ifnet *ifp; @@ -2552,7 +2671,6 @@ mxge_rx_done_big(struct mxge_slice_state *ss, uint32_t len, uint32_t csum) mxge_rx_ring_t *rx; bus_dmamap_t old_map; int idx; - uint16_t tcpudp_csum; sc = ss->sc; ifp = sc->ifp; @@ -2589,14 +2707,18 @@ mxge_rx_done_big(struct mxge_slice_state *ss, uint32_t len, uint32_t csum) mxge_vlan_tag_remove(m, &csum); } /* if the checksum is valid, mark it in the mbuf header */ - if (sc->csum_flag && (0 == (tcpudp_csum = mxge_rx_csum(m, csum)))) { - if (sc->lro_cnt && (0 == mxge_lro_rx(ss, m, csum))) - return; - /* otherwise, it was a UDP frame, or a TCP frame which - we could not do LRO on. Tell the stack that the - checksum is good */ + + if ((ifp->if_capenable & (IFCAP_RXCSUM_IPV6 | IFCAP_RXCSUM)) && + (0 == mxge_rx_csum(m, csum))) { + /* Tell the stack that the checksum is good */ m->m_pkthdr.csum_data = 0xffff; - m->m_pkthdr.csum_flags = CSUM_PSEUDO_HDR | CSUM_DATA_VALID; + m->m_pkthdr.csum_flags = CSUM_PSEUDO_HDR | + CSUM_DATA_VALID; + +#if defined(INET) || defined (INET6) + if (lro && (0 == tcp_lro_rx(&ss->lc, m, 0))) + return; +#endif } /* flowid only valid if RSS hashing is enabled */ if (sc->num_slices > 1) { @@ -2608,7 +2730,8 @@ mxge_rx_done_big(struct mxge_slice_state *ss, uint32_t len, uint32_t csum) } static inline void -mxge_rx_done_small(struct mxge_slice_state *ss, uint32_t len, uint32_t csum) +mxge_rx_done_small(struct mxge_slice_state *ss, uint32_t len, + uint32_t csum, int lro) { mxge_softc_t *sc; struct ifnet *ifp; @@ -2617,7 +2740,6 @@ mxge_rx_done_small(struct mxge_slice_state *ss, uint32_t len, uint32_t csum) mxge_rx_ring_t *rx; bus_dmamap_t old_map; int idx; - uint16_t tcpudp_csum; sc = ss->sc; ifp = sc->ifp; @@ -2654,14 +2776,17 @@ mxge_rx_done_small(struct mxge_slice_state *ss, uint32_t len, uint32_t csum) mxge_vlan_tag_remove(m, &csum); } /* if the checksum is valid, mark it in the mbuf header */ - if (sc->csum_flag && (0 == (tcpudp_csum = mxge_rx_csum(m, csum)))) { - if (sc->lro_cnt && (0 == mxge_lro_rx(ss, m, csum))) - return; - /* otherwise, it was a UDP frame, or a TCP frame which - we could not do LRO on. Tell the stack that the - checksum is good */ + if ((ifp->if_capenable & (IFCAP_RXCSUM_IPV6 | IFCAP_RXCSUM)) && + (0 == mxge_rx_csum(m, csum))) { + /* Tell the stack that the checksum is good */ m->m_pkthdr.csum_data = 0xffff; - m->m_pkthdr.csum_flags = CSUM_PSEUDO_HDR | CSUM_DATA_VALID; + m->m_pkthdr.csum_flags = CSUM_PSEUDO_HDR | + CSUM_DATA_VALID; + +#if defined(INET) || defined (INET6) + if (lro && (0 == tcp_lro_rx(&ss->lc, m, csum))) + return; +#endif } /* flowid only valid if RSS hashing is enabled */ if (sc->num_slices > 1) { @@ -2679,16 +2804,17 @@ mxge_clean_rx_done(struct mxge_slice_state *ss) int limit = 0; uint16_t length; uint16_t checksum; + int lro; - + lro = ss->sc->ifp->if_capenable & IFCAP_LRO; while (rx_done->entry[rx_done->idx].length != 0) { length = ntohs(rx_done->entry[rx_done->idx].length); rx_done->entry[rx_done->idx].length = 0; checksum = rx_done->entry[rx_done->idx].checksum; if (length <= (MHLEN - MXGEFW_PAD)) - mxge_rx_done_small(ss, length, checksum); + mxge_rx_done_small(ss, length, checksum, lro); else - mxge_rx_done_big(ss, length, checksum); + mxge_rx_done_big(ss, length, checksum, lro); rx_done->cnt++; rx_done->idx = rx_done->cnt & rx_done->mask; @@ -2696,11 +2822,11 @@ mxge_clean_rx_done(struct mxge_slice_state *ss) if (__predict_false(++limit > rx_done->mask / 2)) break; } -#ifdef INET - while (!SLIST_EMPTY(&ss->lro_active)) { - struct lro_entry *lro = SLIST_FIRST(&ss->lro_active); - SLIST_REMOVE_HEAD(&ss->lro_active, next); - mxge_lro_flush(ss, lro); +#if defined(INET) || defined (INET6) + while (!SLIST_EMPTY(&ss->lc.lro_active)) { + struct lro_entry *lro = SLIST_FIRST(&ss->lc.lro_active); + SLIST_REMOVE_HEAD(&ss->lc.lro_active, next); + tcp_lro_flush(&ss->lc, lro); } #endif } @@ -3068,15 +3194,11 @@ mxge_init(void *arg) static void mxge_free_slice_mbufs(struct mxge_slice_state *ss) { - struct lro_entry *lro_entry; int i; - while (!SLIST_EMPTY(&ss->lro_free)) { - lro_entry = SLIST_FIRST(&ss->lro_free); - SLIST_REMOVE_HEAD(&ss->lro_free, next); - free(lro_entry, M_DEVBUF); - } - +#if defined(INET) || defined(INET6) + tcp_lro_free(&ss->lc); +#endif for (i = 0; i <= ss->rx_big.mask; i++) { if (ss->rx_big.info[i].m == NULL) continue; @@ -3460,26 +3582,17 @@ mxge_slice_open(struct mxge_slice_state *ss, int nbufs, int cl_size) mxge_softc_t *sc; mxge_cmd_t cmd; bus_dmamap_t map; - struct lro_entry *lro_entry; int err, i, slice; sc = ss->sc; slice = ss - sc->ss; - SLIST_INIT(&ss->lro_free); - SLIST_INIT(&ss->lro_active); - - for (i = 0; i < sc->lro_cnt; i++) { - lro_entry = (struct lro_entry *) - malloc(sizeof (*lro_entry), M_DEVBUF, - M_NOWAIT | M_ZERO); - if (lro_entry == NULL) { - sc->lro_cnt = i; - break; - } - SLIST_INSERT_HEAD(&ss->lro_free, lro_entry, next); - } +#if defined(INET) || defined(INET6) + (void)tcp_lro_init(&ss->lc); +#endif + ss->lc.ifp = sc->ifp; + /* get the lanai pointers to the send and receive rings */ err = 0; @@ -4126,8 +4239,7 @@ mxge_ioctl(struct ifnet *ifp, u_long command, caddr_t data) if (mask & IFCAP_TXCSUM) { if (IFCAP_TXCSUM & ifp->if_capenable) { ifp->if_capenable &= ~(IFCAP_TXCSUM|IFCAP_TSO4); - ifp->if_hwassist &= ~(CSUM_TCP | CSUM_UDP - | CSUM_TSO); + ifp->if_hwassist &= ~(CSUM_TCP | CSUM_UDP); } else { ifp->if_capenable |= IFCAP_TXCSUM; ifp->if_hwassist |= (CSUM_TCP | CSUM_UDP); @@ -4135,16 +4247,13 @@ mxge_ioctl(struct ifnet *ifp, u_long command, caddr_t data) } else if (mask & IFCAP_RXCSUM) { if (IFCAP_RXCSUM & ifp->if_capenable) { ifp->if_capenable &= ~IFCAP_RXCSUM; - sc->csum_flag = 0; } else { ifp->if_capenable |= IFCAP_RXCSUM; - sc->csum_flag = 1; } } if (mask & IFCAP_TSO4) { if (IFCAP_TSO4 & ifp->if_capenable) { ifp->if_capenable &= ~IFCAP_TSO4; - ifp->if_hwassist &= ~CSUM_TSO; } else if (IFCAP_TXCSUM & ifp->if_capenable) { ifp->if_capenable |= IFCAP_TSO4; ifp->if_hwassist |= CSUM_TSO; @@ -4154,12 +4263,41 @@ mxge_ioctl(struct ifnet *ifp, u_long command, caddr_t data) err = EINVAL; } } - if (mask & IFCAP_LRO) { - if (IFCAP_LRO & ifp->if_capenable) - err = mxge_change_lro_locked(sc, 0); - else - err = mxge_change_lro_locked(sc, mxge_lro_cnt); +#if IFCAP_TSO6 + if (mask & IFCAP_TXCSUM_IPV6) { + if (IFCAP_TXCSUM_IPV6 & ifp->if_capenable) { + ifp->if_capenable &= ~(IFCAP_TXCSUM_IPV6 + | IFCAP_TSO6); + ifp->if_hwassist &= ~(CSUM_TCP_IPV6 + | CSUM_UDP); + } else { + ifp->if_capenable |= IFCAP_TXCSUM_IPV6; + ifp->if_hwassist |= (CSUM_TCP_IPV6 + | CSUM_UDP_IPV6); + } + } else if (mask & IFCAP_RXCSUM_IPV6) { + if (IFCAP_RXCSUM_IPV6 & ifp->if_capenable) { + ifp->if_capenable &= ~IFCAP_RXCSUM_IPV6; + } else { + ifp->if_capenable |= IFCAP_RXCSUM_IPV6; + } + } + if (mask & IFCAP_TSO6) { + if (IFCAP_TSO6 & ifp->if_capenable) { + ifp->if_capenable &= ~IFCAP_TSO6; + } else if (IFCAP_TXCSUM_IPV6 & ifp->if_capenable) { + ifp->if_capenable |= IFCAP_TSO6; + ifp->if_hwassist |= CSUM_TSO; + } else { + printf("mxge requires tx checksum offload" + " be enabled to use TSO\n"); + err = EINVAL; + } } +#endif /*IFCAP_TSO6 */ + + if (mask & IFCAP_LRO) + ifp->if_capenable ^= IFCAP_LRO; if (mask & IFCAP_VLAN_HWTAGGING) ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; if (mask & IFCAP_VLAN_HWTSO) @@ -4206,14 +4344,11 @@ mxge_fetch_tunables(mxge_softc_t *sc) TUNABLE_INT_FETCH("hw.mxge.verbose", &mxge_verbose); TUNABLE_INT_FETCH("hw.mxge.ticks", &mxge_ticks); - TUNABLE_INT_FETCH("hw.mxge.lro_cnt", &sc->lro_cnt); TUNABLE_INT_FETCH("hw.mxge.always_promisc", &mxge_always_promisc); TUNABLE_INT_FETCH("hw.mxge.rss_hash_type", &mxge_rss_hash_type); TUNABLE_INT_FETCH("hw.mxge.rss_hashtype", &mxge_rss_hash_type); TUNABLE_INT_FETCH("hw.mxge.initial_mtu", &mxge_initial_mtu); TUNABLE_INT_FETCH("hw.mxge.throttle", &mxge_throttle); - if (sc->lro_cnt != 0) - mxge_lro_cnt = sc->lro_cnt; if (bootverbose) mxge_verbose = 1; @@ -4646,6 +4781,7 @@ mxge_add_irq(mxge_softc_t *sc) static int mxge_attach(device_t dev) { + mxge_cmd_t cmd; mxge_softc_t *sc = device_get_softc(dev); struct ifnet *ifp; int err, rid; @@ -4776,8 +4912,9 @@ mxge_attach(device_t dev) if_initbaudrate(ifp, IF_Gbps(10)); ifp->if_capabilities = IFCAP_RXCSUM | IFCAP_TXCSUM | IFCAP_TSO4 | - IFCAP_VLAN_MTU | IFCAP_LINKSTATE; -#ifdef INET + IFCAP_VLAN_MTU | IFCAP_LINKSTATE | IFCAP_TXCSUM_IPV6 | + IFCAP_RXCSUM_IPV6; +#if defined(INET) || defined(INET6) ifp->if_capabilities |= IFCAP_LRO; #endif @@ -4789,7 +4926,6 @@ mxge_attach(device_t dev) sc->fw_ver_tiny >= 32) ifp->if_capabilities |= IFCAP_VLAN_HWTSO; #endif - sc->max_mtu = mxge_max_mtu(sc); if (sc->max_mtu >= 9000) ifp->if_capabilities |= IFCAP_JUMBO_MTU; @@ -4798,10 +4934,17 @@ mxge_attach(device_t dev) "latest firmware for 9000 byte jumbo support\n", sc->max_mtu - ETHER_HDR_LEN); ifp->if_hwassist = CSUM_TCP | CSUM_UDP | CSUM_TSO; + ifp->if_hwassist |= CSUM_TCP_IPV6 | CSUM_UDP_IPV6; + /* check to see if f/w supports TSO for IPv6 */ + if (!mxge_send_cmd(sc, MXGEFW_CMD_GET_MAX_TSO6_HDR_SIZE, &cmd)) { + if (CSUM_TCP_IPV6) + ifp->if_capabilities |= IFCAP_TSO6; + sc->max_tso6_hlen = min(cmd.data0, + sizeof (sc->ss[0].scratch)); + } ifp->if_capenable = ifp->if_capabilities; if (sc->lro_cnt == 0) ifp->if_capenable &= ~IFCAP_LRO; - sc->csum_flag = 1; ifp->if_init = mxge_init; ifp->if_softc = sc; ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; diff --git a/sys/dev/mxge/if_mxge_var.h b/sys/dev/mxge/if_mxge_var.h index c85a29b..a182a20 100644 --- a/sys/dev/mxge/if_mxge_var.h +++ b/sys/dev/mxge/if_mxge_var.h @@ -1,6 +1,6 @@ /******************************************************************************* -Copyright (c) 2006-2009, Myricom Inc. +Copyright (c) 2006-2013, Myricom Inc. All rights reserved. Redistribution and use in source and binary forms, with or without @@ -50,6 +50,19 @@ $FreeBSD$ #define IFNET_BUF_RING 1 #endif +#if (__FreeBSD_version < 1000020) +#undef IF_Kbps +#undef IF_Mbps +#undef IF_Gbps +#define IF_Kbps(x) ((uintmax_t)(x) * 1000) /* kilobits/sec. */ +#define IF_Mbps(x) (IF_Kbps((x) * 1000)) /* megabits/sec. */ +#define IF_Gbps(x) (IF_Mbps((x) * 1000)) /* gigabits/sec. */ +static __inline void +if_initbaudrate(struct ifnet *ifp, uintmax_t baud) +{ + ifp->if_baudrate = baud; +} +#endif #ifndef VLAN_CAPABILITIES #define VLAN_CAPABILITIES(ifp) #define mxge_vlans_active(sc) (sc)->ifp->if_nvlans @@ -73,10 +86,33 @@ $FreeBSD$ #define IFCAP_TSO4 0 #endif +#ifndef IFCAP_TSO6 +#define IFCAP_TSO6 0 +#endif + +#ifndef IFCAP_TXCSUM_IPV6 +#define IFCAP_TXCSUM_IPV6 0 +#endif + +#ifndef IFCAP_RXCSUM_IPV6 +#define IFCAP_RXCSUM_IPV6 0 +#endif + #ifndef CSUM_TSO #define CSUM_TSO 0 #endif +#ifndef CSUM_TCP_IPV6 +#define CSUM_TCP_IPV6 0 +#endif + +#ifndef CSUM_UDP_IPV6 +#define CSUM_UDP_IPV6 0 +#endif + +#ifndef CSUM_DELAY_DATA_IPV6 +#define CSUM_DELAY_DATA_IPV6 0 +#endif typedef struct { void *addr; @@ -158,31 +194,6 @@ typedef struct char mtx_name[16]; } mxge_tx_ring_t; -struct lro_entry; -struct lro_entry -{ - SLIST_ENTRY(lro_entry) next; - struct mbuf *m_head; - struct mbuf *m_tail; - int timestamp; - struct ip *ip; - uint32_t tsval; - uint32_t tsecr; - uint32_t source_ip; - uint32_t dest_ip; - uint32_t next_seq; - uint32_t ack_seq; - uint32_t len; - uint32_t data_csum; - uint16_t window; - uint16_t source_port; - uint16_t dest_port; - uint16_t append_cnt; - uint16_t mss; - -}; -SLIST_HEAD(lro_head, lro_entry); - struct mxge_softc; typedef struct mxge_softc mxge_softc_t; @@ -200,11 +211,7 @@ struct mxge_slice_state { u_long omcasts; u_long oerrors; int if_drv_flags; - struct lro_head lro_active; - struct lro_head lro_free; - int lro_queued; - int lro_flushed; - int lro_bad_csum; + struct lro_ctrl lc; mxge_dma_t fw_stats_dma; struct sysctl_oid *sysctl_tree; struct sysctl_ctx_list sysctl_ctx; @@ -214,7 +221,6 @@ struct mxge_slice_state { struct mxge_softc { struct ifnet* ifp; struct mxge_slice_state *ss; - int csum_flag; /* rx_csums? */ int tx_boundary; /* boundary transmits cannot cross*/ int lro_cnt; bus_dma_tag_t parent_dmat; @@ -270,6 +276,7 @@ struct mxge_softc { int dying; int connector; int current_media; + int max_tso6_hlen; mxge_dma_t dmabench_dma; struct callout co_hdl; struct taskqueue *tq; @@ -312,6 +319,15 @@ struct mxge_media_type char *name; }; +struct mxge_pkt_info { + int ip_off; + int ip_hlen; + struct ip *ip; + struct ip6_hdr *ip6; + struct tcphdr *tcp; +}; + + /* implement our own memory barriers, since bus_space_barrier cannot handle write-combining regions */ diff --git a/sys/dev/mxge/mxge_lro.c b/sys/dev/mxge/mxge_lro.c deleted file mode 100644 index b313059..0000000 --- a/sys/dev/mxge/mxge_lro.c +++ /dev/null @@ -1,357 +0,0 @@ -/****************************************************************************** - -Copyright (c) 2007-2008, Myricom Inc. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions and the following disclaimer. - - 2. Neither the name of the Myricom Inc, nor the names of its - contributors may be used to endorse or promote products derived from - this software without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -POSSIBILITY OF SUCH DAMAGE. - -***************************************************************************/ - -#include <sys/cdefs.h> -__FBSDID("$FreeBSD$"); - -#include <sys/param.h> -#include <sys/systm.h> -#include <sys/endian.h> -#include <sys/mbuf.h> -#include <sys/kernel.h> -#include <sys/socket.h> -#include <sys/sysctl.h> -#include <sys/bus.h> - -#include <net/if.h> -#include <net/ethernet.h> -#include <net/if_media.h> - -#include <netinet/in_systm.h> -#include <netinet/in.h> -#include <netinet/ip.h> -#include <netinet/tcp.h> - -#include <machine/bus.h> -#include <machine/in_cksum.h> - -#include <dev/mxge/mxge_mcp.h> -#include <dev/mxge/if_mxge_var.h> - -#include "opt_inet.h" - -#ifdef INET - -/* Assume len is a multiple of 4 */ -static uint16_t -mxge_csum_generic(uint16_t *raw, int len) -{ - uint32_t csum; - csum = 0; - while (len > 0) { - csum += *raw; - raw++; - csum += *raw; - raw++; - len -= 4; - } - csum = (csum >> 16) + (csum & 0xffff); - csum = (csum >> 16) + (csum & 0xffff); - return (uint16_t)csum; -} - - -void -mxge_lro_flush(struct mxge_slice_state *ss, struct lro_entry *lro) -{ - mxge_softc_t *mgp = ss->sc; - struct ifnet *ifp; - struct ip *ip; - struct tcphdr *tcp; - uint32_t *ts_ptr; - uint32_t tcplen, tcp_csum; - - if (lro->append_cnt) { - /* incorporate the new len into the ip header and - * re-calculate the checksum */ - ip = lro->ip; - ip->ip_len = htons(lro->len - ETHER_HDR_LEN); - ip->ip_sum = 0; - ip->ip_sum = 0xffff ^ - mxge_csum_generic((uint16_t*)ip, - sizeof (*ip)); - - lro->m_head->m_pkthdr.csum_flags = CSUM_IP_CHECKED | - CSUM_IP_VALID | CSUM_DATA_VALID | CSUM_PSEUDO_HDR; - lro->m_head->m_pkthdr.csum_data = 0xffff; - lro->m_head->m_pkthdr.len = lro->len; - - /* incorporate the latest ack into the tcp header */ - tcp = (struct tcphdr *) (ip + 1); - tcp->th_ack = lro->ack_seq; - tcp->th_win = lro->window; - /* incorporate latest timestamp into the tcp header */ - if (lro->timestamp) { - ts_ptr = (uint32_t *)(tcp + 1); - ts_ptr[1] = htonl(lro->tsval); - ts_ptr[2] = lro->tsecr; - } - /* - * update checksum in tcp header by re-calculating the - * tcp pseudoheader checksum, and adding it to the checksum - * of the tcp payload data - */ - tcp->th_sum = 0; - tcplen = lro->len - sizeof(*ip) - ETHER_HDR_LEN; - tcp_csum = lro->data_csum; - tcp_csum += in_pseudo(ip->ip_src.s_addr, ip->ip_dst.s_addr, - htons(tcplen + IPPROTO_TCP)); - tcp_csum += mxge_csum_generic((uint16_t*)tcp, - tcp->th_off << 2); - tcp_csum = (tcp_csum & 0xffff) + (tcp_csum >> 16); - tcp_csum = (tcp_csum & 0xffff) + (tcp_csum >> 16); -#if 0 - IOLog("pseudo = 0x%x, generic = 0x%x, sum = %x\n", - in_pseudo(ip->ip_src.s_addr, ip->ip_dst.s_addr, - htons(tcplen + IPPROTO_TCP)), - mxge_csum_generic((uint16_t*)tcp, - tcp->th_off << 2), - htons(0xffff ^ tcp_csum)); -#endif - tcp->th_sum = 0xffff ^ tcp_csum; - } - ifp = mgp->ifp; - (*ifp->if_input)(mgp->ifp, lro->m_head); - ss->lro_queued += lro->append_cnt + 1; - ss->lro_flushed++; - lro->m_head = NULL; - lro->timestamp = 0; - lro->append_cnt = 0; - SLIST_INSERT_HEAD(&ss->lro_free, lro, next); -} - -int -mxge_lro_rx(struct mxge_slice_state *ss, struct mbuf *m_head, uint32_t csum) -{ - struct ether_header *eh; - struct ip *ip; - struct tcphdr *tcp; - uint32_t *ts_ptr; - struct mbuf *m_nxt, *m_tail; - struct lro_entry *lro; - int hlen, ip_len, tcp_hdr_len, tcp_data_len, tot_len; - int opt_bytes, trim; - uint32_t seq, tmp_csum, device_mtu; - - eh = mtod(m_head, struct ether_header *); - if (eh->ether_type != htons(ETHERTYPE_IP)) - return 1; - ip = (struct ip *) (eh + 1); - if (ip->ip_p != IPPROTO_TCP) - return 1; - - /* ensure there are no options */ - if ((ip->ip_hl << 2) != sizeof (*ip)) - return -1; - - /* .. and the packet is not fragmented */ - if (ip->ip_off & htons(IP_MF|IP_OFFMASK)) - return -1; - - /* verify that the IP header checksum is correct */ - tmp_csum = mxge_csum_generic((uint16_t *)ip, sizeof (*ip)); - if (__predict_false((tmp_csum ^ 0xffff) != 0)) { - ss->lro_bad_csum++; - return -1; - } - - /* find the TCP header */ - tcp = (struct tcphdr *) (ip + 1); - - /* ensure no bits set besides ack or psh */ - if ((tcp->th_flags & ~(TH_ACK | TH_PUSH)) != 0) - return -1; - - /* check for timestamps. Since the only option we handle are - timestamps, we only have to handle the simple case of - aligned timestamps */ - - opt_bytes = (tcp->th_off << 2) - sizeof (*tcp); - tcp_hdr_len = sizeof (*tcp) + opt_bytes; - ts_ptr = (uint32_t *)(tcp + 1); - if (opt_bytes != 0) { - if (__predict_false(opt_bytes != TCPOLEN_TSTAMP_APPA) || - (*ts_ptr != ntohl(TCPOPT_NOP<<24|TCPOPT_NOP<<16|TCPOPT_TIMESTAMP<<8|TCPOLEN_TIMESTAMP))) - return -1; - } - - ip_len = ntohs(ip->ip_len); - tcp_data_len = ip_len - (tcp->th_off << 2) - sizeof (*ip); - - - /* - * If frame is padded beyond the end of the IP packet, - * then we must trim the extra bytes off the end. - */ - tot_len = m_head->m_pkthdr.len; - trim = tot_len - (ip_len + ETHER_HDR_LEN); - if (trim != 0) { - if (trim < 0) { - /* truncated packet */ - return -1; - } - m_adj(m_head, -trim); - tot_len = m_head->m_pkthdr.len; - } - - m_nxt = m_head; - m_tail = NULL; /* -Wuninitialized */ - while (m_nxt != NULL) { - m_tail = m_nxt; - m_nxt = m_tail->m_next; - } - - hlen = ip_len + ETHER_HDR_LEN - tcp_data_len; - seq = ntohl(tcp->th_seq); - - SLIST_FOREACH(lro, &ss->lro_active, next) { - if (lro->source_port == tcp->th_sport && - lro->dest_port == tcp->th_dport && - lro->source_ip == ip->ip_src.s_addr && - lro->dest_ip == ip->ip_dst.s_addr) { - /* Try to append it */ - - if (__predict_false(seq != lro->next_seq || - (tcp_data_len == 0 && - lro->ack_seq == tcp->th_ack))) { - /* out of order packet or dup ack */ - SLIST_REMOVE(&ss->lro_active, lro, - lro_entry, next); - mxge_lro_flush(ss, lro); - return -1; - } - - if (opt_bytes) { - uint32_t tsval = ntohl(*(ts_ptr + 1)); - /* make sure timestamp values are increasing */ - if (__predict_false(lro->tsval > tsval || - *(ts_ptr + 2) == 0)) { - return -1; - } - lro->tsval = tsval; - lro->tsecr = *(ts_ptr + 2); - } - - lro->next_seq += tcp_data_len; - lro->ack_seq = tcp->th_ack; - lro->window = tcp->th_win; - lro->append_cnt++; - if (tcp_data_len == 0) { - m_freem(m_head); - return 0; - } - /* subtract off the checksum of the tcp header - * from the hardware checksum, and add it to the - * stored tcp data checksum. Byteswap the checksum - * if the total length so far is odd - */ - tmp_csum = mxge_csum_generic((uint16_t*)tcp, - tcp_hdr_len); - csum = csum + (tmp_csum ^ 0xffff); - csum = (csum & 0xffff) + (csum >> 16); - csum = (csum & 0xffff) + (csum >> 16); - if (lro->len & 0x1) { - /* Odd number of bytes so far, flip bytes */ - csum = ((csum << 8) | (csum >> 8)) & 0xffff; - } - csum = csum + lro->data_csum; - csum = (csum & 0xffff) + (csum >> 16); - csum = (csum & 0xffff) + (csum >> 16); - lro->data_csum = csum; - - lro->len += tcp_data_len; - - /* adjust mbuf so that m->m_data points to - the first byte of the payload */ - m_adj(m_head, hlen); - /* append mbuf chain */ - lro->m_tail->m_next = m_head; - /* advance the last pointer */ - lro->m_tail = m_tail; - /* flush packet if required */ - device_mtu = ss->sc->ifp->if_mtu; - if (lro->len > (65535 - device_mtu)) { - SLIST_REMOVE(&ss->lro_active, lro, - lro_entry, next); - mxge_lro_flush(ss, lro); - } - return 0; - } - } - - if (SLIST_EMPTY(&ss->lro_free)) - return -1; - - /* start a new chain */ - lro = SLIST_FIRST(&ss->lro_free); - SLIST_REMOVE_HEAD(&ss->lro_free, next); - SLIST_INSERT_HEAD(&ss->lro_active, lro, next); - lro->source_port = tcp->th_sport; - lro->dest_port = tcp->th_dport; - lro->source_ip = ip->ip_src.s_addr; - lro->dest_ip = ip->ip_dst.s_addr; - lro->next_seq = seq + tcp_data_len; - lro->mss = tcp_data_len; - lro->ack_seq = tcp->th_ack; - lro->window = tcp->th_win; - - /* save the checksum of just the TCP payload by - * subtracting off the checksum of the TCP header from - * the entire hardware checksum - * Since IP header checksum is correct, checksum over - * the IP header is -0. Substracting -0 is unnecessary. - */ - tmp_csum = mxge_csum_generic((uint16_t*)tcp, tcp_hdr_len); - csum = csum + (tmp_csum ^ 0xffff); - csum = (csum & 0xffff) + (csum >> 16); - csum = (csum & 0xffff) + (csum >> 16); - lro->data_csum = csum; - - lro->ip = ip; - /* record timestamp if it is present */ - if (opt_bytes) { - lro->timestamp = 1; - lro->tsval = ntohl(*(ts_ptr + 1)); - lro->tsecr = *(ts_ptr + 2); - } - lro->len = tot_len; - lro->m_head = m_head; - lro->m_tail = m_tail; - return 0; -} - -#endif /* INET */ -/* - This file uses Myri10GE driver indentation. - - Local Variables: - c-file-style:"linux" - tab-width:8 - End: -*/ diff --git a/sys/dev/ppc/ppc.c b/sys/dev/ppc/ppc.c index 5da180c..e1edc4d 100644 --- a/sys/dev/ppc/ppc.c +++ b/sys/dev/ppc/ppc.c @@ -74,6 +74,22 @@ static void ppcintr(void *arg); #define DEVTOSOFTC(dev) ((struct ppc_data *)device_get_softc(dev)) +/* + * We use critical enter/exit for the simple config locking needed to + * detect the devices. We just want to make sure that both of our writes + * happen without someone else also writing to those config registers. Since + * we just do this at startup, Giant keeps multiple threads from executing, + * and critical_enter() then is all that's needed to keep us from being preempted + * during the critical sequences with the hardware. + * + * Note: this doesn't prevent multiple threads from putting the chips into + * config mode, but since we only do that to detect the type at startup the + * extra overhead isn't needed since Giant protects us from multiple entry + * and no other code changes these registers. + */ +#define PPC_CONFIG_LOCK(ppc) critical_enter() +#define PPC_CONFIG_UNLOCK(ppc) critical_exit() + devclass_t ppc_devclass; const char ppc_driver_name[] = "ppc"; @@ -689,7 +705,7 @@ ppc_pc873xx_detect(struct ppc_data *ppc, int chipset_mode) /* XXX mode never for static int ppc_smc37c66xgt_detect(struct ppc_data *ppc, int chipset_mode) { - int s, i; + int i; u_char r; int type = -1; int csr = SMC66x_CSR; /* initial value is 0x3F0 */ @@ -702,11 +718,10 @@ ppc_smc37c66xgt_detect(struct ppc_data *ppc, int chipset_mode) /* * Detection: enter configuration mode and read CRD register. */ - - s = splhigh(); + PPC_CONFIG_LOCK(ppc); outb(csr, SMC665_iCODE); outb(csr, SMC665_iCODE); - splx(s); + PPC_CONFIG_UNLOCK(ppc); outb(csr, 0xd); if (inb(cio) == 0x65) { @@ -715,10 +730,10 @@ ppc_smc37c66xgt_detect(struct ppc_data *ppc, int chipset_mode) } for (i = 0; i < 2; i++) { - s = splhigh(); + PPC_CONFIG_LOCK(ppc); outb(csr, SMC666_iCODE); outb(csr, SMC666_iCODE); - splx(s); + PPC_CONFIG_UNLOCK(ppc); outb(csr, 0xd); if (inb(cio) == 0x66) { @@ -734,16 +749,20 @@ config: /* * If chipset not found, do not continue. */ - if (type == -1) + if (type == -1) { + outb(csr, 0xaa); /* end config mode */ return (-1); + } /* select CR1 */ outb(csr, 0x1); /* read the port's address: bits 0 and 1 of CR1 */ r = inb(cio) & SMC_CR1_ADDR; - if (port_address[(int)r] != ppc->ppc_base) + if (port_address[(int)r] != ppc->ppc_base) { + outb(csr, 0xaa); /* end config mode */ return (-1); + } ppc->ppc_model = type; @@ -881,8 +900,7 @@ end_detect: outb(cio, (r | SMC_CR4_EPPTYPE)); } - /* end config mode */ - outb(csr, 0xaa); + outb(csr, 0xaa); /* end config mode */ ppc->ppc_type = PPC_TYPE_SMCLIKE; ppc_smclike_setmode(ppc, chipset_mode); @@ -897,13 +915,12 @@ end_detect: static int ppc_smc37c935_detect(struct ppc_data *ppc, int chipset_mode) { - int s; int type = -1; - s = splhigh(); + PPC_CONFIG_LOCK(ppc); outb(SMC935_CFG, 0x55); /* enter config mode */ outb(SMC935_CFG, 0x55); - splx(s); + PPC_CONFIG_UNLOCK(ppc); outb(SMC935_IND, SMC935_ID); /* check device id */ if (inb(SMC935_DAT) == 0x2) diff --git a/sys/dev/ppc/ppc_isa.c b/sys/dev/ppc/ppc_isa.c index 14424a3..a40fc8e 100644 --- a/sys/dev/ppc/ppc_isa.c +++ b/sys/dev/ppc/ppc_isa.c @@ -141,7 +141,7 @@ ppc_isa_write(device_t dev, char *buf, int len, int how) { struct ppc_data *ppc = device_get_softc(dev); char ecr, ecr_sav, ctr, ctr_sav; - int s, error = 0; + int error = 0; int spin; PPC_ASSERT_LOCKED(ppc); @@ -190,12 +190,6 @@ ppc_isa_write(device_t dev, char *buf, int len, int how) w_ecr(ppc, ecr); ecr = r_ecr(ppc); - /* enter splhigh() not to be preempted - * by the dma interrupt, we may miss - * the wakeup otherwise - */ - s = splhigh(); - ppc->ppc_dmastat = PPC_DMA_INIT; /* enable interrupts */ @@ -221,8 +215,6 @@ ppc_isa_write(device_t dev, char *buf, int len, int how) "ppcdma", 0); } while (error == EWOULDBLOCK); - splx(s); - if (error) { #ifdef PPC_DEBUG printf("i"); diff --git a/sys/dev/sdhci/sdhci.c b/sys/dev/sdhci/sdhci.c index 0ef0617..1044bb6 100644 --- a/sys/dev/sdhci/sdhci.c +++ b/sys/dev/sdhci/sdhci.c @@ -98,6 +98,9 @@ static void sdhci_card_task(void *, int); #define SDHCI_DEFAULT_MAX_FREQ 50 +#define SDHCI_200_MAX_DIVIDER 256 +#define SDHCI_300_MAX_DIVIDER 2046 + static void sdhci_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) { @@ -238,7 +241,7 @@ sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock) if (slot->version < SDHCI_SPEC_300) { /* Looking for highest freq <= clock. */ res = slot->max_clk; - for (div = 1; div < 256; div <<= 1) { + for (div = 1; div < SDHCI_200_MAX_DIVIDER; div <<= 1) { if (res <= clock) break; res >>= 1; @@ -248,10 +251,10 @@ sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock) } else { /* Version 3.0 divisors are multiples of two up to 1023*2 */ - if (clock > slot->max_clk) - div = 2; + if (clock >= slot->max_clk) + div = 0; else { - for (div = 2; div < 1023*2; div += 2) { + for (div = 2; div < SDHCI_300_MAX_DIVIDER; div += 2) { if ((slot->max_clk / div) <= clock) break; } @@ -545,7 +548,7 @@ sdhci_init_slot(device_t dev, struct sdhci_slot *slot, int num) "frequency.\n"); } - slot->host.f_min = slot->max_clk / 256; + slot->host.f_min = SDHCI_MIN_FREQ(slot->bus, slot); slot->host.f_max = slot->max_clk; slot->host.host_ocr = 0; if (caps & SDHCI_CAN_VDD_330) @@ -635,6 +638,15 @@ sdhci_generic_resume(struct sdhci_slot *slot) return (0); } +uint32_t +sdhci_generic_min_freq(device_t brdev, struct sdhci_slot *slot) +{ + if (slot->version >= SDHCI_SPEC_300) + return (slot->max_clk / SDHCI_300_MAX_DIVIDER); + else + return (slot->max_clk / SDHCI_200_MAX_DIVIDER); +} + int sdhci_generic_update_ios(device_t brdev, device_t reqdev) { @@ -1299,14 +1311,30 @@ sdhci_generic_write_ivar(device_t bus, device_t child, int which, uintptr_t valu break; case MMCBR_IVAR_CLOCK: if (value > 0) { - uint32_t clock = slot->max_clk; + uint32_t max_clock; + uint32_t clock; int i; - for (i = 0; i < 8; i++) { - if (clock <= value) - break; - clock >>= 1; + max_clock = slot->max_clk; + clock = max_clock; + + if (slot->version < SDHCI_SPEC_300) { + for (i = 0; i < SDHCI_200_MAX_DIVIDER; + i <<= 1) { + if (clock <= value) + break; + clock >>= 1; + } } + else { + for (i = 0; i < SDHCI_300_MAX_DIVIDER; + i += 2) { + if (clock <= value) + break; + clock = max_clock / (i + 2); + } + } + slot->host.ios.clock = clock; } else slot->host.ios.clock = 0; diff --git a/sys/dev/sdhci/sdhci.h b/sys/dev/sdhci/sdhci.h index 400f98e..31fbe68 100644 --- a/sys/dev/sdhci/sdhci.h +++ b/sys/dev/sdhci/sdhci.h @@ -266,5 +266,6 @@ int sdhci_generic_get_ro(device_t brdev, device_t reqdev); int sdhci_generic_acquire_host(device_t brdev, device_t reqdev); int sdhci_generic_release_host(device_t brdev, device_t reqdev); void sdhci_generic_intr(struct sdhci_slot *slot); +uint32_t sdhci_generic_min_freq(device_t brdev, struct sdhci_slot *slot); #endif /* __SDHCI_H__ */ diff --git a/sys/dev/sdhci/sdhci_if.m b/sys/dev/sdhci/sdhci_if.m index cc8a7d3..b434fd2 100644 --- a/sys/dev/sdhci/sdhci_if.m +++ b/sys/dev/sdhci/sdhci_if.m @@ -58,7 +58,18 @@ # that mmc/sd card drivers call to make requests. # +#include <sys/types.h> +#include <sys/systm.h> +#include <sys/lock.h> +#include <sys/mutex.h> +#include <sys/taskqueue.h> + #include <machine/bus.h> + +#include <dev/mmc/bridge.h> +#include <dev/mmc/mmcreg.h> +#include <dev/sdhci/sdhci.h> + CODE { struct sdhci_slot; } @@ -119,3 +130,8 @@ METHOD void write_multi_4 { uint32_t *data; bus_size_t count; } + +METHOD uint32_t min_freq { + device_t brdev; + struct sdhci_slot *slot; +} DEFAULT sdhci_generic_min_freq; diff --git a/sys/dev/si/si.c b/sys/dev/si/si.c index 416771c..c9d1c83 100644 --- a/sys/dev/si/si.c +++ b/sys/dev/si/si.c @@ -1446,7 +1446,6 @@ si_start(struct tty *tp) #if 0 /* - * Note: called at splsoftclock from the timeout code * This has to deal with two things... cause wakeups while waiting for * tty drains on last process exit, and call l_start at about the right * time for protocols like ppp. diff --git a/sys/dev/sound/pci/hda/hdaa.c b/sys/dev/sound/pci/hda/hdaa.c index 69fab04..ac10d0a 100644 --- a/sys/dev/sound/pci/hda/hdaa.c +++ b/sys/dev/sound/pci/hda/hdaa.c @@ -557,7 +557,7 @@ hdaa_presence_handler(struct hdaa_widget *w) HDA_BOOTVERBOSE( if (connected || old != 2) { device_printf(devinfo->dev, - "Pin sense: nid=%d sence=0x%08x (%sconnected)\n", + "Pin sense: nid=%d sense=0x%08x (%sconnected)\n", w->nid, res, !connected ? "dis" : ""); } ); @@ -706,7 +706,7 @@ hdaa_eld_handler(struct hdaa_widget *w) } HDA_BOOTVERBOSE( device_printf(devinfo->dev, - "Pin sense: nid=%d sence=0x%08x " + "Pin sense: nid=%d sense=0x%08x " "(%sconnected, ELD %svalid)\n", w->nid, res, (res & HDA_CMD_GET_PIN_SENSE_PRESENCE_DETECT) ? "" : "dis", diff --git a/sys/dev/usb/wlan/if_upgt.c b/sys/dev/usb/wlan/if_upgt.c index 0467100..eff7922 100644 --- a/sys/dev/usb/wlan/if_upgt.c +++ b/sys/dev/usb/wlan/if_upgt.c @@ -1132,12 +1132,23 @@ upgt_eeprom_parse(struct upgt_softc *sc) (sizeof(struct upgt_eeprom_header) + preamble_len)); while (!option_end) { + + /* sanity check */ + if (eeprom_option >= (struct upgt_eeprom_option *) + (sc->sc_eeprom + UPGT_EEPROM_SIZE)) { + return (EINVAL); + } + /* the eeprom option length is stored in words */ option_len = (le16toh(eeprom_option->len) - 1) * sizeof(uint16_t); option_type = le16toh(eeprom_option->type); + /* sanity check */ + if (option_len == 0 || option_len >= UPGT_EEPROM_SIZE) + return (EINVAL); + switch (option_type) { case UPGT_EEPROM_TYPE_NAME: DPRINTF(sc, UPGT_DEBUG_FW, @@ -1208,7 +1219,6 @@ upgt_eeprom_parse(struct upgt_softc *sc) eeprom_option = (struct upgt_eeprom_option *) (eeprom_option->data + option_len); } - return (0); } @@ -1217,7 +1227,9 @@ upgt_eeprom_parse_freq3(struct upgt_softc *sc, uint8_t *data, int len) { struct upgt_eeprom_freq3_header *freq3_header; struct upgt_lmac_freq3 *freq3; - int i, elements, flags; + int i; + int elements; + int flags; unsigned channel; freq3_header = (struct upgt_eeprom_freq3_header *)data; @@ -1229,6 +1241,9 @@ upgt_eeprom_parse_freq3(struct upgt_softc *sc, uint8_t *data, int len) DPRINTF(sc, UPGT_DEBUG_FW, "flags=0x%02x elements=%d\n", flags, elements); + if (elements >= (int)(UPGT_EEPROM_SIZE / sizeof(freq3[0]))) + return; + for (i = 0; i < elements; i++) { channel = ieee80211_mhz2ieee(le16toh(freq3[i].freq), 0); if (channel >= IEEE80211_CHAN_MAX) @@ -1247,7 +1262,11 @@ upgt_eeprom_parse_freq4(struct upgt_softc *sc, uint8_t *data, int len) struct upgt_eeprom_freq4_header *freq4_header; struct upgt_eeprom_freq4_1 *freq4_1; struct upgt_eeprom_freq4_2 *freq4_2; - int i, j, elements, settings, flags; + int i; + int j; + int elements; + int settings; + int flags; unsigned channel; freq4_header = (struct upgt_eeprom_freq4_header *)data; @@ -1262,6 +1281,9 @@ upgt_eeprom_parse_freq4(struct upgt_softc *sc, uint8_t *data, int len) DPRINTF(sc, UPGT_DEBUG_FW, "flags=0x%02x elements=%d settings=%d\n", flags, elements, settings); + if (elements >= (int)(UPGT_EEPROM_SIZE / sizeof(freq4_1[0]))) + return; + for (i = 0; i < elements; i++) { channel = ieee80211_mhz2ieee(le16toh(freq4_1[i].freq), 0); if (channel >= IEEE80211_CHAN_MAX) @@ -1282,7 +1304,8 @@ void upgt_eeprom_parse_freq6(struct upgt_softc *sc, uint8_t *data, int len) { struct upgt_lmac_freq6 *freq6; - int i, elements; + int i; + int elements; unsigned channel; freq6 = (struct upgt_lmac_freq6 *)data; @@ -1290,6 +1313,9 @@ upgt_eeprom_parse_freq6(struct upgt_softc *sc, uint8_t *data, int len) DPRINTF(sc, UPGT_DEBUG_FW, "elements=%d\n", elements); + if (elements >= (int)(UPGT_EEPROM_SIZE / sizeof(freq6[0]))) + return; + for (i = 0; i < elements; i++) { channel = ieee80211_mhz2ieee(le16toh(freq6[i].freq), 0); if (channel >= IEEE80211_CHAN_MAX) diff --git a/sys/dev/usb/wlan/if_upgtvar.h b/sys/dev/usb/wlan/if_upgtvar.h index 6ef699f..070f9f6 100644 --- a/sys/dev/usb/wlan/if_upgtvar.h +++ b/sys/dev/usb/wlan/if_upgtvar.h @@ -453,7 +453,7 @@ struct upgt_softc { struct upgt_memory sc_memory; /* data which we found in the EEPROM */ - uint8_t sc_eeprom[UPGT_EEPROM_SIZE]; + uint8_t sc_eeprom[2 * UPGT_EEPROM_SIZE] __aligned(4); uint16_t sc_eeprom_hwrx; struct upgt_lmac_freq3 sc_eeprom_freq3[IEEE80211_CHAN_MAX]; struct upgt_lmac_freq4 sc_eeprom_freq4[IEEE80211_CHAN_MAX][8]; diff --git a/sys/fs/msdosfs/msdosfs_fat.c b/sys/fs/msdosfs/msdosfs_fat.c index 3994042..c660601 100644 --- a/sys/fs/msdosfs/msdosfs_fat.c +++ b/sys/fs/msdosfs/msdosfs_fat.c @@ -328,29 +328,6 @@ updatefats(pmp, bp, fatbn) printf("updatefats(pmp %p, bp %p, fatbn %lu)\n", pmp, bp, fatbn); #endif - /* - * If we have an FSInfo block, update it. - */ - if (pmp->pm_fsinfo) { - if (bread(pmp->pm_devvp, pmp->pm_fsinfo, pmp->pm_BytesPerSec, - NOCRED, &bpn) != 0) { - /* - * Ignore the error, but turn off FSInfo update for the future. - */ - pmp->pm_fsinfo = 0; - brelse(bpn); - } else { - struct fsinfo *fp = (struct fsinfo *)bpn->b_data; - - putulong(fp->fsinfree, pmp->pm_freeclustercount); - putulong(fp->fsinxtfree, pmp->pm_nxtfree); - if (pmp->pm_flags & MSDOSFSMNT_WAITONFAT) - bwrite(bpn); - else - bdwrite(bpn); - } - } - if (pmp->pm_flags & MSDOSFS_FATMIRROR) { /* * Now copy the block(s) of the modified fat to the other copies of @@ -393,9 +370,6 @@ updatefats(pmp, bp, fatbn) bwrite(bp); else bdwrite(bp); - /* - * Maybe update fsinfo sector here? - */ } /* @@ -431,6 +405,7 @@ usemap_alloc(pmp, cn) pmp->pm_inusemap[cn / N_INUSEBITS] |= 1 << (cn % N_INUSEBITS); KASSERT(pmp->pm_freeclustercount > 0, ("usemap_alloc: too little")); pmp->pm_freeclustercount--; + pmp->pm_flags |= MSDOSFS_FSIMOD; } static __inline void @@ -441,6 +416,7 @@ usemap_free(pmp, cn) MSDOSFS_ASSERT_MP_LOCKED(pmp); pmp->pm_freeclustercount++; + pmp->pm_flags |= MSDOSFS_FSIMOD; KASSERT((pmp->pm_inusemap[cn / N_INUSEBITS] & (1 << (cn % N_INUSEBITS))) != 0, ("Freeing unused sector %ld %ld %x", cn, cn % N_INUSEBITS, (unsigned)pmp->pm_inusemap[cn / N_INUSEBITS])); @@ -742,7 +718,10 @@ chainalloc(pmp, start, count, fillwith, retcluster, got) for (cl = start, n = count; n-- > 0;) usemap_alloc(pmp, cl++); - + pmp->pm_nxtfree = start + count; + if (pmp->pm_nxtfree > pmp->pm_maxcluster) + pmp->pm_nxtfree = CLUST_FIRST; + pmp->pm_flags |= MSDOSFS_FSIMOD; error = fatchain(pmp, start, count, fillwith); if (error != 0) return (error); @@ -754,9 +733,6 @@ chainalloc(pmp, start, count, fillwith, retcluster, got) *retcluster = start; if (got) *got = count; - pmp->pm_nxtfree = start + count; - if (pmp->pm_nxtfree > pmp->pm_maxcluster) - pmp->pm_nxtfree = CLUST_FIRST; return (0); } diff --git a/sys/fs/msdosfs/msdosfs_vfsops.c b/sys/fs/msdosfs/msdosfs_vfsops.c index a209970..213dd00 100644 --- a/sys/fs/msdosfs/msdosfs_vfsops.c +++ b/sys/fs/msdosfs/msdosfs_vfsops.c @@ -896,6 +896,40 @@ msdosfs_statfs(struct mount *mp, struct statfs *sbp) return (0); } +/* + * If we have an FSInfo block, update it. + */ +static int +msdosfs_fsiflush(struct msdosfsmount *pmp, int waitfor) +{ + struct fsinfo *fp; + struct buf *bp; + int error; + + MSDOSFS_LOCK_MP(pmp); + if (pmp->pm_fsinfo == 0 || (pmp->pm_flags & MSDOSFS_FSIMOD) == 0) { + error = 0; + goto unlock; + } + error = bread(pmp->pm_devvp, pmp->pm_fsinfo, pmp->pm_BytesPerSec, + NOCRED, &bp); + if (error != 0) { + brelse(bp); + goto unlock; + } + fp = (struct fsinfo *)bp->b_data; + putulong(fp->fsinfree, pmp->pm_freeclustercount); + putulong(fp->fsinxtfree, pmp->pm_nxtfree); + pmp->pm_flags &= ~MSDOSFS_FSIMOD; + if (waitfor == MNT_WAIT) + error = bwrite(bp); + else + bawrite(bp); +unlock: + MSDOSFS_UNLOCK_MP(pmp); + return (error); +} + static int msdosfs_sync(struct mount *mp, int waitfor) { @@ -958,6 +992,10 @@ loop: allerror = error; VOP_UNLOCK(pmp->pm_devvp, 0); } + + error = msdosfs_fsiflush(pmp, waitfor); + if (error != 0) + allerror = error; return (allerror); } diff --git a/sys/fs/msdosfs/msdosfsmount.h b/sys/fs/msdosfs/msdosfsmount.h index 673095e..10ed95b 100644 --- a/sys/fs/msdosfs/msdosfsmount.h +++ b/sys/fs/msdosfs/msdosfsmount.h @@ -262,6 +262,7 @@ struct msdosfs_args { #define MSDOSFSMNT_WAITONFAT 0x40000000 /* mounted synchronous */ #define MSDOSFS_FATMIRROR 0x20000000 /* FAT is mirrored */ #define MSDOSFS_LARGEFS 0x10000000 /* perform fileno mapping */ +#define MSDOSFS_FSIMOD 0x01000000 #define MSDOSFS_ARGSMAGIC 0xe4eff300 diff --git a/sys/fs/nfs/nfs_commonkrpc.c b/sys/fs/nfs/nfs_commonkrpc.c index f08ba85..86b6987 100644 --- a/sys/fs/nfs/nfs_commonkrpc.c +++ b/sys/fs/nfs/nfs_commonkrpc.c @@ -1080,7 +1080,6 @@ newnfs_set_sigmask(struct thread *td, sigset_t *oldset) SIGDELSET(newset, newnfs_sig_set[i]); } mtx_unlock(&p->p_sigacts->ps_mtx); - sigdeferstop(td); kern_sigprocmask(td, SIG_SETMASK, &newset, oldset, SIGPROCMASK_PROC_LOCKED); PROC_UNLOCK(p); @@ -1092,7 +1091,6 @@ newnfs_restore_sigmask(struct thread *td, sigset_t *set) if (td == NULL) td = curthread; /* XXX */ kern_sigprocmask(td, SIG_SETMASK, set, NULL, 0); - sigallowstop(td); } /* diff --git a/sys/fs/nfsclient/nfs_clstate.c b/sys/fs/nfsclient/nfs_clstate.c index a774103..c62000c 100644 --- a/sys/fs/nfsclient/nfs_clstate.c +++ b/sys/fs/nfsclient/nfs_clstate.c @@ -1888,7 +1888,7 @@ nfscl_recover(struct nfsclclient *clp, struct ucred *cred, NFSPROC_T *p) struct nfsreq *rep; u_int64_t len; u_int32_t delegtype = NFSV4OPEN_DELEGATEWRITE, mode; - int i, igotlock = 0, error, trycnt, firstlock, s; + int i, igotlock = 0, error, trycnt, firstlock; struct nfscllayout *lyp, *nlyp; /* @@ -1945,14 +1945,12 @@ nfscl_recover(struct nfsclclient *clp, struct ucred *cred, NFSPROC_T *p) * This will be translated to NFSERR_STALEDONTRECOVER when * R_DONTRECOVER is set. */ - s = splsoftclock(); NFSLOCKREQ(); TAILQ_FOREACH(rep, &nfsd_reqq, r_chain) { if (rep->r_nmp == nmp) rep->r_flags |= R_DONTRECOVER; } NFSUNLOCKREQ(); - splx(s); /* * Now, mark all delegations "need reclaim". diff --git a/sys/fs/nfsclient/nfs_clvfsops.c b/sys/fs/nfsclient/nfs_clvfsops.c index 83ce3cb..281ce44 100644 --- a/sys/fs/nfsclient/nfs_clvfsops.c +++ b/sys/fs/nfsclient/nfs_clvfsops.c @@ -132,7 +132,7 @@ static struct vfsops nfs_vfsops = { .vfs_unmount = nfs_unmount, .vfs_sysctl = nfs_sysctl, }; -VFS_SET(nfs_vfsops, nfs, VFCF_NETWORK); +VFS_SET(nfs_vfsops, nfs, VFCF_NETWORK | VFCF_SBDRY); /* So that loader and kldload(2) can find us, wherever we are.. */ MODULE_VERSION(nfs, 1); diff --git a/sys/geom/geom_vfs.c b/sys/geom/geom_vfs.c index afc6549..bbed550 100644 --- a/sys/geom/geom_vfs.c +++ b/sys/geom/geom_vfs.c @@ -192,6 +192,10 @@ g_vfs_strategy(struct bufobj *bo, struct buf *bp) bip->bio_done = g_vfs_done; bip->bio_caller2 = bp; bip->bio_length = bp->b_bcount; + if (bp->b_flags & B_BARRIER) { + bip->bio_flags |= BIO_ORDERED; + bp->b_flags &= ~B_BARRIER; + } g_io_request(bip, cp); } diff --git a/sys/i386/acpica/acpi_machdep.c b/sys/i386/acpica/acpi_machdep.c index 0872127..a244e73 100644 --- a/sys/i386/acpica/acpi_machdep.c +++ b/sys/i386/acpica/acpi_machdep.c @@ -139,7 +139,7 @@ table_map(vm_paddr_t pa, int offset, vm_offset_t length) void *data; off = pa & PAGE_MASK; - length = roundup(length + off, PAGE_SIZE); + length = round_page(length + off); pa = pa & PG_FRAME; va = (vm_offset_t)pmap_kenter_temporary(pa, offset) + (offset * PAGE_SIZE); @@ -163,7 +163,7 @@ table_unmap(void *data, vm_offset_t length) va = (vm_offset_t)data; off = va & PAGE_MASK; - length = roundup(length + off, PAGE_SIZE); + length = round_page(length + off); va &= ~PAGE_MASK; while (length > 0) { pmap_kremove(va); diff --git a/sys/i386/i386/pmap.c b/sys/i386/i386/pmap.c index f6ce067..5b784ee 100644 --- a/sys/i386/i386/pmap.c +++ b/sys/i386/i386/pmap.c @@ -5052,7 +5052,7 @@ pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode) vm_size_t tmpsize; offset = pa & PAGE_MASK; - size = roundup(offset + size, PAGE_SIZE); + size = round_page(offset + size); pa = pa & PG_FRAME; if (pa < KERNLOAD && pa + size <= KERNLOAD) @@ -5092,7 +5092,7 @@ pmap_unmapdev(vm_offset_t va, vm_size_t size) return; base = trunc_page(va); offset = va & PAGE_MASK; - size = roundup(offset + size, PAGE_SIZE); + size = round_page(offset + size); kmem_free(kernel_map, base, size); } @@ -5183,7 +5183,7 @@ pmap_change_attr(vm_offset_t va, vm_size_t size, int mode) base = trunc_page(va); offset = va & PAGE_MASK; - size = roundup(offset + size, PAGE_SIZE); + size = round_page(offset + size); /* * Only supported on kernel virtual addresses above the recursive map. diff --git a/sys/i386/include/elf.h b/sys/i386/include/elf.h index 93fa1fd..f932377 100644 --- a/sys/i386/include/elf.h +++ b/sys/i386/include/elf.h @@ -1,118 +1,6 @@ /*- - * Copyright (c) 1996-1997 John D. Polstra. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * $FreeBSD$ + * This file is in the public domain. */ +/* $FreeBSD$ */ -#ifndef _MACHINE_ELF_H_ -#define _MACHINE_ELF_H_ 1 - -/* - * ELF definitions for the i386 architecture. - */ - -#include <sys/elf32.h> /* Definitions common to all 32 bit architectures. */ -#if defined(__ELF_WORD_SIZE) && __ELF_WORD_SIZE == 64 -#include <sys/elf64.h> /* Definitions common to all 64 bit architectures. */ -#endif - -#ifndef __ELF_WORD_SIZE -#define __ELF_WORD_SIZE 32 /* Used by <sys/elf_generic.h> */ -#endif - -#include <sys/elf_generic.h> - -#define ELF_ARCH EM_386 - -#define ELF_MACHINE_OK(x) ((x) == EM_386 || (x) == EM_486) - -/* - * Auxiliary vector entries for passing information to the interpreter. - * - * The i386 supplement to the SVR4 ABI specification names this "auxv_t", - * but POSIX lays claim to all symbols ending with "_t". - */ - -typedef struct { /* Auxiliary vector entry on initial stack */ - int a_type; /* Entry type. */ - union { - long a_val; /* Integer value. */ - void *a_ptr; /* Address. */ - void (*a_fcn)(void); /* Function pointer (not used). */ - } a_un; -} Elf32_Auxinfo; - -#if __ELF_WORD_SIZE == 64 -/* Fake for amd64 loader support */ -typedef struct { - int fake; -} Elf64_Auxinfo; -#endif - -__ElfType(Auxinfo); - -/* Values for a_type. */ -#define AT_NULL 0 /* Terminates the vector. */ -#define AT_IGNORE 1 /* Ignored entry. */ -#define AT_EXECFD 2 /* File descriptor of program to load. */ -#define AT_PHDR 3 /* Program header of program already loaded. */ -#define AT_PHENT 4 /* Size of each program header entry. */ -#define AT_PHNUM 5 /* Number of program header entries. */ -#define AT_PAGESZ 6 /* Page size in bytes. */ -#define AT_BASE 7 /* Interpreter's base address. */ -#define AT_FLAGS 8 /* Flags (unused for i386). */ -#define AT_ENTRY 9 /* Where interpreter should transfer control. */ -#define AT_NOTELF 10 /* Program is not ELF ?? */ -#define AT_UID 11 /* Real uid. */ -#define AT_EUID 12 /* Effective uid. */ -#define AT_GID 13 /* Real gid. */ -#define AT_EGID 14 /* Effective gid. */ -#define AT_EXECPATH 15 /* Path to the executable. */ -#define AT_CANARY 16 /* Canary for SSP. */ -#define AT_CANARYLEN 17 /* Length of the canary. */ -#define AT_OSRELDATE 18 /* OSRELDATE. */ -#define AT_NCPUS 19 /* Number of CPUs. */ -#define AT_PAGESIZES 20 /* Pagesizes. */ -#define AT_PAGESIZESLEN 21 /* Number of pagesizes. */ -#define AT_TIMEKEEP 22 /* Pointer to timehands. */ -#define AT_STACKPROT 23 /* Initial stack protection. */ - -#define AT_COUNT 24 /* Count of defined aux entry types. */ - -/* - * Relocation types. - */ - -#define R_386_COUNT 38 /* Count of defined relocation types. */ - -/* Define "machine" characteristics */ -#define ELF_TARG_CLASS ELFCLASS32 -#define ELF_TARG_DATA ELFDATA2LSB -#define ELF_TARG_MACH EM_386 -#define ELF_TARG_VER 1 - -#define ET_DYN_LOAD_ADDR 0x01001000 - -#endif /* !_MACHINE_ELF_H_ */ +#include <x86/elf.h> diff --git a/sys/i386/include/frame.h b/sys/i386/include/frame.h index 3558b98..0953be7 100644 --- a/sys/i386/include/frame.h +++ b/sys/i386/include/frame.h @@ -1,100 +1,6 @@ /*- - * Copyright (c) 1990 The Regents of the University of California. - * All rights reserved. - * - * This code is derived from software contributed to Berkeley by - * William Jolitz. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 4. Neither the name of the University nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * from: @(#)frame.h 5.2 (Berkeley) 1/18/91 - * $FreeBSD$ + * This file is in the public domain. */ +/* $FreeBSD$ */ -#ifndef _MACHINE_FRAME_H_ -#define _MACHINE_FRAME_H_ 1 - -/* - * System stack frames. - */ - -/* - * Exception/Trap Stack Frame - */ - -struct trapframe { - int tf_fs; - int tf_es; - int tf_ds; - int tf_edi; - int tf_esi; - int tf_ebp; - int tf_isp; - int tf_ebx; - int tf_edx; - int tf_ecx; - int tf_eax; - int tf_trapno; - /* below portion defined in 386 hardware */ - int tf_err; - int tf_eip; - int tf_cs; - int tf_eflags; - /* below only when crossing rings (e.g. user to kernel) */ - int tf_esp; - int tf_ss; -}; - -/* Superset of trap frame, for traps from virtual-8086 mode */ - -struct trapframe_vm86 { - int tf_fs; - int tf_es; - int tf_ds; - int tf_edi; - int tf_esi; - int tf_ebp; - int tf_isp; - int tf_ebx; - int tf_edx; - int tf_ecx; - int tf_eax; - int tf_trapno; - /* below portion defined in 386 hardware */ - int tf_err; - int tf_eip; - int tf_cs; - int tf_eflags; - /* below only when crossing rings (e.g. user to kernel) */ - int tf_esp; - int tf_ss; - /* below only when switching out of VM86 mode */ - int tf_vm86_es; - int tf_vm86_ds; - int tf_vm86_fs; - int tf_vm86_gs; -}; - -#endif /* _MACHINE_FRAME_H_ */ +#include <x86/frame.h> diff --git a/sys/i386/include/sigframe.h b/sys/i386/include/sigframe.h index 98be731..8de4664 100644 --- a/sys/i386/include/sigframe.h +++ b/sys/i386/include/sigframe.h @@ -89,25 +89,6 @@ struct sigframe4 { #endif #endif -struct sigframe { - /* - * The first four members may be used by applications. - * - * NOTE: The 4th argument is undocumented, ill commented - * on and seems to be somewhat BSD "standard". Handlers - * installed with sigvec may be using it. - */ - register_t sf_signum; - register_t sf_siginfo; /* code or pointer to sf_si */ - register_t sf_ucontext; /* points to sf_uc */ - register_t sf_addr; /* undocumented 4th arg */ - - union { - __siginfohandler_t *sf_action; - __sighandler_t *sf_handler; - } sf_ahu; - ucontext_t sf_uc; /* = *sf_ucontext */ - siginfo_t sf_si; /* = *sf_siginfo (SA_SIGINFO case) */ -}; +#include <x86/sigframe.h> #endif /* !_MACHINE_SIGFRAME_H_ */ diff --git a/sys/i386/include/signal.h b/sys/i386/include/signal.h index 892115b..26c1ee6 100644 --- a/sys/i386/include/signal.h +++ b/sys/i386/include/signal.h @@ -33,25 +33,7 @@ #ifndef _MACHINE_SIGNAL_H_ #define _MACHINE_SIGNAL_H_ -#include <sys/cdefs.h> -#include <sys/_sigset.h> - -/* - * Machine-dependent signal definitions - */ - -typedef int sig_atomic_t; - -#if __BSD_VISIBLE -#include <machine/trap.h> /* codes for SIGILL, SIGFPE */ - -/* - * Information pushed on stack when a signal is delivered. - * This is used by the kernel to restore state following - * execution of the signal handler. It is also made available - * to the handler to allow it to restore state properly if - * a non-standard exit is performed. - */ +#include <x86/signal.h> #if defined(_KERNEL) && defined(COMPAT_43) /* @@ -82,57 +64,4 @@ struct osigcontext { }; #endif -/* - * The sequence of the fields/registers in struct sigcontext should match - * those in mcontext_t and struct trapframe. - */ -struct sigcontext { - struct __sigset sc_mask; /* signal mask to restore */ - int sc_onstack; /* sigstack state to restore */ - int sc_gs; /* machine state (struct trapframe) */ - int sc_fs; - int sc_es; - int sc_ds; - int sc_edi; - int sc_esi; - int sc_ebp; - int sc_isp; - int sc_ebx; - int sc_edx; - int sc_ecx; - int sc_eax; - int sc_trapno; - int sc_err; - int sc_eip; - int sc_cs; - int sc_efl; - int sc_esp; - int sc_ss; - int sc_len; /* sizeof(mcontext_t) */ - /* - * See <machine/ucontext.h> and <machine/npx.h> for - * the following fields. - */ - int sc_fpformat; - int sc_ownedfp; - int sc_flags; - int sc_fpstate[128] __aligned(16); - - int sc_fsbase; - int sc_gsbase; - - int sc_xfpustate; - int sc_xfpustate_len; - - int sc_spare2[4]; -}; - -#define sc_sp sc_esp -#define sc_fp sc_ebp -#define sc_pc sc_eip -#define sc_ps sc_efl -#define sc_eflags sc_efl - -#endif /* __BSD_VISIBLE */ - #endif /* !_MACHINE_SIGNAL_H_ */ diff --git a/sys/i386/include/ucontext.h b/sys/i386/include/ucontext.h index 79aabd7..fe21b34 100644 --- a/sys/i386/include/ucontext.h +++ b/sys/i386/include/ucontext.h @@ -31,64 +31,6 @@ #ifndef _MACHINE_UCONTEXT_H_ #define _MACHINE_UCONTEXT_H_ -/* Keep _MC_* values similar to amd64 */ -#define _MC_HASSEGS 0x1 -#define _MC_HASBASES 0x2 -#define _MC_HASFPXSTATE 0x4 -#define _MC_FLAG_MASK (_MC_HASSEGS | _MC_HASBASES | _MC_HASFPXSTATE) - -typedef struct __mcontext { - /* - * The definition of mcontext_t must match the layout of - * struct sigcontext after the sc_mask member. This is so - * that we can support sigcontext and ucontext_t at the same - * time. - */ - __register_t mc_onstack; /* XXX - sigcontext compat. */ - __register_t mc_gs; /* machine state (struct trapframe) */ - __register_t mc_fs; - __register_t mc_es; - __register_t mc_ds; - __register_t mc_edi; - __register_t mc_esi; - __register_t mc_ebp; - __register_t mc_isp; - __register_t mc_ebx; - __register_t mc_edx; - __register_t mc_ecx; - __register_t mc_eax; - __register_t mc_trapno; - __register_t mc_err; - __register_t mc_eip; - __register_t mc_cs; - __register_t mc_eflags; - __register_t mc_esp; - __register_t mc_ss; - - int mc_len; /* sizeof(mcontext_t) */ -#define _MC_FPFMT_NODEV 0x10000 /* device not present or configured */ -#define _MC_FPFMT_387 0x10001 -#define _MC_FPFMT_XMM 0x10002 - int mc_fpformat; -#define _MC_FPOWNED_NONE 0x20000 /* FP state not used */ -#define _MC_FPOWNED_FPU 0x20001 /* FP state came from FPU */ -#define _MC_FPOWNED_PCB 0x20002 /* FP state came from PCB */ - int mc_ownedfp; - __register_t mc_flags; - /* - * See <machine/npx.h> for the internals of mc_fpstate[]. - */ - int mc_fpstate[128] __aligned(16); - - __register_t mc_fsbase; - __register_t mc_gsbase; - - __register_t mc_xfpustate; - __register_t mc_xfpustate_len; - - int mc_spare2[4]; -} mcontext_t; - #if defined(_KERNEL) && defined(COMPAT_FREEBSD4) struct mcontext4 { __register_t mc_onstack; /* XXX - sigcontext compat. */ @@ -116,4 +58,6 @@ struct mcontext4 { }; #endif +#include <x86/ucontext.h> + #endif /* !_MACHINE_UCONTEXT_H_ */ diff --git a/sys/i386/isa/pmtimer.c b/sys/i386/isa/pmtimer.c index d8e6d1f..b5a0302 100644 --- a/sys/i386/isa/pmtimer.c +++ b/sys/i386/isa/pmtimer.c @@ -82,26 +82,21 @@ static struct timeval diff_time; static int pmtimer_suspend(device_t dev) { - int pl; - pl = splsoftclock(); microtime(&diff_time); inittodr(0); microtime(&suspend_time); timevalsub(&diff_time, &suspend_time); - splx(pl); return (0); } static int pmtimer_resume(device_t dev) { - int pl; u_int second, minute, hour; struct timeval resume_time, tmp_time; /* modified for adjkerntz */ - pl = splsoftclock(); timer_restore(); /* restore the all timers */ inittodr(0); /* adjust time to RTC */ microtime(&resume_time); @@ -118,16 +113,13 @@ pmtimer_resume(device_t dev) timevalsub(&resume_time, &suspend_time); /* Fixup the calltodo list with the delta time. */ adjust_timeout_calltodo(&resume_time); -#endif /* PMTIMER_FIXUP_CALLTODOK */ - splx(pl); -#ifndef PMTIMER_FIXUP_CALLTODO - second = resume_time.tv_sec - suspend_time.tv_sec; -#else /* PMTIMER_FIXUP_CALLTODO */ /* * We've already calculated resume_time to be the delta between * the suspend and the resume. */ second = resume_time.tv_sec; +#else /* !PMTIMER_FIXUP_CALLTODO */ + second = resume_time.tv_sec - suspend_time.tv_sec; #endif /* PMTIMER_FIXUP_CALLTODO */ hour = second / 3600; second %= 3600; diff --git a/sys/i386/xen/pmap.c b/sys/i386/xen/pmap.c index 7f65a21..a8f11a4 100644 --- a/sys/i386/xen/pmap.c +++ b/sys/i386/xen/pmap.c @@ -3973,7 +3973,7 @@ pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode) vm_size_t tmpsize; offset = pa & PAGE_MASK; - size = roundup(offset + size, PAGE_SIZE); + size = round_page(offset + size); pa = pa & PG_FRAME; if (pa < KERNLOAD && pa + size <= KERNLOAD) @@ -4013,7 +4013,7 @@ pmap_unmapdev(vm_offset_t va, vm_size_t size) return; base = trunc_page(va); offset = va & PAGE_MASK; - size = roundup(offset + size, PAGE_SIZE); + size = round_page(offset + size); kmem_free(kernel_map, base, size); } @@ -4105,7 +4105,7 @@ pmap_change_attr(vm_offset_t va, vm_size_t size, int mode) base = trunc_page(va); offset = va & PAGE_MASK; - size = roundup(offset + size, PAGE_SIZE); + size = round_page(offset + size); /* Only supported on kernel virtual addresses. */ if (base <= VM_MAXUSER_ADDRESS) diff --git a/sys/ia64/conf/GENERIC b/sys/ia64/conf/GENERIC index 196e5be..810578f 100644 --- a/sys/ia64/conf/GENERIC +++ b/sys/ia64/conf/GENERIC @@ -44,7 +44,7 @@ options NFSLOCKD # Network Lock Manager options NFSD # New Network Filesystem Server options NFS_ROOT # NFS usable as root device options P1003_1B_SEMAPHORES # POSIX-style semaphores -#options PREEMPTION # Enable kernel thread preemption +options PREEMPTION # Enable kernel thread preemption options PRINTF_BUFR_SIZE=128 # Printf buffering to limit interspersion options PROCFS # Process filesystem (/proc) options PSEUDOFS # Pseudo-filesystem framework diff --git a/sys/ia64/ia64/mem.c b/sys/ia64/ia64/mem.c index 339985d..70dcf7b 100644 --- a/sys/ia64/ia64/mem.c +++ b/sys/ia64/ia64/mem.c @@ -128,6 +128,8 @@ kmemphys: */ addr = trunc_page(v); eaddr = round_page(v + c); + if (addr < VM_MAXUSER_ADDRESS) + return (EFAULT); for (; addr < eaddr; addr += PAGE_SIZE) { if (pmap_kextract(addr) == 0) return (EFAULT); diff --git a/sys/ia64/ia64/syscall.S b/sys/ia64/ia64/syscall.S index ef559e8..84a03da 100644 --- a/sys/ia64/ia64/syscall.S +++ b/sys/ia64/ia64/syscall.S @@ -228,7 +228,7 @@ ENTRY_NOPROFILE(epc_syscall, 8) { .mmi mov r16=ar.rsc mov ar.rsc=0 - mov r17=r13 + nop 0 ;; } { .mmi @@ -239,13 +239,13 @@ ENTRY_NOPROFILE(epc_syscall, 8) ;; } { .mmi - mov r13=ar.k4 + mov r21=ar.unat add r30=-SIZEOF_TRAPFRAME,r14 mov r20=sp ;; } { .mii - mov r21=ar.unat + mov r17=r13 dep r30=0,r30,0,10 ;; add sp=-16,r30 @@ -258,10 +258,10 @@ ENTRY_NOPROFILE(epc_syscall, 8) add r31=8,r30 ;; } -{ .mii +{ .mmi + mov r13=ar.k4 mov r22=ar.fpsr sub r29=r14,r30 - nop 0 } { .mmi mov r23=ar.bsp diff --git a/sys/kern/kern_descrip.c b/sys/kern/kern_descrip.c index fc74bdb..9de55e82 100644 --- a/sys/kern/kern_descrip.c +++ b/sys/kern/kern_descrip.c @@ -1949,11 +1949,11 @@ fdfree(struct thread *td) fdp->fd_jdir = NULL; FILEDESC_XUNLOCK(fdp); - if (cdir) + if (cdir != NULL) vrele(cdir); - if (rdir) + if (rdir != NULL) vrele(rdir); - if (jdir) + if (jdir != NULL) vrele(jdir); fddrop(fdp); diff --git a/sys/kern/kern_fork.c b/sys/kern/kern_fork.c index 0d2709f..287d202 100644 --- a/sys/kern/kern_fork.c +++ b/sys/kern/kern_fork.c @@ -942,7 +942,7 @@ fail1: vmspace_free(vm2); uma_zfree(proc_zone, newproc); #ifdef PROCDESC - if (((flags & RFPROCDESC) != 0) && (fp_procdesc != NULL)) { + if ((flags & RFPROCDESC) != 0 && fp_procdesc != NULL) { fdclose(td->td_proc->p_fd, fp_procdesc, *procdescp, td); fdrop(fp_procdesc, td); } diff --git a/sys/kern/kern_sig.c b/sys/kern/kern_sig.c index 5bb49a8..e1dbedc 100644 --- a/sys/kern/kern_sig.c +++ b/sys/kern/kern_sig.c @@ -2537,16 +2537,22 @@ tdsigcleanup(struct thread *td) } -/* Defer the delivery of SIGSTOP for the current thread. */ -void -sigdeferstop(struct thread *td) +/* + * Defer the delivery of SIGSTOP for the current thread. Returns true + * if stops were deferred and false if they were already deferred. + */ +int +sigdeferstop(void) { + struct thread *td; - KASSERT(!(td->td_flags & TDF_SBDRY), - ("attempt to set TDF_SBDRY recursively")); + td = curthread; + if (td->td_flags & TDF_SBDRY) + return (0); thread_lock(td); td->td_flags |= TDF_SBDRY; thread_unlock(td); + return (1); } /* @@ -2555,11 +2561,11 @@ sigdeferstop(struct thread *td) * will suspend either via ast() or a subsequent interruptible sleep. */ void -sigallowstop(struct thread *td) +sigallowstop() { + struct thread *td; - KASSERT(td->td_flags & TDF_SBDRY, - ("attempt to clear already-cleared TDF_SBDRY")); + td = curthread; thread_lock(td); td->td_flags &= ~TDF_SBDRY; thread_unlock(td); @@ -3130,6 +3136,7 @@ corefile_open(const char *comm, uid_t uid, pid_t pid, struct thread *td, break; default: sbuf_putc(&sb, format[i]); + break; } } free(hostname, M_TEMP); diff --git a/sys/kern/kern_tc.c b/sys/kern/kern_tc.c index 2ffa2f9..6e1f486 100644 --- a/sys/kern/kern_tc.c +++ b/sys/kern/kern_tc.c @@ -1446,6 +1446,50 @@ SYSCTL_PROC(_kern_timecounter, OID_AUTO, choice, CTLTYPE_STRING | CTLFLAG_RD, * RFC 2783 PPS-API implementation. */ +static int +pps_fetch(struct pps_fetch_args *fapi, struct pps_state *pps) +{ + int err, timo; + pps_seq_t aseq, cseq; + struct timeval tv; + + if (fapi->tsformat && fapi->tsformat != PPS_TSFMT_TSPEC) + return (EINVAL); + + /* + * If no timeout is requested, immediately return whatever values were + * most recently captured. If timeout seconds is -1, that's a request + * to block without a timeout. WITNESS won't let us sleep forever + * without a lock (we really don't need a lock), so just repeatedly + * sleep a long time. + */ + if (fapi->timeout.tv_sec || fapi->timeout.tv_nsec) { + if (fapi->timeout.tv_sec == -1) + timo = 0x7fffffff; + else { + tv.tv_sec = fapi->timeout.tv_sec; + tv.tv_usec = fapi->timeout.tv_nsec / 1000; + timo = tvtohz(&tv); + } + aseq = pps->ppsinfo.assert_sequence; + cseq = pps->ppsinfo.clear_sequence; + while (aseq == pps->ppsinfo.assert_sequence && + cseq == pps->ppsinfo.clear_sequence) { + err = tsleep(pps, PCATCH, "ppsfch", timo); + if (err == EWOULDBLOCK && fapi->timeout.tv_sec == -1) { + continue; + } else if (err != 0) { + return (err); + } + } + } + + pps->ppsinfo.current_mode = pps->ppsparam.mode; + fapi->pps_info_buf = pps->ppsinfo; + + return (0); +} + int pps_ioctl(u_long cmd, caddr_t data, struct pps_state *pps) { @@ -1485,13 +1529,7 @@ pps_ioctl(u_long cmd, caddr_t data, struct pps_state *pps) return (0); case PPS_IOC_FETCH: fapi = (struct pps_fetch_args *)data; - if (fapi->tsformat && fapi->tsformat != PPS_TSFMT_TSPEC) - return (EINVAL); - if (fapi->timeout.tv_sec || fapi->timeout.tv_nsec) - return (EOPNOTSUPP); - pps->ppsinfo.current_mode = pps->ppsparam.mode; - fapi->pps_info_buf = pps->ppsinfo; - return (0); + return (pps_fetch(fapi, pps)); #ifdef FFCLOCK case PPS_IOC_FETCH_FFCOUNTER: fapi_ffc = (struct pps_fetch_ffc_args *)data; @@ -1540,7 +1578,7 @@ pps_ioctl(u_long cmd, caddr_t data, struct pps_state *pps) void pps_init(struct pps_state *pps) { - pps->ppscap |= PPS_TSFMT_TSPEC; + pps->ppscap |= PPS_TSFMT_TSPEC | PPS_CANWAIT; if (pps->ppscap & PPS_CAPTUREASSERT) pps->ppscap |= PPS_OFFSETASSERT; if (pps->ppscap & PPS_CAPTURECLEAR) @@ -1680,6 +1718,9 @@ pps_event(struct pps_state *pps, int event) hardpps(tsp, ts.tv_nsec + 1000000000 * ts.tv_sec); } #endif + + /* Wakeup anyone sleeping in pps_fetch(). */ + wakeup(pps); } /* diff --git a/sys/kern/kern_thread.c b/sys/kern/kern_thread.c index bee267f..4f0266b 100644 --- a/sys/kern/kern_thread.c +++ b/sys/kern/kern_thread.c @@ -748,10 +748,10 @@ stopme: * P_SINGLE_EXIT | return_instead == 0| return_instead != 0 *---------------+--------------------+--------------------- * 0 | returns 0 | returns 0 or 1 - * | when ST ends | immediatly + * | when ST ends | immediately *---------------+--------------------+--------------------- * 1 | thread exits | returns 1 - * | | immediatly + * | | immediately * 0 = thread_exit() or suspension ok, * other = return error instead of stopping the thread. * diff --git a/sys/kern/subr_trap.c b/sys/kern/subr_trap.c index 22cabcb..bd06f20 100644 --- a/sys/kern/subr_trap.c +++ b/sys/kern/subr_trap.c @@ -164,6 +164,8 @@ userret(struct thread *td, struct trapframe *frame) ("userret: Returning with with pinned thread")); KASSERT(td->td_vp_reserv == 0, ("userret: Returning while holding vnode reservation")); + KASSERT((td->td_flags & TDF_SBDRY) == 0, + ("userret: Returning with stop signals deferred")); #ifdef VIMAGE /* Unfortunately td_vnet_lpush needs VNET_DEBUG. */ VNET_ASSERT(curvnet == NULL, diff --git a/sys/kern/subr_turnstile.c b/sys/kern/subr_turnstile.c index 76fb964..0a21ad9 100644 --- a/sys/kern/subr_turnstile.c +++ b/sys/kern/subr_turnstile.c @@ -215,10 +215,9 @@ propagate_priority(struct thread *td) /* * If the thread is asleep, then we are probably about - * to deadlock. To make debugging this easier, just - * panic and tell the user which thread misbehaved so - * they can hopefully get a stack trace from the truly - * misbehaving thread. + * to deadlock. To make debugging this easier, show + * backtrace of misbehaving thread and panic to not + * leave the kernel deadlocked. */ if (TD_IS_SLEEPING(td)) { printf( diff --git a/sys/kern/sys_capability.c b/sys/kern/sys_capability.c index fa76356..6fb4fee 100644 --- a/sys/kern/sys_capability.c +++ b/sys/kern/sys_capability.c @@ -113,7 +113,7 @@ sys_cap_getmode(struct thread *td, struct cap_getmode_args *uap) { u_int i; - i = (IN_CAPABILITY_MODE(td)) ? 1 : 0; + i = IN_CAPABILITY_MODE(td) ? 1 : 0; return (copyout(&i, uap->modep, sizeof(i))); } diff --git a/sys/kern/sys_pipe.c b/sys/kern/sys_pipe.c index 338256c..5d0c434 100644 --- a/sys/kern/sys_pipe.c +++ b/sys/kern/sys_pipe.c @@ -473,7 +473,7 @@ sys_pipe(struct thread *td, struct pipe_args *uap) error = kern_pipe(td, fildes); if (error) return (error); - + td->td_retval[0] = fildes[0]; td->td_retval[1] = fildes[1]; diff --git a/sys/kern/vfs_bio.c b/sys/kern/vfs_bio.c index 96c8442..6393399 100644 --- a/sys/kern/vfs_bio.c +++ b/sys/kern/vfs_bio.c @@ -206,6 +206,9 @@ SYSCTL_INT(_vfs, OID_AUTO, flushbufqtarget, CTLFLAG_RW, &flushbufqtarget, 0, static long notbufdflashes; SYSCTL_LONG(_vfs, OID_AUTO, notbufdflashes, CTLFLAG_RD, ¬bufdflashes, 0, "Number of dirty buffer flushes done by the bufdaemon helpers"); +static long barrierwrites; +SYSCTL_LONG(_vfs, OID_AUTO, barrierwrites, CTLFLAG_RW, &barrierwrites, 0, + "Number of barrier writes"); /* * Wakeup point for bufdaemon, as well as indicator of whether it is already @@ -888,6 +891,9 @@ bufwrite(struct buf *bp) return (0); } + if (bp->b_flags & B_BARRIER) + barrierwrites++; + oldflags = bp->b_flags; BUF_ASSERT_HELD(bp); @@ -1007,6 +1013,8 @@ bdwrite(struct buf *bp) CTR3(KTR_BUF, "bdwrite(%p) vp %p flags %X", bp, bp->b_vp, bp->b_flags); KASSERT(bp->b_bufobj != NULL, ("No b_bufobj %p", bp)); + KASSERT((bp->b_flags & B_BARRIER) == 0, + ("Barrier request in delayed write %p", bp)); BUF_ASSERT_HELD(bp); if (bp->b_flags & B_INVAL) { @@ -1167,6 +1175,40 @@ bawrite(struct buf *bp) } /* + * babarrierwrite: + * + * Asynchronous barrier write. Start output on a buffer, but do not + * wait for it to complete. Place a write barrier after this write so + * that this buffer and all buffers written before it are committed to + * the disk before any buffers written after this write are committed + * to the disk. The buffer is released when the output completes. + */ +void +babarrierwrite(struct buf *bp) +{ + + bp->b_flags |= B_ASYNC | B_BARRIER; + (void) bwrite(bp); +} + +/* + * bbarrierwrite: + * + * Synchronous barrier write. Start output on a buffer and wait for + * it to complete. Place a write barrier after this write so that + * this buffer and all buffers written before it are committed to + * the disk before any buffers written after this write are committed + * to the disk. The buffer is released when the output completes. + */ +int +bbarrierwrite(struct buf *bp) +{ + + bp->b_flags |= B_BARRIER; + return (bwrite(bp)); +} + +/* * bwillwrite: * * Called prior to the locking of any vnodes when we are expecting to diff --git a/sys/kern/vfs_cluster.c b/sys/kern/vfs_cluster.c index 19ee05f..663b66f 100644 --- a/sys/kern/vfs_cluster.c +++ b/sys/kern/vfs_cluster.c @@ -944,11 +944,17 @@ cluster_wbuild(vp, size, start_lbn, len) } bp->b_bcount += size; bp->b_bufsize += size; - bundirty(tbp); - tbp->b_flags &= ~B_DONE; - tbp->b_ioflags &= ~BIO_ERROR; + /* + * If any of the clustered buffers have their + * B_BARRIER flag set, transfer that request to + * the cluster. + */ + bp->b_flags |= (tbp->b_flags & B_BARRIER); + tbp->b_flags &= ~(B_DONE | B_BARRIER); tbp->b_flags |= B_ASYNC; + tbp->b_ioflags &= ~BIO_ERROR; tbp->b_iocmd = BIO_WRITE; + bundirty(tbp); reassignbuf(tbp); /* put on clean list */ bufobj_wref(tbp->b_bufobj); BUF_KERNPROC(tbp); diff --git a/sys/kern/vfs_export.c b/sys/kern/vfs_export.c index 114c23e..6a3f291 100644 --- a/sys/kern/vfs_export.c +++ b/sys/kern/vfs_export.c @@ -49,6 +49,7 @@ __FBSDID("$FreeBSD$"); #include <sys/mutex.h> #include <sys/rwlock.h> #include <sys/refcount.h> +#include <sys/signalvar.h> #include <sys/socket.h> #include <sys/systm.h> #include <sys/vnode.h> diff --git a/sys/kern/vfs_init.c b/sys/kern/vfs_init.c index 8172f18..eab48fb 100644 --- a/sys/kern/vfs_init.c +++ b/sys/kern/vfs_init.c @@ -122,7 +122,7 @@ struct vfsconf * vfs_byname_kld(const char *fstype, struct thread *td, int *error) { struct vfsconf *vfsp; - int fileid; + int fileid, loaded; vfsp = vfs_byname(fstype); if (vfsp != NULL) @@ -130,13 +130,17 @@ vfs_byname_kld(const char *fstype, struct thread *td, int *error) /* Try to load the respective module. */ *error = kern_kldload(td, fstype, &fileid); + loaded = (*error == 0); + if (*error == EEXIST) + *error = 0; if (*error) return (NULL); /* Look up again to see if the VFS was loaded. */ vfsp = vfs_byname(fstype); if (vfsp == NULL) { - (void)kern_kldunload(td, fileid, LINKER_UNLOAD_FORCE); + if (loaded) + (void)kern_kldunload(td, fileid, LINKER_UNLOAD_FORCE); *error = ENODEV; return (NULL); } diff --git a/sys/kern/vfs_lookup.c b/sys/kern/vfs_lookup.c index e5ee4f6..fbde152 100644 --- a/sys/kern/vfs_lookup.c +++ b/sys/kern/vfs_lookup.c @@ -339,7 +339,7 @@ namei(struct nameidata *ndp) auio.uio_offset = 0; auio.uio_rw = UIO_READ; auio.uio_segflg = UIO_SYSSPACE; - auio.uio_td = (struct thread *)0; + auio.uio_td = td; auio.uio_resid = MAXPATHLEN; error = VOP_READLINK(ndp->ni_vp, &auio, cnp->cn_cred); if (error) { diff --git a/sys/kern/vfs_syscalls.c b/sys/kern/vfs_syscalls.c index dd1232c..bbda70d 100644 --- a/sys/kern/vfs_syscalls.c +++ b/sys/kern/vfs_syscalls.c @@ -980,7 +980,10 @@ flags_to_rights(int flags) if (flags & O_TRUNC) rights |= CAP_FTRUNCATE; - if ((flags & O_EXLOCK) || (flags & O_SHLOCK)) + if (flags & (O_SYNC | O_FSYNC)) + rights |= CAP_FSYNC; + + if (flags & (O_EXLOCK | O_SHLOCK)) rights |= CAP_FLOCK; return (rights); @@ -3265,8 +3268,7 @@ kern_futimes(struct thread *td, int fd, struct timeval *tptr, AUDIT_ARG_FD(fd); if ((error = getutimes(tptr, tptrseg, ts)) != 0) return (error); - if ((error = getvnode(td->td_proc->p_fd, fd, CAP_FUTIMES, &fp)) - != 0) + if ((error = getvnode(td->td_proc->p_fd, fd, CAP_FUTIMES, &fp)) != 0) return (error); #ifdef AUDIT vn_lock(fp->f_vnode, LK_SHARED | LK_RETRY); @@ -3416,8 +3418,7 @@ sys_fsync(td, uap) int error, lock_flags; AUDIT_ARG_FD(uap->fd); - if ((error = getvnode(td->td_proc->p_fd, uap->fd, CAP_FSYNC, - &fp)) != 0) + if ((error = getvnode(td->td_proc->p_fd, uap->fd, CAP_FSYNC, &fp)) != 0) return (error); vp = fp->f_vnode; if ((error = vn_start_write(vp, &mp, V_WAIT | PCATCH)) != 0) @@ -3526,8 +3527,7 @@ kern_renameat(struct thread *td, int oldfd, char *old, int newfd, char *new, goto out1; } NDINIT_ATRIGHTS(&tond, RENAME, LOCKPARENT | LOCKLEAF | NOCACHE | - SAVESTART | AUDITVNODE2, pathseg, new, newfd, CAP_CREATE, - td); + SAVESTART | AUDITVNODE2, pathseg, new, newfd, CAP_CREATE, td); if (fromnd.ni_vp->v_type == VDIR) tond.ni_cnd.cn_flags |= WILLBEDIR; if ((error = namei(&tond)) != 0) { @@ -3826,8 +3826,7 @@ kern_ogetdirentries(struct thread *td, struct ogetdirentries_args *uap, /* XXX arbitrary sanity limit on `count'. */ if (uap->count > 64 * 1024) return (EINVAL); - if ((error = getvnode(td->td_proc->p_fd, uap->fd, CAP_READ, - &fp)) != 0) + if ((error = getvnode(td->td_proc->p_fd, uap->fd, CAP_READ, &fp)) != 0) return (error); if ((fp->f_flag & FREAD) == 0) { fdrop(fp, td); @@ -4618,7 +4617,7 @@ kern_posix_fadvise(struct thread *td, int fd, off_t offset, off_t len, error = fget(td, fd, 0, &fp); if (error != 0) goto out; - + switch (fp->f_type) { case DTYPE_VNODE: break; diff --git a/sys/modules/acpi/acpi/Makefile b/sys/modules/acpi/acpi/Makefile index 467d19f..5206678 100644 --- a/sys/modules/acpi/acpi/Makefile +++ b/sys/modules/acpi/acpi/Makefile @@ -32,33 +32,35 @@ KMOD= acpi # ACPI CA sources -SRCS+= dbcmds.c dbdisply.c dbexec.c dbfileio.c dbhistry.c dbinput.c dbmethod.c -SRCS+= dbnames.c dbstats.c dbutils.c dbxface.c +SRCS+= dbcmds.c dbconvert.c dbdisply.c dbexec.c dbfileio.c dbhistry.c +SRCS+= dbinput.c dbmethod.c dbnames.c dbstats.c dbutils.c dbxface.c SRCS+= dmbuffer.c dmdeferred.c dmnames.c dmopcode.c dmobject.c dmresrc.c SRCS+= dmresrcl.c dmresrcl2.c dmresrcs.c dmutils.c dmwalk.c SRCS+= dsargs.c dscontrol.c dsfield.c dsinit.c dsmethod.c dsmthdat.c SRCS+= dsobject.c dsopcode.c dsutils.c dswexec.c dswload.c dswload2.c SRCS+= dswscope.c dswstate.c -SRCS+= evevent.c evglock.c evgpe.c evgpeblk.c evgpeinit.c evgpeutil.c evmisc.c -SRCS+= evregion.c evrgnini.c evsci.c evxface.c evxfevnt.c evxfgpe.c evxfregn.c +SRCS+= evevent.c evglock.c evgpe.c evgpeblk.c evgpeinit.c evgpeutil.c +SRCS+= evhandler.c evmisc.c evregion.c evrgnini.c evsci.c evxface.c +SRCS+= evxfevnt.c evxfgpe.c evxfregn.c SRCS+= exconfig.c exconvrt.c excreate.c exdebug.c exdump.c exfield.c SRCS+= exfldio.c exmisc.c exmutex.c exnames.c exoparg1.c exoparg2.c SRCS+= exoparg3.c exoparg6.c exprep.c exregion.c exresnte.c exresolv.c SRCS+= exresop.c exstore.c exstoren.c exstorob.c exsystem.c exutils.c SRCS+= hwacpi.c hwesleep.c hwgpe.c hwpci.c hwregs.c hwsleep.c hwtimer.c SRCS+= hwvalid.c hwxface.c hwxfsleep.c -SRCS+= nsaccess.c nsalloc.c nsdump.c nseval.c nsinit.c nsload.c nsnames.c -SRCS+= nsobject.c nsparse.c nspredef.c nsrepair.c nsrepair2.c nssearch.c -SRCS+= nsutils.c nswalk.c nsxfeval.c nsxfname.c nsxfobj.c -SRCS+= psargs.c psloop.c psopcode.c psparse.c psscope.c pstree.c psutils.c -SRCS+= pswalk.c psxface.c -SRCS+= rsaddr.c rscalc.c rscreate.c rsdump.c rsinfo.c rsio.c rsirq.c rslist.c -SRCS+= rsmemory.c rsmisc.c rsserial.c rsutils.c rsxface.c +SRCS+= nsaccess.c nsalloc.c nsconvert.c nsdump.c nseval.c nsinit.c nsload.c +SRCS+= nsnames.c nsobject.c nsparse.c nspredef.c nsprepkg.c nsrepair.c +SRCS+= nsrepair2.c nssearch.c nsutils.c nswalk.c nsxfeval.c nsxfname.c +SRCS+= nsxfobj.c +SRCS+= psargs.c psloop.c psobject.c psopcode.c psopinfo.c psparse.c +SRCS+= psscope.c pstree.c psutils.c pswalk.c psxface.c +SRCS+= rsaddr.c rscalc.c rscreate.c rsdump.c rsdumpinfo.c rsinfo.c rsio.c +SRCS+= rsirq.c rslist.c rsmemory.c rsmisc.c rsserial.c rsutils.c rsxface.c SRCS+= tbfadt.c tbfind.c tbinstal.c tbutils.c tbxface.c tbxfload.c tbxfroot.c SRCS+= utaddress.c utalloc.c utcache.c utcopy.c utdebug.c utdecode.c SRCS+= utdelete.c uteval.c utexcep.c utglobal.c utids.c utinit.c utlock.c -SRCS+= utmath.c utmisc.c utmutex.c utobject.c utosi.c utresrc.c utstate.c -SRCS+= utxface.c utxferror.c utxfinit.c +SRCS+= utmath.c utmisc.c utmutex.c utobject.c utosi.c utownerid.c utresrc.c +SRCS+= utstate.c utstring.c utxface.c utxferror.c utxfinit.c #SRCS+= utxfmutex.c # OSPM layer and core hardware drivers diff --git a/sys/modules/mxge/mxge/Makefile b/sys/modules/mxge/mxge/Makefile index c478462..3f1f80f 100644 --- a/sys/modules/mxge/mxge/Makefile +++ b/sys/modules/mxge/mxge/Makefile @@ -3,6 +3,6 @@ .PATH: ${.CURDIR}/../../../dev/mxge KMOD= if_mxge -SRCS= if_mxge.c mxge_lro.c device_if.h bus_if.h pci_if.h opt_inet.h +SRCS= if_mxge.c device_if.h bus_if.h pci_if.h opt_inet.h opt_inet6.h .include <bsd.kmod.mk> diff --git a/sys/net80211/ieee80211_adhoc.c b/sys/net80211/ieee80211_adhoc.c index b0998f5..ecf3a87 100644 --- a/sys/net80211/ieee80211_adhoc.c +++ b/sys/net80211/ieee80211_adhoc.c @@ -688,7 +688,9 @@ adhoc_recv_mgmt(struct ieee80211_node *ni, struct mbuf *m0, struct ieee80211_frame *wh; uint8_t *frm, *efrm, *sfrm; uint8_t *ssid, *rates, *xrates; +#if 0 int ht_state_change = 0; +#endif wh = mtod(m0, struct ieee80211_frame *); frm = (uint8_t *)&wh[1]; @@ -768,8 +770,23 @@ adhoc_recv_mgmt(struct ieee80211_node *ni, struct mbuf *m0, IEEE80211_RSSI_LPF(ni->ni_avgrssi, rssi); ni->ni_noise = nf; } + /* + * Same here - the channel width change should + * be applied to the specific peer node, not + * to the ic. Ie, the interface configuration + * should stay in its current channel width; + * but it should change the rate control and + * any queued frames for the given node only. + * + * Since there's no (current) way to inform + * the driver that a channel width change has + * occured for a single node, just stub this + * out. + */ +#if 0 if (ht_state_change) ieee80211_update_chw(ic); +#endif } break; } diff --git a/sys/net80211/ieee80211_mesh.c b/sys/net80211/ieee80211_mesh.c index f4f94d1..9750a4a 100644 --- a/sys/net80211/ieee80211_mesh.c +++ b/sys/net80211/ieee80211_mesh.c @@ -2625,7 +2625,7 @@ mesh_parse_meshgate_action(struct ieee80211_node *ni, switch (*frm) { case IEEE80211_ELEMID_MESHGANN: gannie = (const struct ieee80211_meshgann_ie *) frm; - memset(ie, 0, sizeof(ie)); + memset(ie, 0, sizeof(*ie)); ie->gann_ie = gannie->gann_ie; ie->gann_len = gannie->gann_len; ie->gann_flags = gannie->gann_flags; diff --git a/sys/netinet/ip_input.c b/sys/netinet/ip_input.c index 0e559a6..555b5d0 100644 --- a/sys/netinet/ip_input.c +++ b/sys/netinet/ip_input.c @@ -1592,8 +1592,8 @@ ip_savecontrol(struct inpcb *inp, struct mbuf **mp, struct ip *ip, bintime(&bt); if (inp->inp_socket->so_options & SO_BINTIME) { - *mp = sbcreatecontrol((caddr_t) &bt, sizeof(bt), - SCM_BINTIME, SOL_SOCKET); + *mp = sbcreatecontrol((caddr_t)&bt, sizeof(bt), + SCM_BINTIME, SOL_SOCKET); if (*mp) mp = &(*mp)->m_next; } @@ -1601,20 +1601,20 @@ ip_savecontrol(struct inpcb *inp, struct mbuf **mp, struct ip *ip, struct timeval tv; bintime2timeval(&bt, &tv); - *mp = sbcreatecontrol((caddr_t) &tv, sizeof(tv), - SCM_TIMESTAMP, SOL_SOCKET); + *mp = sbcreatecontrol((caddr_t)&tv, sizeof(tv), + SCM_TIMESTAMP, SOL_SOCKET); if (*mp) mp = &(*mp)->m_next; } } if (inp->inp_flags & INP_RECVDSTADDR) { - *mp = sbcreatecontrol((caddr_t) &ip->ip_dst, + *mp = sbcreatecontrol((caddr_t)&ip->ip_dst, sizeof(struct in_addr), IP_RECVDSTADDR, IPPROTO_IP); if (*mp) mp = &(*mp)->m_next; } if (inp->inp_flags & INP_RECVTTL) { - *mp = sbcreatecontrol((caddr_t) &ip->ip_ttl, + *mp = sbcreatecontrol((caddr_t)&ip->ip_ttl, sizeof(u_char), IP_RECVTTL, IPPROTO_IP); if (*mp) mp = &(*mp)->m_next; @@ -1626,14 +1626,14 @@ ip_savecontrol(struct inpcb *inp, struct mbuf **mp, struct ip *ip, */ /* options were tossed already */ if (inp->inp_flags & INP_RECVOPTS) { - *mp = sbcreatecontrol((caddr_t) opts_deleted_above, + *mp = sbcreatecontrol((caddr_t)opts_deleted_above, sizeof(struct in_addr), IP_RECVOPTS, IPPROTO_IP); if (*mp) mp = &(*mp)->m_next; } /* ip_srcroute doesn't do what we want here, need to fix */ if (inp->inp_flags & INP_RECVRETOPTS) { - *mp = sbcreatecontrol((caddr_t) ip_srcroute(m), + *mp = sbcreatecontrol((caddr_t)ip_srcroute(m), sizeof(struct in_addr), IP_RECVRETOPTS, IPPROTO_IP); if (*mp) mp = &(*mp)->m_next; @@ -1648,32 +1648,32 @@ ip_savecontrol(struct inpcb *inp, struct mbuf **mp, struct ip *ip, struct sockaddr_dl *sdp; struct sockaddr_dl *sdl2 = &sdlbuf.sdl; - if (((ifp = m->m_pkthdr.rcvif)) - && ( ifp->if_index && (ifp->if_index <= V_if_index))) { + if ((ifp = m->m_pkthdr.rcvif) && + ifp->if_index && ifp->if_index <= V_if_index) { sdp = (struct sockaddr_dl *)ifp->if_addr->ifa_addr; /* * Change our mind and don't try copy. */ - if ((sdp->sdl_family != AF_LINK) - || (sdp->sdl_len > sizeof(sdlbuf))) { + if (sdp->sdl_family != AF_LINK || + sdp->sdl_len > sizeof(sdlbuf)) { goto makedummy; } bcopy(sdp, sdl2, sdp->sdl_len); } else { makedummy: - sdl2->sdl_len - = offsetof(struct sockaddr_dl, sdl_data[0]); + sdl2->sdl_len = + offsetof(struct sockaddr_dl, sdl_data[0]); sdl2->sdl_family = AF_LINK; sdl2->sdl_index = 0; sdl2->sdl_nlen = sdl2->sdl_alen = sdl2->sdl_slen = 0; } - *mp = sbcreatecontrol((caddr_t) sdl2, sdl2->sdl_len, - IP_RECVIF, IPPROTO_IP); + *mp = sbcreatecontrol((caddr_t)sdl2, sdl2->sdl_len, + IP_RECVIF, IPPROTO_IP); if (*mp) mp = &(*mp)->m_next; } if (inp->inp_flags & INP_RECVTOS) { - *mp = sbcreatecontrol((caddr_t) &ip->ip_tos, + *mp = sbcreatecontrol((caddr_t)&ip->ip_tos, sizeof(u_char), IP_RECVTOS, IPPROTO_IP); if (*mp) mp = &(*mp)->m_next; diff --git a/sys/netinet/tcp_lro.c b/sys/netinet/tcp_lro.c index 3718e4d..032d47c 100644 --- a/sys/netinet/tcp_lro.c +++ b/sys/netinet/tcp_lro.c @@ -333,7 +333,7 @@ tcp_lro_rx_ipv4(struct lro_ctrl *lc, struct mbuf *m, struct ip *ip4, } } else { csum = in_cksum_hdr(ip4); - if (__predict_false((csum ^ 0xffff) != 0)) { + if (__predict_false((csum) != 0)) { lc->lro_bad_csum++; return (TCP_LRO_CANNOT); } diff --git a/sys/nfsclient/nfs_krpc.c b/sys/nfsclient/nfs_krpc.c index 851b0b6..d3082d8 100644 --- a/sys/nfsclient/nfs_krpc.c +++ b/sys/nfsclient/nfs_krpc.c @@ -748,7 +748,6 @@ nfs_set_sigmask(struct thread *td, sigset_t *oldset) SIGDELSET(newset, nfs_sig_set[i]); } mtx_unlock(&p->p_sigacts->ps_mtx); - sigdeferstop(td); kern_sigprocmask(td, SIG_SETMASK, &newset, oldset, SIGPROCMASK_PROC_LOCKED); PROC_UNLOCK(p); @@ -760,7 +759,6 @@ nfs_restore_sigmask(struct thread *td, sigset_t *set) if (td == NULL) td = curthread; /* XXX */ kern_sigprocmask(td, SIG_SETMASK, set, NULL, 0); - sigallowstop(td); } /* diff --git a/sys/nfsclient/nfs_vfsops.c b/sys/nfsclient/nfs_vfsops.c index 63b5772..9cec307 100644 --- a/sys/nfsclient/nfs_vfsops.c +++ b/sys/nfsclient/nfs_vfsops.c @@ -146,7 +146,7 @@ static struct vfsops nfs_vfsops = { .vfs_unmount = nfs_unmount, .vfs_sysctl = nfs_sysctl, }; -VFS_SET(nfs_vfsops, oldnfs, VFCF_NETWORK); +VFS_SET(nfs_vfsops, oldnfs, VFCF_NETWORK | VFCF_SBDRY); /* So that loader and kldload(2) can find us, wherever we are.. */ MODULE_VERSION(oldnfs, 1); diff --git a/sys/opencrypto/xform.c b/sys/opencrypto/xform.c index 26e383c..bfb061b 100644 --- a/sys/opencrypto/xform.c +++ b/sys/opencrypto/xform.c @@ -1,8 +1,9 @@ /* $OpenBSD: xform.c,v 1.16 2001/08/28 12:20:43 ben Exp $ */ /*- * The authors of this code are John Ioannidis (ji@tla.org), - * Angelos D. Keromytis (kermit@csd.uch.gr) and - * Niels Provos (provos@physnet.uni-hamburg.de). + * Angelos D. Keromytis (kermit@csd.uch.gr), + * Niels Provos (provos@physnet.uni-hamburg.de) and + * Damien Miller (djm@mindrot.org). * * This code was written by John Ioannidis for BSD/OS in Athens, Greece, * in November 1995. @@ -15,11 +16,15 @@ * * Additional features in 1999 by Angelos D. Keromytis. * + * AES XTS implementation in 2008 by Damien Miller + * * Copyright (C) 1995, 1996, 1997, 1998, 1999 by John Ioannidis, * Angelos D. Keromytis and Niels Provos. * * Copyright (C) 2001, Angelos D. Keromytis. * + * Copyright (C) 2008, Damien Miller + * * Permission to use, copy, and modify this software with or without fee * is hereby granted, provided that this entire notice is included in * all copies of any software which is or includes a copy or diff --git a/sys/pci/ncr.c b/sys/pci/ncr.c index ead7d43..70b08c7 100644 --- a/sys/pci/ncr.c +++ b/sys/pci/ncr.c @@ -5544,7 +5544,6 @@ static void ncr_exception (ncb_p np) ** Freeze system to be able to read the messages. */ printf ("ncr: fatal error: system halted - press reset to reboot ..."); - (void) splhigh(); for (;;); #endif @@ -6397,12 +6396,8 @@ static nccb_p ncr_get_nccb (ncb_p np, u_long target, u_long lun) { lcb_p lp; - int s; nccb_p cp = NULL; - /* Keep our timeout handler out */ - s = splsoftclock(); - /* ** Lun structure available ? */ @@ -6430,12 +6425,10 @@ static nccb_p ncr_get_nccb if (cp != NULL) { if (cp->magic) { printf("%s: Bogus free cp found\n", ncr_name(np)); - splx(s); return (NULL); } cp->magic = 1; } - splx(s); return (cp); } diff --git a/sys/powerpc/include/vmparam.h b/sys/powerpc/include/vmparam.h index 8368a41..4b36d9d 100644 --- a/sys/powerpc/include/vmparam.h +++ b/sys/powerpc/include/vmparam.h @@ -121,11 +121,6 @@ #endif /* AIM/E500 */ -/* XXX max. amount of KVM to be used by buffers. */ -#ifndef VM_MAX_KERNEL_BUF -#define VM_MAX_KERNEL_BUF (SEGMENT_LENGTH * 7 / 10) -#endif - #if !defined(LOCORE) struct pmap_physseg { struct pv_entry *pvent; diff --git a/sys/security/audit/audit_bsm.c b/sys/security/audit/audit_bsm.c index b02d677..8881cea 100644 --- a/sys/security/audit/audit_bsm.c +++ b/sys/security/audit/audit_bsm.c @@ -223,9 +223,7 @@ kau_free(struct au_record *rec) } while (0) #define UPATH1_VNODE1_TOKENS do { \ - if (ARG_IS_VALID(kar, ARG_UPATH1)) { \ - UPATH1_TOKENS; \ - } \ + UPATH1_TOKENS; \ if (ARG_IS_VALID(kar, ARG_VNODE1)) { \ tok = au_to_attr32(&ar->ar_arg_vnode1); \ kau_write(rec, tok); \ diff --git a/sys/sys/buf.h b/sys/sys/buf.h index 418d6c5..672ef5a 100644 --- a/sys/sys/buf.h +++ b/sys/sys/buf.h @@ -205,7 +205,7 @@ struct buf { #define B_00000800 0x00000800 /* Available flag. */ #define B_00001000 0x00001000 /* Available flag. */ #define B_INVAL 0x00002000 /* Does not contain valid info. */ -#define B_00004000 0x00004000 /* Available flag. */ +#define B_BARRIER 0x00004000 /* Write this and all preceeding first. */ #define B_NOCACHE 0x00008000 /* Do not cache block after use. */ #define B_MALLOC 0x00010000 /* malloced b_data */ #define B_CLUSTEROK 0x00020000 /* Pagein op, so swap() can count it. */ @@ -488,6 +488,8 @@ int breadn_flags(struct vnode *, daddr_t, int, daddr_t *, int *, int, void breada(struct vnode *, daddr_t *, int *, int, struct ucred *); void bdwrite(struct buf *); void bawrite(struct buf *); +void babarrierwrite(struct buf *); +int bbarrierwrite(struct buf *); void bdirty(struct buf *); void bundirty(struct buf *); void bufstrategy(struct bufobj *, struct buf *); diff --git a/sys/sys/filedesc.h b/sys/sys/filedesc.h index 855d2b3..07cfb1f 100644 --- a/sys/sys/filedesc.h +++ b/sys/sys/filedesc.h @@ -88,7 +88,7 @@ struct filedesc_to_leader { /* * Per-process open flags. */ -#define UF_EXCLOSE 0x01 /* auto-close on exec */ +#define UF_EXCLOSE 0x01 /* auto-close on exec */ #ifdef _KERNEL diff --git a/sys/sys/mount.h b/sys/sys/mount.h index bbbc569..f73d5d7 100644 --- a/sys/sys/mount.h +++ b/sys/sys/mount.h @@ -493,6 +493,7 @@ struct ovfsconf { #define VFCF_UNICODE 0x00200000 /* stores file names as Unicode */ #define VFCF_JAIL 0x00400000 /* can be mounted from within a jail */ #define VFCF_DELEGADMIN 0x00800000 /* supports delegated administration */ +#define VFCF_SBDRY 0x01000000 /* defer stop requests */ typedef uint32_t fsctlop_t; @@ -629,30 +630,121 @@ struct vfsops { vfs_statfs_t __vfs_statfs; -#define VFS_MOUNT(MP) (*(MP)->mnt_op->vfs_mount)(MP) -#define VFS_UNMOUNT(MP, FORCE) (*(MP)->mnt_op->vfs_unmount)(MP, FORCE) -#define VFS_ROOT(MP, FLAGS, VPP) \ - (*(MP)->mnt_op->vfs_root)(MP, FLAGS, VPP) -#define VFS_QUOTACTL(MP, C, U, A) \ - (*(MP)->mnt_op->vfs_quotactl)(MP, C, U, A) -#define VFS_STATFS(MP, SBP) __vfs_statfs((MP), (SBP)) -#define VFS_SYNC(MP, WAIT) (*(MP)->mnt_op->vfs_sync)(MP, WAIT) -#define VFS_VGET(MP, INO, FLAGS, VPP) \ - (*(MP)->mnt_op->vfs_vget)(MP, INO, FLAGS, VPP) -#define VFS_FHTOVP(MP, FIDP, FLAGS, VPP) \ - (*(MP)->mnt_op->vfs_fhtovp)(MP, FIDP, FLAGS, VPP) -#define VFS_CHECKEXP(MP, NAM, EXFLG, CRED, NUMSEC, SEC) \ - (*(MP)->mnt_op->vfs_checkexp)(MP, NAM, EXFLG, CRED, NUMSEC, SEC) -#define VFS_EXTATTRCTL(MP, C, FN, NS, N) \ - (*(MP)->mnt_op->vfs_extattrctl)(MP, C, FN, NS, N) -#define VFS_SYSCTL(MP, OP, REQ) \ - (*(MP)->mnt_op->vfs_sysctl)(MP, OP, REQ) -#define VFS_SUSP_CLEAN(MP) \ - ({if (*(MP)->mnt_op->vfs_susp_clean != NULL) \ - (*(MP)->mnt_op->vfs_susp_clean)(MP); }) -#define VFS_RECLAIM_LOWERVP(MP, VP) \ - ({if (*(MP)->mnt_op->vfs_reclaim_lowervp != NULL) \ - (*(MP)->mnt_op->vfs_reclaim_lowervp)((MP), (VP)); }) +#define VFS_PROLOGUE(MP) do { \ + int _enable_stops; \ + \ + _enable_stops = ((MP) != NULL && \ + ((MP)->mnt_vfc->vfc_flags & VFCF_SBDRY) && sigdeferstop()) + +#define VFS_EPILOGUE(MP) \ + if (_enable_stops) \ + sigallowstop(); \ +} while (0) + +#define VFS_MOUNT(MP) ({ \ + int _rc; \ + \ + VFS_PROLOGUE(MP); \ + _rc = (*(MP)->mnt_op->vfs_mount)(MP); \ + VFS_EPILOGUE(MP); \ + _rc; }) + +#define VFS_UNMOUNT(MP, FORCE) ({ \ + int _rc; \ + \ + VFS_PROLOGUE(MP); \ + _rc = (*(MP)->mnt_op->vfs_unmount)(MP, FORCE); \ + VFS_EPILOGUE(MP); \ + _rc; }) + +#define VFS_ROOT(MP, FLAGS, VPP) ({ \ + int _rc; \ + \ + VFS_PROLOGUE(MP); \ + _rc = (*(MP)->mnt_op->vfs_root)(MP, FLAGS, VPP); \ + VFS_EPILOGUE(MP); \ + _rc; }) + +#define VFS_QUOTACTL(MP, C, U, A) ({ \ + int _rc; \ + \ + VFS_PROLOGUE(MP); \ + _rc = (*(MP)->mnt_op->vfs_quotactl)(MP, C, U, A); \ + VFS_EPILOGUE(MP); \ + _rc; }) + +#define VFS_STATFS(MP, SBP) ({ \ + int _rc; \ + \ + VFS_PROLOGUE(MP); \ + _rc = __vfs_statfs((MP), (SBP)); \ + VFS_EPILOGUE(MP); \ + _rc; }) + +#define VFS_SYNC(MP, WAIT) ({ \ + int _rc; \ + \ + VFS_PROLOGUE(MP); \ + _rc = (*(MP)->mnt_op->vfs_sync)(MP, WAIT); \ + VFS_EPILOGUE(MP); \ + _rc; }) + +#define VFS_VGET(MP, INO, FLAGS, VPP) ({ \ + int _rc; \ + \ + VFS_PROLOGUE(MP); \ + _rc = (*(MP)->mnt_op->vfs_vget)(MP, INO, FLAGS, VPP); \ + VFS_EPILOGUE(MP); \ + _rc; }) + +#define VFS_FHTOVP(MP, FIDP, FLAGS, VPP) ({ \ + int _rc; \ + \ + VFS_PROLOGUE(MP); \ + _rc = (*(MP)->mnt_op->vfs_fhtovp)(MP, FIDP, FLAGS, VPP); \ + VFS_EPILOGUE(MP); \ + _rc; }) + +#define VFS_CHECKEXP(MP, NAM, EXFLG, CRED, NUMSEC, SEC) ({ \ + int _rc; \ + \ + VFS_PROLOGUE(MP); \ + _rc = (*(MP)->mnt_op->vfs_checkexp)(MP, NAM, EXFLG, CRED, NUMSEC,\ + SEC); \ + VFS_EPILOGUE(MP); \ + _rc; }) + +#define VFS_EXTATTRCTL(MP, C, FN, NS, N) ({ \ + int _rc; \ + \ + VFS_PROLOGUE(MP); \ + _rc = (*(MP)->mnt_op->vfs_extattrctl)(MP, C, FN, NS, N); \ + VFS_EPILOGUE(MP); \ + _rc; }) + +#define VFS_SYSCTL(MP, OP, REQ) ({ \ + int _rc; \ + \ + VFS_PROLOGUE(MP); \ + _rc = (*(MP)->mnt_op->vfs_sysctl)(MP, OP, REQ); \ + VFS_EPILOGUE(MP); \ + _rc; }) + +#define VFS_SUSP_CLEAN(MP) do { \ + if (*(MP)->mnt_op->vfs_susp_clean != NULL) { \ + VFS_PROLOGUE(MP); \ + (*(MP)->mnt_op->vfs_susp_clean)(MP); \ + VFS_EPILOGUE(MP); \ + } \ +} while (0) + +#define VFS_RECLAIM_LOWERVP(MP, VP) do { \ + if (*(MP)->mnt_op->vfs_reclaim_lowervp != NULL) { \ + VFS_PROLOGUE(MP); \ + (*(MP)->mnt_op->vfs_reclaim_lowervp)((MP), (VP)); \ + VFS_EPILOGUE(MP); \ + } \ +} while (0) #define VFS_KNOTE_LOCKED(vp, hint) do \ { \ diff --git a/sys/sys/namei.h b/sys/sys/namei.h index 04e7b59..3b43916 100644 --- a/sys/sys/namei.h +++ b/sys/sys/namei.h @@ -145,7 +145,7 @@ struct nameidata { #define NOCROSSMOUNT 0x00400000 /* do not cross mount points */ #define NOMACCHECK 0x00800000 /* do not perform MAC checks */ #define AUDITVNODE1 0x04000000 /* audit the looked up vnode information */ -#define AUDITVNODE2 0x08000000 /* audit the looked up vnode information */ +#define AUDITVNODE2 0x08000000 /* audit the looked up vnode information */ #define TRAILINGSLASH 0x10000000 /* path ended in a slash */ #define NOCAPCHECK 0x20000000 /* do not perform capability checks */ #define PARAMASK 0x3ffffe00 /* mask of parameter descriptors */ diff --git a/sys/sys/protosw.h b/sys/sys/protosw.h index a74771e..78d6e06 100644 --- a/sys/sys/protosw.h +++ b/sys/sys/protosw.h @@ -203,15 +203,15 @@ struct pr_usrreqs { int (*pru_peeraddr)(struct socket *so, struct sockaddr **nam); int (*pru_rcvd)(struct socket *so, int flags); int (*pru_rcvoob)(struct socket *so, struct mbuf *m, int flags); - int (*pru_send)(struct socket *so, int flags, struct mbuf *m, + int (*pru_send)(struct socket *so, int flags, struct mbuf *m, struct sockaddr *addr, struct mbuf *control, struct thread *td); #define PRUS_OOB 0x1 #define PRUS_EOF 0x2 #define PRUS_MORETOCOME 0x4 int (*pru_sense)(struct socket *so, struct stat *sb); - int (*pru_shutdown)(struct socket *so); - int (*pru_flush)(struct socket *so, int direction); + int (*pru_shutdown)(struct socket *so); + int (*pru_flush)(struct socket *so, int direction); int (*pru_sockaddr)(struct socket *so, struct sockaddr **nam); int (*pru_sosend)(struct socket *so, struct sockaddr *addr, struct uio *uio, struct mbuf *top, struct mbuf *control, @@ -266,7 +266,7 @@ int pru_sopoll_notsupp(struct socket *so, int events, struct ucred *cred, */ #define PRC_IFDOWN 0 /* interface transition */ #define PRC_ROUTEDEAD 1 /* select new route if possible ??? */ -#define PRC_IFUP 2 /* interface has come back up */ +#define PRC_IFUP 2 /* interface has come back up */ #define PRC_QUENCH2 3 /* DEC congestion bit says slow down */ #define PRC_QUENCH 4 /* some one said to slow down */ #define PRC_MSGSIZE 5 /* message size forced drop */ diff --git a/sys/sys/signalvar.h b/sys/sys/signalvar.h index 91655b2..fcf25ad 100644 --- a/sys/sys/signalvar.h +++ b/sys/sys/signalvar.h @@ -328,8 +328,8 @@ extern struct mtx sigio_lock; #define SIGPROCMASK_PS_LOCKED 0x0004 int cursig(struct thread *td, int stop_allowed); -void sigdeferstop(struct thread *td); -void sigallowstop(struct thread *td); +int sigdeferstop(void); +void sigallowstop(void); void execsigs(struct proc *p); void gsignal(int pgid, int sig, ksiginfo_t *ksi); void killproc(struct proc *p, char *why); diff --git a/sys/sys/systm.h b/sys/sys/systm.h index dd96d70..611d014 100644 --- a/sys/sys/systm.h +++ b/sys/sys/systm.h @@ -324,19 +324,12 @@ caddr_t kern_timeout_callwheel_alloc(caddr_t v); void kern_timeout_callwheel_init(void); /* Stubs for obsolete functions that used to be for interrupt management */ -static __inline void spl0(void) { return; } static __inline intrmask_t splbio(void) { return 0; } static __inline intrmask_t splcam(void) { return 0; } static __inline intrmask_t splclock(void) { return 0; } static __inline intrmask_t splhigh(void) { return 0; } static __inline intrmask_t splimp(void) { return 0; } static __inline intrmask_t splnet(void) { return 0; } -static __inline intrmask_t splsoftcam(void) { return 0; } -static __inline intrmask_t splsoftclock(void) { return 0; } -static __inline intrmask_t splsofttty(void) { return 0; } -static __inline intrmask_t splsoftvm(void) { return 0; } -static __inline intrmask_t splsofttq(void) { return 0; } -static __inline intrmask_t splstatclock(void) { return 0; } static __inline intrmask_t spltty(void) { return 0; } static __inline intrmask_t splvm(void) { return 0; } static __inline void splx(intrmask_t ipl __unused) { return; } diff --git a/sys/tools/vnode_if.awk b/sys/tools/vnode_if.awk index c991458..2347004 100644 --- a/sys/tools/vnode_if.awk +++ b/sys/tools/vnode_if.awk @@ -172,6 +172,7 @@ if (cfile) { "#include <sys/kernel.h>\n" \ "#include <sys/mount.h>\n" \ "#include <sys/sdt.h>\n" \ + "#include <sys/signalvar.h>\n" \ "#include <sys/systm.h>\n" \ "#include <sys/vnode.h>\n" \ "\n" \ @@ -365,10 +366,12 @@ while ((getline < srcfile) > 0) { add_debug_code(name, args[i], "Entry", "\t"); printc("\tKTR_START" ctrstr); add_pre(name); + printc("\tVFS_PROLOGUE(a->a_" args[0]"->v_mount);") printc("\tif (vop->"name" != NULL)") printc("\t\trc = vop->"name"(a);") printc("\telse") printc("\t\trc = vop->vop_bypass(&a->a_gen);") + printc("\tVFS_EPILOGUE(a->a_" args[0]"->v_mount);") printc("\tSDT_PROBE(vfs, vop, " name ", return, a->a_" args[0] ", a, rc, 0, 0);\n"); printc("\tif (rc == 0) {"); for (i = 0; i < numargs; ++i) diff --git a/sys/ufs/ffs/ffs_alloc.c b/sys/ufs/ffs/ffs_alloc.c index d462cbb..abe4073 100644 --- a/sys/ufs/ffs/ffs_alloc.c +++ b/sys/ufs/ffs/ffs_alloc.c @@ -1861,7 +1861,6 @@ gotit: /* * Check to see if we need to initialize more inodes. */ - ibp = NULL; if (fs->fs_magic == FS_UFS2_MAGIC && ipref + INOPB(fs) > cgp->cg_initediblk && cgp->cg_initediblk < cgp->cg_niblk) { @@ -1874,6 +1873,16 @@ gotit: dp2->di_gen = arc4random() / 2 + 1; dp2++; } + /* + * Rather than adding a soft updates dependency to ensure + * that the new inode block is written before it is claimed + * by the cylinder group map, we just do a barrier write + * here. The barrier write will ensure that the inode block + * gets written before the updated cylinder group map can be + * written. The barrier write should only slow down bulk + * loading of newly created filesystems. + */ + babarrierwrite(ibp); cgp->cg_initediblk += INOPB(fs); } UFS_LOCK(ump); @@ -1892,8 +1901,6 @@ gotit: if (DOINGSOFTDEP(ITOV(ip))) softdep_setup_inomapdep(bp, ip, cg * fs->fs_ipg + ipref, mode); bdwrite(bp); - if (ibp != NULL) - bawrite(ibp); return ((ino_t)(cg * fs->fs_ipg + ipref)); } diff --git a/sys/vm/vm_kern.c b/sys/vm/vm_kern.c index 4d789ce..ad9aa0d 100644 --- a/sys/vm/vm_kern.c +++ b/sys/vm/vm_kern.c @@ -98,7 +98,7 @@ SYSCTL_ULONG(_vm, OID_AUTO, min_kernel_address, CTLFLAG_RD, NULL, VM_MIN_KERNEL_ADDRESS, "Min kernel address"); SYSCTL_ULONG(_vm, OID_AUTO, max_kernel_address, CTLFLAG_RD, -#ifdef __sparc64__ +#if defined(__arm__) || defined(__sparc64__) &vm_max_kernel_address, 0, #else NULL, VM_MAX_KERNEL_ADDRESS, diff --git a/sys/x86/include/elf.h b/sys/x86/include/elf.h new file mode 100644 index 0000000..cde395b --- /dev/null +++ b/sys/x86/include/elf.h @@ -0,0 +1,215 @@ +/*- + * Copyright (c) 1996-1997 John D. Polstra. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _MACHINE_ELF_H_ +#define _MACHINE_ELF_H_ 1 + +#if defined(__i386__) || defined(_MACHINE_ELF_WANT_32BIT) + +/* + * ELF definitions for the i386 architecture. + */ + +#include <sys/elf32.h> /* Definitions common to all 32 bit architectures. */ +#if defined(__ELF_WORD_SIZE) && __ELF_WORD_SIZE == 64 +#include <sys/elf64.h> /* Definitions common to all 64 bit architectures. */ +#endif + +#ifndef __ELF_WORD_SIZE +#define __ELF_WORD_SIZE 32 /* Used by <sys/elf_generic.h> */ +#endif + +#include <sys/elf_generic.h> + +#define ELF_ARCH EM_386 + +#define ELF_MACHINE_OK(x) ((x) == EM_386 || (x) == EM_486) + +/* + * Auxiliary vector entries for passing information to the interpreter. + * + * The i386 supplement to the SVR4 ABI specification names this "auxv_t", + * but POSIX lays claim to all symbols ending with "_t". + */ + +typedef struct { /* Auxiliary vector entry on initial stack */ + int a_type; /* Entry type. */ + union { + long a_val; /* Integer value. */ + void *a_ptr; /* Address. */ + void (*a_fcn)(void); /* Function pointer (not used). */ + } a_un; +} Elf32_Auxinfo; + +#if __ELF_WORD_SIZE == 64 +/* Fake for amd64 loader support */ +typedef struct { + int fake; +} Elf64_Auxinfo; +#endif + +__ElfType(Auxinfo); + +/* Values for a_type. */ +#define AT_NULL 0 /* Terminates the vector. */ +#define AT_IGNORE 1 /* Ignored entry. */ +#define AT_EXECFD 2 /* File descriptor of program to load. */ +#define AT_PHDR 3 /* Program header of program already loaded. */ +#define AT_PHENT 4 /* Size of each program header entry. */ +#define AT_PHNUM 5 /* Number of program header entries. */ +#define AT_PAGESZ 6 /* Page size in bytes. */ +#define AT_BASE 7 /* Interpreter's base address. */ +#define AT_FLAGS 8 /* Flags (unused for i386). */ +#define AT_ENTRY 9 /* Where interpreter should transfer control. */ +#define AT_NOTELF 10 /* Program is not ELF ?? */ +#define AT_UID 11 /* Real uid. */ +#define AT_EUID 12 /* Effective uid. */ +#define AT_GID 13 /* Real gid. */ +#define AT_EGID 14 /* Effective gid. */ +#define AT_EXECPATH 15 /* Path to the executable. */ +#define AT_CANARY 16 /* Canary for SSP. */ +#define AT_CANARYLEN 17 /* Length of the canary. */ +#define AT_OSRELDATE 18 /* OSRELDATE. */ +#define AT_NCPUS 19 /* Number of CPUs. */ +#define AT_PAGESIZES 20 /* Pagesizes. */ +#define AT_PAGESIZESLEN 21 /* Number of pagesizes. */ +#define AT_TIMEKEEP 22 /* Pointer to timehands. */ +#define AT_STACKPROT 23 /* Initial stack protection. */ + +#define AT_COUNT 24 /* Count of defined aux entry types. */ + +/* + * Relocation types. + */ + +#define R_386_COUNT 38 /* Count of defined relocation types. */ + +/* Define "machine" characteristics */ +#define ELF_TARG_CLASS ELFCLASS32 +#define ELF_TARG_DATA ELFDATA2LSB +#define ELF_TARG_MACH EM_386 +#define ELF_TARG_VER 1 + +#define ET_DYN_LOAD_ADDR 0x01001000 + +#elif defined(__amd64__) + +/* + * ELF definitions for the AMD64 architecture. + */ + +#ifndef __ELF_WORD_SIZE +#define __ELF_WORD_SIZE 64 /* Used by <sys/elf_generic.h> */ +#endif +#include <sys/elf32.h> /* Definitions common to all 32 bit architectures. */ +#include <sys/elf64.h> /* Definitions common to all 64 bit architectures. */ +#include <sys/elf_generic.h> + +#define ELF_ARCH EM_X86_64 +#define ELF_ARCH32 EM_386 + +#define ELF_MACHINE_OK(x) ((x) == EM_X86_64) + +/* + * Auxiliary vector entries for passing information to the interpreter. + * + * The i386 supplement to the SVR4 ABI specification names this "auxv_t", + * but POSIX lays claim to all symbols ending with "_t". + */ +typedef struct { /* Auxiliary vector entry on initial stack */ + int a_type; /* Entry type. */ + union { + int a_val; /* Integer value. */ + } a_un; +} Elf32_Auxinfo; + + +typedef struct { /* Auxiliary vector entry on initial stack */ + long a_type; /* Entry type. */ + union { + long a_val; /* Integer value. */ + void *a_ptr; /* Address. */ + void (*a_fcn)(void); /* Function pointer (not used). */ + } a_un; +} Elf64_Auxinfo; + +__ElfType(Auxinfo); + +/* Values for a_type. */ +#define AT_NULL 0 /* Terminates the vector. */ +#define AT_IGNORE 1 /* Ignored entry. */ +#define AT_EXECFD 2 /* File descriptor of program to load. */ +#define AT_PHDR 3 /* Program header of program already loaded. */ +#define AT_PHENT 4 /* Size of each program header entry. */ +#define AT_PHNUM 5 /* Number of program header entries. */ +#define AT_PAGESZ 6 /* Page size in bytes. */ +#define AT_BASE 7 /* Interpreter's base address. */ +#define AT_FLAGS 8 /* Flags (unused for i386). */ +#define AT_ENTRY 9 /* Where interpreter should transfer control. */ +#define AT_NOTELF 10 /* Program is not ELF ?? */ +#define AT_UID 11 /* Real uid. */ +#define AT_EUID 12 /* Effective uid. */ +#define AT_GID 13 /* Real gid. */ +#define AT_EGID 14 /* Effective gid. */ +#define AT_EXECPATH 15 /* Path to the executable. */ +#define AT_CANARY 16 /* Canary for SSP */ +#define AT_CANARYLEN 17 /* Length of the canary. */ +#define AT_OSRELDATE 18 /* OSRELDATE. */ +#define AT_NCPUS 19 /* Number of CPUs. */ +#define AT_PAGESIZES 20 /* Pagesizes. */ +#define AT_PAGESIZESLEN 21 /* Number of pagesizes. */ +#define AT_TIMEKEEP 22 /* Pointer to timehands. */ +#define AT_STACKPROT 23 /* Initial stack protection. */ + +#define AT_COUNT 24 /* Count of defined aux entry types. */ + +/* + * Relocation types. + */ + +#define R_X86_64_COUNT 24 /* Count of defined relocation types. */ + +/* Define "machine" characteristics */ +#if __ELF_WORD_SIZE == 32 +#define ELF_TARG_CLASS ELFCLASS32 +#else +#define ELF_TARG_CLASS ELFCLASS64 +#endif +#define ELF_TARG_DATA ELFDATA2LSB +#define ELF_TARG_MACH EM_X86_64 +#define ELF_TARG_VER 1 + +#if __ELF_WORD_SIZE == 32 +#define ET_DYN_LOAD_ADDR 0x01001000 +#else +#define ET_DYN_LOAD_ADDR 0x01021000 +#endif + +#endif /* __i386__, __amd64__ */ + +#endif /* !_MACHINE_ELF_H_ */ diff --git a/sys/x86/include/frame.h b/sys/x86/include/frame.h new file mode 100644 index 0000000..a32ef7c --- /dev/null +++ b/sys/x86/include/frame.h @@ -0,0 +1,148 @@ +/*- + * Copyright (c) 2003 Peter Wemm. + * Copyright (c) 1990 The Regents of the University of California. + * All rights reserved. + * + * This code is derived from software contributed to Berkeley by + * William Jolitz. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * from: @(#)frame.h 5.2 (Berkeley) 1/18/91 + * $FreeBSD$ + */ + +#ifndef _MACHINE_FRAME_H_ +#define _MACHINE_FRAME_H_ 1 + +/* + * System stack frames. + */ + +#ifdef __i386__ +/* + * Exception/Trap Stack Frame + */ + +struct trapframe { + int tf_fs; + int tf_es; + int tf_ds; + int tf_edi; + int tf_esi; + int tf_ebp; + int tf_isp; + int tf_ebx; + int tf_edx; + int tf_ecx; + int tf_eax; + int tf_trapno; + /* below portion defined in 386 hardware */ + int tf_err; + int tf_eip; + int tf_cs; + int tf_eflags; + /* below only when crossing rings (e.g. user to kernel) */ + int tf_esp; + int tf_ss; +}; + +/* Superset of trap frame, for traps from virtual-8086 mode */ + +struct trapframe_vm86 { + int tf_fs; + int tf_es; + int tf_ds; + int tf_edi; + int tf_esi; + int tf_ebp; + int tf_isp; + int tf_ebx; + int tf_edx; + int tf_ecx; + int tf_eax; + int tf_trapno; + /* below portion defined in 386 hardware */ + int tf_err; + int tf_eip; + int tf_cs; + int tf_eflags; + /* below only when crossing rings (e.g. user to kernel) */ + int tf_esp; + int tf_ss; + /* below only when switching out of VM86 mode */ + int tf_vm86_es; + int tf_vm86_ds; + int tf_vm86_fs; + int tf_vm86_gs; +}; +#endif /* __i386__ */ + +#ifdef __amd64__ +/* + * Exception/Trap Stack Frame + * + * The ordering of this is specifically so that we can take first 6 + * the syscall arguments directly from the beginning of the frame. + */ + +struct trapframe { + register_t tf_rdi; + register_t tf_rsi; + register_t tf_rdx; + register_t tf_rcx; + register_t tf_r8; + register_t tf_r9; + register_t tf_rax; + register_t tf_rbx; + register_t tf_rbp; + register_t tf_r10; + register_t tf_r11; + register_t tf_r12; + register_t tf_r13; + register_t tf_r14; + register_t tf_r15; + uint32_t tf_trapno; + uint16_t tf_fs; + uint16_t tf_gs; + register_t tf_addr; + uint32_t tf_flags; + uint16_t tf_es; + uint16_t tf_ds; + /* below portion defined in hardware */ + register_t tf_err; + register_t tf_rip; + register_t tf_cs; + register_t tf_rflags; + register_t tf_rsp; + register_t tf_ss; +}; + +#define TF_HASSEGS 0x1 +#define TF_HASBASES 0x2 +#define TF_HASFPXSTATE 0x4 +#endif /* __amd64__ */ + +#endif /* _MACHINE_FRAME_H_ */ diff --git a/sys/x86/include/sigframe.h b/sys/x86/include/sigframe.h new file mode 100644 index 0000000..972a78e --- /dev/null +++ b/sys/x86/include/sigframe.h @@ -0,0 +1,72 @@ +/*- + * Copyright (c) 1999 Marcel Moolenaar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer + * in this position and unchanged. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _X86_SIGFRAME_H_ +#define _X86_SIGFRAME_H_ + +/* + * Signal frames, arguments passed to application signal handlers. + */ + +#ifdef __i386__ +struct sigframe { + /* + * The first four members may be used by applications. + * + * NOTE: The 4th argument is undocumented, ill commented + * on and seems to be somewhat BSD "standard". Handlers + * installed with sigvec may be using it. + */ + register_t sf_signum; + register_t sf_siginfo; /* code or pointer to sf_si */ + register_t sf_ucontext; /* points to sf_uc */ + register_t sf_addr; /* undocumented 4th arg */ + + union { + __siginfohandler_t *sf_action; + __sighandler_t *sf_handler; + } sf_ahu; + ucontext_t sf_uc; /* = *sf_ucontext */ + siginfo_t sf_si; /* = *sf_siginfo (SA_SIGINFO case) */ +}; +#endif /* __i386__ */ + +#ifdef __amd64__ +struct sigframe { + union { + __siginfohandler_t *sf_action; + __sighandler_t *sf_handler; + } sf_ahu; + ucontext_t sf_uc; /* = *sf_ucontext */ + siginfo_t sf_si; /* = *sf_siginfo (SA_SIGINFO case) */ +}; +#endif /* __amd64__ */ + +#endif /* _X86_SIGFRAME_H_ */ diff --git a/sys/x86/include/signal.h b/sys/x86/include/signal.h new file mode 100644 index 0000000..dee908f --- /dev/null +++ b/sys/x86/include/signal.h @@ -0,0 +1,167 @@ +/*- + * Copyright (c) 1986, 1989, 1991, 1993 + * The Regents of the University of California. All rights reserved. + * Copyright (c) 2003 Peter Wemm. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)signal.h 8.1 (Berkeley) 6/11/93 + * $FreeBSD$ + */ + +#ifndef _X86_SIGNAL_H +#define _X86_SIGNAL_H 1 + +/* + * Machine-dependent signal definitions + */ + +#include <sys/cdefs.h> +#include <sys/_sigset.h> + +#if __BSD_VISIBLE +#include <machine/trap.h> /* codes for SIGILL, SIGFPE */ +#endif + +#ifdef __i386__ +typedef int sig_atomic_t; + +#if __BSD_VISIBLE +struct sigcontext { + struct __sigset sc_mask; /* signal mask to restore */ + int sc_onstack; /* sigstack state to restore */ + int sc_gs; /* machine state (struct trapframe) */ + int sc_fs; + int sc_es; + int sc_ds; + int sc_edi; + int sc_esi; + int sc_ebp; + int sc_isp; + int sc_ebx; + int sc_edx; + int sc_ecx; + int sc_eax; + int sc_trapno; + int sc_err; + int sc_eip; + int sc_cs; + int sc_efl; + int sc_esp; + int sc_ss; + int sc_len; /* sizeof(mcontext_t) */ + /* + * See <machine/ucontext.h> and <machine/npx.h> for + * the following fields. + */ + int sc_fpformat; + int sc_ownedfp; + int sc_flags; + int sc_fpstate[128] __aligned(16); + + int sc_fsbase; + int sc_gsbase; + + int sc_xfpustate; + int sc_xfpustate_len; + + int sc_spare2[4]; +}; + +#define sc_sp sc_esp +#define sc_fp sc_ebp +#define sc_pc sc_eip +#define sc_ps sc_efl +#define sc_eflags sc_efl + +#endif /* __BSD_VISIBLE */ +#endif /* __i386__ */ + +#ifdef __amd64__ +typedef long sig_atomic_t; + +#if __BSD_VISIBLE +/* + * Information pushed on stack when a signal is delivered. + * This is used by the kernel to restore state following + * execution of the signal handler. It is also made available + * to the handler to allow it to restore state properly if + * a non-standard exit is performed. + * + * The sequence of the fields/registers after sc_mask in struct + * sigcontext must match those in mcontext_t and struct trapframe. + */ +struct sigcontext { + struct __sigset sc_mask; /* signal mask to restore */ + long sc_onstack; /* sigstack state to restore */ + long sc_rdi; /* machine state (struct trapframe) */ + long sc_rsi; + long sc_rdx; + long sc_rcx; + long sc_r8; + long sc_r9; + long sc_rax; + long sc_rbx; + long sc_rbp; + long sc_r10; + long sc_r11; + long sc_r12; + long sc_r13; + long sc_r14; + long sc_r15; + int sc_trapno; + short sc_fs; + short sc_gs; + long sc_addr; + int sc_flags; + short sc_es; + short sc_ds; + long sc_err; + long sc_rip; + long sc_cs; + long sc_rflags; + long sc_rsp; + long sc_ss; + long sc_len; /* sizeof(mcontext_t) */ + /* + * See <machine/ucontext.h> and <machine/fpu.h> for the following + * fields. + */ + long sc_fpformat; + long sc_ownedfp; + long sc_fpstate[64] __aligned(16); + + long sc_fsbase; + long sc_gsbase; + + long sc_xfpustate; + long sc_xfpustate_len; + + long sc_spare[4]; +}; +#endif /* __BSD_VISIBLE */ +#endif /* __amd64__ */ + +#endif diff --git a/sys/x86/include/ucontext.h b/sys/x86/include/ucontext.h new file mode 100644 index 0000000..2173efd --- /dev/null +++ b/sys/x86/include/ucontext.h @@ -0,0 +1,165 @@ +/*- + * Copyright (c) 2003 Peter Wemm + * Copyright (c) 1999 Marcel Moolenaar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer + * in this position and unchanged. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _X86_UCONTEXT_H_ +#define _X86_UCONTEXT_H_ + +#ifdef __i386__ +/* Keep _MC_* values similar to amd64 */ +#define _MC_HASSEGS 0x1 +#define _MC_HASBASES 0x2 +#define _MC_HASFPXSTATE 0x4 +#define _MC_FLAG_MASK (_MC_HASSEGS | _MC_HASBASES | _MC_HASFPXSTATE) + +typedef struct __mcontext { + /* + * The definition of mcontext_t must match the layout of + * struct sigcontext after the sc_mask member. This is so + * that we can support sigcontext and ucontext_t at the same + * time. + */ + __register_t mc_onstack; /* XXX - sigcontext compat. */ + __register_t mc_gs; /* machine state (struct trapframe) */ + __register_t mc_fs; + __register_t mc_es; + __register_t mc_ds; + __register_t mc_edi; + __register_t mc_esi; + __register_t mc_ebp; + __register_t mc_isp; + __register_t mc_ebx; + __register_t mc_edx; + __register_t mc_ecx; + __register_t mc_eax; + __register_t mc_trapno; + __register_t mc_err; + __register_t mc_eip; + __register_t mc_cs; + __register_t mc_eflags; + __register_t mc_esp; + __register_t mc_ss; + + int mc_len; /* sizeof(mcontext_t) */ +#define _MC_FPFMT_NODEV 0x10000 /* device not present or configured */ +#define _MC_FPFMT_387 0x10001 +#define _MC_FPFMT_XMM 0x10002 + int mc_fpformat; +#define _MC_FPOWNED_NONE 0x20000 /* FP state not used */ +#define _MC_FPOWNED_FPU 0x20001 /* FP state came from FPU */ +#define _MC_FPOWNED_PCB 0x20002 /* FP state came from PCB */ + int mc_ownedfp; + __register_t mc_flags; + /* + * See <machine/npx.h> for the internals of mc_fpstate[]. + */ + int mc_fpstate[128] __aligned(16); + + __register_t mc_fsbase; + __register_t mc_gsbase; + + __register_t mc_xfpustate; + __register_t mc_xfpustate_len; + + int mc_spare2[4]; +} mcontext_t; +#endif /* __i386__ */ + +#ifdef __amd64__ +/* + * mc_trapno bits. Shall be in sync with TF_XXX. + */ +#define _MC_HASSEGS 0x1 +#define _MC_HASBASES 0x2 +#define _MC_HASFPXSTATE 0x4 +#define _MC_FLAG_MASK (_MC_HASSEGS | _MC_HASBASES | _MC_HASFPXSTATE) + +typedef struct __mcontext { + /* + * The definition of mcontext_t must match the layout of + * struct sigcontext after the sc_mask member. This is so + * that we can support sigcontext and ucontext_t at the same + * time. + */ + __register_t mc_onstack; /* XXX - sigcontext compat. */ + __register_t mc_rdi; /* machine state (struct trapframe) */ + __register_t mc_rsi; + __register_t mc_rdx; + __register_t mc_rcx; + __register_t mc_r8; + __register_t mc_r9; + __register_t mc_rax; + __register_t mc_rbx; + __register_t mc_rbp; + __register_t mc_r10; + __register_t mc_r11; + __register_t mc_r12; + __register_t mc_r13; + __register_t mc_r14; + __register_t mc_r15; + __uint32_t mc_trapno; + __uint16_t mc_fs; + __uint16_t mc_gs; + __register_t mc_addr; + __uint32_t mc_flags; + __uint16_t mc_es; + __uint16_t mc_ds; + __register_t mc_err; + __register_t mc_rip; + __register_t mc_cs; + __register_t mc_rflags; + __register_t mc_rsp; + __register_t mc_ss; + + long mc_len; /* sizeof(mcontext_t) */ + +#define _MC_FPFMT_NODEV 0x10000 /* device not present or configured */ +#define _MC_FPFMT_XMM 0x10002 + long mc_fpformat; +#define _MC_FPOWNED_NONE 0x20000 /* FP state not used */ +#define _MC_FPOWNED_FPU 0x20001 /* FP state came from FPU */ +#define _MC_FPOWNED_PCB 0x20002 /* FP state came from PCB */ + long mc_ownedfp; + /* + * See <machine/fpu.h> for the internals of mc_fpstate[]. + */ + long mc_fpstate[64] __aligned(16); + + __register_t mc_fsbase; + __register_t mc_gsbase; + + __register_t mc_xfpustate; + __register_t mc_xfpustate_len; + + long mc_spare[4]; +} mcontext_t; +#endif /* __amd64__ */ + +#endif /* !_X86_UCONTEXT_H_ */ diff --git a/sys/x86/isa/atrtc.c b/sys/x86/isa/atrtc.c index 2980098..c6a6f8c 100644 --- a/sys/x86/isa/atrtc.c +++ b/sys/x86/isa/atrtc.c @@ -38,6 +38,7 @@ __FBSDID("$FreeBSD$"); #include <sys/clock.h> #include <sys/lock.h> #include <sys/mutex.h> +#include <sys/kdb.h> #include <sys/kernel.h> #include <sys/module.h> #include <sys/proc.h> @@ -52,8 +53,8 @@ __FBSDID("$FreeBSD$"); #include <machine/intr_machdep.h> #include "clock_if.h" -#define RTC_LOCK mtx_lock_spin(&clock_lock) -#define RTC_UNLOCK mtx_unlock_spin(&clock_lock) +#define RTC_LOCK do { if (!kdb_active) mtx_lock_spin(&clock_lock); } while (0) +#define RTC_UNLOCK do { if (!kdb_active) mtx_unlock_spin(&clock_lock); } while (0) int atrtcclock_disable = 0; @@ -328,7 +329,6 @@ static int atrtc_gettime(device_t dev, struct timespec *ts) { struct clocktime ct; - int s; /* Look if we have a RTC present and the time is valid */ if (!(rtcin(RTC_STATUSD) & RTCSD_PWR)) { @@ -336,13 +336,16 @@ atrtc_gettime(device_t dev, struct timespec *ts) return (EINVAL); } - /* wait for time update to complete */ - /* If RTCSA_TUP is zero, we have at least 244us before next update */ - s = splhigh(); - while (rtcin(RTC_STATUSA) & RTCSA_TUP) { - splx(s); - s = splhigh(); - } + /* + * wait for time update to complete + * If RTCSA_TUP is zero, we have at least 244us before next update. + * This is fast enough on most hardware, but a refinement would be + * to make sure that no more than 240us pass after we start reading, + * and try again if so. + */ + while (rtcin(RTC_STATUSA) & RTCSA_TUP) + continue; + critical_enter(); ct.nsec = 0; ct.sec = readrtc(RTC_SEC); ct.min = readrtc(RTC_MIN); @@ -356,6 +359,7 @@ atrtc_gettime(device_t dev, struct timespec *ts) #else ct.year += 2000; #endif + critical_exit(); /* Set dow = -1 because some clocks don't set it correctly. */ ct.dow = -1; return (clock_ct_to_ts(&ct, ts)); diff --git a/sys/x86/isa/clock.c b/sys/x86/isa/clock.c index a74c11f..232c913 100644 --- a/sys/x86/isa/clock.c +++ b/sys/x86/isa/clock.c @@ -125,6 +125,8 @@ struct attimer_softc { static struct attimer_softc *attimer_sc = NULL; static int timer0_period = -2; +static int timer0_mode = 0xffff; +static int timer0_last = 0xffff; /* Values for timerX_state: */ #define RELEASED 0 @@ -404,7 +406,7 @@ DELAY(int n) static void set_i8254_freq(int mode, uint32_t period) { - int new_count; + int new_count, new_mode; mtx_lock_spin(&clock_lock); if (mode == MODE_STOP) { @@ -423,21 +425,36 @@ set_i8254_freq(int mode, uint32_t period) timer0_period = (mode == MODE_PERIODIC) ? new_count : -1; switch (mode) { case MODE_STOP: - outb(TIMER_MODE, TIMER_SEL0 | TIMER_INTTC | TIMER_16BIT); + new_mode = TIMER_SEL0 | TIMER_INTTC | TIMER_16BIT; + outb(TIMER_MODE, new_mode); outb(TIMER_CNTR0, 0); outb(TIMER_CNTR0, 0); break; case MODE_PERIODIC: - outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); + new_mode = TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT; + outb(TIMER_MODE, new_mode); outb(TIMER_CNTR0, new_count & 0xff); outb(TIMER_CNTR0, new_count >> 8); break; case MODE_ONESHOT: - outb(TIMER_MODE, TIMER_SEL0 | TIMER_INTTC | TIMER_16BIT); + if (new_count < 256 && timer0_last < 256) { + new_mode = TIMER_SEL0 | TIMER_INTTC | TIMER_LSB; + if (new_mode != timer0_mode) + outb(TIMER_MODE, new_mode); + outb(TIMER_CNTR0, new_count & 0xff); + break; + } + new_mode = TIMER_SEL0 | TIMER_INTTC | TIMER_16BIT; + if (new_mode != timer0_mode) + outb(TIMER_MODE, new_mode); outb(TIMER_CNTR0, new_count & 0xff); outb(TIMER_CNTR0, new_count >> 8); break; + default: + panic("set_i8254_freq: unknown operational mode"); } + timer0_mode = new_mode; + timer0_last = new_count; out: mtx_unlock_spin(&clock_lock); } @@ -447,6 +464,8 @@ i8254_restore(void) { timer0_period = -2; + timer0_mode = 0xffff; + timer0_last = 0xffff; if (attimer_sc != NULL) set_i8254_freq(attimer_sc->mode, attimer_sc->period); else @@ -459,9 +478,10 @@ i8254_restore(void) * * This function is called from pmtimer_resume() to restore all the timers. * This should not be necessary, but there are broken laptops that do not - * restore all the timers on resume. - * As long as pmtimer is not part of amd64 suport, skip this for the amd64 - * case. + * restore all the timers on resume. The APM spec was at best vague on the + * subject. + * pmtimer is used only with the old APM power management, and not with + * acpi, which is required for amd64, so skip it in that case. */ void timer_restore(void) |
