diff options
Diffstat (limited to 'sys')
| -rw-r--r-- | sys/dev/uart/uart_dev_i8251.c | 759 | ||||
| -rw-r--r-- | sys/dev/uart/uart_dev_i8251.h | 153 | ||||
| -rw-r--r-- | sys/dev/uart/uart_dev_ns8250.h | 153 | ||||
| -rw-r--r-- | sys/dev/uart/uart_dev_sab82532.h | 320 | ||||
| -rw-r--r-- | sys/dev/uart/uart_dev_z8530.h | 252 |
5 files changed, 0 insertions, 1637 deletions
diff --git a/sys/dev/uart/uart_dev_i8251.c b/sys/dev/uart/uart_dev_i8251.c deleted file mode 100644 index 4da2fa0..0000000 --- a/sys/dev/uart/uart_dev_i8251.c +++ /dev/null @@ -1,759 +0,0 @@ -/* - * Copyright (c) 2003 Marcel Moolenaar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include <sys/cdefs.h> -__FBSDID("$FreeBSD$"); - -#include <sys/param.h> -#include <sys/systm.h> -#include <sys/bus.h> -#include <sys/conf.h> -#include <machine/bus.h> - -#include <dev/uart/uart.h> -#include <dev/uart/uart_cpu.h> -#include <dev/uart/uart_bus.h> -#include <dev/uart/uart_dev_i8251.h> - -#include "uart_if.h" - -#define DEFAULT_RCLK 1843200 - -/* - * Clear pending interrupts. THRE is cleared by reading IIR. Data - * that may have been received gets lost here. - */ -static void -i8251_clrint(struct uart_bas *bas) -{ - uint8_t iir; - - iir = uart_getreg(bas, REG_IIR); - while ((iir & IIR_NOPEND) == 0) { - iir &= IIR_IMASK; - if (iir == IIR_RLS) - (void)uart_getreg(bas, REG_LSR); - else if (iir == IIR_RXRDY || iir == IIR_RXTOUT) - (void)uart_getreg(bas, REG_DATA); - else if (iir == IIR_MLSC) - (void)uart_getreg(bas, REG_MSR); - uart_barrier(bas); - iir = uart_getreg(bas, REG_IIR); - } -} - -static int -i8251_delay(struct uart_bas *bas) -{ - int divisor; - u_char lcr; - - lcr = uart_getreg(bas, REG_LCR); - uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); - uart_barrier(bas); - divisor = uart_getdreg(bas, REG_DL); - uart_barrier(bas); - uart_setreg(bas, REG_LCR, lcr); - uart_barrier(bas); - - /* 1/10th the time to transmit 1 character (estimate). */ - return (16000000 * divisor / bas->rclk); -} - -static int -i8251_divisor(int rclk, int baudrate) -{ - int actual_baud, divisor; - int error; - - if (baudrate == 0) - return (0); - - divisor = (rclk / (baudrate << 3) + 1) >> 1; - if (divisor == 0 || divisor >= 65536) - return (0); - actual_baud = rclk / (divisor << 4); - - /* 10 times error in percent: */ - error = ((actual_baud - baudrate) * 2000 / baudrate + 1) >> 1; - - /* 3.0% maximum error tolerance: */ - if (error < -30 || error > 30) - return (0); - - return (divisor); -} - -static int -i8251_drain(struct uart_bas *bas, int what) -{ - int delay, limit; - - delay = i8251_delay(bas); - - if (what & UART_DRAIN_TRANSMITTER) { - /* - * Pick an arbitrary high limit to avoid getting stuck in - * an infinite loop when the hardware is broken. Make the - * limit high enough to handle large FIFOs. - */ - limit = 10*1024; - while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) - DELAY(delay); - if (limit == 0) { - /* printf("i8251: transmitter appears stuck... "); */ - return (EIO); - } - } - - if (what & UART_DRAIN_RECEIVER) { - /* - * Pick an arbitrary high limit to avoid getting stuck in - * an infinite loop when the hardware is broken. Make the - * limit high enough to handle large FIFOs and integrated - * UARTs. The HP rx2600 for example has 3 UARTs on the - * management board that tend to get a lot of data send - * to it when the UART is first activated. - */ - limit=10*4096; - while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) { - (void)uart_getreg(bas, REG_DATA); - uart_barrier(bas); - DELAY(delay << 2); - } - if (limit == 0) { - /* printf("i8251: receiver appears broken... "); */ - return (EIO); - } - } - - return (0); -} - -/* - * We can only flush UARTs with FIFOs. UARTs without FIFOs should be - * drained. WARNING: this function clobbers the FIFO setting! - */ -static void -i8251_flush(struct uart_bas *bas, int what) -{ - uint8_t fcr; - - fcr = FCR_ENABLE; - if (what & UART_FLUSH_TRANSMITTER) - fcr |= FCR_XMT_RST; - if (what & UART_FLUSH_RECEIVER) - fcr |= FCR_RCV_RST; - uart_setreg(bas, REG_FCR, fcr); - uart_barrier(bas); -} - -static int -i8251_param(struct uart_bas *bas, int baudrate, int databits, int stopbits, - int parity) -{ - int divisor; - uint8_t lcr; - - lcr = 0; - if (databits >= 8) - lcr |= LCR_8BITS; - else if (databits == 7) - lcr |= LCR_7BITS; - else if (databits == 6) - lcr |= LCR_6BITS; - else - lcr |= LCR_5BITS; - if (stopbits > 1) - lcr |= LCR_STOPB; - lcr |= parity << 3; - - /* Set baudrate. */ - if (baudrate > 0) { - uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); - uart_barrier(bas); - divisor = i8251_divisor(bas->rclk, baudrate); - if (divisor == 0) - return (EINVAL); - uart_setdreg(bas, REG_DL, divisor); - uart_barrier(bas); - } - - /* Set LCR and clear DLAB. */ - uart_setreg(bas, REG_LCR, lcr); - uart_barrier(bas); - return (0); -} - -/* - * Low-level UART interface. - */ -static int i8251_probe(struct uart_bas *bas); -static void i8251_init(struct uart_bas *bas, int, int, int, int); -static void i8251_term(struct uart_bas *bas); -static void i8251_putc(struct uart_bas *bas, int); -static int i8251_poll(struct uart_bas *bas); -static int i8251_getc(struct uart_bas *bas); - -struct uart_ops uart_i8251_ops = { - .probe = i8251_probe, - .init = i8251_init, - .term = i8251_term, - .putc = i8251_putc, - .poll = i8251_poll, - .getc = i8251_getc, -}; - -static int -i8251_probe(struct uart_bas *bas) -{ - u_char lcr, val; - - /* Check known 0 bits that don't depend on DLAB. */ - val = uart_getreg(bas, REG_IIR); - if (val & 0x30) - return (ENXIO); - val = uart_getreg(bas, REG_MCR); - if (val & 0xe0) - return (ENXIO); - - lcr = uart_getreg(bas, REG_LCR); - uart_setreg(bas, REG_LCR, lcr & ~LCR_DLAB); - uart_barrier(bas); - - /* Check known 0 bits that depend on !DLAB. */ - val = uart_getreg(bas, REG_IER); - if (val & 0xf0) - goto fail; - - uart_setreg(bas, REG_LCR, lcr); - uart_barrier(bas); - return (0); - - fail: - uart_setreg(bas, REG_LCR, lcr); - uart_barrier(bas); - return (ENXIO); -} - -static void -i8251_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, - int parity) -{ - - if (bas->rclk == 0) - bas->rclk = DEFAULT_RCLK; - i8251_param(bas, baudrate, databits, stopbits, parity); - - /* Disable all interrupt sources. */ - uart_setreg(bas, REG_IER, 0); - uart_barrier(bas); - - /* Disable the FIFO (if present). */ - uart_setreg(bas, REG_FCR, 0); - uart_barrier(bas); - - /* Set RTS & DTR. */ - uart_setreg(bas, REG_MCR, MCR_IE | MCR_RTS | MCR_DTR); - uart_barrier(bas); - - i8251_clrint(bas); -} - -static void -i8251_term(struct uart_bas *bas) -{ - - /* Clear RTS & DTR. */ - uart_setreg(bas, REG_MCR, MCR_IE); - uart_barrier(bas); -} - -static void -i8251_putc(struct uart_bas *bas, int c) -{ - int delay, limit; - - /* 1/10th the time to transmit 1 character (estimate). */ - delay = i8251_delay(bas); - - limit = 20; - while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0 && --limit) - DELAY(delay); - uart_setreg(bas, REG_DATA, c); - limit = 40; - while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) - DELAY(delay); -} - -static int -i8251_poll(struct uart_bas *bas) -{ - - if (uart_getreg(bas, REG_LSR) & LSR_RXRDY) - return (uart_getreg(bas, REG_DATA)); - return (-1); -} - -static int -i8251_getc(struct uart_bas *bas) -{ - int delay; - - /* 1/10th the time to transmit 1 character (estimate). */ - delay = i8251_delay(bas); - - while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) - DELAY(delay); - return (uart_getreg(bas, REG_DATA)); -} - -/* - * High-level UART interface. - */ -struct i8251_softc { - struct uart_softc base; - uint8_t fcr; - uint8_t ier; - uint8_t mcr; -}; - -static int i8251_bus_attach(struct uart_softc *); -static int i8251_bus_detach(struct uart_softc *); -static int i8251_bus_flush(struct uart_softc *, int); -static int i8251_bus_getsig(struct uart_softc *); -static int i8251_bus_ioctl(struct uart_softc *, int, intptr_t); -static int i8251_bus_ipend(struct uart_softc *); -static int i8251_bus_param(struct uart_softc *, int, int, int, int); -static int i8251_bus_probe(struct uart_softc *); -static int i8251_bus_receive(struct uart_softc *); -static int i8251_bus_setsig(struct uart_softc *, int); -static int i8251_bus_transmit(struct uart_softc *); - -static kobj_method_t i8251_methods[] = { - KOBJMETHOD(uart_attach, i8251_bus_attach), - KOBJMETHOD(uart_detach, i8251_bus_detach), - KOBJMETHOD(uart_flush, i8251_bus_flush), - KOBJMETHOD(uart_getsig, i8251_bus_getsig), - KOBJMETHOD(uart_ioctl, i8251_bus_ioctl), - KOBJMETHOD(uart_ipend, i8251_bus_ipend), - KOBJMETHOD(uart_param, i8251_bus_param), - KOBJMETHOD(uart_probe, i8251_bus_probe), - KOBJMETHOD(uart_receive, i8251_bus_receive), - KOBJMETHOD(uart_setsig, i8251_bus_setsig), - KOBJMETHOD(uart_transmit, i8251_bus_transmit), - { 0, 0 } -}; - -struct uart_class uart_i8251_class = { - "i8251 class", - i8251_methods, - sizeof(struct i8251_softc), - .uc_range = 8, - .uc_rclk = DEFAULT_RCLK -}; - -#define SIGCHG(c, i, s, d) \ - if (c) { \ - i |= (i & s) ? s : s | d; \ - } else { \ - i = (i & s) ? (i & ~s) | d : i; \ - } - -static int -i8251_bus_attach(struct uart_softc *sc) -{ - struct i8251_softc *i8251 = (struct i8251_softc*)sc; - struct uart_bas *bas; - - bas = &sc->sc_bas; - - i8251->mcr = uart_getreg(bas, REG_MCR); - i8251->fcr = FCR_ENABLE | FCR_RX_MEDH; - uart_setreg(bas, REG_FCR, i8251->fcr); - uart_barrier(bas); - i8251_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); - - if (i8251->mcr & MCR_DTR) - sc->sc_hwsig |= SER_DTR; - if (i8251->mcr & MCR_RTS) - sc->sc_hwsig |= SER_RTS; - i8251_bus_getsig(sc); - - i8251_clrint(bas); - i8251->ier = IER_EMSC | IER_ERLS | IER_ERXRDY; - uart_setreg(bas, REG_IER, i8251->ier); - uart_barrier(bas); - return (0); -} - -static int -i8251_bus_detach(struct uart_softc *sc) -{ - struct uart_bas *bas; - - bas = &sc->sc_bas; - uart_setreg(bas, REG_IER, 0); - uart_barrier(bas); - i8251_clrint(bas); - return (0); -} - -static int -i8251_bus_flush(struct uart_softc *sc, int what) -{ - struct i8251_softc *i8251 = (struct i8251_softc*)sc; - struct uart_bas *bas; - int error; - - bas = &sc->sc_bas; - mtx_lock_spin(&sc->sc_hwmtx); - if (sc->sc_hasfifo) { - i8251_flush(bas, what); - uart_setreg(bas, REG_FCR, i8251->fcr); - uart_barrier(bas); - error = 0; - } else - error = i8251_drain(bas, what); - mtx_unlock_spin(&sc->sc_hwmtx); - return (error); -} - -static int -i8251_bus_getsig(struct uart_softc *sc) -{ - uint32_t new, old, sig; - uint8_t msr; - - do { - old = sc->sc_hwsig; - sig = old; - mtx_lock_spin(&sc->sc_hwmtx); - msr = uart_getreg(&sc->sc_bas, REG_MSR); - mtx_unlock_spin(&sc->sc_hwmtx); - SIGCHG(msr & MSR_DSR, sig, SER_DSR, SER_DDSR); - SIGCHG(msr & MSR_CTS, sig, SER_CTS, SER_DCTS); - SIGCHG(msr & MSR_DCD, sig, SER_DCD, SER_DDCD); - SIGCHG(msr & MSR_RI, sig, SER_RI, SER_DRI); - new = sig & ~UART_SIGMASK_DELTA; - } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); - return (sig); -} - -static int -i8251_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) -{ - struct uart_bas *bas; - int error; - uint8_t lcr; - - bas = &sc->sc_bas; - error = 0; - mtx_lock_spin(&sc->sc_hwmtx); - switch (request) { - case UART_IOCTL_BREAK: - lcr = uart_getreg(bas, REG_LCR); - if (data) - lcr |= LCR_SBREAK; - else - lcr &= ~LCR_SBREAK; - uart_setreg(bas, REG_LCR, lcr); - uart_barrier(bas); - break; - default: - error = EINVAL; - break; - } - mtx_unlock_spin(&sc->sc_hwmtx); - return (error); -} - -static int -i8251_bus_ipend(struct uart_softc *sc) -{ - struct uart_bas *bas; - int ipend; - uint8_t iir, lsr; - - bas = &sc->sc_bas; - mtx_lock_spin(&sc->sc_hwmtx); - iir = uart_getreg(bas, REG_IIR); - if (iir & IIR_NOPEND) { - mtx_unlock_spin(&sc->sc_hwmtx); - return (0); - } - ipend = 0; - if (iir & IIR_RXRDY) { - lsr = uart_getreg(bas, REG_LSR); - mtx_unlock_spin(&sc->sc_hwmtx); - if (lsr & LSR_OE) - ipend |= UART_IPEND_OVERRUN; - if (lsr & LSR_BI) - ipend |= UART_IPEND_BREAK; - if (lsr & LSR_RXRDY) - ipend |= UART_IPEND_RXREADY; - } else { - mtx_unlock_spin(&sc->sc_hwmtx); - if (iir & IIR_TXRDY) - ipend |= UART_IPEND_TXIDLE; - else - ipend |= UART_IPEND_SIGCHG; - } - return ((sc->sc_leaving) ? 0 : ipend); -} - -static int -i8251_bus_param(struct uart_softc *sc, int baudrate, int databits, - int stopbits, int parity) -{ - struct uart_bas *bas; - int error; - - bas = &sc->sc_bas; - mtx_lock_spin(&sc->sc_hwmtx); - error = i8251_param(bas, baudrate, databits, stopbits, parity); - mtx_unlock_spin(&sc->sc_hwmtx); - return (error); -} - -static int -i8251_bus_probe(struct uart_softc *sc) -{ - struct uart_bas *bas; - int count, delay, error, limit; - uint8_t mcr; - - bas = &sc->sc_bas; - - error = i8251_probe(bas); - if (error) - return (error); - - mcr = MCR_IE; - if (sc->sc_sysdev == NULL) { - /* By using i8251_init() we also set DTR and RTS. */ - i8251_init(bas, 9600, 8, 1, UART_PARITY_NONE); - } else - mcr |= MCR_DTR | MCR_RTS; - - error = i8251_drain(bas, UART_DRAIN_TRANSMITTER); - if (error) - return (error); - - /* - * Set loopback mode. This avoids having garbage on the wire and - * also allows us send and receive data. We set DTR and RTS to - * avoid the possibility that automatic flow-control prevents - * any data from being sent. We clear IE to avoid raising interrupts. - */ - uart_setreg(bas, REG_MCR, MCR_LOOPBACK | MCR_DTR | MCR_RTS); - uart_barrier(bas); - - /* - * Enable FIFOs. And check that the UART has them. If not, we're - * done. Otherwise we set DMA mode with the highest trigger level - * so that we can determine the FIFO size. Since this is the first - * time we enable the FIFOs, we reset them. - */ - uart_setreg(bas, REG_FCR, FCR_ENABLE); - uart_barrier(bas); - sc->sc_hasfifo = (uart_getreg(bas, REG_IIR) & IIR_FIFO_MASK) ? 1 : 0; - if (!sc->sc_hasfifo) { - /* - * NS16450 or II8251. We don't bother to differentiate - * between them. They're too old to be interesting. - */ - uart_setreg(bas, REG_MCR, mcr); - uart_barrier(bas); - device_set_desc(sc->sc_dev, "8250 or 16450 or compatible"); - return (0); - } - - uart_setreg(bas, REG_FCR, FCR_ENABLE | FCR_DMA | FCR_RX_HIGH | - FCR_XMT_RST | FCR_RCV_RST); - uart_barrier(bas); - - count = 0; - delay = i8251_delay(bas); - - /* We have FIFOs. Drain the transmitter and receiver. */ - error = i8251_drain(bas, UART_DRAIN_RECEIVER|UART_DRAIN_TRANSMITTER); - if (error) { - uart_setreg(bas, REG_MCR, mcr); - uart_setreg(bas, REG_FCR, 0); - uart_barrier(bas); - goto describe; - } - - uart_setreg(bas, REG_IER, IER_ERXRDY); - uart_barrier(bas); - - /* - * We should have a sufficiently clean "pipe" to determine the - * size of the FIFOs. We send as much characters as is reasonable - * and wait for the the RX interrupt to be asserted, counting the - * characters as we send them. Based on that count we know the - * FIFO size. - */ - while ((uart_getreg(bas, REG_IIR) & IIR_RXRDY) == 0 && count < 1030) { - uart_setreg(bas, REG_DATA, 0); - uart_barrier(bas); - count++; - - limit = 30; - while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) - DELAY(delay); - if (limit == 0) { - uart_setreg(bas, REG_IER, 0); - uart_setreg(bas, REG_MCR, mcr); - uart_setreg(bas, REG_FCR, 0); - uart_barrier(bas); - count = 0; - goto describe; - } - } - - uart_setreg(bas, REG_IER, 0); - uart_setreg(bas, REG_MCR, mcr); - - /* Reset FIFOs. */ - i8251_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); - - describe: - if (count >= 14 && count < 16) { - sc->sc_rxfifosz = 16; - device_set_desc(sc->sc_dev, "16550 or compatible"); - } else if (count >= 28 && count < 32) { - sc->sc_rxfifosz = 32; - device_set_desc(sc->sc_dev, "16650 or compatible"); - } else if (count >= 56 && count < 64) { - sc->sc_rxfifosz = 64; - device_set_desc(sc->sc_dev, "16750 or compatible"); - } else if (count >= 112 && count < 128) { - sc->sc_rxfifosz = 128; - device_set_desc(sc->sc_dev, "16950 or compatible"); - } else { - sc->sc_rxfifosz = 1; - device_set_desc(sc->sc_dev, - "Non-standard i8251 class UART with FIFOs"); - } - - /* - * Force the Tx FIFO size to 16 bytes for now. We don't program the - * Tx trigger. Also, we assume that all data has been sent when the - * interrupt happens. - */ - sc->sc_txfifosz = 16; - - return (0); -} - -static int -i8251_bus_receive(struct uart_softc *sc) -{ - struct uart_bas *bas; - int xc; - uint8_t lsr; - - bas = &sc->sc_bas; - mtx_lock_spin(&sc->sc_hwmtx); - lsr = uart_getreg(bas, REG_LSR); - while (lsr & LSR_RXRDY) { - if (uart_rx_full(sc)) { - sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; - break; - } - xc = uart_getreg(bas, REG_DATA); - if (lsr & LSR_FE) - xc |= UART_STAT_FRAMERR; - if (lsr & LSR_PE) - xc |= UART_STAT_PARERR; - uart_rx_put(sc, xc); - lsr = uart_getreg(bas, REG_LSR); - } - /* Discard everything left in the Rx FIFO. */ - while (lsr & LSR_RXRDY) { - (void)uart_getreg(bas, REG_DATA); - uart_barrier(bas); - lsr = uart_getreg(bas, REG_LSR); - } - mtx_unlock_spin(&sc->sc_hwmtx); - return (0); -} - -static int -i8251_bus_setsig(struct uart_softc *sc, int sig) -{ - struct i8251_softc *i8251 = (struct i8251_softc*)sc; - struct uart_bas *bas; - uint32_t new, old; - - bas = &sc->sc_bas; - do { - old = sc->sc_hwsig; - new = old; - if (sig & SER_DDTR) { - SIGCHG(sig & SER_DTR, new, SER_DTR, - SER_DDTR); - } - if (sig & SER_DRTS) { - SIGCHG(sig & SER_RTS, new, SER_RTS, - SER_DRTS); - } - } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); - mtx_lock_spin(&sc->sc_hwmtx); - i8251->mcr &= ~(MCR_DTR|MCR_RTS); - if (new & SER_DTR) - i8251->mcr |= MCR_DTR; - if (new & SER_RTS) - i8251->mcr |= MCR_RTS; - uart_setreg(bas, REG_MCR, i8251->mcr); - uart_barrier(bas); - mtx_unlock_spin(&sc->sc_hwmtx); - return (0); -} - -static int -i8251_bus_transmit(struct uart_softc *sc) -{ - struct i8251_softc *i8251 = (struct i8251_softc*)sc; - struct uart_bas *bas; - int i; - - bas = &sc->sc_bas; - mtx_lock_spin(&sc->sc_hwmtx); - while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0) - ; - uart_setreg(bas, REG_IER, i8251->ier | IER_ETXRDY); - uart_barrier(bas); - for (i = 0; i < sc->sc_txdatasz; i++) { - uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]); - uart_barrier(bas); - } - sc->sc_txbusy = 1; - mtx_unlock_spin(&sc->sc_hwmtx); - return (0); -} diff --git a/sys/dev/uart/uart_dev_i8251.h b/sys/dev/uart/uart_dev_i8251.h deleted file mode 100644 index bdb47f3..0000000 --- a/sys/dev/uart/uart_dev_i8251.h +++ /dev/null @@ -1,153 +0,0 @@ -/* - * Copyright (c) 2003 Marcel Moolenaar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * $FreeBSD$ - */ - -#ifndef _DEV_UART_DEV_I8251_H_ -#define _DEV_UART_DEV_I8251_H_ - -/* Enhanced Feature Register. */ -#define EFR_CTS 0x80 -#define EFR_RTS 0x40 -#define EFR_SCD 0x20 /* Special Character Detect. */ -#define EFR_EFC 0x10 /* Enhanced Function Control. */ -#define EFR_SFC_MASK 0x0f /* Software Flow Control. */ -#define EFR_SFC_TX12 0x0c /* BIT: Transmit XON1+2/XOFF1+2. */ -#define EFR_SFC_TX1 0x08 /* BIT: Transmit XON1/XOFF1. */ -#define EFR_SFC_TX2 0x04 /* BIT: Transmit XON2/XOFF2. */ -#define EFR_SFC_RX1 0x02 /* BIT: Receive XON1/XOFF1. */ -#define EFR_SFC_RX2 0x01 /* BIT: Receive XON2/XOFF2. */ -#define EFR_SFC_T12R12 0x0f /* VAL: TX 1+2, RX 1+2. */ -#define EFR_SFC_T1R12 0x0b /* VAL: TX 1, RX 1+2. */ -#define EFR_SFC_T2R12 0x07 /* VAL: TX 2, RX 1+2. */ - -/* FIFO Control Register. */ -#define FCR_RX_HIGH 0xc0 -#define FCR_RX_MEDH 0x80 -#define FCR_RX_MEDL 0x40 -#define FCR_RX_LOW 0x00 -#define FCR_TX_HIGH 0x30 -#define FCR_TX_MEDH 0x20 -#define FCR_TX_LOW 0x10 -#define FCR_TX_MEDL 0x00 -#define FCR_DMA 0x08 -#define FCR_XMT_RST 0x04 -#define FCR_RCV_RST 0x02 -#define FCR_ENABLE 0x01 - -/* Interrupt Enable Register. */ -#define IER_CTS 0x80 -#define IER_RTS 0x40 -#define IER_XOFF 0x20 -#define IER_SLEEP 0x10 -#define IER_EMSC 0x08 -#define IER_ERLS 0x04 -#define IER_ETXRDY 0x02 -#define IER_ERXRDY 0x01 - -/* Interrupt Identification Register. */ -#define IIR_FIFO_MASK 0xc0 -#define IIR_RTSCTS 0x20 -#define IIR_XOFF 0x10 -#define IIR_IMASK 0x0f -#define IIR_RXTOUT 0x0c -#define IIR_RLS 0x06 -#define IIR_RXRDY 0x04 -#define IIR_TXRDY 0x02 -#define IIR_MLSC 0x00 -#define IIR_NOPEND 0x01 - -/* Line Control Register. */ -#define LCR_DLAB 0x80 -#define LCR_SBREAK 0x40 -#define LCR_PZERO 0x30 -#define LCR_PONE 0x20 -#define LCR_PEVEN 0x10 -#define LCR_PODD 0x00 -#define LCR_PENAB 0x08 -#define LCR_STOPB 0x04 -#define LCR_8BITS 0x03 -#define LCR_7BITS 0x02 -#define LCR_6BITS 0x01 -#define LCR_5BITS 0x00 - -/* Line Status Register. */ -#define LSR_DERR 0x80 -#define LSR_TEMT 0x40 /* Transmitter Empty. */ -#define LSR_THRE 0x20 /* Transmitter Holding Register Empty. */ -#define LSR_BI 0x10 -#define LSR_FE 0x08 -#define LSR_PE 0x04 -#define LSR_OE 0x02 -#define LSR_RXRDY 0x01 - -/* Modem Control Register. */ -#define MCR_CS 0x80 -#define MCR_IRE 0x40 -#define MCR_ISEL 0x20 -#define MCR_LOOPBACK 0x10 -#define MCR_IE 0x08 -#define MCR_LBDCD MCR_IE -#define MCR_LBRI 0x04 -#define MCR_RTS 0x02 -#define MCR_DTR 0x01 - -/* Modem Status Register. */ -#define MSR_DCD 0x80 -#define MSR_RI 0x40 -#define MSR_DSR 0x20 -#define MSR_CTS 0x10 -#define MSR_DDCD 0x08 -#define MSR_TERI 0x04 -#define MSR_DDSR 0x02 -#define MSR_DCTS 0x01 - -/* General registers. */ -#define REG_DATA 0 /* Data Register. */ -#define REG_RBR REG_DATA /* Receiver Buffer Register (R). */ -#define REG_THR REG_DATA /* Transmitter Holding Register (W). */ -#define REG_IER 1 /* Interrupt Enable Register */ -#define REG_IIR 2 /* Interrupt Ident. Register (R). */ -#define REG_FCR 2 /* FIFO Control Register (W). */ -#define REG_LCR 3 /* Line Control Register. */ -#define REG_MCR 4 /* Modem Control Register. */ -#define REG_LSR 5 /* Line Status Register. */ -#define REG_MSR 6 /* Modem Status Register. */ -#define REG_SPR 7 /* Scratch Pad Register. */ - -/* Baudrate registers (LCR[7] = 1). */ -#define REG_DLBL 0 /* Divisor Latch (LSB). */ -#define REG_DLBH 1 /* Divisor Latch (MSB). */ -#define REG_DL REG_DLBL /* Divisor Latch (16-bit I/O). */ - -/* Enhanced registers (LCR = 0xBF). */ -#define REG_EFR 2 /* Enhanced Feature Register. */ -#define REG_XON1 4 /* XON character 1. */ -#define REG_XON2 5 /* XON character 2. */ -#define REG_XOFF1 6 /* XOFF character 1. */ -#define REG_XOFF2 7 /* XOFF character 2. */ - -#endif /* _DEV_UART_DEV_I8251_H_ */ diff --git a/sys/dev/uart/uart_dev_ns8250.h b/sys/dev/uart/uart_dev_ns8250.h deleted file mode 100644 index 85c4722..0000000 --- a/sys/dev/uart/uart_dev_ns8250.h +++ /dev/null @@ -1,153 +0,0 @@ -/* - * Copyright (c) 2003 Marcel Moolenaar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * $FreeBSD$ - */ - -#ifndef _DEV_UART_DEV_NS8250_H_ -#define _DEV_UART_DEV_NS8250_H_ - -/* Enhanced Feature Register. */ -#define EFR_CTS 0x80 -#define EFR_RTS 0x40 -#define EFR_SCD 0x20 /* Special Character Detect. */ -#define EFR_EFC 0x10 /* Enhanced Function Control. */ -#define EFR_SFC_MASK 0x0f /* Software Flow Control. */ -#define EFR_SFC_TX12 0x0c /* BIT: Transmit XON1+2/XOFF1+2. */ -#define EFR_SFC_TX1 0x08 /* BIT: Transmit XON1/XOFF1. */ -#define EFR_SFC_TX2 0x04 /* BIT: Transmit XON2/XOFF2. */ -#define EFR_SFC_RX1 0x02 /* BIT: Receive XON1/XOFF1. */ -#define EFR_SFC_RX2 0x01 /* BIT: Receive XON2/XOFF2. */ -#define EFR_SFC_T12R12 0x0f /* VAL: TX 1+2, RX 1+2. */ -#define EFR_SFC_T1R12 0x0b /* VAL: TX 1, RX 1+2. */ -#define EFR_SFC_T2R12 0x07 /* VAL: TX 2, RX 1+2. */ - -/* FIFO Control Register. */ -#define FCR_RX_HIGH 0xc0 -#define FCR_RX_MEDH 0x80 -#define FCR_RX_MEDL 0x40 -#define FCR_RX_LOW 0x00 -#define FCR_TX_HIGH 0x30 -#define FCR_TX_MEDH 0x20 -#define FCR_TX_LOW 0x10 -#define FCR_TX_MEDL 0x00 -#define FCR_DMA 0x08 -#define FCR_XMT_RST 0x04 -#define FCR_RCV_RST 0x02 -#define FCR_ENABLE 0x01 - -/* Interrupt Enable Register. */ -#define IER_CTS 0x80 -#define IER_RTS 0x40 -#define IER_XOFF 0x20 -#define IER_SLEEP 0x10 -#define IER_EMSC 0x08 -#define IER_ERLS 0x04 -#define IER_ETXRDY 0x02 -#define IER_ERXRDY 0x01 - -/* Interrupt Identification Register. */ -#define IIR_FIFO_MASK 0xc0 -#define IIR_RTSCTS 0x20 -#define IIR_XOFF 0x10 -#define IIR_IMASK 0x0f -#define IIR_RXTOUT 0x0c -#define IIR_RLS 0x06 -#define IIR_RXRDY 0x04 -#define IIR_TXRDY 0x02 -#define IIR_MLSC 0x00 -#define IIR_NOPEND 0x01 - -/* Line Control Register. */ -#define LCR_DLAB 0x80 -#define LCR_SBREAK 0x40 -#define LCR_PZERO 0x30 -#define LCR_PONE 0x20 -#define LCR_PEVEN 0x10 -#define LCR_PODD 0x00 -#define LCR_PENAB 0x08 -#define LCR_STOPB 0x04 -#define LCR_8BITS 0x03 -#define LCR_7BITS 0x02 -#define LCR_6BITS 0x01 -#define LCR_5BITS 0x00 - -/* Line Status Register. */ -#define LSR_DERR 0x80 -#define LSR_TEMT 0x40 /* Transmitter Empty. */ -#define LSR_THRE 0x20 /* Transmitter Holding Register Empty. */ -#define LSR_BI 0x10 -#define LSR_FE 0x08 -#define LSR_PE 0x04 -#define LSR_OE 0x02 -#define LSR_RXRDY 0x01 - -/* Modem Control Register. */ -#define MCR_CS 0x80 -#define MCR_IRE 0x40 -#define MCR_ISEL 0x20 -#define MCR_LOOPBACK 0x10 -#define MCR_IE 0x08 -#define MCR_LBDCD MCR_IE -#define MCR_LBRI 0x04 -#define MCR_RTS 0x02 -#define MCR_DTR 0x01 - -/* Modem Status Register. */ -#define MSR_DCD 0x80 -#define MSR_RI 0x40 -#define MSR_DSR 0x20 -#define MSR_CTS 0x10 -#define MSR_DDCD 0x08 -#define MSR_TERI 0x04 -#define MSR_DDSR 0x02 -#define MSR_DCTS 0x01 - -/* General registers. */ -#define REG_DATA 0 /* Data Register. */ -#define REG_RBR REG_DATA /* Receiver Buffer Register (R). */ -#define REG_THR REG_DATA /* Transmitter Holding Register (W). */ -#define REG_IER 1 /* Interrupt Enable Register */ -#define REG_IIR 2 /* Interrupt Ident. Register (R). */ -#define REG_FCR 2 /* FIFO Control Register (W). */ -#define REG_LCR 3 /* Line Control Register. */ -#define REG_MCR 4 /* Modem Control Register. */ -#define REG_LSR 5 /* Line Status Register. */ -#define REG_MSR 6 /* Modem Status Register. */ -#define REG_SPR 7 /* Scratch Pad Register. */ - -/* Baudrate registers (LCR[7] = 1). */ -#define REG_DLBL 0 /* Divisor Latch (LSB). */ -#define REG_DLBH 1 /* Divisor Latch (MSB). */ -#define REG_DL REG_DLBL /* Divisor Latch (16-bit I/O). */ - -/* Enhanced registers (LCR = 0xBF). */ -#define REG_EFR 2 /* Enhanced Feature Register. */ -#define REG_XON1 4 /* XON character 1. */ -#define REG_XON2 5 /* XON character 2. */ -#define REG_XOFF1 6 /* XOFF character 1. */ -#define REG_XOFF2 7 /* XOFF character 2. */ - -#endif /* _DEV_UART_DEV_NS8250_H_ */ diff --git a/sys/dev/uart/uart_dev_sab82532.h b/sys/dev/uart/uart_dev_sab82532.h deleted file mode 100644 index 8b53371..0000000 --- a/sys/dev/uart/uart_dev_sab82532.h +++ /dev/null @@ -1,320 +0,0 @@ -/* $OpenBSD: sab82532reg.h,v 1.2 2002/04/08 17:49:42 jason Exp $ */ - -/* - * Copyright (c) 2001 Jason L. Wright (jason@thought.net) - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by Jason L. Wright - * 4. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * Effort sponsored in part by the Defense Advanced Research Projects - * Agency (DARPA) and Air Force Research Laboratory, Air Force - * Materiel Command, USAF, under agreement number F30602-01-2-0537. - * - * $FreeBSD$ - */ - -/* - * Register definitions for SAB82532 based on "Enhanced Serial Communication - * Controller ESCC2 Version 3.2 User's Manual 07.96" from: - * http://www.infineon.com - */ - -#define SAB_NCHAN 2 /* number of channels */ -#define SAB_CHANLEN 0x40 /* length of channel register set */ - -#define SAB_CHAN_A 0x00 /* channel A register offset */ -#define SAB_CHAN_B 0x40 /* channel B register offset */ - -#define SAB_RFIFO 0x00 /* r: rx fifo */ -#define SAB_XFIFO 0x00 /* w: tx fifo */ -#define SAB_STAR 0x20 /* r: status register */ -#define SAB_CMDR 0x20 /* w: command register */ -#define SAB_MODE 0x22 /* rw: mode register */ -#define SAB_TIMR 0x23 /* rw: timer register */ -#define SAB_XON 0x24 /* rw: xon character */ -#define SAB_XOFF 0x25 /* rw: xoff character */ -#define SAB_TCR 0x26 /* rw: termination character */ -#define SAB_DAFO 0x27 /* rw: data format */ -#define SAB_RFC 0x28 /* rw: rfifo control register */ -#define SAB_RBCL 0x2a /* r: rx byte count low */ -#define SAB_TBCL 0x2a /* w: tx byte count low */ -#define SAB_RBCH 0x2b /* r: rx byte count high */ -#define SAB_XBCH 0x2b /* w: tx byte count high */ -#define SAB_CCR0 0x2c /* rw: channel configuration register 0 */ -#define SAB_CCR1 0x2d /* rw: channel configuration register 1 */ -#define SAB_CCR2 0x2e /* rw: channel configuration register 2 */ -#define SAB_CCR3 0x2f /* rw: channel configuration register 3 */ -#define SAB_TSAX 0x30 /* w: time-slot assignment register tx */ -#define SAB_TSAR 0x31 /* w: time-slot assignment register rx */ -#define SAB_XCCR 0x32 /* w: tx channel capacity register */ -#define SAB_RCCR 0x33 /* w: receive channel capacity register */ -#define SAB_VSTR 0x34 /* r: version status */ -#define SAB_BGR 0x34 /* w: baud rate generator */ -#define SAB_TIC 0x35 /* w: transmit immediate character */ -#define SAB_MXN 0x36 /* w: mask xon character */ -#define SAB_MXF 0x37 /* w: mask xoff character */ -#define SAB_GIS 0x38 /* r: global interrupt status */ -#define SAB_IVA 0x38 /* w: interrupt vector address */ -#define SAB_IPC 0x39 /* rw: interrupt port configuration */ -#define SAB_ISR0 0x3a /* r: interrupt status 0 */ -#define SAB_IMR0 0x3a /* w: interrupt mask 0 */ -#define SAB_ISR1 0x3b /* r: interrupt status 1 */ -#define SAB_IMR1 0x3b /* w: interrupt mask 1 */ -#define SAB_PVR 0x3c /* rw: port value register */ -#define SAB_PIS 0x3d /* r: port interrupt status */ -#define SAB_PIM 0x3d /* w: port interrupt mask */ -#define SAB_PCR 0x3e /* w: port configuration register */ -#define SAB_CCR4 0x3f /* rw: channel configuration register 4 */ - -/* SAB_STAR: status register */ -#define SAB_STAR_XDOV 0x80 /* transmit data overflow */ -#define SAB_STAR_XFW 0x40 /* transmit fifo write enable */ -#define SAB_STAR_RFNE 0x20 /* rfifo not empty */ -#define SAB_STAR_FCS 0x10 /* flow control status */ -#define SAB_STAR_TEC 0x08 /* tx immediate char is executing */ -#define SAB_STAR_CEC 0x04 /* command is executing */ -#define SAB_STAR_CTS 0x02 /* cts status: 0:inactive/high,1:active/low */ - -/* SAB_CMDR: command register */ -#define SAB_CMDR_RMC 0x80 /* receive message complete */ -#define SAB_CMDR_RRES 0x40 /* receiver reset */ -#define SAB_CMDR_RFRD 0x20 /* receive fifo read enable */ -#define SAB_CMDR_STI 0x10 /* start timer */ -#define SAB_CMDR_XF 0x08 /* transmit frame */ -#define SAB_CMDR_XRES 0x01 /* transmit reset */ - -/* SAB_MODE: mode register */ -#define SAB_MODE_FRTS 0x40 /* flow control using rts */ -#define SAB_MODE_FCTS 0x20 /* flow control using cts */ -#define SAB_MODE_FLON 0x10 /* flow control on */ -#define SAB_MODE_RAC 0x08 /* receiver active */ -#define SAB_MODE_RTS 0x04 /* request to send */ -#define SAB_MODE_TRS 0x02 /* timer resolution */ -#define SAB_MODE_TLP 0x01 /* test loop */ - -/* SAB_TIMR: timer register */ -#define SAB_TIMR_CNT 0xe0 /* count mask */ -#define SAB_TIMR_VAL 0x1f /* value mask */ - -/* SAB_DAFO: data format */ -#define SAB_DAFO_XBRK 0x40 /* transmit break */ -#define SAB_DAFO_STOP 0x20 /* stop bit: 0:1 bit, 1:2 bits */ -#define SAB_DAFO_PAR1 0x10 /* parity 1, see below */ -#define SAB_DAFO_PAR0 0x08 /* parity 0, see below */ -#define SAB_DAFO_PARE 0x04 /* parity enable */ -#define SAB_DAFO_CHL1 0x02 /* character length 1, see below */ -#define SAB_DAFO_CHL0 0x01 /* character length 0, see below */ - -#define SAB_DAFO_CHL_CSIZE (SAB_DAFO_CHL1|SAB_DAFO_CHL0) -#define SAB_DAFO_CHL_CS5 (SAB_DAFO_CHL1|SAB_DAFO_CHL0) -#define SAB_DAFO_CHL_CS6 (SAB_DAFO_CHL1) -#define SAB_DAFO_CHL_CS7 (SAB_DAFO_CHL0) -#define SAB_DAFO_CHL_CS8 (0) - -#define SAB_DAFO_PARMASK (SAB_DAFO_PAR1|SAB_DAFO_PAR0|SAB_DAFO_PARE) -#define SAB_DAFO_PAR_MARK (SAB_DAFO_PAR1|SAB_DAFO_PAR0|SAB_DAFO_PARE) -#define SAB_DAFO_PAR_EVEN (SAB_DAFO_PAR1|SAB_DAFO_PARE) -#define SAB_DAFO_PAR_ODD (SAB_DAFO_PAR0|SAB_DAFO_PARE) -#define SAB_DAFO_PAR_SPACE (SAB_DAFO_PARE) -#define SAB_DAFO_PAR_NONE (0) - -/* SAB_RFC: rfifo control register */ -#define SAB_RFC_DPS 0x40 /* disable parity storage */ -#define SAB_RFC_DXS 0x20 /* disable storage of xon/xoff characters */ -#define SAB_RFC_RFDF 0x10 /* rfifo data format: 0 data,1 data+stat */ -#define SAB_RFC_RFTH1 0x08 /* rfifo threshold level 1, see below */ -#define SAB_RFC_RFTH0 0x04 /* rfifo threshold level 0, see below */ -#define SAB_RFC_TCDE 0x01 /* termination character detection enable */ - -#define SAB_RFC_RFTH_MASK (SAB_RFC_RFTH1|SAB_RFC_RFTH0) -#define SAB_RFC_RFTH_32CHAR (SAB_RFC_RFTH1|SAB_RFC_RFTH0) -#define SAB_RFC_RFTH_16CHAR (SAB_RFC_RFTH1) -#define SAB_RFC_RFTH_4CHAR (SAB_RFC_RFTH0) -#define SAB_RFC_RFTH_1CHAR (0) - -/* SAB_RBCH: received byte count high */ -#define SAB_RBCH_DMA 0x80 /* read back of XBCH DMA bit */ -#define SAB_RBCH_CAS 0x20 /* read back of XBCH CAS bit */ -#define SAB_RBCH_CNT 0x0f /* ms 4 bits of rx byte count (not used) */ - -/* SAB_XBCH: transmit byte count high */ -#define SAB_XBCH_DMA 0x80 /* dma mode: 1:dma, 0:interrupt */ -#define SAB_XBCH_CAS 0x20 /* carrier detect auto-start */ -#define SAB_XBCH_XC 0x10 /* transmit continuously */ -#define SAB_XBCH_CNT 0x0f /* ms 4 bits of tx byte count */ - -/* SAB_CCR0: channel configuration register 0 */ -#define SAB_CCR0_PU 0x80 /* 0:power-down, 1:power-up */ -#define SAB_CCR0_MCE 0x40 /* master clock enable */ -#define SAB_CCR0_SC2 0x10 /* serial port config 2, see below */ -#define SAB_CCR0_SC1 0x08 /* serial port config 1, see below */ -#define SAB_CCR0_SC0 0x04 /* serial port config 0, see below */ -#define SAB_CCR0_SM1 0x02 /* serial mode 1, see below */ -#define SAB_CCR0_SM0 0x01 /* serial mode 0, see below */ - -#define SAB_CCR0_SC_MASK (SAB_CCR0_SC2|SAB_CCR0_SC1|SAB_CCR0_SC0) -#define SAB_CCR0_SC_NRZ (0) -#define SAB_CCR0_SC_NRZI (SAB_CCR0_SC1) -#define SAB_CCR0_SC_FM0 (SAB_CCR0_SC2) -#define SAB_CCR0_SC_FM1 (SAB_CCR0_SC2|SAB_CCR0_SC0) -#define SAB_CCR0_SC_MANCHESTER (SAB_CCR0_SC2|SAB_CCR0_SC1) - -#define SAB_CCR0_SM_MASK (SAB_CCR0_SM1|SAB_CCR0_SM0) -#define SAB_CCR0_SM_DLC (0) -#define SAB_CCR0_SM_DLCLOOP (SAB_CCR0_SM0) -#define SAB_CCR0_SM_BISYNC (SAB_CCR0_SM1) -#define SAB_CCR0_SM_ASYNC (SAB_CCR0_SM1|SAB_CCR0_SM0) - -/* SAB_CCR1: channel configuration register 1 */ -#define SAB_CCR1_ODS 0x10 /* Output driver select:1:pushpull,0:odrain */ -#define SAB_CCR1_BCR 0x08 /* bit clock rate: 1:async, 0:isochronous */ -#define SAB_CCR1_CM2 0x04 /* clock mode 2, see below */ -#define SAB_CCR1_CM1 0x02 /* clock mode 1, see below */ -#define SAB_CCR1_CM0 0x01 /* clock mode 0, see below */ - -#define SAB_CCR1_CM_MASK (SAB_CCR1_CM2|SAB_CCR1_CM1|SAB_CCR1_CM0) -#define SAB_CCR1_CM_7 (SAB_CCR1_CM2|SAB_CCR1_CM1|SAB_CCR1_CM0) - -/* SAB_CCR2: channel configuration register 2, depends on clock mode above */ -/* clock mode 0a, 1, 4, 5 */ -#define SAB_CCR2_SOC1 0x80 /* special output 1, below */ -#define SAB_CCR2_SOC0 0x40 /* special output 0, below */ -#define SAB_CCR2_SOC_MASK (SAB_CCR2_SOC1|SAB_CCR2_SOC0) -#define SAB_CCR2_SOC_RTSHIGH (SAB_CCR2_SOC1) -#define SAB_CCR2_SOC_RTSNORM (0) -#define SAB_CCR2_SOC_RTSRX (SAB_CCR2_SOC1|SAB_CCR2_SOC0) -/* clock mode 0b, 2, 3, 6, 7 */ -#define SAB_CCR2_BR9 0x80 /* baud rate bit 9 */ -#define SAB_CCR2_BR8 0x40 /* baud rate bit 8 */ -#define SAB_CCR2_BDF 0x20 /* baud rate division factor: 0:1: 1:BRG */ -#define SAB_CCR2_SSEL 0x10 /* clock source select */ -/* clock mode 5 */ -#define SAB_CCR2_XCS0 0x20 /* tx clock shift, bit 0 */ -#define SAB_CCR2_RCS0 0x10 /* rx clock shift, bit 0 */ -/* clock mode 0b, 2, 3, 4, 5, 6, 7 */ -#define SAB_CCR2_TOE 0x08 /* tx clock output enable */ -/* clock mode 0a, 0b, 1, 2, 3, 4, 5, 6, 7 */ -#define SAB_CCR2_RWX 0x04 /* read/write exchange (dma mode only) */ -#define SAB_CCR2_DIV 0x01 /* data inversion (nrz) */ - -/* SAB_CCR3: channel configuration register 3 (v2 or greater) */ -#define SAB_CCR3_PSD 0x01 /* dpll phase shift disable (nrz/nrzi) */ - -/* SAB_TSAX: time-slot assignment register transmit (clock mode 5 only) */ -#define SAB_TSAX_TSNX 0xfc /* time-slot number transmit */ -#define SAB_TSAX_XCS2 0x02 /* transmit clock shift bit 2 */ -#define SAB_TSAX_XCS1 0x01 /* transmit clock shift bit 1 */ - -/* SAB_TSAR: time-slot assignment register receive (clock mode 5 only) */ -#define SAB_TSAR_TSNR 0xfc /* time-slot number receive */ -#define SAB_TSAR_RCS2 0x02 /* receive clock shift bit 2 */ -#define SAB_TSAR_RCS1 0x01 /* receive clock shift bit 1 */ - -/* SAB_VSTR: version status register */ -#define SAB_VSTR_CD 0x80 /* carrier detect status */ -#define SAB_VSTR_DPLA 0x40 /* dpll asynchronous */ -#define SAB_VSTR_VMASK 0x0f /* chip version mask: */ -#define SAB_VSTR_V_1 0x00 /* version 1 */ -#define SAB_VSTR_V_2 0x01 /* version 2 */ -#define SAB_VSTR_V_32 0x02 /* version 3.2 */ - -/* SAB_GIS: global interrupt status register */ -#define SAB_GIS_PI 0x80 /* universal port interrupt */ -#define SAB_GIS_ISA1 0x08 /* interrupt status a1 */ -#define SAB_GIS_ISA0 0x04 /* interrupt status a0 */ -#define SAB_GIS_ISB1 0x02 /* interrupt status b1 */ -#define SAB_GIS_ISB0 0x01 /* interrupt status b0 */ - -/* SAB_IVA: interrupt vector address */ -#define SAB_IVA_MASK 0xf8 /* interrupt vector address mask */ - -/* SAB_IPC: interrupt port configuration */ -#define SAB_IPC_VIS 0x80 /* masked interrupt bits visible */ -#define SAB_IPC_SLAMASK 0x18 /* slave address mask */ -#define SAB_IPC_CASM 0x04 /* cascading mode */ -#define SAB_IPC_ICMASK 0x03 /* port config mask: */ -#define SAB_IPC_ICOD 0x00 /* open drain output */ -#define SAB_IPC_ICPL 0x01 /* push/pull active low output */ -#define SAB_IPC_ICPH 0x03 /* push/pull active high output */ - -/* SAB_ISR0: interrupt status 0 */ -#define SAB_ISR0_TCD 0x80 /* termination character detected */ -#define SAB_ISR0_TIME 0x40 /* time-out limit exceeded */ -#define SAB_ISR0_PERR 0x20 /* parity error */ -#define SAB_ISR0_FERR 0x10 /* framing error */ -#define SAB_ISR0_PLLA 0x08 /* dpll asynchronous */ -#define SAB_ISR0_CDSC 0x04 /* carrier detect status change */ -#define SAB_ISR0_RFO 0x02 /* rfifo overflow */ -#define SAB_ISR0_RPF 0x01 /* receive pool full */ - -/* SAB_ISR1: interrupt status 1 */ -#define SAB_ISR1_BRK 0x80 /* break detected */ -#define SAB_ISR1_BRKT 0x40 /* break terminated */ -#define SAB_ISR1_ALLS 0x20 /* all sent */ -#define SAB_ISR1_XOFF 0x10 /* xoff detected */ -#define SAB_ISR1_TIN 0x08 /* timer interrupt */ -#define SAB_ISR1_CSC 0x04 /* clear to send status change */ -#define SAB_ISR1_XON 0x02 /* xon detected */ -#define SAB_ISR1_XPR 0x01 /* transmit pool ready */ - -/* SAB_IMR0: interrupt mask 0 */ -#define SAB_IMR0_TCD 0x80 /* termination character detected */ -#define SAB_IMR0_TIME 0x40 /* time-out limit exceeded */ -#define SAB_IMR0_PERR 0x20 /* parity error */ -#define SAB_IMR0_FERR 0x10 /* framing error */ -#define SAB_IMR0_PLLA 0x08 /* dpll asynchronous */ -#define SAB_IMR0_CDSC 0x04 /* carrier detect status change */ -#define SAB_IMR0_RFO 0x02 /* rfifo overflow */ -#define SAB_IMR0_RPF 0x01 /* receive pool full */ - -/* SAB_ISR1: interrupt mask 1 */ -#define SAB_IMR1_BRK 0x80 /* break detected */ -#define SAB_IMR1_BRKT 0x40 /* break terminated */ -#define SAB_IMR1_ALLS 0x20 /* all sent */ -#define SAB_IMR1_XDU 0x10 /* xoff detected */ -#define SAB_IMR1_TIN 0x08 /* timer interrupt */ -#define SAB_IMR1_CSC 0x04 /* clear to send status change */ -#define SAB_IMR1_XMR 0x02 /* xon detected */ -#define SAB_IMR1_XPR 0x01 /* transmit pool ready */ - -/* SAB_PVR: port value register */ -#define SAB_PVR_DSR_A 0x01 /* port A DSR */ -#define SAB_PVR_DTR_A 0x02 /* port A DTR */ -#define SAB_PVR_DTR_B 0x04 /* port B DTR */ -#define SAB_PVR_DSR_B 0x08 /* port B DSR */ -#define SAB_PVR_MAGIC 0x10 /* dunno... */ - -/* SAB_CCR4: channel configuration register 4 */ -#define SAB_CCR4_MCK4 0x80 /* master clock divide by 4 */ -#define SAB_CCR4_EBRG 0x40 /* enhanced baud rate generator mode */ -#define SAB_CCR4_TST1 0x20 /* test pin */ -#define SAB_CCR4_ICD 0x10 /* invert polarity of carrier detect */ - -/* Receive status byte */ -#define SAB_RSTAT_PE 0x80 /* parity error */ -#define SAB_RSTAT_FE 0x40 /* framing error */ -#define SAB_RSTAT_PAR 0x01 /* parity bit */ diff --git a/sys/dev/uart/uart_dev_z8530.h b/sys/dev/uart/uart_dev_z8530.h deleted file mode 100644 index 458aff7..0000000 --- a/sys/dev/uart/uart_dev_z8530.h +++ /dev/null @@ -1,252 +0,0 @@ -/* - * Copyright (c) 2003 Marcel Moolenaar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * $FreeBSD$ - */ - -#ifndef _DEV_UART_DEV_Z8530_H_ -#define _DEV_UART_DEV_Z8530_H_ - -/* - * Channel B control: 0 - * Channel B data: 1 - * Channel A control: 2 - * Channel A data: 3 - * - * We expect a seperate subregion for each channel. - */ -#define REG_CTRL 0 -#define REG_DATA 1 - -/* Write registers. */ -#define WR_CR 0 /* Command Register. */ -#define WR_IDT 1 /* Interrupt and Data Transfer Mode. */ -#define WR_IV 2 /* Interrupt Vector (shared). */ -#define WR_RPC 3 /* Receive Parameters and Control. */ -#define WR_MPM 4 /* Miscellaneous Parameters and Modes. */ -#define WR_TPC 5 /* Transmit Parameters and Control. */ -#define WR_SCAF 6 /* Sync Character or (SDLC) Address Field. */ -#define WR_SCF 7 /* Sync Character or (SDCL) Flag. */ -#define WR_EFC 7 /* Extended Feature and FIFO Control. */ -#define WR_TB 8 /* Transmit Buffer. */ -#define WR_MIC 9 /* Master Interrupt Control (shared). */ -#define WR_MCB1 10 /* Miscellaneous Control Bits (part 1 :-). */ -#define WR_CMC 11 /* Clock Mode Control. */ -#define WR_TCL 12 /* BRG Time Constant Low. */ -#define WR_TCH 13 /* BRG Time Constant High. */ -#define WR_MCB2 14 /* Miscellaneous Control Bits (part 2 :-). */ -#define WR_IC 15 /* Interrupt Control. */ - -/* Read registers. */ -#define RR_BES 0 /* Buffer and External Status. */ -#define RR_SRC 1 /* Special Receive Condition. */ -#define RR_IV 2 /* Interrupt Vector. */ -#define RR_IP 3 /* Interrupt Pending (ch A only). */ -#define RR_MPM 4 /* Miscellaneous Parameters and Modes. */ -#define RR_TPC 5 /* Transmit Parameters and Control. */ -#define RR_BCL 6 /* Byte Count Low. */ -#define RR_BCH 7 /* Byte Count High. */ -#define RR_RB 8 /* Receive Buffer. */ -#define RR_RPC 9 /* Receive Parameters and Contro. */ -#define RR_MSB 10 /* Miscellaneous Status Bits. */ -#define RR_MCB1 11 /* Miscellaneous Control Bits (part 1). */ -#define RR_TCL 12 /* BRG Time Constant Low. */ -#define RR_TCH 13 /* BRG Time Constant High. */ -#define RR_EFC 14 /* Extended Feature and FIFO Control. */ -#define RR_IC 15 /* Interrupt Control. */ - -/* Buffer and External Status (RR0). */ -#define BES_BRK 0x80 /* Break (Abort). */ -#define BES_TXU 0x40 /* Tx Underrun (EOM). */ -#define BES_CTS 0x20 /* CTS. */ -#define BES_SYNC 0x10 /* Sync. */ -#define BES_DCD 0x08 /* DCD. */ -#define BES_TXE 0x04 /* Tx Empty. */ -#define BES_ZC 0x02 /* Zero Count. */ -#define BES_RXA 0x01 /* Rx Available. */ - -/* Clock Mode Control (WR11). */ -#define CMC_XTAL 0x80 /* -RTxC connects to quartz crystal. */ -#define CMC_RC_DPLL 0x60 /* Rx Clock from DPLL. */ -#define CMC_RC_BRG 0x40 /* Rx Clock from BRG. */ -#define CMC_RC_TRXC 0x20 /* Rx Clock from -TRxC. */ -#define CMC_RC_RTXC 0x00 /* Rx Clock from -RTxC. */ -#define CMC_TC_DPLL 0x18 /* Tx Clock from DPLL */ -#define CMC_TC_BRG 0x10 /* Tx Clock from BRG */ -#define CMC_TC_TRXC 0x08 /* Tx Clock from -TRxC. */ -#define CMC_TC_RTXC 0x00 /* Tx Clock from -RTxC. */ -#define CMC_TRXC_OUT 0x04 /* -TRxC is output. */ -#define CMC_TRXC_DPLL 0x03 /* -TRxC from DPLL */ -#define CMC_TRXC_BRG 0x02 /* -TRxC from BRG */ -#define CMC_TRXC_XMIT 0x01 /* -TRxC from Tx clock. */ -#define CMC_TRXC_XTAL 0x00 /* -TRxC from XTAL. */ - -/* Command Register (WR0). */ -#define CR_RSTTXU 0xc0 /* Reset Tx. Underrun/EOM. */ -#define CR_RSTTXCRC 0x80 /* Reset Tx. CRC. */ -#define CR_RSTRXCRC 0x40 /* Reset Rx. CRC. */ -#define CR_RSTIUS 0x38 /* Reset Int. Under Service. */ -#define CR_RSTERR 0x30 /* Error Reset. */ -#define CR_RSTTXI 0x28 /* Reset Tx. Int. */ -#define CR_ENARXI 0x20 /* Enable Rx. Int. */ -#define CR_ABORT 0x18 /* Send Abort. */ -#define CR_RSTXSI 0x10 /* Reset Ext/Status Int. */ - -/* Extended Feature and FIFO Control (WR7 prime). */ -#define EFC_ERE 0x40 /* Extended Read Enable. */ -#define EFC_FE 0x20 /* Transmit FIFO Empty. */ -#define EFC_RQT 0x10 /* Request Timing. */ -#define EFC_FHF 0x08 /* Receive FIFO Half Full. */ -#define EFC_RTS 0x04 /* Auto RTS Deactivation. */ -#define EFC_EOM 0x02 /* Auto EOM Reset. */ -#define EFC_FLAG 0x01 /* Auto SDLC Flag on Tx. */ - -/* Interrupt Control (WR15). */ -#define IC_BRK 0x80 /* Break (Abort) IE. */ -#define IC_TXU 0x40 /* Tx Underrun IE. */ -#define IC_CTS 0x20 /* CTS IE. */ -#define IC_SYNC 0x10 /* Sync IE. */ -#define IC_DCD 0x08 /* DCD IE. */ -#define IC_FIFO 0x04 /* SDLC FIFO Enable. */ -#define IC_ZC 0x02 /* Zero Count IE. */ -#define IC_EF 0x01 /* Extended Feature Enable. */ - -/* Interrupt and Data Transfer Mode (WR1). */ -#define IDT_WRE 0x80 /* Wait/DMA Request Enable. */ -#define IDT_REQ 0x40 /* DMA Request. */ -#define IDT_WRR 0x20 /* Wait/DMA Reuest on Receive. */ -#define IDT_RISC 0x18 /* Rx Int. on Special Condition Only. */ -#define IDT_RIA 0x10 /* Rx Int. on All Characters. */ -#define IDT_RIF 0x08 /* Rx Int. on First Character. */ -#define IDT_PSC 0x04 /* Parity is Special Condition. */ -#define IDT_TIE 0x02 /* Tx Int. Enable. */ -#define IDT_XIE 0x01 /* Ext. Int. Enable. */ - -/* Interrupt Pending (RR3). */ -#define IP_RIA 0x20 /* Rx. Int. ch. A. */ -#define IP_TIA 0x10 /* Tx. Int. ch. A. */ -#define IP_SIA 0x08 /* Ext/Status Int. ch. A. */ -#define IP_RIB 0x04 /* Rx. Int. ch. B. */ -#define IP_TIB 0x02 /* Tx. Int. ch. B. */ -#define IP_SIB 0x01 /* Ext/Status Int. ch. B. */ - -/* Interrupt Vector Status Low (RR2). */ -#define IV_SCA 0x0e /* Special Condition ch. A. */ -#define IV_RAA 0x0c /* Receive Available ch. A. */ -#define IV_XSA 0x0a /* External/Status Change ch. A. */ -#define IV_TEA 0x08 /* Transmitter Empty ch. A. */ -#define IV_SCB 0x06 /* Special Condition ch. B. */ -#define IV_RAB 0x04 /* Receive Available ch. B. */ -#define IV_XSB 0x02 /* External/Status Change ch. B. */ -#define IV_TEB 0x00 /* Transmitter Empty ch. B. */ - -/* Miscellaneous Control Bits part 1 (WR10). */ -#define MCB1_CRC1 0x80 /* CRC presets to 1. */ -#define MCB1_FM0 0x60 /* FM0 Encoding. */ -#define MCB1_FM1 0x40 /* FM1 Encoding. */ -#define MCB1_NRZI 0x20 /* NRZI Encoding. */ -#define MCB1_NRZ 0x00 /* NRZ Encoding. */ -#define MCB1_AOP 0x10 /* Active On Poll. */ -#define MCB1_MI 0x08 /* Mark Idle. */ -#define MCB1_AOU 0x04 /* Abort On Underrun. */ -#define MCB1_LM 0x02 /* Loop Mode. */ -#define MCB1_SIX 0x01 /* 6 or 12 bit SYNC. */ - -/* Miscellaneous Control Bits part 2 (WR14). */ -#define MCB2_NRZI 0xe0 /* DPLL - NRZI mode. */ -#define MCB2_FM 0xc0 /* DPLL - FM mode. */ -#define MCB2_RTXC 0xa0 /* DPLL - Clock from -RTxC. */ -#define MCB2_BRG 0x80 /* DPLL - Clock from BRG. */ -#define MCB2_OFF 0x60 /* DPLL - Disable. */ -#define MCB2_RMC 0x40 /* DPLL - Reset Missing Clock. */ -#define MCB2_ESM 0x20 /* DPLL - Enter Search Mode. */ -#define MCB2_LL 0x10 /* Local Loopback. */ -#define MCB2_AE 0x08 /* Auto Echo. */ -#define MCB2_REQ 0x04 /* Request Function. */ -#define MCB2_PCLK 0x02 /* BRG source is PCLK. */ -#define MCB2_BRGE 0x01 /* BRG enable. */ - -/* Master Interrupt Control (WR9). */ -#define MIC_FHR 0xc0 /* Force Hardware Reset. */ -#define MIC_CRA 0x80 /* Channel Reset A. */ -#define MIC_CRB 0x40 /* Channel Reset B. */ -#define MIC_SIE 0x20 /* Software INTACK Enable. */ -#define MIC_SH 0x10 /* Status High. */ -#define MIC_MIE 0x08 /* Master Interrupt Enable. */ -#define MIC_DLC 0x04 /* Disable Lower Chain. */ -#define MIC_NV 0x02 /* No Vector. */ -#define MIC_VIS 0x01 /* Vector Includes Status. */ - -/* Transmit/Receive Miscellaneous Parameters and Modes (WR4). */ -#define MPM_CM64 0xc0 /* X64 Clock Mode. */ -#define MPM_CM32 0x80 /* X32 Clock Mode. */ -#define MPM_CM16 0x40 /* X16 Clock Mode. */ -#define MPM_CM1 0x00 /* X1 Clock Mode. */ -#define MPM_EXT 0x30 /* External Sync Mode. */ -#define MPM_SDLC 0x20 /* SDLC mode. */ -#define MPM_BI 0x10 /* 16-bit Sync (bi-sync). */ -#define MPM_MONO 0x00 /* 8-bit Sync (mono-sync). */ -#define MPM_SB2 0x0c /* Async mode: 2 stopbits. */ -#define MPM_SB15 0x08 /* Async mode: 1.5 stopbits. */ -#define MPM_SB1 0x04 /* Async mode: 1 stopbit. */ -#define MPM_SYNC 0x00 /* Sync Mode Enable. */ -#define MPM_EVEN 0x02 /* Async mode: even parity. */ -#define MPM_PE 0x01 /* Async mode: parity enable. */ - -/* Receive Parameters and Control (WR3). */ -#define RPC_RB8 0xc0 /* 8 databits. */ -#define RPC_RB6 0x80 /* 6 databits. */ -#define RPC_RB7 0x40 /* 7 databits. */ -#define RPC_RB5 0x00 /* 5 databits. */ -#define RPC_AE 0x20 /* Auto Enable. */ -#define RPC_EHM 0x10 /* Enter Hunt Mode. */ -#define RPC_CRC 0x08 /* CRC Enable. */ -#define RPC_ASM 0x04 /* Address Search Mode. */ -#define RPC_LI 0x02 /* SYNC Character Load Inhibit */ -#define RPC_RXE 0x01 /* Receiver Enable */ - -/* Special Receive Condition (RR1). */ -#define SRC_EOF 0x80 /* End Of Frame. */ -#define SRC_FE 0x40 /* Framing Error. */ -#define SRC_OVR 0x20 /* Rx. Overrun. */ -#define SRC_PE 0x10 /* Parity Error. */ -#define SRC_RC0 0x08 /* Residue Code 0. */ -#define SRC_RC1 0x04 /* Residue Code 1. */ -#define SRC_RC2 0x02 /* Residue Code 2. */ -#define SRC_AS 0x01 /* All Sent. */ - -/* Transmit Parameter and Control (WR5). */ -#define TPC_DTR 0x80 /* DTR. */ -#define TPC_TB8 0x60 /* 8 databits. */ -#define TPC_TB6 0x40 /* 6 databits. */ -#define TPC_TB7 0x20 /* 7 databits. */ -#define TPC_TB5 0x00 /* 5 or fewer databits. */ -#define TPC_BRK 0x10 /* Send break. */ -#define TPC_TXE 0x08 /* Transmitter Enable. */ -#define TPC_CRC16 0x04 /* CRC16. */ -#define TPC_RTS 0x02 /* RTS. */ -#define TPC_CRC 0x01 /* CRC Enable. */ - -#endif /* _DEV_UART_DEV_Z8530_H_ */ |
