diff options
Diffstat (limited to 'sys/x86')
| -rw-r--r-- | sys/x86/x86/mca.c | 25 |
1 files changed, 17 insertions, 8 deletions
diff --git a/sys/x86/x86/mca.c b/sys/x86/x86/mca.c index b0e0672..1bb8854 100644 --- a/sys/x86/x86/mca.c +++ b/sys/x86/x86/mca.c @@ -254,15 +254,24 @@ mca_mute(const struct mca_record *rec) { /* - * Skip spurious corrected parity errors generated by desktop Haswell - * (see HSD131 erratum) unless reporting is enabled. - * Note that these errors also have been observed with D0-stepping, - * while the revision 014 desktop Haswell specification update only - * talks about C0-stepping. + * Skip spurious corrected parity errors generated by Intel Haswell- + * and Broadwell-based CPUs (see HSD131, HSM142, HSW131 and BDM48 + * erratum respectively), unless reporting is enabled. + * Note that these errors also have been observed with the D0-stepping + * of Haswell, while at least initially the CPU specification updates + * suggested only the C0-stepping to be affected. Similarly, Celeron + * 2955U with a CPU ID of 0x45 apparently are also concerned with the + * same problem, with HSM142 only referring to 0x3c and 0x46. */ - if (rec->mr_cpu_vendor_id == CPU_VENDOR_INTEL && - rec->mr_cpu_id == 0x306c3 && rec->mr_bank == 0 && - rec->mr_status == 0x90000040000f0005 && !intel6h_HSD131) + if (cpu_vendor_id == CPU_VENDOR_INTEL && + CPUID_TO_FAMILY(cpu_id) == 0x6 && + (CPUID_TO_MODEL(cpu_id) == 0x3c || /* HSD131, HSM142, HSW131 */ + CPUID_TO_MODEL(cpu_id) == 0x3d || /* BDM48 */ + CPUID_TO_MODEL(cpu_id) == 0x45 || + CPUID_TO_MODEL(cpu_id) == 0x46) && /* HSM142 */ + rec->mr_bank == 0 && + (rec->mr_status & 0xa0000000ffffffff) == 0x80000000000f0005 && + !intel6h_HSD131) return (1); return (0); |
