diff options
Diffstat (limited to 'sys/x86/isa')
| -rw-r--r-- | sys/x86/isa/atpic.c | 686 | ||||
| -rw-r--r-- | sys/x86/isa/atrtc.c | 331 | ||||
| -rw-r--r-- | sys/x86/isa/clock.c | 719 | ||||
| -rw-r--r-- | sys/x86/isa/elcr.c | 139 | ||||
| -rw-r--r-- | sys/x86/isa/icu.h | 53 | ||||
| -rw-r--r-- | sys/x86/isa/isa.c | 265 | ||||
| -rw-r--r-- | sys/x86/isa/isa.h | 102 | ||||
| -rw-r--r-- | sys/x86/isa/isa_dma.c | 611 | ||||
| -rw-r--r-- | sys/x86/isa/nmi.c | 107 | ||||
| -rw-r--r-- | sys/x86/isa/orm.c | 185 |
10 files changed, 3198 insertions, 0 deletions
diff --git a/sys/x86/isa/atpic.c b/sys/x86/isa/atpic.c new file mode 100644 index 0000000..d17153c --- /dev/null +++ b/sys/x86/isa/atpic.c @@ -0,0 +1,686 @@ +/*- + * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the author nor the names of any co-contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +/* + * PIC driver for the 8259A Master and Slave PICs in PC/AT machines. + */ + +#include <sys/cdefs.h> +__FBSDID("$FreeBSD$"); + +#include "opt_auto_eoi.h" +#include "opt_isa.h" + +#include <sys/param.h> +#include <sys/systm.h> +#include <sys/bus.h> +#include <sys/interrupt.h> +#include <sys/kernel.h> +#include <sys/lock.h> +#include <sys/module.h> + +#include <machine/cpufunc.h> +#include <machine/frame.h> +#include <machine/intr_machdep.h> +#include <machine/md_var.h> +#include <machine/resource.h> +#include <machine/segments.h> + +#include <dev/ic/i8259.h> +#include <x86/isa/icu.h> +#ifdef PC98 +#include <pc98/cbus/cbus.h> +#else +#include <x86/isa/isa.h> +#endif +#include <isa/isavar.h> + +#ifdef __amd64__ +#define SDT_ATPIC SDT_SYSIGT +#define GSEL_ATPIC 0 +#else +#define SDT_ATPIC SDT_SYS386IGT +#define GSEL_ATPIC GSEL(GCODE_SEL, SEL_KPL) +#endif + +#define MASTER 0 +#define SLAVE 1 + +/* + * PC-98 machines wire the slave 8259A to pin 7 on the master PIC, and + * PC-AT machines wire the slave PIC to pin 2 on the master PIC. + */ +#ifdef PC98 +#define ICU_SLAVEID 7 +#else +#define ICU_SLAVEID 2 +#endif + +/* + * Determine the base master and slave modes not including auto EOI support. + * All machines that FreeBSD supports use 8086 mode. + */ +#ifdef PC98 +/* + * PC-98 machines do not support auto EOI on the second PIC. Also, it + * seems that PC-98 machine PICs use buffered mode, and the master PIC + * uses special fully nested mode. + */ +#define BASE_MASTER_MODE (ICW4_SFNM | ICW4_BUF | ICW4_MS | ICW4_8086) +#define BASE_SLAVE_MODE (ICW4_BUF | ICW4_8086) +#else +#define BASE_MASTER_MODE ICW4_8086 +#define BASE_SLAVE_MODE ICW4_8086 +#endif + +/* Enable automatic EOI if requested. */ +#ifdef AUTO_EOI_1 +#define MASTER_MODE (BASE_MASTER_MODE | ICW4_AEOI) +#else +#define MASTER_MODE BASE_MASTER_MODE +#endif +#ifdef AUTO_EOI_2 +#define SLAVE_MODE (BASE_SLAVE_MODE | ICW4_AEOI) +#else +#define SLAVE_MODE BASE_SLAVE_MODE +#endif + +#define IRQ_MASK(irq) (1 << (irq)) +#define IMEN_MASK(ai) (IRQ_MASK((ai)->at_irq)) + +#define NUM_ISA_IRQS 16 + +static void atpic_init(void *dummy); + +unsigned int imen; /* XXX */ + +inthand_t + IDTVEC(atpic_intr0), IDTVEC(atpic_intr1), IDTVEC(atpic_intr2), + IDTVEC(atpic_intr3), IDTVEC(atpic_intr4), IDTVEC(atpic_intr5), + IDTVEC(atpic_intr6), IDTVEC(atpic_intr7), IDTVEC(atpic_intr8), + IDTVEC(atpic_intr9), IDTVEC(atpic_intr10), IDTVEC(atpic_intr11), + IDTVEC(atpic_intr12), IDTVEC(atpic_intr13), IDTVEC(atpic_intr14), + IDTVEC(atpic_intr15); + +#define IRQ(ap, ai) ((ap)->at_irqbase + (ai)->at_irq) + +#define ATPIC(io, base, eoi, imenptr) \ + { { atpic_enable_source, atpic_disable_source, (eoi), \ + atpic_enable_intr, atpic_disable_intr, atpic_vector, \ + atpic_source_pending, NULL, atpic_resume, atpic_config_intr,\ + atpic_assign_cpu }, (io), (base), IDT_IO_INTS + (base), \ + (imenptr) } + +#define INTSRC(irq) \ + { { &atpics[(irq) / 8].at_pic }, IDTVEC(atpic_intr ## irq ), \ + (irq) % 8 } + +struct atpic { + struct pic at_pic; + int at_ioaddr; + int at_irqbase; + uint8_t at_intbase; + uint8_t *at_imen; +}; + +struct atpic_intsrc { + struct intsrc at_intsrc; + inthand_t *at_intr; + int at_irq; /* Relative to PIC base. */ + enum intr_trigger at_trigger; + u_long at_count; + u_long at_straycount; +}; + +static void atpic_enable_source(struct intsrc *isrc); +static void atpic_disable_source(struct intsrc *isrc, int eoi); +static void atpic_eoi_master(struct intsrc *isrc); +static void atpic_eoi_slave(struct intsrc *isrc); +static void atpic_enable_intr(struct intsrc *isrc); +static void atpic_disable_intr(struct intsrc *isrc); +static int atpic_vector(struct intsrc *isrc); +static void atpic_resume(struct pic *pic); +static int atpic_source_pending(struct intsrc *isrc); +static int atpic_config_intr(struct intsrc *isrc, enum intr_trigger trig, + enum intr_polarity pol); +static int atpic_assign_cpu(struct intsrc *isrc, u_int apic_id); +static void i8259_init(struct atpic *pic, int slave); + +static struct atpic atpics[] = { + ATPIC(IO_ICU1, 0, atpic_eoi_master, (uint8_t *)&imen), + ATPIC(IO_ICU2, 8, atpic_eoi_slave, ((uint8_t *)&imen) + 1) +}; + +static struct atpic_intsrc atintrs[] = { + INTSRC(0), + INTSRC(1), + INTSRC(2), + INTSRC(3), + INTSRC(4), + INTSRC(5), + INTSRC(6), + INTSRC(7), + INTSRC(8), + INTSRC(9), + INTSRC(10), + INTSRC(11), + INTSRC(12), + INTSRC(13), + INTSRC(14), + INTSRC(15), +}; + +CTASSERT(sizeof(atintrs) / sizeof(atintrs[0]) == NUM_ISA_IRQS); + +static __inline void +_atpic_eoi_master(struct intsrc *isrc) +{ + + KASSERT(isrc->is_pic == &atpics[MASTER].at_pic, + ("%s: mismatched pic", __func__)); +#ifndef AUTO_EOI_1 + outb(atpics[MASTER].at_ioaddr, OCW2_EOI); +#endif +} + +/* + * The data sheet says no auto-EOI on slave, but it sometimes works. + * So, if AUTO_EOI_2 is enabled, we use it. + */ +static __inline void +_atpic_eoi_slave(struct intsrc *isrc) +{ + + KASSERT(isrc->is_pic == &atpics[SLAVE].at_pic, + ("%s: mismatched pic", __func__)); +#ifndef AUTO_EOI_2 + outb(atpics[SLAVE].at_ioaddr, OCW2_EOI); +#ifndef AUTO_EOI_1 + outb(atpics[MASTER].at_ioaddr, OCW2_EOI); +#endif +#endif +} + +static void +atpic_enable_source(struct intsrc *isrc) +{ + struct atpic_intsrc *ai = (struct atpic_intsrc *)isrc; + struct atpic *ap = (struct atpic *)isrc->is_pic; + + spinlock_enter(); + if (*ap->at_imen & IMEN_MASK(ai)) { + *ap->at_imen &= ~IMEN_MASK(ai); + outb(ap->at_ioaddr + ICU_IMR_OFFSET, *ap->at_imen); + } + spinlock_exit(); +} + +static void +atpic_disable_source(struct intsrc *isrc, int eoi) +{ + struct atpic_intsrc *ai = (struct atpic_intsrc *)isrc; + struct atpic *ap = (struct atpic *)isrc->is_pic; + + spinlock_enter(); + if (ai->at_trigger != INTR_TRIGGER_EDGE) { + *ap->at_imen |= IMEN_MASK(ai); + outb(ap->at_ioaddr + ICU_IMR_OFFSET, *ap->at_imen); + } + + /* + * Take care to call these functions directly instead of through + * a function pointer. All of the referenced variables should + * still be hot in the cache. + */ + if (eoi == PIC_EOI) { + if (isrc->is_pic == &atpics[MASTER].at_pic) + _atpic_eoi_master(isrc); + else + _atpic_eoi_slave(isrc); + } + + spinlock_exit(); +} + +static void +atpic_eoi_master(struct intsrc *isrc) +{ +#ifndef AUTO_EOI_1 + spinlock_enter(); + _atpic_eoi_master(isrc); + spinlock_exit(); +#endif +} + +static void +atpic_eoi_slave(struct intsrc *isrc) +{ +#ifndef AUTO_EOI_2 + spinlock_enter(); + _atpic_eoi_slave(isrc); + spinlock_exit(); +#endif +} + +static void +atpic_enable_intr(struct intsrc *isrc) +{ +} + +static void +atpic_disable_intr(struct intsrc *isrc) +{ +} + + +static int +atpic_vector(struct intsrc *isrc) +{ + struct atpic_intsrc *ai = (struct atpic_intsrc *)isrc; + struct atpic *ap = (struct atpic *)isrc->is_pic; + + return (IRQ(ap, ai)); +} + +static int +atpic_source_pending(struct intsrc *isrc) +{ + struct atpic_intsrc *ai = (struct atpic_intsrc *)isrc; + struct atpic *ap = (struct atpic *)isrc->is_pic; + + return (inb(ap->at_ioaddr) & IMEN_MASK(ai)); +} + +static void +atpic_resume(struct pic *pic) +{ + struct atpic *ap = (struct atpic *)pic; + + i8259_init(ap, ap == &atpics[SLAVE]); +#ifndef PC98 + if (ap == &atpics[SLAVE] && elcr_found) + elcr_resume(); +#endif +} + +static int +atpic_config_intr(struct intsrc *isrc, enum intr_trigger trig, + enum intr_polarity pol) +{ + struct atpic_intsrc *ai = (struct atpic_intsrc *)isrc; + u_int vector; + + /* Map conforming values to edge/hi and sanity check the values. */ + if (trig == INTR_TRIGGER_CONFORM) + trig = INTR_TRIGGER_EDGE; + if (pol == INTR_POLARITY_CONFORM) + pol = INTR_POLARITY_HIGH; + vector = atpic_vector(isrc); + if ((trig == INTR_TRIGGER_EDGE && pol == INTR_POLARITY_LOW) || + (trig == INTR_TRIGGER_LEVEL && pol == INTR_POLARITY_HIGH)) { + printf( + "atpic: Mismatched config for IRQ%u: trigger %s, polarity %s\n", + vector, trig == INTR_TRIGGER_EDGE ? "edge" : "level", + pol == INTR_POLARITY_HIGH ? "high" : "low"); + return (EINVAL); + } + + /* If there is no change, just return. */ + if (ai->at_trigger == trig) + return (0); + +#ifdef PC98 + if ((vector == 0 || vector == 1 || vector == 7 || vector == 8) && + trig == INTR_TRIGGER_LEVEL) { + if (bootverbose) + printf( + "atpic: Ignoring invalid level/low configuration for IRQ%u\n", + vector); + return (EINVAL); + } + return (ENXIO); +#else + /* + * Certain IRQs can never be level/lo, so don't try to set them + * that way if asked. At least some ELCR registers ignore setting + * these bits as well. + */ + if ((vector == 0 || vector == 1 || vector == 2 || vector == 13) && + trig == INTR_TRIGGER_LEVEL) { + if (bootverbose) + printf( + "atpic: Ignoring invalid level/low configuration for IRQ%u\n", + vector); + return (EINVAL); + } + if (!elcr_found) { + if (bootverbose) + printf("atpic: No ELCR to configure IRQ%u as %s\n", + vector, trig == INTR_TRIGGER_EDGE ? "edge/high" : + "level/low"); + return (ENXIO); + } + if (bootverbose) + printf("atpic: Programming IRQ%u as %s\n", vector, + trig == INTR_TRIGGER_EDGE ? "edge/high" : "level/low"); + spinlock_enter(); + elcr_write_trigger(atpic_vector(isrc), trig); + ai->at_trigger = trig; + spinlock_exit(); + return (0); +#endif /* PC98 */ +} + +static int +atpic_assign_cpu(struct intsrc *isrc, u_int apic_id) +{ + + /* + * 8259A's are only used in UP in which case all interrupts always + * go to the sole CPU and this function shouldn't even be called. + */ + panic("%s: bad cookie", __func__); +} + +static void +i8259_init(struct atpic *pic, int slave) +{ + int imr_addr; + + /* Reset the PIC and program with next four bytes. */ + spinlock_enter(); +#ifdef DEV_MCA + /* MCA uses level triggered interrupts. */ + if (MCA_system) + outb(pic->at_ioaddr, ICW1_RESET | ICW1_IC4 | ICW1_LTIM); + else +#endif + outb(pic->at_ioaddr, ICW1_RESET | ICW1_IC4); + imr_addr = pic->at_ioaddr + ICU_IMR_OFFSET; + + /* Start vector. */ + outb(imr_addr, pic->at_intbase); + + /* + * Setup slave links. For the master pic, indicate what line + * the slave is configured on. For the slave indicate + * which line on the master we are connected to. + */ + if (slave) + outb(imr_addr, ICU_SLAVEID); + else + outb(imr_addr, IRQ_MASK(ICU_SLAVEID)); + + /* Set mode. */ + if (slave) + outb(imr_addr, SLAVE_MODE); + else + outb(imr_addr, MASTER_MODE); + + /* Set interrupt enable mask. */ + outb(imr_addr, *pic->at_imen); + + /* Reset is finished, default to IRR on read. */ + outb(pic->at_ioaddr, OCW3_SEL | OCW3_RR); + +#ifndef PC98 + /* OCW2_L1 sets priority order to 3-7, 0-2 (com2 first). */ + if (!slave) + outb(pic->at_ioaddr, OCW2_R | OCW2_SL | OCW2_L1); +#endif + spinlock_exit(); +} + +void +atpic_startup(void) +{ + struct atpic_intsrc *ai; + int i; + + /* Start off with all interrupts disabled. */ + imen = 0xffff; + i8259_init(&atpics[MASTER], 0); + i8259_init(&atpics[SLAVE], 1); + atpic_enable_source((struct intsrc *)&atintrs[ICU_SLAVEID]); + + /* Install low-level interrupt handlers for all of our IRQs. */ + for (i = 0, ai = atintrs; i < NUM_ISA_IRQS; i++, ai++) { + if (i == ICU_SLAVEID) + continue; + ai->at_intsrc.is_count = &ai->at_count; + ai->at_intsrc.is_straycount = &ai->at_straycount; + setidt(((struct atpic *)ai->at_intsrc.is_pic)->at_intbase + + ai->at_irq, ai->at_intr, SDT_ATPIC, SEL_KPL, GSEL_ATPIC); + } + +#ifdef DEV_MCA + /* For MCA systems, all interrupts are level triggered. */ + if (MCA_system) + for (i = 0, ai = atintrs; i < NUM_ISA_IRQS; i++, ai++) + ai->at_trigger = INTR_TRIGGER_LEVEL; + else +#endif + +#ifdef PC98 + for (i = 0, ai = atintrs; i < NUM_ISA_IRQS; i++, ai++) + switch (i) { + case 0: + case 1: + case 7: + case 8: + ai->at_trigger = INTR_TRIGGER_EDGE; + break; + default: + ai->at_trigger = INTR_TRIGGER_LEVEL; + break; + } +#else + /* + * Look for an ELCR. If we find one, update the trigger modes. + * If we don't find one, assume that IRQs 0, 1, 2, and 13 are + * edge triggered and that everything else is level triggered. + * We only use the trigger information to reprogram the ELCR if + * we have one and as an optimization to avoid masking edge + * triggered interrupts. For the case that we don't have an ELCR, + * it doesn't hurt to mask an edge triggered interrupt, so we + * assume level trigger for any interrupt that we aren't sure is + * edge triggered. + */ + if (elcr_found) { + for (i = 0, ai = atintrs; i < NUM_ISA_IRQS; i++, ai++) + ai->at_trigger = elcr_read_trigger(i); + } else { + for (i = 0, ai = atintrs; i < NUM_ISA_IRQS; i++, ai++) + switch (i) { + case 0: + case 1: + case 2: + case 8: + case 13: + ai->at_trigger = INTR_TRIGGER_EDGE; + break; + default: + ai->at_trigger = INTR_TRIGGER_LEVEL; + break; + } + } +#endif /* PC98 */ +} + +static void +atpic_init(void *dummy __unused) +{ + struct atpic_intsrc *ai; + int i; + + /* + * Register our PICs, even if we aren't going to use any of their + * pins so that they are suspended and resumed. + */ + if (intr_register_pic(&atpics[0].at_pic) != 0 || + intr_register_pic(&atpics[1].at_pic) != 0) + panic("Unable to register ATPICs"); + + /* + * If any of the ISA IRQs have an interrupt source already, then + * assume that the APICs are being used and don't register any + * of our interrupt sources. This makes sure we don't accidentally + * use mixed mode. The "accidental" use could otherwise occur on + * machines that route the ACPI SCI interrupt to a different ISA + * IRQ (at least one machines routes it to IRQ 13) thus disabling + * that APIC ISA routing and allowing the ATPIC source for that IRQ + * to leak through. We used to depend on this feature for routing + * IRQ0 via mixed mode, but now we don't use mixed mode at all. + */ + for (i = 0; i < NUM_ISA_IRQS; i++) + if (intr_lookup_source(i) != NULL) + return; + + /* Loop through all interrupt sources and add them. */ + for (i = 0, ai = atintrs; i < NUM_ISA_IRQS; i++, ai++) { + if (i == ICU_SLAVEID) + continue; + intr_register_source(&ai->at_intsrc); + } +} +SYSINIT(atpic_init, SI_SUB_INTR, SI_ORDER_SECOND + 1, atpic_init, NULL); + +void +atpic_handle_intr(u_int vector, struct trapframe *frame) +{ + struct intsrc *isrc; + + KASSERT(vector < NUM_ISA_IRQS, ("unknown int %u\n", vector)); + isrc = &atintrs[vector].at_intsrc; + + /* + * If we don't have an event, see if this is a spurious + * interrupt. + */ + if (isrc->is_event == NULL && (vector == 7 || vector == 15)) { + int port, isr; + + /* + * Read the ISR register to see if IRQ 7/15 is really + * pending. Reset read register back to IRR when done. + */ + port = ((struct atpic *)isrc->is_pic)->at_ioaddr; + spinlock_enter(); + outb(port, OCW3_SEL | OCW3_RR | OCW3_RIS); + isr = inb(port); + outb(port, OCW3_SEL | OCW3_RR); + spinlock_exit(); + if ((isr & IRQ_MASK(7)) == 0) + return; + } + intr_execute_handlers(isrc, frame); +} + +#ifdef DEV_ISA +/* + * Bus attachment for the ISA PIC. + */ +static struct isa_pnp_id atpic_ids[] = { + { 0x0000d041 /* PNP0000 */, "AT interrupt controller" }, + { 0 } +}; + +static int +atpic_probe(device_t dev) +{ + int result; + + result = ISA_PNP_PROBE(device_get_parent(dev), dev, atpic_ids); + if (result <= 0) + device_quiet(dev); + return (result); +} + +/* + * We might be granted IRQ 2, as this is typically consumed by chaining + * between the two PIC components. If we're using the APIC, however, + * this may not be the case, and as such we should free the resource. + * (XXX untested) + * + * The generic ISA attachment code will handle allocating any other resources + * that we don't explicitly claim here. + */ +static int +atpic_attach(device_t dev) +{ + struct resource *res; + int rid; + + /* Try to allocate our IRQ and then free it. */ + rid = 0; + res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 0); + if (res != NULL) + bus_release_resource(dev, SYS_RES_IRQ, rid, res); + return (0); +} + +static device_method_t atpic_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, atpic_probe), + DEVMETHOD(device_attach, atpic_attach), + DEVMETHOD(device_detach, bus_generic_detach), + DEVMETHOD(device_shutdown, bus_generic_shutdown), + DEVMETHOD(device_suspend, bus_generic_suspend), + DEVMETHOD(device_resume, bus_generic_resume), + { 0, 0 } +}; + +static driver_t atpic_driver = { + "atpic", + atpic_methods, + 1, /* no softc */ +}; + +static devclass_t atpic_devclass; + +DRIVER_MODULE(atpic, isa, atpic_driver, atpic_devclass, 0, 0); +#ifndef PC98 +DRIVER_MODULE(atpic, acpi, atpic_driver, atpic_devclass, 0, 0); +#endif + +/* + * Return a bitmap of the current interrupt requests. This is 8259-specific + * and is only suitable for use at probe time. + */ +intrmask_t +isa_irq_pending(void) +{ + u_char irr1; + u_char irr2; + + irr1 = inb(IO_ICU1); + irr2 = inb(IO_ICU2); + return ((irr2 << 8) | irr1); +} +#endif /* DEV_ISA */ diff --git a/sys/x86/isa/atrtc.c b/sys/x86/isa/atrtc.c new file mode 100644 index 0000000..777c720 --- /dev/null +++ b/sys/x86/isa/atrtc.c @@ -0,0 +1,331 @@ +/*- + * Copyright (c) 2008 Poul-Henning Kamp + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#include <sys/cdefs.h> +__FBSDID("$FreeBSD$"); + +#include "opt_isa.h" + +#include <sys/param.h> +#include <sys/systm.h> +#include <sys/bus.h> +#include <sys/clock.h> +#include <sys/lock.h> +#include <sys/mutex.h> +#include <sys/kernel.h> +#include <sys/module.h> + +#include <isa/rtc.h> +#ifdef DEV_ISA +#include <isa/isareg.h> +#include <isa/isavar.h> +#endif + +#define RTC_LOCK mtx_lock_spin(&clock_lock) +#define RTC_UNLOCK mtx_unlock_spin(&clock_lock) + +int atrtcclock_disable = 0; + +static int rtc_reg = -1; +static u_char rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF; +static u_char rtc_statusb = RTCSB_24HR; + +/* + * RTC support routines + */ + +int +rtcin(int reg) +{ + u_char val; + + RTC_LOCK; + if (rtc_reg != reg) { + inb(0x84); + outb(IO_RTC, reg); + rtc_reg = reg; + inb(0x84); + } + val = inb(IO_RTC + 1); + RTC_UNLOCK; + return (val); +} + +void +writertc(int reg, u_char val) +{ + + RTC_LOCK; + if (rtc_reg != reg) { + inb(0x84); + outb(IO_RTC, reg); + rtc_reg = reg; + inb(0x84); + } + outb(IO_RTC + 1, val); + inb(0x84); + RTC_UNLOCK; +} + +static __inline int +readrtc(int port) +{ + return(bcd2bin(rtcin(port))); +} + +void +atrtc_start(void) +{ + + writertc(RTC_STATUSA, rtc_statusa); + writertc(RTC_STATUSB, RTCSB_24HR); +} + +void +atrtc_rate(unsigned rate) +{ + + rtc_statusa = RTCSA_DIVIDER | rate; + writertc(RTC_STATUSA, rtc_statusa); +} + +void +atrtc_enable_intr(void) +{ + + rtc_statusb |= RTCSB_PINTR; + writertc(RTC_STATUSB, rtc_statusb); + rtcin(RTC_INTR); +} + +void +atrtc_restore(void) +{ + + /* Restore all of the RTC's "status" (actually, control) registers. */ + rtcin(RTC_STATUSA); /* dummy to get rtc_reg set */ + writertc(RTC_STATUSB, RTCSB_24HR); + writertc(RTC_STATUSA, rtc_statusa); + writertc(RTC_STATUSB, rtc_statusb); + rtcin(RTC_INTR); +} + +int +atrtc_setup_clock(void) +{ + int diag; + + if (atrtcclock_disable) + return (0); + + diag = rtcin(RTC_DIAG); + if (diag != 0) { + printf("RTC BIOS diagnostic error %b\n", + diag, RTCDG_BITS); + return (0); + } + + stathz = RTC_NOPROFRATE; + profhz = RTC_PROFRATE; + + return (1); +} + +/********************************************************************** + * RTC driver for subr_rtc + */ + +#include "clock_if.h" + +#include <sys/rman.h> + +struct atrtc_softc { + int port_rid, intr_rid; + struct resource *port_res; + struct resource *intr_res; +}; + +/* + * Attach to the ISA PnP descriptors for the timer and realtime clock. + */ +static struct isa_pnp_id atrtc_ids[] = { + { 0x000bd041 /* PNP0B00 */, "AT realtime clock" }, + { 0 } +}; + +static int +atrtc_probe(device_t dev) +{ + int result; + + device_set_desc(dev, "AT Real Time Clock"); + result = ISA_PNP_PROBE(device_get_parent(dev), dev, atrtc_ids); + /* ENXIO if wrong PnP-ID, ENOENT ifno PnP-ID, zero if good PnP-iD */ + if (result != ENOENT) + return(result); + /* All PC's have an RTC, and we're hosed without it, so... */ + return (BUS_PROBE_LOW_PRIORITY); +} + +static int +atrtc_attach(device_t dev) +{ + struct atrtc_softc *sc; + int i; + + /* + * Not that we need them or anything, but grab our resources + * so they show up, correctly attributed, in the big picture. + */ + + sc = device_get_softc(dev); + if (!(sc->port_res = bus_alloc_resource(dev, SYS_RES_IOPORT, + &sc->port_rid, IO_RTC, IO_RTC + 1, 2, RF_ACTIVE))) + device_printf(dev,"Warning: Couldn't map I/O.\n"); + if (!(sc->intr_res = bus_alloc_resource(dev, SYS_RES_IRQ, + &sc->intr_rid, 8, 8, 1, RF_ACTIVE))) + device_printf(dev,"Warning: Couldn't map Interrupt.\n"); + clock_register(dev, 1000000); + if (resource_int_value("atrtc", 0, "clock", &i) == 0 && i == 0) + atrtcclock_disable = 1; + return(0); +} + +static int +atrtc_resume(device_t dev) +{ + + atrtc_restore(); + return(0); +} + +static int +atrtc_settime(device_t dev __unused, struct timespec *ts) +{ + struct clocktime ct; + + clock_ts_to_ct(ts, &ct); + + /* Disable RTC updates and interrupts. */ + writertc(RTC_STATUSB, RTCSB_HALT | RTCSB_24HR); + + writertc(RTC_SEC, bin2bcd(ct.sec)); /* Write back Seconds */ + writertc(RTC_MIN, bin2bcd(ct.min)); /* Write back Minutes */ + writertc(RTC_HRS, bin2bcd(ct.hour)); /* Write back Hours */ + + writertc(RTC_WDAY, ct.dow + 1); /* Write back Weekday */ + writertc(RTC_DAY, bin2bcd(ct.day)); /* Write back Day */ + writertc(RTC_MONTH, bin2bcd(ct.mon)); /* Write back Month */ + writertc(RTC_YEAR, bin2bcd(ct.year % 100)); /* Write back Year */ +#ifdef USE_RTC_CENTURY + writertc(RTC_CENTURY, bin2bcd(ct.year / 100)); /* ... and Century */ +#endif + + /* Reenable RTC updates and interrupts. */ + writertc(RTC_STATUSB, rtc_statusb); + rtcin(RTC_INTR); + return (0); +} + +static int +atrtc_gettime(device_t dev, struct timespec *ts) +{ + struct clocktime ct; + int s; + + /* Look if we have a RTC present and the time is valid */ + if (!(rtcin(RTC_STATUSD) & RTCSD_PWR)) { + device_printf(dev, "WARNING: Battery failure indication\n"); + return (EINVAL); + } + + /* wait for time update to complete */ + /* If RTCSA_TUP is zero, we have at least 244us before next update */ + s = splhigh(); + while (rtcin(RTC_STATUSA) & RTCSA_TUP) { + splx(s); + s = splhigh(); + } + ct.nsec = 0; + ct.sec = readrtc(RTC_SEC); + ct.min = readrtc(RTC_MIN); + ct.hour = readrtc(RTC_HRS); + ct.day = readrtc(RTC_DAY); + ct.dow = readrtc(RTC_WDAY) - 1; + ct.mon = readrtc(RTC_MONTH); + ct.year = readrtc(RTC_YEAR); +#ifdef USE_RTC_CENTURY + ct.year += readrtc(RTC_CENTURY) * 100; +#else + ct.year += 2000; +#endif + /* Set dow = -1 because some clocks don't set it correctly. */ + ct.dow = -1; + return (clock_ct_to_ts(&ct, ts)); +} + +static device_method_t atrtc_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, atrtc_probe), + DEVMETHOD(device_attach, atrtc_attach), + DEVMETHOD(device_detach, bus_generic_detach), + DEVMETHOD(device_shutdown, bus_generic_shutdown), + DEVMETHOD(device_suspend, bus_generic_suspend), + /* XXX stop statclock? */ + DEVMETHOD(device_resume, atrtc_resume), + + /* clock interface */ + DEVMETHOD(clock_gettime, atrtc_gettime), + DEVMETHOD(clock_settime, atrtc_settime), + + { 0, 0 } +}; + +static driver_t atrtc_driver = { + "atrtc", + atrtc_methods, + sizeof(struct atrtc_softc), +}; + +static devclass_t atrtc_devclass; + +DRIVER_MODULE(atrtc, isa, atrtc_driver, atrtc_devclass, 0, 0); +DRIVER_MODULE(atrtc, acpi, atrtc_driver, atrtc_devclass, 0, 0); + +#include "opt_ddb.h" +#ifdef DDB +#include <ddb/ddb.h> + +DB_SHOW_COMMAND(rtc, rtc) +{ + printf("%02x/%02x/%02x %02x:%02x:%02x, A = %02x, B = %02x, C = %02x\n", + rtcin(RTC_YEAR), rtcin(RTC_MONTH), rtcin(RTC_DAY), + rtcin(RTC_HRS), rtcin(RTC_MIN), rtcin(RTC_SEC), + rtcin(RTC_STATUSA), rtcin(RTC_STATUSB), rtcin(RTC_INTR)); +} +#endif /* DDB */ diff --git a/sys/x86/isa/clock.c b/sys/x86/isa/clock.c new file mode 100644 index 0000000..6ced537 --- /dev/null +++ b/sys/x86/isa/clock.c @@ -0,0 +1,719 @@ +/*- + * Copyright (c) 1990 The Regents of the University of California. + * All rights reserved. + * + * This code is derived from software contributed to Berkeley by + * William Jolitz and Don Ahn. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * from: @(#)clock.c 7.2 (Berkeley) 5/12/91 + */ + +#include <sys/cdefs.h> +__FBSDID("$FreeBSD$"); + +/* + * Routines to handle clock hardware. + */ + +#ifndef __amd64__ +#include "opt_apic.h" +#endif +#include "opt_clock.h" +#include "opt_kdtrace.h" +#include "opt_isa.h" +#include "opt_mca.h" + +#include <sys/param.h> +#include <sys/systm.h> +#include <sys/bus.h> +#include <sys/lock.h> +#include <sys/kdb.h> +#include <sys/mutex.h> +#include <sys/proc.h> +#include <sys/timetc.h> +#include <sys/kernel.h> +#include <sys/module.h> +#include <sys/sched.h> +#include <sys/smp.h> +#include <sys/sysctl.h> + +#include <machine/clock.h> +#include <machine/cpu.h> +#include <machine/intr_machdep.h> +#include <machine/md_var.h> +#include <machine/apicvar.h> +#include <machine/ppireg.h> +#include <machine/timerreg.h> +#include <machine/smp.h> + +#include <isa/rtc.h> +#ifdef DEV_ISA +#include <isa/isareg.h> +#include <isa/isavar.h> +#endif + +#ifdef DEV_MCA +#include <i386/bios/mca_machdep.h> +#endif + +#ifdef KDTRACE_HOOKS +#include <sys/dtrace_bsd.h> +#endif + +#define TIMER_DIV(x) ((i8254_freq + (x) / 2) / (x)) + +int clkintr_pending; +static int pscnt = 1; +static int psdiv = 1; +#ifndef TIMER_FREQ +#define TIMER_FREQ 1193182 +#endif +u_int i8254_freq = TIMER_FREQ; +TUNABLE_INT("hw.i8254.freq", &i8254_freq); +int i8254_max_count; +static int i8254_real_max_count; + +struct mtx clock_lock; +static struct intsrc *i8254_intsrc; +static u_int32_t i8254_lastcount; +static u_int32_t i8254_offset; +static int (*i8254_pending)(struct intsrc *); +static int i8254_ticked; +static int using_atrtc_timer; +static enum lapic_clock using_lapic_timer = LAPIC_CLOCK_NONE; + +/* Values for timerX_state: */ +#define RELEASED 0 +#define RELEASE_PENDING 1 +#define ACQUIRED 2 +#define ACQUIRE_PENDING 3 + +static u_char timer2_state; + +static unsigned i8254_get_timecount(struct timecounter *tc); +static unsigned i8254_simple_get_timecount(struct timecounter *tc); +static void set_i8254_freq(u_int freq, int intr_freq); + +static struct timecounter i8254_timecounter = { + i8254_get_timecount, /* get_timecount */ + 0, /* no poll_pps */ + ~0u, /* counter_mask */ + 0, /* frequency */ + "i8254", /* name */ + 0 /* quality */ +}; + +int +hardclockintr(struct trapframe *frame) +{ + + if (PCPU_GET(cpuid) == 0) + hardclock(TRAPF_USERMODE(frame), TRAPF_PC(frame)); + else + hardclock_cpu(TRAPF_USERMODE(frame)); + return (FILTER_HANDLED); +} + +int +statclockintr(struct trapframe *frame) +{ + + profclockintr(frame); + statclock(TRAPF_USERMODE(frame)); + return (FILTER_HANDLED); +} + +int +profclockintr(struct trapframe *frame) +{ + + if (!using_atrtc_timer) + hardclockintr(frame); + if (profprocs != 0) + profclock(TRAPF_USERMODE(frame), TRAPF_PC(frame)); + return (FILTER_HANDLED); +} + +static int +clkintr(struct trapframe *frame) +{ + + if (timecounter->tc_get_timecount == i8254_get_timecount) { + mtx_lock_spin(&clock_lock); + if (i8254_ticked) + i8254_ticked = 0; + else { + i8254_offset += i8254_max_count; + i8254_lastcount = 0; + } + clkintr_pending = 0; + mtx_unlock_spin(&clock_lock); + } + KASSERT(using_lapic_timer == LAPIC_CLOCK_NONE, + ("clk interrupt enabled with lapic timer")); + +#ifdef KDTRACE_HOOKS + /* + * If the DTrace hooks are configured and a callback function + * has been registered, then call it to process the high speed + * timers. + */ + int cpu = PCPU_GET(cpuid); + if (lapic_cyclic_clock_func[cpu] != NULL) + (*lapic_cyclic_clock_func[cpu])(frame); +#endif + + if (using_atrtc_timer) { +#ifdef SMP + if (smp_started) + ipi_all_but_self(IPI_HARDCLOCK); +#endif + hardclockintr(frame); + } else { + if (--pscnt <= 0) { + pscnt = psratio; +#ifdef SMP + if (smp_started) + ipi_all_but_self(IPI_STATCLOCK); +#endif + statclockintr(frame); + } else { +#ifdef SMP + if (smp_started) + ipi_all_but_self(IPI_PROFCLOCK); +#endif + profclockintr(frame); + } + } + +#ifdef DEV_MCA + /* Reset clock interrupt by asserting bit 7 of port 0x61 */ + if (MCA_system) + outb(0x61, inb(0x61) | 0x80); +#endif + return (FILTER_HANDLED); +} + +int +timer_spkr_acquire(void) +{ + int mode; + + mode = TIMER_SEL2 | TIMER_SQWAVE | TIMER_16BIT; + + if (timer2_state != RELEASED) + return (-1); + timer2_state = ACQUIRED; + + /* + * This access to the timer registers is as atomic as possible + * because it is a single instruction. We could do better if we + * knew the rate. Use of splclock() limits glitches to 10-100us, + * and this is probably good enough for timer2, so we aren't as + * careful with it as with timer0. + */ + outb(TIMER_MODE, TIMER_SEL2 | (mode & 0x3f)); + ppi_spkr_on(); /* enable counter2 output to speaker */ + return (0); +} + +int +timer_spkr_release(void) +{ + + if (timer2_state != ACQUIRED) + return (-1); + timer2_state = RELEASED; + outb(TIMER_MODE, TIMER_SEL2 | TIMER_SQWAVE | TIMER_16BIT); + ppi_spkr_off(); /* disable counter2 output to speaker */ + return (0); +} + +void +timer_spkr_setfreq(int freq) +{ + + freq = i8254_freq / freq; + mtx_lock_spin(&clock_lock); + outb(TIMER_CNTR2, freq & 0xff); + outb(TIMER_CNTR2, freq >> 8); + mtx_unlock_spin(&clock_lock); +} + +/* + * This routine receives statistical clock interrupts from the RTC. + * As explained above, these occur at 128 interrupts per second. + * When profiling, we receive interrupts at a rate of 1024 Hz. + * + * This does not actually add as much overhead as it sounds, because + * when the statistical clock is active, the hardclock driver no longer + * needs to keep (inaccurate) statistics on its own. This decouples + * statistics gathering from scheduling interrupts. + * + * The RTC chip requires that we read status register C (RTC_INTR) + * to acknowledge an interrupt, before it will generate the next one. + * Under high interrupt load, rtcintr() can be indefinitely delayed and + * the clock can tick immediately after the read from RTC_INTR. In this + * case, the mc146818A interrupt signal will not drop for long enough + * to register with the 8259 PIC. If an interrupt is missed, the stat + * clock will halt, considerably degrading system performance. This is + * why we use 'while' rather than a more straightforward 'if' below. + * Stat clock ticks can still be lost, causing minor loss of accuracy + * in the statistics, but the stat clock will no longer stop. + */ +static int +rtcintr(struct trapframe *frame) +{ + int flag = 0; + + while (rtcin(RTC_INTR) & RTCIR_PERIOD) { + flag = 1; + if (--pscnt <= 0) { + pscnt = psdiv; +#ifdef SMP + if (smp_started) + ipi_all_but_self(IPI_STATCLOCK); +#endif + statclockintr(frame); + } else { +#ifdef SMP + if (smp_started) + ipi_all_but_self(IPI_PROFCLOCK); +#endif + profclockintr(frame); + } + } + return(flag ? FILTER_HANDLED : FILTER_STRAY); +} + +static int +getit(void) +{ + int high, low; + + mtx_lock_spin(&clock_lock); + + /* Select timer0 and latch counter value. */ + outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH); + + low = inb(TIMER_CNTR0); + high = inb(TIMER_CNTR0); + + mtx_unlock_spin(&clock_lock); + return ((high << 8) | low); +} + +/* + * Wait "n" microseconds. + * Relies on timer 1 counting down from (i8254_freq / hz) + * Note: timer had better have been programmed before this is first used! + */ +void +DELAY(int n) +{ + int delta, prev_tick, tick, ticks_left; + +#ifdef DELAYDEBUG + int getit_calls = 1; + int n1; + static int state = 0; +#endif + + if (tsc_freq != 0 && !tsc_is_broken) { + uint64_t start, end, now; + + sched_pin(); + start = rdtsc(); + end = start + (tsc_freq * n) / 1000000; + do { + cpu_spinwait(); + now = rdtsc(); + } while (now < end || (now > start && end < start)); + sched_unpin(); + return; + } +#ifdef DELAYDEBUG + if (state == 0) { + state = 1; + for (n1 = 1; n1 <= 10000000; n1 *= 10) + DELAY(n1); + state = 2; + } + if (state == 1) + printf("DELAY(%d)...", n); +#endif + /* + * Read the counter first, so that the rest of the setup overhead is + * counted. Guess the initial overhead is 20 usec (on most systems it + * takes about 1.5 usec for each of the i/o's in getit(). The loop + * takes about 6 usec on a 486/33 and 13 usec on a 386/20. The + * multiplications and divisions to scale the count take a while). + * + * However, if ddb is active then use a fake counter since reading + * the i8254 counter involves acquiring a lock. ddb must not do + * locking for many reasons, but it calls here for at least atkbd + * input. + */ +#ifdef KDB + if (kdb_active) + prev_tick = 1; + else +#endif + prev_tick = getit(); + n -= 0; /* XXX actually guess no initial overhead */ + /* + * Calculate (n * (i8254_freq / 1e6)) without using floating point + * and without any avoidable overflows. + */ + if (n <= 0) + ticks_left = 0; + else if (n < 256) + /* + * Use fixed point to avoid a slow division by 1000000. + * 39099 = 1193182 * 2^15 / 10^6 rounded to nearest. + * 2^15 is the first power of 2 that gives exact results + * for n between 0 and 256. + */ + ticks_left = ((u_int)n * 39099 + (1 << 15) - 1) >> 15; + else + /* + * Don't bother using fixed point, although gcc-2.7.2 + * generates particularly poor code for the long long + * division, since even the slow way will complete long + * before the delay is up (unless we're interrupted). + */ + ticks_left = ((u_int)n * (long long)i8254_freq + 999999) + / 1000000; + + while (ticks_left > 0) { +#ifdef KDB + if (kdb_active) { + inb(0x84); + tick = prev_tick - 1; + if (tick <= 0) + tick = i8254_max_count; + } else +#endif + tick = getit(); +#ifdef DELAYDEBUG + ++getit_calls; +#endif + delta = prev_tick - tick; + prev_tick = tick; + if (delta < 0) { + delta += i8254_max_count; + /* + * Guard against i8254_max_count being wrong. + * This shouldn't happen in normal operation, + * but it may happen if set_i8254_freq() is + * traced. + */ + if (delta < 0) + delta = 0; + } + ticks_left -= delta; + } +#ifdef DELAYDEBUG + if (state == 1) + printf(" %d calls to getit() at %d usec each\n", + getit_calls, (n + 5) / getit_calls); +#endif +} + +static void +set_i8254_freq(u_int freq, int intr_freq) +{ + int new_i8254_real_max_count; + + i8254_timecounter.tc_frequency = freq; + mtx_lock_spin(&clock_lock); + i8254_freq = freq; + if (using_lapic_timer != LAPIC_CLOCK_NONE) + new_i8254_real_max_count = 0x10000; + else + new_i8254_real_max_count = TIMER_DIV(intr_freq); + if (new_i8254_real_max_count != i8254_real_max_count) { + i8254_real_max_count = new_i8254_real_max_count; + if (i8254_real_max_count == 0x10000) + i8254_max_count = 0xffff; + else + i8254_max_count = i8254_real_max_count; + outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); + outb(TIMER_CNTR0, i8254_real_max_count & 0xff); + outb(TIMER_CNTR0, i8254_real_max_count >> 8); + } + mtx_unlock_spin(&clock_lock); +} + +static void +i8254_restore(void) +{ + + mtx_lock_spin(&clock_lock); + outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); + outb(TIMER_CNTR0, i8254_real_max_count & 0xff); + outb(TIMER_CNTR0, i8254_real_max_count >> 8); + mtx_unlock_spin(&clock_lock); +} + +#ifndef __amd64__ +/* + * Restore all the timers non-atomically (XXX: should be atomically). + * + * This function is called from pmtimer_resume() to restore all the timers. + * This should not be necessary, but there are broken laptops that do not + * restore all the timers on resume. + * As long as pmtimer is not part of amd64 suport, skip this for the amd64 + * case. + */ +void +timer_restore(void) +{ + + i8254_restore(); /* restore i8254_freq and hz */ + atrtc_restore(); /* reenable RTC interrupts */ +} +#endif + +/* This is separate from startrtclock() so that it can be called early. */ +void +i8254_init(void) +{ + + mtx_init(&clock_lock, "clk", NULL, MTX_SPIN | MTX_NOPROFILE); + set_i8254_freq(i8254_freq, hz); +} + +void +startrtclock() +{ + + atrtc_start(); + + set_i8254_freq(i8254_freq, hz); + tc_init(&i8254_timecounter); + + init_TSC(); +} + +/* + * Start both clocks running. + */ +void +cpu_initclocks() +{ + +#if defined(__amd64__) || defined(DEV_APIC) + using_lapic_timer = lapic_setup_clock(); +#endif + /* + * If we aren't using the local APIC timer to drive the kernel + * clocks, setup the interrupt handler for the 8254 timer 0 so + * that it can drive hardclock(). Otherwise, change the 8254 + * timecounter to user a simpler algorithm. + */ + if (using_lapic_timer == LAPIC_CLOCK_NONE) { + intr_add_handler("clk", 0, (driver_filter_t *)clkintr, NULL, + NULL, INTR_TYPE_CLK, NULL); + i8254_intsrc = intr_lookup_source(0); + if (i8254_intsrc != NULL) + i8254_pending = + i8254_intsrc->is_pic->pic_source_pending; + } else { + i8254_timecounter.tc_get_timecount = + i8254_simple_get_timecount; + i8254_timecounter.tc_counter_mask = 0xffff; + set_i8254_freq(i8254_freq, hz); + } + + /* Initialize RTC. */ + atrtc_start(); + + /* + * If the separate statistics clock hasn't been explicility disabled + * and we aren't already using the local APIC timer to drive the + * kernel clocks, then setup the RTC to periodically interrupt to + * drive statclock() and profclock(). + */ + if (using_lapic_timer != LAPIC_CLOCK_ALL) { + using_atrtc_timer = atrtc_setup_clock(); + if (using_atrtc_timer) { + /* Enable periodic interrupts from the RTC. */ + intr_add_handler("rtc", 8, + (driver_filter_t *)rtcintr, NULL, NULL, + INTR_TYPE_CLK, NULL); + atrtc_enable_intr(); + } else { + profhz = hz; + if (hz < 128) + stathz = hz; + else + stathz = hz / (hz / 128); + } + } + + init_TSC_tc(); +} + +void +cpu_startprofclock(void) +{ + + if (using_lapic_timer == LAPIC_CLOCK_ALL || !using_atrtc_timer) + return; + atrtc_rate(RTCSA_PROF); + psdiv = pscnt = psratio; +} + +void +cpu_stopprofclock(void) +{ + + if (using_lapic_timer == LAPIC_CLOCK_ALL || !using_atrtc_timer) + return; + atrtc_rate(RTCSA_NOPROF); + psdiv = pscnt = 1; +} + +static int +sysctl_machdep_i8254_freq(SYSCTL_HANDLER_ARGS) +{ + int error; + u_int freq; + + /* + * Use `i8254' instead of `timer' in external names because `timer' + * is is too generic. Should use it everywhere. + */ + freq = i8254_freq; + error = sysctl_handle_int(oidp, &freq, 0, req); + if (error == 0 && req->newptr != NULL) + set_i8254_freq(freq, hz); + return (error); +} + +SYSCTL_PROC(_machdep, OID_AUTO, i8254_freq, CTLTYPE_INT | CTLFLAG_RW, + 0, sizeof(u_int), sysctl_machdep_i8254_freq, "IU", ""); + +static unsigned +i8254_simple_get_timecount(struct timecounter *tc) +{ + + return (i8254_max_count - getit()); +} + +static unsigned +i8254_get_timecount(struct timecounter *tc) +{ + register_t flags; + u_int count; + u_int high, low; + +#ifdef __amd64__ + flags = read_rflags(); +#else + flags = read_eflags(); +#endif + mtx_lock_spin(&clock_lock); + + /* Select timer0 and latch counter value. */ + outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH); + + low = inb(TIMER_CNTR0); + high = inb(TIMER_CNTR0); + count = i8254_max_count - ((high << 8) | low); + if (count < i8254_lastcount || + (!i8254_ticked && (clkintr_pending || + ((count < 20 || (!(flags & PSL_I) && + count < i8254_max_count / 2u)) && + i8254_pending != NULL && i8254_pending(i8254_intsrc))))) { + i8254_ticked = 1; + i8254_offset += i8254_max_count; + } + i8254_lastcount = count; + count += i8254_offset; + mtx_unlock_spin(&clock_lock); + return (count); +} + +#ifdef DEV_ISA +/* + * Attach to the ISA PnP descriptors for the timer + */ +static struct isa_pnp_id attimer_ids[] = { + { 0x0001d041 /* PNP0100 */, "AT timer" }, + { 0 } +}; + +static int +attimer_probe(device_t dev) +{ + int result; + + result = ISA_PNP_PROBE(device_get_parent(dev), dev, attimer_ids); + if (result <= 0) + device_quiet(dev); + return(result); +} + +static int +attimer_attach(device_t dev) +{ + return(0); +} + +static int +attimer_resume(device_t dev) +{ + + i8254_restore(); + return (0); +} + +static device_method_t attimer_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, attimer_probe), + DEVMETHOD(device_attach, attimer_attach), + DEVMETHOD(device_detach, bus_generic_detach), + DEVMETHOD(device_shutdown, bus_generic_shutdown), + DEVMETHOD(device_suspend, bus_generic_suspend), + DEVMETHOD(device_resume, attimer_resume), + { 0, 0 } +}; + +static driver_t attimer_driver = { + "attimer", + attimer_methods, + 1, /* no softc */ +}; + +static devclass_t attimer_devclass; + +DRIVER_MODULE(attimer, isa, attimer_driver, attimer_devclass, 0, 0); +DRIVER_MODULE(attimer, acpi, attimer_driver, attimer_devclass, 0, 0); + +#endif /* DEV_ISA */ diff --git a/sys/x86/isa/elcr.c b/sys/x86/isa/elcr.c new file mode 100644 index 0000000..266d783 --- /dev/null +++ b/sys/x86/isa/elcr.c @@ -0,0 +1,139 @@ +/*- + * Copyright (c) 2004 John Baldwin <jhb@FreeBSD.org> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the author nor the names of any co-contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <sys/cdefs.h> +__FBSDID("$FreeBSD$"); + +/* + * The ELCR is a register that controls the trigger mode and polarity of + * EISA and ISA interrupts. In FreeBSD 3.x and 4.x, the ELCR was only + * consulted for determining the appropriate trigger mode of EISA + * interrupts when using an APIC. However, it seems that almost all + * systems that include PCI also include an ELCR that manages the ISA + * IRQs 0 through 15. Thus, we check for the presence of an ELCR on + * every machine by checking to see if the values found at bootup are + * sane. Note that the polarity of ISA and EISA IRQs are linked to the + * trigger mode. All edge triggered IRQs use active-hi polarity, and + * all level triggered interrupts use active-lo polarity. + * + * The format of the ELCR is simple: it is a 16-bit bitmap where bit 0 + * controls IRQ 0, bit 1 controls IRQ 1, etc. If the bit is zero, the + * associated IRQ is edge triggered. If the bit is one, the IRQ is + * level triggered. + */ + +#include <sys/param.h> +#include <sys/bus.h> +#include <sys/systm.h> +#include <machine/intr_machdep.h> + +#define ELCR_PORT 0x4d0 +#define ELCR_MASK(irq) (1 << (irq)) + +static int elcr_status; +int elcr_found; + +/* + * Check to see if we have what looks like a valid ELCR. We do this by + * verifying that IRQs 0, 1, 2, and 13 are all edge triggered. + */ +int +elcr_probe(void) +{ + int i; + + elcr_status = inb(ELCR_PORT) | inb(ELCR_PORT + 1) << 8; + if ((elcr_status & (ELCR_MASK(0) | ELCR_MASK(1) | ELCR_MASK(2) | + ELCR_MASK(8) | ELCR_MASK(13))) != 0) + return (ENXIO); + if (bootverbose) { + printf("ELCR Found. ISA IRQs programmed as:\n"); + for (i = 0; i < 16; i++) + printf(" %2d", i); + printf("\n"); + for (i = 0; i < 16; i++) + if (elcr_status & ELCR_MASK(i)) + printf(" L"); + else + printf(" E"); + printf("\n"); + } + if (resource_disabled("elcr", 0)) + return (ENXIO); + elcr_found = 1; + return (0); +} + +/* + * Returns 1 for level trigger, 0 for edge. + */ +enum intr_trigger +elcr_read_trigger(u_int irq) +{ + + KASSERT(elcr_found, ("%s: no ELCR was found!", __func__)); + KASSERT(irq <= 15, ("%s: invalid IRQ %u", __func__, irq)); + if (elcr_status & ELCR_MASK(irq)) + return (INTR_TRIGGER_LEVEL); + else + return (INTR_TRIGGER_EDGE); +} + +/* + * Set the trigger mode for a specified IRQ. Mode of 0 means edge triggered, + * and a mode of 1 means level triggered. + */ +void +elcr_write_trigger(u_int irq, enum intr_trigger trigger) +{ + int new_status; + + KASSERT(elcr_found, ("%s: no ELCR was found!", __func__)); + KASSERT(irq <= 15, ("%s: invalid IRQ %u", __func__, irq)); + if (trigger == INTR_TRIGGER_LEVEL) + new_status = elcr_status | ELCR_MASK(irq); + else + new_status = elcr_status & ~ELCR_MASK(irq); + if (new_status == elcr_status) + return; + elcr_status = new_status; + if (irq >= 8) + outb(ELCR_PORT + 1, elcr_status >> 8); + else + outb(ELCR_PORT, elcr_status & 0xff); +} + +void +elcr_resume(void) +{ + + KASSERT(elcr_found, ("%s: no ELCR was found!", __func__)); + outb(ELCR_PORT, elcr_status & 0xff); + outb(ELCR_PORT + 1, elcr_status >> 8); +} diff --git a/sys/x86/isa/icu.h b/sys/x86/isa/icu.h new file mode 100644 index 0000000..d7cd87a --- /dev/null +++ b/sys/x86/isa/icu.h @@ -0,0 +1,53 @@ +/*- + * Copyright (c) 1990 The Regents of the University of California. + * All rights reserved. + * + * This code is derived from software contributed to Berkeley by + * William Jolitz. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * from: @(#)icu.h 5.6 (Berkeley) 5/9/91 + * $FreeBSD$ + */ + +/* + * AT/386 Interrupt Control constants + * W. Jolitz 8/89 + */ + +#ifndef _X86_ISA_ICU_H_ +#define _X86_ISA_ICU_H_ + +#ifdef PC98 +#define ICU_IMR_OFFSET 2 +#else +#define ICU_IMR_OFFSET 1 +#endif + +void atpic_handle_intr(u_int vector, struct trapframe *frame); +void atpic_startup(void); + +#endif /* !_X86_ISA_ICU_H_ */ diff --git a/sys/x86/isa/isa.c b/sys/x86/isa/isa.c new file mode 100644 index 0000000..7b2982a --- /dev/null +++ b/sys/x86/isa/isa.c @@ -0,0 +1,265 @@ +/*- + * Copyright (c) 1998 Doug Rabson + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <sys/cdefs.h> +__FBSDID("$FreeBSD$"); + +/*- + * Modifications for Intel architecture by Garrett A. Wollman. + * Copyright 1998 Massachusetts Institute of Technology + * + * Permission to use, copy, modify, and distribute this software and + * its documentation for any purpose and without fee is hereby + * granted, provided that both the above copyright notice and this + * permission notice appear in all copies, that both the above + * copyright notice and this permission notice appear in all + * supporting documentation, and that the name of M.I.T. not be used + * in advertising or publicity pertaining to distribution of the + * software without specific, written prior permission. M.I.T. makes + * no representations about the suitability of this software for any + * purpose. It is provided "as is" without express or implied + * warranty. + * + * THIS SOFTWARE IS PROVIDED BY M.I.T. ``AS IS''. M.I.T. DISCLAIMS + * ALL EXPRESS OR IMPLIED WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT + * SHALL M.I.T. BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <sys/param.h> +#include <sys/bus.h> +#include <sys/kernel.h> +#include <sys/malloc.h> +#include <sys/module.h> +#include <machine/bus.h> +#include <sys/rman.h> +#ifdef PC98 +#include <sys/systm.h> +#endif + +#include <machine/resource.h> + +#include <isa/isavar.h> +#include <isa/isa_common.h> + +void +isa_init(device_t dev) +{ +} + +/* + * This implementation simply passes the request up to the parent + * bus, which in our case is the special i386 nexus, substituting any + * configured values if the caller defaulted. We can get away with + * this because there is no special mapping for ISA resources on an Intel + * platform. When porting this code to another architecture, it may be + * necessary to interpose a mapping layer here. + */ +struct resource * +isa_alloc_resource(device_t bus, device_t child, int type, int *rid, + u_long start, u_long end, u_long count, u_int flags) +{ + /* + * Consider adding a resource definition. + */ + int passthrough = (device_get_parent(child) != bus); + int isdefault = (start == 0UL && end == ~0UL); + struct isa_device* idev = DEVTOISA(child); + struct resource_list *rl = &idev->id_resources; + struct resource_list_entry *rle; + + if (!passthrough && !isdefault) { + rle = resource_list_find(rl, type, *rid); + if (!rle) { + if (*rid < 0) + return 0; + switch (type) { + case SYS_RES_IRQ: + if (*rid >= ISA_NIRQ) + return 0; + break; + case SYS_RES_DRQ: + if (*rid >= ISA_NDRQ) + return 0; + break; + case SYS_RES_MEMORY: + if (*rid >= ISA_NMEM) + return 0; + break; + case SYS_RES_IOPORT: + if (*rid >= ISA_NPORT) + return 0; + break; + default: + return 0; + } + resource_list_add(rl, type, *rid, start, end, count); + } + } + + return resource_list_alloc(rl, bus, child, type, rid, + start, end, count, flags); +} + +#ifdef PC98 +/* + * Indirection support. The type of bus_space_handle_t is + * defined in sys/i386/include/bus_pc98.h. + */ +struct resource * +isa_alloc_resourcev(device_t child, int type, int *rid, + bus_addr_t *res, bus_size_t count, u_int flags) +{ + struct isa_device* idev = DEVTOISA(child); + struct resource_list *rl = &idev->id_resources; + + device_t bus = device_get_parent(child); + bus_addr_t start; + bus_space_handle_t bh; + struct resource *re; + struct resource **bsre; + int i, j, k, linear_cnt, ressz, bsrid; + + start = bus_get_resource_start(child, type, *rid); + + linear_cnt = count; + ressz = 1; + for (i = 1; i < count; ++i) { + if (res[i] != res[i - 1] + 1) { + if (i < linear_cnt) + linear_cnt = i; + ++ressz; + } + } + + re = isa_alloc_resource(bus, child, type, rid, + start + res[0], start + res[linear_cnt - 1], + linear_cnt, flags); + if (re == NULL) + return NULL; + + bsre = malloc(sizeof (struct resource *) * ressz, M_DEVBUF, M_NOWAIT); + if (bsre == NULL) { + resource_list_release(rl, bus, child, type, *rid, re); + return NULL; + } + bsre[0] = re; + + for (i = linear_cnt, k = 1; i < count; i = j, k++) { + for (j = i + 1; j < count; j++) { + if (res[j] != res[j - 1] + 1) + break; + } + bsrid = *rid + k; + bsre[k] = isa_alloc_resource(bus, child, type, &bsrid, + start + res[i], start + res[j - 1], j - i, flags); + if (bsre[k] == NULL) { + for (k--; k >= 0; k--) + resource_list_release(rl, bus, child, type, + *rid + k, bsre[k]); + free(bsre, M_DEVBUF); + return NULL; + } + } + + bh = rman_get_bushandle(re); + bh->bsh_res = bsre; + bh->bsh_ressz = ressz; + + return re; +} + +int +isa_load_resourcev(struct resource *re, bus_addr_t *res, bus_size_t count) +{ + + return bus_space_map_load(rman_get_bustag(re), rman_get_bushandle(re), + count, res, 0); +} +#endif /* PC98 */ + +int +isa_release_resource(device_t bus, device_t child, int type, int rid, + struct resource *r) +{ + struct isa_device* idev = DEVTOISA(child); + struct resource_list *rl = &idev->id_resources; +#ifdef PC98 + /* + * Indirection support. The type of bus_space_handle_t is + * defined in sys/i386/include/bus_pc98.h. + */ + int i; + bus_space_handle_t bh; + + if (type == SYS_RES_MEMORY || type == SYS_RES_IOPORT) { + bh = rman_get_bushandle(r); + if (bh != NULL) { + for (i = 1; i < bh->bsh_ressz; i++) + resource_list_release(rl, bus, child, type, + rid + i, bh->bsh_res[i]); + if (bh->bsh_res != NULL) + free(bh->bsh_res, M_DEVBUF); + } + } +#endif + return resource_list_release(rl, bus, child, type, rid, r); +} + +/* + * We can't use the bus_generic_* versions of these methods because those + * methods always pass the bus param as the requesting device, and we need + * to pass the child (the i386 nexus knows about this and is prepared to + * deal). + */ +int +isa_setup_intr(device_t bus, device_t child, struct resource *r, int flags, + driver_filter_t *filter, void (*ihand)(void *), void *arg, + void **cookiep) +{ + return (BUS_SETUP_INTR(device_get_parent(bus), child, r, flags, + filter, ihand, arg, cookiep)); +} + +int +isa_teardown_intr(device_t bus, device_t child, struct resource *r, + void *cookie) +{ + return (BUS_TEARDOWN_INTR(device_get_parent(bus), child, r, cookie)); +} + +/* + * On this platform, isa can also attach to the legacy bus. + */ +DRIVER_MODULE(isa, legacy, isa_driver, isa_devclass, 0, 0); diff --git a/sys/x86/isa/isa.h b/sys/x86/isa/isa.h new file mode 100644 index 0000000..78bd956 --- /dev/null +++ b/sys/x86/isa/isa.h @@ -0,0 +1,102 @@ +/*- + * Copyright (c) 1990 The Regents of the University of California. + * All rights reserved. + * + * This code is derived from software contributed to Berkeley by + * William Jolitz. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * from: @(#)isa.h 5.7 (Berkeley) 5/9/91 + * $FreeBSD$ + */ + +#ifdef PC98 +#error isa.h is included from PC-9801 source +#endif + +#ifndef _X86_ISA_ISA_H_ +#define _X86_ISA_ISA_H_ + +/* BEWARE: Included in both assembler and C code */ + +/* + * ISA Bus conventions + */ + +/* + * Input / Output Port Assignments + */ +#ifndef IO_ISABEGIN +#define IO_ISABEGIN 0x000 /* 0x000 - Beginning of I/O Registers */ + + /* CPU Board */ +#define IO_ICU1 0x020 /* 8259A Interrupt Controller #1 */ +#define IO_PMP1 0x026 /* 82347 Power Management Peripheral */ +#define IO_KBD 0x060 /* 8042 Keyboard */ +#define IO_RTC 0x070 /* RTC */ +#define IO_NMI IO_RTC /* NMI Control */ +#define IO_ICU2 0x0A0 /* 8259A Interrupt Controller #2 */ + + /* Cards */ +#define IO_VGA 0x3C0 /* E/VGA Ports */ +#define IO_CGA 0x3D0 /* CGA Ports */ +#define IO_MDA 0x3B0 /* Monochome Adapter */ + +#define IO_ISAEND 0x3FF /* End (actually Max) of I/O Regs */ +#endif /* !IO_ISABEGIN */ + +/* + * Input / Output Port Sizes - these are from several sources, and tend + * to be the larger of what was found. + */ +#ifndef IO_ISASIZES +#define IO_ISASIZES + +#define IO_CGASIZE 12 /* CGA controllers */ +#define IO_MDASIZE 12 /* Monochrome display controllers */ +#define IO_VGASIZE 16 /* VGA controllers */ + +#endif /* !IO_ISASIZES */ + +/* + * Input / Output Memory Physical Addresses + */ +#ifndef IOM_BEGIN +#define IOM_BEGIN 0x0A0000 /* Start of I/O Memory "hole" */ +#define IOM_END 0x100000 /* End of I/O Memory "hole" */ +#define IOM_SIZE (IOM_END - IOM_BEGIN) +#endif /* !IOM_BEGIN */ + +/* + * RAM Physical Address Space (ignoring the above mentioned "hole") + */ +#ifndef RAM_BEGIN +#define RAM_BEGIN 0x0000000 /* Start of RAM Memory */ +#define RAM_END 0x1000000 /* End of RAM Memory */ +#define RAM_SIZE (RAM_END - RAM_BEGIN) +#endif /* !RAM_BEGIN */ + +#endif /* !_X86_ISA_ISA_H_ */ diff --git a/sys/x86/isa/isa_dma.c b/sys/x86/isa/isa_dma.c new file mode 100644 index 0000000..cbc9959 --- /dev/null +++ b/sys/x86/isa/isa_dma.c @@ -0,0 +1,611 @@ +/*- + * Copyright (c) 1991 The Regents of the University of California. + * All rights reserved. + * + * This code is derived from software contributed to Berkeley by + * William Jolitz. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * from: @(#)isa.c 7.2 (Berkeley) 5/13/91 + */ + +#include <sys/cdefs.h> +__FBSDID("$FreeBSD$"); + +/* + * code to manage AT bus + * + * 92/08/18 Frank P. MacLachlan (fpm@crash.cts.com): + * Fixed uninitialized variable problem and added code to deal + * with DMA page boundaries in isa_dmarangecheck(). Fixed word + * mode DMA count compution and reorganized DMA setup code in + * isa_dmastart() + */ + +#include <sys/param.h> +#include <sys/systm.h> +#include <sys/bus.h> +#include <sys/kernel.h> +#include <sys/malloc.h> +#include <sys/lock.h> +#include <sys/proc.h> +#include <sys/mutex.h> +#include <sys/module.h> +#include <vm/vm.h> +#include <vm/vm_param.h> +#include <vm/pmap.h> +#include <isa/isareg.h> +#include <isa/isavar.h> +#include <isa/isa_dmareg.h> + +#define ISARAM_END RAM_END + +static int isa_dmarangecheck(caddr_t va, u_int length, int chan); + +static caddr_t dma_bouncebuf[8]; +static u_int dma_bouncebufsize[8]; +static u_int8_t dma_bounced = 0; +static u_int8_t dma_busy = 0; /* Used in isa_dmastart() */ +static u_int8_t dma_inuse = 0; /* User for acquire/release */ +static u_int8_t dma_auto_mode = 0; +static struct mtx isa_dma_lock; +MTX_SYSINIT(isa_dma_lock, &isa_dma_lock, "isa DMA lock", MTX_DEF); + +#define VALID_DMA_MASK (7) + +/* high byte of address is stored in this port for i-th dma channel */ +static int dmapageport[8] = { 0x87, 0x83, 0x81, 0x82, 0x8f, 0x8b, 0x89, 0x8a }; + +/* + * Setup a DMA channel's bounce buffer. + */ +int +isa_dma_init(int chan, u_int bouncebufsize, int flag) +{ + void *buf; + int contig; + +#ifdef DIAGNOSTIC + if (chan & ~VALID_DMA_MASK) + panic("isa_dma_init: channel out of range"); +#endif + + + /* Try malloc() first. It works better if it works. */ + buf = malloc(bouncebufsize, M_DEVBUF, flag); + if (buf != NULL) { + if (isa_dmarangecheck(buf, bouncebufsize, chan) != 0) { + free(buf, M_DEVBUF); + buf = NULL; + } + contig = 0; + } + + if (buf == NULL) { + buf = contigmalloc(bouncebufsize, M_DEVBUF, flag, 0ul, 0xfffffful, + 1ul, chan & 4 ? 0x20000ul : 0x10000ul); + contig = 1; + } + + if (buf == NULL) + return (ENOMEM); + + mtx_lock(&isa_dma_lock); + /* + * If a DMA channel is shared, both drivers have to call isa_dma_init + * since they don't know that the other driver will do it. + * Just return if we're already set up good. + * XXX: this only works if they agree on the bouncebuf size. This + * XXX: is typically the case since they are multiple instances of + * XXX: the same driver. + */ + if (dma_bouncebuf[chan] != NULL) { + if (contig) + contigfree(buf, bouncebufsize, M_DEVBUF); + else + free(buf, M_DEVBUF); + mtx_unlock(&isa_dma_lock); + return (0); + } + + dma_bouncebufsize[chan] = bouncebufsize; + dma_bouncebuf[chan] = buf; + + mtx_unlock(&isa_dma_lock); + + return (0); +} + +/* + * Register a DMA channel's usage. Usually called from a device driver + * in open() or during its initialization. + */ +int +isa_dma_acquire(chan) + int chan; +{ +#ifdef DIAGNOSTIC + if (chan & ~VALID_DMA_MASK) + panic("isa_dma_acquire: channel out of range"); +#endif + + mtx_lock(&isa_dma_lock); + if (dma_inuse & (1 << chan)) { + printf("isa_dma_acquire: channel %d already in use\n", chan); + mtx_unlock(&isa_dma_lock); + return (EBUSY); + } + dma_inuse |= (1 << chan); + dma_auto_mode &= ~(1 << chan); + mtx_unlock(&isa_dma_lock); + + return (0); +} + +/* + * Unregister a DMA channel's usage. Usually called from a device driver + * during close() or during its shutdown. + */ +void +isa_dma_release(chan) + int chan; +{ +#ifdef DIAGNOSTIC + if (chan & ~VALID_DMA_MASK) + panic("isa_dma_release: channel out of range"); + + mtx_lock(&isa_dma_lock); + if ((dma_inuse & (1 << chan)) == 0) + printf("isa_dma_release: channel %d not in use\n", chan); +#else + mtx_lock(&isa_dma_lock); +#endif + + if (dma_busy & (1 << chan)) { + dma_busy &= ~(1 << chan); + /* + * XXX We should also do "dma_bounced &= (1 << chan);" + * because we are acting on behalf of isa_dmadone() which + * was not called to end the last DMA operation. This does + * not matter now, but it may in the future. + */ + } + + dma_inuse &= ~(1 << chan); + dma_auto_mode &= ~(1 << chan); + + mtx_unlock(&isa_dma_lock); +} + +/* + * isa_dmacascade(): program 8237 DMA controller channel to accept + * external dma control by a board. + */ +void +isa_dmacascade(chan) + int chan; +{ +#ifdef DIAGNOSTIC + if (chan & ~VALID_DMA_MASK) + panic("isa_dmacascade: channel out of range"); +#endif + + mtx_lock(&isa_dma_lock); + /* set dma channel mode, and set dma channel mode */ + if ((chan & 4) == 0) { + outb(DMA1_MODE, DMA37MD_CASCADE | chan); + outb(DMA1_SMSK, chan); + } else { + outb(DMA2_MODE, DMA37MD_CASCADE | (chan & 3)); + outb(DMA2_SMSK, chan & 3); + } + mtx_unlock(&isa_dma_lock); +} + +/* + * isa_dmastart(): program 8237 DMA controller channel, avoid page alignment + * problems by using a bounce buffer. + */ +void +isa_dmastart(int flags, caddr_t addr, u_int nbytes, int chan) +{ + vm_paddr_t phys; + int waport; + caddr_t newaddr; + int dma_range_checked; + + /* translate to physical */ + phys = pmap_extract(kernel_pmap, (vm_offset_t)addr); + dma_range_checked = isa_dmarangecheck(addr, nbytes, chan); + +#ifdef DIAGNOSTIC + if (chan & ~VALID_DMA_MASK) + panic("isa_dmastart: channel out of range"); + + if ((chan < 4 && nbytes > (1<<16)) + || (chan >= 4 && (nbytes > (1<<17) || (uintptr_t)addr & 1))) + panic("isa_dmastart: impossible request"); + + mtx_lock(&isa_dma_lock); + if ((dma_inuse & (1 << chan)) == 0) + printf("isa_dmastart: channel %d not acquired\n", chan); +#else + mtx_lock(&isa_dma_lock); +#endif + +#if 0 + /* + * XXX This should be checked, but drivers like ad1848 only call + * isa_dmastart() once because they use Auto DMA mode. If we + * leave this in, drivers that do this will print this continuously. + */ + if (dma_busy & (1 << chan)) + printf("isa_dmastart: channel %d busy\n", chan); +#endif + + dma_busy |= (1 << chan); + + if (dma_range_checked) { + if (dma_bouncebuf[chan] == NULL + || dma_bouncebufsize[chan] < nbytes) + panic("isa_dmastart: bad bounce buffer"); + dma_bounced |= (1 << chan); + newaddr = dma_bouncebuf[chan]; + + /* copy bounce buffer on write */ + if (!(flags & ISADMA_READ)) + bcopy(addr, newaddr, nbytes); + addr = newaddr; + } + + if (flags & ISADMA_RAW) { + dma_auto_mode |= (1 << chan); + } else { + dma_auto_mode &= ~(1 << chan); + } + + if ((chan & 4) == 0) { + /* + * Program one of DMA channels 0..3. These are + * byte mode channels. + */ + /* set dma channel mode, and reset address ff */ + + /* If ISADMA_RAW flag is set, then use autoinitialise mode */ + if (flags & ISADMA_RAW) { + if (flags & ISADMA_READ) + outb(DMA1_MODE, DMA37MD_AUTO|DMA37MD_WRITE|chan); + else + outb(DMA1_MODE, DMA37MD_AUTO|DMA37MD_READ|chan); + } + else + if (flags & ISADMA_READ) + outb(DMA1_MODE, DMA37MD_SINGLE|DMA37MD_WRITE|chan); + else + outb(DMA1_MODE, DMA37MD_SINGLE|DMA37MD_READ|chan); + outb(DMA1_FFC, 0); + + /* send start address */ + waport = DMA1_CHN(chan); + outb(waport, phys); + outb(waport, phys>>8); + outb(dmapageport[chan], phys>>16); + + /* send count */ + outb(waport + 1, --nbytes); + outb(waport + 1, nbytes>>8); + + /* unmask channel */ + outb(DMA1_SMSK, chan); + } else { + /* + * Program one of DMA channels 4..7. These are + * word mode channels. + */ + /* set dma channel mode, and reset address ff */ + + /* If ISADMA_RAW flag is set, then use autoinitialise mode */ + if (flags & ISADMA_RAW) { + if (flags & ISADMA_READ) + outb(DMA2_MODE, DMA37MD_AUTO|DMA37MD_WRITE|(chan&3)); + else + outb(DMA2_MODE, DMA37MD_AUTO|DMA37MD_READ|(chan&3)); + } + else + if (flags & ISADMA_READ) + outb(DMA2_MODE, DMA37MD_SINGLE|DMA37MD_WRITE|(chan&3)); + else + outb(DMA2_MODE, DMA37MD_SINGLE|DMA37MD_READ|(chan&3)); + outb(DMA2_FFC, 0); + + /* send start address */ + waport = DMA2_CHN(chan - 4); + outb(waport, phys>>1); + outb(waport, phys>>9); + outb(dmapageport[chan], phys>>16); + + /* send count */ + nbytes >>= 1; + outb(waport + 2, --nbytes); + outb(waport + 2, nbytes>>8); + + /* unmask channel */ + outb(DMA2_SMSK, chan & 3); + } + mtx_unlock(&isa_dma_lock); +} + +void +isa_dmadone(int flags, caddr_t addr, int nbytes, int chan) +{ +#ifdef DIAGNOSTIC + if (chan & ~VALID_DMA_MASK) + panic("isa_dmadone: channel out of range"); + + if ((dma_inuse & (1 << chan)) == 0) + printf("isa_dmadone: channel %d not acquired\n", chan); +#endif + + mtx_lock(&isa_dma_lock); + if (((dma_busy & (1 << chan)) == 0) && + (dma_auto_mode & (1 << chan)) == 0 ) + printf("isa_dmadone: channel %d not busy\n", chan); + + if ((dma_auto_mode & (1 << chan)) == 0) + outb(chan & 4 ? DMA2_SMSK : DMA1_SMSK, (chan & 3) | 4); + + if (dma_bounced & (1 << chan)) { + /* copy bounce buffer on read */ + if (flags & ISADMA_READ) + bcopy(dma_bouncebuf[chan], addr, nbytes); + + dma_bounced &= ~(1 << chan); + } + dma_busy &= ~(1 << chan); + mtx_unlock(&isa_dma_lock); +} + +/* + * Check for problems with the address range of a DMA transfer + * (non-contiguous physical pages, outside of bus address space, + * crossing DMA page boundaries). + * Return true if special handling needed. + */ + +static int +isa_dmarangecheck(caddr_t va, u_int length, int chan) +{ + vm_paddr_t phys, priorpage = 0; + vm_offset_t endva; + u_int dma_pgmsk = (chan & 4) ? ~(128*1024-1) : ~(64*1024-1); + + endva = (vm_offset_t)round_page((vm_offset_t)va + length); + for (; va < (caddr_t) endva ; va += PAGE_SIZE) { + phys = trunc_page(pmap_extract(kernel_pmap, (vm_offset_t)va)); + if (phys == 0) + panic("isa_dmacheck: no physical page present"); + if (phys >= ISARAM_END) + return (1); + if (priorpage) { + if (priorpage + PAGE_SIZE != phys) + return (1); + /* check if crossing a DMA page boundary */ + if (((u_int)priorpage ^ (u_int)phys) & dma_pgmsk) + return (1); + } + priorpage = phys; + } + return (0); +} + +/* + * Query the progress of a transfer on a DMA channel. + * + * To avoid having to interrupt a transfer in progress, we sample + * each of the high and low databytes twice, and apply the following + * logic to determine the correct count. + * + * Reads are performed with interrupts disabled, thus it is to be + * expected that the time between reads is very small. At most + * one rollover in the low count byte can be expected within the + * four reads that are performed. + * + * There are three gaps in which a rollover can occur : + * + * - read low1 + * gap1 + * - read high1 + * gap2 + * - read low2 + * gap3 + * - read high2 + * + * If a rollover occurs in gap1 or gap2, the low2 value will be + * greater than the low1 value. In this case, low2 and high2 are a + * corresponding pair. + * + * In any other case, low1 and high1 can be considered to be correct. + * + * The function returns the number of bytes remaining in the transfer, + * or -1 if the channel requested is not active. + * + */ +static int +isa_dmastatus_locked(int chan) +{ + u_long cnt = 0; + int ffport, waport; + u_long low1, high1, low2, high2; + + mtx_assert(&isa_dma_lock, MA_OWNED); + + /* channel active? */ + if ((dma_inuse & (1 << chan)) == 0) { + printf("isa_dmastatus: channel %d not active\n", chan); + return(-1); + } + /* channel busy? */ + + if (((dma_busy & (1 << chan)) == 0) && + (dma_auto_mode & (1 << chan)) == 0 ) { + printf("chan %d not busy\n", chan); + return -2 ; + } + if (chan < 4) { /* low DMA controller */ + ffport = DMA1_FFC; + waport = DMA1_CHN(chan) + 1; + } else { /* high DMA controller */ + ffport = DMA2_FFC; + waport = DMA2_CHN(chan - 4) + 2; + } + + disable_intr(); /* no interrupts Mr Jones! */ + outb(ffport, 0); /* clear register LSB flipflop */ + low1 = inb(waport); + high1 = inb(waport); + outb(ffport, 0); /* clear again */ + low2 = inb(waport); + high2 = inb(waport); + enable_intr(); /* enable interrupts again */ + + /* + * Now decide if a wrap has tried to skew our results. + * Note that after TC, the count will read 0xffff, while we want + * to return zero, so we add and then mask to compensate. + */ + if (low1 >= low2) { + cnt = (low1 + (high1 << 8) + 1) & 0xffff; + } else { + cnt = (low2 + (high2 << 8) + 1) & 0xffff; + } + + if (chan >= 4) /* high channels move words */ + cnt *= 2; + return(cnt); +} + +int +isa_dmastatus(int chan) +{ + int status; + + mtx_lock(&isa_dma_lock); + status = isa_dmastatus_locked(chan); + mtx_unlock(&isa_dma_lock); + + return (status); +} + +/* + * Reached terminal count yet ? + */ +int +isa_dmatc(int chan) +{ + + if (chan < 4) + return(inb(DMA1_STATUS) & (1 << chan)); + else + return(inb(DMA2_STATUS) & (1 << (chan & 3))); +} + +/* + * Stop a DMA transfer currently in progress. + */ +int +isa_dmastop(int chan) +{ + int status; + + mtx_lock(&isa_dma_lock); + if ((dma_inuse & (1 << chan)) == 0) + printf("isa_dmastop: channel %d not acquired\n", chan); + + if (((dma_busy & (1 << chan)) == 0) && + ((dma_auto_mode & (1 << chan)) == 0)) { + printf("chan %d not busy\n", chan); + mtx_unlock(&isa_dma_lock); + return -2 ; + } + + if ((chan & 4) == 0) { + outb(DMA1_SMSK, (chan & 3) | 4 /* disable mask */); + } else { + outb(DMA2_SMSK, (chan & 3) | 4 /* disable mask */); + } + + status = isa_dmastatus_locked(chan); + + mtx_unlock(&isa_dma_lock); + + return (status); +} + +/* + * Attach to the ISA PnP descriptor for the AT DMA controller + */ +static struct isa_pnp_id atdma_ids[] = { + { 0x0002d041 /* PNP0200 */, "AT DMA controller" }, + { 0 } +}; + +static int +atdma_probe(device_t dev) +{ + int result; + + if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, atdma_ids)) <= 0) + device_quiet(dev); + return(result); +} + +static int +atdma_attach(device_t dev) +{ + return(0); +} + +static device_method_t atdma_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, atdma_probe), + DEVMETHOD(device_attach, atdma_attach), + DEVMETHOD(device_detach, bus_generic_detach), + DEVMETHOD(device_shutdown, bus_generic_shutdown), + DEVMETHOD(device_suspend, bus_generic_suspend), + DEVMETHOD(device_resume, bus_generic_resume), + { 0, 0 } +}; + +static driver_t atdma_driver = { + "atdma", + atdma_methods, + 1, /* no softc */ +}; + +static devclass_t atdma_devclass; + +DRIVER_MODULE(atdma, isa, atdma_driver, atdma_devclass, 0, 0); +DRIVER_MODULE(atdma, acpi, atdma_driver, atdma_devclass, 0, 0); diff --git a/sys/x86/isa/nmi.c b/sys/x86/isa/nmi.c new file mode 100644 index 0000000..db5550c --- /dev/null +++ b/sys/x86/isa/nmi.c @@ -0,0 +1,107 @@ +/*- + * Copyright (c) 1991 The Regents of the University of California. + * All rights reserved. + * + * This code is derived from software contributed to Berkeley by + * William Jolitz. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * from: @(#)isa.c 7.2 (Berkeley) 5/13/91 + */ + +#include <sys/cdefs.h> +__FBSDID("$FreeBSD$"); + +#include "opt_mca.h" + +#include <sys/types.h> +#include <sys/syslog.h> +#include <sys/systm.h> + +#include <machine/md_var.h> + +#ifdef DEV_MCA +#include <i386/bios/mca_machdep.h> +#endif + +#define NMI_PARITY (1 << 7) +#define NMI_IOCHAN (1 << 6) +#define ENMI_WATCHDOG (1 << 7) +#define ENMI_BUSTIMER (1 << 6) +#define ENMI_IOSTATUS (1 << 5) + +/* + * Handle a NMI, possibly a machine check. + * return true to panic system, false to ignore. + */ +int +isa_nmi(int cd) +{ + int retval = 0; + int isa_port = inb(0x61); + int eisa_port = inb(0x461); + + log(LOG_CRIT, "NMI ISA %x, EISA %x\n", isa_port, eisa_port); +#ifdef DEV_MCA + if (MCA_system && mca_bus_nmi()) + return(0); +#endif + + if (isa_port & NMI_PARITY) { + log(LOG_CRIT, "RAM parity error, likely hardware failure."); + retval = 1; + } + + if (isa_port & NMI_IOCHAN) { + log(LOG_CRIT, "I/O channel check, likely hardware failure."); + retval = 1; + } + + /* + * On a real EISA machine, this will never happen. However it can + * happen on ISA machines which implement XT style floating point + * error handling (very rare). Save them from a meaningless panic. + */ + if (eisa_port == 0xff) + return(retval); + + if (eisa_port & ENMI_WATCHDOG) { + log(LOG_CRIT, "EISA watchdog timer expired, likely hardware failure."); + retval = 1; + } + + if (eisa_port & ENMI_BUSTIMER) { + log(LOG_CRIT, "EISA bus timeout, likely hardware failure."); + retval = 1; + } + + if (eisa_port & ENMI_IOSTATUS) { + log(LOG_CRIT, "EISA I/O port status error."); + retval = 1; + } + + return(retval); +} diff --git a/sys/x86/isa/orm.c b/sys/x86/isa/orm.c new file mode 100644 index 0000000..f25312f --- /dev/null +++ b/sys/x86/isa/orm.c @@ -0,0 +1,185 @@ +/*- + * Copyright (c) 2000 Nikolai Saoukh + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <sys/cdefs.h> +__FBSDID("$FreeBSD$"); + +/* + * Driver to take care of holes in ISA I/O memory occupied + * by option rom(s) + */ + +#include <sys/param.h> +#include <sys/systm.h> +#include <sys/kernel.h> +#include <sys/socket.h> + +#include <sys/module.h> +#include <sys/bus.h> + +#include <machine/bus.h> +#include <machine/resource.h> +#include <sys/rman.h> + +#include <isa/isavar.h> +#include <isa/pnpvar.h> + +#define IOMEM_START 0x0a0000 +#define IOMEM_STEP 0x000800 +#define IOMEM_END 0x100000 + +#define ORM_ID 0x00004d3e + +static struct isa_pnp_id orm_ids[] = { + { ORM_ID, NULL }, /* ORM0000 */ + { 0, NULL }, +}; + +#define MAX_ROMS 16 + +struct orm_softc { + int rnum; + int rid[MAX_ROMS]; + struct resource *res[MAX_ROMS]; +}; + +static int +orm_probe(device_t dev) +{ + return (ISA_PNP_PROBE(device_get_parent(dev), dev, orm_ids)); +} + +static int +orm_attach(device_t dev) +{ + return (0); +} + +static void +orm_identify(driver_t* driver, device_t parent) +{ + bus_space_handle_t bh; + bus_space_tag_t bt; + device_t child; + u_int32_t chunk = IOMEM_START; + struct resource *res; + int rid; + u_int32_t rom_size; + struct orm_softc *sc; + u_int8_t buf[3]; + + child = BUS_ADD_CHILD(parent, ISA_ORDER_SENSITIVE, "orm", -1); + device_set_driver(child, driver); + isa_set_logicalid(child, ORM_ID); + isa_set_vendorid(child, ORM_ID); + sc = device_get_softc(child); + sc->rnum = 0; + while (chunk < IOMEM_END) { + bus_set_resource(child, SYS_RES_MEMORY, sc->rnum, chunk, + IOMEM_STEP); + rid = sc->rnum; + res = bus_alloc_resource_any(child, SYS_RES_MEMORY, &rid, + RF_ACTIVE); + if (res == NULL) { + bus_delete_resource(child, SYS_RES_MEMORY, sc->rnum); + chunk += IOMEM_STEP; + continue; + } + bt = rman_get_bustag(res); + bh = rman_get_bushandle(res); + bus_space_read_region_1(bt, bh, 0, buf, sizeof(buf)); + + /* + * We need to release and delete the resource since we're + * changing its size, or the rom isn't there. There + * is a checksum field in the ROM to prevent false + * positives. However, some common hardware (IBM thinkpads) + * neglects to put a valid checksum in the ROM, so we do + * not double check the checksum here. On the ISA bus + * areas that have no hardware read back as 0xff, so the + * tests to see if we have 0x55 followed by 0xaa are + * generally sufficient. + */ + bus_release_resource(child, SYS_RES_MEMORY, rid, res); + bus_delete_resource(child, SYS_RES_MEMORY, sc->rnum); + if (buf[0] != 0x55 || buf[1] != 0xAA || (buf[2] & 0x03) != 0) { + chunk += IOMEM_STEP; + continue; + } + rom_size = buf[2] << 9; + bus_set_resource(child, SYS_RES_MEMORY, sc->rnum, chunk, + rom_size); + rid = sc->rnum; + res = bus_alloc_resource_any(child, SYS_RES_MEMORY, &rid, 0); + if (res == NULL) { + bus_delete_resource(child, SYS_RES_MEMORY, sc->rnum); + chunk += IOMEM_STEP; + continue; + } + sc->rid[sc->rnum] = rid; + sc->res[sc->rnum] = res; + sc->rnum++; + chunk += rom_size; + } + + if (sc->rnum == 0) + device_delete_child(parent, child); + else if (sc->rnum == 1) + device_set_desc(child, "ISA Option ROM"); + else + device_set_desc(child, "ISA Option ROMs"); +} + +static int +orm_detach(device_t dev) +{ + int i; + struct orm_softc *sc = device_get_softc(dev); + + for (i = 0; i < sc->rnum; i++) + bus_release_resource(dev, SYS_RES_MEMORY, sc->rid[i], + sc->res[i]); + return (0); +} + +static device_method_t orm_methods[] = { + /* Device interface */ + DEVMETHOD(device_identify, orm_identify), + DEVMETHOD(device_probe, orm_probe), + DEVMETHOD(device_attach, orm_attach), + DEVMETHOD(device_detach, orm_detach), + { 0, 0 } +}; + +static driver_t orm_driver = { + "orm", + orm_methods, + sizeof (struct orm_softc) +}; + +static devclass_t orm_devclass; + +DRIVER_MODULE(orm, isa, orm_driver, orm_devclass, 0, 0); |
