1 files changed, 25 insertions, 7 deletions
diff --git a/sys/powerpc/mpc85xx/mpc85xx.c b/sys/powerpc/mpc85xx/mpc85xx.c
index 62a47a6..b75e301 100644
--- a/sys/powerpc/mpc85xx/mpc85xx.c
+++ b/sys/powerpc/mpc85xx/mpc85xx.c
@@ -38,33 +38,51 @@ __FBSDID("$FreeBSD$");
 
 #include <machine/cpu.h>
 #include <machine/cpufunc.h>
-#include <machine/pio.h>
 #include <machine/spr.h>
 
 #include <powerpc/mpc85xx/ocpbus.h>
+#include <powerpc/mpc85xx/mpc85xx.h>
 
 /*
  * MPC85xx system specific routines
  */
 
+uint32_t
+ccsr_read4(uintptr_t addr)
+{
+	volatile uint32_t *ptr = (void *)addr;
+
+	return (*ptr);
+}
+
+void
+ccsr_write4(uintptr_t addr, uint32_t val)
+{
+	volatile uint32_t *ptr = (void *)addr;
+
+	*ptr = val;
+	__asm __volatile("eieio; sync");
+}
+
 void
-cpu_reset()
+cpu_reset(void)
 {
-	uint32_t svr = mfspr(SPR_SVR);
+	uint32_t ver = SVR_VER(mfspr(SPR_SVR));
 
-	if (svr == SVR_MPC8572E || svr == SVR_MPC8572)
+	if (ver == SVR_MPC8572E || ver == SVR_MPC8572)
 		/* Systems with dedicated reset register */
-		out32(OCP85XX_RSTCR, 2);
+		ccsr_write4(OCP85XX_RSTCR, 2);
 	else {
 		/* Clear DBCR0, disables debug interrupts and events. */
 		mtspr(SPR_DBCR0, 0);
-		__asm volatile("isync");
+		__asm __volatile("isync");
 
 		/* Enable Debug Interrupts in MSR. */
 		mtmsr(mfmsr() | PSL_DE);
 
 		/* Enable debug interrupts and issue reset. */
-		mtspr(SPR_DBCR0, mfspr(SPR_DBCR0) | DBCR0_IDM | DBCR0_RST_SYSTEM);
+		mtspr(SPR_DBCR0, mfspr(SPR_DBCR0) | DBCR0_IDM |
+		    DBCR0_RST_SYSTEM);
 	}
 
 	printf("Reset failed...\n");