diff options
Diffstat (limited to 'sys/pci')
| -rw-r--r-- | sys/pci/pci.c | 1420 | ||||
| -rw-r--r-- | sys/pci/pci_if.m | 46 | ||||
| -rw-r--r-- | sys/pci/pcib_if.m | 81 | ||||
| -rw-r--r-- | sys/pci/pcireg.h | 261 | ||||
| -rw-r--r-- | sys/pci/pcisupport.c | 1992 | ||||
| -rw-r--r-- | sys/pci/pcivar.h | 332 |
6 files changed, 0 insertions, 4132 deletions
diff --git a/sys/pci/pci.c b/sys/pci/pci.c deleted file mode 100644 index c87e8e4..0000000 --- a/sys/pci/pci.c +++ /dev/null @@ -1,1420 +0,0 @@ -/* - * Copyright (c) 1997, Stefan Esser <se@freebsd.org> - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice unmodified, this list of conditions, and the following - * disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * $FreeBSD$ - * - */ - -#include "opt_bus.h" - -#include "opt_simos.h" -#include "opt_compat_oldpci.h" - -#include <sys/param.h> -#include <sys/systm.h> -#include <sys/malloc.h> -#include <sys/module.h> -#include <sys/fcntl.h> -#include <sys/conf.h> -#include <sys/kernel.h> -#include <sys/queue.h> -#include <sys/types.h> - -#include <vm/vm.h> -#include <vm/pmap.h> -#include <vm/vm_extern.h> - -#include <sys/bus.h> -#include <machine/bus.h> -#include <sys/rman.h> -#include <machine/resource.h> -#include <machine/md_var.h> /* For the Alpha */ - -#include <sys/pciio.h> -#include <pci/pcireg.h> -#include <pci/pcivar.h> - -#include "pcib_if.h" - -#ifdef __alpha__ -#include <machine/rpb.h> -#endif - -#ifdef APIC_IO -#include <machine/smp.h> -#endif /* APIC_IO */ - -static devclass_t pci_devclass; - -struct pci_quirk { - u_int32_t devid; /* Vendor/device of the card */ - int type; -#define PCI_QUIRK_MAP_REG 1 /* PCI map register in wierd place */ - int arg1; - int arg2; -}; - -struct pci_quirk pci_quirks[] = { - /* - * The Intel 82371AB has a map register at offset 0x90. - */ - { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 }, - - { 0 } -}; - -/* map register information */ -#define PCI_MAPMEM 0x01 /* memory map */ -#define PCI_MAPMEMP 0x02 /* prefetchable memory map */ -#define PCI_MAPPORT 0x04 /* port map */ - -static STAILQ_HEAD(devlist, pci_devinfo) pci_devq; -u_int32_t pci_numdevs = 0; -static u_int32_t pci_generation = 0; - -/* return base address of memory or port map */ - -static u_int32_t -pci_mapbase(unsigned mapreg) -{ - int mask = 0x03; - if ((mapreg & 0x01) == 0) - mask = 0x0f; - return (mapreg & ~mask); -} - -/* return map type of memory or port map */ - -static int -pci_maptype(unsigned mapreg) -{ - static u_int8_t maptype[0x10] = { - PCI_MAPMEM, PCI_MAPPORT, - PCI_MAPMEM, 0, - PCI_MAPMEM, PCI_MAPPORT, - 0, 0, - PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, - PCI_MAPMEM|PCI_MAPMEMP, 0, - PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, - 0, 0, - }; - - return maptype[mapreg & 0x0f]; -} - -/* return log2 of map size decoded for memory or port map */ - -static int -pci_mapsize(unsigned testval) -{ - int ln2size; - - testval = pci_mapbase(testval); - ln2size = 0; - if (testval != 0) { - while ((testval & 1) == 0) - { - ln2size++; - testval >>= 1; - } - } - return (ln2size); -} - -/* return log2 of address range supported by map register */ - -static int -pci_maprange(unsigned mapreg) -{ - int ln2range = 0; - switch (mapreg & 0x07) { - case 0x00: - case 0x01: - case 0x05: - ln2range = 32; - break; - case 0x02: - ln2range = 20; - break; - case 0x04: - ln2range = 64; - break; - } - return (ln2range); -} - -/* adjust some values from PCI 1.0 devices to match 2.0 standards ... */ - -static void -pci_fixancient(pcicfgregs *cfg) -{ - if (cfg->hdrtype != 0) - return; - - /* PCI to PCI bridges use header type 1 */ - if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI) - cfg->hdrtype = 1; -} - -/* read config data specific to header type 1 device (PCI to PCI bridge) */ - -static void * -pci_readppb(device_t pcib, int b, int s, int f) -{ - pcih1cfgregs *p; - - p = malloc(sizeof (pcih1cfgregs), M_DEVBUF, M_WAITOK | M_ZERO); - if (p == NULL) - return (NULL); - - p->secstat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECSTAT_1, 2); - p->bridgectl = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_BRIDGECTL_1, 2); - - p->seclat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECLAT_1, 1); - - p->iobase = PCI_PPBIOBASE (PCIB_READ_CONFIG(pcib, b, s, f, - PCIR_IOBASEH_1, 2), - PCIB_READ_CONFIG(pcib, b, s, f, - PCIR_IOBASEL_1, 1)); - p->iolimit = PCI_PPBIOLIMIT (PCIB_READ_CONFIG(pcib, b, s, f, - PCIR_IOLIMITH_1, 2), - PCIB_READ_CONFIG(pcib, b, s, f, - PCIR_IOLIMITL_1, 1)); - - p->membase = PCI_PPBMEMBASE (0, - PCIB_READ_CONFIG(pcib, b, s, f, - PCIR_MEMBASE_1, 2)); - p->memlimit = PCI_PPBMEMLIMIT (0, - PCIB_READ_CONFIG(pcib, b, s, f, - PCIR_MEMLIMIT_1, 2)); - - p->pmembase = PCI_PPBMEMBASE ( - (pci_addr_t)PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMBASEH_1, 4), - PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMBASEL_1, 2)); - - p->pmemlimit = PCI_PPBMEMLIMIT ( - (pci_addr_t)PCIB_READ_CONFIG(pcib, b, s, f, - PCIR_PMLIMITH_1, 4), - PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMLIMITL_1, 2)); - - return (p); -} - -/* read config data specific to header type 2 device (PCI to CardBus bridge) */ - -static void * -pci_readpcb(device_t pcib, int b, int s, int f) -{ - pcih2cfgregs *p; - - p = malloc(sizeof (pcih2cfgregs), M_DEVBUF, M_WAITOK | M_ZERO); - if (p == NULL) - return (NULL); - - p->secstat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECSTAT_2, 2); - p->bridgectl = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_BRIDGECTL_2, 2); - - p->seclat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECLAT_2, 1); - - p->membase0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMBASE0_2, 4); - p->memlimit0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMLIMIT0_2, 4); - p->membase1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMBASE1_2, 4); - p->memlimit1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMLIMIT1_2, 4); - - p->iobase0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOBASE0_2, 4); - p->iolimit0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOLIMIT0_2, 4); - p->iobase1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOBASE1_2, 4); - p->iolimit1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOLIMIT1_2, 4); - - p->pccardif = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PCCARDIF_2, 4); - return p; -} - -/* extract header type specific config data */ - -static void -pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg) -{ -#define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) - switch (cfg->hdrtype) { - case 0: - cfg->subvendor = REG(PCIR_SUBVEND_0, 2); - cfg->subdevice = REG(PCIR_SUBDEV_0, 2); - cfg->nummaps = PCI_MAXMAPS_0; - break; - case 1: - cfg->subvendor = REG(PCIR_SUBVEND_1, 2); - cfg->subdevice = REG(PCIR_SUBDEV_1, 2); - cfg->secondarybus = REG(PCIR_SECBUS_1, 1); - cfg->subordinatebus = REG(PCIR_SUBBUS_1, 1); - cfg->nummaps = PCI_MAXMAPS_1; - cfg->hdrspec = pci_readppb(pcib, b, s, f); - break; - case 2: - cfg->subvendor = REG(PCIR_SUBVEND_2, 2); - cfg->subdevice = REG(PCIR_SUBDEV_2, 2); - cfg->secondarybus = REG(PCIR_SECBUS_2, 1); - cfg->subordinatebus = REG(PCIR_SUBBUS_2, 1); - cfg->nummaps = PCI_MAXMAPS_2; - cfg->hdrspec = pci_readpcb(pcib, b, s, f); - break; - } -#undef REG -} - -/* read configuration header into pcicfgrect structure */ - -static struct pci_devinfo * -pci_read_device(device_t pcib, int b, int s, int f) -{ -#define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) - pcicfgregs *cfg = NULL; - struct pci_devinfo *devlist_entry; - struct devlist *devlist_head; - - devlist_head = &pci_devq; - - devlist_entry = NULL; - - if (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_DEVVENDOR, 4) != -1) { - devlist_entry = malloc(sizeof(struct pci_devinfo), - M_DEVBUF, M_WAITOK | M_ZERO); - if (devlist_entry == NULL) - return (NULL); - - cfg = &devlist_entry->cfg; - - cfg->bus = b; - cfg->slot = s; - cfg->func = f; - cfg->vendor = REG(PCIR_VENDOR, 2); - cfg->device = REG(PCIR_DEVICE, 2); - cfg->cmdreg = REG(PCIR_COMMAND, 2); - cfg->statreg = REG(PCIR_STATUS, 2); - cfg->baseclass = REG(PCIR_CLASS, 1); - cfg->subclass = REG(PCIR_SUBCLASS, 1); - cfg->progif = REG(PCIR_PROGIF, 1); - cfg->revid = REG(PCIR_REVID, 1); - cfg->hdrtype = REG(PCIR_HEADERTYPE, 1); - cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1); - cfg->lattimer = REG(PCIR_LATTIMER, 1); - cfg->intpin = REG(PCIR_INTPIN, 1); - cfg->intline = REG(PCIR_INTLINE, 1); -#ifdef __alpha__ - alpha_platform_assign_pciintr(cfg); -#endif - -#ifdef APIC_IO - if (cfg->intpin != 0) { - int airq; - - airq = pci_apic_irq(cfg->bus, cfg->slot, cfg->intpin); - if (airq >= 0) { - /* PCI specific entry found in MP table */ - if (airq != cfg->intline) { - undirect_pci_irq(cfg->intline); - cfg->intline = airq; - } - } else { - /* - * PCI interrupts might be redirected to the - * ISA bus according to some MP tables. Use the - * same methods as used by the ISA devices - * devices to find the proper IOAPIC int pin. - */ - airq = isa_apic_irq(cfg->intline); - if ((airq >= 0) && (airq != cfg->intline)) { - /* XXX: undirect_pci_irq() ? */ - undirect_isa_irq(cfg->intline); - cfg->intline = airq; - } - } - } -#endif /* APIC_IO */ - - cfg->mingnt = REG(PCIR_MINGNT, 1); - cfg->maxlat = REG(PCIR_MAXLAT, 1); - - cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0; - cfg->hdrtype &= ~PCIM_MFDEV; - - pci_fixancient(cfg); - pci_hdrtypedata(pcib, b, s, f, cfg); - - STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links); - - devlist_entry->conf.pc_sel.pc_bus = cfg->bus; - devlist_entry->conf.pc_sel.pc_dev = cfg->slot; - devlist_entry->conf.pc_sel.pc_func = cfg->func; - devlist_entry->conf.pc_hdr = cfg->hdrtype; - - devlist_entry->conf.pc_subvendor = cfg->subvendor; - devlist_entry->conf.pc_subdevice = cfg->subdevice; - devlist_entry->conf.pc_vendor = cfg->vendor; - devlist_entry->conf.pc_device = cfg->device; - - devlist_entry->conf.pc_class = cfg->baseclass; - devlist_entry->conf.pc_subclass = cfg->subclass; - devlist_entry->conf.pc_progif = cfg->progif; - devlist_entry->conf.pc_revid = cfg->revid; - - pci_numdevs++; - pci_generation++; - } - return (devlist_entry); -#undef REG -} - -#if 0 -/* free pcicfgregs structure and all depending data structures */ - -static int -pci_freecfg(struct pci_devinfo *dinfo) -{ - struct devlist *devlist_head; - - devlist_head = &pci_devq; - - if (dinfo->cfg.hdrspec != NULL) - free(dinfo->cfg.hdrspec, M_DEVBUF); - if (dinfo->cfg.map != NULL) - free(dinfo->cfg.map, M_DEVBUF); - /* XXX this hasn't been tested */ - STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links); - free(dinfo, M_DEVBUF); - - /* increment the generation count */ - pci_generation++; - - /* we're losing one device */ - pci_numdevs--; - return (0); -} -#endif - - -/* - * This is the user interface to PCI configuration space. - */ - -static int -pci_open(dev_t dev, int oflags, int devtype, struct proc *p) -{ - if ((oflags & FWRITE) && securelevel > 0) { - return EPERM; - } - return 0; -} - -static int -pci_close(dev_t dev, int flag, int devtype, struct proc *p) -{ - return 0; -} - -/* - * Match a single pci_conf structure against an array of pci_match_conf - * structures. The first argument, 'matches', is an array of num_matches - * pci_match_conf structures. match_buf is a pointer to the pci_conf - * structure that will be compared to every entry in the matches array. - * This function returns 1 on failure, 0 on success. - */ -static int -pci_conf_match(struct pci_match_conf *matches, int num_matches, - struct pci_conf *match_buf) -{ - int i; - - if ((matches == NULL) || (match_buf == NULL) || (num_matches <= 0)) - return(1); - - for (i = 0; i < num_matches; i++) { - /* - * I'm not sure why someone would do this...but... - */ - if (matches[i].flags == PCI_GETCONF_NO_MATCH) - continue; - - /* - * Look at each of the match flags. If it's set, do the - * comparison. If the comparison fails, we don't have a - * match, go on to the next item if there is one. - */ - if (((matches[i].flags & PCI_GETCONF_MATCH_BUS) != 0) - && (match_buf->pc_sel.pc_bus != matches[i].pc_sel.pc_bus)) - continue; - - if (((matches[i].flags & PCI_GETCONF_MATCH_DEV) != 0) - && (match_buf->pc_sel.pc_dev != matches[i].pc_sel.pc_dev)) - continue; - - if (((matches[i].flags & PCI_GETCONF_MATCH_FUNC) != 0) - && (match_buf->pc_sel.pc_func != matches[i].pc_sel.pc_func)) - continue; - - if (((matches[i].flags & PCI_GETCONF_MATCH_VENDOR) != 0) - && (match_buf->pc_vendor != matches[i].pc_vendor)) - continue; - - if (((matches[i].flags & PCI_GETCONF_MATCH_DEVICE) != 0) - && (match_buf->pc_device != matches[i].pc_device)) - continue; - - if (((matches[i].flags & PCI_GETCONF_MATCH_CLASS) != 0) - && (match_buf->pc_class != matches[i].pc_class)) - continue; - - if (((matches[i].flags & PCI_GETCONF_MATCH_UNIT) != 0) - && (match_buf->pd_unit != matches[i].pd_unit)) - continue; - - if (((matches[i].flags & PCI_GETCONF_MATCH_NAME) != 0) - && (strncmp(matches[i].pd_name, match_buf->pd_name, - sizeof(match_buf->pd_name)) != 0)) - continue; - - return(0); - } - - return(1); -} - -/* - * Locate the parent of a PCI device by scanning the PCI devlist - * and return the entry for the parent. - * For devices on PCI Bus 0 (the host bus), this is the PCI Host. - * For devices on secondary PCI busses, this is that bus' PCI-PCI Bridge. - */ - -pcicfgregs * -pci_devlist_get_parent(pcicfgregs *cfg) -{ - struct devlist *devlist_head; - struct pci_devinfo *dinfo; - pcicfgregs *bridge_cfg; - int i; - - dinfo = STAILQ_FIRST(devlist_head = &pci_devq); - - /* If the device is on PCI bus 0, look for the host */ - if (cfg->bus == 0) { - for (i = 0; (dinfo != NULL) && (i < pci_numdevs); - dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { - bridge_cfg = &dinfo->cfg; - if (bridge_cfg->baseclass == PCIC_BRIDGE - && bridge_cfg->subclass == PCIS_BRIDGE_HOST - && bridge_cfg->bus == cfg->bus) { - return bridge_cfg; - } - } - } - - /* If the device is not on PCI bus 0, look for the PCI-PCI bridge */ - if (cfg->bus > 0) { - for (i = 0; (dinfo != NULL) && (i < pci_numdevs); - dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { - bridge_cfg = &dinfo->cfg; - if (bridge_cfg->baseclass == PCIC_BRIDGE - && bridge_cfg->subclass == PCIS_BRIDGE_PCI - && bridge_cfg->secondarybus == cfg->bus) { - return bridge_cfg; - } - } - } - - return NULL; -} - -static int -pci_ioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct proc *p) -{ - device_t pci, pcib; - struct pci_io *io; - const char *name; - int error; - - if (!(flag & FWRITE)) - return EPERM; - - - switch(cmd) { - case PCIOCGETCONF: - { - struct pci_devinfo *dinfo; - struct pci_conf_io *cio; - struct devlist *devlist_head; - struct pci_match_conf *pattern_buf; - int num_patterns; - size_t iolen; - int ionum, i; - - cio = (struct pci_conf_io *)data; - - num_patterns = 0; - dinfo = NULL; - - /* - * Hopefully the user won't pass in a null pointer, but it - * can't hurt to check. - */ - if (cio == NULL) { - error = EINVAL; - break; - } - - /* - * If the user specified an offset into the device list, - * but the list has changed since they last called this - * ioctl, tell them that the list has changed. They will - * have to get the list from the beginning. - */ - if ((cio->offset != 0) - && (cio->generation != pci_generation)){ - cio->num_matches = 0; - cio->status = PCI_GETCONF_LIST_CHANGED; - error = 0; - break; - } - - /* - * Check to see whether the user has asked for an offset - * past the end of our list. - */ - if (cio->offset >= pci_numdevs) { - cio->num_matches = 0; - cio->status = PCI_GETCONF_LAST_DEVICE; - error = 0; - break; - } - - /* get the head of the device queue */ - devlist_head = &pci_devq; - - /* - * Determine how much room we have for pci_conf structures. - * Round the user's buffer size down to the nearest - * multiple of sizeof(struct pci_conf) in case the user - * didn't specify a multiple of that size. - */ - iolen = min(cio->match_buf_len - - (cio->match_buf_len % sizeof(struct pci_conf)), - pci_numdevs * sizeof(struct pci_conf)); - - /* - * Since we know that iolen is a multiple of the size of - * the pciconf union, it's okay to do this. - */ - ionum = iolen / sizeof(struct pci_conf); - - /* - * If this test is true, the user wants the pci_conf - * structures returned to match the supplied entries. - */ - if ((cio->num_patterns > 0) - && (cio->pat_buf_len > 0)) { - /* - * pat_buf_len needs to be: - * num_patterns * sizeof(struct pci_match_conf) - * While it is certainly possible the user just - * allocated a large buffer, but set the number of - * matches correctly, it is far more likely that - * their kernel doesn't match the userland utility - * they're using. It's also possible that the user - * forgot to initialize some variables. Yes, this - * may be overly picky, but I hazard to guess that - * it's far more likely to just catch folks that - * updated their kernel but not their userland. - */ - if ((cio->num_patterns * - sizeof(struct pci_match_conf)) != cio->pat_buf_len){ - /* The user made a mistake, return an error*/ - cio->status = PCI_GETCONF_ERROR; - printf("pci_ioctl: pat_buf_len %d != " - "num_patterns (%d) * sizeof(struct " - "pci_match_conf) (%d)\npci_ioctl: " - "pat_buf_len should be = %d\n", - cio->pat_buf_len, cio->num_patterns, - (int)sizeof(struct pci_match_conf), - (int)sizeof(struct pci_match_conf) * - cio->num_patterns); - printf("pci_ioctl: do your headers match your " - "kernel?\n"); - cio->num_matches = 0; - error = EINVAL; - break; - } - - /* - * Check the user's buffer to make sure it's readable. - */ - if (!useracc((caddr_t)cio->patterns, - cio->pat_buf_len, VM_PROT_READ)) { - printf("pci_ioctl: pattern buffer %p, " - "length %u isn't user accessible for" - " READ\n", cio->patterns, - cio->pat_buf_len); - error = EACCES; - break; - } - /* - * Allocate a buffer to hold the patterns. - */ - pattern_buf = malloc(cio->pat_buf_len, M_TEMP, - M_WAITOK); - error = copyin(cio->patterns, pattern_buf, - cio->pat_buf_len); - if (error != 0) - break; - num_patterns = cio->num_patterns; - - } else if ((cio->num_patterns > 0) - || (cio->pat_buf_len > 0)) { - /* - * The user made a mistake, spit out an error. - */ - cio->status = PCI_GETCONF_ERROR; - cio->num_matches = 0; - printf("pci_ioctl: invalid GETCONF arguments\n"); - error = EINVAL; - break; - } else - pattern_buf = NULL; - - /* - * Make sure we can write to the match buffer. - */ - if (!useracc((caddr_t)cio->matches, - cio->match_buf_len, VM_PROT_WRITE)) { - printf("pci_ioctl: match buffer %p, length %u " - "isn't user accessible for WRITE\n", - cio->matches, cio->match_buf_len); - error = EACCES; - break; - } - - /* - * Go through the list of devices and copy out the devices - * that match the user's criteria. - */ - for (cio->num_matches = 0, error = 0, i = 0, - dinfo = STAILQ_FIRST(devlist_head); - (dinfo != NULL) && (cio->num_matches < ionum) - && (error == 0) && (i < pci_numdevs); - dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { - - if (i < cio->offset) - continue; - - /* Populate pd_name and pd_unit */ - name = NULL; - if (dinfo->cfg.dev && dinfo->conf.pd_name[0] == '\0') - name = device_get_name(dinfo->cfg.dev); - if (name) { - strncpy(dinfo->conf.pd_name, name, - sizeof(dinfo->conf.pd_name)); - dinfo->conf.pd_name[PCI_MAXNAMELEN] = 0; - dinfo->conf.pd_unit = - device_get_unit(dinfo->cfg.dev); - } - - if ((pattern_buf == NULL) || - (pci_conf_match(pattern_buf, num_patterns, - &dinfo->conf) == 0)) { - - /* - * If we've filled up the user's buffer, - * break out at this point. Since we've - * got a match here, we'll pick right back - * up at the matching entry. We can also - * tell the user that there are more matches - * left. - */ - if (cio->num_matches >= ionum) - break; - - error = copyout(&dinfo->conf, - &cio->matches[cio->num_matches], - sizeof(struct pci_conf)); - cio->num_matches++; - } - } - - /* - * Set the pointer into the list, so if the user is getting - * n records at a time, where n < pci_numdevs, - */ - cio->offset = i; - - /* - * Set the generation, the user will need this if they make - * another ioctl call with offset != 0. - */ - cio->generation = pci_generation; - - /* - * If this is the last device, inform the user so he won't - * bother asking for more devices. If dinfo isn't NULL, we - * know that there are more matches in the list because of - * the way the traversal is done. - */ - if (dinfo == NULL) - cio->status = PCI_GETCONF_LAST_DEVICE; - else - cio->status = PCI_GETCONF_MORE_DEVS; - - if (pattern_buf != NULL) - free(pattern_buf, M_TEMP); - - break; - } - case PCIOCREAD: - io = (struct pci_io *)data; - switch(io->pi_width) { - case 4: - case 2: - case 1: - /* - * Assume that the user-level bus number is - * actually the pciN instance number. We map - * from that to the real pcib+bus combination. - */ - pci = devclass_get_device(pci_devclass, - io->pi_sel.pc_bus); - if (pci) { - int b = pcib_get_bus(pci); - pcib = device_get_parent(pci); - io->pi_data = - PCIB_READ_CONFIG(pcib, - b, - io->pi_sel.pc_dev, - io->pi_sel.pc_func, - io->pi_reg, - io->pi_width); - error = 0; - } else { - error = ENODEV; - } - break; - default: - error = ENODEV; - break; - } - break; - - case PCIOCWRITE: - io = (struct pci_io *)data; - switch(io->pi_width) { - case 4: - case 2: - case 1: - /* - * Assume that the user-level bus number is - * actually the pciN instance number. We map - * from that to the real pcib+bus combination. - */ - pci = devclass_get_device(pci_devclass, - io->pi_sel.pc_bus); - if (pci) { - int b = pcib_get_bus(pci); - pcib = device_get_parent(pci); - PCIB_WRITE_CONFIG(pcib, - b, - io->pi_sel.pc_dev, - io->pi_sel.pc_func, - io->pi_reg, - io->pi_data, - io->pi_width); - error = 0; - } else { - error = ENODEV; - } - break; - default: - error = ENODEV; - break; - } - break; - - default: - error = ENOTTY; - break; - } - - return (error); -} - -#define PCI_CDEV 78 - -static struct cdevsw pcicdev = { - /* open */ pci_open, - /* close */ pci_close, - /* read */ noread, - /* write */ nowrite, - /* ioctl */ pci_ioctl, - /* poll */ nopoll, - /* mmap */ nommap, - /* strategy */ nostrategy, - /* name */ "pci", - /* maj */ PCI_CDEV, - /* dump */ nodump, - /* psize */ nopsize, - /* flags */ 0, - /* bmaj */ -1 -}; - -#include "pci_if.h" - -/* - * New style pci driver. Parent device is either a pci-host-bridge or a - * pci-pci-bridge. Both kinds are represented by instances of pcib. - */ - -static void -pci_print_verbose(struct pci_devinfo *dinfo) -{ - if (bootverbose) { - pcicfgregs *cfg = &dinfo->cfg; - - printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n", - cfg->vendor, cfg->device, cfg->revid); - printf("\tbus=%d, slot=%d, func=%d\n", - cfg->bus, cfg->slot, cfg->func); - printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n", - cfg->baseclass, cfg->subclass, cfg->progif, - cfg->hdrtype, cfg->mfdev); - printf("\tsubordinatebus=%x \tsecondarybus=%x\n", - cfg->subordinatebus, cfg->secondarybus); -#ifdef PCI_DEBUG - printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n", - cfg->cmdreg, cfg->statreg, cfg->cachelnsz); - printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n", - cfg->lattimer, cfg->lattimer * 30, - cfg->mingnt, cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250); -#endif /* PCI_DEBUG */ - if (cfg->intpin > 0) - printf("\tintpin=%c, irq=%d\n", cfg->intpin +'a' -1, cfg->intline); - } -} - -static int -pci_porten(device_t pcib, int b, int s, int f) -{ - return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) - & PCIM_CMD_PORTEN) != 0; -} - -static int -pci_memen(device_t pcib, int b, int s, int f) -{ - return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) - & PCIM_CMD_MEMEN) != 0; -} - -/* - * Add a resource based on a pci map register. Return 1 if the map - * register is a 32bit map register or 2 if it is a 64bit register. - */ -static int -pci_add_map(device_t pcib, int b, int s, int f, int reg, - struct resource_list *rl) -{ - u_int32_t map; - u_int64_t base; - u_int8_t ln2size; - u_int8_t ln2range; - u_int32_t testval; -#ifdef PCI_ENABLE_IO_MODES - u_int16_t cmd; -#endif - int type; - - map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); - - if (map == 0 || map == 0xffffffff) - return 1; /* skip invalid entry */ - - PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4); - testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); - PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4); - - base = pci_mapbase(map); - if (pci_maptype(map) & PCI_MAPMEM) - type = SYS_RES_MEMORY; - else - type = SYS_RES_IOPORT; - ln2size = pci_mapsize(testval); - ln2range = pci_maprange(testval); - if (ln2range == 64) { - /* Read the other half of a 64bit map register */ - base |= (u_int64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg + 4, 4) << 32; - } - - if (bootverbose) { - printf("\tmap[%02x]: type %x, range %2d, base %08x, size %2d", - reg, pci_maptype(map), ln2range, - (unsigned int) base, ln2size); - if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) - printf(", port disabled\n"); - else if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) - printf(", memory disabled\n"); - else - printf(", enabled\n"); - } - - /* - * This code theoretically does the right thing, but has - * undesirable side effects in some cases where - * peripherals respond oddly to having these bits - * enabled. Leave them alone by default. - */ -#ifdef PCI_ENABLE_IO_MODES - /* Turn on resources that have been left off by a lazy BIOS */ - if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) { - cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); - cmd |= PCIM_CMD_PORTEN; - PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); - } - if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) { - cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); - cmd |= PCIM_CMD_MEMEN; - PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); - } -#else - if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) - return 1; - if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) - return 1; -#endif - - resource_list_add(rl, type, reg, - base, base + (1 << ln2size) - 1, - (1 << ln2size)); - - return (ln2range == 64) ? 2 : 1; -} - -static void -pci_add_resources(device_t pcib, int b, int s, int f, device_t dev) -{ - struct pci_devinfo *dinfo = device_get_ivars(dev); - pcicfgregs *cfg = &dinfo->cfg; - struct resource_list *rl = &dinfo->resources; - struct pci_quirk *q; - int i; - - for (i = 0; i < cfg->nummaps;) { - i += pci_add_map(pcib, b, s, f, PCIR_MAPS + i*4, rl); - } - - for (q = &pci_quirks[0]; q->devid; q++) { - if (q->devid == ((cfg->device << 16) | cfg->vendor) - && q->type == PCI_QUIRK_MAP_REG) - pci_add_map(pcib, b, s, f, q->arg1, rl); - } - - if (cfg->intpin > 0 && cfg->intline != 255) - resource_list_add(rl, SYS_RES_IRQ, 0, - cfg->intline, cfg->intline, 1); -} - -static void -pci_add_children(device_t dev, int busno) -{ - device_t pcib = device_get_parent(dev); - int maxslots; - int s, f; - - maxslots = PCIB_MAXSLOTS(pcib); - - for (s = 0; s <= maxslots; s++) { - int pcifunchigh = 0; - for (f = 0; f <= pcifunchigh; f++) { - struct pci_devinfo *dinfo = - pci_read_device(pcib, busno, s, f); - if (dinfo != NULL) { - if (dinfo->cfg.mfdev) - pcifunchigh = 7; - - pci_print_verbose(dinfo); - dinfo->cfg.dev = device_add_child(dev, NULL, -1); - device_set_ivars(dinfo->cfg.dev, dinfo); - pci_add_resources(pcib, busno, s, f, - dinfo->cfg.dev); - } - } - } -} - -static int -pci_probe(device_t dev) -{ - static int once, busno; - - device_set_desc(dev, "PCI bus"); - - if (bootverbose) - device_printf(dev, "physical bus=%d\n", pcib_get_bus(dev)); - - /* - * Since there can be multiple independantly numbered PCI - * busses on some large alpha systems, we can't use the unit - * number to decide what bus we are probing. We ask the parent - * pcib what our bus number is. - */ - busno = pcib_get_bus(dev); - if (busno < 0) - return ENXIO; - pci_add_children(dev, busno); - - if (!once) { - make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644, "pci"); - once++; - } - - return 0; -} - -static int -pci_print_resources(struct resource_list *rl, const char *name, int type, - const char *format) -{ - struct resource_list_entry *rle; - int printed, retval; - - printed = 0; - retval = 0; - /* Yes, this is kinda cheating */ - SLIST_FOREACH(rle, rl, link) { - if (rle->type == type) { - if (printed == 0) - retval += printf(" %s ", name); - else if (printed > 0) - retval += printf(","); - printed++; - retval += printf(format, rle->start); - if (rle->count > 1) { - retval += printf("-"); - retval += printf(format, rle->start + - rle->count - 1); - } - } - } - return retval; -} - -static int -pci_print_child(device_t dev, device_t child) -{ - struct pci_devinfo *dinfo; - struct resource_list *rl; - pcicfgregs *cfg; - int retval = 0; - - dinfo = device_get_ivars(child); - cfg = &dinfo->cfg; - rl = &dinfo->resources; - - retval += bus_print_child_header(dev, child); - - retval += pci_print_resources(rl, "port", SYS_RES_IOPORT, "%#lx"); - retval += pci_print_resources(rl, "mem", SYS_RES_MEMORY, "%#lx"); - retval += pci_print_resources(rl, "irq", SYS_RES_IRQ, "%ld"); - if (device_get_flags(dev)) - retval += printf(" flags %#x", device_get_flags(dev)); - - retval += printf(" at device %d.%d", pci_get_slot(child), - pci_get_function(child)); - - retval += bus_print_child_footer(dev, child); - - return (retval); -} - -static void -pci_probe_nomatch(device_t dev, device_t child) -{ - struct pci_devinfo *dinfo; - pcicfgregs *cfg; - const char *desc; - int unknown; - - unknown = 0; - dinfo = device_get_ivars(child); - cfg = &dinfo->cfg; - desc = pci_ata_match(child); - if (!desc) desc = pci_usb_match(child); - if (!desc) desc = pci_vga_match(child); - if (!desc) desc = pci_chip_match(child); - if (!desc) { - desc = "unknown card"; - unknown++; - } - device_printf(dev, "<%s>", desc); - if (bootverbose || unknown) { - printf(" (vendor=0x%04x, dev=0x%04x)", - cfg->vendor, - cfg->device); - } - printf(" at %d.%d", - pci_get_slot(child), - pci_get_function(child)); - if (cfg->intpin > 0 && cfg->intline != 255) { - printf(" irq %d", cfg->intline); - } - printf("\n"); - - return; -} - -static int -pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) -{ - struct pci_devinfo *dinfo; - pcicfgregs *cfg; - - dinfo = device_get_ivars(child); - cfg = &dinfo->cfg; - - switch (which) { - case PCI_IVAR_SUBVENDOR: - *result = cfg->subvendor; - break; - case PCI_IVAR_SUBDEVICE: - *result = cfg->subdevice; - break; - case PCI_IVAR_VENDOR: - *result = cfg->vendor; - break; - case PCI_IVAR_DEVICE: - *result = cfg->device; - break; - case PCI_IVAR_DEVID: - *result = (cfg->device << 16) | cfg->vendor; - break; - case PCI_IVAR_CLASS: - *result = cfg->baseclass; - break; - case PCI_IVAR_SUBCLASS: - *result = cfg->subclass; - break; - case PCI_IVAR_PROGIF: - *result = cfg->progif; - break; - case PCI_IVAR_REVID: - *result = cfg->revid; - break; - case PCI_IVAR_INTPIN: - *result = cfg->intpin; - break; - case PCI_IVAR_IRQ: - *result = cfg->intline; - break; - case PCI_IVAR_BUS: - *result = cfg->bus; - break; - case PCI_IVAR_SLOT: - *result = cfg->slot; - break; - case PCI_IVAR_FUNCTION: - *result = cfg->func; - break; - case PCI_IVAR_SECONDARYBUS: - *result = cfg->secondarybus; - break; - case PCI_IVAR_SUBORDINATEBUS: - *result = cfg->subordinatebus; - break; - default: - return ENOENT; - } - return 0; -} - -static int -pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value) -{ - struct pci_devinfo *dinfo; - pcicfgregs *cfg; - - dinfo = device_get_ivars(child); - cfg = &dinfo->cfg; - - switch (which) { - case PCI_IVAR_SUBVENDOR: - case PCI_IVAR_SUBDEVICE: - case PCI_IVAR_VENDOR: - case PCI_IVAR_DEVICE: - case PCI_IVAR_DEVID: - case PCI_IVAR_CLASS: - case PCI_IVAR_SUBCLASS: - case PCI_IVAR_PROGIF: - case PCI_IVAR_REVID: - case PCI_IVAR_INTPIN: - case PCI_IVAR_IRQ: - case PCI_IVAR_BUS: - case PCI_IVAR_SLOT: - case PCI_IVAR_FUNCTION: - return EINVAL; /* disallow for now */ - - case PCI_IVAR_SECONDARYBUS: - cfg->secondarybus = value; - break; - case PCI_IVAR_SUBORDINATEBUS: - cfg->subordinatebus = value; - break; - default: - return ENOENT; - } - return 0; -} - -static struct resource * -pci_alloc_resource(device_t dev, device_t child, int type, int *rid, - u_long start, u_long end, u_long count, u_int flags) -{ - struct pci_devinfo *dinfo = device_get_ivars(child); - struct resource_list *rl = &dinfo->resources; - pcicfgregs *cfg = &dinfo->cfg; - - /* - * Perform lazy resource allocation - * - * XXX add support here for SYS_RES_IOPORT and SYS_RES_MEMORY - */ - if (device_get_parent(child) == dev) { - if ((type == SYS_RES_IRQ) && (cfg->intline == 255)) { -#ifdef __i386__ - cfg->intline = PCIB_ROUTE_INTERRUPT( - device_get_parent(dev), pci_get_slot(child), - cfg->intpin); -#endif /* __i386__ */ - if (cfg->intline != 255) { - pci_write_config(child, PCIR_INTLINE, cfg->intline, 1); - resource_list_add(rl, SYS_RES_IRQ, 0, - cfg->intline, cfg->intline, 1); - } - } - } - - return resource_list_alloc(rl, dev, child, type, rid, - start, end, count, flags); -} - -static void -pci_delete_resource(device_t dev, device_t child, int type, int rid) -{ - printf("pci_delete_resource: PCI resources can not be deleted\n"); -} - -static struct resource_list * -pci_get_resource_list (device_t dev, device_t child) -{ - struct pci_devinfo * dinfo = device_get_ivars(child); - struct resource_list * rl = &dinfo->resources; - - if (!rl) - return (NULL); - - return (rl); -} - -static u_int32_t -pci_read_config_method(device_t dev, device_t child, int reg, int width) -{ - struct pci_devinfo *dinfo = device_get_ivars(child); - pcicfgregs *cfg = &dinfo->cfg; - - return PCIB_READ_CONFIG(device_get_parent(dev), - cfg->bus, cfg->slot, cfg->func, - reg, width); -} - -static void -pci_write_config_method(device_t dev, device_t child, int reg, - u_int32_t val, int width) -{ - struct pci_devinfo *dinfo = device_get_ivars(child); - pcicfgregs *cfg = &dinfo->cfg; - - PCIB_WRITE_CONFIG(device_get_parent(dev), - cfg->bus, cfg->slot, cfg->func, - reg, val, width); -} - -static int -pci_modevent(module_t mod, int what, void *arg) -{ - switch (what) { - case MOD_LOAD: - STAILQ_INIT(&pci_devq); - break; - - case MOD_UNLOAD: - break; - } - - return 0; -} - -static device_method_t pci_methods[] = { - /* Device interface */ - DEVMETHOD(device_probe, pci_probe), - DEVMETHOD(device_attach, bus_generic_attach), - DEVMETHOD(device_shutdown, bus_generic_shutdown), - DEVMETHOD(device_suspend, bus_generic_suspend), - DEVMETHOD(device_resume, bus_generic_resume), - - /* Bus interface */ - DEVMETHOD(bus_print_child, pci_print_child), - DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch), - DEVMETHOD(bus_read_ivar, pci_read_ivar), - DEVMETHOD(bus_write_ivar, pci_write_ivar), - DEVMETHOD(bus_driver_added, bus_generic_driver_added), - DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), - DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), - - DEVMETHOD(bus_get_resource_list,pci_get_resource_list), - DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), - DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), - DEVMETHOD(bus_delete_resource, pci_delete_resource), - DEVMETHOD(bus_alloc_resource, pci_alloc_resource), - DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource), - DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), - DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), - - /* PCI interface */ - DEVMETHOD(pci_read_config, pci_read_config_method), - DEVMETHOD(pci_write_config, pci_write_config_method), - - { 0, 0 } -}; - -static driver_t pci_driver = { - "pci", - pci_methods, - 1, /* no softc */ -}; -DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0); -DRIVER_MODULE(pci, acpi_pcib, pci_driver, pci_devclass, pci_modevent, 0); diff --git a/sys/pci/pci_if.m b/sys/pci/pci_if.m deleted file mode 100644 index e055f42..0000000 --- a/sys/pci/pci_if.m +++ /dev/null @@ -1,46 +0,0 @@ -# -# Copyright (c) 1998 Doug Rabson -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# -# THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND -# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -# ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE -# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -# OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -# HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -# OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -# SUCH DAMAGE. -# -# $FreeBSD$ -# - -#include <sys/bus.h> - -INTERFACE pci; - -METHOD u_int32_t read_config { - device_t dev; - device_t child; - int reg; - int width; -}; - -METHOD void write_config { - device_t dev; - device_t child; - int reg; - u_int32_t val; - int width; -}; diff --git a/sys/pci/pcib_if.m b/sys/pci/pcib_if.m deleted file mode 100644 index 5224778..0000000 --- a/sys/pci/pcib_if.m +++ /dev/null @@ -1,81 +0,0 @@ -# -# Copyright (c) 2000 Doug Rabson -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# -# THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND -# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -# ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE -# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -# OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -# HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -# OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -# SUCH DAMAGE. -# -# $FreeBSD$ -# - -#include <sys/bus.h> - -INTERFACE pcib; - -# -# Return the number of slots on the attached PCI bus. -# -METHOD int maxslots { - device_t dev; -}; - -# -# Read configuration space on the PCI bus. The bus, slot and func -# arguments determine the device which is being read and the reg -# argument is a byte offset into configuration space for that -# device. The width argument (which should be 1, 2 or 4) specifies how -# many byte of configuration space to read from that offset. -# -METHOD u_int32_t read_config { - device_t dev; - u_int bus; - u_int slot; - u_int func; - u_int reg; - int width; -}; - -# -# Write configuration space on the PCI bus. The bus, slot and func -# arguments determine the device which is being written and the reg -# argument is a byte offset into configuration space for that -# device. The value field is written to the configuration space, with -# the number of bytes written depending on the width argument. -# -METHOD void write_config { - device_t dev; - u_int bus; - u_int slot; - u_int func; - u_int reg; - u_int32_t value; - int width; -}; - -# -# Route an interrupt. Returns a value suitable for stuffing into -# a device's interrupt register. -# -METHOD int route_interrupt { - device_t dev; - int device; - int pin; -}; diff --git a/sys/pci/pcireg.h b/sys/pci/pcireg.h deleted file mode 100644 index eb5c471..0000000 --- a/sys/pci/pcireg.h +++ /dev/null @@ -1,261 +0,0 @@ -/* - * Copyright (c) 1997, Stefan Esser <se@freebsd.org> - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice unmodified, this list of conditions, and the following - * disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * $FreeBSD$ - * - */ - -/* - * PCIM_xxx: mask to locate subfield in register - * PCIR_xxx: config register offset - * PCIC_xxx: device class - * PCIS_xxx: device subclass - * PCIP_xxx: device programming interface - * PCIV_xxx: PCI vendor ID (only required to fixup ancient devices) - * PCID_xxx: device ID - */ - -/* some PCI bus constants */ - -#define PCI_BUSMAX 255 -#define PCI_SLOTMAX 31 -#define PCI_FUNCMAX 7 -#define PCI_REGMAX 255 - -/* PCI config header registers for all devices */ - -#define PCIR_DEVVENDOR 0x00 -#define PCIR_VENDOR 0x00 -#define PCIR_DEVICE 0x02 -#define PCIR_COMMAND 0x04 -#define PCIM_CMD_PORTEN 0x0001 -#define PCIM_CMD_MEMEN 0x0002 -#define PCIM_CMD_MWRICEN 0x0010 -#define PCIM_CMD_BUSMASTEREN 0x0004 -#define PCIM_CMD_PERRESPEN 0x0040 -#define PCIR_STATUS 0x06 -#define PCIR_REVID 0x08 -#define PCIR_PROGIF 0x09 -#define PCIR_SUBCLASS 0x0a -#define PCIR_CLASS 0x0b -#define PCIR_CACHELNSZ 0x0c -#define PCIR_LATTIMER 0x0d -#define PCIR_HEADERTYPE 0x0e -#define PCIM_MFDEV 0x80 -#define PCIR_BIST 0x0f - -/* config registers for header type 0 devices */ - -#define PCIR_MAPS 0x10 -#define PCIR_CARDBUSCIS 0x28 -#define PCIR_SUBVEND_0 0x2c -#define PCIR_SUBDEV_0 0x2e -#define PCIR_BIOS 0x30 -#define PCIM_BIOS_ENABLE 0x01 -#define PCIR_INTLINE 0x3c -#define PCIR_INTPIN 0x3d -#define PCIR_MINGNT 0x3e -#define PCIR_MAXLAT 0x3f - -/* config registers for header type 1 devices */ - -#define PCIR_SECSTAT_1 0 /**/ - -#define PCIR_PRIBUS_1 0x18 -#define PCIR_SECBUS_1 0x19 -#define PCIR_SUBBUS_1 0x1a -#define PCIR_SECLAT_1 0x1b - -#define PCIR_IOBASEL_1 0x1c -#define PCIR_IOLIMITL_1 0x1d -#define PCIR_IOBASEH_1 0 /**/ -#define PCIR_IOLIMITH_1 0 /**/ - -#define PCIR_MEMBASE_1 0x20 -#define PCIR_MEMLIMIT_1 0x22 - -#define PCIR_PMBASEL_1 0x24 -#define PCIR_PMLIMITL_1 0x26 -#define PCIR_PMBASEH_1 0 /**/ -#define PCIR_PMLIMITH_1 0 /**/ - -#define PCIR_BRIDGECTL_1 0 /**/ - -#define PCIR_SUBVEND_1 0x34 -#define PCIR_SUBDEV_1 0x36 - -/* config registers for header type 2 devices */ - -#define PCIR_SECSTAT_2 0x16 - -#define PCIR_PRIBUS_2 0x18 -#define PCIR_SECBUS_2 0x19 -#define PCIR_SUBBUS_2 0x1a -#define PCIR_SECLAT_2 0x1b - -#define PCIR_MEMBASE0_2 0x1c -#define PCIR_MEMLIMIT0_2 0x20 -#define PCIR_MEMBASE1_2 0x24 -#define PCIR_MEMLIMIT1_2 0x28 -#define PCIR_IOBASE0_2 0x2c -#define PCIR_IOLIMIT0_2 0x30 -#define PCIR_IOBASE1_2 0x34 -#define PCIR_IOLIMIT1_2 0x38 - -#define PCIR_BRIDGECTL_2 0x3e - -#define PCIR_SUBVEND_2 0x40 -#define PCIR_SUBDEV_2 0x42 - -#define PCIR_PCCARDIF_2 0x44 - -/* PCI device class, subclass and programming interface definitions */ - -#define PCIC_OLD 0x00 -#define PCIS_OLD_NONVGA 0x00 -#define PCIS_OLD_VGA 0x01 - -#define PCIC_STORAGE 0x01 -#define PCIS_STORAGE_SCSI 0x00 -#define PCIS_STORAGE_IDE 0x01 -#define PCIP_STORAGE_IDE_MODEPRIM 0x01 -#define PCIP_STORAGE_IDE_PROGINDPRIM 0x02 -#define PCIP_STORAGE_IDE_MODESEC 0x04 -#define PCIP_STORAGE_IDE_PROGINDSEC 0x08 -#define PCIP_STORAGE_IDE_MASTERDEV 0x80 -#define PCIS_STORAGE_FLOPPY 0x02 -#define PCIS_STORAGE_IPI 0x03 -#define PCIS_STORAGE_RAID 0x04 -#define PCIS_STORAGE_OTHER 0x80 - -#define PCIC_NETWORK 0x02 -#define PCIS_NETWORK_ETHERNET 0x00 -#define PCIS_NETWORK_TOKENRING 0x01 -#define PCIS_NETWORK_FDDI 0x02 -#define PCIS_NETWORK_ATM 0x03 -#define PCIS_NETWORK_OTHER 0x80 - -#define PCIC_DISPLAY 0x03 -#define PCIS_DISPLAY_VGA 0x00 -#define PCIS_DISPLAY_XGA 0x01 -#define PCIS_DISPLAY_OTHER 0x80 - -#define PCIC_MULTIMEDIA 0x04 -#define PCIS_MULTIMEDIA_VIDEO 0x00 -#define PCIS_MULTIMEDIA_AUDIO 0x01 -#define PCIS_MULTIMEDIA_OTHER 0x80 - -#define PCIC_MEMORY 0x05 -#define PCIS_MEMORY_RAM 0x00 -#define PCIS_MEMORY_FLASH 0x01 -#define PCIS_MEMORY_OTHER 0x80 - -#define PCIC_BRIDGE 0x06 -#define PCIS_BRIDGE_HOST 0x00 -#define PCIS_BRIDGE_ISA 0x01 -#define PCIS_BRIDGE_EISA 0x02 -#define PCIS_BRIDGE_MCA 0x03 -#define PCIS_BRIDGE_PCI 0x04 -#define PCIS_BRIDGE_PCMCIA 0x05 -#define PCIS_BRIDGE_NUBUS 0x06 -#define PCIS_BRIDGE_CARDBUS 0x07 -#define PCIS_BRIDGE_OTHER 0x80 - -#define PCIC_SIMPLECOMM 0x07 -#define PCIS_SIMPLECOMM_UART 0x00 -#define PCIP_SIMPLECOMM_UART_16550A 0x02 -#define PCIS_SIMPLECOMM_PAR 0x01 -#define PCIS_SIMPLECOMM_OTHER 0x80 - -#define PCIC_BASEPERIPH 0x08 -#define PCIS_BASEPERIPH_PIC 0x00 -#define PCIS_BASEPERIPH_DMA 0x01 -#define PCIS_BASEPERIPH_TIMER 0x02 -#define PCIS_BASEPERIPH_RTC 0x03 -#define PCIS_BASEPERIPH_OTHER 0x80 - -#define PCIC_INPUTDEV 0x09 -#define PCIS_INPUTDEV_KEYBOARD 0x00 -#define PCIS_INPUTDEV_DIGITIZER 0x01 -#define PCIS_INPUTDEV_MOUSE 0x02 -#define PCIS_INPUTDEV_OTHER 0x80 - -#define PCIC_DOCKING 0x0a -#define PCIS_DOCKING_GENERIC 0x00 -#define PCIS_DOCKING_OTHER 0x80 - -#define PCIC_PROCESSOR 0x0b -#define PCIS_PROCESSOR_386 0x00 -#define PCIS_PROCESSOR_486 0x01 -#define PCIS_PROCESSOR_PENTIUM 0x02 -#define PCIS_PROCESSOR_ALPHA 0x10 -#define PCIS_PROCESSOR_POWERPC 0x20 -#define PCIS_PROCESSOR_COPROC 0x40 - -#define PCIC_SERIALBUS 0x0c -#define PCIS_SERIALBUS_FW 0x00 -#define PCIS_SERIALBUS_ACCESS 0x01 -#define PCIS_SERIALBUS_SSA 0x02 -#define PCIS_SERIALBUS_USB 0x03 -#define PCIS_SERIALBUS_FC 0x04 -#define PCIS_SERIALBUS_SMBUS 0x05 - -#define PCIC_OTHER 0xff - -/* some PCI vendor definitions (only used to identify ancient devices !!! */ - -#define PCIV_INTEL 0x8086 - -#define PCID_INTEL_SATURN 0x0483 -#define PCID_INTEL_ORION 0x84c4 - -/* for compatibility to FreeBSD-2.2 and 3.x versions of PCI code */ - -#if defined(_KERNEL) && !defined(KLD_MODULE) -#include "opt_compat_oldpci.h" -#endif - -#ifdef COMPAT_OLDPCI - -#define PCI_ID_REG 0x00 -#define PCI_COMMAND_STATUS_REG 0x04 -#define PCI_COMMAND_IO_ENABLE 0x00000001 -#define PCI_COMMAND_MEM_ENABLE 0x00000002 -#define PCI_CLASS_REG 0x08 -#define PCI_CLASS_MASK 0xff000000 -#define PCI_SUBCLASS_MASK 0x00ff0000 -#define PCI_REVISION_MASK 0x000000ff -#define PCI_CLASS_PREHISTORIC 0x00000000 -#define PCI_SUBCLASS_PREHISTORIC_VGA 0x00010000 -#define PCI_CLASS_MASS_STORAGE 0x01000000 -#define PCI_CLASS_DISPLAY 0x03000000 -#define PCI_SUBCLASS_DISPLAY_VGA 0x00000000 -#define PCI_CLASS_BRIDGE 0x06000000 -#define PCI_MAP_REG_START 0x10 -#define PCI_MAP_REG_END 0x28 -#define PCI_MAP_IO 0x00000001 -#define PCI_INTERRUPT_REG 0x3c - -#endif /* COMPAT_OLDPCI */ diff --git a/sys/pci/pcisupport.c b/sys/pci/pcisupport.c deleted file mode 100644 index 0ec0ddc..0000000 --- a/sys/pci/pcisupport.c +++ /dev/null @@ -1,1992 +0,0 @@ -/************************************************************************** -** -** $FreeBSD$ -** -** Device driver for DEC/INTEL PCI chipsets. -** -** FreeBSD -** -**------------------------------------------------------------------------- -** -** Written for FreeBSD by -** wolf@cologne.de Wolfgang Stanglmeier -** se@mi.Uni-Koeln.de Stefan Esser -** -**------------------------------------------------------------------------- -** -** Copyright (c) 1994,1995 Stefan Esser. All rights reserved. -** -** Redistribution and use in source and binary forms, with or without -** modification, are permitted provided that the following conditions -** are met: -** 1. Redistributions of source code must retain the above copyright -** notice, this list of conditions and the following disclaimer. -** 2. Redistributions in binary form must reproduce the above copyright -** notice, this list of conditions and the following disclaimer in the -** documentation and/or other materials provided with the distribution. -** 3. The name of the author may not be used to endorse or promote products -** derived from this software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -** DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -*************************************************************************** -*/ - -#include "opt_bus.h" -#include "opt_pci.h" - -#include <sys/param.h> -#include <sys/systm.h> -#include <sys/malloc.h> -#include <sys/kernel.h> -#include <sys/bus.h> - -#include <pci/pcivar.h> -#include <pci/pcireg.h> - -#include <vm/vm.h> -#include <vm/vm_object.h> -#include <vm/pmap.h> - -#include "pcib_if.h" - -/*--------------------------------------------------------- -** -** Intel chipsets for 486 / Pentium processor -** -**--------------------------------------------------------- -*/ - -static void chipset_attach(device_t dev, int unit); - -struct condmsg { - unsigned char port; - unsigned char mask; - unsigned char value; - char flags; - const char *text; -}; - - -static void -fixbushigh_i1225(device_t dev) -{ - int sublementarybus; - - sublementarybus = pci_read_config(dev, 0x41, 1); - if (sublementarybus != 0xff) { - pci_set_secondarybus(dev, sublementarybus + 1); - pci_set_subordinatebus(dev, sublementarybus + 1); - } -} - -static void -fixwsc_natoma(device_t dev) -{ - int pmccfg; - - pmccfg = pci_read_config(dev, 0x50, 2); -#if defined(SMP) - if (pmccfg & 0x8000) { - printf("Correcting Natoma config for SMP\n"); - pmccfg &= ~0x8000; - pci_write_config(dev, 0x50, 2, pmccfg); - } -#else - if ((pmccfg & 0x8000) == 0) { - printf("Correcting Natoma config for non-SMP\n"); - pmccfg |= 0x8000; - pci_write_config(dev, 0x50, 2, pmccfg); - } -#endif -} - -#ifndef PCI_QUIET - -#define M_XX 0 /* end of list */ -#define M_EQ 1 /* mask and return true if equal */ -#define M_NE 2 /* mask and return true if not equal */ -#define M_TR 3 /* don't read config, always true */ -#define M_EN 4 /* mask and print "enabled" if true, "disabled" if false */ -#define M_NN 5 /* opposite sense of M_EN */ - -static const struct condmsg conf82425ex[] = -{ - { 0x00, 0x00, 0x00, M_TR, "\tClock " }, - { 0x50, 0x06, 0x00, M_EQ, "25" }, - { 0x50, 0x06, 0x02, M_EQ, "33" }, - { 0x50, 0x04, 0x04, M_EQ, "??", }, - { 0x00, 0x00, 0x00, M_TR, "MHz, L1 Cache " }, - { 0x50, 0x01, 0x00, M_EQ, "Disabled\n" }, - { 0x50, 0x09, 0x01, M_EQ, "Write-through\n" }, - { 0x50, 0x09, 0x09, M_EQ, "Write-back\n" }, - - { 0x00, 0x00, 0x00, M_TR, "\tL2 Cache " }, - { 0x52, 0x07, 0x00, M_EQ, "Disabled" }, - { 0x52, 0x0f, 0x01, M_EQ, "64KB Write-through" }, - { 0x52, 0x0f, 0x02, M_EQ, "128KB Write-through" }, - { 0x52, 0x0f, 0x03, M_EQ, "256KB Write-through" }, - { 0x52, 0x0f, 0x04, M_EQ, "512KB Write-through" }, - { 0x52, 0x0f, 0x01, M_EQ, "64KB Write-back" }, - { 0x52, 0x0f, 0x02, M_EQ, "128KB Write-back" }, - { 0x52, 0x0f, 0x03, M_EQ, "256KB Write-back" }, - { 0x52, 0x0f, 0x04, M_EQ, "512KB Write-back" }, - { 0x53, 0x01, 0x00, M_EQ, ", 3-" }, - { 0x53, 0x01, 0x01, M_EQ, ", 2-" }, - { 0x53, 0x06, 0x00, M_EQ, "3-3-3" }, - { 0x53, 0x06, 0x02, M_EQ, "2-2-2" }, - { 0x53, 0x06, 0x04, M_EQ, "1-1-1" }, - { 0x53, 0x06, 0x06, M_EQ, "?-?-?" }, - { 0x53, 0x18, 0x00, M_EQ, "/4-2-2-2\n" }, - { 0x53, 0x18, 0x08, M_EQ, "/3-2-2-2\n" }, - { 0x53, 0x18, 0x10, M_EQ, "/?-?-?-?\n" }, - { 0x53, 0x18, 0x18, M_EQ, "/2-1-1-1\n" }, - - { 0x56, 0x00, 0x00, M_TR, "\tDRAM: " }, - { 0x56, 0x02, 0x02, M_EQ, "Fast Code Read, " }, - { 0x56, 0x04, 0x04, M_EQ, "Fast Data Read, " }, - { 0x56, 0x08, 0x08, M_EQ, "Fast Write, " }, - { 0x57, 0x20, 0x20, M_EQ, "Pipelined CAS" }, - { 0x57, 0x2e, 0x00, M_NE, "\n\t" }, - { 0x57, 0x00, 0x00, M_TR, "Timing: RAS: " }, - { 0x57, 0x07, 0x00, M_EQ, "4" }, - { 0x57, 0x07, 0x01, M_EQ, "3" }, - { 0x57, 0x07, 0x02, M_EQ, "2" }, - { 0x57, 0x07, 0x04, M_EQ, "1.5" }, - { 0x57, 0x07, 0x05, M_EQ, "1" }, - { 0x57, 0x00, 0x00, M_TR, " Clocks, CAS Read: " }, - { 0x57, 0x18, 0x00, M_EQ, "3/1", }, - { 0x57, 0x18, 0x00, M_EQ, "2/1", }, - { 0x57, 0x18, 0x00, M_EQ, "1.5/0.5", }, - { 0x57, 0x18, 0x00, M_EQ, "1/1", }, - { 0x57, 0x00, 0x00, M_TR, ", CAS Write: " }, - { 0x57, 0x20, 0x00, M_EQ, "2/1", }, - { 0x57, 0x20, 0x20, M_EQ, "1/1", }, - { 0x57, 0x00, 0x00, M_TR, "\n" }, - - { 0x40, 0x01, 0x01, M_EQ, "\tCPU-to-PCI Byte Merging\n" }, - { 0x40, 0x02, 0x02, M_EQ, "\tCPU-to-PCI Bursting\n" }, - { 0x40, 0x04, 0x04, M_EQ, "\tPCI Posted Writes\n" }, - { 0x40, 0x20, 0x00, M_EQ, "\tDRAM Parity Disabled\n" }, - - { 0x48, 0x03, 0x01, M_EQ, "\tPCI IDE controller: Primary (1F0h-1F7h,3F6h,3F7h)" }, - { 0x48, 0x03, 0x02, M_EQ, "\tPCI IDE controller: Secondary (170h-177h,376h,377h)" }, - { 0x4d, 0x01, 0x01, M_EQ, "\tRTC (70-77h)\n" }, - { 0x4d, 0x02, 0x02, M_EQ, "\tKeyboard (60,62,64,66h)\n" }, - { 0x4d, 0x08, 0x08, M_EQ, "\tIRQ12/M Mouse Function\n" }, - -/* end marker */ - { 0 } -}; - -static const struct condmsg conf82424zx[] = -{ - { 0x00, 0x00, 0x00, M_TR, "\tCPU: " }, - { 0x50, 0xe0, 0x00, M_EQ, "486DX" }, - { 0x50, 0xe0, 0x20, M_EQ, "486SX" }, - { 0x50, 0xe0, 0x40, M_EQ, "486DX2 or 486DX4" }, - { 0x50, 0xe0, 0x80, M_EQ, "Overdrive (writeback)" }, - - { 0x00, 0x00, 0x00, M_TR, ", bus=" }, - { 0x50, 0x03, 0x00, M_EQ, "25MHz" }, - { 0x50, 0x03, 0x01, M_EQ, "33MHz" }, - { 0x53, 0x01, 0x01, M_TR, ", CPU->Memory posting "}, - { 0x53, 0x01, 0x00, M_EQ, "OFF" }, - { 0x53, 0x01, 0x01, M_EQ, "ON" }, - - { 0x56, 0x30, 0x00, M_NE, "\n\tWarning:" }, - { 0x56, 0x20, 0x00, M_NE, " NO cache parity!" }, - { 0x56, 0x10, 0x00, M_NE, " NO DRAM parity!" }, - { 0x55, 0x04, 0x04, M_EQ, "\n\tWarning: refresh OFF! " }, - - { 0x00, 0x00, 0x00, M_TR, "\n\tCache: " }, - { 0x52, 0x01, 0x00, M_EQ, "None" }, - { 0x52, 0xc1, 0x01, M_EQ, "64KB" }, - { 0x52, 0xc1, 0x41, M_EQ, "128KB" }, - { 0x52, 0xc1, 0x81, M_EQ, "256KB" }, - { 0x52, 0xc1, 0xc1, M_EQ, "512KB" }, - { 0x52, 0x03, 0x01, M_EQ, " writethrough" }, - { 0x52, 0x03, 0x03, M_EQ, " writeback" }, - - { 0x52, 0x01, 0x01, M_EQ, ", cache clocks=" }, - { 0x52, 0x05, 0x01, M_EQ, "3-1-1-1" }, - { 0x52, 0x05, 0x05, M_EQ, "2-1-1-1" }, - - { 0x00, 0x00, 0x00, M_TR, "\n\tDRAM:" }, - { 0x55, 0x43, 0x00, M_NE, " page mode" }, - { 0x55, 0x02, 0x02, M_EQ, " code fetch" }, - { 0x55, 0x43, 0x43, M_EQ, "," }, - { 0x55, 0x43, 0x42, M_EQ, " and" }, - { 0x55, 0x40, 0x40, M_EQ, " read" }, - { 0x55, 0x03, 0x03, M_EQ, " and" }, - { 0x55, 0x43, 0x41, M_EQ, " and" }, - { 0x55, 0x01, 0x01, M_EQ, " write" }, - { 0x55, 0x43, 0x00, M_NE, "," }, - - { 0x00, 0x00, 0x00, M_TR, " memory clocks=" }, - { 0x55, 0x20, 0x00, M_EQ, "X-2-2-2" }, - { 0x55, 0x20, 0x20, M_EQ, "X-1-2-1" }, - - { 0x00, 0x00, 0x00, M_TR, "\n\tCPU->PCI: posting " }, - { 0x53, 0x02, 0x00, M_NE, "ON" }, - { 0x53, 0x02, 0x00, M_EQ, "OFF" }, - { 0x00, 0x00, 0x00, M_TR, ", burst mode " }, - { 0x54, 0x02, 0x00, M_NE, "ON" }, - { 0x54, 0x02, 0x00, M_EQ, "OFF" }, - { 0x00, 0x00, 0x00, M_TR, "\n\tPCI->Memory: posting " }, - { 0x54, 0x01, 0x00, M_NE, "ON" }, - { 0x54, 0x01, 0x00, M_EQ, "OFF" }, - - { 0x00, 0x00, 0x00, M_TR, "\n" }, - -/* end marker */ - { 0 } -}; - -static const struct condmsg conf82434lx[] = -{ - { 0x00, 0x00, 0x00, M_TR, "\tCPU: " }, - { 0x50, 0xe3, 0x82, M_EQ, "Pentium, 60MHz" }, - { 0x50, 0xe3, 0x83, M_EQ, "Pentium, 66MHz" }, - { 0x50, 0xe3, 0xa2, M_EQ, "Pentium, 90MHz" }, - { 0x50, 0xe3, 0xa3, M_EQ, "Pentium, 100MHz" }, - { 0x50, 0xc2, 0x82, M_NE, "(unknown)" }, - { 0x50, 0x04, 0x00, M_EQ, " (primary cache OFF)" }, - - { 0x53, 0x01, 0x01, M_TR, ", CPU->Memory posting "}, - { 0x53, 0x01, 0x01, M_NE, "OFF" }, - { 0x53, 0x01, 0x01, M_EQ, "ON" }, - - { 0x53, 0x08, 0x00, M_NE, ", read around write"}, - - { 0x70, 0x04, 0x00, M_EQ, "\n\tWarning: Cache parity disabled!" }, - { 0x57, 0x20, 0x00, M_NE, "\n\tWarning: DRAM parity mask!" }, - { 0x57, 0x01, 0x00, M_EQ, "\n\tWarning: refresh OFF! " }, - - { 0x00, 0x00, 0x00, M_TR, "\n\tCache: " }, - { 0x52, 0x01, 0x00, M_EQ, "None" }, - { 0x52, 0x81, 0x01, M_EQ, "" }, - { 0x52, 0xc1, 0x81, M_EQ, "256KB" }, - { 0x52, 0xc1, 0xc1, M_EQ, "512KB" }, - { 0x52, 0x03, 0x01, M_EQ, " writethrough" }, - { 0x52, 0x03, 0x03, M_EQ, " writeback" }, - - { 0x52, 0x01, 0x01, M_EQ, ", cache clocks=" }, - { 0x52, 0x21, 0x01, M_EQ, "3-2-2-2/4-2-2-2" }, - { 0x52, 0x21, 0x21, M_EQ, "3-1-1-1" }, - - { 0x52, 0x01, 0x01, M_EQ, "\n\tCache flags: " }, - { 0x52, 0x11, 0x11, M_EQ, " cache-all" }, - { 0x52, 0x09, 0x09, M_EQ, " byte-control" }, - { 0x52, 0x05, 0x05, M_EQ, " powersaver" }, - - { 0x00, 0x00, 0x00, M_TR, "\n\tDRAM:" }, - { 0x57, 0x10, 0x00, M_EQ, " page mode" }, - - { 0x00, 0x00, 0x00, M_TR, " memory clocks=" }, - { 0x57, 0xc0, 0x00, M_EQ, "X-4-4-4 (70ns)" }, - { 0x57, 0xc0, 0x40, M_EQ, "X-4-4-4/X-3-3-3 (60ns)" }, - { 0x57, 0xc0, 0x80, M_EQ, "???" }, - { 0x57, 0xc0, 0xc0, M_EQ, "X-3-3-3 (50ns)" }, - { 0x58, 0x02, 0x02, M_EQ, ", RAS-wait" }, - { 0x58, 0x01, 0x01, M_EQ, ", CAS-wait" }, - - { 0x00, 0x00, 0x00, M_TR, "\n\tCPU->PCI: posting " }, - { 0x53, 0x02, 0x02, M_EQ, "ON" }, - { 0x53, 0x02, 0x00, M_EQ, "OFF" }, - { 0x00, 0x00, 0x00, M_TR, ", burst mode " }, - { 0x54, 0x02, 0x00, M_NE, "ON" }, - { 0x54, 0x02, 0x00, M_EQ, "OFF" }, - { 0x54, 0x04, 0x00, M_TR, ", PCI clocks=" }, - { 0x54, 0x04, 0x00, M_EQ, "2-2-2-2" }, - { 0x54, 0x04, 0x00, M_NE, "2-1-1-1" }, - { 0x00, 0x00, 0x00, M_TR, "\n\tPCI->Memory: posting " }, - { 0x54, 0x01, 0x00, M_NE, "ON" }, - { 0x54, 0x01, 0x00, M_EQ, "OFF" }, - - { 0x57, 0x01, 0x01, M_EQ, "\n\tRefresh:" }, - { 0x57, 0x03, 0x03, M_EQ, " CAS#/RAS#(Hidden)" }, - { 0x57, 0x03, 0x01, M_EQ, " RAS#Only" }, - { 0x57, 0x05, 0x05, M_EQ, " BurstOf4" }, - - { 0x00, 0x00, 0x00, M_TR, "\n" }, - -/* end marker */ - { 0 } -}; - -static const struct condmsg conf82378[] = -{ - { 0x00, 0x00, 0x00, M_TR, "\tBus Modes:" }, - { 0x41, 0x04, 0x04, M_EQ, " Bus Park," }, - { 0x41, 0x02, 0x02, M_EQ, " Bus Lock," }, - { 0x41, 0x02, 0x00, M_EQ, " Resource Lock," }, - { 0x41, 0x01, 0x01, M_EQ, " GAT" }, - { 0x4d, 0x20, 0x20, M_EQ, "\n\tCoprocessor errors enabled" }, - { 0x4d, 0x10, 0x10, M_EQ, "\n\tMouse function enabled" }, - - { 0x4e, 0x30, 0x10, M_EQ, "\n\tIDE controller: Primary (1F0h-1F7h,3F6h,3F7h)" }, - { 0x4e, 0x30, 0x30, M_EQ, "\n\tIDE controller: Secondary (170h-177h,376h,377h)" }, - { 0x4e, 0x28, 0x08, M_EQ, "\n\tFloppy controller: 3F0h,3F1h " }, - { 0x4e, 0x24, 0x04, M_EQ, "\n\tFloppy controller: 3F2h-3F7h " }, - { 0x4e, 0x28, 0x28, M_EQ, "\n\tFloppy controller: 370h,371h " }, - { 0x4e, 0x24, 0x24, M_EQ, "\n\tFloppy controller: 372h-377h " }, - { 0x4e, 0x02, 0x02, M_EQ, "\n\tKeyboard controller: 60h,62h,64h,66h" }, - { 0x4e, 0x01, 0x01, M_EQ, "\n\tRTC: 70h-77h" }, - - { 0x4f, 0x80, 0x80, M_EQ, "\n\tConfiguration RAM: 0C00h,0800h-08FFh" }, - { 0x4f, 0x40, 0x40, M_EQ, "\n\tPort 92: enabled" }, - { 0x4f, 0x03, 0x00, M_EQ, "\n\tSerial Port A: COM1 (3F8h-3FFh)" }, - { 0x4f, 0x03, 0x01, M_EQ, "\n\tSerial Port A: COM2 (2F8h-2FFh)" }, - { 0x4f, 0x0c, 0x00, M_EQ, "\n\tSerial Port B: COM1 (3F8h-3FFh)" }, - { 0x4f, 0x0c, 0x04, M_EQ, "\n\tSerial Port B: COM2 (2F8h-2FFh)" }, - { 0x4f, 0x30, 0x00, M_EQ, "\n\tParallel Port: LPT1 (3BCh-3BFh)" }, - { 0x4f, 0x30, 0x04, M_EQ, "\n\tParallel Port: LPT2 (378h-37Fh)" }, - { 0x4f, 0x30, 0x20, M_EQ, "\n\tParallel Port: LPT3 (278h-27Fh)" }, - { 0x00, 0x00, 0x00, M_TR, "\n" }, - -/* end marker */ - { 0 } -}; - -static const struct condmsg conf82437fx[] = -{ - /* PCON -- PCI Control Register */ - { 0x00, 0x00, 0x00, M_TR, "\tCPU Inactivity timer: " }, - { 0x50, 0xe0, 0xe0, M_EQ, "8" }, - { 0x50, 0xe0, 0xd0, M_EQ, "7" }, - { 0x50, 0xe0, 0xc0, M_EQ, "6" }, - { 0x50, 0xe0, 0xb0, M_EQ, "5" }, - { 0x50, 0xe0, 0xa0, M_EQ, "4" }, - { 0x50, 0xe0, 0x90, M_EQ, "3" }, - { 0x50, 0xe0, 0x80, M_EQ, "2" }, - { 0x50, 0xe0, 0x00, M_EQ, "1" }, - { 0x00, 0x00, 0x00, M_TR, " clocks\n\tPeer Concurrency: " }, - { 0x50, 0x08, 0x08, M_EN, 0 }, - { 0x00, 0x00, 0x00, M_TR, "\n\tCPU-to-PCI Write Bursting: " }, - { 0x50, 0x04, 0x00, M_NN, 0 }, - { 0x00, 0x00, 0x00, M_TR, "\n\tPCI Streaming: " }, - { 0x50, 0x02, 0x00, M_NN, 0 }, - { 0x00, 0x00, 0x00, M_TR, "\n\tBus Concurrency: " }, - { 0x50, 0x01, 0x00, M_NN, 0 }, - - /* CC -- Cache Control Regsiter */ - { 0x00, 0x00, 0x00, M_TR, "\n\tCache:" }, - { 0x52, 0xc0, 0x80, M_EQ, " 512K" }, - { 0x52, 0xc0, 0x40, M_EQ, " 256K" }, - { 0x52, 0xc0, 0x00, M_EQ, " NO" }, - { 0x52, 0x30, 0x00, M_EQ, " pipelined-burst" }, - { 0x52, 0x30, 0x10, M_EQ, " burst" }, - { 0x52, 0x30, 0x20, M_EQ, " asynchronous" }, - { 0x52, 0x30, 0x30, M_EQ, " dual-bank pipelined-burst" }, - { 0x00, 0x00, 0x00, M_TR, " secondary; L1 " }, - { 0x52, 0x01, 0x00, M_EN, 0 }, - { 0x00, 0x00, 0x00, M_TR, "\n" }, - - /* DRAMC -- DRAM Control Register */ - { 0x57, 0x07, 0x00, M_EQ, "Warning: refresh OFF!\n" }, - { 0x00, 0x00, 0x00, M_TR, "\tDRAM:" }, - { 0x57, 0xc0, 0x00, M_EQ, " no memory hole" }, - { 0x57, 0xc0, 0x40, M_EQ, " 512K-640K memory hole" }, - { 0x57, 0xc0, 0x80, M_EQ, " 15M-16M memory hole" }, - { 0x57, 0x07, 0x01, M_EQ, ", 50 MHz refresh" }, - { 0x57, 0x07, 0x02, M_EQ, ", 60 MHz refresh" }, - { 0x57, 0x07, 0x03, M_EQ, ", 66 MHz refresh" }, - - /* DRAMT = DRAM Timing Register */ - { 0x00, 0x00, 0x00, M_TR, "\n\tRead burst timing: " }, - { 0x58, 0x60, 0x00, M_EQ, "x-4-4-4/x-4-4-4" }, - { 0x58, 0x60, 0x20, M_EQ, "x-3-3-3/x-4-4-4" }, - { 0x58, 0x60, 0x40, M_EQ, "x-2-2-2/x-3-3-3" }, - { 0x58, 0x60, 0x60, M_EQ, "???" }, - { 0x00, 0x00, 0x00, M_TR, "\n\tWrite burst timing: " }, - { 0x58, 0x18, 0x00, M_EQ, "x-4-4-4" }, - { 0x58, 0x18, 0x08, M_EQ, "x-3-3-3" }, - { 0x58, 0x18, 0x10, M_EQ, "x-2-2-2" }, - { 0x58, 0x18, 0x18, M_EQ, "???" }, - { 0x00, 0x00, 0x00, M_TR, "\n\tRAS-CAS delay: " }, - { 0x58, 0x04, 0x00, M_EQ, "3" }, - { 0x58, 0x04, 0x04, M_EQ, "2" }, - { 0x00, 0x00, 0x00, M_TR, " clocks\n" }, - - /* end marker */ - { 0 } -}; - -static const struct condmsg conf82437vx[] = -{ - /* PCON -- PCI Control Register */ - { 0x00, 0x00, 0x00, M_TR, "\n\tPCI Concurrency: " }, - { 0x50, 0x08, 0x08, M_EN, 0 }, - - /* CC -- Cache Control Regsiter */ - { 0x00, 0x00, 0x00, M_TR, "\n\tCache:" }, - { 0x52, 0xc0, 0x80, M_EQ, " 512K" }, - { 0x52, 0xc0, 0x40, M_EQ, " 256K" }, - { 0x52, 0xc0, 0x00, M_EQ, " NO" }, - { 0x52, 0x30, 0x00, M_EQ, " pipelined-burst" }, - { 0x52, 0x30, 0x10, M_EQ, " burst" }, - { 0x52, 0x30, 0x20, M_EQ, " asynchronous" }, - { 0x52, 0x30, 0x30, M_EQ, " dual-bank pipelined-burst" }, - { 0x00, 0x00, 0x00, M_TR, " secondary; L1 " }, - { 0x52, 0x01, 0x00, M_EN, 0 }, - { 0x00, 0x00, 0x00, M_TR, "\n" }, - - /* DRAMC -- DRAM Control Register */ - { 0x57, 0x07, 0x00, M_EQ, "Warning: refresh OFF!\n" }, - { 0x00, 0x00, 0x00, M_TR, "\tDRAM:" }, - { 0x57, 0xc0, 0x00, M_EQ, " no memory hole" }, - { 0x57, 0xc0, 0x40, M_EQ, " 512K-640K memory hole" }, - { 0x57, 0xc0, 0x80, M_EQ, " 15M-16M memory hole" }, - { 0x57, 0x07, 0x01, M_EQ, ", 50 MHz refresh" }, - { 0x57, 0x07, 0x02, M_EQ, ", 60 MHz refresh" }, - { 0x57, 0x07, 0x03, M_EQ, ", 66 MHz refresh" }, - - /* DRAMT = DRAM Timing Register */ - { 0x00, 0x00, 0x00, M_TR, "\n\tRead burst timing: " }, - { 0x58, 0x60, 0x00, M_EQ, "x-4-4-4/x-4-4-4" }, - { 0x58, 0x60, 0x20, M_EQ, "x-3-3-3/x-4-4-4" }, - { 0x58, 0x60, 0x40, M_EQ, "x-2-2-2/x-3-3-3" }, - { 0x58, 0x60, 0x60, M_EQ, "???" }, - { 0x00, 0x00, 0x00, M_TR, "\n\tWrite burst timing: " }, - { 0x58, 0x18, 0x00, M_EQ, "x-4-4-4" }, - { 0x58, 0x18, 0x08, M_EQ, "x-3-3-3" }, - { 0x58, 0x18, 0x10, M_EQ, "x-2-2-2" }, - { 0x58, 0x18, 0x18, M_EQ, "???" }, - { 0x00, 0x00, 0x00, M_TR, "\n\tRAS-CAS delay: " }, - { 0x58, 0x04, 0x00, M_EQ, "3" }, - { 0x58, 0x04, 0x04, M_EQ, "2" }, - { 0x00, 0x00, 0x00, M_TR, " clocks\n" }, - - /* end marker */ - { 0 } -}; - -static const struct condmsg conf82371fb[] = -{ - /* IORT -- ISA I/O Recovery Timer Register */ - { 0x00, 0x00, 0x00, M_TR, "\tI/O Recovery Timing: 8-bit " }, - { 0x4c, 0x40, 0x00, M_EQ, "3.5" }, - { 0x4c, 0x78, 0x48, M_EQ, "1" }, - { 0x4c, 0x78, 0x50, M_EQ, "2" }, - { 0x4c, 0x78, 0x58, M_EQ, "3" }, - { 0x4c, 0x78, 0x60, M_EQ, "4" }, - { 0x4c, 0x78, 0x68, M_EQ, "5" }, - { 0x4c, 0x78, 0x70, M_EQ, "6" }, - { 0x4c, 0x78, 0x78, M_EQ, "7" }, - { 0x4c, 0x78, 0x40, M_EQ, "8" }, - { 0x00, 0x00, 0x00, M_TR, " clocks, 16-bit " }, - { 0x4c, 0x04, 0x00, M_EQ, "3.5" }, - { 0x4c, 0x07, 0x05, M_EQ, "1" }, - { 0x4c, 0x07, 0x06, M_EQ, "2" }, - { 0x4c, 0x07, 0x07, M_EQ, "3" }, - { 0x4c, 0x07, 0x04, M_EQ, "4" }, - { 0x00, 0x00, 0x00, M_TR, " clocks\n" }, - - /* XBCS -- X-Bus Chip Select Register */ - { 0x00, 0x00, 0x00, M_TR, "\tExtended BIOS: " }, - { 0x4e, 0x80, 0x80, M_EN, 0 }, - { 0x00, 0x00, 0x00, M_TR, "\n\tLower BIOS: " }, - { 0x4e, 0x40, 0x40, M_EN, 0 }, - { 0x00, 0x00, 0x00, M_TR, "\n\tCoprocessor IRQ13: " }, - { 0x4e, 0x20, 0x20, M_EN, 0 }, - { 0x00, 0x00, 0x00, M_TR, "\n\tMouse IRQ12: " }, - { 0x4e, 0x10, 0x10, M_EN, 0 }, - { 0x00, 0x00, 0x00, M_TR, "\n" }, - - { 0x00, 0x00, 0x00, M_TR, "\tInterrupt Routing: " }, -#define PIRQ(x, n) \ - { 0x00, 0x00, 0x00, M_TR, n ": " }, \ - { x, 0x80, 0x80, M_EQ, "disabled" }, \ - { x, 0xc0, 0x40, M_EQ, "[shared] " }, \ - { x, 0x8f, 0x03, M_EQ, "IRQ3" }, \ - { x, 0x8f, 0x04, M_EQ, "IRQ4" }, \ - { x, 0x8f, 0x05, M_EQ, "IRQ5" }, \ - { x, 0x8f, 0x06, M_EQ, "IRQ6" }, \ - { x, 0x8f, 0x07, M_EQ, "IRQ7" }, \ - { x, 0x8f, 0x09, M_EQ, "IRQ9" }, \ - { x, 0x8f, 0x0a, M_EQ, "IRQ10" }, \ - { x, 0x8f, 0x0b, M_EQ, "IRQ11" }, \ - { x, 0x8f, 0x0c, M_EQ, "IRQ12" }, \ - { x, 0x8f, 0x0e, M_EQ, "IRQ14" }, \ - { x, 0x8f, 0x0f, M_EQ, "IRQ15" } - - /* Interrupt routing */ - PIRQ(0x60, "A"), - PIRQ(0x61, ", B"), - PIRQ(0x62, ", C"), - PIRQ(0x63, ", D"), - PIRQ(0x70, "\n\t\tMB0"), - PIRQ(0x71, ", MB1"), - - { 0x00, 0x00, 0x00, M_TR, "\n" }, - -#undef PIRQ - - /* XXX - do DMA routing, too? */ - { 0 } -}; - -static const struct condmsg conf82371fb2[] = -{ - /* IDETM -- IDE Timing Register */ - { 0x00, 0x00, 0x00, M_TR, "\tPrimary IDE: " }, - { 0x41, 0x80, 0x80, M_EN, 0 }, - { 0x00, 0x00, 0x00, M_TR, "\n\tSecondary IDE: " }, - { 0x43, 0x80, 0x80, M_EN, 0 }, - { 0x00, 0x00, 0x00, M_TR, "\n" }, - - /* end of list */ - { 0 } -}; - -static void -writeconfig (device_t dev, const struct condmsg *tbl) -{ - while (tbl->flags != M_XX) { - const char *text = 0; - - if (tbl->flags == M_TR) { - text = tbl->text; - } else { - unsigned char v = pci_read_config(dev, tbl->port, 1); - switch (tbl->flags) { - case M_EQ: - if ((v & tbl->mask) == tbl->value) text = tbl->text; - break; - case M_NE: - if ((v & tbl->mask) != tbl->value) text = tbl->text; - break; - case M_EN: - text = (v & tbl->mask) ? "enabled" : "disabled"; - break; - case M_NN: - text = (v & tbl->mask) ? "disabled" : "enabled"; - } - } - if (text) printf ("%s", text); - tbl++; - } -} - -#ifdef DUMPCONFIGSPACE -static void -dumpconfigspace (device_t dev) -{ - int reg; - printf ("configuration space registers:"); - for (reg = 0; reg < 0x100; reg+=4) { - if ((reg & 0x0f) == 0) - printf ("\n%02x:\t", reg); - printf ("%08x ", pci_read_config(dev, reg, 4)); - } - printf ("\n"); -} -#endif /* DUMPCONFIGSPACE */ - -#endif /* PCI_QUIET */ - - -static void -chipset_attach (device_t dev, int unit) -{ -#ifndef PCI_QUIET - if (!bootverbose) - return; - - switch (pci_get_devid(dev)) { - case 0x04868086: - writeconfig (dev, conf82425ex); - break; - case 0x04838086: - writeconfig (dev, conf82424zx); - break; - case 0x04a38086: - writeconfig (dev, conf82434lx); - break; - case 0x04848086: - writeconfig (dev, conf82378); - break; - case 0x122d8086: - writeconfig (dev, conf82437fx); - break; - case 0x70308086: - writeconfig (dev, conf82437vx); - break; - case 0x70008086: - case 0x122e8086: - writeconfig (dev, conf82371fb); - break; - case 0x70108086: - case 0x12308086: - writeconfig (dev, conf82371fb2); - break; -#if 0 - case 0x00011011: /* DEC 21050 */ - case 0x00221014: /* IBM xxx */ - writeconfig (dev, conf_pci2pci); - break; -#endif - }; -#endif /* PCI_QUIET */ -} - -static const char * -pci_bridge_type(device_t dev) -{ - char *descr, tmpbuf[120]; - - if (pci_get_class(dev) != PCIC_BRIDGE) - return NULL; - - switch (pci_get_subclass(dev)) { - case PCIS_BRIDGE_HOST: strcpy(tmpbuf, "Host to PCI"); break; - case PCIS_BRIDGE_ISA: strcpy(tmpbuf, "PCI to ISA"); break; - case PCIS_BRIDGE_EISA: strcpy(tmpbuf, "PCI to EISA"); break; - case PCIS_BRIDGE_MCA: strcpy(tmpbuf, "PCI to MCA"); break; - case PCIS_BRIDGE_PCI: strcpy(tmpbuf, "PCI to PCI"); break; - case PCIS_BRIDGE_PCMCIA: strcpy(tmpbuf, "PCI to PCMCIA"); break; - case PCIS_BRIDGE_NUBUS: strcpy(tmpbuf, "PCI to NUBUS"); break; - case PCIS_BRIDGE_CARDBUS: strcpy(tmpbuf, "PCI to CardBus"); break; - case PCIS_BRIDGE_OTHER: strcpy(tmpbuf, "PCI to Other"); break; - default: - snprintf(tmpbuf, sizeof(tmpbuf), - "PCI to 0x%x", pci_get_subclass(dev)); - break; - } - snprintf(tmpbuf+strlen(tmpbuf), sizeof(tmpbuf)-strlen(tmpbuf), - " bridge (vendor=%04x device=%04x)", - pci_get_vendor(dev), pci_get_device(dev)); - descr = malloc (strlen(tmpbuf) +1, M_DEVBUF, M_WAITOK); - strcpy(descr, tmpbuf); - return descr; -} - -static const char* -pcib_match(device_t dev) -{ - switch (pci_get_devid(dev)) { - /* Intel -- vendor 0x8086 */ - case 0x71818086: - return ("Intel 82443LX (440 LX) PCI-PCI (AGP) bridge"); - case 0x71918086: - return ("Intel 82443BX (440 BX) PCI-PCI (AGP) bridge"); - case 0x71A18086: - return ("Intel 82443GX (440 GX) PCI-PCI (AGP) bridge"); - case 0x11318086: - return ("Intel 82815 (i815 GMCH) PCI-PCI (AGP) bridge"); - case 0x84cb8086: - return ("Intel 82454NX PCI Expander Bridge"); - case 0x124b8086: - return ("Intel 82380FB mobile PCI to PCI bridge"); - case 0x24188086: - return ("Intel 82801AA (ICH) Hub to PCI bridge"); - case 0x24288086: - return ("Intel 82801AB (ICH0) Hub to PCI bridge"); - case 0x244E8086: - return ("Intel 82801BA (ICH2) Hub to PCI bridge"); - - /* VLSI -- vendor 0x1004 */ - case 0x01021004: - return ("VLSI 82C534 Eagle II PCI Bus bridge"); - case 0x01031004: - return ("VLSI 82C538 Eagle II PCI Docking bridge"); - - /* VIA Technologies -- vendor 0x1106 */ - case 0x85981106: - return ("VIA 82C598MVP/82C694X (Apollo MVP3/Pro133A) PCI-PCI (AGP) bridge"); - case 0x83911106: - return ("VIA 8371 (KX133) PCI-PCI (AGP) bridge"); - case 0x83051106: - return ("VIA 8363 (KT133) PCI-PCI (AGP) bridge"); - - /* AcerLabs -- vendor 0x10b9 */ - /* Funny : The datasheet told me vendor id is "10b8",sub-vendor */ - /* id is '10b9" but the register always shows "10b9". -Foxfair */ - case 0x524710b9: - return ("AcerLabs M5247 PCI-PCI(AGP Supported) bridge"); - case 0x524310b9:/* 5243 seems like 5247, need more info to divide*/ - return ("AcerLabs M5243 PCI-PCI bridge"); - - /* AMD -- vendor 0x1022 */ - case 0x70071022: - return ("AMD-751 PCI-PCI (AGP) bridge"); - - /* DEC -- vendor 0x1011 */ - case 0x00011011: - return ("DEC 21050 PCI-PCI bridge"); - case 0x00211011: - return ("DEC 21052 PCI-PCI bridge"); - case 0x00221011: - return ("DEC 21150 PCI-PCI bridge"); - case 0x00241011: - return ("DEC 21152 PCI-PCI bridge"); - case 0x00251011: - return ("DEC 21153 PCI-PCI bridge"); - case 0x00261011: - return ("DEC 21154 PCI-PCI bridge"); - - /* Compaq -- vendor 0x0e11 */ - case 0x60100e11: - return ("Compaq HotPlug PCI bridge"); - - /* Others */ - case 0x00221014: - return ("IBM 82351 PCI-PCI bridge"); - /* UMC United Microelectronics 0x1060 */ - case 0x88811060: - return ("UMC UM8881 HB4 486 PCI Chipset"); - }; - - if (pci_get_class(dev) == PCIC_BRIDGE - && pci_get_subclass(dev) == PCIS_BRIDGE_PCI) - return pci_bridge_type(dev); - - return NULL; -} - -static int pcib_probe(device_t dev) -{ - const char *desc; - - desc = pcib_match(dev); - if (desc) { - device_set_desc_copy(dev, desc); - return -10000; - } - - return ENXIO; -} - -static int pcib_attach(device_t dev) -{ - u_int8_t secondary; - device_t child; - - chipset_attach(dev, device_get_unit(dev)); - - secondary = pci_get_secondarybus(dev); - if (secondary) { - child = device_add_child(dev, "pci", -1); - *(int*) device_get_softc(dev) = secondary; - return bus_generic_attach(dev); - } else - return 0; -} - -static int -pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) -{ - switch (which) { - case PCIB_IVAR_BUS: - *result = *(int*) device_get_softc(dev); - return 0; - } - return ENOENT; -} - -static int -pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value) -{ - switch (which) { - case PCIB_IVAR_BUS: - *(int*) device_get_softc(dev) = value; - return 0; - } - return ENOENT; -} - -static int -pcib_maxslots(device_t dev) -{ - return 31; -} - -static u_int32_t -pcib_read_config(device_t dev, int b, int s, int f, - int reg, int width) -{ - /* - * Pass through to the next ppb up the chain (i.e. our - * grandparent). - */ - return PCIB_READ_CONFIG(device_get_parent(device_get_parent(dev)), - b, s, f, reg, width); -} - -static void -pcib_write_config(device_t dev, int b, int s, int f, - int reg, u_int32_t val, int width) -{ - /* - * Pass through to the next ppb up the chain (i.e. our - * grandparent). - */ - PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(dev)), - b, s, f, reg, val, width); -} - -static device_method_t pcib_methods[] = { - /* Device interface */ - DEVMETHOD(device_probe, pcib_probe), - DEVMETHOD(device_attach, pcib_attach), - DEVMETHOD(device_shutdown, bus_generic_shutdown), - DEVMETHOD(device_suspend, bus_generic_suspend), - DEVMETHOD(device_resume, bus_generic_resume), - - /* Bus interface */ - DEVMETHOD(bus_print_child, bus_generic_print_child), - DEVMETHOD(bus_read_ivar, pcib_read_ivar), - DEVMETHOD(bus_write_ivar, pcib_write_ivar), - DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource), - DEVMETHOD(bus_release_resource, bus_generic_release_resource), - DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), - DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), - DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), - DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), - - /* pcib interface */ - DEVMETHOD(pcib_maxslots, pcib_maxslots), - DEVMETHOD(pcib_read_config, pcib_read_config), - DEVMETHOD(pcib_write_config, pcib_write_config), - - { 0, 0 } -}; - -static driver_t pcib_driver = { - "pcib", - pcib_methods, - sizeof(int), -}; - -static devclass_t pcib_devclass; - -DRIVER_MODULE(pcib, pci, pcib_driver, pcib_devclass, 0, 0); - -static const char * -eisab_match(device_t dev) -{ - switch (pci_get_devid(dev)) { - case 0x04828086: - /* Recognize this specifically, it has PCI-HOST class (!) */ - return ("Intel 82375EB PCI-EISA bridge"); - } - if (pci_get_class(dev) == PCIC_BRIDGE - && pci_get_subclass(dev) == PCIS_BRIDGE_EISA) - return pci_bridge_type(dev); - - return NULL; -} - -static const char * -isab_match(device_t dev) -{ - unsigned rev; - - switch (pci_get_devid(dev)) { - case 0x04848086: - rev = pci_get_revid(dev); - if (rev == 3) - return ("Intel 82378ZB PCI to ISA bridge"); - return ("Intel 82378IB PCI to ISA bridge"); - case 0x122e8086: - return ("Intel 82371FB PCI to ISA bridge"); - case 0x70008086: - return ("Intel 82371SB PCI to ISA bridge"); - case 0x71108086: - return ("Intel 82371AB PCI to ISA bridge"); - case 0x71988086: - return ("Intel 82443MX PCI to X-bus bridge"); - case 0x24108086: - return ("Intel 82801AA (ICH) PCI to LPC bridge"); - case 0x24208086: - return ("Intel 82801AB (ICH0) PCI to LPC bridge"); - case 0x24408086: - return ("Intel 82801BA (ICH2) PCI to LPC bridge"); - - /* VLSI -- vendor 0x1004 */ - case 0x00061004: - return ("VLSI 82C593 PCI to ISA bridge"); - - /* VIA Technologies -- vendor 0x1106 */ - case 0x05861106: /* south bridge section */ - return ("VIA 82C586 PCI-ISA bridge"); - case 0x05961106: - return ("VIA 82C596 PCI-ISA bridge"); - case 0x06861106: - return ("VIA 82C686 PCI-ISA bridge"); - - /* AcerLabs -- vendor 0x10b9 */ - /* Funny : The datasheet told me vendor id is "10b8",sub-vendor */ - /* id is '10b9" but the register always shows "10b9". -Foxfair */ - case 0x153310b9: - return ("AcerLabs M1533 portable PCI-ISA bridge"); - case 0x154310b9: - return ("AcerLabs M1543 desktop PCI-ISA bridge"); - - /* SiS -- vendor 0x1039 */ - case 0x00081039: - return ("SiS 85c503 PCI-ISA bridge"); - - /* Cyrix -- vendor 0x1078 */ - case 0x00001078: - return ("Cyrix Cx5510 PCI-ISA bridge"); - case 0x01001078: - return ("Cyrix Cx5530 PCI-ISA bridge"); - - /* OPTi -- vendor 0x1045 */ - case 0xc7001045: - return ("OPTi 82C700 (FireStar) PCI-ISA bridge"); - - /* NEC -- vendor 0x1033 */ - /* The "C-bus" is 16-bits bus on PC98. */ - case 0x00011033: - return ("NEC 0001 PCI to PC-98 C-bus bridge"); - case 0x002c1033: - return ("NEC 002C PCI to PC-98 C-bus bridge"); - case 0x003b1033: - return ("NEC 003B PCI to PC-98 C-bus bridge"); - /* UMC United Microelectronics 0x1060 */ - case 0x886a1060: - return ("UMC UM8886 ISA Bridge with EIDE"); - - /* Cypress -- vendor 0x1080 */ - case 0xc6931080: - if (pci_get_class(dev) == PCIC_BRIDGE - && pci_get_subclass(dev) == PCIS_BRIDGE_ISA) - return ("Cypress 82C693 PCI-ISA bridge"); - break; - - /* ServerWorks -- vendor 0x1166 */ - case 0x02001166: - return ("ServerWorks IB6566 PCI to ISA bridge"); - } - - if (pci_get_class(dev) == PCIC_BRIDGE - && pci_get_subclass(dev) == PCIS_BRIDGE_ISA) - return pci_bridge_type(dev); - - return NULL; -} - -static int -isab_probe(device_t dev) -{ - const char *desc; - int is_eisa; - - is_eisa = 0; - desc = eisab_match(dev); - if (desc) - is_eisa = 1; - else - desc = isab_match(dev); - if (desc) { - /* - * For a PCI-EISA bridge, add both eisa and isa. - * Only add one instance of eisa or isa for now. - */ - device_set_desc_copy(dev, desc); - if (is_eisa && !devclass_get_device(devclass_find("eisa"), 0)) - device_add_child(dev, "eisa", -1); - - if (!devclass_get_device(devclass_find("isa"), 0)) - device_add_child(dev, "isa", -1); - return 0; - } - return ENXIO; -} - -static int -isab_attach(device_t dev) -{ - chipset_attach(dev, device_get_unit(dev)); - return bus_generic_attach(dev); -} - -static device_method_t isab_methods[] = { - /* Device interface */ - DEVMETHOD(device_probe, isab_probe), - DEVMETHOD(device_attach, isab_attach), - DEVMETHOD(device_shutdown, bus_generic_shutdown), - DEVMETHOD(device_suspend, bus_generic_suspend), - DEVMETHOD(device_resume, bus_generic_resume), - - /* Bus interface */ - DEVMETHOD(bus_print_child, bus_generic_print_child), - DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource), - DEVMETHOD(bus_release_resource, bus_generic_release_resource), - DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), - DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), - DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), - DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), - - { 0, 0 } -}; - -static driver_t isab_driver = { - "isab", - isab_methods, - 1, -}; - -static devclass_t isab_devclass; - -DRIVER_MODULE(isab, pci, isab_driver, isab_devclass, 0, 0); - -const char * -pci_usb_match(device_t dev) -{ - switch (pci_get_devid(dev)) { - - /* Intel -- vendor 0x8086 */ - case 0x70208086: - return ("Intel 82371SB (PIIX3) USB controller"); - case 0x71128086: - return ("Intel 82371AB/EB (PIIX4) USB controller"); - case 0x719a8086: - return ("Intel 82443MX USB controller"); - case 0x24128086: - return ("Intel 82801AA (ICH) USB controller"); - case 0x24228086: - return ("Intel 82801AB (ICH0) USB controller"); - case 0x24428086: - return ("Intel 82801BA (ICH2) USB controller #1"); - case 0x24448086: - return ("Intel 82801BA (ICH2) USB controller #2"); - - /* VIA Technologies -- vendor 0x1106 (0x1107 on the Apollo Master) */ - case 0x30381106: - return ("VIA 83C572 USB controller"); - - /* AcerLabs -- vendor 0x10b9 */ - case 0x523710b9: - return ("AcerLabs M5237 (Aladdin-V) USB controller"); - - /* OPTi -- vendor 0x1045 */ - case 0xc8611045: - return ("OPTi 82C861 (FireLink) USB controller"); - - /* NEC -- vendor 0x1033 */ - case 0x00351033: - return ("NEC uPD 9210 USB controller"); - - /* CMD Tech -- vendor 0x1095 */ - case 0x06701095: - return ("CMD Tech 670 (USB0670) USB controller"); - case 0x06731095: - return ("CMD Tech 673 (USB0673) USB controller"); - } - - if (pci_get_class(dev) == PCIC_SERIALBUS - && pci_get_subclass(dev) == PCIS_SERIALBUS_USB) { - if (pci_get_progif(dev) == 0x00 /* UHCI */ ) { - return ("UHCI USB controller"); - } else if (pci_get_progif(dev) == 0x10 /* OHCI */ ) { - return ("OHCI USB controller"); - } else { - return ("USB controller"); - } - } - return NULL; -} - -const char * -pci_ata_match(device_t dev) -{ - - switch (pci_get_devid(dev)) { - - /* Intel -- vendor 0x8086 */ - case 0x12308086: - return ("Intel PIIX ATA controller"); - case 0x70108086: - return ("Intel PIIX3 ATA controller"); - case 0x71118086: - return ("Intel PIIX4 ATA controller"); - case 0x12348086: - return ("Intel 82371MX mobile PCI ATA accelerator (MPIIX)"); - - /* Promise -- vendor 0x105a */ - case 0x4d33105a: - return ("Promise Ultra/33 ATA controller"); - case 0x4d38105a: - return ("Promise Ultra/66 ATA controller"); - - /* AcerLabs -- vendor 0x10b9 */ - case 0x522910b9: - return ("AcerLabs Aladdin ATA controller"); - - /* VIA Technologies -- vendor 0x1106 (0x1107 on the Apollo Master) */ - case 0x05711106: - switch (pci_read_config(dev, 0x08, 1)) { - case 1: - return ("VIA 85C586 ATA controller"); - case 6: - return ("VIA 85C586 ATA controller"); - } - /* FALL THROUGH */ - case 0x15711106: - return ("VIA Apollo ATA controller"); - - /* CMD Tech -- vendor 0x1095 */ - case 0x06401095: - return ("CMD 640 ATA controller"); - case 0x06461095: - return ("CMD 646 ATA controller"); - - /* Cypress -- vendor 0x1080 */ - case 0xc6931080: - return ("Cypress 82C693 ATA controller"); - - /* Cyrix -- vendor 0x1078 */ - case 0x01021078: - return ("Cyrix 5530 ATA controller"); - - /* SiS -- vendor 0x1039 */ - case 0x55131039: - return ("SiS 5591 ATA controller"); - - /* Highpoint tech -- vendor 0x1103 */ - case 0x00041103: - return ("HighPoint HPT366 ATA controller"); - - /* OPTi -- vendor 0x1045 */ - case 0xd5681045: - return ("OPTi 82C700 (FireStar) ATA controller(generic mode):"); - } - - if (pci_get_class(dev) == PCIC_STORAGE && - pci_get_subclass(dev) == PCIS_STORAGE_IDE) - return ("Unknown PCI ATA controller"); - - return NULL; -} - -const char* -pci_chip_match(device_t dev) -{ - unsigned rev; - - switch (pci_get_devid(dev)) { - /* Intel -- vendor 0x8086 */ - case 0x00088086: - /* Silently ignore this one! What is it, anyway ??? */ - return (""); - case 0x71108086: - /* - * On my laptop (Tecra 8000DVD), this device has a - * bogus subclass 0x80 so make sure that it doesn't - * match the generic 'chip' driver by accident. - */ - return NULL; - case 0x12258086: - fixbushigh_i1225(dev); - return ("Intel 82454KX/GX (Orion) host to PCI bridge"); - case 0x71808086: - return ("Intel 82443LX (440 LX) host to PCI bridge"); - case 0x71908086: - return ("Intel 82443BX (440 BX) host to PCI bridge"); - case 0x71928086: - return ("Intel 82443BX host to PCI bridge (AGP disabled)"); - case 0x71948086: - return ("Intel 82443MX (440 MX) host to PCI bridge"); - case 0x71a08086: - return ("Intel 82443GX host to PCI bridge"); - case 0x71a18086: - return ("Intel 82443GX host to AGP bridge"); - case 0x71a28086: - return ("Intel 82443GX host to PCI bridge (AGP disabled)"); - case 0x84c48086: - return ("Intel 82454KX/GX (Orion) host to PCI bridge"); - case 0x84ca8086: - return ("Intel 82451NX Memory and I/O controller"); - case 0x04868086: - return ("Intel 82425EX PCI system controller"); - case 0x04838086: - return ("Intel 82424ZX (Saturn) cache DRAM controller"); - case 0x04a38086: - rev = pci_get_revid(dev); - if (rev == 16 || rev == 17) - return ("Intel 82434NX (Neptune) PCI cache memory controller"); - return ("Intel 82434LX (Mercury) PCI cache memory controller"); - case 0x122d8086: - return ("Intel 82437FX PCI cache memory controller"); - case 0x12358086: - return ("Intel 82437MX mobile PCI cache memory controller"); - case 0x12508086: - return ("Intel 82439HX PCI cache memory controller"); - case 0x70308086: - return ("Intel 82437VX PCI cache memory controller"); - case 0x71008086: - return ("Intel 82439TX System controller (MTXC)"); - case 0x71138086: - return ("Intel 82371AB Power management controller"); - case 0x12378086: - fixwsc_natoma(dev); - return ("Intel 82440FX (Natoma) PCI and memory controller"); - case 0x84c58086: - return ("Intel 82453KX/GX (Orion) PCI memory controller"); - case 0x71208086: - return ("Intel 82810 (i810 GMCH) Host To Hub bridge"); - case 0x71228086: - return ("Intel 82810-DC100 (i810-DC100 GMCH) Host To Hub bridge"); - case 0x71248086: - return ("Intel 82810E (i810E GMCH) Host To Hub bridge"); - case 0x11308086: - return ("Intel 82815 (i815 GMCH) Host To Hub bridge"); - case 0x24158086: - return ("Intel 82801AA (ICH) AC'97 Audio Controller"); - case 0x24258086: - return ("Intel 82801AB (ICH0) AC'97 Audio Controller"); - case 0x24458086: - return ("Intel 82801BA (ICH2) AC'97 Audio Controller"); - case 0x24468086: - return ("Intel 82801BA (ICH2) AC'97 Modem Controller"); - case 0x71958086: - return ("Intel 82443MX AC'97 Audio Controller"); - case 0x719b8086: - return ("Intel 82443MX SMBus and power management controller"); - case 0x24438086: - return ("Intel 82801BA (ICH2) SMBus controller"); - - /* Sony -- vendor 0x104d */ - case 0x8009104d: - return ("Sony CXD1947A FireWire Host Controller"); - - /* SiS -- vendor 0x1039 */ - case 0x04961039: - return ("SiS 85c496 PCI/VL Bridge"); - case 0x04061039: - return ("SiS 85c501"); - case 0x06011039: - return ("SiS 85c601"); - case 0x55911039: - return ("SiS 5591 host to PCI bridge"); - case 0x00011039: - return ("SiS 5591 host to AGP bridge"); - - /* VLSI -- vendor 0x1004 */ - case 0x00051004: - return ("VLSI 82C592 Host to PCI bridge"); - case 0x01011004: - return ("VLSI 82C532 Eagle II Peripheral controller"); - case 0x01041004: - return ("VLSI 82C535 Eagle II System controller"); - case 0x01051004: - return ("VLSI 82C147 IrDA controller"); - - /* VIA Technologies -- vendor 0x1106 (0x1107 on the Apollo Master) */ - case 0x15761107: - return ("VIA 82C570 (Apollo Master) system controller"); - case 0x05851106: - return ("VIA 82C585 (Apollo VP1/VPX) system controller"); - case 0x05951106: - case 0x15951106: - return ("VIA 82C595 (Apollo VP2) system controller"); - case 0x05971106: - return ("VIA 82C597 (Apollo VP3) system controller"); - case 0x05981106: - return ("VIA 82C598 (Apollo MVP3) host bridge"); - case 0x06911106: - return ("VIA 82C691 (Apollo Pro) host bridge"); - case 0x06931106: - return ("VIA 82C693 (Apollo Pro+) host bridge"); - case 0x03911106: - return ("VIA 8371 (KX133) host to PCI bridge"); - case 0x30401106: - return ("VIA 82C586B ACPI interface"); - case 0x30501106: - return ("VIA 82C596B ACPI interface"); - case 0x30571106: - return ("VIA 82C686 ACPI interface"); - case 0x30581106: - return ("VIA 82C686 AC97 Audio"); - case 0x30681106: - return ("VIA 82C686 AC97 Modem"); - - /* AMD -- vendor 0x1022 */ - case 0x70061022: - return ("AMD-751 host to PCI bridge"); - - /* NEC -- vendor 0x1033 */ - case 0x00021033: - return ("NEC 0002 PCI to PC-98 local bus bridge"); - case 0x00161033: - return ("NEC 0016 PCI to PC-98 local bus bridge"); - - /* AcerLabs -- vendor 0x10b9 */ - /* Funny : The datasheet told me vendor id is "10b8",sub-vendor */ - /* id is '10b9" but the register always shows "10b9". -Foxfair */ - case 0x154110b9: - return ("AcerLabs M1541 (Aladdin-V) PCI host bridge"); - case 0x710110b9: - return ("AcerLabs M15x3 Power Management Unit"); - - /* OPTi -- vendor 0x1045 */ - case 0xc7011045: - return ("OPTi 82C700 host to PCI bridge"); - case 0xc8221045: - return ("OPTi 82C822 host to PCI Bridge"); - - /* Texas Instruments -- vendor 0x104c */ - case 0x8009104c: - return ("Texas Instruments TSB12LV22 OHCI IEEE 1394 Host Controller"); - case 0xac1c104c: - return ("Texas Instruments PCI1225 CardBus controller"); - case 0xac50104c: - return ("Texas Instruments PCI1410 CardBus controller"); - case 0xac51104c: - return ("Texas Instruments PCI1420 CardBus controller"); - case 0xac1b104c: - return ("Texas Instruments PCI1450 CardBus controller"); - case 0xac52104c: - return ("Texas Instruments PCI1451 CardBus controller"); - - /* NeoMagic -- vendor 0x10c8 */ - case 0x800510c8: - return ("NeoMagic MagicMedia 256AX Audio controller"); - case 0x800610c8: - return ("NeoMagic MagicMedia 256ZX Audio controller"); - - /* ESS Technology Inc -- vendor 0x125d */ - case 0x0100125d: - return ("ESS Technology Maestro 1 Audio controller"); - case 0x1818125d: - return ("ESS Technology Solo-1 Audio controller"); - case 0x1968125d: - return ("ESS Technology Maestro 2 Audio controller"); - case 0x1969125d: - return ("ESS Technology Solo-1 Audio controller"); - case 0x1978125d: - return ("ESS Technology Maestro 2E Audio controller"); - case 0x1998125d: - return ("ESS Technology Maestro 3 Audio controller"); - case 0x1999125d: - return ("ESS Technology Maestro 3 Modem"); - case 0x2898125d: - return ("ESS Technology ES2898 Modem"); - case 0x8888125d: - return ("ESS Technology Solo-1E Audio controller"); - - /* Aureal Inc.-- vendor 0x12eb */ - case 0x000112eb: - return ("Aureal Vortex AU8820 Audio controller"); - case 0x000212eb: - return ("Aureal Vortex AU8830 Audio controller"); - - /* Lucent -- Vendor 0x11c1 */ - case 0x044011c1: - case 0x044811c1: - return ("Lucent K56Flex DSVD LTModem (Win Modem, unsupported)"); - - /* CCUBE -- Vendor 0x123f */ - case 0x8888123f: - return ("Cinemaster C 3.0 DVD Decoder"); - - /* Toshiba -- vendor 0x1179 */ - case 0x07011179: - return ("Toshiba Fast Infra Red controller"); - - /* Compaq -- vendor 0x0e11 */ - case 0xa0f70e11: - return ("Compaq PCI Hotplug controller"); - - /* NEC -- vendor 0x1033 */ - - /* PCI to C-bus bridge */ - /* The following chipsets are PCI to PC98 C-bus bridge. - * The C-bus is the 16-bits bus on PC98 and it should be probed as - * PCI to ISA bridge. Because class of the C-bus is not defined, - * C-bus bridges are recognized as "other bridge." To make C-bus - * bridge be recognized as ISA bridge, this function returns NULL. - */ - case 0x00011033: - case 0x002c1033: - case 0x003b1033: - return NULL; - }; - - if (pci_get_class(dev) == PCIC_BRIDGE && - pci_get_subclass(dev) != PCIS_BRIDGE_PCI && - pci_get_subclass(dev) != PCIS_BRIDGE_ISA && - pci_get_subclass(dev) != PCIS_BRIDGE_EISA) - return pci_bridge_type(dev); - - return NULL; -} - -/*--------------------------------------------------------- -** -** Catchall driver for VGA devices -** -** By Garrett Wollman -** <wollman@halloran-eldar.lcs.mit.edu> -** -**--------------------------------------------------------- -*/ - -const char* pci_vga_match(device_t dev) -{ - u_int id = pci_get_devid(dev); - const char *vendor, *chip, *type; - - vendor = chip = type = 0; - switch (id & 0xffff) { - case 0x003d: - vendor = "Real 3D"; - switch (id >> 16) { - case 0x00d1: - chip = "i740"; break; - } - break; - case 0x10c8: - vendor = "NeoMagic"; - switch (id >> 16) { - case 0x0003: - chip = "MagicGraph 128ZV"; break; - case 0x0004: - chip = "MagicGraph 128XD"; break; - case 0x0005: - chip = "MagicMedia 256AV"; break; - case 0x0006: - chip = "MagicMedia 256ZX"; break; - } - break; - case 0x121a: - vendor = "3Dfx"; - type = "graphics accelerator"; - switch (id >> 16) { - case 0x0001: - chip = "Voodoo"; break; - case 0x0002: - chip = "Voodoo 2"; break; - case 0x0003: - chip = "Voodoo Banshee"; break; - case 0x0005: - chip = "Voodoo 3"; break; - } - break; - case 0x102b: - vendor = "Matrox"; - type = "graphics accelerator"; - switch (id >> 16) { - case 0x0518: - chip = "MGA 2085PX"; break; - case 0x0519: - chip = "MGA Millennium 2064W"; break; - case 0x051a: - chip = "MGA 1024SG/1064SG/1164SG"; break; - case 0x051b: - chip = "MGA Millennium II 2164W"; break; - case 0x051f: - chip = "MGA Millennium II 2164WA-B AG"; break; - case 0x0520: - chip = "MGA G200"; break; - case 0x0521: - chip = "MGA G200 AGP"; break; - case 0x0525: - chip = "MGA G400 AGP"; break; - case 0x0d10: - chip = "MGA Impression"; break; - case 0x1000: - chip = "MGA G100"; break; - case 0x1001: - chip = "MGA G100 AGP"; break; - - } - break; - case 0x1002: - vendor = "ATI"; - type = "graphics accelerator"; - switch (id >> 16) { - case 0x4158: - chip = "Mach32"; break; - case 0x4354: - chip = "Mach64-CT"; break; - case 0x4358: - chip = "Mach64-CX"; break; - case 0x4554: - chip = "Mach64-ET"; break; - case 0x4654: - case 0x5654: - chip = "Mach64-VT"; break; - case 0x4742: - chip = "Mach64-GB"; break; - case 0x4744: - chip = "Mach64-GD"; break; - case 0x4749: - chip = "Mach64-GI"; break; - case 0x474d: - chip = "Mach64-GM"; break; - case 0x474e: - chip = "Mach64-GN"; break; - case 0x474f: - chip = "Mach64-GO"; break; - case 0x4750: - chip = "Mach64-GP"; break; - case 0x4751: - chip = "Mach64-GQ"; break; - case 0x4752: - chip = "Mach64-GR"; break; - case 0x4753: - chip = "Mach64-GS"; break; - case 0x4754: - chip = "Mach64-GT"; break; - case 0x4755: - chip = "Mach64-GU"; break; - case 0x4756: - chip = "Mach64-GV"; break; - case 0x4757: - chip = "Mach64-GW"; break; - case 0x4758: - chip = "Mach64-GX"; break; - case 0x4c42: - chip = "Mach64-LB"; break; - case 0x4c46: - chip = "Rage128-LF Mobility"; break; - case 0x4c4d: - chip = "Mobility-1"; break; - case 0x475a: - chip = "Mach64-GZ"; break; - case 0x5245: - chip = "Rage128-RE"; break; - case 0x5246: - chip = "Rage128-RF"; break; - case 0x524b: - chip = "Rage128-RK"; break; - case 0x524c: - chip = "Rage128-RL"; break; - } - break; - case 0x1005: - vendor = "Avance Logic"; - switch (id >> 16) { - case 0x2301: - chip = "ALG2301"; break; - case 0x2302: - chip = "ALG2302"; break; - } - break; - case 0x100c: - vendor = "Tseng Labs"; - type = "graphics accelerator"; - switch (id >> 16) { - case 0x3202: - case 0x3205: - case 0x3206: - case 0x3207: - chip = "ET4000 W32P"; break; - case 0x3208: - chip = "ET6000/ET6100"; break; - case 0x4702: - chip = "ET6300"; break; - } - break; - case 0x100e: - vendor = "Weitek"; - type = "graphics accelerator"; - switch (id >> 16) { - case 0x9001: - chip = "P9000"; break; - case 0x9100: - chip = "P9100"; break; - } - break; - case 0x1013: - vendor = "Cirrus Logic"; - switch (id >> 16) { - case 0x0038: - chip = "GD7548"; break; - case 0x0040: - chip = "GD7555"; break; - case 0x004c: - chip = "GD7556"; break; - case 0x00a0: - chip = "GD5430"; break; - case 0x00a4: - case 0x00a8: - chip = "GD5434"; break; - case 0x00ac: - chip = "GD5436"; break; - case 0x00b8: - chip = "GD5446"; break; - case 0x00bc: - chip = "GD5480"; break; - case 0x00d0: - chip = "GD5462"; break; - case 0x00d4: - case 0x00d5: - chip = "GD5464"; break; - case 0x00d6: - chip = "GD5465"; break; - case 0x1200: - chip = "GD7542"; break; - case 0x1202: - chip = "GD7543"; break; - case 0x1204: - chip = "GD7541"; break; - } - break; - case 0x1023: - vendor = "Trident"; - break; /* let default deal with it */ - case 0x102c: - vendor = "Chips & Technologies"; - switch (id >> 16) { - case 0x00b8: - chip = "64310"; break; - case 0x00d8: - chip = "65545"; break; - case 0x00dc: - chip = "65548"; break; - case 0x00c0: - chip = "69000"; break; - case 0x00e0: - chip = "65550"; break; - case 0x00e4: - chip = "65554"; break; - case 0x00e5: - chip = "65555"; break; - case 0x00f4: - chip = "68554"; break; - } - break; - case 0x1033: - vendor = "NEC"; - switch (id >> 16) { - case 0x0009: - type = "PCI to PC-98 Core Graph bridge"; - break; - } - break; - case 0x1039: - vendor = "SiS"; - switch (id >> 16) { - case 0x0001: - chip = "86c201"; break; - case 0x0002: - chip = "86c202"; break; - case 0x0205: - chip = "86c205"; break; - case 0x0215: - chip = "86c215"; break; - case 0x0225: - chip = "86c225"; break; - case 0x0200: - chip = "5597/98"; break; - case 0x6326: - chip = "6326"; break; - case 0x6306: - chip = "530/620"; break; - } - break; - case 0x105d: - vendor = "Number Nine"; - type = "graphics accelerator"; - switch (id >> 16) { - case 0x2309: - chip = "Imagine 128"; break; - case 0x2339: - chip = "Imagine 128 II"; break; - } - break; - case 0x1142: - vendor = "Alliance"; - switch (id >> 16) { - case 0x3210: - chip = "PM6410"; break; - case 0x6422: - chip = "PM6422"; break; - case 0x6424: - chip = "PMAT24"; break; - } - break; - case 0x1163: - vendor = "Rendition Verite"; - switch (id >> 16) { - case 0x0001: - chip = "V1000"; break; - case 0x2000: - chip = "V2000"; break; - } - break; - case 0x1236: - vendor = "Sigma Designs"; - if ((id >> 16) == 0x6401) - chip = "REALmagic64/GX"; - break; - case 0x5333: - vendor = "S3"; - type = "graphics accelerator"; - switch (id >> 16) { - case 0x8811: - chip = "Trio"; break; - case 0x8812: - chip = "Aurora 64"; break; - case 0x8814: - chip = "Trio 64UV+"; break; - case 0x8901: - chip = "Trio 64V2/DX/GX"; break; - case 0x8902: - chip = "Plato"; break; - case 0x8904: - chip = "Trio3D"; break; - case 0x8880: - chip = "868"; break; - case 0x88b0: - chip = "928"; break; - case 0x88c0: - case 0x88c1: - chip = "864"; break; - case 0x88d0: - case 0x88d1: - chip = "964"; break; - case 0x88f0: - chip = "968"; break; - case 0x5631: - chip = "ViRGE"; break; - case 0x883d: - chip = "ViRGE VX"; break; - case 0x8a01: - chip = "ViRGE DX/GX"; break; - case 0x8a10: - chip = "ViRGE GX2"; break; - case 0x8a13: - chip = "Trio3D/2X"; break; - case 0x8a20: - case 0x8a21: - chip = "Savage3D"; break; - case 0x8a22: - chip = "Savage 4"; break; - case 0x8c01: - chip = "ViRGE MX"; break; - case 0x8c03: - chip = "ViRGE MX+"; break; - } - break; - case 0xedd8: - vendor = "ARK Logic"; - switch (id >> 16) { - case 0xa091: - chip = "1000PV"; break; - case 0xa099: - chip = "2000PV"; break; - case 0xa0a1: - chip = "2000MT"; break; - case 0xa0a9: - chip = "2000MI"; break; - } - break; - case 0x3d3d: - vendor = "3D Labs"; - type = "graphics accelerator"; - switch (id >> 16) { - case 0x0001: - chip = "300SX"; break; - case 0x0002: - chip = "500TX"; break; - case 0x0003: - chip = "Delta"; break; - case 0x0004: - chip = "PerMedia"; break; - } - break; - case 0x10de: - vendor = "NVidia"; - type = "graphics accelerator"; - switch (id >> 16) { - case 0x0008: - chip = "NV1"; break; - case 0x0020: - chip = "Riva TNT"; break; - case 0x0028: - chip = "Riva TNT2"; break; - case 0x0029: - chip = "Riva Ultra TNT2"; break; - case 0x002c: - chip = "Riva Vanta TNT2"; break; - case 0x002d: - chip = "Riva Ultra Vanta TNT2"; break; - case 0x00a0: - chip = "Riva Integrated TNT2"; break; - case 0x0100: - chip = "GeForce 256"; break; - case 0x0101: - chip = "GeForce DDR"; break; - case 0x0103: - chip = "Quadro"; break; - case 0x0150: - case 0x0151: - case 0x0152: - chip = "GeForce2 GTS"; break; - case 0x0153: - chip = "Quadro2"; break; - } - break; - case 0x12d2: - vendor = "NVidia/SGS-Thomson"; - type = "graphics accelerator"; - switch (id >> 16) { - case 0x0018: - chip = "Riva128"; break; - } - break; - case 0x104a: - vendor = "SGS-Thomson"; - switch (id >> 16) { - case 0x0008: - chip = "STG2000"; break; - } - break; - case 0x8086: - vendor = "Intel"; - switch (id >> 16) { - case 0x7121: - chip = "82810 (i810 GMCH)"; break; - case 0x7123: - chip = "82810-DC100 (i810-DC100 GMCH)"; break; - case 0x7125: - chip = "82810E (i810E GMCH)"; break; - case 0x7800: - chip = "i740 AGP"; break; - } - break; - case 0x10ea: - vendor = "Intergraphics"; - switch (id >> 16) { - case 0x1680: - chip = "IGA-1680"; break; - case 0x1682: - chip = "IGA-1682"; break; - } - break; - } - - if (vendor && chip) { - char *buf; - int len; - - if (type == 0) - type = "SVGA controller"; - - len = strlen(vendor) + strlen(chip) + strlen(type) + 4; - MALLOC(buf, char *, len, M_TEMP, M_NOWAIT); - if (buf) - sprintf(buf, "%s %s %s", vendor, chip, type); - return buf; - } - - switch (pci_get_class(dev)) { - - case PCIC_OLD: - if (pci_get_subclass(dev) != PCIS_OLD_VGA) - return 0; - if (type == 0) - type = "VGA-compatible display device"; - break; - - case PCIC_DISPLAY: - if (type == 0) { - if (pci_get_subclass(dev) == PCIS_DISPLAY_VGA) - type = "VGA-compatible display device"; - else { - /* - * If it isn't a vga display device, - * don't pretend we found one. - */ - return 0; - } - } - break; - - default: - return 0; - }; - /* - * If we got here, we know for sure it's some sort of display - * device, but we weren't able to identify it specifically. - * At a minimum we can return the type, but we'd like to - * identify the vendor and chip ID if at all possible. - * (Some of the checks above intentionally don't bother for - * vendors where we know the chip ID is the same as the - * model number.) - */ - if (vendor) { - char *buf; - int len; - - len = strlen(vendor) + strlen(type) + 2 + 6 + 4 + 1; - MALLOC(buf, char *, len, M_TEMP, M_NOWAIT); - if (buf) - sprintf(buf, "%s model %04x %s", vendor, id >> 16, type); - return buf; - } - return type; -} - -/*--------------------------------------------------------- -** -** Devices to ignore -** -**--------------------------------------------------------- -*/ - -static const char * -ign_match(device_t dev) -{ - switch (pci_get_devid(dev)) { - - case 0x10001042ul: /* wd */ - return ("SMC FDC 37c665"); - }; - - return NULL; -} - -static int -ign_probe(device_t dev) -{ - const char *s; - - s = ign_match(dev); - if (s) { - device_set_desc(dev, s); - device_quiet(dev); - return -10000; - } - return ENXIO; -} - -static int -ign_attach(device_t dev) -{ - return 0; -} - -static device_method_t ign_methods[] = { - /* Device interface */ - DEVMETHOD(device_probe, ign_probe), - DEVMETHOD(device_attach, ign_attach), - - { 0, 0 } -}; - -static driver_t ign_driver = { - "ign", - ign_methods, - 1, -}; - -static devclass_t ign_devclass; - -DRIVER_MODULE(ign, pci, ign_driver, ign_devclass, 0, 0); diff --git a/sys/pci/pcivar.h b/sys/pci/pcivar.h deleted file mode 100644 index 285e4ca..0000000 --- a/sys/pci/pcivar.h +++ /dev/null @@ -1,332 +0,0 @@ -/* - * Copyright (c) 1997, Stefan Esser <se@freebsd.org> - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice unmodified, this list of conditions, and the following - * disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * $FreeBSD$ - * - */ - -#ifndef _PCIVAR_H_ -#define _PCIVAR_H_ - -#include <sys/queue.h> - -/* some PCI bus constants */ - -#define PCI_BUSMAX 255 /* highest supported bus number */ -#define PCI_SLOTMAX 31 /* highest supported slot number */ -#define PCI_FUNCMAX 7 /* highest supported function number */ -#define PCI_REGMAX 255 /* highest supported config register addr. */ - -#define PCI_MAXMAPS_0 6 /* max. no. of memory/port maps */ -#define PCI_MAXMAPS_1 2 /* max. no. of maps for PCI to PCI bridge */ -#define PCI_MAXMAPS_2 1 /* max. no. of maps for CardBus bridge */ - -/* pci_addr_t covers this system's PCI bus address space: 32 or 64 bit */ - -#ifdef PCI_A64 -typedef u_int64_t pci_addr_t; /* u_int64_t for system with 64bit addresses */ -#else -typedef u_int32_t pci_addr_t; /* u_int64_t for system with 64bit addresses */ -#endif - -/* config header information common to all header types */ - -typedef struct pcicfg { - struct device *dev; /* device which owns this */ - void *hdrspec; /* pointer to header type specific data */ - - u_int16_t subvendor; /* card vendor ID */ - u_int16_t subdevice; /* card device ID, assigned by card vendor */ - u_int16_t vendor; /* chip vendor ID */ - u_int16_t device; /* chip device ID, assigned by chip vendor */ - - u_int16_t cmdreg; /* disable/enable chip and PCI options */ - u_int16_t statreg; /* supported PCI features and error state */ - - u_int8_t baseclass; /* chip PCI class */ - u_int8_t subclass; /* chip PCI subclass */ - u_int8_t progif; /* chip PCI programming interface */ - u_int8_t revid; /* chip revision ID */ - - u_int8_t hdrtype; /* chip config header type */ - u_int8_t cachelnsz; /* cache line size in 4byte units */ - u_int8_t intpin; /* PCI interrupt pin */ - u_int8_t intline; /* interrupt line (IRQ for PC arch) */ - - u_int8_t mingnt; /* min. useful bus grant time in 250ns units */ - u_int8_t maxlat; /* max. tolerated bus grant latency in 250ns */ - u_int8_t lattimer; /* latency timer in units of 30ns bus cycles */ - - u_int8_t mfdev; /* multi-function device (from hdrtype reg) */ - u_int8_t nummaps; /* actual number of PCI maps used */ - - u_int8_t bus; /* config space bus address */ - u_int8_t slot; /* config space slot address */ - u_int8_t func; /* config space function number */ - - u_int8_t secondarybus; /* bus on secondary side of bridge, if any */ - u_int8_t subordinatebus; /* topmost bus number behind bridge, if any */ -} pcicfgregs; - -/* additional type 1 device config header information (PCI to PCI bridge) */ - -#ifdef PCI_A64 -#define PCI_PPBMEMBASE(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) & ~0xfffff) -#define PCI_PPBMEMLIMIT(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) | 0xfffff) -#else -#define PCI_PPBMEMBASE(h,l) (((l)<<16) & ~0xfffff) -#define PCI_PPBMEMLIMIT(h,l) (((l)<<16) | 0xfffff) -#endif /* PCI_A64 */ - -#define PCI_PPBIOBASE(h,l) ((((h)<<16) + ((l)<<8)) & ~0xfff) -#define PCI_PPBIOLIMIT(h,l) ((((h)<<16) + ((l)<<8)) | 0xfff) - -typedef struct { - pci_addr_t pmembase; /* base address of prefetchable memory */ - pci_addr_t pmemlimit; /* topmost address of prefetchable memory */ - u_int32_t membase; /* base address of memory window */ - u_int32_t memlimit; /* topmost address of memory window */ - u_int32_t iobase; /* base address of port window */ - u_int32_t iolimit; /* topmost address of port window */ - u_int16_t secstat; /* secondary bus status register */ - u_int16_t bridgectl; /* bridge control register */ - u_int8_t seclat; /* CardBus latency timer */ -} pcih1cfgregs; - -/* additional type 2 device config header information (CardBus bridge) */ - -typedef struct { - u_int32_t membase0; /* base address of memory window */ - u_int32_t memlimit0; /* topmost address of memory window */ - u_int32_t membase1; /* base address of memory window */ - u_int32_t memlimit1; /* topmost address of memory window */ - u_int32_t iobase0; /* base address of port window */ - u_int32_t iolimit0; /* topmost address of port window */ - u_int32_t iobase1; /* base address of port window */ - u_int32_t iolimit1; /* topmost address of port window */ - u_int32_t pccardif; /* PC Card 16bit IF legacy more base addr. */ - u_int16_t secstat; /* secondary bus status register */ - u_int16_t bridgectl; /* bridge control register */ - u_int8_t seclat; /* CardBus latency timer */ -} pcih2cfgregs; - -extern u_int32_t pci_numdevs; - -/* Only if the prerequisites are present */ -#if defined(_SYS_BUS_H_) && defined(_SYS_PCIIO_H_) -struct pci_devinfo { - STAILQ_ENTRY(pci_devinfo) pci_links; - struct resource_list resources; - pcicfgregs cfg; - struct pci_conf conf; -}; -#endif - -/* externally visible functions */ - -const char *pci_ata_match(struct device *dev); -const char *pci_usb_match(struct device *dev); -const char *pci_vga_match(struct device *dev); -const char *pci_chip_match(struct device *dev); - -/* low level PCI config register functions provided by pcibus.c */ - -int pci_cfgread (pcicfgregs *cfg, int reg, int bytes); -void pci_cfgwrite (pcicfgregs *cfg, int reg, int data, int bytes); - -#ifdef __alpha__ -vm_offset_t pci_cvt_to_dense (vm_offset_t); -vm_offset_t pci_cvt_to_bwx (vm_offset_t); -#endif /* __alpha__ */ - -/* low level devlist operations for the 2.2 compatibility code in pci.c */ -pcicfgregs * pci_devlist_get_parent(pcicfgregs *cfg); - -#ifdef _SYS_BUS_H_ - -#include "pci_if.h" - -/* - * Define pci-specific resource flags for accessing memory via dense - * or bwx memory spaces. These flags are ignored on i386. - */ -#define PCI_RF_DENSE 0x10000 -#define PCI_RF_BWX 0x20000 - -enum pci_device_ivars { - PCI_IVAR_SUBVENDOR, - PCI_IVAR_SUBDEVICE, - PCI_IVAR_VENDOR, - PCI_IVAR_DEVICE, - PCI_IVAR_DEVID, - PCI_IVAR_CLASS, - PCI_IVAR_SUBCLASS, - PCI_IVAR_PROGIF, - PCI_IVAR_REVID, - PCI_IVAR_INTPIN, - PCI_IVAR_IRQ, - PCI_IVAR_BUS, - PCI_IVAR_SLOT, - PCI_IVAR_FUNCTION, - PCI_IVAR_SECONDARYBUS, - PCI_IVAR_SUBORDINATEBUS, -}; - -/* - * Simplified accessors for pci devices - */ -#define PCI_ACCESSOR(A, B, T) \ - \ -static __inline T pci_get_ ## A(device_t dev) \ -{ \ - uintptr_t v; \ - BUS_READ_IVAR(device_get_parent(dev), dev, PCI_IVAR_ ## B, &v); \ - return (T) v; \ -} \ - \ -static __inline void pci_set_ ## A(device_t dev, T t) \ -{ \ - uintptr_t v = (uintptr_t) t; \ - BUS_WRITE_IVAR(device_get_parent(dev), dev, PCI_IVAR_ ## B, v); \ -} - -PCI_ACCESSOR(subvendor, SUBVENDOR, u_int16_t) -PCI_ACCESSOR(subdevice, SUBDEVICE, u_int16_t) -PCI_ACCESSOR(vendor, VENDOR, u_int16_t) -PCI_ACCESSOR(device, DEVICE, u_int16_t) -PCI_ACCESSOR(devid, DEVID, u_int32_t) -PCI_ACCESSOR(class, CLASS, u_int8_t) -PCI_ACCESSOR(subclass, SUBCLASS, u_int8_t) -PCI_ACCESSOR(progif, PROGIF, u_int8_t) -PCI_ACCESSOR(revid, REVID, u_int8_t) -PCI_ACCESSOR(intpin, INTPIN, u_int8_t) -PCI_ACCESSOR(irq, IRQ, u_int8_t) -PCI_ACCESSOR(bus, BUS, u_int8_t) -PCI_ACCESSOR(slot, SLOT, u_int8_t) -PCI_ACCESSOR(function, FUNCTION, u_int8_t) -PCI_ACCESSOR(secondarybus, SECONDARYBUS, u_int8_t) -PCI_ACCESSOR(subordinatebus, SUBORDINATEBUS, u_int8_t) - -#undef PCI_ACCESSOR - -static __inline u_int32_t -pci_read_config(device_t dev, int reg, int width) -{ - return PCI_READ_CONFIG(device_get_parent(dev), dev, reg, width); -} - -static __inline void -pci_write_config(device_t dev, int reg, u_int32_t val, int width) -{ - PCI_WRITE_CONFIG(device_get_parent(dev), dev, reg, val, width); -} - -/* - * Ivars for pci bridges. - */ - -/*typedef enum pci_device_ivars pcib_device_ivars;*/ -enum pcib_device_ivars { - PCIB_IVAR_BUS -}; - -#define PCIB_ACCESSOR(A, B, T) \ - \ -static __inline T pcib_get_ ## A(device_t dev) \ -{ \ - uintptr_t v; \ - BUS_READ_IVAR(device_get_parent(dev), dev, PCIB_IVAR_ ## B, &v); \ - return (T) v; \ -} \ - \ -static __inline void pcib_set_ ## A(device_t dev, T t) \ -{ \ - uintptr_t v = (uintptr_t) t; \ - BUS_WRITE_IVAR(device_get_parent(dev), dev, PCIB_IVAR_ ## B, v); \ -} - -PCIB_ACCESSOR(bus, BUS, u_int32_t) - -#undef PCIB_ACCESSOR - -#endif - -/* for compatibility to FreeBSD-2.2 and 3.x versions of PCI code */ - -#if defined(_KERNEL) && !defined(KLD_MODULE) -#include "opt_compat_oldpci.h" -#endif - -#ifdef COMPAT_OLDPCI - -/* all this is going some day */ - -typedef pcicfgregs *pcici_t; -typedef unsigned pcidi_t; -typedef void pci_inthand_t(void *arg); - -#define pci_max_burst_len (3) - -/* just copied from old PCI code for now ... */ - -struct pci_device { - char* pd_name; - const char* (*pd_probe ) (pcici_t tag, pcidi_t type); - void (*pd_attach) (pcici_t tag, int unit); - u_long *pd_count; - int (*pd_shutdown) (int, int); -}; - -#ifdef __i386__ -typedef u_short pci_port_t; -#else -typedef u_int pci_port_t; -#endif - -u_long pci_conf_read (pcici_t tag, u_long reg); -void pci_conf_write (pcici_t tag, u_long reg, u_long data); -int pci_map_port (pcici_t tag, u_long reg, pci_port_t* pa); -int pci_map_mem (pcici_t tag, u_long reg, vm_offset_t* va, vm_offset_t* pa); -int pci_map_int (pcici_t tag, pci_inthand_t *handler, void *arg, - intrmask_t *maskptr); -int pci_map_int_right(pcici_t cfg, pci_inthand_t *handler, void *arg, - intrmask_t *maskptr, u_int flags); -int pci_unmap_int (pcici_t tag); - -pcici_t pci_get_parent_from_tag(pcici_t tag); -int pci_get_bus_from_tag(pcici_t tag); - -struct module; -int compat_pci_handler (struct module *, int, void *); -#define COMPAT_PCI_DRIVER(name, pcidata) \ -static moduledata_t name##_mod = { \ - #name, \ - compat_pci_handler, \ - &pcidata \ -}; \ -DECLARE_MODULE(name, name##_mod, SI_SUB_DRIVERS, SI_ORDER_ANY) -#endif /* COMPAT_OLDPCI */ - -#endif /* _PCIVAR_H_ */ |
