diff options
Diffstat (limited to 'sys/pci')
| -rw-r--r-- | sys/pci/if_xl.c | 16 | ||||
| -rw-r--r-- | sys/pci/if_xlreg.h | 3 |
2 files changed, 16 insertions, 3 deletions
diff --git a/sys/pci/if_xl.c b/sys/pci/if_xl.c index ff990ec..8cb2ef5 100644 --- a/sys/pci/if_xl.c +++ b/sys/pci/if_xl.c @@ -610,7 +610,8 @@ static void xl_miibus_statchg(dev) /* Set ASIC's duplex mode to match the PHY. */ XL_SEL_WIN(3); if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) - CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX); + CSR_WRITE_1(sc, XL_W3_MAC_CTRL, + (CSR_READ_1(sc, XL_W3_MAC_CTRL) | XL_MACCTRL_DUPLEX)); else CSR_WRITE_1(sc, XL_W3_MAC_CTRL, (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX)); @@ -993,7 +994,8 @@ static void xl_setmode(sc, media) IFM_SUBTYPE(media) == IFM_100_FX) { printf("full duplex\n"); XL_SEL_WIN(3); - CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX); + CSR_WRITE_1(sc, XL_W3_MAC_CTRL, + (CSR_READ_1(sc, XL_W3_MAC_CTRL) | XL_MACCTRL_DUPLEX)); } else { printf("half duplex\n"); XL_SEL_WIN(3); @@ -2651,6 +2653,16 @@ static void xl_init(xsc) else CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); + /* + * Allow reception of large packets to make + * people who use 802.1q VLANs happy. + */ + CSR_WRITE_1(sc, XL_W3_MAC_CTRL, + (CSR_READ_1(sc, XL_W3_MAC_CTRL) | XL_MACCTRL_LARGE_PACK)); + + /* increase packet size to allow reception of 802.1q or ISL packets */ + if (sc->xl_type == XL_TYPE_905B) + CSR_WRITE_2(sc, XL_W3_MAXPKTSIZE, XL_PACKET_SIZE); /* Clear out the stats counters. */ CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE); sc->xl_stats_no_timeout = 1; diff --git a/sys/pci/if_xlreg.h b/sys/pci/if_xlreg.h index cd7554d..bd4ca77 100644 --- a/sys/pci/if_xlreg.h +++ b/sys/pci/if_xlreg.h @@ -81,7 +81,7 @@ #define XL_CAPS_100MBPS 0x1000 #define XL_CAPS_PWRMGMT 0x2000 -#define XL_PACKET_SIZE 1536 +#define XL_PACKET_SIZE 1540 /* * Register layouts. @@ -256,6 +256,7 @@ * Window 3 (fifo management) */ #define XL_W3_INTERNAL_CFG 0x00 +#define XL_W3_MAXPKTSIZE 0x04 /* 3c905B only */ #define XL_W3_RESET_OPT 0x08 #define XL_W3_FREE_TX 0x0C #define XL_W3_FREE_RX 0x0A |
