diff options
Diffstat (limited to 'sys/pci/if_rl.c')
| -rw-r--r-- | sys/pci/if_rl.c | 1324 |
1 files changed, 105 insertions, 1219 deletions
diff --git a/sys/pci/if_rl.c b/sys/pci/if_rl.c index df86784..9b9aa46 100644 --- a/sys/pci/if_rl.c +++ b/sys/pci/if_rl.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 1997, 1998-2003 + * Copyright (c) 1997, 1998 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -31,15 +31,15 @@ */ /* - * RealTek 8129/8139/8139C+/8169 PCI NIC driver + * RealTek 8129/8139 PCI NIC driver * - * Supports several extremely cheap PCI 10/100 and 10/100/1000 adapters - * based on RealTek chipsets. Datasheets can be obtained from + * Supports several extremely cheap PCI 10/100 adapters based on + * the RealTek chipset. Datasheets can be obtained from * www.realtek.com.tw. * - * Written by Bill Paul <wpaul@windriver.com> - * Senior Networking Software Engineer - * Wind River Systems + * Written by Bill Paul <wpaul@ctr.columbia.edu> + * Electrical Engineering Department + * Columbia University, New York City */ /* @@ -79,58 +79,6 @@ * chip. The 8129 has a serial MDIO interface for accessing the MII where * the 8139 lets you directly access the on-board PHY registers. We need * to select which interface to use depending on the chip type. - * - * Fast forward a few years. RealTek now has a new chip called the - * 8139C+ which at long last implements descriptor-based DMA. Not - * only that, it supports RX and TX TCP/IP checksum offload, VLAN - * tagging and insertion, TCP large send and 64-bit addressing. - * Better still, it allows arbitrary byte alignments for RX and - * TX buffers, meaning no copying is necessary on any architecture. - * There are a few limitations however: the RX and TX descriptor - * rings must be aligned on 256 byte boundaries, they must be in - * contiguous RAM, and each ring can have a maximum of 64 descriptors. - * There are two TX descriptor queues: one normal priority and one - * high. Descriptor ring addresses and DMA buffer addresses are - * 64 bits wide. The 8139C+ is also backwards compatible with the - * 8139, so the chip will still function with older drivers: C+ - * mode has to be enabled by setting the appropriate bits in the C+ - * command register. The PHY access mechanism appears to be unchanged. - * - * The 8169 is a 10/100/1000 ethernet MAC. It has almost the same - * programming API as the C+ mode of the 8139C+, with a couple of - * minor changes and additions: TX start register and timer interrupt - * register are located at different offsets, and there are additional - * registers for GMII PHY status and control, as well as TBI-mode - * status and control. There is also a maximum RX packet size - * register to allow the chip to receive jumbo frames. The 8169 - * can only be programmed in C+ mode: the old 8139 programming - * method isn't supported with this chip. Also, RealTek has a LOM - * (LAN On Motherboard) gigabit MAC chip called the RTL8110S which - * I believe to be register compatible with the 8169. Unlike the - * 8139C+, the 8169 can have up to 1024 descriptors per DMA ring. - * The reference 8169 board design uses a Marvell 88E1000 'Alaska' - * copper PHY. - * - * The 8169S and 8110S are newer versions of the 8169. Available - * in both 32-bit and 64-bit forms, these devices have built-in - * copper 10/100/1000 PHYs. The 8110S is a lan-on-motherboard chip - * that is pin-for-pin compatible with the 8100. Unfortunately, - * RealTek has not released programming manuals for the 8169S and - * 8110S yet. The datasheet for the original 8169 provides most - * of the information, but you must refer to RealTek's 8169 Linux - * driver to fill in the gaps. Mostly, it appears that the built-in - * PHY requires some special initialization. The original 8169 - * datasheet and the 8139C+ datasheet can be obtained from - * http://www.freebsd.org/~wpaul/RealTek. - * - * This driver now supports both the old 8139 and new 8139C+ - * programming models. We detect the 8139C+ by looking for the - * corresponding hardware rev bits, and we detect the 8169 by its - * PCI ID. Two new NIC type codes, RL_8139CPLUS and RL_8169 have - * been added to distinguish the chips at runtime. Separate RX and - * TX handling routines have been added to handle C+ mode, which - * are selected via function pointers that are initialized during - * the driver attach phase. */ #include <sys/cdefs.h> @@ -150,7 +98,6 @@ __FBSDID("$FreeBSD$"); #include <net/ethernet.h> #include <net/if_dl.h> #include <net/if_media.h> -#include <net/if_vlan_var.h> #include <net/bpf.h> @@ -164,8 +111,8 @@ __FBSDID("$FreeBSD$"); #include <dev/mii/mii.h> #include <dev/mii/miivar.h> -#include <dev/pci/pcireg.h> -#include <dev/pci/pcivar.h> +#include <pci/pcireg.h> +#include <pci/pcivar.h> MODULE_DEPEND(rl, pci, 1, 1, 1); MODULE_DEPEND(rl, ether, 1, 1, 1); @@ -186,8 +133,6 @@ MODULE_DEPEND(rl, miibus, 1, 1, 1); #include <pci/if_rlreg.h> -#define RL_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) - /* * Various supported device vendors/types and their names. */ @@ -196,8 +141,6 @@ static struct rl_type rl_devs[] = { "RealTek 8129 10/100BaseTX" }, { RT_VENDORID, RT_DEVICEID_8139, RL_8139, "RealTek 8139 10/100BaseTX" }, - { RT_VENDORID, RT_DEVICEID_8169, RL_8169, - "RealTek 8169 10/100/1000BaseTX" }, { RT_VENDORID, RT_DEVICEID_8138, RL_8139, "RealTek 8139 10/100BaseTX CardBus" }, { RT_VENDORID, RT_DEVICEID_8100, RL_8139, @@ -218,7 +161,6 @@ static struct rl_type rl_devs[] = { "Corega FEther CB-TXD" }, { COREGA_VENDORID, COREGA_DEVICEID_FETHERIICBTXD, RL_8139, "Corega FEtherII CB-TXD" }, - /* XXX what type of realtek is PEPPERCON_DEVICEID_ROLF ? */ { PEPPERCON_VENDORID, PEPPERCON_DEVICEID_ROLF, RL_8139, "Peppercon AG ROL-F" }, { PLANEX_VENDORID, PLANEX_DEVICEID_FNW3800TX, RL_8139, @@ -229,22 +171,6 @@ static struct rl_type rl_devs[] = { "LevelOne FPC-0106TX" }, { EDIMAX_VENDORID, EDIMAX_DEVICEID_EP4103DL, RL_8139, "Edimax EP-4103DL CardBus" }, - { 0, 0, 0, NULL } -}; - -static struct rl_hwrev rl_hwrevs[] = { - { RL_HWREV_8139, RL_8139, "" }, - { RL_HWREV_8139A, RL_8139, "A" }, - { RL_HWREV_8139AG, RL_8139, "A-G" }, - { RL_HWREV_8139B, RL_8139, "B" }, - { RL_HWREV_8130, RL_8139, "8130" }, - { RL_HWREV_8139C, RL_8139, "C" }, - { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C" }, - { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+"}, - { RL_HWREV_8169, RL_8169, "8169"}, - { RL_HWREV_8110, RL_8169, "8169S/8110S"}, - { RL_HWREV_8100, RL_8139, "8100"}, - { RL_HWREV_8101, RL_8139, "8101"}, { 0, 0, NULL } }; @@ -252,26 +178,13 @@ static int rl_probe (device_t); static int rl_attach (device_t); static int rl_detach (device_t); -static int rl_encap (struct rl_softc *, struct mbuf *); -static int rl_encapcplus (struct rl_softc *, struct mbuf *, int *); - -static void rl_dma_map_addr (void *, bus_dma_segment_t *, int, int); -static void rl_dma_map_desc (void *, bus_dma_segment_t *, int, - bus_size_t, int); -static int rl_allocmem (device_t, struct rl_softc *); -static int rl_allocmemcplus (device_t, struct rl_softc *); -static int rl_newbuf (struct rl_softc *, int, struct mbuf *); -static int rl_rx_list_init (struct rl_softc *); -static int rl_tx_list_init (struct rl_softc *); +static int rl_encap (struct rl_softc *, struct mbuf * ); + static void rl_rxeof (struct rl_softc *); -static void rl_rxeofcplus (struct rl_softc *); static void rl_txeof (struct rl_softc *); -static void rl_txeofcplus (struct rl_softc *); static void rl_intr (void *); -static void rl_intrcplus (void *); static void rl_tick (void *); static void rl_start (struct ifnet *); -static void rl_startcplus (struct ifnet *); static int rl_ioctl (struct ifnet *, u_long, caddr_t); static void rl_init (void *); static void rl_stop (struct rl_softc *); @@ -289,8 +202,6 @@ static void rl_mii_sync (struct rl_softc *); static void rl_mii_send (struct rl_softc *, u_int32_t, int); static int rl_mii_readreg (struct rl_softc *, struct rl_mii_frame *); static int rl_mii_writereg (struct rl_softc *, struct rl_mii_frame *); -static int rl_gmii_readreg (device_t, int, int); -static int rl_gmii_writereg (device_t, int, int, int); static int rl_miibus_readreg (device_t, int, int); static int rl_miibus_writereg (device_t, int, int, int); @@ -686,71 +597,6 @@ rl_mii_writereg(sc, frame) } static int -rl_gmii_readreg(dev, phy, reg) - device_t dev; - int phy, reg; -{ - struct rl_softc *sc; - u_int32_t rval; - int i; - - if (phy != 1) - return(0); - - sc = device_get_softc(dev); - - CSR_WRITE_4(sc, RL_PHYAR, reg << 16); - DELAY(1000); - - for (i = 0; i < RL_TIMEOUT; i++) { - rval = CSR_READ_4(sc, RL_PHYAR); - if (rval & RL_PHYAR_BUSY) - break; - DELAY(100); - } - - if (i == RL_TIMEOUT) { - printf ("rl%d: PHY read failed\n", sc->rl_unit); - return (0); - } - - return (rval & RL_PHYAR_PHYDATA); -} - -static int -rl_gmii_writereg(dev, phy, reg, data) - device_t dev; - int phy, reg, data; -{ - struct rl_softc *sc; - u_int32_t rval; - int i; - - if (phy > 0) - return(0); - - sc = device_get_softc(dev); - - CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) | - (data | RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY); - DELAY(1000); - - for (i = 0; i < RL_TIMEOUT; i++) { - rval = CSR_READ_4(sc, RL_PHYAR); - if (!(rval & RL_PHYAR_BUSY)) - break; - DELAY(100); - } - - if (i == RL_TIMEOUT) { - printf ("rl%d: PHY write failed\n", sc->rl_unit); - return (0); - } - - return (0); -} - -static int rl_miibus_readreg(dev, phy, reg) device_t dev; int phy, reg; @@ -763,13 +609,7 @@ rl_miibus_readreg(dev, phy, reg) sc = device_get_softc(dev); RL_LOCK(sc); - if (sc->rl_type == RL_8169) { - rval = rl_gmii_readreg(dev, phy, reg); - RL_UNLOCK(sc); - return (rval); - } - - if (sc->rl_type == RL_8139 || sc->rl_type == RL_8139CPLUS) { + if (sc->rl_type == RL_8139) { /* Pretend the internal PHY is only at address 0 */ if (phy) { RL_UNLOCK(sc); @@ -833,18 +673,11 @@ rl_miibus_writereg(dev, phy, reg, data) struct rl_softc *sc; struct rl_mii_frame frame; u_int16_t rl8139_reg = 0; - int rval = 0; sc = device_get_softc(dev); RL_LOCK(sc); - if (sc->rl_type == RL_8169) { - rval = rl_gmii_writereg(dev, phy, reg, data); - RL_UNLOCK(sc); - return (rval); - } - - if (sc->rl_type == RL_8139 || sc->rl_type == RL_8139CPLUS) { + if (sc->rl_type == RL_8139) { /* Pretend the internal PHY is only at address 0 */ if (phy) { RL_UNLOCK(sc); @@ -999,8 +832,6 @@ rl_reset(sc) if (i == RL_TIMEOUT) printf("rl%d: reset never completed!\n", sc->rl_unit); - CSR_WRITE_1(sc, 0x82, 1); - return; } @@ -1013,11 +844,9 @@ rl_probe(dev) device_t dev; { struct rl_type *t; - struct rl_softc *sc; - struct rl_hwrev *hw_rev; + struct rl_softc *sc; int rid; u_int32_t hwrev; - char desc[64]; t = rl_devs; sc = device_get_softc(dev); @@ -1043,31 +872,21 @@ rl_probe(dev) mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, MTX_DEF); - RL_LOCK(sc); - if (t->rl_basetype == RL_8139) { - hwrev = CSR_READ_4(sc, RL_TXCFG) & - RL_TXCFG_HWREV; - hw_rev = rl_hwrevs; - while (hw_rev->rl_desc != NULL) { - if (hw_rev->rl_rev == hwrev) { - sprintf(desc, "%s, rev. %s", - t->rl_name, - hw_rev->rl_desc); - sc->rl_type = hw_rev->rl_type; - break; - } - hw_rev++; - } - if (hw_rev->rl_desc == NULL) - sprintf(desc, "%s, rev. %s", - t->rl_name, "unknown"); - } else - sprintf(desc, "%s", t->rl_name); - bus_release_resource(dev, RL_RES, - RL_RID, sc->rl_res); + RL_LOCK(sc); + hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV; + bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); RL_UNLOCK(sc); mtx_destroy(&sc->rl_mtx); - device_set_desc_copy(dev, desc); + + /* Don't attach to 8139C+ or 8169/8110 chips. */ + if (hwrev == RL_HWREV_8139CPLUS || + hwrev == RL_HWREV_8169 || + hwrev == RL_HWREV_8110) { + t++; + continue; + } + + device_set_desc(dev, t->rl_name); return(0); } t++; @@ -1077,255 +896,6 @@ rl_probe(dev) } /* - * This routine takes the segment list provided as the result of - * a bus_dma_map_load() operation and assigns the addresses/lengths - * to RealTek DMA descriptors. This can be called either by the RX - * code or the TX code. In the RX case, we'll probably wind up mapping - * at most one segment. For the TX case, there could be any number of - * segments since TX packets may span multiple mbufs. In either case, - * if the number of segments is larger than the rl_maxsegs limit - * specified by the caller, we abort the mapping operation. Sadly, - * whoever designed the buffer mapping API did not provide a way to - * return an error from here, so we have to fake it a bit. - */ - -static void -rl_dma_map_desc(arg, segs, nseg, mapsize, error) - void *arg; - bus_dma_segment_t *segs; - int nseg; - bus_size_t mapsize; - int error; -{ - struct rl_dmaload_arg *ctx; - struct rl_desc *d = NULL; - int i = 0, idx; - - if (error) - return; - - ctx = arg; - - /* Signal error to caller if there's too many segments */ - if (nseg > ctx->rl_maxsegs) { - ctx->rl_maxsegs = 0; - return; - } - - /* - * Map the segment array into descriptors. Note that we set the - * start-of-frame and end-of-frame markers for either TX or RX, but - * they really only have meaning in the TX case. (In the RX case, - * it's the chip that tells us where packets begin and end.) - * We also keep track of the end of the ring and set the - * end-of-ring bits as needed, and we set the ownership bits - * in all except the very first descriptor. (The caller will - * set this descriptor later when it start transmission or - * reception.) - */ - idx = ctx->rl_idx; - while(1) { - u_int32_t cmdstat; - d = &ctx->rl_ring[idx]; - if (le32toh(d->rl_cmdstat) & RL_RDESC_STAT_OWN) { - ctx->rl_maxsegs = 0; - return; - } - cmdstat = segs[i].ds_len; - d->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr)); - d->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr)); - if (i == 0) - cmdstat |= RL_TDESC_CMD_SOF; - else - cmdstat |= RL_TDESC_CMD_OWN; - if (idx == (RL_RX_DESC_CNT - 1)) - cmdstat |= RL_TDESC_CMD_EOR; - d->rl_cmdstat = htole32(cmdstat | ctx->rl_flags); - i++; - if (i == nseg) - break; - RL_DESC_INC(idx); - } - - d->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF); - ctx->rl_maxsegs = nseg; - ctx->rl_idx = idx; - - return; -} - -/* - * Map a single buffer address. - */ - -static void -rl_dma_map_addr(arg, segs, nseg, error) - void *arg; - bus_dma_segment_t *segs; - int nseg; - int error; -{ - u_int32_t *addr; - - if (error) - return; - - KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); - addr = arg; - *addr = segs->ds_addr; - - return; -} - -static int -rl_allocmem(dev, sc) - device_t dev; - struct rl_softc *sc; -{ - int error; - - /* - * Now allocate a tag for the DMA descriptor lists. - * All of our lists are allocated as a contiguous block - * of memory. - */ - error = bus_dma_tag_create(sc->rl_parent_tag, /* parent */ - 1, 0, /* alignment, boundary */ - BUS_SPACE_MAXADDR, /* lowaddr */ - BUS_SPACE_MAXADDR, /* highaddr */ - NULL, NULL, /* filter, filterarg */ - RL_RXBUFLEN + 1518, 1, /* maxsize,nsegments */ - BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ - 0, /* flags */ - NULL, NULL, /* lockfunc, lockarg */ - &sc->rl_tag); - if (error) - return(error); - - /* - * Now allocate a chunk of DMA-able memory based on the - * tag we just created. - */ - error = bus_dmamem_alloc(sc->rl_tag, - (void **)&sc->rl_cdata.rl_rx_buf, BUS_DMA_NOWAIT, - &sc->rl_cdata.rl_rx_dmamap); - - if (error) { - printf("rl%d: no memory for list buffers!\n", sc->rl_unit); - bus_dma_tag_destroy(sc->rl_tag); - sc->rl_tag = NULL; - return(error); - } - - /* Leave a few bytes before the start of the RX ring buffer. */ - sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf; - sc->rl_cdata.rl_rx_buf += sizeof(u_int64_t); - - return(0); -} - -static int -rl_allocmemcplus(dev, sc) - device_t dev; - struct rl_softc *sc; -{ - int error; - int nseg; - int i; - - /* - * Allocate map for RX mbufs. - */ - nseg = 32; - error = bus_dma_tag_create(sc->rl_parent_tag, ETHER_ALIGN, 0, - BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, - NULL, MCLBYTES * nseg, nseg, MCLBYTES, 0, NULL, NULL, - &sc->rl_ldata.rl_mtag); - if (error) { - device_printf(dev, "could not allocate dma tag\n"); - return (ENOMEM); - } - - /* - * Allocate map for TX descriptor list. - */ - error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, - 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, - NULL, RL_TX_LIST_SZ, 1, RL_TX_LIST_SZ, 0, NULL, NULL, - &sc->rl_ldata.rl_tx_list_tag); - if (error) { - device_printf(dev, "could not allocate dma tag\n"); - return (ENOMEM); - } - - /* Allocate DMA'able memory for the TX ring */ - - error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag, - (void **)&sc->rl_ldata.rl_tx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, - &sc->rl_ldata.rl_tx_list_map); - if (error) - return (ENOMEM); - - /* Load the map for the TX ring. */ - - error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag, - sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list, - RL_TX_LIST_SZ, rl_dma_map_addr, - &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT); - - /* Create DMA maps for TX buffers */ - - for (i = 0; i < RL_TX_DESC_CNT; i++) { - error = bus_dmamap_create(sc->rl_ldata.rl_mtag, 0, - &sc->rl_ldata.rl_tx_dmamap[i]); - if (error) { - device_printf(dev, "can't create DMA map for TX\n"); - return(ENOMEM); - } - } - - /* - * Allocate map for RX descriptor list. - */ - error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, - 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, - NULL, RL_TX_LIST_SZ, 1, RL_TX_LIST_SZ, 0, NULL, NULL, - &sc->rl_ldata.rl_rx_list_tag); - if (error) { - device_printf(dev, "could not allocate dma tag\n"); - return (ENOMEM); - } - - /* Allocate DMA'able memory for the RX ring */ - - error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag, - (void **)&sc->rl_ldata.rl_rx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, - &sc->rl_ldata.rl_rx_list_map); - if (error) - return (ENOMEM); - - /* Load the map for the RX ring. */ - - error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag, - sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list, - RL_TX_LIST_SZ, rl_dma_map_addr, - &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT); - - /* Create DMA maps for RX buffers */ - - for (i = 0; i < RL_RX_DESC_CNT; i++) { - error = bus_dmamap_create(sc->rl_ldata.rl_mtag, 0, - &sc->rl_ldata.rl_rx_dmamap[i]); - if (error) { - device_printf(dev, "can't create DMA map for RX\n"); - return(ENOMEM); - } - } - - return(0); -} - -/* * Attach the interface. Allocate softc structures, do ifmedia * setup and ethernet/BPF attach. */ @@ -1337,10 +907,8 @@ rl_attach(dev) u_int16_t as[3]; struct rl_softc *sc; struct ifnet *ifp; - struct rl_type *t; - struct rl_hwrev *hw_rev; - int hwrev; u_int16_t rl_did = 0; + struct rl_type *t; int unit, error = 0, rid, i; sc = device_get_softc(dev); @@ -1397,8 +965,8 @@ rl_attach(dev) */ if ((rman_get_end(sc->rl_res)-rman_get_start(sc->rl_res))==0xff) { - printf("rl%d: Realtek 8139B detected. Warning," - " this may be unstable in autoselect mode\n", unit); + printf("rl%d: Realtek 8139B detected. Warning, " + "this may be unstable in autoselect mode\n", unit); } #endif @@ -1447,6 +1015,7 @@ rl_attach(dev) rl_read_eeprom(sc, (caddr_t)&rl_did, RL_EE_PCI_DID, 1, 0); t = rl_devs; + sc->rl_type = 0; while(t->rl_name != NULL) { if (rl_did == t->rl_did) { sc->rl_type = t->rl_basetype; @@ -1454,29 +1023,12 @@ rl_attach(dev) } t++; } - if (t->rl_name == NULL) { + + if (sc->rl_type == 0) { printf("rl%d: unknown device ID: %x\n", unit, rl_did); error = ENXIO; goto fail; } - if (sc->rl_type == RL_8139) { - hw_rev = rl_hwrevs; - hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV; - while (hw_rev->rl_desc != NULL) { - if (hw_rev->rl_rev == hwrev) { - sc->rl_type = hw_rev->rl_type; - break; - } - hw_rev++; - } - if (hw_rev->rl_desc == NULL) { - printf("rl%d: unknown hwrev: %x\n", unit, hwrev); - } - } else if (rl_did == RT_DEVICEID_8129) { - sc->rl_type = RL_8129; - } else if (rl_did == RT_DEVICEID_8169) { - sc->rl_type = RL_8169; - } /* * Allocate the parent bus DMA tag appropriate for PCI. @@ -1496,19 +1048,42 @@ rl_attach(dev) goto fail; /* - * If this is an 8139C+ or 8169 chip, we have to allocate - * our busdma tags/memory differently. We need to allocate - * a chunk of DMA'able memory for the RX and TX descriptor - * lists. + * Now allocate a tag for the DMA descriptor lists. + * All of our lists are allocated as a contiguous block + * of memory. */ - if (sc->rl_type == RL_8139CPLUS || sc->rl_type == RL_8169) - error = rl_allocmemcplus(dev, sc); - else - error = rl_allocmem(dev, sc); - + error = bus_dma_tag_create(sc->rl_parent_tag, /* parent */ + 1, 0, /* alignment, boundary */ + BUS_SPACE_MAXADDR, /* lowaddr */ + BUS_SPACE_MAXADDR, /* highaddr */ + NULL, NULL, /* filter, filterarg */ + RL_RXBUFLEN + 1518, 1, /* maxsize,nsegments */ + BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ + BUS_DMA_ALLOCNOW, /* flags */ + NULL, NULL, /* lockfunc, lockarg */ + &sc->rl_tag); if (error) goto fail; + /* + * Now allocate a chunk of DMA-able memory based on the + * tag we just created. + */ + error = bus_dmamem_alloc(sc->rl_tag, + (void **)&sc->rl_cdata.rl_rx_buf, BUS_DMA_NOWAIT | BUS_DMA_ZERO, + &sc->rl_cdata.rl_rx_dmamap); + + if (error) { + printf("rl%d: no memory for list buffers!\n", unit); + bus_dma_tag_destroy(sc->rl_tag); + sc->rl_tag = NULL; + goto fail; + } + + /* Leave a few bytes before the start of the RX ring buffer. */ + sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf; + sc->rl_cdata.rl_rx_buf += sizeof(u_int64_t); + /* Do MII setup */ if (mii_phy_probe(dev, &sc->rl_miibus, rl_ifmedia_upd, rl_ifmedia_sts)) { @@ -1525,18 +1100,11 @@ rl_attach(dev) ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; ifp->if_ioctl = rl_ioctl; ifp->if_output = ether_output; - ifp->if_capabilities = IFCAP_VLAN_MTU; - if (RL_ISCPLUS(sc)) { - ifp->if_start = rl_startcplus; - ifp->if_hwassist = RL_CSUM_FEATURES; - ifp->if_capabilities |= IFCAP_HWCSUM|IFCAP_VLAN_HWTAGGING; - } else - ifp->if_start = rl_start; + ifp->if_start = rl_start; ifp->if_watchdog = rl_watchdog; ifp->if_init = rl_init; ifp->if_baudrate = 10000000; - ifp->if_snd.ifq_maxlen = RL_IFQ_MAXLEN; - ifp->if_capenable = ifp->if_capabilities; + ifp->if_snd.ifq_maxlen = IFQ_MAXLEN; callout_handle_init(&sc->rl_stat_ch); @@ -1547,7 +1115,7 @@ rl_attach(dev) /* Hook interrupt last to avoid having to lock softc */ error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET, - RL_ISCPLUS(sc) ? rl_intrcplus : rl_intr, sc, &sc->rl_intrhand); + rl_intr, sc, &sc->rl_intrhand); if (error) { printf("rl%d: couldn't set up irq\n", unit); @@ -1575,7 +1143,6 @@ rl_detach(dev) { struct rl_softc *sc; struct ifnet *ifp; - int i; sc = device_get_softc(dev); KASSERT(mtx_initialized(&sc->rl_mtx), ("rl mutex not initialized")); @@ -1598,63 +1165,12 @@ rl_detach(dev) if (sc->rl_res) bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); - if (RL_ISCPLUS(sc)) { - - /* Unload and free the RX DMA ring memory and map */ - - if (sc->rl_ldata.rl_rx_list_tag) { - bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag, - sc->rl_ldata.rl_rx_list_map); - bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag, - sc->rl_ldata.rl_rx_list, - sc->rl_ldata.rl_rx_list_map); - bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag); - } - - /* Unload and free the TX DMA ring memory and map */ - - if (sc->rl_ldata.rl_tx_list_tag) { - bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag, - sc->rl_ldata.rl_tx_list_map); - bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag, - sc->rl_ldata.rl_tx_list, - sc->rl_ldata.rl_tx_list_map); - bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag); - } - - /* Destroy all the RX and TX buffer maps */ - - if (sc->rl_ldata.rl_mtag) { - for (i = 0; i < RL_TX_DESC_CNT; i++) - bus_dmamap_destroy(sc->rl_ldata.rl_mtag, - sc->rl_ldata.rl_tx_dmamap[i]); - for (i = 0; i < RL_RX_DESC_CNT; i++) - bus_dmamap_destroy(sc->rl_ldata.rl_mtag, - sc->rl_ldata.rl_rx_dmamap[i]); - bus_dma_tag_destroy(sc->rl_ldata.rl_mtag); - } - - /* Unload and free the stats buffer and map */ - - if (sc->rl_ldata.rl_stag) { - bus_dmamap_unload(sc->rl_ldata.rl_stag, - sc->rl_ldata.rl_rx_list_map); - bus_dmamem_free(sc->rl_ldata.rl_stag, - sc->rl_ldata.rl_stats, - sc->rl_ldata.rl_smap); - bus_dma_tag_destroy(sc->rl_ldata.rl_stag); - } - - } else { - if (sc->rl_tag) { - bus_dmamap_unload(sc->rl_tag, - sc->rl_cdata.rl_rx_dmamap); - bus_dmamem_free(sc->rl_tag, sc->rl_cdata.rl_rx_buf, - sc->rl_cdata.rl_rx_dmamap); - bus_dma_tag_destroy(sc->rl_tag); - } + if (sc->rl_tag) { + bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap); + bus_dmamem_free(sc->rl_tag, sc->rl_cdata.rl_rx_buf, + sc->rl_cdata.rl_rx_dmamap); + bus_dma_tag_destroy(sc->rl_tag); } - if (sc->rl_parent_tag) bus_dma_tag_destroy(sc->rl_parent_tag); @@ -1687,220 +1203,6 @@ rl_list_tx_init(sc) return(0); } -static int -rl_newbuf (sc, idx, m) - struct rl_softc *sc; - int idx; - struct mbuf *m; -{ - struct rl_dmaload_arg arg; - struct mbuf *n = NULL; - int error; - - if (m == NULL) { - n = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); - if (n == NULL) - return(ENOBUFS); - m = n; - } else - m->m_data = m->m_ext.ext_buf; - - /* - * Initialize mbuf length fields and fixup - * alignment so that the frame payload is - * longword aligned. - */ - m->m_len = m->m_pkthdr.len = 1536; - m_adj(m, ETHER_ALIGN); - - arg.sc = sc; - arg.rl_idx = idx; - arg.rl_maxsegs = 1; - arg.rl_flags = 0; - arg.rl_ring = sc->rl_ldata.rl_rx_list; - - error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, - sc->rl_ldata.rl_rx_dmamap[idx], m, rl_dma_map_desc, - &arg, BUS_DMA_NOWAIT); - if (error || arg.rl_maxsegs != 1) { - if (n != NULL) - m_freem(n); - return (ENOMEM); - } - - sc->rl_ldata.rl_rx_list[idx].rl_cmdstat |= htole32(RL_RDESC_CMD_OWN); - sc->rl_ldata.rl_rx_mbuf[idx] = m; - - bus_dmamap_sync(sc->rl_ldata.rl_mtag, - sc->rl_ldata.rl_rx_dmamap[idx], - BUS_DMASYNC_PREREAD); - - return(0); -} - -static int -rl_tx_list_init(sc) - struct rl_softc *sc; -{ - bzero ((char *)sc->rl_ldata.rl_tx_list, RL_TX_LIST_SZ); - bzero ((char *)&sc->rl_ldata.rl_tx_mbuf, - (RL_TX_DESC_CNT * sizeof(struct mbuf *))); - - bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, - sc->rl_ldata.rl_tx_list_map, BUS_DMASYNC_PREWRITE); - sc->rl_ldata.rl_tx_prodidx = 0; - sc->rl_ldata.rl_tx_considx = 0; - sc->rl_ldata.rl_tx_free = RL_TX_DESC_CNT; - - return(0); -} - -static int -rl_rx_list_init(sc) - struct rl_softc *sc; -{ - int i; - - bzero ((char *)sc->rl_ldata.rl_rx_list, RL_RX_LIST_SZ); - bzero ((char *)&sc->rl_ldata.rl_rx_mbuf, - (RL_RX_DESC_CNT * sizeof(struct mbuf *))); - - for (i = 0; i < RL_RX_DESC_CNT; i++) { - if (rl_newbuf(sc, i, NULL) == ENOBUFS) - return(ENOBUFS); - } - - /* Flush the RX descriptors */ - - bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, - sc->rl_ldata.rl_rx_list_map, - BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); - - sc->rl_ldata.rl_rx_prodidx = 0; - - return(0); -} - -/* - * RX handler for C+. This is pretty much like any other - * descriptor-based RX handler. - */ -static void -rl_rxeofcplus(sc) - struct rl_softc *sc; -{ - struct mbuf *m; - struct ifnet *ifp; - int i, total_len; - struct rl_desc *cur_rx; - u_int32_t rxstat, rxvlan; - - ifp = &sc->arpcom.ac_if; - i = sc->rl_ldata.rl_rx_prodidx; - - /* Invalidate the descriptor memory */ - - bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, - sc->rl_ldata.rl_rx_list_map, - BUS_DMASYNC_POSTREAD); - - while (!RL_OWN(&sc->rl_ldata.rl_rx_list[i])) { - - cur_rx = &sc->rl_ldata.rl_rx_list[i]; - m = sc->rl_ldata.rl_rx_mbuf[i]; - total_len = RL_RXBYTES(cur_rx) - ETHER_CRC_LEN; - rxstat = le32toh(cur_rx->rl_cmdstat); - rxvlan = le32toh(cur_rx->rl_vlanctl); - - /* Invalidate the RX mbuf and unload its map */ - - bus_dmamap_sync(sc->rl_ldata.rl_mtag, - sc->rl_ldata.rl_rx_dmamap[i], - BUS_DMASYNC_POSTREAD); - bus_dmamap_unload(sc->rl_ldata.rl_mtag, - sc->rl_ldata.rl_rx_dmamap[i]); - - /* - * NOTE: For some reason that I can't comprehend, - * the RealTek engineers decided not to implement - * the 'frame alignment error' bit in the 8169's - * status word. Unfortunately, rather than simply - * mark the bit as 'reserved,' they took it away - * completely and shifted the other status bits - * over one slot. The OWN, EOR, FS and LS bits are - * still in the same places, as is the frame length - * field. We have already extracted the frame length - * and checked the OWN bit, so to work around this - * problem, we shift the status bits one space to - * the right so that we can evaluate everything else - * correctly. - */ - if (sc->rl_type == RL_8169) - rxstat >>= 1; - - if (rxstat & RL_RDESC_STAT_RXERRSUM) { - ifp->if_ierrors++; - rl_newbuf(sc, i, m); - RL_DESC_INC(i); - continue; - } - - /* - * If allocating a replacement mbuf fails, - * reload the current one. - */ - - if (rl_newbuf(sc, i, NULL)) { - ifp->if_ierrors++; - rl_newbuf(sc, i, m); - RL_DESC_INC(i); - continue; - } - - RL_DESC_INC(i); - - ifp->if_ipackets++; - m->m_pkthdr.len = m->m_len = total_len; - m->m_pkthdr.rcvif = ifp; - - /* Do RX checksumming if enabled */ - - if (ifp->if_capenable & IFCAP_RXCSUM) { - - /* Check IP header checksum */ - if (rxstat & RL_RDESC_STAT_PROTOID) - m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; - if (!(rxstat & RL_RDESC_STAT_IPSUMBAD)) - m->m_pkthdr.csum_flags |= CSUM_IP_VALID; - - /* Check TCP/UDP checksum */ - if ((RL_TCPPKT(rxstat) && - !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || - (RL_UDPPKT(rxstat) && - !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { - m->m_pkthdr.csum_flags |= - CSUM_DATA_VALID|CSUM_PSEUDO_HDR; - m->m_pkthdr.csum_data = 0xffff; - } - } - - if (rxvlan & RL_RDESC_VLANCTL_TAG) - VLAN_INPUT_TAG(ifp, m, - ntohs((rxvlan & RL_RDESC_VLANCTL_DATA)), continue); - (*ifp->if_input)(ifp, m); - } - - /* Flush the RX DMA ring */ - - bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, - sc->rl_ldata.rl_rx_list_map, - BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); - - sc->rl_ldata.rl_rx_prodidx = i; - - return; -} - /* * A frame has been uploaded: pass the resulting mbuf chain up to * the higher level protocols. @@ -2042,64 +1344,6 @@ rl_rxeof(sc) return; } -static void -rl_txeofcplus(sc) - struct rl_softc *sc; -{ - struct ifnet *ifp; - u_int32_t txstat; - int idx; - - ifp = &sc->arpcom.ac_if; - idx = sc->rl_ldata.rl_tx_considx; - - /* Invalidate the TX descriptor list */ - - bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, - sc->rl_ldata.rl_tx_list_map, - BUS_DMASYNC_POSTREAD); - - while (idx != sc->rl_ldata.rl_tx_prodidx) { - - txstat = le32toh(sc->rl_ldata.rl_tx_list[idx].rl_cmdstat); - if (txstat & RL_TDESC_CMD_OWN) - break; - - /* - * We only stash mbufs in the last descriptor - * in a fragment chain, which also happens to - * be the only place where the TX status bits - * are valid. - */ - - if (txstat & RL_TDESC_CMD_EOF) { - m_freem(sc->rl_ldata.rl_tx_mbuf[idx]); - sc->rl_ldata.rl_tx_mbuf[idx] = NULL; - bus_dmamap_unload(sc->rl_ldata.rl_mtag, - sc->rl_ldata.rl_tx_dmamap[idx]); - if (txstat & (RL_TDESC_STAT_EXCESSCOL| - RL_TDESC_STAT_COLCNT)) - ifp->if_collisions++; - if (txstat & RL_TDESC_STAT_TXERRSUM) - ifp->if_oerrors++; - else - ifp->if_opackets++; - } - sc->rl_ldata.rl_tx_free++; - RL_DESC_INC(idx); - } - - /* No changes made to the TX ring, so no flush needed */ - - if (idx != sc->rl_ldata.rl_tx_considx) { - sc->rl_ldata.rl_tx_considx = idx; - ifp->if_flags &= ~IFF_OACTIVE; - ifp->if_timer = 0; - } - - return; -} - /* * A frame was downloaded to the chip. It's safe for us to clean up * the list buffers. @@ -2188,24 +1432,15 @@ rl_poll (struct ifnet *ifp, enum poll_cmd cmd, int count) RL_LOCK(sc); if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ - if (RL_ISCPLUS(sc)) - CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); - else - CSR_WRITE_2(sc, RL_IMR, RL_INTRS); + CSR_WRITE_2(sc, RL_IMR, RL_INTRS); goto done; } sc->rxcycles = count; - if (RL_ISCPLUS(sc)) { - rl_rxeofcplus(sc); - rl_txeofcplus(sc); - } else { - rl_rxeof(sc); - rl_txeof(sc); - } - + rl_rxeof(sc); + rl_txeof(sc); if (ifp->if_snd.ifq_head != NULL) - (*ifp->if_start)(ifp); + rl_start(ifp); if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ u_int16_t status; @@ -2231,74 +1466,6 @@ done: #endif /* DEVICE_POLLING */ static void -rl_intrcplus(arg) - void *arg; -{ - struct rl_softc *sc; - struct ifnet *ifp; - u_int16_t status; - - sc = arg; - - if (sc->suspended) { - return; - } - - RL_LOCK(sc); - ifp = &sc->arpcom.ac_if; - -#ifdef DEVICE_POLLING - if (ifp->if_flags & IFF_POLLING) - goto done; - if (ether_poll_register(rl_poll, ifp)) { /* ok, disable interrupts */ - CSR_WRITE_2(sc, RL_IMR, 0x0000); - rl_poll(ifp, 0, 1); - goto done; - } -#endif /* DEVICE_POLLING */ - - for (;;) { - - status = CSR_READ_2(sc, RL_ISR); - /* If the card has gone away the read returns 0xffff. */ - if (status == 0xffff) - break; - if (status) - CSR_WRITE_2(sc, RL_ISR, status); - - if ((status & RL_INTRS_CPLUS) == 0) - break; - - if (status & RL_ISR_RX_OK) - rl_rxeofcplus(sc); - - if (status & RL_ISR_RX_ERR) - rl_rxeofcplus(sc); - - if ((status & RL_ISR_TIMEOUT_EXPIRED) || - (status & RL_ISR_TX_ERR) || - (status & RL_ISR_TX_DESC_UNAVAIL)) - rl_txeofcplus(sc); - - if (status & RL_ISR_SYSTEM_ERR) { - rl_reset(sc); - rl_init(sc); - } - - } - - if (ifp->if_snd.ifq_head != NULL) - (*ifp->if_start)(ifp); - -#ifdef DEVICE_POLLING -done: -#endif - RL_UNLOCK(sc); - - return; -} - -static void rl_intr(arg) void *arg; { @@ -2354,7 +1521,7 @@ rl_intr(arg) } if (ifp->if_snd.ifq_head != NULL) - (*ifp->if_start)(ifp); + rl_start(ifp); #ifdef DEVICE_POLLING done: @@ -2364,184 +1531,6 @@ done: return; } -static int -rl_encapcplus(sc, m_head, idx) - struct rl_softc *sc; - struct mbuf *m_head; - int *idx; -{ - struct mbuf *m_new = NULL; - struct rl_dmaload_arg arg; - bus_dmamap_t map; - int error; - struct m_tag *mtag; - - if (sc->rl_ldata.rl_tx_free < 4) - return(EFBIG); - - /* - * Set up checksum offload. Note: checksum offload bits must - * appear in all descriptors of a multi-descriptor transmit - * attempt. (This is according to testing done with an 8169 - * chip. I'm not sure if this is a requirement or a bug.) - */ - - arg.rl_flags = 0; - - if (m_head->m_pkthdr.csum_flags & CSUM_IP) - arg.rl_flags |= RL_TDESC_CMD_IPCSUM; - if (m_head->m_pkthdr.csum_flags & CSUM_TCP) - arg.rl_flags |= RL_TDESC_CMD_TCPCSUM; - if (m_head->m_pkthdr.csum_flags & CSUM_UDP) - arg.rl_flags |= RL_TDESC_CMD_UDPCSUM; - - arg.sc = sc; - arg.rl_idx = *idx; - arg.rl_maxsegs = sc->rl_ldata.rl_tx_free; - arg.rl_ring = sc->rl_ldata.rl_tx_list; - - map = sc->rl_ldata.rl_tx_dmamap[*idx]; - error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, map, - m_head, rl_dma_map_desc, &arg, BUS_DMA_NOWAIT); - - if (error && error != EFBIG) { - printf("rl%d: can't map mbuf (error %d)\n", sc->rl_unit, error); - return(ENOBUFS); - } - - /* Too many segments to map, coalesce into a single mbuf */ - - if (error || arg.rl_maxsegs == 0) { - m_new = m_defrag(m_head, M_DONTWAIT); - if (m_new == NULL) - return(1); - else - m_head = m_new; - - arg.sc = sc; - arg.rl_idx = *idx; - arg.rl_maxsegs = sc->rl_ldata.rl_tx_free; - arg.rl_ring = sc->rl_ldata.rl_tx_list; - - error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, map, - m_head, rl_dma_map_desc, &arg, BUS_DMA_NOWAIT); - if (error) { - printf("rl%d: can't map mbuf (error %d)\n", - sc->rl_unit, error); - return(EFBIG); - } - } - - /* - * Insure that the map for this transmission - * is placed at the array index of the last descriptor - * in this chain. - */ - sc->rl_ldata.rl_tx_dmamap[*idx] = - sc->rl_ldata.rl_tx_dmamap[arg.rl_idx]; - sc->rl_ldata.rl_tx_dmamap[arg.rl_idx] = map; - - sc->rl_ldata.rl_tx_mbuf[arg.rl_idx] = m_head; - sc->rl_ldata.rl_tx_free -= arg.rl_maxsegs; - - /* - * Set up hardware VLAN tagging. Note: vlan tag info must - * appear in the first descriptor of a multi-descriptor - * transmission attempt. - */ - - mtag = VLAN_OUTPUT_TAG(&sc->arpcom.ac_if, m_head); - if (mtag != NULL) - sc->rl_ldata.rl_tx_list[*idx].rl_vlanctl = - htole32(htons(VLAN_TAG_VALUE(mtag)) | RL_TDESC_VLANCTL_TAG); - - /* Transfer ownership of packet to the chip. */ - - sc->rl_ldata.rl_tx_list[arg.rl_idx].rl_cmdstat |= - htole32(RL_TDESC_CMD_OWN); - if (*idx != arg.rl_idx) - sc->rl_ldata.rl_tx_list[*idx].rl_cmdstat |= - htole32(RL_TDESC_CMD_OWN); - - RL_DESC_INC(arg.rl_idx); - *idx = arg.rl_idx; - - return(0); -} - -/* - * Main transmit routine for C+ and gigE NICs. - */ - -static void -rl_startcplus(ifp) - struct ifnet *ifp; -{ - struct rl_softc *sc; - struct mbuf *m_head = NULL; - int idx; - - sc = ifp->if_softc; - RL_LOCK(sc); - - idx = sc->rl_ldata.rl_tx_prodidx; - - while (sc->rl_ldata.rl_tx_mbuf[idx] == NULL) { - IF_DEQUEUE(&ifp->if_snd, m_head); - if (m_head == NULL) - break; - - if (rl_encapcplus(sc, m_head, &idx)) { - IF_PREPEND(&ifp->if_snd, m_head); - ifp->if_flags |= IFF_OACTIVE; - break; - } - - /* - * If there's a BPF listener, bounce a copy of this frame - * to him. - */ - BPF_MTAP(ifp, m_head); - } - - /* Flush the TX descriptors */ - - bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, - sc->rl_ldata.rl_tx_list_map, - BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); - - sc->rl_ldata.rl_tx_prodidx = idx; - - /* - * RealTek put the TX poll request register in a different - * location on the 8169 gigE chip. I don't know why. - */ - - if (sc->rl_type == RL_8169) - CSR_WRITE_2(sc, RL_GTXSTART, RL_TXSTART_START); - else - CSR_WRITE_2(sc, RL_TXSTART, RL_TXSTART_START); - - /* - * Use the countdown timer for interrupt moderation. - * 'TX done' interrupts are disabled. Instead, we reset the - * countdown timer, which will begin counting until it hits - * the value in the TIMERINT register, and then trigger an - * interrupt. Each time we write to the TIMERCNT register, - * the timer count is reset to 0. - */ - CSR_WRITE_4(sc, RL_TIMERCNT, 1); - - RL_UNLOCK(sc); - - /* - * Set a timeout in case the chip goes out to lunch. - */ - ifp->if_timer = 5; - - return; -} - /* * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data * pointers to the fragment pointers. @@ -2621,8 +1610,7 @@ rl_start(ifp) bus_dmamap_create(sc->rl_tag, 0, &RL_CUR_DMAMAP(sc)); bus_dmamap_load(sc->rl_tag, RL_CUR_DMAMAP(sc), mtod(RL_CUR_TXMBUF(sc), void *), - RL_CUR_TXMBUF(sc)->m_pkthdr.len, rl_dma_map_txbuf, - sc, BUS_DMA_NOWAIT); + RL_CUR_TXMBUF(sc)->m_pkthdr.len, rl_dma_map_txbuf, sc, 0); bus_dmamap_sync(sc->rl_tag, RL_CUR_DMAMAP(sc), BUS_DMASYNC_PREREAD); CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc), @@ -2679,24 +1667,14 @@ rl_init(xsc) *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); - /* - * For C+ mode, initialize the RX descriptors and mbufs. - */ - if (RL_ISCPLUS(sc)) { - rl_rx_list_init(sc); - rl_tx_list_init(sc); - } else { - - /* Init the RX buffer pointer register. */ - bus_dmamap_load(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, - sc->rl_cdata.rl_rx_buf, RL_RXBUFLEN, - rl_dma_map_rxbuf, sc, BUS_DMA_NOWAIT); - bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, - BUS_DMASYNC_PREWRITE); + /* Init the RX buffer pointer register. */ + bus_dmamap_load(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, + sc->rl_cdata.rl_rx_buf, RL_RXBUFLEN, rl_dma_map_rxbuf, sc, 0); + bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, + BUS_DMASYNC_PREWRITE); - /* Init TX descriptors. */ - rl_list_tx_init(sc); - } + /* Init TX descriptors. */ + rl_list_tx_init(sc); /* * Enable transmit and receive. @@ -2749,64 +1727,16 @@ rl_init(xsc) /* * Enable interrupts. */ - if (RL_ISCPLUS(sc)) - CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); - else - CSR_WRITE_2(sc, RL_IMR, RL_INTRS); + CSR_WRITE_2(sc, RL_IMR, RL_INTRS); /* Set initial TX threshold */ sc->rl_txthresh = RL_TX_THRESH_INIT; /* Start RX/TX process. */ CSR_WRITE_4(sc, RL_MISSEDPKT, 0); -#ifdef notdef + /* Enable receiver and transmitter. */ CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); -#endif - /* - * If this is a C+ capable chip, enable C+ RX and TX mode, - * and load the addresses of the RX and TX lists into the chip. - */ - if (RL_ISCPLUS(sc)) { - CSR_WRITE_2(sc, RL_CPLUS_CMD, RL_CPLUSCMD_RXENB| - RL_CPLUSCMD_TXENB|RL_CPLUSCMD_PCI_MRW| - RL_CPLUSCMD_VLANSTRIP| - (ifp->if_capenable & IFCAP_RXCSUM ? - RL_CPLUSCMD_RXCSUM_ENB : 0)); - - CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI, - RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr)); - CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO, - RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr)); - - CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI, - RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr)); - CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO, - RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr)); - - CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, RL_EARLYTXTHRESH_CNT); - - /* - * Initialize the timer interrupt register so that - * a timer interrupt will be generated once the timer - * reaches a certain number of ticks. The timer is - * reloaded on each transmit. This gives us TX interrupt - * moderation, which dramatically improves TX frame rate. - */ - - if (sc->rl_type == RL_8169) - CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800); - else - CSR_WRITE_4(sc, RL_TIMERINT, 0x400); - - /* - * For 8169 gigE NICs, set the max allowed RX packet - * size so we can receive jumbo frames. - */ - if (sc->rl_type == RL_8169) - CSR_WRITE_2(sc, RL_MAXRXPKTLEN, RL_PKTSZ(16384)); - - } mii_mediachg(mii); @@ -2892,15 +1822,6 @@ rl_ioctl(ifp, command, data) mii = device_get_softc(sc->rl_miibus); error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); break; - case SIOCSIFCAP: - ifp->if_capenable = ifr->ifr_reqcap; - if (ifp->if_capenable & IFCAP_TXCSUM) - ifp->if_hwassist = RL_CSUM_FEATURES; - else - ifp->if_hwassist = 0; - if (ifp->if_flags & IFF_RUNNING) - rl_init(sc); - break; default: error = ether_ioctl(ifp, command, data); break; @@ -2922,16 +1843,9 @@ rl_watchdog(ifp) printf("rl%d: watchdog timeout\n", sc->rl_unit); ifp->if_oerrors++; - if (RL_ISCPLUS(sc)) { - rl_txeofcplus(sc); - rl_rxeofcplus(sc); - } else { - rl_txeof(sc); - rl_rxeof(sc); - } - + rl_txeof(sc); + rl_rxeof(sc); rl_init(sc); - RL_UNLOCK(sc); return; @@ -2960,48 +1874,20 @@ rl_stop(sc) CSR_WRITE_1(sc, RL_COMMAND, 0x00); CSR_WRITE_2(sc, RL_IMR, 0x0000); + bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap); - if (RL_ISCPLUS(sc)) { - - /* Free the TX list buffers. */ - - for (i = 0; i < RL_TX_DESC_CNT; i++) { - if (sc->rl_ldata.rl_tx_mbuf[i] != NULL) { - bus_dmamap_unload(sc->rl_ldata.rl_mtag, - sc->rl_ldata.rl_tx_dmamap[i]); - m_freem(sc->rl_ldata.rl_tx_mbuf[i]); - sc->rl_ldata.rl_tx_mbuf[i] = NULL; - } - } - - /* Free the RX list buffers. */ - - for (i = 0; i < RL_RX_DESC_CNT; i++) { - if (sc->rl_ldata.rl_rx_mbuf[i] != NULL) { - bus_dmamap_unload(sc->rl_ldata.rl_mtag, - sc->rl_ldata.rl_rx_dmamap[i]); - m_freem(sc->rl_ldata.rl_rx_mbuf[i]); - sc->rl_ldata.rl_rx_mbuf[i] = NULL; - } - } - - } else { - - bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap); - - /* - * Free the TX list buffers. - */ - for (i = 0; i < RL_TX_LIST_CNT; i++) { - if (sc->rl_cdata.rl_tx_chain[i] != NULL) { - bus_dmamap_unload(sc->rl_tag, - sc->rl_cdata.rl_tx_dmamap[i]); - bus_dmamap_destroy(sc->rl_tag, - sc->rl_cdata.rl_tx_dmamap[i]); - m_freem(sc->rl_cdata.rl_tx_chain[i]); - sc->rl_cdata.rl_tx_chain[i] = NULL; - CSR_WRITE_4(sc, RL_TXADDR0 + i, 0x0000000); - } + /* + * Free the TX list buffers. + */ + for (i = 0; i < RL_TX_LIST_CNT; i++) { + if (sc->rl_cdata.rl_tx_chain[i] != NULL) { + bus_dmamap_unload(sc->rl_tag, + sc->rl_cdata.rl_tx_dmamap[i]); + bus_dmamap_destroy(sc->rl_tag, + sc->rl_cdata.rl_tx_dmamap[i]); + m_freem(sc->rl_cdata.rl_tx_chain[i]); + sc->rl_cdata.rl_tx_chain[i] = NULL; + CSR_WRITE_4(sc, RL_TXADDR0 + i, 0x0000000); } } @@ -3026,7 +1912,7 @@ rl_suspend(dev) rl_stop(sc); for (i = 0; i < 5; i++) - sc->saved_maps[i] = pci_read_config(dev, PCIR_BAR(i), 4); + sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); @@ -3055,7 +1941,7 @@ rl_resume(dev) /* better way to do this? */ for (i = 0; i < 5; i++) - pci_write_config(dev, PCIR_BAR(i), sc->saved_maps[i], 4); + pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); |
