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-rw-r--r--sys/mips/include/_types.h8
-rw-r--r--sys/mips/include/cpufunc.h12
-rw-r--r--sys/mips/include/param.h73
-rw-r--r--sys/mips/include/proc.h22
-rw-r--r--sys/mips/include/pte.h63
-rw-r--r--sys/mips/mips/dump_machdep.c2
-rw-r--r--sys/mips/mips/exception.S77
-rw-r--r--sys/mips/mips/machdep.c5
-rw-r--r--sys/mips/mips/pmap.c2
-rw-r--r--sys/mips/mips/swtch.S13
-rw-r--r--sys/mips/rmi/xlr_machdep.c2
11 files changed, 159 insertions, 120 deletions
diff --git a/sys/mips/include/_types.h b/sys/mips/include/_types.h
index 57fc843..40c8db2 100644
--- a/sys/mips/include/_types.h
+++ b/sys/mips/include/_types.h
@@ -133,13 +133,17 @@ typedef __uint32_t __u_register_t;
#endif
#ifdef __LP64__
typedef __uint64_t __vm_offset_t;
-typedef __uint64_t __vm_paddr_t;
typedef __uint64_t __vm_size_t;
#else
typedef __uint32_t __vm_offset_t;
-typedef __uint32_t __vm_paddr_t;
typedef __uint32_t __vm_size_t;
#endif
+#if defined(__LP64__) || defined(__mips_n32) /* PHYSADDR_64_BIT */
+typedef __uint64_t __vm_paddr_t;
+#else
+typedef __uint32_t __vm_paddr_t;
+#endif
+
typedef __int64_t __vm_ooffset_t;
typedef __uint64_t __vm_pindex_t;
diff --git a/sys/mips/include/cpufunc.h b/sys/mips/include/cpufunc.h
index 01018da..e9350be 100644
--- a/sys/mips/include/cpufunc.h
+++ b/sys/mips/include/cpufunc.h
@@ -138,11 +138,13 @@ mips_wr_ ## n (uint64_t a0) \
#if defined(__mips_n64)
MIPS_RW64_COP0(excpc, MIPS_COP_0_EXC_PC);
-MIPS_RW64_COP0(entrylo0, MIPS_COP_0_TLB_LO0);
-MIPS_RW64_COP0(entrylo1, MIPS_COP_0_TLB_LO1);
MIPS_RW64_COP0(entryhi, MIPS_COP_0_TLB_HI);
MIPS_RW64_COP0(pagemask, MIPS_COP_0_TLB_PG_MASK);
#endif
+#if defined(__mips_n64) || defined(__mips_n32) /* PHYSADDR_64_BIT */
+MIPS_RW64_COP0(entrylo0, MIPS_COP_0_TLB_LO0);
+MIPS_RW64_COP0(entrylo1, MIPS_COP_0_TLB_LO1);
+#endif
MIPS_RW64_COP0(xcontext, MIPS_COP_0_TLB_XCONTEXT);
#undef MIPS_RW64_COP0
@@ -221,11 +223,13 @@ MIPS_RW32_COP0(status, MIPS_COP_0_STATUS);
/* XXX: Some of these registers are specific to MIPS32. */
#if !defined(__mips_n64)
-MIPS_RW32_COP0(entrylo0, MIPS_COP_0_TLB_LO0);
-MIPS_RW32_COP0(entrylo1, MIPS_COP_0_TLB_LO1);
MIPS_RW32_COP0(entryhi, MIPS_COP_0_TLB_HI);
MIPS_RW32_COP0(pagemask, MIPS_COP_0_TLB_PG_MASK);
#endif
+#if !defined(__mips_n64) && !defined(__mips_n32) /* !PHYSADDR_64_BIT */
+MIPS_RW32_COP0(entrylo0, MIPS_COP_0_TLB_LO0);
+MIPS_RW32_COP0(entrylo1, MIPS_COP_0_TLB_LO1);
+#endif
MIPS_RW32_COP0(prid, MIPS_COP_0_PRID);
/* XXX 64-bit? */
MIPS_RW32_COP0_SEL(ebase, MIPS_COP_0_PRID, 1);
diff --git a/sys/mips/include/param.h b/sys/mips/include/param.h
index d3bed63..0b1ea98 100644
--- a/sys/mips/include/param.h
+++ b/sys/mips/include/param.h
@@ -116,31 +116,39 @@
#define CACHE_LINE_SHIFT 6
#define CACHE_LINE_SIZE (1 << CACHE_LINE_SHIFT)
-#define PAGE_SHIFT 12 /* LOG2(PAGE_SIZE) */
-#define PAGE_SIZE (1<<PAGE_SHIFT) /* bytes/page */
-#define PAGE_MASK (PAGE_SIZE-1)
-
-#define NPTEPG (PAGE_SIZE/(sizeof (pt_entry_t)))
-#define NPDEPG (PAGE_SIZE/(sizeof (pd_entry_t)))
-
-#if defined(__mips_n64)
-#define SEGSHIFT 31 /* LOG2(NBSEG) */
-#define NBSEG (1ul << SEGSHIFT) /* bytes/segment */
-#define PDRSHIFT 22 /* second level */
-#define PDRMASK ((1 << PDRSHIFT) - 1)
+#define PAGE_SHIFT 12 /* LOG2(PAGE_SIZE) */
+#define PAGE_SIZE (1<<PAGE_SHIFT) /* bytes/page */
+#define PAGE_MASK (PAGE_SIZE-1)
+
+#define NPTEPG (PAGE_SIZE/(sizeof (pt_entry_t)))
+#define NPDEPG (PAGE_SIZE/(sizeof (pd_entry_t)))
+
+#if defined(__mips_n32) || defined(__mips_n64) /* PHYSADDR_64_BIT */
+#define NPTEPGSHIFT 9 /* LOG2(NPTEPG) */
+#else
+#define NPTEPGSHIFT 10 /* LOG2(NPTEPG) */
+#endif
+
+#ifdef __mips_n64
+#define NPDEPGSHIFT 9 /* LOG2(NPTEPG) */
+#define SEGSHIFT (PAGE_SHIFT + NPTEPGSHIFT + NPDEPGSHIFT)
+#define NBSEG (1ul << SEGSHIFT)
+#define PDRSHIFT (PAGE_SHIFT + NPTEPGSHIFT)
+#define PDRMASK ((1 << PDRSHIFT) - 1)
#else
-#define SEGSHIFT 22 /* LOG2(NBSEG) */
-#define NBSEG (1 << SEGSHIFT) /* bytes/segment */
-#define PDRSHIFT SEGSHIFT /* alias for SEG in 32 bit */
-#define PDRMASK ((1 << PDRSHIFT) - 1)
+#define NPDEPGSHIFT 10 /* LOG2(NPTEPG) */
+#define SEGSHIFT (PAGE_SHIFT + NPTEPGSHIFT)
+#define NBSEG (1 << SEGSHIFT) /* bytes/segment */
+#define PDRSHIFT SEGSHIFT /* alias for SEG in 32 bit */
+#define PDRMASK ((1 << PDRSHIFT) - 1)
#endif
-#define NBPDR (1 << PDRSHIFT) /* bytes/pagedir */
-#define SEGMASK (NBSEG-1) /* byte offset into segment */
+#define NBPDR (1 << PDRSHIFT) /* bytes/pagedir */
+#define SEGMASK (NBSEG - 1) /* byte offset into segment */
-#define MAXPAGESIZES 1 /* maximum number of supported page sizes */
+#define MAXPAGESIZES 1 /* max supported pagesizes */
-#define BLKDEV_IOSIZE 2048 /* xxx: Why is this 1/2 page? */
-#define MAXDUMPPGS 1 /* xxx: why is this only one? */
+#define BLKDEV_IOSIZE 2048 /* xxx: Why is this 1/2 page? */
+#define MAXDUMPPGS 1 /* xxx: why is this only one? */
/*
* The kernel stack needs to be aligned on a (PAGE_SIZE * 2) boundary.
@@ -151,8 +159,8 @@
#define UPAGES 2
/* pages ("clicks") (4096 bytes) to disk blocks */
-#define ctod(x) ((x) << (PAGE_SHIFT - DEV_BSHIFT))
-#define dtoc(x) ((x) >> (PAGE_SHIFT - DEV_BSHIFT))
+#define ctod(x) ((x) << (PAGE_SHIFT - DEV_BSHIFT))
+#define dtoc(x) ((x) >> (PAGE_SHIFT - DEV_BSHIFT))
/*
* Map a ``block device block'' to a file system block.
@@ -160,24 +168,17 @@
* field from the disk label.
* For now though just use DEV_BSIZE.
*/
-#define bdbtofsb(bn) ((bn) / (BLKDEV_IOSIZE/DEV_BSIZE))
+#define bdbtofsb(bn) ((bn) / (BLKDEV_IOSIZE/DEV_BSIZE))
/*
* Mach derived conversion macros
*/
-#define round_page(x) (((unsigned long)(x) + PAGE_MASK) & ~PAGE_MASK)
-#define trunc_page(x) ((unsigned long)(x) & ~PAGE_MASK)
-
-#define atop(x) ((unsigned long)(x) >> PAGE_SHIFT)
-#define ptoa(x) ((unsigned long)(x) << PAGE_SHIFT)
-
-#define mips_btop(x) ((unsigned long)(x) >> PAGE_SHIFT)
-#define mips_ptob(x) ((unsigned long)(x) << PAGE_SHIFT)
+#define round_page(x) (((x) + PAGE_MASK) & ~PAGE_MASK)
+#define trunc_page(x) ((x) & ~PAGE_MASK)
-#define pgtok(x) ((unsigned long)(x) * (PAGE_SIZE / 1024))
+#define atop(x) ((x) >> PAGE_SHIFT)
+#define ptoa(x) ((x) << PAGE_SHIFT)
-#ifndef _KERNEL
-#define DELAY(n) { register int N = (n); while (--N > 0); }
-#endif /* !_KERNEL */
+#define pgtok(x) ((x) * (PAGE_SIZE / 1024))
#endif /* !_MIPS_INCLUDE_PARAM_H_ */
diff --git a/sys/mips/include/proc.h b/sys/mips/include/proc.h
index e71c858..11a1f8e 100644
--- a/sys/mips/include/proc.h
+++ b/sys/mips/include/proc.h
@@ -43,17 +43,21 @@
* Machine-dependent part of the proc structure.
*/
struct mdthread {
- int md_flags; /* machine-dependent flags */
- int md_upte[KSTACK_PAGES]; /* ptes for mapping u pcb */
- int md_ss_addr; /* single step address for ptrace */
- int md_ss_instr; /* single step instruction for ptrace */
+ int md_flags; /* machine-dependent flags */
+#if defined(__mips_n64) || defined(__mips_n32) /* PHYSADDR_64_BIT */
+ uint64_t md_upte[KSTACK_PAGES]; /* ptes for mapping u pcb */
+#else
+ int md_upte[KSTACK_PAGES];
+#endif
+ int md_ss_addr; /* single step address for ptrace */
+ int md_ss_instr; /* single step instruction for ptrace */
register_t md_saved_intr;
- u_int md_spinlock_count;
+ u_int md_spinlock_count;
/* The following is CPU dependent, but kept in for compatibility */
- int md_pc_ctrl; /* performance counter control */
- int md_pc_count; /* performance counter */
- int md_pc_spill; /* performance counter spill */
- void *md_tls;
+ int md_pc_ctrl; /* performance counter control */
+ int md_pc_count; /* performance counter */
+ int md_pc_spill; /* performance counter spill */
+ void *md_tls;
};
/* md_flags */
diff --git a/sys/mips/include/pte.h b/sys/mips/include/pte.h
index a8926da..4266b4b 100644
--- a/sys/mips/include/pte.h
+++ b/sys/mips/include/pte.h
@@ -30,8 +30,11 @@
#define _MACHINE_PTE_H_
#ifndef _LOCORE
-/* pt_entry_t is 32 bit for now, has to be made 64 bit for n64 */
+#if defined(__mips_n64) || defined(__mips_n32) /* PHYSADDR_64_BIT */
+typedef uint64_t pt_entry_t;
+#else
typedef uint32_t pt_entry_t;
+#endif
typedef pt_entry_t *pd_entry_t;
#endif
@@ -61,10 +64,15 @@ typedef pt_entry_t *pd_entry_t;
* written as anything, but otherwise they have as much meaning as
* other 0 fields.
*/
+#if defined(__mips_n64) || defined(__mips_n32) /* PHYSADDR_64_BIT */
+#define TLBLO_SWBITS_SHIFT (34)
+#define TLBLO_PFN_MASK 0x3FFFFFFC0ULL
+#else
#define TLBLO_SWBITS_SHIFT (30)
-#define TLBLO_SWBITS_MASK (0x3U << TLBLO_SWBITS_SHIFT)
-#define TLBLO_PFN_SHIFT (6)
#define TLBLO_PFN_MASK (0x3FFFFFC0)
+#endif
+#define TLBLO_PFN_SHIFT (6)
+#define TLBLO_SWBITS_MASK ((pt_entry_t)0x3 << TLBLO_SWBITS_SHIFT)
#define TLBLO_PA_TO_PFN(pa) ((((pa) >> TLB_PAGE_SHIFT) << TLBLO_PFN_SHIFT) & TLBLO_PFN_MASK)
#define TLBLO_PFN_TO_PA(pfn) ((vm_paddr_t)((pfn) >> TLBLO_PFN_SHIFT) << TLB_PAGE_SHIFT)
#define TLBLO_PTE_TO_PFN(pte) ((pte) & TLBLO_PFN_MASK)
@@ -96,10 +104,10 @@ typedef pt_entry_t *pd_entry_t;
#define TLBHI_ENTRY(va, asid) ((TLBHI_VA_R((va))) /* Region. */ | \
(TLBHI_VA_TO_VPN2((va))) /* VPN2. */ | \
((asid) & TLBHI_ASID_MASK))
-#else
+#else /* !defined(__mips_n64) */
#define TLBHI_PAGE_MASK (2 * PAGE_SIZE - 1)
#define TLBHI_ENTRY(va, asid) (((va) & ~TLBHI_PAGE_MASK) | ((asid) & TLBHI_ASID_MASK))
-#endif
+#endif /* defined(__mips_n64) */
/*
* TLB flags managed in hardware:
@@ -112,12 +120,12 @@ typedef pt_entry_t *pd_entry_t;
* in EVERY address space, and to ignore the ASID when
* it is matched.
*/
-#define PTE_C(attr) ((attr & 0x07) << 3)
-#define PTE_C_UNCACHED (PTE_C(MIPS_CCA_UNCACHED))
-#define PTE_C_CACHE (PTE_C(MIPS_CCA_CACHED))
-#define PTE_D 0x04
-#define PTE_V 0x02
-#define PTE_G 0x01
+#define PTE_C(attr) ((attr & 0x07) << 3)
+#define PTE_C_UNCACHED (PTE_C(MIPS_CCA_UNCACHED))
+#define PTE_C_CACHE (PTE_C(MIPS_CCA_CACHED))
+#define PTE_D 0x04
+#define PTE_V 0x02
+#define PTE_G 0x01
/*
* VM flags managed in software:
@@ -125,8 +133,8 @@ typedef pt_entry_t *pd_entry_t;
* listen to requests to write to it.
* W: Wired. ???
*/
-#define PTE_RO (0x01 << TLBLO_SWBITS_SHIFT)
-#define PTE_W (0x02 << TLBLO_SWBITS_SHIFT)
+#define PTE_RO ((pt_entry_t)0x01 << TLBLO_SWBITS_SHIFT)
+#define PTE_W ((pt_entry_t)0x02 << TLBLO_SWBITS_SHIFT)
/*
* PTE management functions for bits defined above.
@@ -135,4 +143,33 @@ typedef pt_entry_t *pd_entry_t;
#define pte_set(pte, bit) (*(pte) |= (bit))
#define pte_test(pte, bit) ((*(pte) & (bit)) == (bit))
+/* Assembly support for PTE access*/
+#ifdef LOCORE
+#if defined(__mips_n64) || defined(__mips_n32) /* PHYSADDR_64_BIT */
+#define PTESHIFT 3
+#define PTE2MASK 0xff0 /* for the 2-page lo0/lo1 */
+#define PTEMASK 0xff8
+#define PTESIZE 8
+#define PTE_L ld
+#define PTE_MTC0 dmtc0
+#define CLEAR_PTE_SWBITS(pr)
+#else
+#define PTESHIFT 2
+#define PTE2MASK 0xff8 /* for the 2-page lo0/lo1 */
+#define PTEMASK 0xffc
+#define PTESIZE 4
+#define PTE_L lw
+#define PTE_MTC0 mtc0
+#define CLEAR_PTE_SWBITS(r) sll r, 2; srl r, 2 /* remove 2 high bits */
+#endif /* defined(__mips_n64) || defined(__mips_n32) */
+
+#if defined(__mips_n64)
+#define PTRSHIFT 3
+#define PDEPTRMASK 0xff8
+#else
+#define PTRSHIFT 2
+#define PDEPTRMASK 0xffc
+#endif
+
+#endif /* LOCORE */
#endif /* !_MACHINE_PTE_H_ */
diff --git a/sys/mips/mips/dump_machdep.c b/sys/mips/mips/dump_machdep.c
index 78938de..412c94d 100644
--- a/sys/mips/mips/dump_machdep.c
+++ b/sys/mips/mips/dump_machdep.c
@@ -182,7 +182,7 @@ cb_dumpdata(struct md_pa *mdp, int seqnr, void *arg)
counter &= (1<<24) - 1;
}
- error = dump_write(di, (void *)(pa),0, dumplo, sz);
+ error = dump_write(di, (void *)(intptr_t)(pa),0, dumplo, sz); /* XXX fix PA */
if (error)
break;
dumplo += sz;
diff --git a/sys/mips/mips/exception.S b/sys/mips/mips/exception.S
index fdd0a02..da32a77 100644
--- a/sys/mips/mips/exception.S
+++ b/sys/mips/mips/exception.S
@@ -66,28 +66,13 @@
#include "assym.s"
-/*
- * Clear the software-managed bits in a PTE in register pr.
- */
-#define CLEAR_PTE_SWBITS(pr) \
- sll pr, 2 ; \
- srl pr, 2 # keep bottom 30 bits
-
- .set noreorder # Noreorder is default style!
+ .set noreorder # Noreorder is default style!
/*
* Reasonable limit
*/
#define INTRCNT_COUNT 128
-/* Pointer size and mask for n64 */
-#if defined(__mips_n64)
-#define PTRSHIFT 3
-#define PTRMASK 0xff8
-#else
-#define PTRSHIFT 2
-#define PTRMASK 0xffc
-#endif
/*
*----------------------------------------------------------------------------
@@ -131,7 +116,7 @@ MipsDoTLBMiss:
GET_CPU_PCPU(k1)
PTR_L k1, PC_SEGBASE(k1)
beqz k1, 2f #05: make sure segbase is not null
- andi k0, k0, PTRMASK #06: k0=seg offset
+ andi k0, k0, PDEPTRMASK #06: k0=seg offset
PTR_ADDU k1, k0, k1 #07: k1=seg entry address
PTR_L k1, 0(k1) #08: k1=seg entry
@@ -139,22 +124,22 @@ MipsDoTLBMiss:
beq k1, zero, 2f #0a: ==0 -- no page table
#ifdef __mips_n64
PTR_SRL k0, PDRSHIFT - PTRSHIFT # k0=VPN
- andi k0, k0, PTRMASK # k0=pde offset
+ andi k0, k0, PDEPTRMASK # k0=pde offset
PTR_ADDU k1, k0, k1 # k1=pde entry address
PTR_L k1, 0(k1) # k1=pde entry
MFC0 k0, MIPS_COP_0_BAD_VADDR # k0=bad address (again)
beq k1, zero, 2f # ==0 -- no page table
#endif
- PTR_SRL k0, PAGE_SHIFT - 2 #0b: k0=VPN (aka va>>10)
- andi k0, k0, 0xff8 #0c: k0=page tab offset
+ PTR_SRL k0, PAGE_SHIFT - PTESHIFT #0b: k0=VPN (aka va>>10)
+ andi k0, k0, PTE2MASK #0c: k0=page tab offset
PTR_ADDU k1, k1, k0 #0d: k1=pte address
- lw k0, 0(k1) #0e: k0=lo0 pte
- lw k1, 4(k1) #0f: k1=lo0 pte
+ PTE_L k0, 0(k1) #0e: k0=lo0 pte
+ PTE_L k1, PTESIZE(k1) #0f: k1=lo0 pte
CLEAR_PTE_SWBITS(k0)
- MTC0 k0, MIPS_COP_0_TLB_LO0 #12: lo0 is loaded
+ PTE_MTC0 k0, MIPS_COP_0_TLB_LO0 #12: lo0 is loaded
COP0_SYNC
CLEAR_PTE_SWBITS(k1)
- MTC0 k1, MIPS_COP_0_TLB_LO1 #15: lo1 is loaded
+ PTE_MTC0 k1, MIPS_COP_0_TLB_LO1 #15: lo1 is loaded
COP0_SYNC
tlbwr #1a: write to tlb
HAZARD_DELAY
@@ -824,7 +809,7 @@ NLEAF(MipsTLBInvalidException)
PTR_SRL k0, SEGSHIFT - PTRSHIFT # k0=seg offset (almost)
beq k1, zero, MipsKernGenException # ==0 -- no seg tab
- andi k0, k0, PTRMASK # k0=seg offset
+ andi k0, k0, PDEPTRMASK #06: k0=seg offset
PTR_ADDU k1, k0, k1 # k1=seg entry address
PTR_L k1, 0(k1) # k1=seg entry
@@ -836,7 +821,7 @@ NLEAF(MipsTLBInvalidException)
MFC0 k0, MIPS_COP_0_BAD_VADDR
PTR_SRL k0, PDRSHIFT - PTRSHIFT # k0=pde offset (almost)
beq k1, zero, MipsKernGenException # ==0 -- no pde tab
- andi k0, k0, PTRMASK # k0=pde offset
+ andi k0, k0, PDEPTRMASK # k0=pde offset
PTR_ADDU k1, k0, k1 # k1=pde entry address
PTR_L k1, 0(k1) # k1=pde entry
@@ -845,10 +830,10 @@ NLEAF(MipsTLBInvalidException)
nop
#endif
MFC0 k0, MIPS_COP_0_BAD_VADDR # k0=bad address (again)
- PTR_SRL k0, PAGE_SHIFT - 2 # k0=VPN
- andi k0, k0, 0xffc # k0=page tab offset
+ PTR_SRL k0, PAGE_SHIFT - PTESHIFT # k0=VPN
+ andi k0, k0, PTEMASK # k0=page tab offset
PTR_ADDU k1, k1, k0 # k1=pte address
- lw k0, 0(k1) # k0=this PTE
+ PTE_L k0, 0(k1) # k0=this PTE
/* Validate page table entry. */
andi k0, PTE_V
@@ -856,30 +841,30 @@ NLEAF(MipsTLBInvalidException)
nop
/* Check whether this is an even or odd entry. */
- andi k0, k1, 4
+ andi k0, k1, PTESIZE
bnez k0, odd_page
nop
- lw k0, 0(k1)
- lw k1, 4(k1)
+ PTE_L k0, 0(k1)
+ PTE_L k1, PTESIZE(k1)
CLEAR_PTE_SWBITS(k0)
- MTC0 k0, MIPS_COP_0_TLB_LO0
+ PTE_MTC0 k0, MIPS_COP_0_TLB_LO0
COP0_SYNC
CLEAR_PTE_SWBITS(k1)
- MTC0 k1, MIPS_COP_0_TLB_LO1
+ PTE_MTC0 k1, MIPS_COP_0_TLB_LO1
COP0_SYNC
b tlb_insert_entry
nop
odd_page:
- lw k0, -4(k1)
- lw k1, 0(k1)
+ PTE_L k0, -PTESIZE(k1)
+ PTE_L k1, 0(k1)
CLEAR_PTE_SWBITS(k0)
- MTC0 k0, MIPS_COP_0_TLB_LO0
+ PTE_MTC0 k0, MIPS_COP_0_TLB_LO0
COP0_SYNC
CLEAR_PTE_SWBITS(k1)
- MTC0 k1, MIPS_COP_0_TLB_LO1
+ PTE_MTC0 k1, MIPS_COP_0_TLB_LO1
COP0_SYNC
tlb_insert_entry:
@@ -999,29 +984,29 @@ NLEAF(MipsTLBMissException)
PTR_SRL k0, SEGSHIFT - PTRSHIFT # k0=seg offset (almost)
PTR_L k1, %lo(kernel_segmap)(k1) # k1=segment tab base
beq k1, zero, MipsKernGenException # ==0 -- no seg tab
- andi k0, k0, PTRMASK # k0=seg offset
+ andi k0, k0, PDEPTRMASK #06: k0=seg offset
PTR_ADDU k1, k0, k1 # k1=seg entry address
PTR_L k1, 0(k1) # k1=seg entry
MFC0 k0, MIPS_COP_0_BAD_VADDR # k0=bad address (again)
beq k1, zero, MipsKernGenException # ==0 -- no page table
#ifdef __mips_n64
PTR_SRL k0, PDRSHIFT - PTRSHIFT # k0=VPN
- andi k0, k0, PTRMASK # k0=pde offset
+ andi k0, k0, PDEPTRMASK # k0=pde offset
PTR_ADDU k1, k0, k1 # k1=pde entry address
PTR_L k1, 0(k1) # k1=pde entry
MFC0 k0, MIPS_COP_0_BAD_VADDR # k0=bad address (again)
beq k1, zero, MipsKernGenException # ==0 -- no page table
#endif
- PTR_SRL k0, PAGE_SHIFT - 2 # k0=VPN
- andi k0, k0, 0xff8 # k0=page tab offset
+ PTR_SRL k0, PAGE_SHIFT - PTESHIFT # k0=VPN
+ andi k0, k0, PTE2MASK # k0=page tab offset
PTR_ADDU k1, k1, k0 # k1=pte address
- lw k0, 0(k1) # k0=lo0 pte
- lw k1, 4(k1) # k1=lo1 pte
+ PTE_L k0, 0(k1) # k0=lo0 pte
+ PTE_L k1, PTESIZE(k1) # k1=lo1 pte
CLEAR_PTE_SWBITS(k0)
- MTC0 k0, MIPS_COP_0_TLB_LO0 # lo0 is loaded
+ PTE_MTC0 k0, MIPS_COP_0_TLB_LO0 # lo0 is loaded
COP0_SYNC
CLEAR_PTE_SWBITS(k1)
- MTC0 k1, MIPS_COP_0_TLB_LO1 # lo1 is loaded
+ PTE_MTC0 k1, MIPS_COP_0_TLB_LO1 # lo1 is loaded
COP0_SYNC
tlbwr # write to tlb
HAZARD_DELAY
diff --git a/sys/mips/mips/machdep.c b/sys/mips/mips/machdep.c
index 0b4468c..93b803b 100644
--- a/sys/mips/mips/machdep.c
+++ b/sys/mips/mips/machdep.c
@@ -205,8 +205,9 @@ cpu_startup(void *dummy)
vm_ksubmap_init(&kmi);
- printf("avail memory = %lu (%luMB)\n", ptoa(cnt.v_free_count),
- ptoa(cnt.v_free_count) / 1048576);
+ printf("avail memory = %ju (%juMB)\n",
+ ptoa((uintmax_t)cnt.v_free_count),
+ ptoa((uintmax_t)cnt.v_free_count) / 1048576);
cpu_init_interrupts();
/*
diff --git a/sys/mips/mips/pmap.c b/sys/mips/mips/pmap.c
index 3cf8246..8530c6e 100644
--- a/sys/mips/mips/pmap.c
+++ b/sys/mips/mips/pmap.c
@@ -3151,7 +3151,7 @@ pmap_asid_alloc(pmap)
int
page_is_managed(vm_paddr_t pa)
{
- vm_offset_t pgnum = mips_btop(pa);
+ vm_offset_t pgnum = atop(pa);
if (pgnum >= first_page) {
vm_page_t m;
diff --git a/sys/mips/mips/swtch.S b/sys/mips/mips/swtch.S
index 80c0cab..9390e41 100644
--- a/sys/mips/mips/swtch.S
+++ b/sys/mips/mips/swtch.S
@@ -91,6 +91,7 @@
#define RESTORE_U_PCB_CONTEXT(reg, offs, base) \
REG_L reg, U_PCB_CONTEXT + (SZREG * offs) (base)
+
/*
* Setup for and return to user.
*/
@@ -284,8 +285,8 @@ blocked_loop:
PTR_LI s0, MIPS_KSEG2_START # If Uarea addr is below kseg2,
#endif
bltu v0, s0, sw2 # no need to insert in TLB.
- lw a1, TD_UPTE + 0(s7) # a1 = u. pte #0
- lw a2, TD_UPTE + 4(s7) # a2 = u. pte #1
+ PTE_L a1, TD_UPTE + 0(s7) # a1 = u. pte #0
+ PTE_L a2, TD_UPTE + PTESIZE(s7) # a2 = u. pte #1
/*
* Wiredown the USPACE of newproc in TLB entry#0. Check whether target
* USPACE is already in another place of TLB before that, and if so
@@ -306,8 +307,8 @@ blocked_loop:
sll s0, PAGE_SHIFT + 1
addu t1, s0
MTC0 t1, MIPS_COP_0_TLB_HI
- mtc0 zero, MIPS_COP_0_TLB_LO0
- mtc0 zero, MIPS_COP_0_TLB_LO1
+ PTE_MTC0 zero, MIPS_COP_0_TLB_LO0
+ PTE_MTC0 zero, MIPS_COP_0_TLB_LO1
HAZARD_DELAY
tlbwi
HAZARD_DELAY
@@ -317,9 +318,9 @@ entry0set:
/* SMP!! - Works only for unshared TLB case - i.e. no v-cpus */
mtc0 zero, MIPS_COP_0_TLB_INDEX # TLB entry #0
HAZARD_DELAY
- mtc0 a1, MIPS_COP_0_TLB_LO0 # upte[0]
+ PTE_MTC0 a1, MIPS_COP_0_TLB_LO0 # upte[0]
HAZARD_DELAY
- mtc0 a2, MIPS_COP_0_TLB_LO1 # upte[1]
+ PTE_MTC0 a2, MIPS_COP_0_TLB_LO1 # upte[1]
HAZARD_DELAY
tlbwi # set TLB entry #0
HAZARD_DELAY
diff --git a/sys/mips/rmi/xlr_machdep.c b/sys/mips/rmi/xlr_machdep.c
index 93d615d..dd1049a 100644
--- a/sys/mips/rmi/xlr_machdep.c
+++ b/sys/mips/rmi/xlr_machdep.c
@@ -365,6 +365,7 @@ xlr_mem_init(void)
dump_avail[0] = phys_avail[0];
dump_avail[1] = phys_avail[1];
} else {
+#if !defined(__mips_n64) && !defined(__mips_n32) /* !PHYSADDR_64_BIT */
/*
* In 32 bit physical address mode we cannot use
* mem > 0xffffffff
@@ -383,6 +384,7 @@ xlr_mem_init(void)
printf("Memory: start %#jx limited to 4GB\n",
(intmax_t)boot_map->physmem_map[i].addr);
}
+#endif /* !PHYSADDR_64_BIT */
phys_avail[j] = (vm_paddr_t)
boot_map->physmem_map[i].addr;
phys_avail[j + 1] = phys_avail[j] +
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