diff options
Diffstat (limited to 'sys/mips/rmi/msgring.cfg')
| -rw-r--r-- | sys/mips/rmi/msgring.cfg | 1182 |
1 files changed, 1182 insertions, 0 deletions
diff --git a/sys/mips/rmi/msgring.cfg b/sys/mips/rmi/msgring.cfg new file mode 100644 index 0000000..cf9ea54 --- /dev/null +++ b/sys/mips/rmi/msgring.cfg @@ -0,0 +1,1182 @@ +/*- + * Copyright (c) 2003-2009 RMI Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of RMI Corporation, nor the names of its contributors, + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * RMI_BSD */ +/* + * This file defines the message ring configuration for phoenix-8. It tries to allow + * many different point-point communications between the message stations on the message ring + * and as result is _not_ the best configuration for performance + * + * The message ring on phoenix family of processors connects the cpus, gmacs, xgmac/spi4, + * security engine and the general purpose DMA engines. It provides a high bandwidth, + * low latency communication links. On traditional processors, this communication goes through + * which inherently does not scale very well with increasing number of cpus. + * + * Message ring has an in-built flow control mechanism. Every agent/station on the ring has to + * have software configured credits to send messages to any agent. Every receiving agent on the + * ring has a 256 entry FIFO that can divided into "buckets". All addressing on the ring is + * in terms of buckets. There are a total 128 buckets on the ring. The total number of credits + * across all sending agents should not exceed the bucket size. + * + * Below are the receiving agents and the max number of buckets they can have + * CPU 0 : 8 buckets + * CPU 1 : 8 buckets + * CPU 2 : 8 buckets + * CPU 3 : 8 buckets + * CPU 4 : 8 buckets + * CPU 5 : 8 buckets + * CPU 6 : 8 buckets + * CPU 7 : 8 buckets + * + * XGMAC 0 / SPI4 0 + * TX : 16 buckets + * FREE : 2 buckets + * XGMAC 1 / SPI4 1 + * TX : 16 buckets + * FREE : 2 buckets + * + * GMAC : 8 buckets + * + * SEC : 8 buckets + * + * DMA : 8 buckets + * + * The bucket size of a bucket should be aligned to the bucket's starting index in that + * receiving station's FIFO. For example, if sizes of bucket0 and bucket1 of a station + * are 32 and 32, bucket2's size has to be 64. bucket size 0 is valid. + * + * The format of the file is pretty straight forward. Each bucket definition has the size + * and the list of sending agents to that bucket with the number of credits to send. + * + * Undefined buckets have a size of 0 and Tx stations have 0 credits to send to that bucket. + * + * Following are the currently supported bucket names + * cpu_0_0 + * cpu_0_1 + * cpu_0_2 + * cpu_0_3 + * cpu_0_4 + * cpu_0_5 + * cpu_0_6 + * cpu_0_7 + * + * cpu_1_0 + * cpu_1_1 + * cpu_1_2 + * cpu_1_3 + * cpu_1_4 + * cpu_1_5 + * cpu_1_6 + * cpu_1_7 + * + * cpu_2_0 + * cpu_2_1 + * cpu_2_2 + * cpu_2_3 + * cpu_2_4 + * cpu_2_5 + * cpu_2_6 + * cpu_2_7 + * + * cpu_3_0 + * cpu_3_1 + * cpu_3_2 + * cpu_3_3 + * cpu_3_4 + * cpu_3_5 + * cpu_3_6 + * cpu_3_7 + * + * cpu_4_0 + * cpu_4_1 + * cpu_4_2 + * cpu_4_3 + * cpu_4_4 + * cpu_4_5 + * cpu_4_6 + * cpu_4_7 + * + * cpu_5_0 + * cpu_5_1 + * cpu_5_2 + * cpu_5_3 + * cpu_5_4 + * cpu_5_5 + * cpu_5_6 + * cpu_5_7 + * + * cpu_6_0 + * cpu_6_1 + * cpu_6_2 + * cpu_6_3 + * cpu_6_4 + * cpu_6_5 + * cpu_6_6 + * cpu_6_7 + * + * cpu_7_0 + * cpu_7_1 + * cpu_7_2 + * cpu_7_3 + * cpu_7_4 + * cpu_7_5 + * cpu_7_6 + * cpu_7_7 + * + * xgs_0_tx_0 + * xgs_0_tx_1 + * xgs_0_tx_2 + * xgs_0_tx_3 + * xgs_0_tx_4 + * xgs_0_tx_5 + * xgs_0_tx_6 + * xgs_0_tx_7 + * xgs_0_tx_8 + * xgs_0_tx_9 + * xgs_0_tx_10 + * xgs_0_tx_11 + * xgs_0_tx_12 + * xgs_0_tx_13 + * xgs_0_tx_14 + * xgs_0_tx_15 + * + * xgs_1_tx_0 + * xgs_1_tx_1 + * xgs_1_tx_2 + * xgs_1_tx_3 + * xgs_1_tx_4 + * xgs_1_tx_5 + * xgs_1_tx_6 + * xgs_1_tx_7 + * xgs_1_tx_8 + * xgs_1_tx_9 + * xgs_1_tx_10 + * xgs_1_tx_11 + * xgs_1_tx_12 + * xgs_1_tx_13 + * xgs_1_tx_14 + * xgs_1_tx_15 + * + * gmac_rsvd_0 + * gmac_rfr_0 + * gmac_tx_0 + * gmac_tx_1 + * gmac_tx_2 + * gmac_tx_3 + * gmac_rsvd_1 + * gmac_rfr_1 + * + * xgs_0_rsvd + * xgs_0_rfr + * + * xgs_1_rsvd + * xgs_1_rfr + * + * sec_pipe_0 + * sec_pipe_1 + * sec_pipe_2 + * sec_pipe_3 + * sec_rsa + * + * Following are the currently supported Tx Agent/Station names + * + * tx_stn_cpu_0 + * tx_stn_cpu_1 + * tx_stn_cpu_2 + * tx_stn_cpu_3 + * tx_stn_cpu_4 + * tx_stn_cpu_5 + * tx_stn_cpu_6 + * tx_stn_cpu_7 + * + * tx_stn_xgs_0 + * tx_stn_xgs_1 + * + * tx_stn_gmac + * + * tx_stn_dma + * + * tx_stn_sec + * + * + * + */ + +/*************************************************************/ +// CPU_0 Message Station + +bucket "cpu_0_0" { + size 32; + "tx_stn_xgs_0" 8; + "tx_stn_xgs_1" 8; + "tx_stn_gmac" 8; + "tx_stn_sec" 8; +} +bucket "cpu_0_1" { + size 32; + "tx_stn_xgs_0" 8; + "tx_stn_xgs_1" 8; + "tx_stn_gmac" 8; + "tx_stn_sec" 8; +} +bucket "cpu_0_2" { + size 32; + "tx_stn_xgs_0" 8; + "tx_stn_xgs_1" 8; + "tx_stn_gmac" 8; + "tx_stn_sec" 8; +} +bucket "cpu_0_3" { + size 32; + "tx_stn_xgs_0" 8; + "tx_stn_xgs_1" 8; + "tx_stn_gmac" 8; + "tx_stn_sec" 8; +} +bucket "cpu_0_4" { + size 32; + "tx_stn_gmac" 16; + "tx_stn_xgs_0" 8; + "tx_stn_xgs_1" 8; +} +bucket "cpu_0_5" { + size 32; + "tx_stn_gmac" 16; + "tx_stn_xgs_0" 8; + "tx_stn_xgs_1" 8; +} +bucket "cpu_0_6" { + size 32; + "tx_stn_gmac" 16; + "tx_stn_xgs_0" 8; + "tx_stn_xgs_1" 8; +} +bucket "cpu_0_7" { + size 32; + "tx_stn_gmac" 16; + "tx_stn_xgs_0" 8; + "tx_stn_xgs_1" 8; +} + +/*************************************************************/ +// CPU_1 Message Station + +bucket "cpu_1_0" { + size 32; + "tx_stn_xgs_0" 8; + "tx_stn_xgs_1" 8; + "tx_stn_gmac" 8; + "tx_stn_sec" 8; +} +bucket "cpu_1_1" { + size 32; + "tx_stn_xgs_0" 8; + "tx_stn_xgs_1" 8; + "tx_stn_gmac" 8; + "tx_stn_sec" 8; +} +bucket "cpu_1_2" { + size 32; + "tx_stn_xgs_0" 8; + "tx_stn_xgs_1" 8; + "tx_stn_gmac" 8; + "tx_stn_sec" 8; +} +bucket "cpu_1_3" { + size 32; + "tx_stn_xgs_0" 8; + "tx_stn_xgs_1" 8; + "tx_stn_gmac" 8; + "tx_stn_sec" 4; + "tx_stn_cpu_0" 4; /* NEEDED BY RMIOS IPSEC */ +} +bucket "cpu_1_4" { + size 32; + "tx_stn_gmac" 16; + "tx_stn_xgs_0" 8; + "tx_stn_xgs_1" 8; +} +bucket "cpu_1_5" { + size 32; + "tx_stn_gmac" 16; + "tx_stn_xgs_0" 8; + "tx_stn_xgs_1" 8; +} +bucket "cpu_1_6" { + size 32; + "tx_stn_gmac" 16; + "tx_stn_xgs_0" 8; + "tx_stn_xgs_1" 8; +} +bucket "cpu_1_7" { + size 32; + "tx_stn_gmac" 16; + "tx_stn_xgs_0" 8; + "tx_stn_xgs_1" 8; +} + +/*************************************************************/ +// CPU_2 Message Station + +bucket "cpu_2_0" { + size 32; + "tx_stn_xgs_0" 8; + "tx_stn_xgs_1" 8; + "tx_stn_gmac" 8; + "tx_stn_sec" 8; +} +bucket "cpu_2_1" { + size 32; + "tx_stn_xgs_0" 8; + "tx_stn_xgs_1" 8; + "tx_stn_gmac" 8; + "tx_stn_sec" 8; +} +bucket "cpu_2_2" { + size 32; + "tx_stn_xgs_0" 8; + "tx_stn_xgs_1" 8; + "tx_stn_gmac" 8; + "tx_stn_sec" 8; +} +bucket "cpu_2_3" { + size 32; + "tx_stn_xgs_0" 8; + "tx_stn_xgs_1" 8; + "tx_stn_gmac" 8; + "tx_stn_sec" 8; +} +bucket "cpu_2_4" { + size 32; + "tx_stn_gmac" 16; + "tx_stn_xgs_0" 8; + "tx_stn_xgs_1" 8; +} +bucket "cpu_2_5" { + size 32; + "tx_stn_gmac" 16; + "tx_stn_xgs_0" 8; + "tx_stn_xgs_1" 8; +} +bucket "cpu_2_6" { + size 32; + "tx_stn_gmac" 16; + "tx_stn_xgs_0" 8; + "tx_stn_xgs_1" 8; +} +bucket "cpu_2_7" { + size 32; + "tx_stn_gmac" 16; + "tx_stn_xgs_0" 8; + "tx_stn_xgs_1" 8; +} + +/*************************************************************/ +// CPU_3 Message Station + +bucket "cpu_3_0" { + size 32; + "tx_stn_xgs_0" 8; + "tx_stn_xgs_1" 8; + "tx_stn_gmac" 8; + "tx_stn_sec" 8; +} +bucket "cpu_3_1" { + size 32; + "tx_stn_xgs_0" 8; + "tx_stn_xgs_1" 8; + "tx_stn_gmac" 8; + "tx_stn_sec" 8; +} +bucket "cpu_3_2" { + size 32; + "tx_stn_xgs_0" 8; + "tx_stn_xgs_1" 8; + "tx_stn_gmac" 8; + "tx_stn_sec" 8; +} +bucket "cpu_3_3" { + size 32; + "tx_stn_xgs_0" 8; + "tx_stn_xgs_1" 8; + "tx_stn_gmac" 8; + "tx_stn_sec" 8; +} +bucket "cpu_3_4" { + size 32; + "tx_stn_gmac" 16; + "tx_stn_xgs_0" 8; + "tx_stn_xgs_1" 8; +} +bucket "cpu_3_5" { + size 32; + "tx_stn_gmac" 16; + "tx_stn_xgs_0" 8; + "tx_stn_xgs_1" 8; +} +bucket "cpu_3_6" { + size 32; + "tx_stn_gmac" 16; + "tx_stn_xgs_0" 8; + "tx_stn_xgs_1" 8; +} +bucket "cpu_3_7" { + size 32; + "tx_stn_gmac" 16; + "tx_stn_xgs_0" 8; + "tx_stn_xgs_1" 8; +} + +/*************************************************************/ +// CPU_4 Message Station + +bucket "cpu_4_0" { + size 32; + "tx_stn_xgs_0" 8; + "tx_stn_xgs_1" 8; + "tx_stn_gmac" 8; + "tx_stn_sec" 8; +} +bucket "cpu_4_1" { + size 32; + "tx_stn_xgs_0" 8; + "tx_stn_xgs_1" 8; + "tx_stn_gmac" 8; + "tx_stn_sec" 8; +} +bucket "cpu_4_2" { + size 32; + "tx_stn_xgs_0" 8; + "tx_stn_xgs_1" 8; + "tx_stn_gmac" 8; + "tx_stn_sec" 8; +} +bucket "cpu_4_3" { + size 32; + "tx_stn_xgs_0" 8; + "tx_stn_xgs_1" 8; + "tx_stn_gmac" 8; + "tx_stn_sec" 8; +} +bucket "cpu_4_4" { + size 32; + "tx_stn_gmac" 16; + "tx_stn_xgs_0" 8; + "tx_stn_xgs_1" 8; +} +bucket "cpu_4_5" { + size 32; + "tx_stn_gmac" 16; + "tx_stn_xgs_0" 8; + "tx_stn_xgs_1" 8; +} +bucket "cpu_4_6" { + size 32; + "tx_stn_gmac" 16; + "tx_stn_xgs_0" 8; + "tx_stn_xgs_1" 8; +} +bucket "cpu_4_7" { + size 32; + "tx_stn_gmac" 16; + "tx_stn_xgs_0" 8; + "tx_stn_xgs_1" 8; +} + +/*************************************************************/ +// CPU_5 Message Station + +bucket "cpu_5_0" { + size 32; + "tx_stn_xgs_0" 8; + "tx_stn_xgs_1" 8; + "tx_stn_gmac" 8; + "tx_stn_sec" 8; +} +bucket "cpu_5_1" { + size 32; + "tx_stn_xgs_0" 8; + "tx_stn_xgs_1" 8; + "tx_stn_gmac" 8; + "tx_stn_sec" 8; +} +bucket "cpu_5_2" { + size 32; + "tx_stn_xgs_0" 8; + "tx_stn_xgs_1" 8; + "tx_stn_gmac" 8; + "tx_stn_sec" 8; +} +bucket "cpu_5_3" { + size 32; + "tx_stn_xgs_0" 8; + "tx_stn_xgs_1" 8; + "tx_stn_gmac" 8; + "tx_stn_sec" 8; +} +bucket "cpu_5_4" { + size 32; + "tx_stn_gmac" 16; + "tx_stn_xgs_0" 8; + "tx_stn_xgs_1" 8; +} +bucket "cpu_5_5" { + size 32; + "tx_stn_gmac" 16; + "tx_stn_xgs_0" 8; + "tx_stn_xgs_1" 8; +} +bucket "cpu_5_6" { + size 32; + "tx_stn_gmac" 16; + "tx_stn_xgs_0" 8; + "tx_stn_xgs_1" 8; +} +bucket "cpu_5_7" { + size 32; + "tx_stn_gmac" 16; + "tx_stn_xgs_0" 8; + "tx_stn_xgs_1" 8; +} + + +/*************************************************************/ +// CPU_6 Message Station + +bucket "cpu_6_0" { + size 32; + "tx_stn_xgs_0" 8; + "tx_stn_xgs_1" 8; + "tx_stn_gmac" 8; + "tx_stn_sec" 8; +} +bucket "cpu_6_1" { + size 32; + "tx_stn_xgs_0" 8; + "tx_stn_xgs_1" 8; + "tx_stn_gmac" 8; + "tx_stn_sec" 8; +} +bucket "cpu_6_2" { + size 32; + "tx_stn_xgs_0" 8; + "tx_stn_xgs_1" 8; + "tx_stn_gmac" 8; + "tx_stn_sec" 8; +} +bucket "cpu_6_3" { + size 32; + "tx_stn_xgs_0" 8; + "tx_stn_xgs_1" 8; + "tx_stn_gmac" 8; + "tx_stn_sec" 8; +} +bucket "cpu_6_4" { + size 32; + "tx_stn_gmac" 16; + "tx_stn_xgs_0" 8; + "tx_stn_xgs_1" 8; +} +bucket "cpu_6_5" { + size 32; + "tx_stn_gmac" 16; + "tx_stn_xgs_0" 8; + "tx_stn_xgs_1" 8; +} +bucket "cpu_6_6" { + size 32; + "tx_stn_gmac" 16; + "tx_stn_xgs_0" 8; + "tx_stn_xgs_1" 8; +} +bucket "cpu_6_7" { + size 32; + "tx_stn_gmac" 16; + "tx_stn_xgs_0" 8; + "tx_stn_xgs_1" 8; +} + + +/*************************************************************/ +// CPU_7 Message Station + +bucket "cpu_7_0" { + size 32; + "tx_stn_xgs_0" 8; + "tx_stn_xgs_1" 8; + "tx_stn_gmac" 8; + "tx_stn_sec" 8; +} +bucket "cpu_7_1" { + size 32; + "tx_stn_xgs_0" 8; + "tx_stn_xgs_1" 8; + "tx_stn_gmac" 8; + "tx_stn_sec" 8; +} +bucket "cpu_7_2" { + size 32; + "tx_stn_xgs_0" 8; + "tx_stn_xgs_1" 8; + "tx_stn_gmac" 8; + "tx_stn_sec" 8; +} +bucket "cpu_7_3" { + size 32; + "tx_stn_xgs_0" 8; + "tx_stn_xgs_1" 8; + "tx_stn_gmac" 8; + "tx_stn_sec" 8; +} +bucket "cpu_7_4" { + size 32; + "tx_stn_gmac" 16; + "tx_stn_xgs_0" 8; + "tx_stn_xgs_1" 8; +} +bucket "cpu_7_5" { + size 32; + "tx_stn_gmac" 16; + "tx_stn_xgs_0" 8; + "tx_stn_xgs_1" 8; +} +bucket "cpu_7_6" { + size 32; + "tx_stn_gmac" 16; + "tx_stn_xgs_0" 8; + "tx_stn_xgs_1" 8; +} +bucket "cpu_7_7" { + size 32; + "tx_stn_gmac" 16; + "tx_stn_xgs_0" 8; + "tx_stn_xgs_1" 8; +} + + +/*************************************************************/ +// GMAC Message Station + +bucket "gmac_rfr_0" { + size 32; + "tx_stn_cpu_0" 2; + "tx_stn_cpu_1" 2; + "tx_stn_cpu_2" 4; + "tx_stn_cpu_3" 4; + "tx_stn_cpu_4" 4; + "tx_stn_cpu_5" 4; + "tx_stn_cpu_6" 4; + "tx_stn_cpu_7" 4; + "tx_stn_gmac" 4; +} + +bucket "gmac_tx_0" { + size 32; + "tx_stn_cpu_0" 4; + "tx_stn_cpu_1" 4; + "tx_stn_cpu_2" 4; + "tx_stn_cpu_3" 4; + "tx_stn_cpu_4" 4; + "tx_stn_cpu_5" 4; + "tx_stn_cpu_6" 4; + "tx_stn_cpu_7" 4; +} + +bucket "gmac_tx_1" { + size 32; + "tx_stn_cpu_0" 4; + "tx_stn_cpu_1" 4; + "tx_stn_cpu_2" 4; + "tx_stn_cpu_3" 4; + "tx_stn_cpu_4" 4; + "tx_stn_cpu_5" 4; + "tx_stn_cpu_6" 4; + "tx_stn_cpu_7" 4; +} + +bucket "gmac_tx_2" { + size 32; + "tx_stn_cpu_0" 4; + "tx_stn_cpu_1" 4; + "tx_stn_cpu_2" 4; + "tx_stn_cpu_3" 4; + "tx_stn_cpu_4" 4; + "tx_stn_cpu_5" 4; + "tx_stn_cpu_6" 4; + "tx_stn_cpu_7" 4; +} + +bucket "gmac_tx_3" { + size 32; + "tx_stn_cpu_0" 4; + "tx_stn_cpu_1" 4; + "tx_stn_cpu_2" 4; + "tx_stn_cpu_3" 4; + "tx_stn_cpu_4" 4; + "tx_stn_cpu_5" 4; + "tx_stn_cpu_6" 4; + "tx_stn_cpu_7" 4; +} + +bucket "gmac_rfr_1" { + size 32; + "tx_stn_cpu_0" 2; + "tx_stn_cpu_1" 2; + "tx_stn_cpu_2" 4; + "tx_stn_cpu_3" 4; + "tx_stn_cpu_4" 4; + "tx_stn_cpu_5" 4; + "tx_stn_cpu_6" 4; + "tx_stn_cpu_7" 4; + "tx_stn_gmac" 4; +} +/*********************************************/ +// xgmac +bucket "xgs_0_rfr" { + size 32; + "tx_stn_cpu_0" 2; + "tx_stn_cpu_1" 2; + "tx_stn_cpu_2" 4; + "tx_stn_cpu_3" 4; + "tx_stn_cpu_4" 4; + "tx_stn_cpu_5" 4; + "tx_stn_cpu_6" 4; + "tx_stn_cpu_7" 4; + "tx_stn_xgs_0" 4; +} + +bucket "xgs_0_tx_0" { + size 32; + "tx_stn_cpu_0" 4; + "tx_stn_cpu_1" 4; + "tx_stn_cpu_2" 4; + "tx_stn_cpu_3" 4; + "tx_stn_cpu_4" 4; + "tx_stn_cpu_5" 4; + "tx_stn_cpu_6" 4; + "tx_stn_cpu_7" 4; +} + +bucket "xgs_0_tx_1" { + size 16; + "tx_stn_cpu_0" 2; + "tx_stn_cpu_1" 2; + "tx_stn_cpu_2" 2; + "tx_stn_cpu_3" 2; + "tx_stn_cpu_4" 2; + "tx_stn_cpu_5" 2; + "tx_stn_cpu_6" 2; + "tx_stn_cpu_7" 2; +} + +bucket "xgs_0_tx_2" { + size 16; + "tx_stn_cpu_0" 2; + "tx_stn_cpu_1" 2; + "tx_stn_cpu_2" 2; + "tx_stn_cpu_3" 2; + "tx_stn_cpu_4" 2; + "tx_stn_cpu_5" 2; + "tx_stn_cpu_6" 2; + "tx_stn_cpu_7" 2; +} + +bucket "xgs_0_tx_3" { + size 16; + "tx_stn_cpu_0" 2; + "tx_stn_cpu_1" 2; + "tx_stn_cpu_2" 2; + "tx_stn_cpu_3" 2; + "tx_stn_cpu_4" 2; + "tx_stn_cpu_5" 2; + "tx_stn_cpu_6" 2; + "tx_stn_cpu_7" 2; +} + +bucket "xgs_0_tx_4" { + size 16; + "tx_stn_cpu_0" 2; + "tx_stn_cpu_1" 2; + "tx_stn_cpu_2" 2; + "tx_stn_cpu_3" 2; + "tx_stn_cpu_4" 2; + "tx_stn_cpu_5" 2; + "tx_stn_cpu_6" 2; + "tx_stn_cpu_7" 2; +} +bucket "xgs_0_tx_5" { + size 16; + "tx_stn_cpu_0" 2; + "tx_stn_cpu_1" 2; + "tx_stn_cpu_2" 2; + "tx_stn_cpu_3" 2; + "tx_stn_cpu_4" 2; + "tx_stn_cpu_5" 2; + "tx_stn_cpu_6" 2; + "tx_stn_cpu_7" 2; +} + +bucket "xgs_0_tx_6" { + size 16; + "tx_stn_cpu_0" 2; + "tx_stn_cpu_1" 2; + "tx_stn_cpu_2" 2; + "tx_stn_cpu_3" 2; + "tx_stn_cpu_4" 2; + "tx_stn_cpu_5" 2; + "tx_stn_cpu_6" 2; + "tx_stn_cpu_7" 2; +} + +bucket "xgs_0_tx_7" { + size 16; + "tx_stn_cpu_0" 2; + "tx_stn_cpu_1" 2; + "tx_stn_cpu_2" 2; + "tx_stn_cpu_3" 2; + "tx_stn_cpu_4" 2; + "tx_stn_cpu_5" 2; + "tx_stn_cpu_6" 2; + "tx_stn_cpu_7" 2; +} + +bucket "xgs_0_tx_8" { + size 16; + "tx_stn_cpu_0" 2; + "tx_stn_cpu_1" 2; + "tx_stn_cpu_2" 2; + "tx_stn_cpu_3" 2; + "tx_stn_cpu_4" 2; + "tx_stn_cpu_5" 2; + "tx_stn_cpu_6" 2; + "tx_stn_cpu_7" 2; +} + +bucket "xgs_0_tx_9" { + size 16; + "tx_stn_cpu_0" 2; + "tx_stn_cpu_1" 2; + "tx_stn_cpu_2" 2; + "tx_stn_cpu_3" 2; + "tx_stn_cpu_4" 2; + "tx_stn_cpu_5" 2; + "tx_stn_cpu_6" 2; + "tx_stn_cpu_7" 2; +} + +bucket "xgs_0_tx_10" { + size 16; + "tx_stn_cpu_0" 2; + "tx_stn_cpu_1" 2; + "tx_stn_cpu_2" 2; + "tx_stn_cpu_3" 2; + "tx_stn_cpu_4" 2; + "tx_stn_cpu_5" 2; + "tx_stn_cpu_6" 2; + "tx_stn_cpu_7" 2; +} + + +bucket "xgs_0_tx_11" { + size 16; + "tx_stn_cpu_0" 2; + "tx_stn_cpu_1" 2; + "tx_stn_cpu_2" 2; + "tx_stn_cpu_3" 2; + "tx_stn_cpu_4" 2; + "tx_stn_cpu_5" 2; + "tx_stn_cpu_6" 2; + "tx_stn_cpu_7" 2; +} + +bucket "xgs_0_tx_12" { + size 16; + "tx_stn_cpu_0" 2; + "tx_stn_cpu_1" 2; + "tx_stn_cpu_2" 2; + "tx_stn_cpu_3" 2; + "tx_stn_cpu_4" 2; + "tx_stn_cpu_5" 2; + "tx_stn_cpu_6" 2; + "tx_stn_cpu_7" 2; +} + +bucket "xgs_0_tx_13" { + size 16; + "tx_stn_cpu_0" 2; + "tx_stn_cpu_1" 2; + "tx_stn_cpu_2" 2; + "tx_stn_cpu_3" 2; + "tx_stn_cpu_4" 2; + "tx_stn_cpu_5" 2; + "tx_stn_cpu_6" 2; + "tx_stn_cpu_7" 2; +} + +bucket "xgs_0_tx_14" { + size 16; + "tx_stn_cpu_0" 2; + "tx_stn_cpu_1" 2; + "tx_stn_cpu_2" 2; + "tx_stn_cpu_3" 2; + "tx_stn_cpu_4" 2; + "tx_stn_cpu_5" 2; + "tx_stn_cpu_6" 2; + "tx_stn_cpu_7" 2; +} + + +bucket "xgs_1_rfr" { + size 32; + "tx_stn_cpu_0" 2; + "tx_stn_cpu_1" 2; + "tx_stn_cpu_2" 4; + "tx_stn_cpu_3" 4; + "tx_stn_cpu_4" 4; + "tx_stn_cpu_5" 4; + "tx_stn_cpu_6" 4; + "tx_stn_cpu_7" 4; + "tx_stn_xgs_1" 4; +} + +bucket "xgs_1_tx_0" { + size 32; + "tx_stn_cpu_0" 4; + "tx_stn_cpu_1" 4; + "tx_stn_cpu_2" 4; + "tx_stn_cpu_3" 4; + "tx_stn_cpu_4" 4; + "tx_stn_cpu_5" 4; + "tx_stn_cpu_6" 4; + "tx_stn_cpu_7" 4; +} + + +bucket "xgs_1_tx_1" { + size 16; + "tx_stn_cpu_0" 2; + "tx_stn_cpu_1" 2; + "tx_stn_cpu_2" 2; + "tx_stn_cpu_3" 2; + "tx_stn_cpu_4" 2; + "tx_stn_cpu_5" 2; + "tx_stn_cpu_6" 2; + "tx_stn_cpu_7" 2; +} + +bucket "xgs_1_tx_2" { + size 16; + "tx_stn_cpu_0" 2; + "tx_stn_cpu_1" 2; + "tx_stn_cpu_2" 2; + "tx_stn_cpu_3" 2; + "tx_stn_cpu_4" 2; + "tx_stn_cpu_5" 2; + "tx_stn_cpu_6" 2; + "tx_stn_cpu_7" 2; +} + +bucket "xgs_1_tx_3" { + size 16; + "tx_stn_cpu_0" 2; + "tx_stn_cpu_1" 2; + "tx_stn_cpu_2" 2; + "tx_stn_cpu_3" 2; + "tx_stn_cpu_4" 2; + "tx_stn_cpu_5" 2; + "tx_stn_cpu_6" 2; + "tx_stn_cpu_7" 2; +} + +bucket "xgs_1_tx_4" { + size 16; + "tx_stn_cpu_0" 2; + "tx_stn_cpu_1" 2; + "tx_stn_cpu_2" 2; + "tx_stn_cpu_3" 2; + "tx_stn_cpu_4" 2; + "tx_stn_cpu_5" 2; + "tx_stn_cpu_6" 2; + "tx_stn_cpu_7" 2; +} + +bucket "xgs_1_tx_5" { + size 16; + "tx_stn_cpu_0" 2; + "tx_stn_cpu_1" 2; + "tx_stn_cpu_2" 2; + "tx_stn_cpu_3" 2; + "tx_stn_cpu_4" 2; + "tx_stn_cpu_5" 2; + "tx_stn_cpu_6" 2; + "tx_stn_cpu_7" 2; +} + +bucket "xgs_1_tx_6" { + size 16; + "tx_stn_cpu_0" 2; + "tx_stn_cpu_1" 2; + "tx_stn_cpu_2" 2; + "tx_stn_cpu_3" 2; + "tx_stn_cpu_4" 2; + "tx_stn_cpu_5" 2; + "tx_stn_cpu_6" 2; + "tx_stn_cpu_7" 2; +} + +bucket "xgs_1_tx_7" { + size 16; + "tx_stn_cpu_0" 2; + "tx_stn_cpu_1" 2; + "tx_stn_cpu_2" 2; + "tx_stn_cpu_3" 2; + "tx_stn_cpu_4" 2; + "tx_stn_cpu_5" 2; + "tx_stn_cpu_6" 2; + "tx_stn_cpu_7" 2; +} + + +bucket "xgs_1_tx_8" { + size 16; + "tx_stn_cpu_0" 2; + "tx_stn_cpu_1" 2; + "tx_stn_cpu_2" 2; + "tx_stn_cpu_3" 2; + "tx_stn_cpu_4" 2; + "tx_stn_cpu_5" 2; + "tx_stn_cpu_6" 2; + "tx_stn_cpu_7" 2; +} + + +bucket "xgs_1_tx_9" { + size 16; + "tx_stn_cpu_0" 2; + "tx_stn_cpu_1" 2; + "tx_stn_cpu_2" 2; + "tx_stn_cpu_3" 2; + "tx_stn_cpu_4" 2; + "tx_stn_cpu_5" 2; + "tx_stn_cpu_6" 2; + "tx_stn_cpu_7" 2; +} + + +bucket "xgs_1_tx_10" { + size 16; + "tx_stn_cpu_0" 2; + "tx_stn_cpu_1" 2; + "tx_stn_cpu_2" 2; + "tx_stn_cpu_3" 2; + "tx_stn_cpu_4" 2; + "tx_stn_cpu_5" 2; + "tx_stn_cpu_6" 2; + "tx_stn_cpu_7" 2; +} + +bucket "xgs_1_tx_11" { + size 16; + "tx_stn_cpu_0" 2; + "tx_stn_cpu_1" 2; + "tx_stn_cpu_2" 2; + "tx_stn_cpu_3" 2; + "tx_stn_cpu_4" 2; + "tx_stn_cpu_5" 2; + "tx_stn_cpu_6" 2; + "tx_stn_cpu_7" 2; +} + +bucket "xgs_1_tx_12" { + size 16; + "tx_stn_cpu_0" 2; + "tx_stn_cpu_1" 2; + "tx_stn_cpu_2" 2; + "tx_stn_cpu_3" 2; + "tx_stn_cpu_4" 2; + "tx_stn_cpu_5" 2; + "tx_stn_cpu_6" 2; + "tx_stn_cpu_7" 2; +} + +bucket "xgs_1_tx_13" { + size 16; + "tx_stn_cpu_0" 2; + "tx_stn_cpu_1" 2; + "tx_stn_cpu_2" 2; + "tx_stn_cpu_3" 2; + "tx_stn_cpu_4" 2; + "tx_stn_cpu_5" 2; + "tx_stn_cpu_6" 2; + "tx_stn_cpu_7" 2; +} + +bucket "xgs_1_tx_14" { + size 16; + "tx_stn_cpu_0" 2; + "tx_stn_cpu_1" 2; + "tx_stn_cpu_2" 2; + "tx_stn_cpu_3" 2; + "tx_stn_cpu_4" 2; + "tx_stn_cpu_5" 2; + "tx_stn_cpu_6" 2; + "tx_stn_cpu_7" 2; +} + + + + + + +/*************************************************************/ +// Security Message Station + +bucket "sec_pipe_0" { + size 128; + "tx_stn_cpu_0" 16; + "tx_stn_cpu_1" 16; + "tx_stn_cpu_2" 16; + "tx_stn_cpu_3" 16; + "tx_stn_cpu_4" 16; + "tx_stn_cpu_5" 16; + "tx_stn_cpu_6" 16; + "tx_stn_cpu_7" 16; +} + +bucket "sec_rsa" { + size 128; + "tx_stn_cpu_0" 16; + "tx_stn_cpu_1" 16; + "tx_stn_cpu_2" 16; + "tx_stn_cpu_3" 16; + "tx_stn_cpu_4" 16; + "tx_stn_cpu_5" 16; + "tx_stn_cpu_6" 16; + "tx_stn_cpu_7" 16; +} + |
