diff options
Diffstat (limited to 'sys/mips/rmi/board.h')
| -rw-r--r-- | sys/mips/rmi/board.h | 96 |
1 files changed, 61 insertions, 35 deletions
diff --git a/sys/mips/rmi/board.h b/sys/mips/rmi/board.h index 814eba1..62f7283 100644 --- a/sys/mips/rmi/board.h +++ b/sys/mips/rmi/board.h @@ -30,22 +30,22 @@ * $FreeBSD$ */ #ifndef _RMI_BOARD_H_ -#define _RMI_BOARD_H_ +#define _RMI_BOARD_H_ /* * Engineering boards have a major/minor number in their EEPROM to * identify their configuration */ -#define RMI_XLR_BOARD_ARIZONA_I 1 -#define RMI_XLR_BOARD_ARIZONA_II 2 -#define RMI_XLR_BOARD_ARIZONA_III 3 -#define RMI_XLR_BOARD_ARIZONA_IV 4 -#define RMI_XLR_BOARD_ARIZONA_V 5 -#define RMI_XLR_BOARD_ARIZONA_VI 6 -#define RMI_XLR_BOARD_ARIZONA_VII 7 -#define RMI_XLR_BOARD_ARIZONA_VIII 8 -#define RMI_XLR_BOARD_ARIZONA_XI 11 -#define RMI_XLR_BOARD_ARIZONA_XII 12 +#define RMI_XLR_BOARD_ARIZONA_I 1 +#define RMI_XLR_BOARD_ARIZONA_II 2 +#define RMI_XLR_BOARD_ARIZONA_III 3 +#define RMI_XLR_BOARD_ARIZONA_IV 4 +#define RMI_XLR_BOARD_ARIZONA_V 5 +#define RMI_XLR_BOARD_ARIZONA_VI 6 +#define RMI_XLR_BOARD_ARIZONA_VII 7 +#define RMI_XLR_BOARD_ARIZONA_VIII 8 +#define RMI_XLR_BOARD_ARIZONA_XI 11 +#define RMI_XLR_BOARD_ARIZONA_XII 12 /* * RMI Chips - Values in Processor ID field @@ -55,24 +55,39 @@ #define RMI_CHIP_XLR308 0x06 #define RMI_CHIP_XLR532 0x09 -#define RMI_CHIP_XLS616_B0 0x40 -#define RMI_CHIP_XLS608_B0 0x4a -#define RMI_CHIP_XLS608 0x80 /* Internal */ -#define RMI_CHIP_XLS416_B0 0x44 -#define RMI_CHIP_XLS412_B0 0x4c -#define RMI_CHIP_XLS408_B0 0x4e -#define RMI_CHIP_XLS408 0x88 /* Lite "Condor" */ -#define RMI_CHIP_XLS404_B0 0x4f -#define RMI_CHIP_XLS404 0x8c /* Lite "Condor" */ -#define RMI_CHIP_XLS208 0x8e -#define RMI_CHIP_XLS204 0x8f -#define RMI_CHIP_XLS108 0xce -#define RMI_CHIP_XLS104 0xcf +/* + * XLR C revisions + */ +#define RMI_CHIP_XLR308_C 0x0F +#define RMI_CHIP_XLR508_C 0x0b +#define RMI_CHIP_XLR516_C 0x0a +#define RMI_CHIP_XLR532_C 0x08 + +/* + * XLS processors + */ +#define RMI_CHIP_XLS408 0x88 /* Lite "Condor" */ +#define RMI_CHIP_XLS608 0x80 /* Internal */ +#define RMI_CHIP_XLS404 0x8c /* Lite "Condor" */ +#define RMI_CHIP_XLS208 0x8e +#define RMI_CHIP_XLS204 0x8f +#define RMI_CHIP_XLS108 0xce +#define RMI_CHIP_XLS104 0xcf + +/* + * XLS B revision chips + */ +#define RMI_CHIP_XLS616_B0 0x40 +#define RMI_CHIP_XLS608_B0 0x4a +#define RMI_CHIP_XLS416_B0 0x44 +#define RMI_CHIP_XLS412_B0 0x4c +#define RMI_CHIP_XLS408_B0 0x4e +#define RMI_CHIP_XLS404_B0 0x4f /* * The XLS product line has chip versions 0x4x and 0x8x */ -static __inline__ unsigned int +static __inline unsigned int xlr_is_xls(void) { uint32_t prid = mips_rd_prid(); @@ -84,18 +99,20 @@ xlr_is_xls(void) /* * The last byte of the processor id field is revision */ -static __inline__ unsigned int +static __inline unsigned int xlr_revision(void) { - return mips_rd_prid() & 0xff; + + return (mips_rd_prid() & 0xff); } /* * The 15:8 byte of the PR Id register is the Processor ID */ -static __inline__ unsigned int +static __inline unsigned int xlr_processor_id(void) { + return ((mips_rd_prid() & 0xff00) >> 8); } @@ -103,14 +120,15 @@ xlr_processor_id(void) * RMI Engineering boards which are PCI cards * These should come up in PCI device mode (not yet) */ -static __inline__ int +static __inline int xlr_board_pci(int board_major) { + return ((board_major == RMI_XLR_BOARD_ARIZONA_III) || (board_major == RMI_XLR_BOARD_ARIZONA_V)); } -static __inline__ int +static __inline int xlr_is_xls1xx(void) { uint32_t chipid = xlr_processor_id(); @@ -118,7 +136,7 @@ xlr_is_xls1xx(void) return (chipid == 0xce || chipid == 0xcf); } -static __inline__ int +static __inline int xlr_is_xls2xx(void) { uint32_t chipid = xlr_processor_id(); @@ -126,16 +144,24 @@ xlr_is_xls2xx(void) return (chipid == 0x8e || chipid == 0x8f); } -static __inline__ int +static __inline int xlr_is_xls4xx_lite(void) { uint32_t chipid = xlr_processor_id(); return (chipid == 0x88 || chipid == 0x8c); - } - +} + +static __inline unsigned int +xlr_is_xls_b0(void) +{ + uint32_t chipid = xlr_processor_id(); + + return (chipid >= 0x40 && chipid <= 0x4f); +} + /* SPI-4 --> 8 ports, 1G MAC --> 4 ports and 10G MAC --> 1 port */ -#define MAX_NA_PORTS 8 +#define MAX_NA_PORTS 8 /* all our knowledge of chip and board that cannot be detected run-time goes here */ enum gmac_block_types { XLR_GMAC, XLR_XGMAC, XLR_SPI4}; |
