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Diffstat (limited to 'sys/mips/nlm/hal/bridge.h')
| -rw-r--r-- | sys/mips/nlm/hal/bridge.h | 177 |
1 files changed, 177 insertions, 0 deletions
diff --git a/sys/mips/nlm/hal/bridge.h b/sys/mips/nlm/hal/bridge.h new file mode 100644 index 0000000..d91ccd6 --- /dev/null +++ b/sys/mips/nlm/hal/bridge.h @@ -0,0 +1,177 @@ +/*- + * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights + * reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * + * $FreeBSD$ + * NETLOGIC_BSD */ + +#ifndef __NLM_BRIDGE_H__ +#define __NLM_BRIDGE_H__ + +/** +* @file_name mio.h +* @author Netlogic Microsystems +* @brief Basic definitions of XLP memory and io subsystem +*/ + +/* BRIDGE specific registers */ +#define XLP_BRIDGE_MODE_REG 0x40 +#define XLP_BRIDGE_PCI_CFG_BASE_REG 0x41 +#define XLP_BRIDGE_PCI_CFG_LIMIT_REG 0x42 +#define XLP_BRIDGE_PCIE_CFG_BASE_REG 0x43 +#define XLP_BRIDGE_PCIE_CFG_LIMIT_REG 0x44 +#define XLP_BRIDGE_BUSNUM_BAR0_REG 0x45 +#define XLP_BRIDGE_BUSNUM_BAR1_REG 0x46 +#define XLP_BRIDGE_BUSNUM_BAR2_REG 0x47 +#define XLP_BRIDGE_BUSNUM_BAR3_REG 0x48 +#define XLP_BRIDGE_BUSNUM_BAR4_REG 0x49 +#define XLP_BRIDGE_BUSNUM_BAR5_REG 0x4a +#define XLP_BRIDGE_BUSNUM_BAR6_REG 0x4b +#define XLP_BRIDGE_FLASH_BAR0_REG 0x4c +#define XLP_BRIDGE_FLASH_BAR1_REG 0x4d +#define XLP_BRIDGE_FLASH_BAR2_REG 0x4e +#define XLP_BRIDGE_FLASH_BAR3_REG 0x4f +#define XLP_BRIDGE_FLASH_LIMIT0_REG 0x50 +#define XLP_BRIDGE_FLASH_LIMIT1_REG 0x51 +#define XLP_BRIDGE_FLASH_LIMIT2_REG 0x52 +#define XLP_BRIDGE_FLASH_LIMIT3_REG 0x53 + +#define XLP_BRIDGE_DRAM_BAR_REG(i) (0x54 + (i)) +#define XLP_BRIDGE_DRAM_BAR0_REG 0x54 +#define XLP_BRIDGE_DRAM_BAR1_REG 0x55 +#define XLP_BRIDGE_DRAM_BAR2_REG 0x56 +#define XLP_BRIDGE_DRAM_BAR3_REG 0x57 +#define XLP_BRIDGE_DRAM_BAR4_REG 0x58 +#define XLP_BRIDGE_DRAM_BAR5_REG 0x59 +#define XLP_BRIDGE_DRAM_BAR6_REG 0x5a +#define XLP_BRIDGE_DRAM_BAR7_REG 0x5b + +#define XLP_BRIDGE_DRAM_LIMIT_REG(i) (0x5c + (i)) +#define XLP_BRIDGE_DRAM_LIMIT0_REG 0x5c +#define XLP_BRIDGE_DRAM_LIMIT1_REG 0x5d +#define XLP_BRIDGE_DRAM_LIMIT2_REG 0x5e +#define XLP_BRIDGE_DRAM_LIMIT3_REG 0x5f +#define XLP_BRIDGE_DRAM_LIMIT4_REG 0x60 +#define XLP_BRIDGE_DRAM_LIMIT5_REG 0x61 +#define XLP_BRIDGE_DRAM_LIMIT6_REG 0x62 +#define XLP_BRIDGE_DRAM_LIMIT7_REG 0x63 + +#define XLP_BRIDGE_DRAM_NODE_TRANSLN0_REG 0x64 +#define XLP_BRIDGE_DRAM_NODE_TRANSLN1_REG 0x65 +#define XLP_BRIDGE_DRAM_NODE_TRANSLN2_REG 0x66 +#define XLP_BRIDGE_DRAM_NODE_TRANSLN3_REG 0x67 +#define XLP_BRIDGE_DRAM_NODE_TRANSLN4_REG 0x68 +#define XLP_BRIDGE_DRAM_NODE_TRANSLN5_REG 0x69 +#define XLP_BRIDGE_DRAM_NODE_TRANSLN6_REG 0x6a +#define XLP_BRIDGE_DRAM_NODE_TRANSLN7_REG 0x6b +#define XLP_BRIDGE_DRAM_CHNL_TRANSLN0_REG 0x6c +#define XLP_BRIDGE_DRAM_CHNL_TRANSLN1_REG 0x6d +#define XLP_BRIDGE_DRAM_CHNL_TRANSLN2_REG 0x6e +#define XLP_BRIDGE_DRAM_CHNL_TRANSLN3_REG 0x6f +#define XLP_BRIDGE_DRAM_CHNL_TRANSLN4_REG 0x70 +#define XLP_BRIDGE_DRAM_CHNL_TRANSLN5_REG 0x71 +#define XLP_BRIDGE_DRAM_CHNL_TRANSLN6_REG 0x72 +#define XLP_BRIDGE_DRAM_CHNL_TRANSLN7_REG 0x73 +#define XLP_BRIDGE_PCIEMEM_BASE0_REG 0x74 +#define XLP_BRIDGE_PCIEMEM_BASE1_REG 0x75 +#define XLP_BRIDGE_PCIEMEM_BASE2_REG 0x76 +#define XLP_BRIDGE_PCIEMEM_BASE3_REG 0x77 +#define XLP_BRIDGE_PCIEMEM_LIMIT0_REG 0x78 +#define XLP_BRIDGE_PCIEMEM_LIMIT1_REG 0x79 +#define XLP_BRIDGE_PCIEMEM_LIMIT2_REG 0x7a +#define XLP_BRIDGE_PCIEMEM_LIMIT3_REG 0x7b +#define XLP_BRIDGE_PCIEIO_BASE0_REG 0x7c +#define XLP_BRIDGE_PCIEIO_BASE1_REG 0x7d +#define XLP_BRIDGE_PCIEIO_BASE2_REG 0x7e +#define XLP_BRIDGE_PCIEIO_BASE3_REG 0x7f +#define XLP_BRIDGE_PCIEIO_LIMIT0_REG 0x80 +#define XLP_BRIDGE_PCIEIO_LIMIT1_REG 0x81 +#define XLP_BRIDGE_PCIEIO_LIMIT2_REG 0x82 +#define XLP_BRIDGE_PCIEIO_LIMIT3_REG 0x83 +#define XLP_BRIDGE_PCIEMEM_BASE4_REG 0x84 +#define XLP_BRIDGE_PCIEMEM_BASE5_REG 0x85 +#define XLP_BRIDGE_PCIEMEM_BASE6_REG 0x86 +#define XLP_BRIDGE_PCIEMEM_LIMIT4_REG 0x87 +#define XLP_BRIDGE_PCIEMEM_LIMIT5_REG 0x88 +#define XLP_BRIDGE_PCIEMEM_LIMIT6_REG 0x89 +#define XLP_BRIDGE_PCIEIO_BASE4_REG 0x8a +#define XLP_BRIDGE_PCIEIO_BASE5_REG 0x8b +#define XLP_BRIDGE_PCIEIO_BASE6_REG 0x8c +#define XLP_BRIDGE_PCIEIO_LIMIT4_REG 0x8d +#define XLP_BRIDGE_PCIEIO_LIMIT5_REG 0x8e +#define XLP_BRIDGE_PCIEIO_LIMIT6_REG 0x8f +#define XLP_BRIDGE_NBU_EVENT_CNT_CTL_REG 0x90 +#define XLP_BRIDGE_EVNTCTR1_LOW_REG 0x91 +#define XLP_BRIDGE_EVNTCTR1_HI_REG 0x92 +#define XLP_BRIDGE_EVNT_CNT_CTL2_REG 0x93 +#define XLP_BRIDGE_EVNTCTR2_LOW_REG 0x94 +#define XLP_BRIDGE_EVNTCTR2_HI_REG 0x95 +#define XLP_BRIDGE_TRACEBUF_MATCH_REG0 0x96 +#define XLP_BRIDGE_TRACEBUF_MATCH_REG1 0x97 +#define XLP_BRIDGE_TRACEBUF_MATCH_LOW_REG 0x98 +#define XLP_BRIDGE_TRACEBUF_MATCH_HI_REG 0x99 +#define XLP_BRIDGE_TRACEBUF_CTRL_REG 0x9a +#define XLP_BRIDGE_TRACEBUF_INIT_REG 0x9b +#define XLP_BRIDGE_TRACEBUF_ACCESS_REG 0x9c +#define XLP_BRIDGE_TRACEBUF_READ_DATA_REG0 0x9d +#define XLP_BRIDGE_TRACEBUF_READ_DATA_REG1 0x9d +#define XLP_BRIDGE_TRACEBUF_READ_DATA_REG2 0x9f +#define XLP_BRIDGE_TRACEBUF_READ_DATA_REG3 0xa0 +#define XLP_BRIDGE_TRACEBUF_STATUS_REG 0xa1 +#define XLP_BRIDGE_ADDRESS_ERROR0_REG 0xa2 +#define XLP_BRIDGE_ADDRESS_ERROR1_REG 0xa3 +#define XLP_BRIDGE_ADDRESS_ERROR2_REG 0xa4 +#define XLP_BRIDGE_TAG_ECC_ADDR_ERROR0_REG 0xa5 +#define XLP_BRIDGE_TAG_ECC_ADDR_ERROR1_REG 0xa6 +#define XLP_BRIDGE_TAG_ECC_ADDR_ERROR2_REG 0xa7 +#define XLP_BRIDGE_LINE_FLUSH_REG0 0xa8 +#define XLP_BRIDGE_LINE_FLUSH_REG1 0xa9 +#define XLP_BRIDGE_NODE_ID_REG 0xaa +#define XLP_BRIDGE_ERROR_INTERRUPT_EN_REG 0xab +#define XLP_BRIDGE_PCIE0_WEIGHT_REG 0x300 +#define XLP_BRIDGE_PCIE1_WEIGHT_REG 0x301 +#define XLP_BRIDGE_PCIE2_WEIGHT_REG 0x302 +#define XLP_BRIDGE_PCIE3_WEIGHT_REG 0x303 +#define XLP_BRIDGE_USB_WEIGHT_REG 0x304 +#define XLP_BRIDGE_NET_WEIGHT_REG 0x305 +#define XLP_BRIDGE_POE_WEIGHT_REG 0x306 +#define XLP_BRIDGE_CMS_WEIGHT_REG 0x307 +#define XLP_BRIDGE_DMAENG_WEIGHT_REG 0x308 +#define XLP_BRIDGE_SEC_WEIGHT_REG 0x309 +#define XLP_BRIDGE_COMP_WEIGHT_REG 0x30a +#define XLP_BRIDGE_GIO_WEIGHT_REG 0x30b +#define XLP_BRIDGE_FLASH_WEIGHT_REG 0x30c + +#if !defined(LOCORE) && !defined(__ASSEMBLY__) + +#define nlm_rdreg_bridge(b, r) nlm_read_reg_kseg(b, r) +#define nlm_wreg_bridge(b, r, v) nlm_write_reg_kseg(b, r, v) +#define nlm_pcibase_bridge(node) nlm_pcicfg_base(XLP_IO_BRIDGE_OFFSET(node)) +#define nlm_regbase_bridge(node) nlm_pcibase_bridge(node) + +#endif + +#endif |
