diff options
Diffstat (limited to 'sys/mips/include')
| -rw-r--r-- | sys/mips/include/cpufunc.h | 3 | ||||
| -rw-r--r-- | sys/mips/include/cpuinfo.h | 1 | ||||
| -rw-r--r-- | sys/mips/include/cpuregs.h | 13 | ||||
| -rw-r--r-- | sys/mips/include/ofw_machdep.h | 3 | ||||
| -rw-r--r-- | sys/mips/include/pte.h | 13 |
5 files changed, 28 insertions, 5 deletions
diff --git a/sys/mips/include/cpufunc.h b/sys/mips/include/cpufunc.h index d47f9aa..6ffb0ba 100644 --- a/sys/mips/include/cpufunc.h +++ b/sys/mips/include/cpufunc.h @@ -248,7 +248,7 @@ MIPS_RW32_COP0_SEL(config5, MIPS_COP_0_CONFIG, 5); #if defined(CPU_NLM) || defined(BERI_LARGE_TLB) MIPS_RW32_COP0_SEL(config6, MIPS_COP_0_CONFIG, 6); #endif -#ifdef CPU_NLM +#if defined(CPU_NLM) || defined(CPU_MIPS1004KC) MIPS_RW32_COP0_SEL(config7, MIPS_COP_0_CONFIG, 7); #endif MIPS_RW32_COP0(count, MIPS_COP_0_COUNT); @@ -259,6 +259,7 @@ MIPS_RW32_COP0(cause, MIPS_COP_0_CAUSE); MIPS_RW32_COP0(excpc, MIPS_COP_0_EXC_PC); #endif MIPS_RW32_COP0(status, MIPS_COP_0_STATUS); +MIPS_RW32_COP0_SEL(cmgcrbase, 15, 3); /* XXX: Some of these registers are specific to MIPS32. */ #if !defined(__mips_n64) diff --git a/sys/mips/include/cpuinfo.h b/sys/mips/include/cpuinfo.h index baf3039..deeb93b 100644 --- a/sys/mips/include/cpuinfo.h +++ b/sys/mips/include/cpuinfo.h @@ -54,6 +54,7 @@ struct mips_cpuinfo { u_int8_t cpu_rev; u_int8_t cpu_impl; u_int8_t tlb_type; + u_int32_t tlb_pgmask; u_int16_t tlb_nentries; u_int8_t icache_virtual; boolean_t cache_coherent_dma; diff --git a/sys/mips/include/cpuregs.h b/sys/mips/include/cpuregs.h index a39f6a6..976321a 100644 --- a/sys/mips/include/cpuregs.h +++ b/sys/mips/include/cpuregs.h @@ -154,6 +154,11 @@ #define MIPS_CCA_CACHED 0x03 #endif +#if defined(CPU_MIPS1004KC) +#define MIPS_CCA_UNCACHED 0x02 +#define MIPS_CCA_CACHED 0x05 +#endif + #ifndef MIPS_CCA_UNCACHED #define MIPS_CCA_UNCACHED MIPS_CCA_UC #endif @@ -209,7 +214,7 @@ #define COP0_SYNC .word 0xc0 /* ehb */ #elif defined(CPU_SB1) #define COP0_SYNC ssnop; ssnop; ssnop; ssnop; ssnop; ssnop; ssnop; ssnop; ssnop -#elif defined(CPU_MIPS74KC) +#elif defined(CPU_MIPS74KC) || defined(CPU_MIPS1004KC) #define COP0_SYNC .word 0xc0 /* ehb */ #else /* @@ -557,6 +562,8 @@ #define MIPS_CONFIG2_SS_SHIFT 8 /* Secondary cache sets per way */ #define MIPS_CONFIG2_SS_MASK 0xf +#define MIPS_CONFIG3_CMGCR_MASK (1 << 29) /* Coherence manager present */ + #define MIPS_CONFIG4_MMUSIZEEXT 0x000000FF /* bits 7.. 0 MMU Size Extension */ #define MIPS_CONFIG4_MMUEXTDEF 0x0000C000 /* bits 15.14 MMU Extension Definition */ #define MIPS_CONFIG4_MMUEXTDEF_MMUSIZEEXT 0x00004000 /* This values denotes CONFIG4 bits */ @@ -634,4 +641,8 @@ #define MIPS_OPCODE_SHIFT 26 #define MIPS_OPCODE_C1 0x11 +/* Coherence manager constants */ +#define MIPS_CMGCRB_BASE 11 +#define MIPS_CMGCRF_BASE (~((1 << MIPS_CMGCRB_BASE) - 1)) + #endif /* _MIPS_CPUREGS_H_ */ diff --git a/sys/mips/include/ofw_machdep.h b/sys/mips/include/ofw_machdep.h index 35afce1..f14cfdf 100644 --- a/sys/mips/include/ofw_machdep.h +++ b/sys/mips/include/ofw_machdep.h @@ -32,7 +32,6 @@ #include <sys/types.h> #include <sys/rman.h> #include <sys/bus.h> -#include <dev/ofw/openfirm.h> typedef uint32_t cell_t; struct mem_region { @@ -40,8 +39,6 @@ struct mem_region { vm_size_t mr_size; }; - -int OF_decode_addr(phandle_t, int, bus_space_tag_t *, bus_space_handle_t *); void OF_getetheraddr(device_t dev, u_char *addr); void OF_initial_setup(void *fdt_ptr, void *junk, int (*openfirm)(void *)); diff --git a/sys/mips/include/pte.h b/sys/mips/include/pte.h index 2f2f995..4b628db 100644 --- a/sys/mips/include/pte.h +++ b/sys/mips/include/pte.h @@ -188,4 +188,17 @@ typedef pt_entry_t *pd_entry_t; #endif #endif /* LOCORE */ + +/* PageMask Register (CP0 Register 5, Select 0) Values */ +#define MIPS3_PGMASK_MASKX 0x00001800 +#define MIPS3_PGMASK_4K 0x00000000 +#define MIPS3_PGMASK_16K 0x00006000 +#define MIPS3_PGMASK_64K 0x0001e000 +#define MIPS3_PGMASK_256K 0x0007e000 +#define MIPS3_PGMASK_1M 0x001fe000 +#define MIPS3_PGMASK_4M 0x007fe000 +#define MIPS3_PGMASK_16M 0x01ffe000 +#define MIPS3_PGMASK_64M 0x07ffe000 +#define MIPS3_PGMASK_256M 0x1fffe000 + #endif /* !_MACHINE_PTE_H_ */ |
