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-rw-r--r--sys/dev/bge/if_bgereg.h8
-rw-r--r--sys/dev/gx/if_gxvar.h18
-rw-r--r--sys/dev/my/if_my.c4
-rw-r--r--sys/dev/nge/if_nge.c4
-rw-r--r--sys/dev/ppbus/ppb_msq.h42
-rw-r--r--sys/dev/sym/sym_defs.h4
-rw-r--r--sys/dev/ti/if_tireg.h14
-rw-r--r--sys/dev/twe/twe_compat.h8
8 files changed, 52 insertions, 50 deletions
diff --git a/sys/dev/bge/if_bgereg.h b/sys/dev/bge/if_bgereg.h
index b127f18..3dca979 100644
--- a/sys/dev/bge/if_bgereg.h
+++ b/sys/dev/bge/if_bgereg.h
@@ -2044,14 +2044,14 @@ struct vpd_key {
bus_space_read_4(sc->bge_btag, sc->bge_bhandle, reg)
#define BGE_SETBIT(sc, reg, x) \
- CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | x))
+ CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | (x)))
#define BGE_CLRBIT(sc, reg, x) \
- CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~x))
+ CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~(x)))
#define PCI_SETBIT(dev, reg, x, s) \
- pci_write_config(dev, reg, (pci_read_config(dev, reg, s) | x), s)
+ pci_write_config(dev, reg, (pci_read_config(dev, reg, s) | (x)), s)
#define PCI_CLRBIT(dev, reg, x, s) \
- pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~x), s)
+ pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~(x)), s)
/*
* Memory management stuff. Note: the SSLOTS, MSLOTS and JSLOTS
diff --git a/sys/dev/gx/if_gxvar.h b/sys/dev/gx/if_gxvar.h
index a6f7364..c70aa0c 100644
--- a/sys/dev/gx/if_gxvar.h
+++ b/sys/dev/gx/if_gxvar.h
@@ -53,22 +53,24 @@ struct mtx { int filler; };
/* CSR_WRITE_8 assumes the register is in low/high order */
#define CSR_WRITE_8(gx, reg, val) do { \
- bus_space_write_4(gx->gx_btag, gx->gx_bhandle, reg, val & 0xffffffff); \
- bus_space_write_4(gx->gx_btag, gx->gx_bhandle, reg + 4, val >> 32); \
+ bus_space_write_4((gx)->gx_btag, (gx)->gx_bhandle, \
+ reg, (val) & 0xffffffff); \
+ bus_space_write_4((gx)->gx_btag, (gx)->gx_bhandle, \
+ (reg) + 4, (val) >> 32); \
} while (0)
#define CSR_WRITE_4(gx, reg, val) \
- bus_space_write_4(gx->gx_btag, gx->gx_bhandle, reg, val)
+ bus_space_write_4((gx)->gx_btag, (gx)->gx_bhandle, reg, val)
#define CSR_WRITE_2(gx, reg, val) \
- bus_space_write_2(gx->gx_btag, gx->gx_bhandle, reg, val)
+ bus_space_write_2((gx)->gx_btag, (gx)->gx_bhandle, reg, val)
#define CSR_WRITE_1(gx, reg, val) \
- bus_space_write_1(gx->gx_btag, gx->gx_bhandle, reg, val)
+ bus_space_write_1((gx)->gx_btag, (gx)->gx_bhandle, reg, val)
#define CSR_READ_4(gx, reg) \
- bus_space_read_4(gx->gx_btag, gx->gx_bhandle, reg)
+ bus_space_read_4((gx)->gx_btag, (gx)->gx_bhandle, reg)
#define CSR_READ_2(gx, reg) \
- bus_space_read_2(gx->gx_btag, gx->gx_bhandle, reg)
+ bus_space_read_2((gx)->gx_btag, (gx)->gx_bhandle, reg)
#define CSR_READ_1(gx, reg) \
- bus_space_read_1(gx->gx_btag, gx->gx_bhandle, reg)
+ bus_space_read_1((gx)->gx_btag, (gx)->gx_bhandle, reg)
#define GX_SETBIT(gx, reg, x) \
CSR_WRITE_4(gx, reg, (CSR_READ_4(gx, reg) | (x)))
diff --git a/sys/dev/my/if_my.c b/sys/dev/my/if_my.c
index 6fedd54..5f10be7 100644
--- a/sys/dev/my/if_my.c
+++ b/sys/dev/my/if_my.c
@@ -148,8 +148,8 @@ static int my_list_rx_init(struct my_softc *);
static int my_list_tx_init(struct my_softc *);
static long my_send_cmd_to_phy(struct my_softc *, int, int);
-#define MY_SETBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x)
-#define MY_CLRBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x)
+#define MY_SETBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
+#define MY_CLRBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
static device_method_t my_methods[] = {
/* Device interface */
diff --git a/sys/dev/nge/if_nge.c b/sys/dev/nge/if_nge.c
index 98f43f3..b7af59a 100644
--- a/sys/dev/nge/if_nge.c
+++ b/sys/dev/nge/if_nge.c
@@ -238,10 +238,10 @@ DRIVER_MODULE(miibus, nge, miibus_driver, miibus_devclass, 0, 0);
CSR_READ_4(sc, reg) & ~(x))
#define SIO_SET(x) \
- CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) | x)
+ CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) | (x))
#define SIO_CLR(x) \
- CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) & ~x)
+ CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) & ~(x))
static void
nge_delay(sc)
diff --git a/sys/dev/ppbus/ppb_msq.h b/sys/dev/ppbus/ppb_msq.h
index 64d16d895..1ee55e5 100644
--- a/sys/dev/ppbus/ppb_msq.h
+++ b/sys/dev/ppbus/ppb_msq.h
@@ -106,53 +106,53 @@
*/
/* register operations */
-#define MS_RSET(reg,assert,clear) { MS_OP_RSET, {{ reg }, { assert }, { clear }}}
-#define MS_RASSERT(reg,byte) { MS_OP_RASSERT, { { reg }, { byte }}}
-#define MS_RCLR(reg,clear) { MS_OP_RSET, {{ reg }, { MS_ASSERT_NONE }, { clear }}}
+#define MS_RSET(reg,assert,clear) { MS_OP_RSET, {{ (reg) }, { (assert) }, { (clear) }}}
+#define MS_RASSERT(reg,byte) { MS_OP_RASSERT, { { (reg) }, { (byte) }}}
+#define MS_RCLR(reg,clear) { MS_OP_RSET, {{ (reg) }, { MS_ASSERT_NONE }, { (clear) }}}
-#define MS_RFETCH(reg,mask,ptr) { MS_OP_RFETCH, {{ reg }, { mask }, { ptr }}}
+#define MS_RFETCH(reg,mask,ptr) { MS_OP_RFETCH, {{ (reg) }, { (mask) }, { (ptr) }}}
/* trigger the port with array[char, delay,...] */
-#define MS_TRIG(reg,len,array) { MS_OP_TRIG, {{ reg }, { len }, { array }}}
+#define MS_TRIG(reg,len,array) { MS_OP_TRIG, {{ (reg) }, { (len) }, { (array) }}}
/* assert/fetch from/to ptr */
-#define MS_RASSERT_P(n,reg) { MS_OP_RASSERT_P, {{ n }, { reg }}}
-#define MS_RFETCH_P(n,reg,mask) { MS_OP_RFETCH_P, {{ n }, { reg }, { mask }}}
+#define MS_RASSERT_P(n,reg) { MS_OP_RASSERT_P, {{ (n) }, { (reg) }}}
+#define MS_RFETCH_P(n,reg,mask) { MS_OP_RFETCH_P, {{ (n) }, { (reg) }, { (mask) }}}
/* ptr manipulation */
-#define MS_PTR(ptr) { MS_OP_PTR, {{ ptr }}}
+#define MS_PTR(ptr) { MS_OP_PTR, {{ (ptr) }}}
#define MS_DASS(byte) MS_RASSERT(MS_REG_DTR,byte)
#define MS_SASS(byte) MS_RASSERT(MS_REG_STR,byte)
#define MS_CASS(byte) MS_RASSERT(MS_REG_CTR,byte)
-#define MS_SET(accum) { MS_OP_SET, {{ accum }}}
-#define MS_BRSET(mask,offset) { MS_OP_BRSET, {{ mask }, { offset }}}
-#define MS_DBRA(offset) { MS_OP_DBRA, {{ offset }}}
-#define MS_BRCLEAR(mask,offset) { MS_OP_BRCLEAR, {{ mask }, { offset }}}
+#define MS_SET(accum) { MS_OP_SET, {{ (accum) }}}
+#define MS_BRSET(mask,offset) { MS_OP_BRSET, {{ (mask) }, { (offset) }}}
+#define MS_DBRA(offset) { MS_OP_DBRA, {{ (offset) }}}
+#define MS_BRCLEAR(mask,offset) { MS_OP_BRCLEAR, {{ (mask) }, { (offset) }}}
#define MS_BRSTAT(mask_set,mask_clr,offset) \
- { MS_OP_BRSTAT, {{ mask_set }, { mask_clr }, { offset }}}
+ { MS_OP_BRSTAT, {{ mask_set }, { mask_clr }, { (offset) }}}
/* C function or submicrosequence call */
#define MS_C_CALL(function,parameter) \
- { MS_OP_C_CALL, {{ function }, { parameter }}}
-#define MS_CALL(microseq) { MS_OP_CALL, {{ microseq }}}
+ { MS_OP_C_CALL, {{ (function) }, { (parameter) }}}
+#define MS_CALL(microseq) { MS_OP_CALL, {{ (microseq) }}}
/* mode dependent read/write operations
* ppb_MS_xxx_init() call required otherwise default is
* IEEE1284 operating mode */
-#define MS_PUT(ptr,len) { MS_OP_PUT, {{ ptr }, { len }}}
-#define MS_GET(ptr,len) { MS_OP_GET, {{ ptr }, { len }}}
+#define MS_PUT(ptr,len) { MS_OP_PUT, {{ (ptr) }, { (len) }}}
+#define MS_GET(ptr,len) { MS_OP_GET, {{ (ptr) }, { (len) }}}
/* delay in microseconds */
-#define MS_DELAY(udelay) { MS_OP_DELAY, {{ udelay }}}
+#define MS_DELAY(udelay) { MS_OP_DELAY, {{ (udelay) }}}
/* asynchroneous delay in ms */
-#define MS_ADELAY(mdelay) { MS_OP_ADELAY, {{ mdelay }}}
+#define MS_ADELAY(mdelay) { MS_OP_ADELAY, {{ (mdelay) }}}
/* return from submicrosequence execution or microseqence execution */
-#define MS_SUBRET(code) { MS_OP_SUBRET, {{ code }}}
-#define MS_RET(code) { MS_OP_RET, {{ code }}}
+#define MS_SUBRET(code) { MS_OP_SUBRET, {{ (code) }}}
+#define MS_RET(code) { MS_OP_RET, {{ (code) }}}
/*
* Function abstraction level
diff --git a/sys/dev/sym/sym_defs.h b/sys/dev/sym/sym_defs.h
index 9fb976b..61caabd 100644
--- a/sys/dev/sym/sym_defs.h
+++ b/sys/dev/sym/sym_defs.h
@@ -798,10 +798,10 @@ struct sym_tblsel {
#define SCR_DSA_REL2 0x10000000
#define SCR_LOAD_R(reg, how, n) \
- (0xe1000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
+ (0xe1000000 | (how) | (SCR_REG_OFS2(REG(reg))) | (n))
#define SCR_STORE_R(reg, how, n) \
- (0xe0000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
+ (0xe0000000 | (how) | (SCR_REG_OFS2(REG(reg))) | (n))
#define SCR_LOAD_ABS(reg, n) SCR_LOAD_R(reg, SCR_NO_FLUSH2, n)
#define SCR_LOAD_REL(reg, n) SCR_LOAD_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2, n)
diff --git a/sys/dev/ti/if_tireg.h b/sys/dev/ti/if_tireg.h
index e1d56f8..b15b28b 100644
--- a/sys/dev/ti/if_tireg.h
+++ b/sys/dev/ti/if_tireg.h
@@ -807,16 +807,16 @@ struct ti_cmd_desc {
* that 'sc' and 'cmd' are in local scope.
*/
#define TI_DO_CMD(x, y, z) \
- cmd.ti_cmd = x; \
- cmd.ti_code = y; \
- cmd.ti_idx = z; \
+ cmd.ti_cmd = (x); \
+ cmd.ti_code = (y); \
+ cmd.ti_idx = (z); \
ti_cmd(sc, &cmd);
#define TI_DO_CMD_EXT(x, y, z, v, w) \
- cmd.ti_cmd = x; \
- cmd.ti_code = y; \
- cmd.ti_idx = z; \
- ti_cmd_ext(sc, &cmd, v, w);
+ cmd.ti_cmd = (x); \
+ cmd.ti_code = (y); \
+ cmd.ti_idx = (z); \
+ ti_cmd_ext(sc, &cmd, (v), (w));
/*
* Other utility macros.
diff --git a/sys/dev/twe/twe_compat.h b/sys/dev/twe/twe_compat.h
index ed82631..2dc17b5 100644
--- a/sys/dev/twe/twe_compat.h
+++ b/sys/dev/twe/twe_compat.h
@@ -95,10 +95,10 @@
/*
* Wrappers for bus-space actions
*/
-#define TWE_CONTROL(sc, val) bus_space_write_4(sc->twe_btag, sc->twe_bhandle, 0x0, (u_int32_t)val)
-#define TWE_STATUS(sc) (u_int32_t)bus_space_read_4(sc->twe_btag, sc->twe_bhandle, 0x4)
-#define TWE_COMMAND_QUEUE(sc, val) bus_space_write_4(sc->twe_btag, sc->twe_bhandle, 0x8, (u_int32_t)val)
-#define TWE_RESPONSE_QUEUE(sc) (TWE_Response_Queue)bus_space_read_4(sc->twe_btag, sc->twe_bhandle, 0xc)
+#define TWE_CONTROL(sc, val) bus_space_write_4((sc)->twe_btag, (sc)->twe_bhandle, 0x0, (u_int32_t)val)
+#define TWE_STATUS(sc) (u_int32_t)bus_space_read_4((sc)->twe_btag, (sc)->twe_bhandle, 0x4)
+#define TWE_COMMAND_QUEUE(sc, val) bus_space_write_4((sc)->twe_btag, (sc)->twe_bhandle, 0x8, (u_int32_t)val)
+#define TWE_RESPONSE_QUEUE(sc) (TWE_Response_Queue)bus_space_read_4((sc)->twe_btag, (sc)->twe_bhandle, 0xc)
/*
* FreeBSD-specific softc elements
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