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-rw-r--r--sys/dev/e1000/if_em.c53
-rw-r--r--sys/dev/e1000/if_igb.c66
-rw-r--r--sys/dev/gpioapu/gpioapu.c336
-rw-r--r--sys/dev/ichwd/ichwd.c473
-rw-r--r--sys/dev/ichwd/ichwd.h65
-rw-r--r--sys/dev/ixgbe/if_ix.c25
-rw-r--r--sys/dev/ixgbe/if_ixv.c3
-rw-r--r--sys/dev/ixgbe/ix_txrx.c7
-rw-r--r--sys/dev/ixgbe/ixgbe.h3
-rw-r--r--sys/dev/oce/oce_if.c11
-rw-r--r--sys/dev/random/hash.c6
-rw-r--r--sys/dev/random/hash.h6
-rw-r--r--sys/dev/usb/wlan/if_run.c1
-rw-r--r--sys/dev/usb/wlan/if_upgt.c2
-rw-r--r--sys/dev/virtio/network/if_vtnet.c26
-rw-r--r--sys/dev/vmware/vmxnet3/if_vmx.c24
16 files changed, 776 insertions, 331 deletions
diff --git a/sys/dev/e1000/if_em.c b/sys/dev/e1000/if_em.c
index 49e5abd..691292d 100644
--- a/sys/dev/e1000/if_em.c
+++ b/sys/dev/e1000/if_em.c
@@ -211,15 +211,15 @@ static int em_detach(device_t);
static int em_shutdown(device_t);
static int em_suspend(device_t);
static int em_resume(device_t);
-#ifdef EM_MULTIQUEUE
+
static int em_mq_start(struct ifnet *, struct mbuf *);
static int em_mq_start_locked(struct ifnet *,
struct tx_ring *);
static void em_qflush(struct ifnet *);
-#else
+
static void em_start(struct ifnet *);
static void em_start_locked(struct ifnet *, struct tx_ring *);
-#endif
+
static int em_ioctl(struct ifnet *, u_long, caddr_t);
static void em_init(void *);
static void em_init_locked(struct adapter *);
@@ -926,13 +926,13 @@ em_resume(device_t dev)
(ifp->if_drv_flags & IFF_DRV_RUNNING) && adapter->link_active) {
for (int i = 0; i < adapter->num_queues; i++, txr++) {
EM_TX_LOCK(txr);
-#ifdef EM_MULTIQUEUE
+
if (!drbr_empty(ifp, txr->br))
em_mq_start_locked(ifp, txr);
-#else
+
if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
em_start_locked(ifp, txr);
-#endif
+
EM_TX_UNLOCK(txr);
}
}
@@ -942,7 +942,7 @@ em_resume(device_t dev)
}
-#ifndef EM_MULTIQUEUE
+
static void
em_start_locked(struct ifnet *ifp, struct tx_ring *txr)
{
@@ -1005,7 +1005,7 @@ em_start(struct ifnet *ifp)
}
return;
}
-#else /* EM_MULTIQUEUE */
+
/*********************************************************************
* Multiqueue Transmit routines
*
@@ -1112,7 +1112,7 @@ em_qflush(struct ifnet *ifp)
}
if_qflush(ifp);
}
-#endif /* EM_MULTIQUEUE */
+
/*********************************************************************
* Ioctl entry point
@@ -1513,13 +1513,13 @@ em_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
EM_TX_LOCK(txr);
em_txeof(txr);
-#ifdef EM_MULTIQUEUE
+
if (!drbr_empty(ifp, txr->br))
em_mq_start_locked(ifp, txr);
-#else
+
if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
em_start_locked(ifp, txr);
-#endif
+
EM_TX_UNLOCK(txr);
return (rx_done);
@@ -1587,13 +1587,13 @@ em_handle_que(void *context, int pending)
EM_TX_LOCK(txr);
em_txeof(txr);
-#ifdef EM_MULTIQUEUE
+
if (!drbr_empty(ifp, txr->br))
em_mq_start_locked(ifp, txr);
-#else
+
if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
em_start_locked(ifp, txr);
-#endif
+
EM_TX_UNLOCK(txr);
if (more) {
taskqueue_enqueue(adapter->tq, &adapter->que_task);
@@ -1621,13 +1621,13 @@ em_msix_tx(void *arg)
++txr->tx_irq;
EM_TX_LOCK(txr);
em_txeof(txr);
-#ifdef EM_MULTIQUEUE
+
if (!drbr_empty(ifp, txr->br))
em_mq_start_locked(ifp, txr);
-#else
+
if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
em_start_locked(ifp, txr);
-#endif
+
/* Reenable this interrupt */
E1000_WRITE_REG(&adapter->hw, E1000_IMS, txr->ims);
@@ -1722,13 +1722,13 @@ em_handle_tx(void *context, int pending)
EM_TX_LOCK(txr);
em_txeof(txr);
-#ifdef EM_MULTIQUEUE
+
if (!drbr_empty(ifp, txr->br))
em_mq_start_locked(ifp, txr);
-#else
+
if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
em_start_locked(ifp, txr);
-#endif
+
E1000_WRITE_REG(&adapter->hw, E1000_IMS, txr->ims);
EM_TX_UNLOCK(txr);
}
@@ -1752,13 +1752,13 @@ em_handle_link(void *context, int pending)
if (adapter->link_active) {
for (int i = 0; i < adapter->num_queues; i++, txr++) {
EM_TX_LOCK(txr);
-#ifdef EM_MULTIQUEUE
+
if (!drbr_empty(ifp, txr->br))
em_mq_start_locked(ifp, txr);
-#else
+
if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
em_start_locked(ifp, txr);
-#endif
+
EM_TX_UNLOCK(txr);
}
}
@@ -3101,16 +3101,15 @@ em_setup_interface(device_t dev, struct adapter *adapter)
ifp->if_hw_tsomaxsegcount = EM_MAX_SCATTER;
ifp->if_hw_tsomaxsegsize = EM_TSO_SEG_SIZE;
-#ifdef EM_MULTIQUEUE
/* Multiqueue stack interface */
ifp->if_transmit = em_mq_start;
ifp->if_qflush = em_qflush;
-#else
+
ifp->if_start = em_start;
IFQ_SET_MAXLEN(&ifp->if_snd, adapter->num_tx_desc - 1);
ifp->if_snd.ifq_drv_maxlen = adapter->num_tx_desc - 1;
IFQ_SET_READY(&ifp->if_snd);
-#endif
+
ether_ifattach(ifp, adapter->hw.mac.addr);
diff --git a/sys/dev/e1000/if_igb.c b/sys/dev/e1000/if_igb.c
index 620fbad..4bb5b57 100644
--- a/sys/dev/e1000/if_igb.c
+++ b/sys/dev/e1000/if_igb.c
@@ -43,9 +43,7 @@
#include <sys/param.h>
#include <sys/systm.h>
-#ifndef IGB_LEGACY_TX
#include <sys/buf_ring.h>
-#endif
#include <sys/bus.h>
#include <sys/endian.h>
#include <sys/kernel.h>
@@ -189,15 +187,12 @@ static int igb_detach(device_t);
static int igb_shutdown(device_t);
static int igb_suspend(device_t);
static int igb_resume(device_t);
-#ifndef IGB_LEGACY_TX
static int igb_mq_start(struct ifnet *, struct mbuf *);
static int igb_mq_start_locked(struct ifnet *, struct tx_ring *);
static void igb_qflush(struct ifnet *);
static void igb_deferred_mq_start(void *, int);
-#else
static void igb_start(struct ifnet *);
static void igb_start_locked(struct tx_ring *, struct ifnet *ifp);
-#endif
static int igb_ioctl(struct ifnet *, u_long, caddr_t);
static void igb_init(void *);
static void igb_init_locked(struct adapter *);
@@ -361,7 +356,6 @@ TUNABLE_INT("hw.igb.max_interrupt_rate", &igb_max_interrupt_rate);
SYSCTL_INT(_hw_igb, OID_AUTO, max_interrupt_rate, CTLFLAG_RDTUN,
&igb_max_interrupt_rate, 0, "Maximum interrupts per second");
-#ifndef IGB_LEGACY_TX
/*
** Tuneable number of buffers in the buf-ring (drbr_xxx)
*/
@@ -369,7 +363,6 @@ static int igb_buf_ring_size = IGB_BR_SIZE;
TUNABLE_INT("hw.igb.buf_ring_size", &igb_buf_ring_size);
SYSCTL_INT(_hw_igb, OID_AUTO, buf_ring_size, CTLFLAG_RDTUN,
&igb_buf_ring_size, 0, "Size of the bufring");
-#endif
/*
** Header split causes the packet header to
@@ -876,15 +869,15 @@ igb_resume(device_t dev)
(ifp->if_drv_flags & IFF_DRV_RUNNING) && adapter->link_active) {
for (int i = 0; i < adapter->num_queues; i++, txr++) {
IGB_TX_LOCK(txr);
-#ifndef IGB_LEGACY_TX
+
/* Process the stack queue only if not depleted */
if (((txr->queue_status & IGB_QUEUE_DEPLETED) == 0) &&
!drbr_empty(ifp, txr->br))
igb_mq_start_locked(ifp, txr);
-#else
+
if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
igb_start_locked(txr, ifp);
-#endif
+
IGB_TX_UNLOCK(txr);
}
}
@@ -894,7 +887,6 @@ igb_resume(device_t dev)
}
-#ifdef IGB_LEGACY_TX
/*********************************************************************
* Transmit entry point
@@ -972,7 +964,6 @@ igb_start(struct ifnet *ifp)
return;
}
-#else /* ~IGB_LEGACY_TX */
/*
** Multiqueue Transmit Entry:
@@ -1092,7 +1083,6 @@ igb_qflush(struct ifnet *ifp)
}
if_qflush(ifp);
}
-#endif /* ~IGB_LEGACY_TX */
/*********************************************************************
* Ioctl entry point
@@ -1427,15 +1417,15 @@ igb_handle_que(void *context, int pending)
IGB_TX_LOCK(txr);
igb_txeof(txr);
-#ifndef IGB_LEGACY_TX
+
/* Process the stack queue only if not depleted */
if (((txr->queue_status & IGB_QUEUE_DEPLETED) == 0) &&
!drbr_empty(ifp, txr->br))
igb_mq_start_locked(ifp, txr);
-#else
+
if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
igb_start_locked(txr, ifp);
-#endif
+
IGB_TX_UNLOCK(txr);
/* Do we need another? */
if (more) {
@@ -1478,15 +1468,15 @@ igb_handle_link_locked(struct adapter *adapter)
if ((ifp->if_drv_flags & IFF_DRV_RUNNING) && adapter->link_active) {
for (int i = 0; i < adapter->num_queues; i++, txr++) {
IGB_TX_LOCK(txr);
-#ifndef IGB_LEGACY_TX
+
/* Process the stack queue only if not depleted */
if (((txr->queue_status & IGB_QUEUE_DEPLETED) == 0) &&
!drbr_empty(ifp, txr->br))
igb_mq_start_locked(ifp, txr);
-#else
+
if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
igb_start_locked(txr, ifp);
-#endif
+
IGB_TX_UNLOCK(txr);
}
}
@@ -1580,13 +1570,10 @@ igb_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
do {
more = igb_txeof(txr);
} while (loop-- && more);
-#ifndef IGB_LEGACY_TX
if (!drbr_empty(ifp, txr->br))
igb_mq_start_locked(ifp, txr);
-#else
if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
igb_start_locked(txr, ifp);
-#endif
IGB_TX_UNLOCK(txr);
}
@@ -1619,15 +1606,12 @@ igb_msix_que(void *arg)
IGB_TX_LOCK(txr);
igb_txeof(txr);
-#ifndef IGB_LEGACY_TX
/* Process the stack queue only if not depleted */
if (((txr->queue_status & IGB_QUEUE_DEPLETED) == 0) &&
!drbr_empty(ifp, txr->br))
igb_mq_start_locked(ifp, txr);
-#else
if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
igb_start_locked(txr, ifp);
-#endif
IGB_TX_UNLOCK(txr);
more_rx = igb_rxeof(que, adapter->rx_process_limit, NULL);
@@ -2390,9 +2374,7 @@ igb_allocate_legacy(struct adapter *adapter)
{
device_t dev = adapter->dev;
struct igb_queue *que = adapter->queues;
-#ifndef IGB_LEGACY_TX
struct tx_ring *txr = adapter->tx_rings;
-#endif
int error, rid = 0;
/* Turn off all interrupts */
@@ -2411,9 +2393,7 @@ igb_allocate_legacy(struct adapter *adapter)
return (ENXIO);
}
-#ifndef IGB_LEGACY_TX
TASK_INIT(&txr->txq_task, 0, igb_deferred_mq_start, txr);
-#endif
/*
* Try allocating a fast interrupt and the associated deferred
@@ -2495,10 +2475,8 @@ igb_allocate_msix(struct adapter *adapter)
i,igb_last_bind_cpu);
igb_last_bind_cpu = CPU_NEXT(igb_last_bind_cpu);
}
-#ifndef IGB_LEGACY_TX
TASK_INIT(&que->txr->txq_task, 0, igb_deferred_mq_start,
que->txr);
-#endif
/* Make tasklet for deferred handling */
TASK_INIT(&que->que_task, 0, igb_handle_que, que);
que->tq = taskqueue_create("igb_que", M_NOWAIT,
@@ -2722,9 +2700,9 @@ igb_free_pci_resources(struct adapter *adapter)
for (int i = 0; i < adapter->num_queues; i++, que++) {
if (que->tq != NULL) {
-#ifndef IGB_LEGACY_TX
+
taskqueue_drain(que->tq, &que->txr->txq_task);
-#endif
+
taskqueue_drain(que->tq, &que->que_task);
taskqueue_free(que->tq);
}
@@ -3125,15 +3103,15 @@ igb_setup_interface(device_t dev, struct adapter *adapter)
ifp->if_softc = adapter;
ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
ifp->if_ioctl = igb_ioctl;
-#ifndef IGB_LEGACY_TX
+
ifp->if_transmit = igb_mq_start;
ifp->if_qflush = igb_qflush;
-#else
+
ifp->if_start = igb_start;
IFQ_SET_MAXLEN(&ifp->if_snd, adapter->num_tx_desc - 1);
ifp->if_snd.ifq_drv_maxlen = adapter->num_tx_desc - 1;
IFQ_SET_READY(&ifp->if_snd);
-#endif
+
ether_ifattach(ifp, adapter->hw.mac.addr);
@@ -3372,11 +3350,11 @@ igb_allocate_queues(struct adapter *adapter)
error = ENOMEM;
goto err_tx_desc;
}
-#ifndef IGB_LEGACY_TX
+
/* Allocate a buf ring */
txr->br = buf_ring_alloc(igb_buf_ring_size, M_DEVBUF,
M_WAITOK, &txr->tx_mtx);
-#endif
+
}
/*
@@ -3433,9 +3411,9 @@ err_tx_desc:
igb_dma_free(adapter, &txr->txdma);
free(adapter->rx_rings, M_DEVBUF);
rx_fail:
-#ifndef IGB_LEGACY_TX
+
buf_ring_free(txr->br, M_DEVBUF);
-#endif
+
free(adapter->tx_rings, M_DEVBUF);
tx_fail:
free(adapter->queues, M_DEVBUF);
@@ -3691,10 +3669,10 @@ igb_free_transmit_buffers(struct tx_ring *txr)
tx_buffer->map = NULL;
}
}
-#ifndef IGB_LEGACY_TX
+
if (txr->br != NULL)
buf_ring_free(txr->br, M_DEVBUF);
-#endif
+
if (txr->tx_buffers != NULL) {
free(txr->tx_buffers, M_DEVBUF);
txr->tx_buffers = NULL;
@@ -5000,10 +4978,10 @@ igb_rxeof(struct igb_queue *que, int count, int *done)
*/
M_HASHTYPE_SET(rxr->fmp, M_HASHTYPE_OPAQUE);
} else {
-#ifndef IGB_LEGACY_TX
+
rxr->fmp->m_pkthdr.flowid = que->msix;
M_HASHTYPE_SET(rxr->fmp, M_HASHTYPE_OPAQUE);
-#endif
+
}
sendmp = rxr->fmp;
/* Make sure to set M_PKTHDR. */
diff --git a/sys/dev/gpioapu/gpioapu.c b/sys/dev/gpioapu/gpioapu.c
new file mode 100644
index 0000000..11e5e13
--- /dev/null
+++ b/sys/dev/gpioapu/gpioapu.c
@@ -0,0 +1,336 @@
+/*-
+ * Copyright (c) 2013 Ermal Luci <eri@FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+
+#include <sys/types.h>
+#include <sys/param.h>
+#include <sys/conf.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/systm.h>
+#include <sys/sysctl.h>
+#include <sys/priv.h>
+#include <sys/bus.h>
+#include <machine/bus.h>
+#include <sys/rman.h>
+#include <machine/resource.h>
+#include <sys/proc.h>
+#include <sys/uio.h>
+
+#include <dev/pci/pcivar.h>
+#include <isa/isavar.h>
+
+/* SB7xx RRG 2.3.3.1.1. */
+#define AMDSB_PMIO_INDEX 0xcd6
+#define AMDSB_PMIO_DATA (PMIO_INDEX + 1)
+#define AMDSB_PMIO_WIDTH 2
+
+#define AMDSB_SMBUS_DEVID 0x43851002
+#define AMDSB8_SMBUS_REVID 0x40
+
+#define IOMUX_OFFSET 0xD00
+#define GPIO_SPACE_OFFSET 0x100
+#define GPIO_SPACE_SIZE 0x100
+/* SB8xx RRG 2.3.3. */
+#define AMDSB8_PM_WDT_EN 0x24
+
+#define GPIO_187 187 // MODESW
+#define GPIO_189 189 // LED1#
+#define GPIO_190 190 // LED2#
+#define GPIO_191 191 // LED3#
+#define GPIO_OUTPUT 0x08
+#define GPIO_INPUT 0x28
+
+struct gpioapu_softc {
+ device_t dev;
+ struct cdev *cdev;
+ struct resource *res_ctrl;
+ struct resource *res_count;
+ int rid_ctrl;
+ int rid_count;
+};
+
+static int gpioapu_open(struct cdev *dev, int flags, int fmt,
+ struct thread *td);
+static int gpioapu_close(struct cdev *dev, int flags, int fmt,
+ struct thread *td);
+static int gpioapu_write(struct cdev *dev, struct uio *uio, int ioflag);
+static int gpioapu_read(struct cdev *dev, struct uio *uio, int ioflag);
+
+static struct cdevsw gpioapu_cdevsw = {
+ .d_version = D_VERSION,
+ .d_open = gpioapu_open,
+ .d_read = gpioapu_read,
+ .d_write = gpioapu_write,
+ .d_close = gpioapu_close,
+ .d_name = "gpioapu",
+};
+
+static void gpioapu_identify(driver_t *driver, device_t parent);
+static int gpioapu_probe(device_t dev);
+static int gpioapu_attach(device_t dev);
+static int gpioapu_detach(device_t dev);
+
+static device_method_t gpioapu_methods[] = {
+ DEVMETHOD(device_identify, gpioapu_identify),
+ DEVMETHOD(device_probe, gpioapu_probe),
+ DEVMETHOD(device_attach, gpioapu_attach),
+ DEVMETHOD(device_detach, gpioapu_detach),
+ {0, 0}
+};
+
+static devclass_t gpioapu_devclass;
+
+static driver_t gpioapu_driver = {
+ "gpioapu",
+ gpioapu_methods,
+ sizeof(struct gpioapu_softc)
+};
+
+DRIVER_MODULE(gpioapu, isa, gpioapu_driver, gpioapu_devclass, NULL, NULL);
+
+
+static uint8_t
+pmio_read(struct resource *res, uint8_t reg)
+{
+ bus_write_1(res, 0, reg); /* Index */
+ return (bus_read_1(res, 1)); /* Data */
+}
+
+#if 0
+static void
+pmio_write(struct resource *res, uint8_t reg, uint8_t val)
+{
+ bus_write_1(res, 0, reg); /* Index */
+ bus_write_1(res, 1, val); /* Data */
+}
+#endif
+
+/* ARGSUSED */
+static int
+gpioapu_open(struct cdev *dev __unused, int flags __unused, int fmt __unused,
+ struct thread *td)
+{
+ int error;
+
+ error = priv_check(td, PRIV_IO);
+ if (error != 0)
+ return (error);
+ error = securelevel_gt(td->td_ucred, 0);
+ if (error != 0)
+ return (error);
+
+ return (error);
+}
+
+static int
+gpioapu_read(struct cdev *dev, struct uio *uio, int ioflag) {
+ struct gpioapu_softc *sc = dev->si_drv1;
+ uint8_t tmp;
+ char ch;
+ int error;
+
+ tmp = bus_read_1(sc->res_ctrl, GPIO_187);
+#ifdef DEBUG
+ device_printf(sc->dev, "returned %x\n", (u_int)tmp);
+#endif
+ if (tmp & 0x80)
+ ch = '1';
+ else
+ ch = '0';
+
+ error = uiomove(&ch, sizeof(ch), uio);
+
+ return (error);
+}
+static int
+gpioapu_write(struct cdev *dev, struct uio *uio, int ioflag) {
+ struct gpioapu_softc *sc = dev->si_drv1;
+ char ch[3];
+ uint8_t old;
+ int error, i, start;
+
+ error = uiomove(ch, sizeof(ch), uio);
+ if (error)
+ return (error);
+
+ start = GPIO_189;
+ for (i = 0; i < 3; i++) {
+ old = bus_read_1(sc->res_ctrl, start + i);
+#ifdef DEBUG
+ device_printf(sc->dev, "returned %x - %c\n", (u_int)old, ch[i]);
+#endif
+ if (ch[i] == '1')
+ old &= 0x80;
+ else
+ old = 0xc8;
+ bus_write_1(sc->res_ctrl, start + i, old);
+ }
+
+ return (error);
+}
+
+static int
+gpioapu_close(struct cdev *dev __unused, int flags __unused, int fmt __unused,
+ struct thread *td)
+{
+ struct gpioapu_softc *sc = dev->si_drv1;
+ int i, start;
+
+ start = GPIO_187;
+ for (i = 0; i < 2; i++) {
+ bus_write_1(sc->res_ctrl, start, 0xc8);
+ }
+
+ return (0);
+}
+
+static void
+gpioapu_identify(driver_t *driver, device_t parent)
+{
+ device_t child;
+ device_t smb_dev;
+
+ if (resource_disabled("gpioapu", 0))
+ return;
+
+
+ if (device_find_child(parent, "gpioapu", -1) != NULL)
+ return;
+
+ /*
+ * Try to identify SB600/SB7xx by PCI Device ID of SMBus device
+ * that should be present at bus 0, device 20, function 0.
+ */
+ smb_dev = pci_find_bsf(0, 20, 0);
+ if (smb_dev == NULL)
+ return;
+
+ if (pci_get_devid(smb_dev) != AMDSB_SMBUS_DEVID)
+ return;
+
+ child = BUS_ADD_CHILD(parent, ISA_ORDER_SPECULATIVE, "gpioapu", -1);
+ if (child == NULL)
+ device_printf(parent, "add gpioapu child failed\n");
+}
+
+static int
+gpioapu_probe(device_t dev)
+{
+ struct resource *res;
+ uint32_t addr;
+ int rid;
+ int rc, i;
+ char *value;
+
+ value = getenv("smbios.system.product");
+ device_printf(dev, "Environment returned %s\n", value);
+ if (value == NULL || strncmp(value, "APU", strlen("APU")))
+ return (ENXIO);
+
+ /* Do not claim some ISA PnP device by accident. */
+ if (isa_get_logicalid(dev) != 0)
+ return (ENXIO);
+
+ rc = bus_set_resource(dev, SYS_RES_IOPORT, 0, AMDSB_PMIO_INDEX,
+ AMDSB_PMIO_WIDTH);
+ if (rc != 0) {
+ device_printf(dev, "bus_set_resource for IO failed\n");
+ return (ENXIO);
+ }
+ rid = 0;
+ res = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 0ul, ~0ul,
+ AMDSB_PMIO_WIDTH, RF_ACTIVE | RF_SHAREABLE);
+ if (res == NULL) {
+ device_printf(dev, "bus_alloc_resource for IO failed\n");
+ return (ENXIO);
+ }
+
+ /* Find base address of memory mapped WDT registers. */
+ for (addr = 0, i = 0; i < 4; i++) {
+ addr <<= 8;
+ addr |= pmio_read(res, AMDSB8_PM_WDT_EN + 3 - i);
+ }
+ addr &= 0xFFFFF000;
+ device_printf(dev, "Address on reg 0x24 is 0x%x/%u\n", addr, addr);
+
+ bus_release_resource(dev, SYS_RES_IOPORT, rid, res);
+ bus_delete_resource(dev, SYS_RES_IOPORT, rid);
+
+ rc = bus_set_resource(dev, SYS_RES_MEMORY, 0, addr + GPIO_SPACE_OFFSET,
+ GPIO_SPACE_SIZE);
+ if (rc != 0) {
+ device_printf(dev, "bus_set_resource for memory failed\n");
+ return (ENXIO);
+ }
+
+ return (0);
+}
+
+static int
+gpioapu_attach(device_t dev)
+{
+ struct gpioapu_softc *sc;
+
+ sc = device_get_softc(dev);
+ sc->dev = dev;
+ sc->rid_ctrl = 0;
+
+ sc->res_ctrl = bus_alloc_resource(dev, SYS_RES_MEMORY, &sc->rid_ctrl, 0ul, ~0ul,
+ GPIO_SPACE_SIZE, RF_ACTIVE | RF_SHAREABLE);
+ if (sc->res_ctrl == NULL) {
+ device_printf(dev, "bus_alloc_resource for memory failed\n");
+ return (ENXIO);
+ }
+
+ sc->dev = dev;
+ sc->cdev = make_dev(&gpioapu_cdevsw, 0,
+ UID_ROOT, GID_WHEEL, 0600, "gpioapu");
+
+ sc->cdev->si_drv1 = sc;
+
+ return (0);
+
+}
+
+static int
+gpioapu_detach(device_t dev)
+{
+ struct gpioapu_softc *sc;
+
+ sc = device_get_softc(dev);
+
+ if (sc->res_ctrl != NULL) {
+ bus_release_resource(dev, SYS_RES_MEMORY, sc->rid_ctrl,
+ sc->res_ctrl);
+ bus_delete_resource(dev, SYS_RES_MEMORY, sc->rid_ctrl);
+ }
+
+ destroy_dev(sc->cdev);
+
+ return (0);
+}
diff --git a/sys/dev/ichwd/ichwd.c b/sys/dev/ichwd/ichwd.c
index 9f8704f..73fcd7e 100644
--- a/sys/dev/ichwd/ichwd.c
+++ b/sys/dev/ichwd/ichwd.c
@@ -53,6 +53,7 @@
* (document no. 252516-001) sections 9.10 and 9.11.
*
* ICH6/7/8 support by Takeharu KATO <takeharu1219@ybb.ne.jp>
+ * SoC PMC support by Denir Li <denir.li@cas-well.com>
*/
#include <sys/cdefs.h>
@@ -74,161 +75,216 @@ __FBSDID("$FreeBSD$");
#include <dev/ichwd/ichwd.h>
static struct ichwd_device ichwd_devices[] = {
- { DEVICEID_82801AA, "Intel 82801AA watchdog timer", 1 },
- { DEVICEID_82801AB, "Intel 82801AB watchdog timer", 1 },
- { DEVICEID_82801BA, "Intel 82801BA watchdog timer", 2 },
- { DEVICEID_82801BAM, "Intel 82801BAM watchdog timer", 2 },
- { DEVICEID_82801CA, "Intel 82801CA watchdog timer", 3 },
- { DEVICEID_82801CAM, "Intel 82801CAM watchdog timer", 3 },
- { DEVICEID_82801DB, "Intel 82801DB watchdog timer", 4 },
- { DEVICEID_82801DBM, "Intel 82801DBM watchdog timer", 4 },
- { DEVICEID_82801E, "Intel 82801E watchdog timer", 5 },
- { DEVICEID_82801EB, "Intel 82801EB watchdog timer", 5 },
- { DEVICEID_82801EBR, "Intel 82801EB/ER watchdog timer", 5 },
- { DEVICEID_6300ESB, "Intel 6300ESB watchdog timer", 5 },
- { DEVICEID_82801FBR, "Intel 82801FB/FR watchdog timer", 6 },
- { DEVICEID_ICH6M, "Intel ICH6M watchdog timer", 6 },
- { DEVICEID_ICH6W, "Intel ICH6W watchdog timer", 6 },
- { DEVICEID_ICH7, "Intel ICH7 watchdog timer", 7 },
- { DEVICEID_ICH7DH, "Intel ICH7DH watchdog timer", 7 },
- { DEVICEID_ICH7M, "Intel ICH7M watchdog timer", 7 },
- { DEVICEID_ICH7MDH, "Intel ICH7MDH watchdog timer", 7 },
- { DEVICEID_NM10, "Intel NM10 watchdog timer", 7 },
- { DEVICEID_ICH8, "Intel ICH8 watchdog timer", 8 },
- { DEVICEID_ICH8DH, "Intel ICH8DH watchdog timer", 8 },
- { DEVICEID_ICH8DO, "Intel ICH8DO watchdog timer", 8 },
- { DEVICEID_ICH8M, "Intel ICH8M watchdog timer", 8 },
- { DEVICEID_ICH8ME, "Intel ICH8M-E watchdog timer", 8 },
- { DEVICEID_63XXESB, "Intel 63XXESB watchdog timer", 8 },
- { DEVICEID_ICH9, "Intel ICH9 watchdog timer", 9 },
- { DEVICEID_ICH9DH, "Intel ICH9DH watchdog timer", 9 },
- { DEVICEID_ICH9DO, "Intel ICH9DO watchdog timer", 9 },
- { DEVICEID_ICH9M, "Intel ICH9M watchdog timer", 9 },
- { DEVICEID_ICH9ME, "Intel ICH9M-E watchdog timer", 9 },
- { DEVICEID_ICH9R, "Intel ICH9R watchdog timer", 9 },
- { DEVICEID_ICH10, "Intel ICH10 watchdog timer", 10 },
- { DEVICEID_ICH10D, "Intel ICH10D watchdog timer", 10 },
- { DEVICEID_ICH10DO, "Intel ICH10DO watchdog timer", 10 },
- { DEVICEID_ICH10R, "Intel ICH10R watchdog timer", 10 },
- { DEVICEID_PCH, "Intel PCH watchdog timer", 10 },
- { DEVICEID_PCHM, "Intel PCH watchdog timer", 10 },
- { DEVICEID_P55, "Intel P55 watchdog timer", 10 },
- { DEVICEID_PM55, "Intel PM55 watchdog timer", 10 },
- { DEVICEID_H55, "Intel H55 watchdog timer", 10 },
- { DEVICEID_QM57, "Intel QM57 watchdog timer", 10 },
- { DEVICEID_H57, "Intel H57 watchdog timer", 10 },
- { DEVICEID_HM55, "Intel HM55 watchdog timer", 10 },
- { DEVICEID_Q57, "Intel Q57 watchdog timer", 10 },
- { DEVICEID_HM57, "Intel HM57 watchdog timer", 10 },
- { DEVICEID_PCHMSFF, "Intel PCHMSFF watchdog timer", 10 },
- { DEVICEID_QS57, "Intel QS57 watchdog timer", 10 },
- { DEVICEID_3400, "Intel 3400 watchdog timer", 10 },
- { DEVICEID_3420, "Intel 3420 watchdog timer", 10 },
- { DEVICEID_3450, "Intel 3450 watchdog timer", 10 },
- { DEVICEID_CPT0, "Intel Cougar Point watchdog timer", 10 },
- { DEVICEID_CPT1, "Intel Cougar Point watchdog timer", 10 },
- { DEVICEID_CPT2, "Intel Cougar Point watchdog timer", 10 },
- { DEVICEID_CPT3, "Intel Cougar Point watchdog timer", 10 },
- { DEVICEID_CPT4, "Intel Cougar Point watchdog timer", 10 },
- { DEVICEID_CPT5, "Intel Cougar Point watchdog timer", 10 },
- { DEVICEID_CPT6, "Intel Cougar Point watchdog timer", 10 },
- { DEVICEID_CPT7, "Intel Cougar Point watchdog timer", 10 },
- { DEVICEID_CPT8, "Intel Cougar Point watchdog timer", 10 },
- { DEVICEID_CPT9, "Intel Cougar Point watchdog timer", 10 },
- { DEVICEID_CPT10, "Intel Cougar Point watchdog timer", 10 },
- { DEVICEID_CPT11, "Intel Cougar Point watchdog timer", 10 },
- { DEVICEID_CPT12, "Intel Cougar Point watchdog timer", 10 },
- { DEVICEID_CPT13, "Intel Cougar Point watchdog timer", 10 },
- { DEVICEID_CPT14, "Intel Cougar Point watchdog timer", 10 },
- { DEVICEID_CPT15, "Intel Cougar Point watchdog timer", 10 },
- { DEVICEID_CPT16, "Intel Cougar Point watchdog timer", 10 },
- { DEVICEID_CPT17, "Intel Cougar Point watchdog timer", 10 },
- { DEVICEID_CPT18, "Intel Cougar Point watchdog timer", 10 },
- { DEVICEID_CPT19, "Intel Cougar Point watchdog timer", 10 },
- { DEVICEID_CPT20, "Intel Cougar Point watchdog timer", 10 },
- { DEVICEID_CPT21, "Intel Cougar Point watchdog timer", 10 },
- { DEVICEID_CPT22, "Intel Cougar Point watchdog timer", 10 },
- { DEVICEID_CPT23, "Intel Cougar Point watchdog timer", 10 },
- { DEVICEID_CPT23, "Intel Cougar Point watchdog timer", 10 },
- { DEVICEID_CPT25, "Intel Cougar Point watchdog timer", 10 },
- { DEVICEID_CPT26, "Intel Cougar Point watchdog timer", 10 },
- { DEVICEID_CPT27, "Intel Cougar Point watchdog timer", 10 },
- { DEVICEID_CPT28, "Intel Cougar Point watchdog timer", 10 },
- { DEVICEID_CPT29, "Intel Cougar Point watchdog timer", 10 },
- { DEVICEID_CPT30, "Intel Cougar Point watchdog timer", 10 },
- { DEVICEID_CPT31, "Intel Cougar Point watchdog timer", 10 },
- { DEVICEID_PATSBURG_LPC1, "Intel Patsburg watchdog timer", 10 },
- { DEVICEID_PATSBURG_LPC2, "Intel Patsburg watchdog timer", 10 },
- { DEVICEID_PPT0, "Intel Panther Point watchdog timer", 10 },
- { DEVICEID_PPT1, "Intel Panther Point watchdog timer", 10 },
- { DEVICEID_PPT2, "Intel Panther Point watchdog timer", 10 },
- { DEVICEID_PPT3, "Intel Panther Point watchdog timer", 10 },
- { DEVICEID_PPT4, "Intel Panther Point watchdog timer", 10 },
- { DEVICEID_PPT5, "Intel Panther Point watchdog timer", 10 },
- { DEVICEID_PPT6, "Intel Panther Point watchdog timer", 10 },
- { DEVICEID_PPT7, "Intel Panther Point watchdog timer", 10 },
- { DEVICEID_PPT8, "Intel Panther Point watchdog timer", 10 },
- { DEVICEID_PPT9, "Intel Panther Point watchdog timer", 10 },
- { DEVICEID_PPT10, "Intel Panther Point watchdog timer", 10 },
- { DEVICEID_PPT11, "Intel Panther Point watchdog timer", 10 },
- { DEVICEID_PPT12, "Intel Panther Point watchdog timer", 10 },
- { DEVICEID_PPT13, "Intel Panther Point watchdog timer", 10 },
- { DEVICEID_PPT14, "Intel Panther Point watchdog timer", 10 },
- { DEVICEID_PPT15, "Intel Panther Point watchdog timer", 10 },
- { DEVICEID_PPT16, "Intel Panther Point watchdog timer", 10 },
- { DEVICEID_PPT17, "Intel Panther Point watchdog timer", 10 },
- { DEVICEID_PPT18, "Intel Panther Point watchdog timer", 10 },
- { DEVICEID_PPT19, "Intel Panther Point watchdog timer", 10 },
- { DEVICEID_PPT20, "Intel Panther Point watchdog timer", 10 },
- { DEVICEID_PPT21, "Intel Panther Point watchdog timer", 10 },
- { DEVICEID_PPT22, "Intel Panther Point watchdog timer", 10 },
- { DEVICEID_PPT23, "Intel Panther Point watchdog timer", 10 },
- { DEVICEID_PPT24, "Intel Panther Point watchdog timer", 10 },
- { DEVICEID_PPT25, "Intel Panther Point watchdog timer", 10 },
- { DEVICEID_PPT26, "Intel Panther Point watchdog timer", 10 },
- { DEVICEID_PPT27, "Intel Panther Point watchdog timer", 10 },
- { DEVICEID_PPT28, "Intel Panther Point watchdog timer", 10 },
- { DEVICEID_PPT29, "Intel Panther Point watchdog timer", 10 },
- { DEVICEID_PPT30, "Intel Panther Point watchdog timer", 10 },
- { DEVICEID_PPT31, "Intel Panther Point watchdog timer", 10 },
- { DEVICEID_LPT0, "Intel Lynx Point watchdog timer", 10 },
- { DEVICEID_LPT1, "Intel Lynx Point watchdog timer", 10 },
- { DEVICEID_LPT2, "Intel Lynx Point watchdog timer", 10 },
- { DEVICEID_LPT3, "Intel Lynx Point watchdog timer", 10 },
- { DEVICEID_LPT4, "Intel Lynx Point watchdog timer", 10 },
- { DEVICEID_LPT5, "Intel Lynx Point watchdog timer", 10 },
- { DEVICEID_LPT6, "Intel Lynx Point watchdog timer", 10 },
- { DEVICEID_LPT7, "Intel Lynx Point watchdog timer", 10 },
- { DEVICEID_LPT8, "Intel Lynx Point watchdog timer", 10 },
- { DEVICEID_LPT9, "Intel Lynx Point watchdog timer", 10 },
- { DEVICEID_LPT10, "Intel Lynx Point watchdog timer", 10 },
- { DEVICEID_LPT11, "Intel Lynx Point watchdog timer", 10 },
- { DEVICEID_LPT12, "Intel Lynx Point watchdog timer", 10 },
- { DEVICEID_LPT13, "Intel Lynx Point watchdog timer", 10 },
- { DEVICEID_LPT14, "Intel Lynx Point watchdog timer", 10 },
- { DEVICEID_LPT15, "Intel Lynx Point watchdog timer", 10 },
- { DEVICEID_LPT16, "Intel Lynx Point watchdog timer", 10 },
- { DEVICEID_LPT17, "Intel Lynx Point watchdog timer", 10 },
- { DEVICEID_LPT18, "Intel Lynx Point watchdog timer", 10 },
- { DEVICEID_LPT19, "Intel Lynx Point watchdog timer", 10 },
- { DEVICEID_LPT20, "Intel Lynx Point watchdog timer", 10 },
- { DEVICEID_LPT21, "Intel Lynx Point watchdog timer", 10 },
- { DEVICEID_LPT22, "Intel Lynx Point watchdog timer", 10 },
- { DEVICEID_LPT23, "Intel Lynx Point watchdog timer", 10 },
- { DEVICEID_LPT24, "Intel Lynx Point watchdog timer", 10 },
- { DEVICEID_LPT25, "Intel Lynx Point watchdog timer", 10 },
- { DEVICEID_LPT26, "Intel Lynx Point watchdog timer", 10 },
- { DEVICEID_LPT27, "Intel Lynx Point watchdog timer", 10 },
- { DEVICEID_LPT28, "Intel Lynx Point watchdog timer", 10 },
- { DEVICEID_LPT29, "Intel Lynx Point watchdog timer", 10 },
- { DEVICEID_LPT30, "Intel Lynx Point watchdog timer", 10 },
- { DEVICEID_LPT31, "Intel Lynx Point watchdog timer", 10 },
- { DEVICEID_WCPT2, "Intel Wildcat Point watchdog timer", 10 },
- { DEVICEID_WCPT4, "Intel Wildcat Point watchdog timer", 10 },
- { DEVICEID_WCPT6, "Intel Wildcat Point watchdog timer", 10 },
- { DEVICEID_DH89XXCC_LPC, "Intel DH89xxCC watchdog timer", 10 },
- { DEVICEID_COLETOCRK_LPC, "Intel Coleto Creek watchdog timer", 10 },
- { 0, NULL, 0 },
+ { DEVICEID_82801AA, "Intel 82801AA watchdog timer", 1, 1 },
+ { DEVICEID_82801AB, "Intel 82801AB watchdog timer", 1, 1 },
+ { DEVICEID_82801BA, "Intel 82801BA watchdog timer", 2, 1 },
+ { DEVICEID_82801BAM, "Intel 82801BAM watchdog timer", 2, 1 },
+ { DEVICEID_82801CA, "Intel 82801CA watchdog timer", 3, 1 },
+ { DEVICEID_82801CAM, "Intel 82801CAM watchdog timer", 3, 1 },
+ { DEVICEID_82801DB, "Intel 82801DB watchdog timer", 4, 1 },
+ { DEVICEID_82801DBM, "Intel 82801DBM watchdog timer", 4, 1 },
+ { DEVICEID_82801E, "Intel 82801E watchdog timer", 5, 1 },
+ { DEVICEID_82801EB, "Intel 82801EB watchdog timer", 5, 1 },
+ { DEVICEID_82801EBR, "Intel 82801EB/ER watchdog timer", 5, 1 },
+ { DEVICEID_6300ESB, "Intel 6300ESB watchdog timer", 5, 1 },
+ { DEVICEID_82801FBR, "Intel 82801FB/FR watchdog timer", 6, 2 },
+ { DEVICEID_ICH6M, "Intel ICH6M watchdog timer", 6, 2 },
+ { DEVICEID_ICH6W, "Intel ICH6W watchdog timer", 6, 2 },
+ { DEVICEID_ICH7, "Intel ICH7 watchdog timer", 7, 2 },
+ { DEVICEID_ICH7DH, "Intel ICH7DH watchdog timer", 7, 2 },
+ { DEVICEID_ICH7M, "Intel ICH7M watchdog timer", 7, 2 },
+ { DEVICEID_ICH7MDH, "Intel ICH7MDH watchdog timer", 7, 2 },
+ { DEVICEID_NM10, "Intel NM10 watchdog timer", 7, 2 },
+ { DEVICEID_ICH8, "Intel ICH8 watchdog timer", 8, 2 },
+ { DEVICEID_ICH8DH, "Intel ICH8DH watchdog timer", 8, 2 },
+ { DEVICEID_ICH8DO, "Intel ICH8DO watchdog timer", 8, 2 },
+ { DEVICEID_ICH8M, "Intel ICH8M watchdog timer", 8, 2 },
+ { DEVICEID_ICH8ME, "Intel ICH8M-E watchdog timer", 8, 2 },
+ { DEVICEID_63XXESB, "Intel 63XXESB watchdog timer", 8, 2 },
+ { DEVICEID_ICH9, "Intel ICH9 watchdog timer", 9, 2 },
+ { DEVICEID_ICH9DH, "Intel ICH9DH watchdog timer", 9, 2 },
+ { DEVICEID_ICH9DO, "Intel ICH9DO watchdog timer", 9, 2 },
+ { DEVICEID_ICH9M, "Intel ICH9M watchdog timer", 9, 2 },
+ { DEVICEID_ICH9ME, "Intel ICH9M-E watchdog timer", 9, 2 },
+ { DEVICEID_ICH9R, "Intel ICH9R watchdog timer", 9, 2 },
+ { DEVICEID_ICH10, "Intel ICH10 watchdog timer", 10, 2 },
+ { DEVICEID_ICH10D, "Intel ICH10D watchdog timer", 10, 2 },
+ { DEVICEID_ICH10DO, "Intel ICH10DO watchdog timer", 10, 2 },
+ { DEVICEID_ICH10R, "Intel ICH10R watchdog timer", 10, 2 },
+ { DEVICEID_PCH, "Intel PCH watchdog timer", 10, 2 },
+ { DEVICEID_PCHM, "Intel PCH watchdog timer", 10, 2 },
+ { DEVICEID_P55, "Intel P55 watchdog timer", 10, 2 },
+ { DEVICEID_PM55, "Intel PM55 watchdog timer", 10, 2 },
+ { DEVICEID_H55, "Intel H55 watchdog timer", 10, 2 },
+ { DEVICEID_QM57, "Intel QM57 watchdog timer", 10, 2 },
+ { DEVICEID_H57, "Intel H57 watchdog timer", 10, 2 },
+ { DEVICEID_HM55, "Intel HM55 watchdog timer", 10, 2 },
+ { DEVICEID_Q57, "Intel Q57 watchdog timer", 10, 2 },
+ { DEVICEID_HM57, "Intel HM57 watchdog timer", 10, 2 },
+ { DEVICEID_PCHMSFF, "Intel PCHMSFF watchdog timer", 10, 2 },
+ { DEVICEID_QS57, "Intel QS57 watchdog timer", 10, 2 },
+ { DEVICEID_3400, "Intel 3400 watchdog timer", 10, 2 },
+ { DEVICEID_3420, "Intel 3420 watchdog timer", 10, 2 },
+ { DEVICEID_3450, "Intel 3450 watchdog timer", 10, 2 },
+ { DEVICEID_CPT0, "Intel Cougar Point watchdog timer", 10, 2 },
+ { DEVICEID_CPT1, "Intel Cougar Point watchdog timer", 10, 2 },
+ { DEVICEID_CPT2, "Intel Cougar Point watchdog timer", 10, 2 },
+ { DEVICEID_CPT3, "Intel Cougar Point watchdog timer", 10, 2 },
+ { DEVICEID_CPT4, "Intel Cougar Point watchdog timer", 10, 2 },
+ { DEVICEID_CPT5, "Intel Cougar Point watchdog timer", 10, 2 },
+ { DEVICEID_CPT6, "Intel Cougar Point watchdog timer", 10, 2 },
+ { DEVICEID_CPT7, "Intel Cougar Point watchdog timer", 10, 2 },
+ { DEVICEID_CPT8, "Intel Cougar Point watchdog timer", 10, 2 },
+ { DEVICEID_CPT9, "Intel Cougar Point watchdog timer", 10, 2 },
+ { DEVICEID_CPT10, "Intel Cougar Point watchdog timer", 10, 2 },
+ { DEVICEID_CPT11, "Intel Cougar Point watchdog timer", 10, 2 },
+ { DEVICEID_CPT12, "Intel Cougar Point watchdog timer", 10, 2 },
+ { DEVICEID_CPT13, "Intel Cougar Point watchdog timer", 10, 2 },
+ { DEVICEID_CPT14, "Intel Cougar Point watchdog timer", 10, 2 },
+ { DEVICEID_CPT15, "Intel Cougar Point watchdog timer", 10, 2 },
+ { DEVICEID_CPT16, "Intel Cougar Point watchdog timer", 10, 2 },
+ { DEVICEID_CPT17, "Intel Cougar Point watchdog timer", 10, 2 },
+ { DEVICEID_CPT18, "Intel Cougar Point watchdog timer", 10, 2 },
+ { DEVICEID_CPT19, "Intel Cougar Point watchdog timer", 10, 2 },
+ { DEVICEID_CPT20, "Intel Cougar Point watchdog timer", 10, 2 },
+ { DEVICEID_CPT21, "Intel Cougar Point watchdog timer", 10, 2 },
+ { DEVICEID_CPT22, "Intel Cougar Point watchdog timer", 10, 2 },
+ { DEVICEID_CPT23, "Intel Cougar Point watchdog timer", 10, 2 },
+ { DEVICEID_CPT24, "Intel Cougar Point watchdog timer", 10, 2 },
+ { DEVICEID_CPT25, "Intel Cougar Point watchdog timer", 10, 2 },
+ { DEVICEID_CPT26, "Intel Cougar Point watchdog timer", 10, 2 },
+ { DEVICEID_CPT27, "Intel Cougar Point watchdog timer", 10, 2 },
+ { DEVICEID_CPT28, "Intel Cougar Point watchdog timer", 10, 2 },
+ { DEVICEID_CPT29, "Intel Cougar Point watchdog timer", 10, 2 },
+ { DEVICEID_CPT30, "Intel Cougar Point watchdog timer", 10, 2 },
+ { DEVICEID_CPT31, "Intel Cougar Point watchdog timer", 10, 2 },
+ { DEVICEID_PATSBURG_LPC1, "Intel Patsburg watchdog timer", 10, 2 },
+ { DEVICEID_PATSBURG_LPC2, "Intel Patsburg watchdog timer", 10, 2 },
+ { DEVICEID_PPT0, "Intel Panther Point watchdog timer", 10, 2 },
+ { DEVICEID_PPT1, "Intel Panther Point watchdog timer", 10, 2 },
+ { DEVICEID_PPT2, "Intel Panther Point watchdog timer", 10, 2 },
+ { DEVICEID_PPT3, "Intel Panther Point watchdog timer", 10, 2 },
+ { DEVICEID_PPT4, "Intel Panther Point watchdog timer", 10, 2 },
+ { DEVICEID_PPT5, "Intel Panther Point watchdog timer", 10, 2 },
+ { DEVICEID_PPT6, "Intel Panther Point watchdog timer", 10, 2 },
+ { DEVICEID_PPT7, "Intel Panther Point watchdog timer", 10, 2 },
+ { DEVICEID_PPT8, "Intel Panther Point watchdog timer", 10, 2 },
+ { DEVICEID_PPT9, "Intel Panther Point watchdog timer", 10, 2 },
+ { DEVICEID_PPT10, "Intel Panther Point watchdog timer", 10, 2 },
+ { DEVICEID_PPT11, "Intel Panther Point watchdog timer", 10, 2 },
+ { DEVICEID_PPT12, "Intel Panther Point watchdog timer", 10, 2 },
+ { DEVICEID_PPT13, "Intel Panther Point watchdog timer", 10, 2 },
+ { DEVICEID_PPT14, "Intel Panther Point watchdog timer", 10, 2 },
+ { DEVICEID_PPT15, "Intel Panther Point watchdog timer", 10, 2 },
+ { DEVICEID_PPT16, "Intel Panther Point watchdog timer", 10, 2 },
+ { DEVICEID_PPT17, "Intel Panther Point watchdog timer", 10, 2 },
+ { DEVICEID_PPT18, "Intel Panther Point watchdog timer", 10, 2 },
+ { DEVICEID_PPT19, "Intel Panther Point watchdog timer", 10, 2 },
+ { DEVICEID_PPT20, "Intel Panther Point watchdog timer", 10, 2 },
+ { DEVICEID_PPT21, "Intel Panther Point watchdog timer", 10, 2 },
+ { DEVICEID_PPT22, "Intel Panther Point watchdog timer", 10, 2 },
+ { DEVICEID_PPT23, "Intel Panther Point watchdog timer", 10, 2 },
+ { DEVICEID_PPT24, "Intel Panther Point watchdog timer", 10, 2 },
+ { DEVICEID_PPT25, "Intel Panther Point watchdog timer", 10, 2 },
+ { DEVICEID_PPT26, "Intel Panther Point watchdog timer", 10, 2 },
+ { DEVICEID_PPT27, "Intel Panther Point watchdog timer", 10, 2 },
+ { DEVICEID_PPT28, "Intel Panther Point watchdog timer", 10, 2 },
+ { DEVICEID_PPT29, "Intel Panther Point watchdog timer", 10, 2 },
+ { DEVICEID_PPT30, "Intel Panther Point watchdog timer", 10, 2 },
+ { DEVICEID_PPT31, "Intel Panther Point watchdog timer", 10, 2 },
+ { DEVICEID_LPT0, "Intel Lynx Point watchdog timer", 10, 2 },
+ { DEVICEID_LPT1, "Intel Lynx Point watchdog timer", 10, 2 },
+ { DEVICEID_LPT2, "Intel Lynx Point watchdog timer", 10, 2 },
+ { DEVICEID_LPT3, "Intel Lynx Point watchdog timer", 10, 2 },
+ { DEVICEID_LPT4, "Intel Lynx Point watchdog timer", 10, 2 },
+ { DEVICEID_LPT5, "Intel Lynx Point watchdog timer", 10, 2 },
+ { DEVICEID_LPT6, "Intel Lynx Point watchdog timer", 10, 2 },
+ { DEVICEID_LPT7, "Intel Lynx Point watchdog timer", 10, 2 },
+ { DEVICEID_LPT8, "Intel Lynx Point watchdog timer", 10, 2 },
+ { DEVICEID_LPT9, "Intel Lynx Point watchdog timer", 10, 2 },
+ { DEVICEID_LPT10, "Intel Lynx Point watchdog timer", 10, 2 },
+ { DEVICEID_LPT11, "Intel Lynx Point watchdog timer", 10, 2 },
+ { DEVICEID_LPT12, "Intel Lynx Point watchdog timer", 10, 2 },
+ { DEVICEID_LPT13, "Intel Lynx Point watchdog timer", 10, 2 },
+ { DEVICEID_LPT14, "Intel Lynx Point watchdog timer", 10, 2 },
+ { DEVICEID_LPT15, "Intel Lynx Point watchdog timer", 10, 2 },
+ { DEVICEID_LPT16, "Intel Lynx Point watchdog timer", 10, 2 },
+ { DEVICEID_LPT17, "Intel Lynx Point watchdog timer", 10, 2 },
+ { DEVICEID_LPT18, "Intel Lynx Point watchdog timer", 10, 2 },
+ { DEVICEID_LPT19, "Intel Lynx Point watchdog timer", 10, 2 },
+ { DEVICEID_LPT20, "Intel Lynx Point watchdog timer", 10, 2 },
+ { DEVICEID_LPT21, "Intel Lynx Point watchdog timer", 10, 2 },
+ { DEVICEID_LPT22, "Intel Lynx Point watchdog timer", 10, 2 },
+ { DEVICEID_LPT23, "Intel Lynx Point watchdog timer", 10, 2 },
+ { DEVICEID_LPT24, "Intel Lynx Point watchdog timer", 10, 2 },
+ { DEVICEID_LPT25, "Intel Lynx Point watchdog timer", 10, 2 },
+ { DEVICEID_LPT26, "Intel Lynx Point watchdog timer", 10, 2 },
+ { DEVICEID_LPT27, "Intel Lynx Point watchdog timer", 10, 2 },
+ { DEVICEID_LPT28, "Intel Lynx Point watchdog timer", 10, 2 },
+ { DEVICEID_LPT29, "Intel Lynx Point watchdog timer", 10, 2 },
+ { DEVICEID_LPT30, "Intel Lynx Point watchdog timer", 10, 2 },
+ { DEVICEID_LPT31, "Intel Lynx Point watchdog timer", 10, 2 },
+ { DEVICEID_WCPT1, "Intel Wildcat Point watchdog timer", 10, 2 },
+ { DEVICEID_WCPT2, "Intel Wildcat Point watchdog timer", 10, 2 },
+ { DEVICEID_WCPT3, "Intel Wildcat Point watchdog timer", 10, 2 },
+ { DEVICEID_WCPT4, "Intel Wildcat Point watchdog timer", 10, 2 },
+ { DEVICEID_WCPT6, "Intel Wildcat Point watchdog timer", 10, 2 },
+ { DEVICEID_WBG0, "Intel Wellsburg watchdog timer", 10, 2 },
+ { DEVICEID_WBG1, "Intel Wellsburg watchdog timer", 10, 2 },
+ { DEVICEID_WBG2, "Intel Wellsburg watchdog timer", 10, 2 },
+ { DEVICEID_WBG3, "Intel Wellsburg watchdog timer", 10, 2 },
+ { DEVICEID_WBG4, "Intel Wellsburg watchdog timer", 10, 2 },
+ { DEVICEID_WBG5, "Intel Wellsburg watchdog timer", 10, 2 },
+ { DEVICEID_WBG6, "Intel Wellsburg watchdog timer", 10, 2 },
+ { DEVICEID_WBG7, "Intel Wellsburg watchdog timer", 10, 2 },
+ { DEVICEID_WBG8, "Intel Wellsburg watchdog timer", 10, 2 },
+ { DEVICEID_WBG9, "Intel Wellsburg watchdog timer", 10, 2 },
+ { DEVICEID_WBG10, "Intel Wellsburg watchdog timer", 10, 2 },
+ { DEVICEID_WBG11, "Intel Wellsburg watchdog timer", 10, 2 },
+ { DEVICEID_WBG12, "Intel Wellsburg watchdog timer", 10, 2 },
+ { DEVICEID_WBG13, "Intel Wellsburg watchdog timer", 10, 2 },
+ { DEVICEID_WBG14, "Intel Wellsburg watchdog timer", 10, 2 },
+ { DEVICEID_WBG15, "Intel Wellsburg watchdog timer", 10, 2 },
+ { DEVICEID_WBG16, "Intel Wellsburg watchdog timer", 10, 2 },
+ { DEVICEID_WBG17, "Intel Wellsburg watchdog timer", 10, 2 },
+ { DEVICEID_WBG18, "Intel Wellsburg watchdog timer", 10, 2 },
+ { DEVICEID_WBG19, "Intel Wellsburg watchdog timer", 10, 2 },
+ { DEVICEID_WBG20, "Intel Wellsburg watchdog timer", 10, 2 },
+ { DEVICEID_WBG21, "Intel Wellsburg watchdog timer", 10, 2 },
+ { DEVICEID_WBG22, "Intel Wellsburg watchdog timer", 10, 2 },
+ { DEVICEID_WBG23, "Intel Wellsburg watchdog timer", 10, 2 },
+ { DEVICEID_WBG24, "Intel Wellsburg watchdog timer", 10, 2 },
+ { DEVICEID_WBG25, "Intel Wellsburg watchdog timer", 10, 2 },
+ { DEVICEID_WBG26, "Intel Wellsburg watchdog timer", 10, 2 },
+ { DEVICEID_WBG27, "Intel Wellsburg watchdog timer", 10, 2 },
+ { DEVICEID_WBG28, "Intel Wellsburg watchdog timer", 10, 2 },
+ { DEVICEID_WBG29, "Intel Wellsburg watchdog timer", 10, 2 },
+ { DEVICEID_WBG30, "Intel Wellsburg watchdog timer", 10, 2 },
+ { DEVICEID_WBG31, "Intel Wellsburg watchdog timer", 10, 2 },
+ { DEVICEID_LPT_LP0, "Intel Lynx Point-LP watchdog timer", 10, 2 },
+ { DEVICEID_LPT_LP1, "Intel Lynx Point-LP watchdog timer", 10, 2 },
+ { DEVICEID_LPT_LP2, "Intel Lynx Point-LP watchdog timer", 10, 2 },
+ { DEVICEID_LPT_LP3, "Intel Lynx Point-LP watchdog timer", 10, 2 },
+ { DEVICEID_LPT_LP4, "Intel Lynx Point-LP watchdog timer", 10, 2 },
+ { DEVICEID_LPT_LP5, "Intel Lynx Point-LP watchdog timer", 10, 2 },
+ { DEVICEID_LPT_LP6, "Intel Lynx Point-LP watchdog timer", 10, 2 },
+ { DEVICEID_LPT_LP7, "Intel Lynx Point-LP watchdog timer", 10, 2 },
+ { DEVICEID_WCPT_LP1, "Intel Wildcat Point-LP watchdog timer", 10, 2 },
+ { DEVICEID_WCPT_LP2, "Intel Wildcat Point-LP watchdog timer", 10, 2 },
+ { DEVICEID_WCPT_LP3, "Intel Wildcat Point-LP watchdog timer", 10, 2 },
+ { DEVICEID_WCPT_LP5, "Intel Wildcat Point-LP watchdog timer", 10, 2 },
+ { DEVICEID_WCPT_LP6, "Intel Wildcat Point-LP watchdog timer", 10, 2 },
+ { DEVICEID_WCPT_LP7, "Intel Wildcat Point-LP watchdog timer", 10, 2 },
+ { DEVICEID_WCPT_LP9, "Intel Wildcat Point-LP watchdog timer", 10, 2 },
+ { DEVICEID_DH89XXCC_LPC, "Intel DH89xxCC watchdog timer", 10, 2 },
+ { DEVICEID_COLETOCRK_LPC, "Intel Coleto Creek watchdog timer", 10, 2 },
+ { DEVICEID_AVN0, "Intel Avoton/Rangeley SoC watchdog timer",10, 3 },
+ { DEVICEID_AVN1, "Intel Avoton/Rangeley SoC watchdog timer",10, 3 },
+ { DEVICEID_AVN2, "Intel Avoton/Rangeley SoC watchdog timer",10, 3 },
+ { DEVICEID_AVN3, "Intel Avoton/Rangeley SoC watchdog timer",10, 3 },
+ { DEVICEID_BAYTRAIL, "Intel Bay Trail SoC watchdog timer", 10, 3 },
+ { DEVICEID_BRASWELL, "Intel Braswell SoC watchdog timer", 10, 3 },
+ { 0, NULL, 0, 0 },
};
static devclass_t ichwd_devclass;
@@ -241,7 +297,7 @@ static devclass_t ichwd_devclass;
bus_read_4((sc)->tco_res, (off))
#define ichwd_read_smi_4(sc, off) \
bus_read_4((sc)->smi_res, (off))
-#define ichwd_read_gcs_4(sc, off) \
+#define ichwd_read_gcs_pmc_4(sc, off) \
bus_read_4((sc)->gcs_res, (off))
#define ichwd_write_tco_1(sc, off, val) \
@@ -252,7 +308,7 @@ static devclass_t ichwd_devclass;
bus_write_4((sc)->tco_res, (off), (val))
#define ichwd_write_smi_4(sc, off, val) \
bus_write_4((sc)->smi_res, (off), (val))
-#define ichwd_write_gcs_4(sc, off, val) \
+#define ichwd_write_gcs_pmc_4(sc, off, val) \
bus_write_4((sc)->gcs_res, (off), (val))
#define ichwd_verbose_printf(dev, ...) \
@@ -352,7 +408,7 @@ ichwd_tmr_disable(struct ichwd_softc *sc)
static __inline void
ichwd_tmr_reload(struct ichwd_softc *sc)
{
- if (sc->ich_version <= 5)
+ if (sc->tco_version == 1)
ichwd_write_tco_1(sc, TCO_RLD, 1);
else
ichwd_write_tco_2(sc, TCO_RLD, 1);
@@ -369,7 +425,7 @@ ichwd_tmr_set(struct ichwd_softc *sc, unsigned int timeout)
if (timeout < TCO_RLD_TMR_MIN)
timeout = TCO_RLD_TMR_MIN;
- if (sc->ich_version <= 5) {
+ if (sc->tco_version == 1) {
uint8_t tmr_val8 = ichwd_read_tco_1(sc, TCO_TMR1);
tmr_val8 &= (~TCO_RLD1_TMR_MAX & 0xff);
@@ -399,20 +455,40 @@ ichwd_clear_noreboot(struct ichwd_softc *sc)
int rc = 0;
/* try to clear the NO_REBOOT bit */
- if (sc->ich_version <= 5) {
- status = pci_read_config(sc->ich, ICH_GEN_STA, 1);
- status &= ~ICH_GEN_STA_NO_REBOOT;
- pci_write_config(sc->ich, ICH_GEN_STA, status, 1);
- status = pci_read_config(sc->ich, ICH_GEN_STA, 1);
- if (status & ICH_GEN_STA_NO_REBOOT)
- rc = EIO;
- } else {
- status = ichwd_read_gcs_4(sc, 0);
- status &= ~ICH_GCS_NO_REBOOT;
- ichwd_write_gcs_4(sc, 0, status);
- status = ichwd_read_gcs_4(sc, 0);
- if (status & ICH_GCS_NO_REBOOT)
- rc = EIO;
+ switch (sc->tco_version)
+ {
+ case 1:
+ status = pci_read_config(sc->ich, ICH_GEN_STA, 1);
+ status &= ~ICH_GEN_STA_NO_REBOOT;
+ pci_write_config(sc->ich, ICH_GEN_STA, status, 1);
+ status = pci_read_config(sc->ich, ICH_GEN_STA, 1);
+ if (status & ICH_GEN_STA_NO_REBOOT)
+ rc = EIO;
+ break;
+
+ case 2:
+ status = ichwd_read_gcs_pmc_4(sc, 0);
+ status &= ~ICH_GCS_NO_REBOOT;
+ ichwd_write_gcs_pmc_4(sc, 0, status);
+ status = ichwd_read_gcs_pmc_4(sc, 0);
+ if (status & ICH_GCS_NO_REBOOT)
+ rc = EIO;
+ break;
+
+ case 3:
+ status = ichwd_read_gcs_pmc_4(sc, 0);
+ status &= ~ICH_PMC_NO_REBOOT;
+ ichwd_write_gcs_pmc_4(sc, 0, status);
+ status = ichwd_read_gcs_pmc_4(sc, 0);
+ if (status & ICH_PMC_NO_REBOOT)
+ rc = EIO;
+ break;
+
+ default:
+ ichwd_verbose_printf(sc->device,
+ "Unknown TCO Version: %d, can't set NO_REBOOT.\n",
+ sc->tco_version);
+ break;
}
if (rc)
@@ -463,7 +539,7 @@ ichwd_find_ich_lpc_bridge(struct ichwd_device **id_p)
return (NULL);
ichwd_verbose_printf(ich, "found ICH%d or equivalent chipset: %s\n",
- id->version, id->desc);
+ id->ich_version, id->desc);
if (id_p)
*id_p = id;
@@ -481,7 +557,7 @@ ichwd_identify(driver_t *driver, device_t parent)
struct ichwd_device *id_p;
device_t ich = NULL;
device_t dev;
- uint32_t rcba;
+ uint32_t base_address;
int rc;
ich = ichwd_find_ich_lpc_bridge(&id_p);
@@ -497,14 +573,40 @@ ichwd_identify(driver_t *driver, device_t parent)
device_set_desc_copy(dev, id_p->desc);
- if (id_p->version >= 6) {
- /* get RCBA (root complex base address) */
- rcba = pci_read_config(ich, ICH_RCBA, 4);
- rc = bus_set_resource(ich, SYS_RES_MEMORY, 0,
- (rcba & 0xffffc000) + ICH_GCS_OFFSET, ICH_GCS_SIZE);
- if (rc)
+ switch (id_p->tco_version)
+ {
+ case 1:
+ break;
+
+ case 2:
+ /* get RCBA (root complex base address) */
+ base_address = pci_read_config(ich, ICH_RCBA, 4);
+ rc = bus_set_resource(ich, SYS_RES_MEMORY, 0,
+ (base_address & 0xffffc000) + ICH_GCS_OFFSET,
+ ICH_GCS_SIZE);
+ if (rc)
+ ichwd_verbose_printf(dev,
+ "Can not set TCO v%d memory resource for RCBA\n",
+ id_p->tco_version);
+ break;
+
+ case 3:
+ /* get PBASE (Power Management Controller base address) */
+ base_address = pci_read_config(ich, ICH_PBASE, 4);
+ rc = bus_set_resource(ich, SYS_RES_MEMORY, 0,
+ (base_address & 0xfffffe00) + ICH_PMC_OFFSET,
+ ICH_PMC_SIZE);
+ if (rc)
+ ichwd_verbose_printf(dev,
+ "Can not set TCO v%d memory resource for PBASE\n",
+ id_p->tco_version);
+ break;
+
+ default:
ichwd_verbose_printf(dev,
- "Can not set memory resource for RCBA\n");
+ "Can not set unknown TCO v%d memory resource for unknown base address\n",
+ id_p->tco_version);
+ break;
}
}
@@ -535,7 +637,8 @@ ichwd_attach(device_t dev)
goto fail;
}
sc->ich = ich;
- sc->ich_version = id_p->version;
+ sc->ich_version = id_p->ich_version;
+ sc->tco_version = id_p->tco_version;
/* get ACPI base address */
pmbase = pci_read_config(ich, ICH_PMBASE, 2) & ICH_PMBASE_MASK;
@@ -564,7 +667,7 @@ ichwd_attach(device_t dev)
}
sc->gcs_rid = 0;
- if (sc->ich_version >= 6) {
+ if (sc->tco_version >= 2) {
sc->gcs_res = bus_alloc_resource_any(ich, SYS_RES_MEMORY,
&sc->gcs_rid, RF_ACTIVE|RF_SHAREABLE);
if (sc->gcs_res == NULL) {
@@ -577,7 +680,7 @@ ichwd_attach(device_t dev)
goto fail;
ichwd_verbose_printf(dev, "%s (ICH%d or equivalent)\n",
- device_get_desc(dev), sc->ich_version);
+ id_p->desc, sc->ich_version);
/*
* Determine if we are coming up after a watchdog-induced reset. Some
diff --git a/sys/dev/ichwd/ichwd.h b/sys/dev/ichwd/ichwd.h
index 0699279..dc24a9d 100644
--- a/sys/dev/ichwd/ichwd.h
+++ b/sys/dev/ichwd/ichwd.h
@@ -34,13 +34,15 @@
struct ichwd_device {
uint16_t device;
char *desc;
- unsigned int version;
+ unsigned int ich_version;
+ unsigned int tco_version;
};
struct ichwd_softc {
device_t device;
device_t ich;
int ich_version;
+ int tco_version;
int active;
unsigned int timeout;
@@ -59,6 +61,7 @@ struct ichwd_softc {
};
#define VENDORID_INTEL 0x8086
+#define DEVICEID_BAYTRAIL 0x0f1c
#define DEVICEID_CPT0 0x1c40
#define DEVICEID_CPT1 0x1c41
#define DEVICEID_CPT2 0x1c42
@@ -125,6 +128,11 @@ struct ichwd_softc {
#define DEVICEID_PPT29 0x1e5d
#define DEVICEID_PPT30 0x1e5e
#define DEVICEID_PPT31 0x1e5f
+#define DEVICEID_AVN0 0x1f38
+#define DEVICEID_AVN1 0x1f39
+#define DEVICEID_AVN2 0x1f3a
+#define DEVICEID_AVN3 0x1f3b
+#define DEVICEID_BRASWELL 0x229c
#define DEVICEID_DH89XXCC_LPC 0x2310
#define DEVICEID_COLETOCRK_LPC 0x2390
#define DEVICEID_82801AA 0x2410
@@ -210,9 +218,58 @@ struct ichwd_softc {
#define DEVICEID_LPT29 0x8c5d
#define DEVICEID_LPT30 0x8c5e
#define DEVICEID_LPT31 0x8c5f
+#define DEVICEID_WCPT1 0x8cc1
#define DEVICEID_WCPT2 0x8cc2
+#define DEVICEID_WCPT3 0x8cc3
#define DEVICEID_WCPT4 0x8cc4
#define DEVICEID_WCPT6 0x8cc6
+#define DEVICEID_WBG0 0x8d40
+#define DEVICEID_WBG1 0x8d41
+#define DEVICEID_WBG2 0x8d42
+#define DEVICEID_WBG3 0x8d43
+#define DEVICEID_WBG4 0x8d44
+#define DEVICEID_WBG5 0x8d45
+#define DEVICEID_WBG6 0x8d46
+#define DEVICEID_WBG7 0x8d47
+#define DEVICEID_WBG8 0x8d48
+#define DEVICEID_WBG9 0x8d49
+#define DEVICEID_WBG10 0x8d4a
+#define DEVICEID_WBG11 0x8d4b
+#define DEVICEID_WBG12 0x8d4c
+#define DEVICEID_WBG13 0x8d4d
+#define DEVICEID_WBG14 0x8d4e
+#define DEVICEID_WBG15 0x8d4f
+#define DEVICEID_WBG16 0x8d50
+#define DEVICEID_WBG17 0x8d51
+#define DEVICEID_WBG18 0x8d52
+#define DEVICEID_WBG19 0x8d53
+#define DEVICEID_WBG20 0x8d54
+#define DEVICEID_WBG21 0x8d55
+#define DEVICEID_WBG22 0x8d56
+#define DEVICEID_WBG23 0x8d57
+#define DEVICEID_WBG24 0x8d58
+#define DEVICEID_WBG25 0x8d59
+#define DEVICEID_WBG26 0x8d5a
+#define DEVICEID_WBG27 0x8d5b
+#define DEVICEID_WBG28 0x8d5c
+#define DEVICEID_WBG29 0x8d5d
+#define DEVICEID_WBG30 0x8d5e
+#define DEVICEID_WBG31 0x8d5f
+#define DEVICEID_LPT_LP0 0x9c40
+#define DEVICEID_LPT_LP1 0x9c41
+#define DEVICEID_LPT_LP2 0x9c42
+#define DEVICEID_LPT_LP3 0x9c43
+#define DEVICEID_LPT_LP4 0x9c44
+#define DEVICEID_LPT_LP5 0x9c45
+#define DEVICEID_LPT_LP6 0x9c46
+#define DEVICEID_LPT_LP7 0x9c47
+#define DEVICEID_WCPT_LP1 0x9cc1
+#define DEVICEID_WCPT_LP2 0x9cc2
+#define DEVICEID_WCPT_LP3 0x9cc3
+#define DEVICEID_WCPT_LP5 0x9cc5
+#define DEVICEID_WCPT_LP6 0x9cc6
+#define DEVICEID_WCPT_LP7 0x9cc7
+#define DEVICEID_WCPT_LP9 0x9cc9
/* ICH LPC Interface Bridge Registers (ICH5 and older) */
#define ICH_GEN_STA 0xd4
@@ -226,6 +283,12 @@ struct ichwd_softc {
#define ICH_GCS_SIZE 0x4
#define ICH_GCS_NO_REBOOT 0x20
+/* SoC Power Management Configuration Registers */
+#define ICH_PBASE 0x44
+#define ICH_PMC_OFFSET 0x08
+#define ICH_PMC_SIZE 0x4
+#define ICH_PMC_NO_REBOOT 0x10
+
/* register names and locations (relative to PMBASE) */
#define SMI_BASE 0x30 /* base address for SMI registers */
#define SMI_LEN 0x08
diff --git a/sys/dev/ixgbe/if_ix.c b/sys/dev/ixgbe/if_ix.c
index 65e868a..48ee76b 100644
--- a/sys/dev/ixgbe/if_ix.c
+++ b/sys/dev/ixgbe/if_ix.c
@@ -718,9 +718,7 @@ ixgbe_detach(device_t dev)
for (int i = 0; i < adapter->num_queues; i++, que++, txr++) {
if (que->tq) {
-#ifndef IXGBE_LEGACY_TX
taskqueue_drain(que->tq, &txr->txq_task);
-#endif
taskqueue_drain(que->tq, &que->que_task);
taskqueue_free(que->tq);
}
@@ -1464,13 +1462,10 @@ ixgbe_handle_que(void *context, int pending)
ixgbe_rxeof(que);
IXGBE_TX_LOCK(txr);
ixgbe_txeof(txr);
-#ifndef IXGBE_LEGACY_TX
if (!drbr_empty(ifp, txr->br))
ixgbe_mq_start_locked(ifp, txr);
-#else
if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
ixgbe_start_locked(txr, ifp);
-#endif
IXGBE_TX_UNLOCK(txr);
}
@@ -1513,13 +1508,10 @@ ixgbe_legacy_irq(void *arg)
IXGBE_TX_LOCK(txr);
ixgbe_txeof(txr);
-#ifdef IXGBE_LEGACY_TX
if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
ixgbe_start_locked(txr, ifp);
-#else
if (!drbr_empty(ifp, txr->br))
ixgbe_mq_start_locked(ifp, txr);
-#endif
IXGBE_TX_UNLOCK(txr);
/* Check for fan failure */
@@ -1575,13 +1567,10 @@ ixgbe_msix_que(void *arg)
IXGBE_TX_LOCK(txr);
ixgbe_txeof(txr);
-#ifdef IXGBE_LEGACY_TX
- if (!IFQ_DRV_IS_EMPTY(ifp->if_snd))
+ if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
ixgbe_start_locked(txr, ifp);
-#else
if (!drbr_empty(ifp, txr->br))
ixgbe_mq_start_locked(ifp, txr);
-#endif
IXGBE_TX_UNLOCK(txr);
/* Do AIM now? */
@@ -2398,9 +2387,7 @@ ixgbe_allocate_legacy(struct adapter *adapter)
{
device_t dev = adapter->dev;
struct ix_queue *que = adapter->queues;
-#ifndef IXGBE_LEGACY_TX
struct tx_ring *txr = adapter->tx_rings;
-#endif
int error, rid = 0;
/* MSI RID at 1 */
@@ -2420,9 +2407,7 @@ ixgbe_allocate_legacy(struct adapter *adapter)
* Try allocating a fast interrupt and the associated deferred
* processing contexts.
*/
-#ifndef IXGBE_LEGACY_TX
TASK_INIT(&txr->txq_task, 0, ixgbe_deferred_mq_start, txr);
-#endif
TASK_INIT(&que->que_task, 0, ixgbe_handle_que, que);
que->tq = taskqueue_create_fast("ixgbe_que", M_NOWAIT,
taskqueue_thread_enqueue, &que->tq);
@@ -2555,9 +2540,7 @@ ixgbe_allocate_msix(struct adapter *adapter)
#endif /* IXGBE_DEBUG */
-#ifndef IXGBE_LEGACY_TX
TASK_INIT(&txr->txq_task, 0, ixgbe_deferred_mq_start, txr);
-#endif
TASK_INIT(&que->que_task, 0, ixgbe_handle_que, que);
que->tq = taskqueue_create_fast("ixgbe_que", M_NOWAIT,
taskqueue_thread_enqueue, &que->tq);
@@ -2840,15 +2823,15 @@ ixgbe_setup_interface(device_t dev, struct adapter *adapter)
ifp->if_hw_tsomaxsegcount = IXGBE_82599_SCATTER;
ifp->if_hw_tsomaxsegsize = 2048;
#endif
-#ifndef IXGBE_LEGACY_TX
+
ifp->if_transmit = ixgbe_mq_start;
ifp->if_qflush = ixgbe_qflush;
-#else
+
ifp->if_start = ixgbe_start;
IFQ_SET_MAXLEN(&ifp->if_snd, adapter->num_tx_desc - 2);
ifp->if_snd.ifq_drv_maxlen = adapter->num_tx_desc - 2;
IFQ_SET_READY(&ifp->if_snd);
-#endif
+
ether_ifattach(ifp, adapter->hw.mac.addr);
diff --git a/sys/dev/ixgbe/if_ixv.c b/sys/dev/ixgbe/if_ixv.c
index 914f742..f47cf60 100644
--- a/sys/dev/ixgbe/if_ixv.c
+++ b/sys/dev/ixgbe/if_ixv.c
@@ -871,13 +871,10 @@ ixv_msix_que(void *arg)
** has anything queued the task gets
** scheduled to handle it.
*/
-#ifdef IXGBE_LEGACY_TX
if (!IFQ_DRV_IS_EMPTY(&adapter->ifp->if_snd))
ixgbe_start_locked(txr, ifp);
-#else
if (!drbr_empty(adapter->ifp, txr->br))
ixgbe_mq_start_locked(ifp, txr);
-#endif
IXGBE_TX_UNLOCK(txr);
/* Do AIM now? */
diff --git a/sys/dev/ixgbe/ix_txrx.c b/sys/dev/ixgbe/ix_txrx.c
index 9e90e0d..ef42714 100644
--- a/sys/dev/ixgbe/ix_txrx.c
+++ b/sys/dev/ixgbe/ix_txrx.c
@@ -102,7 +102,6 @@ static __inline void ixgbe_rx_discard(struct rx_ring *, int);
static __inline void ixgbe_rx_input(struct rx_ring *, struct ifnet *,
struct mbuf *, u32);
-#ifdef IXGBE_LEGACY_TX
/*********************************************************************
* Transmit entry point
*
@@ -164,7 +163,6 @@ ixgbe_start(struct ifnet *ifp)
return;
}
-#else /* ! IXGBE_LEGACY_TX */
/*
** Multiqueue Transmit Entry Point
@@ -316,7 +314,6 @@ ixgbe_qflush(struct ifnet *ifp)
}
if_qflush(ifp);
}
-#endif /* IXGBE_LEGACY_TX */
/*********************************************************************
@@ -697,10 +694,8 @@ ixgbe_free_transmit_buffers(struct tx_ring *txr)
tx_buffer->map = NULL;
}
}
-#ifdef IXGBE_LEGACY_TX
if (txr->br != NULL)
buf_ring_free(txr->br, M_DEVBUF);
-#endif
if (txr->tx_buffers != NULL) {
free(txr->tx_buffers, M_DEVBUF);
txr->tx_buffers = NULL;
@@ -2187,7 +2182,6 @@ ixgbe_allocate_queues(struct adapter *adapter)
error = ENOMEM;
goto err_tx_desc;
}
-#ifndef IXGBE_LEGACY_TX
/* Allocate a buf ring */
txr->br = buf_ring_alloc(IXGBE_BR_SIZE, M_DEVBUF,
M_WAITOK, &txr->tx_mtx);
@@ -2197,7 +2191,6 @@ ixgbe_allocate_queues(struct adapter *adapter)
error = ENOMEM;
goto err_tx_desc;
}
-#endif
}
/*
diff --git a/sys/dev/ixgbe/ixgbe.h b/sys/dev/ixgbe/ixgbe.h
index 558b532..008ced3 100644
--- a/sys/dev/ixgbe/ixgbe.h
+++ b/sys/dev/ixgbe/ixgbe.h
@@ -728,15 +728,12 @@ ixv_check_ether_addr(u8 *addr)
/* Shared Prototypes */
-#ifdef IXGBE_LEGACY_TX
void ixgbe_start(struct ifnet *);
void ixgbe_start_locked(struct tx_ring *, struct ifnet *);
-#else /* ! IXGBE_LEGACY_TX */
int ixgbe_mq_start(struct ifnet *, struct mbuf *);
int ixgbe_mq_start_locked(struct ifnet *, struct tx_ring *);
void ixgbe_qflush(struct ifnet *);
void ixgbe_deferred_mq_start(void *, int);
-#endif /* IXGBE_LEGACY_TX */
int ixgbe_allocate_queues(struct adapter *);
int ixgbe_allocate_transmit_buffers(struct tx_ring *);
diff --git a/sys/dev/oce/oce_if.c b/sys/dev/oce/oce_if.c
index f37ef3a..3711503 100644
--- a/sys/dev/oce/oce_if.c
+++ b/sys/dev/oce/oce_if.c
@@ -1060,11 +1060,10 @@ oce_tx_restart(POCE_SOFTC sc, struct oce_wq *wq)
if ((sc->ifp->if_drv_flags & IFF_DRV_RUNNING) != IFF_DRV_RUNNING)
return;
-#if __FreeBSD_version >= 800000
if (!drbr_empty(sc->ifp, wq->br))
-#else
+ taskqueue_enqueue_fast(taskqueue_swi, &wq->txtask);
+
if (!IFQ_DRV_IS_EMPTY(&sc->ifp->if_snd))
-#endif
taskqueue_enqueue_fast(taskqueue_swi, &wq->txtask);
}
@@ -1147,7 +1146,7 @@ oce_tx_task(void *arg, int npending)
struct ifnet *ifp = sc->ifp;
int rc = 0;
-#if __FreeBSD_version >= 800000
+
LOCK(&wq->tx_lock);
rc = oce_multiq_transmit(ifp, NULL, wq);
if (rc) {
@@ -1155,9 +1154,9 @@ oce_tx_task(void *arg, int npending)
"TX[%d] restart failed\n", wq->queue_index);
}
UNLOCK(&wq->tx_lock);
-#else
+
oce_start(ifp);
-#endif
+
}
diff --git a/sys/dev/random/hash.c b/sys/dev/random/hash.c
index cf0feaa..e37f090 100644
--- a/sys/dev/random/hash.c
+++ b/sys/dev/random/hash.c
@@ -45,7 +45,7 @@ randomdev_hash_init(struct randomdev_hash *context)
/* Iterate the hash */
void
-randomdev_hash_iterate(struct randomdev_hash *context, void *data, size_t size)
+randomdev_hash_iterate(struct randomdev_hash *context, const void *data, size_t size)
{
SHA256_Update(&context->sha, data, size);
}
@@ -64,7 +64,7 @@ randomdev_hash_finish(struct randomdev_hash *context, void *buf)
* data. Use CBC mode for better avalanche.
*/
void
-randomdev_encrypt_init(struct randomdev_key *context, void *data)
+randomdev_encrypt_init(struct randomdev_key *context, const void *data)
{
rijndael_cipherInit(&context->cipher, MODE_CBC, NULL);
rijndael_makeKey(&context->key, DIR_ENCRYPT, KEYSIZE*8, data);
@@ -75,7 +75,7 @@ randomdev_encrypt_init(struct randomdev_key *context, void *data)
* a multiple of BLOCKSIZE.
*/
void
-randomdev_encrypt(struct randomdev_key *context, void *d_in, void *d_out, unsigned length)
+randomdev_encrypt(struct randomdev_key *context, const void *d_in, void *d_out, unsigned length)
{
rijndael_blockEncrypt(&context->cipher, &context->key, d_in, length*8, d_out);
}
diff --git a/sys/dev/random/hash.h b/sys/dev/random/hash.h
index 4e6a4a0..8655d88 100644
--- a/sys/dev/random/hash.h
+++ b/sys/dev/random/hash.h
@@ -42,9 +42,9 @@ struct randomdev_key { /* Big! Make static! */
};
void randomdev_hash_init(struct randomdev_hash *);
-void randomdev_hash_iterate(struct randomdev_hash *, void *, size_t);
+void randomdev_hash_iterate(struct randomdev_hash *, const void *, size_t);
void randomdev_hash_finish(struct randomdev_hash *, void *);
-void randomdev_encrypt_init(struct randomdev_key *, void *);
-void randomdev_encrypt(struct randomdev_key *context, void *, void *, unsigned);
+void randomdev_encrypt_init(struct randomdev_key *, const void *);
+void randomdev_encrypt(struct randomdev_key *context, const void *, void *, unsigned);
#endif
diff --git a/sys/dev/usb/wlan/if_run.c b/sys/dev/usb/wlan/if_run.c
index 212408f..c4b09a0 100644
--- a/sys/dev/usb/wlan/if_run.c
+++ b/sys/dev/usb/wlan/if_run.c
@@ -318,7 +318,6 @@ static const STRUCT_USB_HOST_ID run_devs[] = {
RUN_DEV(ZINWELL, RT3072_2),
RUN_DEV(ZYXEL, RT2870_1),
RUN_DEV(ZYXEL, RT2870_2),
- RUN_DEV(ZYXEL, RT3070),
RUN_DEV_EJECT(ZYXEL, NWD2705),
RUN_DEV_EJECT(RALINK, RT_STOR),
#undef RUN_DEV_EJECT
diff --git a/sys/dev/usb/wlan/if_upgt.c b/sys/dev/usb/wlan/if_upgt.c
index 210be1f..1f60ebc 100644
--- a/sys/dev/usb/wlan/if_upgt.c
+++ b/sys/dev/usb/wlan/if_upgt.c
@@ -182,7 +182,7 @@ static const STRUCT_USB_HOST_ID upgt_devs[] = {
UPGT_DEV(FSC, E5400),
UPGT_DEV(GLOBESPAN, PRISM_GT_1),
UPGT_DEV(GLOBESPAN, PRISM_GT_2),
- UPGT_DEV(NETGEAR, WG111V1_2),
+ UPGT_DEV(NETGEAR, WG111V2_2),
UPGT_DEV(INTERSIL, PRISM_GT),
UPGT_DEV(SMC, 2862WG),
UPGT_DEV(USR, USR5422),
diff --git a/sys/dev/virtio/network/if_vtnet.c b/sys/dev/virtio/network/if_vtnet.c
index 5453998..a5e6383 100644
--- a/sys/dev/virtio/network/if_vtnet.c
+++ b/sys/dev/virtio/network/if_vtnet.c
@@ -139,23 +139,21 @@ static struct mbuf *
static int vtnet_txq_enqueue_buf(struct vtnet_txq *, struct mbuf **,
struct vtnet_tx_header *);
static int vtnet_txq_encap(struct vtnet_txq *, struct mbuf **);
-#ifdef VTNET_LEGACY_TX
+
static void vtnet_start_locked(struct vtnet_txq *, struct ifnet *);
static void vtnet_start(struct ifnet *);
-#else
+
static int vtnet_txq_mq_start_locked(struct vtnet_txq *, struct mbuf *);
static int vtnet_txq_mq_start(struct ifnet *, struct mbuf *);
static void vtnet_txq_tq_deferred(void *, int);
-#endif
+
static void vtnet_txq_start(struct vtnet_txq *);
static void vtnet_txq_tq_intr(void *, int);
static int vtnet_txq_eof(struct vtnet_txq *);
static void vtnet_tx_vq_intr(void *);
static void vtnet_tx_start_all(struct vtnet_softc *);
-#ifndef VTNET_LEGACY_TX
static void vtnet_qflush(struct ifnet *);
-#endif
static int vtnet_watchdog(struct vtnet_txq *);
static void vtnet_rxq_accum_stats(struct vtnet_rxq *,
@@ -922,16 +920,16 @@ vtnet_setup_interface(struct vtnet_softc *sc)
ifp->if_init = vtnet_init;
ifp->if_ioctl = vtnet_ioctl;
-#ifndef VTNET_LEGACY_TX
+
ifp->if_transmit = vtnet_txq_mq_start;
ifp->if_qflush = vtnet_qflush;
-#else
+
struct virtqueue *vq = sc->vtnet_txqs[0].vtntx_vq;
ifp->if_start = vtnet_start;
IFQ_SET_MAXLEN(&ifp->if_snd, virtqueue_size(vq) - 1);
ifp->if_snd.ifq_drv_maxlen = virtqueue_size(vq) - 1;
IFQ_SET_READY(&ifp->if_snd);
-#endif
+
ifmedia_init(&sc->vtnet_media, IFM_IMASK, vtnet_ifmedia_upd,
vtnet_ifmedia_sts);
@@ -2209,7 +2207,7 @@ fail:
return (error);
}
-#ifdef VTNET_LEGACY_TX
+
static void
vtnet_start_locked(struct vtnet_txq *txq, struct ifnet *ifp)
@@ -2275,7 +2273,7 @@ vtnet_start(struct ifnet *ifp)
VTNET_TXQ_UNLOCK(txq);
}
-#else /* !VTNET_LEGACY_TX */
+
static int
vtnet_txq_mq_start_locked(struct vtnet_txq *txq, struct mbuf *m)
@@ -2387,7 +2385,7 @@ vtnet_txq_tq_deferred(void *xtxq, int pending)
VTNET_TXQ_UNLOCK(txq);
}
-#endif /* VTNET_LEGACY_TX */
+
static void
vtnet_txq_start(struct vtnet_txq *txq)
@@ -2398,13 +2396,13 @@ vtnet_txq_start(struct vtnet_txq *txq)
sc = txq->vtntx_sc;
ifp = sc->vtnet_ifp;
-#ifdef VTNET_LEGACY_TX
+
if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
vtnet_start_locked(txq, ifp);
-#else
+
if (!drbr_empty(ifp, txq->vtntx_br))
vtnet_txq_mq_start_locked(txq, NULL);
-#endif
+
}
static void
diff --git a/sys/dev/vmware/vmxnet3/if_vmx.c b/sys/dev/vmware/vmxnet3/if_vmx.c
index e92cc00..0629f2b 100644
--- a/sys/dev/vmware/vmxnet3/if_vmx.c
+++ b/sys/dev/vmware/vmxnet3/if_vmx.c
@@ -166,15 +166,15 @@ static int vmxnet3_txq_load_mbuf(struct vmxnet3_txqueue *, struct mbuf **,
bus_dmamap_t, bus_dma_segment_t [], int *);
static void vmxnet3_txq_unload_mbuf(struct vmxnet3_txqueue *, bus_dmamap_t);
static int vmxnet3_txq_encap(struct vmxnet3_txqueue *, struct mbuf **);
-#ifdef VMXNET3_LEGACY_TX
+
static void vmxnet3_start_locked(struct ifnet *);
static void vmxnet3_start(struct ifnet *);
-#else
+
static int vmxnet3_txq_mq_start_locked(struct vmxnet3_txqueue *,
struct mbuf *);
static int vmxnet3_txq_mq_start(struct ifnet *, struct mbuf *);
static void vmxnet3_txq_tq_deferred(void *, int);
-#endif
+
static void vmxnet3_txq_start(struct vmxnet3_txqueue *);
static void vmxnet3_tx_start_all(struct vmxnet3_softc *);
@@ -1731,15 +1731,15 @@ vmxnet3_setup_interface(struct vmxnet3_softc *sc)
ifp->if_hw_tsomaxsegcount = VMXNET3_TX_MAXSEGS;
ifp->if_hw_tsomaxsegsize = VMXNET3_TX_MAXSEGSIZE;
-#ifdef VMXNET3_LEGACY_TX
+
ifp->if_start = vmxnet3_start;
ifp->if_snd.ifq_drv_maxlen = sc->vmx_ntxdescs - 1;
IFQ_SET_MAXLEN(&ifp->if_snd, sc->vmx_ntxdescs - 1);
IFQ_SET_READY(&ifp->if_snd);
-#else
+
ifp->if_transmit = vmxnet3_txq_mq_start;
ifp->if_qflush = vmxnet3_qflush;
-#endif
+
vmxnet3_get_lladdr(sc);
ether_ifattach(ifp, sc->vmx_lladdr);
@@ -2872,7 +2872,7 @@ vmxnet3_txq_encap(struct vmxnet3_txqueue *txq, struct mbuf **m0)
return (0);
}
-#ifdef VMXNET3_LEGACY_TX
+
static void
vmxnet3_start_locked(struct ifnet *ifp)
@@ -2936,7 +2936,7 @@ vmxnet3_start(struct ifnet *ifp)
VMXNET3_TXQ_UNLOCK(txq);
}
-#else /* !VMXNET3_LEGACY_TX */
+
static int
vmxnet3_txq_mq_start_locked(struct vmxnet3_txqueue *txq, struct mbuf *m)
@@ -3043,7 +3043,7 @@ vmxnet3_txq_tq_deferred(void *xtxq, int pending)
VMXNET3_TXQ_UNLOCK(txq);
}
-#endif /* VMXNET3_LEGACY_TX */
+
static void
vmxnet3_txq_start(struct vmxnet3_txqueue *txq)
@@ -3054,13 +3054,13 @@ vmxnet3_txq_start(struct vmxnet3_txqueue *txq)
sc = txq->vxtxq_sc;
ifp = sc->vmx_ifp;
-#ifdef VMXNET3_LEGACY_TX
+
if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
vmxnet3_start_locked(ifp);
-#else
+
if (!drbr_empty(ifp, txq->vxtxq_br))
vmxnet3_txq_mq_start_locked(txq, NULL);
-#endif
+
}
static void
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