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-rw-r--r--sys/dev/pci/eisa_pci.c127
-rw-r--r--sys/dev/pci/fixup_pci.c100
-rw-r--r--sys/dev/pci/ignore_pci.c70
-rw-r--r--sys/dev/pci/isa_pci.c239
-rw-r--r--sys/dev/pci/pci.c1414
-rw-r--r--sys/dev/pci/pci_if.m79
-rw-r--r--sys/dev/pci/pci_pci.c528
-rw-r--r--sys/dev/pci/pci_private.h72
-rw-r--r--sys/dev/pci/pci_user.c492
-rw-r--r--sys/dev/pci/pcib_if.m81
-rw-r--r--sys/dev/pci/pcib_private.h77
-rw-r--r--sys/dev/pci/pcireg.h319
-rw-r--r--sys/dev/pci/pcivar.h326
13 files changed, 3924 insertions, 0 deletions
diff --git a/sys/dev/pci/eisa_pci.c b/sys/dev/pci/eisa_pci.c
new file mode 100644
index 0000000..6572801
--- /dev/null
+++ b/sys/dev/pci/eisa_pci.c
@@ -0,0 +1,127 @@
+/*-
+ * Copyright (c) 1994,1995 Stefan Esser, Wolfgang StanglMeier
+ * Copyright (c) 2000 Michael Smith <msmith@freebsd.org>
+ * Copyright (c) 2000 BSDi
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+/*
+ * PCI:EISA bridge support
+ */
+
+#include <sys/param.h>
+#include <sys/kernel.h>
+#include <sys/bus.h>
+
+#include <pci/pcivar.h>
+#include <pci/pcireg.h>
+
+static int eisab_probe(device_t dev);
+static int eisab_attach(device_t dev);
+
+static device_method_t eisab_methods[] = {
+ /* Device interface */
+ DEVMETHOD(device_probe, eisab_probe),
+ DEVMETHOD(device_attach, eisab_attach),
+ DEVMETHOD(device_shutdown, bus_generic_shutdown),
+ DEVMETHOD(device_suspend, bus_generic_suspend),
+ DEVMETHOD(device_resume, bus_generic_resume),
+
+ /* Bus interface */
+ DEVMETHOD(bus_print_child, bus_generic_print_child),
+ DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource),
+ DEVMETHOD(bus_release_resource, bus_generic_release_resource),
+ DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
+ DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
+ DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
+ DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
+
+ { 0, 0 }
+};
+
+static driver_t eisab_driver = {
+ "eisab",
+ eisab_methods,
+ 0,
+};
+
+static devclass_t eisab_devclass;
+
+DRIVER_MODULE(eisab, pci, eisab_driver, eisab_devclass, 0, 0);
+
+static int
+eisab_probe(device_t dev)
+{
+ int matched = 0;
+
+ /*
+ * Generic match by class/subclass.
+ */
+ if ((pci_get_class(dev) == PCIC_BRIDGE) &&
+ (pci_get_subclass(dev) == PCIS_BRIDGE_EISA))
+ matched = 1;
+
+ /*
+ * Some bridges don't correctly report their class.
+ */
+ switch (pci_get_devid(dev)) {
+ case 0x04828086: /* may show up as PCI-HOST or 0:0 */
+ matched = 1;
+ break;
+ default:
+ break;
+ }
+
+ if (matched) {
+ device_set_desc(dev, "PCI-EISA bridge");
+ return(-10000);
+ }
+ return(ENXIO);
+}
+
+static int
+eisab_attach(device_t dev)
+{
+ /*
+ * Attach an EISA bus. Note that we can only have one EISA bus.
+ */
+ if (!devclass_get_device(devclass_find("eisa"), 0))
+ device_add_child(dev, "eisa", -1);
+
+ /*
+ * Attach an ISA bus as well, since the EISA bus may have ISA
+ * cards installed, and we may have no EISA support in the system.
+ */
+ if (!devclass_get_device(devclass_find("isa"), 0))
+ device_add_child(dev, "isa", -1);
+
+ bus_generic_attach(dev);
+
+ return(0);
+}
+
diff --git a/sys/dev/pci/fixup_pci.c b/sys/dev/pci/fixup_pci.c
new file mode 100644
index 0000000..df487b2
--- /dev/null
+++ b/sys/dev/pci/fixup_pci.c
@@ -0,0 +1,100 @@
+/*-
+ * Copyright (c) 1994,1995 Stefan Esser, Wolfgang StanglMeier
+ * Copyright (c) 2000 Michael Smith <msmith@freebsd.org>
+ * Copyright (c) 2000 BSDi
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/malloc.h>
+#include <sys/kernel.h>
+#include <sys/bus.h>
+
+#include <pci/pcivar.h>
+#include <pci/pcireg.h>
+
+/*
+ * Chipset fixups.
+ *
+ * These routines are invoked during the probe phase for devices which
+ * typically don't have specific device drivers, but which require
+ * some cleaning up.
+ */
+
+static int fixup_pci_probe(device_t dev);
+static void fixwsc_natoma(device_t dev);
+
+static device_method_t fixup_pci_methods[] = {
+ /* Device interface */
+ DEVMETHOD(device_probe, fixup_pci_probe),
+ DEVMETHOD(device_attach, bus_generic_attach),
+ { 0, 0 }
+};
+
+static driver_t fixup_pci_driver = {
+ "fixup_pci",
+ fixup_pci_methods,
+ 0,
+};
+
+static devclass_t fixup_pci_devclass;
+
+DRIVER_MODULE(fixup_pci, pci, fixup_pci_driver, fixup_pci_devclass, 0, 0);
+
+static int
+fixup_pci_probe(device_t dev)
+{
+ switch (pci_get_devid(dev)) {
+ case 0x12378086: /* Intel 82440FX (Natoma) */
+ fixwsc_natoma(dev);
+ break;
+ }
+ return(ENXIO);
+}
+
+static void
+fixwsc_natoma(device_t dev)
+{
+ int pmccfg;
+
+ pmccfg = pci_read_config(dev, 0x50, 2);
+#if defined(SMP)
+ if (pmccfg & 0x8000) {
+ printf("Correcting Natoma config for SMP\n");
+ pmccfg &= ~0x8000;
+ pci_write_config(dev, 0x50, pmccfg, 2);
+ }
+#else
+ if ((pmccfg & 0x8000) == 0) {
+ printf("Correcting Natoma config for non-SMP\n");
+ pmccfg |= 0x8000;
+ pci_write_config(dev, 0x50, pmccfg, 2);
+ }
+#endif
+}
diff --git a/sys/dev/pci/ignore_pci.c b/sys/dev/pci/ignore_pci.c
new file mode 100644
index 0000000..520099d
--- /dev/null
+++ b/sys/dev/pci/ignore_pci.c
@@ -0,0 +1,70 @@
+/*-
+ * Copyright (c) 2000 Michael Smith <msmith@freebsd.org>
+ * Copyright (c) 2000 BSDi
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+/*
+ * 'Ignore' driver - eats devices that show up errnoeously on PCI
+ * but shouldn't ever be listed or handled by a driver.
+ */
+
+#include <sys/param.h>
+#include <sys/kernel.h>
+#include <sys/bus.h>
+
+#include <pci/pcivar.h>
+
+static int ignore_pci_probe(device_t dev);
+
+static device_method_t ignore_pci_methods[] = {
+ /* Device interface */
+ DEVMETHOD(device_probe, ignore_pci_probe),
+ DEVMETHOD(device_attach, bus_generic_attach),
+ { 0, 0 }
+};
+
+static driver_t ignore_pci_driver = {
+ "ignore_pci",
+ ignore_pci_methods,
+ 0,
+};
+
+static devclass_t ignore_pci_devclass;
+
+DRIVER_MODULE(ignore_pci, pci, ignore_pci_driver, ignore_pci_devclass, 0, 0);
+
+static int
+ignore_pci_probe(device_t dev)
+{
+ switch (pci_get_devid(dev)) {
+ case 0x10001042ul: /* SMC 37C665 */
+ device_set_desc(dev, "ignored");
+ device_quiet(dev);
+ return(-10000);
+ }
+ return(ENXIO);
+}
diff --git a/sys/dev/pci/isa_pci.c b/sys/dev/pci/isa_pci.c
new file mode 100644
index 0000000..5690df1
--- /dev/null
+++ b/sys/dev/pci/isa_pci.c
@@ -0,0 +1,239 @@
+/*-
+ * Copyright (c) 1994,1995 Stefan Esser, Wolfgang StanglMeier
+ * Copyright (c) 2000 Michael Smith <msmith@freebsd.org>
+ * Copyright (c) 2000 BSDi
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+/*
+ * PCI:ISA bridge support
+ */
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+#include <machine/bus.h>
+#include <machine/resource.h>
+#include <sys/bus.h>
+#include <sys/rman.h>
+
+#include <pci/pcivar.h>
+#include <pci/pcireg.h>
+
+#define ELCR_IOADDR 0x4d0 /* Interrupt Edge/Level Control Registers */
+#define ELCR_IOLEN 2
+
+struct isab_softc {
+ struct resource *elcr_res;
+ u_char saved_elcr[ELCR_IOLEN];
+};
+
+static int isab_probe(device_t dev);
+static int isab_attach(device_t dev);
+static int isab_detach(device_t dev);
+static int isab_resume(device_t dev);
+static int isab_suspend(device_t dev);
+
+static device_method_t isab_methods[] = {
+ /* Device interface */
+ DEVMETHOD(device_probe, isab_probe),
+ DEVMETHOD(device_attach, isab_attach),
+ DEVMETHOD(device_detach, isab_detach),
+ DEVMETHOD(device_shutdown, bus_generic_shutdown),
+ DEVMETHOD(device_suspend, isab_suspend),
+ DEVMETHOD(device_resume, isab_resume),
+
+ /* Bus interface */
+ DEVMETHOD(bus_print_child, bus_generic_print_child),
+ DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource),
+ DEVMETHOD(bus_release_resource, bus_generic_release_resource),
+ DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
+ DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
+ DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
+ DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
+
+ { 0, 0 }
+};
+
+static driver_t isab_driver = {
+ "isab",
+ isab_methods,
+ sizeof(struct isab_softc),
+};
+
+static devclass_t isab_devclass;
+
+DRIVER_MODULE(isab, pci, isab_driver, isab_devclass, 0, 0);
+
+/*
+ * XXX we need to add a quirk list here for bridges that don't correctly
+ * report themselves.
+ */
+static int
+isab_probe(device_t dev)
+{
+ int matched = 0;
+
+ /*
+ * Try for a generic match based on class/subclass.
+ */
+ if ((pci_get_class(dev) == PCIC_BRIDGE) &&
+ (pci_get_subclass(dev) == PCIS_BRIDGE_ISA)) {
+ matched = 1;
+ } else {
+ /*
+ * These are devices that we *know* are PCI:ISA bridges.
+ * Sometimes, however, they don't report themselves as
+ * such. Check in case one of them is pretending to be
+ * something else.
+ */
+ switch (pci_get_devid(dev)) {
+ case 0x04848086: /* Intel 82378ZB/82378IB */
+ case 0x122e8086: /* Intel 82371FB */
+ case 0x70008086: /* Intel 82371SB */
+ case 0x71108086: /* Intel 82371AB */
+ case 0x71988086: /* Intel 82443MX */
+ case 0x24108086: /* Intel 82801AA (ICH) */
+ case 0x24208086: /* Intel 82801AB (ICH0) */
+ case 0x24408086: /* Intel 82801AB (ICH2) */
+ case 0x00061004: /* VLSI 82C593 */
+ case 0x05861106: /* VIA 82C586 */
+ case 0x05961106: /* VIA 82C596 */
+ case 0x06861106: /* VIA 82C686 */
+ case 0x153310b9: /* AcerLabs M1533 */
+ case 0x154310b9: /* AcerLabs M1543 */
+ case 0x00081039: /* SiS 85c503 */
+ case 0x00001078: /* Cyrix Cx5510 */
+ case 0x01001078: /* Cyrix Cx5530 */
+ case 0xc7001045: /* OPTi 82C700 (FireStar) */
+ case 0x00011033: /* NEC 0001 (C-bus) */
+ case 0x002c1033: /* NEC 002C (C-bus) */
+ case 0x003b1033: /* NEC 003B (C-bus) */
+ case 0x886a1060: /* UMC UM8886 ISA */
+ case 0x02001166: /* ServerWorks IB6566 PCI */
+ if (bootverbose)
+ printf("PCI-ISA bridge with incorrect subclass 0x%x\n",
+ pci_get_subclass(dev));
+ matched = 1;
+ break;
+
+ default:
+ break;
+ }
+ }
+
+ if (matched) {
+ device_set_desc(dev, "PCI-ISA bridge");
+ return(-10000);
+ }
+ return(ENXIO);
+}
+
+static int
+isab_attach(device_t dev)
+{
+ device_t child;
+ struct isab_softc *sc = device_get_softc(dev);
+ int error, rid;
+
+ /*
+ * Attach an ISA bus. Note that we can only have one ISA bus.
+ */
+ child = device_add_child(dev, "isa", 0);
+ if (child != NULL) {
+ error = bus_generic_attach(dev);
+ if (error)
+ return (error);
+ }
+
+ switch (pci_get_devid(dev)) {
+ case 0x71108086: /* Intel 82371AB */
+ /*
+ * Sometimes the ELCR (Edge/Level Control Register) is not restored
+ * correctly on resume by the BIOS, so we handle it ourselves.
+ */
+ rid = 0;
+ bus_set_resource(dev, SYS_RES_IOPORT, rid, ELCR_IOADDR, ELCR_IOLEN);
+ sc->elcr_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 0, ~0, 1,
+ RF_ACTIVE);
+ if (sc->elcr_res == NULL)
+ device_printf(dev, "failed to allocate ELCR resource\n");
+ break;
+ }
+
+ return(0);
+}
+
+static int
+isab_detach(device_t dev)
+{
+ struct isab_softc *sc = device_get_softc(dev);
+
+ if (sc->elcr_res != NULL)
+ bus_release_resource(dev, SYS_RES_IOPORT, 0, sc->elcr_res);
+
+ return (bus_generic_detach(dev));
+}
+
+static int
+isab_suspend(device_t dev)
+{
+ struct isab_softc *sc = device_get_softc(dev);
+ bus_space_tag_t bst;
+ bus_space_handle_t bsh;
+ int i;
+
+ /* Save the ELCR if required. */
+ if (sc->elcr_res != NULL) {
+ bst = rman_get_bustag(sc->elcr_res);
+ bsh = rman_get_bushandle(sc->elcr_res);
+ for (i = 0; i < ELCR_IOLEN; i++)
+ sc->saved_elcr[i] = bus_space_read_1(bst, bsh, i);
+ }
+
+ return (bus_generic_suspend(dev));
+}
+
+static int
+isab_resume(device_t dev)
+{
+ struct isab_softc *sc = device_get_softc(dev);
+ bus_space_tag_t bst;
+ bus_space_handle_t bsh;
+ int i;
+
+ /* Restore the ELCR if required. */
+ if (sc->elcr_res != NULL) {
+ bst = rman_get_bustag(sc->elcr_res);
+ bsh = rman_get_bushandle(sc->elcr_res);
+ for (i = 0; i < ELCR_IOLEN; i++)
+ bus_space_write_1(bst, bsh, i, sc->saved_elcr[i]);
+ }
+
+ return (bus_generic_resume(dev));
+}
diff --git a/sys/dev/pci/pci.c b/sys/dev/pci/pci.c
new file mode 100644
index 0000000..2c5e7a4
--- /dev/null
+++ b/sys/dev/pci/pci.c
@@ -0,0 +1,1414 @@
+/*
+ * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
+ * Copyright (c) 2000, Michael Smith <msmith@freebsd.org>
+ * Copyright (c) 2000, BSDi
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice unmodified, this list of conditions, and the following
+ * disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ *
+ */
+
+#include "opt_bus.h"
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/malloc.h>
+#include <sys/module.h>
+#include <sys/linker.h>
+#include <sys/fcntl.h>
+#include <sys/conf.h>
+#include <sys/kernel.h>
+#include <sys/queue.h>
+#include <sys/sysctl.h>
+#include <sys/types.h>
+
+#include <vm/vm.h>
+#include <vm/pmap.h>
+#include <vm/vm_extern.h>
+
+#include <sys/bus.h>
+#include <machine/bus.h>
+#include <sys/rman.h>
+#include <machine/resource.h>
+
+#include <sys/pciio.h>
+#include <dev/pci/pcireg.h>
+#include <dev/pci/pcivar.h>
+#include <dev/pci/pci_private.h>
+
+#include "pcib_if.h"
+#include "pci_if.h"
+
+static u_int32_t pci_mapbase(unsigned mapreg);
+static int pci_maptype(unsigned mapreg);
+static int pci_mapsize(unsigned testval);
+static int pci_maprange(unsigned mapreg);
+static void pci_fixancient(pcicfgregs *cfg);
+static void pci_hdrtypedata(device_t pcib, int b, int s, int f,
+ pcicfgregs *cfg);
+static void pci_read_extcap(device_t pcib, pcicfgregs *cfg);
+
+static int pci_porten(device_t pcib, int b, int s, int f);
+static int pci_memen(device_t pcib, int b, int s, int f);
+static int pci_add_map(device_t pcib, int b, int s, int f, int reg,
+ struct resource_list *rl);
+static void pci_add_resources(device_t pcib, device_t dev);
+static int pci_probe(device_t dev);
+static int pci_attach(device_t dev);
+static void pci_load_vendor_data(void);
+static int pci_describe_parse_line(char **ptr, int *vendor,
+ int *device, char **desc);
+static char *pci_describe_device(device_t dev);
+static int pci_modevent(module_t mod, int what, void *arg);
+
+static device_method_t pci_methods[] = {
+ /* Device interface */
+ DEVMETHOD(device_probe, pci_probe),
+ DEVMETHOD(device_attach, pci_attach),
+ DEVMETHOD(device_shutdown, bus_generic_shutdown),
+ DEVMETHOD(device_suspend, bus_generic_suspend),
+ DEVMETHOD(device_resume, bus_generic_resume),
+
+ /* Bus interface */
+ DEVMETHOD(bus_print_child, pci_print_child),
+ DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch),
+ DEVMETHOD(bus_read_ivar, pci_read_ivar),
+ DEVMETHOD(bus_write_ivar, pci_write_ivar),
+ DEVMETHOD(bus_driver_added, bus_generic_driver_added),
+ DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
+ DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
+
+ DEVMETHOD(bus_get_resource_list,pci_get_resource_list),
+ DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource),
+ DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource),
+ DEVMETHOD(bus_delete_resource, pci_delete_resource),
+ DEVMETHOD(bus_alloc_resource, pci_alloc_resource),
+ DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource),
+ DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
+ DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
+
+ /* PCI interface */
+ DEVMETHOD(pci_read_config, pci_read_config_method),
+ DEVMETHOD(pci_write_config, pci_write_config_method),
+ DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method),
+ DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method),
+ DEVMETHOD(pci_enable_io, pci_enable_io_method),
+ DEVMETHOD(pci_disable_io, pci_disable_io_method),
+ DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method),
+ DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method),
+
+ { 0, 0 }
+};
+
+static driver_t pci_driver = {
+ "pci",
+ pci_methods,
+ 0, /* no softc */
+};
+
+devclass_t pci_devclass;
+DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0);
+MODULE_VERSION(pci, 1);
+
+static char *pci_vendordata;
+static size_t pci_vendordata_size;
+
+
+struct pci_quirk {
+ u_int32_t devid; /* Vendor/device of the card */
+ int type;
+#define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */
+ int arg1;
+ int arg2;
+};
+
+struct pci_quirk pci_quirks[] = {
+ /* The Intel 82371AB and 82443MX has a map register at offset 0x90. */
+ { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 },
+ { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 },
+ /* As does the Serverworks OSB4 (the SMBus mapping register) */
+ { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 },
+
+ { 0 }
+};
+
+/* map register information */
+#define PCI_MAPMEM 0x01 /* memory map */
+#define PCI_MAPMEMP 0x02 /* prefetchable memory map */
+#define PCI_MAPPORT 0x04 /* port map */
+
+struct devlist pci_devq;
+u_int32_t pci_generation;
+u_int32_t pci_numdevs = 0;
+
+/* sysctl vars */
+SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD, 0, "PCI bus tuning parameters");
+
+static int pci_enable_io_modes = 1;
+TUNABLE_INT("hw.pci.enable_io_modes", (int *)&pci_enable_io_modes);
+SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RW,
+ &pci_enable_io_modes, 1,
+ "Enable I/O and memory bits in the config register. Some BIOSes do not\n\
+enable these bits correctly. We'd like to do this all the time, but there\n\
+are some peripherals that this causes problems with.");
+
+/* Find a device_t by bus/slot/function */
+
+device_t
+pci_find_bsf(u_int8_t bus, u_int8_t slot, u_int8_t func)
+{
+ struct pci_devinfo *dinfo;
+
+ STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
+ if ((dinfo->cfg.bus == bus) &&
+ (dinfo->cfg.slot == slot) &&
+ (dinfo->cfg.func == func)) {
+ return (dinfo->cfg.dev);
+ }
+ }
+
+ return (NULL);
+}
+
+/* Find a device_t by vendor/device ID */
+
+device_t
+pci_find_device(u_int16_t vendor, u_int16_t device)
+{
+ struct pci_devinfo *dinfo;
+
+ STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
+ if ((dinfo->cfg.vendor == vendor) &&
+ (dinfo->cfg.device == device)) {
+ return (dinfo->cfg.dev);
+ }
+ }
+
+ return (NULL);
+}
+
+/* return base address of memory or port map */
+
+static u_int32_t
+pci_mapbase(unsigned mapreg)
+{
+ int mask = 0x03;
+ if ((mapreg & 0x01) == 0)
+ mask = 0x0f;
+ return (mapreg & ~mask);
+}
+
+/* return map type of memory or port map */
+
+static int
+pci_maptype(unsigned mapreg)
+{
+ static u_int8_t maptype[0x10] = {
+ PCI_MAPMEM, PCI_MAPPORT,
+ PCI_MAPMEM, 0,
+ PCI_MAPMEM, PCI_MAPPORT,
+ 0, 0,
+ PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT,
+ PCI_MAPMEM|PCI_MAPMEMP, 0,
+ PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT,
+ 0, 0,
+ };
+
+ return maptype[mapreg & 0x0f];
+}
+
+/* return log2 of map size decoded for memory or port map */
+
+static int
+pci_mapsize(unsigned testval)
+{
+ int ln2size;
+
+ testval = pci_mapbase(testval);
+ ln2size = 0;
+ if (testval != 0) {
+ while ((testval & 1) == 0)
+ {
+ ln2size++;
+ testval >>= 1;
+ }
+ }
+ return (ln2size);
+}
+
+/* return log2 of address range supported by map register */
+
+static int
+pci_maprange(unsigned mapreg)
+{
+ int ln2range = 0;
+ switch (mapreg & 0x07) {
+ case 0x00:
+ case 0x01:
+ case 0x05:
+ ln2range = 32;
+ break;
+ case 0x02:
+ ln2range = 20;
+ break;
+ case 0x04:
+ ln2range = 64;
+ break;
+ }
+ return (ln2range);
+}
+
+/* adjust some values from PCI 1.0 devices to match 2.0 standards ... */
+
+static void
+pci_fixancient(pcicfgregs *cfg)
+{
+ if (cfg->hdrtype != 0)
+ return;
+
+ /* PCI to PCI bridges use header type 1 */
+ if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI)
+ cfg->hdrtype = 1;
+}
+
+/* extract header type specific config data */
+
+static void
+pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg)
+{
+#define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
+ switch (cfg->hdrtype) {
+ case 0:
+ cfg->subvendor = REG(PCIR_SUBVEND_0, 2);
+ cfg->subdevice = REG(PCIR_SUBDEV_0, 2);
+ cfg->nummaps = PCI_MAXMAPS_0;
+ break;
+ case 1:
+ cfg->subvendor = REG(PCIR_SUBVEND_1, 2);
+ cfg->subdevice = REG(PCIR_SUBDEV_1, 2);
+ cfg->nummaps = PCI_MAXMAPS_1;
+ break;
+ case 2:
+ cfg->subvendor = REG(PCIR_SUBVEND_2, 2);
+ cfg->subdevice = REG(PCIR_SUBDEV_2, 2);
+ cfg->nummaps = PCI_MAXMAPS_2;
+ break;
+ }
+#undef REG
+}
+
+/* read configuration header into pcicfgregs structure */
+
+struct pci_devinfo *
+pci_read_device(device_t pcib, int b, int s, int f, size_t size)
+{
+#define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
+ pcicfgregs *cfg = NULL;
+ struct pci_devinfo *devlist_entry;
+ struct devlist *devlist_head;
+
+ devlist_head = &pci_devq;
+
+ devlist_entry = NULL;
+
+ if (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_DEVVENDOR, 4) != -1) {
+ devlist_entry = malloc(size, M_DEVBUF, M_WAITOK | M_ZERO);
+ if (devlist_entry == NULL)
+ return (NULL);
+
+ cfg = &devlist_entry->cfg;
+
+ cfg->bus = b;
+ cfg->slot = s;
+ cfg->func = f;
+ cfg->vendor = REG(PCIR_VENDOR, 2);
+ cfg->device = REG(PCIR_DEVICE, 2);
+ cfg->cmdreg = REG(PCIR_COMMAND, 2);
+ cfg->statreg = REG(PCIR_STATUS, 2);
+ cfg->baseclass = REG(PCIR_CLASS, 1);
+ cfg->subclass = REG(PCIR_SUBCLASS, 1);
+ cfg->progif = REG(PCIR_PROGIF, 1);
+ cfg->revid = REG(PCIR_REVID, 1);
+ cfg->hdrtype = REG(PCIR_HEADERTYPE, 1);
+ cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1);
+ cfg->lattimer = REG(PCIR_LATTIMER, 1);
+ cfg->intpin = REG(PCIR_INTPIN, 1);
+ cfg->intline = REG(PCIR_INTLINE, 1);
+
+ cfg->mingnt = REG(PCIR_MINGNT, 1);
+ cfg->maxlat = REG(PCIR_MAXLAT, 1);
+
+ cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0;
+ cfg->hdrtype &= ~PCIM_MFDEV;
+
+ pci_fixancient(cfg);
+ pci_hdrtypedata(pcib, b, s, f, cfg);
+
+ if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT)
+ pci_read_extcap(pcib, cfg);
+
+ STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links);
+
+ devlist_entry->conf.pc_sel.pc_bus = cfg->bus;
+ devlist_entry->conf.pc_sel.pc_dev = cfg->slot;
+ devlist_entry->conf.pc_sel.pc_func = cfg->func;
+ devlist_entry->conf.pc_hdr = cfg->hdrtype;
+
+ devlist_entry->conf.pc_subvendor = cfg->subvendor;
+ devlist_entry->conf.pc_subdevice = cfg->subdevice;
+ devlist_entry->conf.pc_vendor = cfg->vendor;
+ devlist_entry->conf.pc_device = cfg->device;
+
+ devlist_entry->conf.pc_class = cfg->baseclass;
+ devlist_entry->conf.pc_subclass = cfg->subclass;
+ devlist_entry->conf.pc_progif = cfg->progif;
+ devlist_entry->conf.pc_revid = cfg->revid;
+
+ pci_numdevs++;
+ pci_generation++;
+ }
+ return (devlist_entry);
+#undef REG
+}
+
+static void
+pci_read_extcap(device_t pcib, pcicfgregs *cfg)
+{
+#define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
+ int ptr, nextptr, ptrptr;
+
+ switch (cfg->hdrtype) {
+ case 0:
+ ptrptr = 0x34;
+ break;
+ case 2:
+ ptrptr = 0x14;
+ break;
+ default:
+ return; /* no extended capabilities support */
+ }
+ nextptr = REG(ptrptr, 1); /* sanity check? */
+
+ /*
+ * Read capability entries.
+ */
+ while (nextptr != 0) {
+ /* Sanity check */
+ if (nextptr > 255) {
+ printf("illegal PCI extended capability offset %d\n",
+ nextptr);
+ return;
+ }
+ /* Find the next entry */
+ ptr = nextptr;
+ nextptr = REG(ptr + 1, 1);
+
+ /* Process this entry */
+ switch (REG(ptr, 1)) {
+ case 0x01: /* PCI power management */
+ if (cfg->pp_cap == 0) {
+ cfg->pp_cap = REG(ptr + PCIR_POWER_CAP, 2);
+ cfg->pp_status = ptr + PCIR_POWER_STATUS;
+ cfg->pp_pmcsr = ptr + PCIR_POWER_PMCSR;
+ if ((nextptr - ptr) > PCIR_POWER_DATA)
+ cfg->pp_data = ptr + PCIR_POWER_DATA;
+ }
+ break;
+ default:
+ break;
+ }
+ }
+#undef REG
+}
+
+/* free pcicfgregs structure and all depending data structures */
+
+int
+pci_freecfg(struct pci_devinfo *dinfo)
+{
+ struct devlist *devlist_head;
+
+ devlist_head = &pci_devq;
+
+ /* XXX this hasn't been tested */
+ STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links);
+ free(dinfo, M_DEVBUF);
+
+ /* increment the generation count */
+ pci_generation++;
+
+ /* we're losing one device */
+ pci_numdevs--;
+ return (0);
+}
+
+/*
+ * PCI power manangement
+ */
+int
+pci_set_powerstate_method(device_t dev, device_t child, int state)
+{
+ struct pci_devinfo *dinfo = device_get_ivars(child);
+ pcicfgregs *cfg = &dinfo->cfg;
+ u_int16_t status;
+ int result;
+
+ if (cfg->pp_cap != 0) {
+ status = PCI_READ_CONFIG(dev, child, cfg->pp_status, 2) & ~PCIM_PSTAT_DMASK;
+ result = 0;
+ switch (state) {
+ case PCI_POWERSTATE_D0:
+ status |= PCIM_PSTAT_D0;
+ break;
+ case PCI_POWERSTATE_D1:
+ if (cfg->pp_cap & PCIM_PCAP_D1SUPP) {
+ status |= PCIM_PSTAT_D1;
+ } else {
+ result = EOPNOTSUPP;
+ }
+ break;
+ case PCI_POWERSTATE_D2:
+ if (cfg->pp_cap & PCIM_PCAP_D2SUPP) {
+ status |= PCIM_PSTAT_D2;
+ } else {
+ result = EOPNOTSUPP;
+ }
+ break;
+ case PCI_POWERSTATE_D3:
+ status |= PCIM_PSTAT_D3;
+ break;
+ default:
+ result = EINVAL;
+ }
+ if (result == 0)
+ PCI_WRITE_CONFIG(dev, child, cfg->pp_status, status, 2);
+ } else {
+ result = ENXIO;
+ }
+ return(result);
+}
+
+int
+pci_get_powerstate_method(device_t dev, device_t child)
+{
+ struct pci_devinfo *dinfo = device_get_ivars(child);
+ pcicfgregs *cfg = &dinfo->cfg;
+ u_int16_t status;
+ int result;
+
+ if (cfg->pp_cap != 0) {
+ status = PCI_READ_CONFIG(dev, child, cfg->pp_status, 2);
+ switch (status & PCIM_PSTAT_DMASK) {
+ case PCIM_PSTAT_D0:
+ result = PCI_POWERSTATE_D0;
+ break;
+ case PCIM_PSTAT_D1:
+ result = PCI_POWERSTATE_D1;
+ break;
+ case PCIM_PSTAT_D2:
+ result = PCI_POWERSTATE_D2;
+ break;
+ case PCIM_PSTAT_D3:
+ result = PCI_POWERSTATE_D3;
+ break;
+ default:
+ result = PCI_POWERSTATE_UNKNOWN;
+ break;
+ }
+ } else {
+ /* No support, device is always at D0 */
+ result = PCI_POWERSTATE_D0;
+ }
+ return(result);
+}
+
+/*
+ * Some convenience functions for PCI device drivers.
+ */
+
+static __inline void
+pci_set_command_bit(device_t dev, device_t child, u_int16_t bit)
+{
+ u_int16_t command;
+
+ command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
+ command |= bit;
+ PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
+}
+
+static __inline void
+pci_clear_command_bit(device_t dev, device_t child, u_int16_t bit)
+{
+ u_int16_t command;
+
+ command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
+ command &= ~bit;
+ PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
+}
+
+void
+pci_enable_busmaster_method(device_t dev, device_t child)
+{
+ pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
+}
+
+void
+pci_disable_busmaster_method(device_t dev, device_t child)
+{
+ pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
+}
+
+void
+pci_enable_io_method(device_t dev, device_t child, int space)
+{
+ switch(space) {
+ case SYS_RES_IOPORT:
+ pci_set_command_bit(dev, child, PCIM_CMD_PORTEN);
+ break;
+ case SYS_RES_MEMORY:
+ pci_set_command_bit(dev, child, PCIM_CMD_MEMEN);
+ break;
+ }
+}
+
+void
+pci_disable_io_method(device_t dev, device_t child, int space)
+{
+ switch(space) {
+ case SYS_RES_IOPORT:
+ pci_clear_command_bit(dev, child, PCIM_CMD_PORTEN);
+ break;
+ case SYS_RES_MEMORY:
+ pci_clear_command_bit(dev, child, PCIM_CMD_MEMEN);
+ break;
+ }
+}
+
+/*
+ * New style pci driver. Parent device is either a pci-host-bridge or a
+ * pci-pci-bridge. Both kinds are represented by instances of pcib.
+ */
+
+void
+pci_print_verbose(struct pci_devinfo *dinfo)
+{
+ if (bootverbose) {
+ pcicfgregs *cfg = &dinfo->cfg;
+
+ printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n",
+ cfg->vendor, cfg->device, cfg->revid);
+ printf("\tbus=%d, slot=%d, func=%d\n",
+ cfg->bus, cfg->slot, cfg->func);
+ printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n",
+ cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype,
+ cfg->mfdev);
+ printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n",
+ cfg->cmdreg, cfg->statreg, cfg->cachelnsz);
+ printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n",
+ cfg->lattimer, cfg->lattimer * 30, cfg->mingnt,
+ cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250);
+ if (cfg->intpin > 0)
+ printf("\tintpin=%c, irq=%d\n",
+ cfg->intpin +'a' -1, cfg->intline);
+ if (cfg->pp_cap) {
+ u_int16_t status;
+
+ status = pci_read_config(cfg->dev, cfg->pp_status, 2);
+ printf("\tpowerspec %d supports D0%s%s D3 current D%d\n",
+ cfg->pp_cap & PCIM_PCAP_SPEC,
+ cfg->pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "",
+ cfg->pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "",
+ status & PCIM_PSTAT_DMASK);
+ }
+ }
+}
+
+static int
+pci_porten(device_t pcib, int b, int s, int f)
+{
+ return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
+ & PCIM_CMD_PORTEN) != 0;
+}
+
+static int
+pci_memen(device_t pcib, int b, int s, int f)
+{
+ return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
+ & PCIM_CMD_MEMEN) != 0;
+}
+
+/*
+ * Add a resource based on a pci map register. Return 1 if the map
+ * register is a 32bit map register or 2 if it is a 64bit register.
+ */
+static int
+pci_add_map(device_t pcib, int b, int s, int f, int reg,
+ struct resource_list *rl)
+{
+ u_int32_t map;
+ u_int64_t base;
+ u_int8_t ln2size;
+ u_int8_t ln2range;
+ u_int32_t testval;
+ u_int16_t cmd;
+ int type;
+
+ map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
+
+ if (map == 0 || map == 0xffffffff)
+ return (1); /* skip invalid entry */
+
+ PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4);
+ testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
+ PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4);
+
+ base = pci_mapbase(map);
+ if (pci_maptype(map) & PCI_MAPMEM)
+ type = SYS_RES_MEMORY;
+ else
+ type = SYS_RES_IOPORT;
+ ln2size = pci_mapsize(testval);
+ ln2range = pci_maprange(testval);
+ if (ln2range == 64) {
+ /* Read the other half of a 64bit map register */
+ base |= (u_int64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg + 4, 4) << 32;
+ }
+
+ if (bootverbose) {
+ printf("\tmap[%02x]: type %x, range %2d, base %08x, size %2d",
+ reg, pci_maptype(map), ln2range,
+ (unsigned int) base, ln2size);
+ if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f))
+ printf(", port disabled\n");
+ else if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f))
+ printf(", memory disabled\n");
+ else
+ printf(", enabled\n");
+ }
+
+ /*
+ * This code theoretically does the right thing, but has
+ * undesirable side effects in some cases where
+ * peripherals respond oddly to having these bits
+ * enabled. Leave them alone by default.
+ */
+ if (pci_enable_io_modes) {
+ /* Turn on resources that have been left off by a lazy BIOS */
+ if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) {
+ cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
+ cmd |= PCIM_CMD_PORTEN;
+ PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
+ }
+ if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) {
+ cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
+ cmd |= PCIM_CMD_MEMEN;
+ PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
+ }
+ } else {
+ if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f))
+ return (1);
+ if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f))
+ return (1);
+ }
+ resource_list_add(rl, type, reg, base, base + (1 << ln2size) - 1,
+ (1 << ln2size));
+
+ return ((ln2range == 64) ? 2 : 1);
+}
+
+static void
+pci_add_resources(device_t pcib, device_t dev)
+{
+ struct pci_devinfo *dinfo = device_get_ivars(dev);
+ pcicfgregs *cfg = &dinfo->cfg;
+ struct resource_list *rl = &dinfo->resources;
+ struct pci_quirk *q;
+ int b, i, f, s;
+
+ b = cfg->bus;
+ s = cfg->slot;
+ f = cfg->func;
+ for (i = 0; i < cfg->nummaps;) {
+ i += pci_add_map(pcib, b, s, f, PCIR_MAPS + i*4, rl);
+ }
+
+ for (q = &pci_quirks[0]; q->devid; q++) {
+ if (q->devid == ((cfg->device << 16) | cfg->vendor)
+ && q->type == PCI_QUIRK_MAP_REG)
+ pci_add_map(pcib, b, s, f, q->arg1, rl);
+ }
+
+ if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) {
+#ifdef __ia64__
+ /*
+ * Re-route interrupts on ia64 so that we can get the
+ * I/O SAPIC interrupt numbers (the BIOS leaves legacy
+ * PIC interrupt numbers in the intline registers).
+ */
+ cfg->intline = PCIB_ROUTE_INTERRUPT(pcib, dev, cfg->intpin);
+#endif
+ resource_list_add(rl, SYS_RES_IRQ, 0, cfg->intline,
+ cfg->intline, 1);
+ }
+}
+
+void
+pci_add_children(device_t dev, int busno, size_t dinfo_size)
+{
+ device_t pcib = device_get_parent(dev);
+ struct pci_devinfo *dinfo;
+ int maxslots;
+ int s, f, pcifunchigh;
+
+ KASSERT(dinfo_size >= sizeof(struct pci_devinfo),
+ ("dinfo_size too small"));
+ maxslots = PCIB_MAXSLOTS(pcib);
+ for (s = 0; s <= maxslots; s++) {
+ pcifunchigh = 0;
+ for (f = 0; f <= pcifunchigh; f++) {
+ dinfo = pci_read_device(pcib, busno, s, f, dinfo_size);
+ if (dinfo != NULL) {
+ if (dinfo->cfg.mfdev)
+ pcifunchigh = PCI_FUNCMAX;
+ pci_add_child(dev, dinfo);
+ }
+ }
+ }
+}
+
+void
+pci_add_child(device_t bus, struct pci_devinfo *dinfo)
+{
+ device_t pcib;
+
+ pcib = device_get_parent(bus);
+ dinfo->cfg.dev = device_add_child(bus, NULL, -1);
+ device_set_ivars(dinfo->cfg.dev, dinfo);
+ pci_add_resources(pcib, dinfo->cfg.dev);
+ pci_print_verbose(dinfo);
+}
+
+static int
+pci_probe(device_t dev)
+{
+
+ device_set_desc(dev, "PCI bus");
+
+ /* Allow other subclasses to override this driver. */
+ return (-1000);
+}
+
+static int
+pci_attach(device_t dev)
+{
+ int busno;
+
+ /*
+ * Since there can be multiple independantly numbered PCI
+ * busses on some large alpha systems, we can't use the unit
+ * number to decide what bus we are probing. We ask the parent
+ * pcib what our bus number is.
+ */
+ busno = pcib_get_bus(dev);
+ if (bootverbose)
+ device_printf(dev, "physical bus=%d\n", busno);
+
+ pci_add_children(dev, busno, sizeof(struct pci_devinfo));
+
+ return (bus_generic_attach(dev));
+}
+
+static void
+pci_load_vendor_data(void)
+{
+ caddr_t vendordata, info;
+
+ if ((vendordata = preload_search_by_type("pci_vendor_data")) != NULL) {
+ info = preload_search_info(vendordata, MODINFO_ADDR);
+ pci_vendordata = *(char **)info;
+ info = preload_search_info(vendordata, MODINFO_SIZE);
+ pci_vendordata_size = *(size_t *)info;
+ /* terminate the database */
+ pci_vendordata[pci_vendordata_size] = '\n';
+ }
+}
+
+int
+pci_print_child(device_t dev, device_t child)
+{
+ struct pci_devinfo *dinfo;
+ struct resource_list *rl;
+ pcicfgregs *cfg;
+ int retval = 0;
+
+ dinfo = device_get_ivars(child);
+ cfg = &dinfo->cfg;
+ rl = &dinfo->resources;
+
+ retval += bus_print_child_header(dev, child);
+
+ retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#lx");
+ retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx");
+ retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld");
+ if (device_get_flags(dev))
+ retval += printf(" flags %#x", device_get_flags(dev));
+
+ retval += printf(" at device %d.%d", pci_get_slot(child),
+ pci_get_function(child));
+
+ retval += bus_print_child_footer(dev, child);
+
+ return (retval);
+}
+
+static struct
+{
+ int class;
+ int subclass;
+ char *desc;
+} pci_nomatch_tab[] = {
+ {PCIC_OLD, -1, "old"},
+ {PCIC_OLD, PCIS_OLD_NONVGA, "non-VGA display device"},
+ {PCIC_OLD, PCIS_OLD_VGA, "VGA-compatible display device"},
+ {PCIC_STORAGE, -1, "mass storage"},
+ {PCIC_STORAGE, PCIS_STORAGE_SCSI, "SCSI"},
+ {PCIC_STORAGE, PCIS_STORAGE_IDE, "ATA"},
+ {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, "floppy disk"},
+ {PCIC_STORAGE, PCIS_STORAGE_IPI, "IPI"},
+ {PCIC_STORAGE, PCIS_STORAGE_RAID, "RAID"},
+ {PCIC_NETWORK, -1, "network"},
+ {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, "ethernet"},
+ {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, "token ring"},
+ {PCIC_NETWORK, PCIS_NETWORK_FDDI, "fddi"},
+ {PCIC_NETWORK, PCIS_NETWORK_ATM, "ATM"},
+ {PCIC_DISPLAY, -1, "display"},
+ {PCIC_DISPLAY, PCIS_DISPLAY_VGA, "VGA"},
+ {PCIC_DISPLAY, PCIS_DISPLAY_XGA, "XGA"},
+ {PCIC_MULTIMEDIA, -1, "multimedia"},
+ {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, "video"},
+ {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, "audio"},
+ {PCIC_MEMORY, -1, "memory"},
+ {PCIC_MEMORY, PCIS_MEMORY_RAM, "RAM"},
+ {PCIC_MEMORY, PCIS_MEMORY_FLASH, "flash"},
+ {PCIC_BRIDGE, -1, "bridge"},
+ {PCIC_BRIDGE, PCIS_BRIDGE_HOST, "HOST-PCI"},
+ {PCIC_BRIDGE, PCIS_BRIDGE_ISA, "PCI-ISA"},
+ {PCIC_BRIDGE, PCIS_BRIDGE_EISA, "PCI-EISA"},
+ {PCIC_BRIDGE, PCIS_BRIDGE_MCA, "PCI-MCA"},
+ {PCIC_BRIDGE, PCIS_BRIDGE_PCI, "PCI-PCI"},
+ {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, "PCI-PCMCIA"},
+ {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, "PCI-NuBus"},
+ {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, "PCI-CardBus"},
+ {PCIC_BRIDGE, PCIS_BRIDGE_OTHER, "PCI-unknown"},
+ {PCIC_SIMPLECOMM, -1, "simple comms"},
+ {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, "UART"}, /* could detect 16550 */
+ {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, "parallel port"},
+ {PCIC_BASEPERIPH, -1, "base peripheral"},
+ {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, "interrupt controller"},
+ {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, "DMA controller"},
+ {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, "timer"},
+ {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, "realtime clock"},
+ {PCIC_INPUTDEV, -1, "input device"},
+ {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, "keyboard"},
+ {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,"digitizer"},
+ {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, "mouse"},
+ {PCIC_DOCKING, -1, "docking station"},
+ {PCIC_PROCESSOR, -1, "processor"},
+ {PCIC_SERIALBUS, -1, "serial bus"},
+ {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, "FireWire"},
+ {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, "AccessBus"},
+ {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, "SSA"},
+ {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, "USB"},
+ {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, "Fibre Channel"},
+ {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, "SMBus"},
+ {0, 0, NULL}
+};
+
+void
+pci_probe_nomatch(device_t dev, device_t child)
+{
+ int i;
+ char *cp, *scp, *device;
+
+ /*
+ * Look for a listing for this device in a loaded device database.
+ */
+ if ((device = pci_describe_device(child)) != NULL) {
+ device_printf(dev, "<%s>", device);
+ free(device, M_DEVBUF);
+ } else {
+ /*
+ * Scan the class/subclass descriptions for a general
+ * description.
+ */
+ cp = "unknown";
+ scp = NULL;
+ for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) {
+ if (pci_nomatch_tab[i].class == pci_get_class(child)) {
+ if (pci_nomatch_tab[i].subclass == -1) {
+ cp = pci_nomatch_tab[i].desc;
+ } else if (pci_nomatch_tab[i].subclass ==
+ pci_get_subclass(child)) {
+ scp = pci_nomatch_tab[i].desc;
+ }
+ }
+ }
+ device_printf(dev, "<%s%s%s>",
+ cp ? cp : "",
+ ((cp != NULL) && (scp != NULL)) ? ", " : "",
+ scp ? scp : "");
+ }
+ printf(" at device %d.%d (no driver attached)\n",
+ pci_get_slot(child), pci_get_function(child));
+ return;
+}
+
+/*
+ * Parse the PCI device database, if loaded, and return a pointer to a
+ * description of the device.
+ *
+ * The database is flat text formatted as follows:
+ *
+ * Any line not in a valid format is ignored.
+ * Lines are terminated with newline '\n' characters.
+ *
+ * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then
+ * the vendor name.
+ *
+ * A DEVICE line is entered immediately below the corresponding VENDOR ID.
+ * - devices cannot be listed without a corresponding VENDOR line.
+ * A DEVICE line consists of a TAB, the 4 digit (hex) device code,
+ * another TAB, then the device name.
+ */
+
+/*
+ * Assuming (ptr) points to the beginning of a line in the database,
+ * return the vendor or device and description of the next entry.
+ * The value of (vendor) or (device) inappropriate for the entry type
+ * is set to -1. Returns nonzero at the end of the database.
+ *
+ * Note that this is slightly unrobust in the face of corrupt data;
+ * we attempt to safeguard against this by spamming the end of the
+ * database with a newline when we initialise.
+ */
+static int
+pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc)
+{
+ char *cp = *ptr;
+ int left;
+
+ *device = -1;
+ *vendor = -1;
+ **desc = '\0';
+ for (;;) {
+ left = pci_vendordata_size - (cp - pci_vendordata);
+ if (left <= 0) {
+ *ptr = cp;
+ return(1);
+ }
+
+ /* vendor entry? */
+ if (*cp != '\t' &&
+ sscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2)
+ break;
+ /* device entry? */
+ if (*cp == '\t' &&
+ sscanf(cp, "%x\t%80[^\n]", device, *desc) == 2)
+ break;
+
+ /* skip to next line */
+ while (*cp != '\n' && left > 0) {
+ cp++;
+ left--;
+ }
+ if (*cp == '\n') {
+ cp++;
+ left--;
+ }
+ }
+ /* skip to next line */
+ while (*cp != '\n' && left > 0) {
+ cp++;
+ left--;
+ }
+ if (*cp == '\n' && left > 0)
+ cp++;
+ *ptr = cp;
+ return(0);
+}
+
+static char *
+pci_describe_device(device_t dev)
+{
+ int vendor, device;
+ char *desc, *vp, *dp, *line;
+
+ desc = vp = dp = NULL;
+
+ /*
+ * If we have no vendor data, we can't do anything.
+ */
+ if (pci_vendordata == NULL)
+ goto out;
+
+ /*
+ * Scan the vendor data looking for this device
+ */
+ line = pci_vendordata;
+ if ((vp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL)
+ goto out;
+ for (;;) {
+ if (pci_describe_parse_line(&line, &vendor, &device, &vp))
+ goto out;
+ if (vendor == pci_get_vendor(dev))
+ break;
+ }
+ if ((dp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL)
+ goto out;
+ for (;;) {
+ if (pci_describe_parse_line(&line, &vendor, &device, &dp)) {
+ *dp = 0;
+ break;
+ }
+ if (vendor != -1) {
+ *dp = 0;
+ break;
+ }
+ if (device == pci_get_device(dev))
+ break;
+ }
+ if (dp[0] == '\0')
+ snprintf(dp, 80, "0x%x", pci_get_device(dev));
+ if ((desc = malloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) !=
+ NULL)
+ sprintf(desc, "%s, %s", vp, dp);
+ out:
+ if (vp != NULL)
+ free(vp, M_DEVBUF);
+ if (dp != NULL)
+ free(dp, M_DEVBUF);
+ return(desc);
+}
+
+int
+pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
+{
+ struct pci_devinfo *dinfo;
+ pcicfgregs *cfg;
+
+ dinfo = device_get_ivars(child);
+ cfg = &dinfo->cfg;
+
+ switch (which) {
+ case PCI_IVAR_ETHADDR:
+ /*
+ * The generic accessor doesn't deal with failure, so
+ * we set the return value, then return an error.
+ */
+ *((u_int8_t **) result) = NULL;
+ return (EINVAL);
+ case PCI_IVAR_SUBVENDOR:
+ *result = cfg->subvendor;
+ break;
+ case PCI_IVAR_SUBDEVICE:
+ *result = cfg->subdevice;
+ break;
+ case PCI_IVAR_VENDOR:
+ *result = cfg->vendor;
+ break;
+ case PCI_IVAR_DEVICE:
+ *result = cfg->device;
+ break;
+ case PCI_IVAR_DEVID:
+ *result = (cfg->device << 16) | cfg->vendor;
+ break;
+ case PCI_IVAR_CLASS:
+ *result = cfg->baseclass;
+ break;
+ case PCI_IVAR_SUBCLASS:
+ *result = cfg->subclass;
+ break;
+ case PCI_IVAR_PROGIF:
+ *result = cfg->progif;
+ break;
+ case PCI_IVAR_REVID:
+ *result = cfg->revid;
+ break;
+ case PCI_IVAR_INTPIN:
+ *result = cfg->intpin;
+ break;
+ case PCI_IVAR_IRQ:
+ *result = cfg->intline;
+ break;
+ case PCI_IVAR_BUS:
+ *result = cfg->bus;
+ break;
+ case PCI_IVAR_SLOT:
+ *result = cfg->slot;
+ break;
+ case PCI_IVAR_FUNCTION:
+ *result = cfg->func;
+ break;
+ default:
+ return (ENOENT);
+ }
+ return (0);
+}
+
+int
+pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
+{
+ struct pci_devinfo *dinfo;
+ pcicfgregs *cfg;
+
+ dinfo = device_get_ivars(child);
+ cfg = &dinfo->cfg;
+
+ switch (which) {
+ case PCI_IVAR_ETHADDR:
+ case PCI_IVAR_SUBVENDOR:
+ case PCI_IVAR_SUBDEVICE:
+ case PCI_IVAR_VENDOR:
+ case PCI_IVAR_DEVICE:
+ case PCI_IVAR_DEVID:
+ case PCI_IVAR_CLASS:
+ case PCI_IVAR_SUBCLASS:
+ case PCI_IVAR_PROGIF:
+ case PCI_IVAR_REVID:
+ case PCI_IVAR_INTPIN:
+ case PCI_IVAR_IRQ:
+ case PCI_IVAR_BUS:
+ case PCI_IVAR_SLOT:
+ case PCI_IVAR_FUNCTION:
+ return (EINVAL); /* disallow for now */
+
+ default:
+ return (ENOENT);
+ }
+ return (0);
+}
+
+
+#include "opt_ddb.h"
+#ifdef DDB
+#include <ddb/ddb.h>
+#include <sys/cons.h>
+
+/*
+ * List resources based on pci map registers, used for within ddb
+ */
+
+DB_SHOW_COMMAND(pciregs, db_pci_dump)
+{
+ struct pci_devinfo *dinfo;
+ struct devlist *devlist_head;
+ struct pci_conf *p;
+ const char *name;
+ int i, error, none_count, nl;
+
+ none_count = 0;
+ nl = 0;
+ /* get the head of the device queue */
+ devlist_head = &pci_devq;
+
+ /*
+ * Go through the list of devices and print out devices
+ */
+ for (error = 0, i = 0,
+ dinfo = STAILQ_FIRST(devlist_head);
+ (dinfo != NULL) && (error == 0) && (i < pci_numdevs);
+ dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
+
+ /* Populate pd_name and pd_unit */
+ name = NULL;
+ if (dinfo->cfg.dev)
+ name = device_get_name(dinfo->cfg.dev);
+
+ p = &dinfo->conf;
+ /*
+ * XXX just take 20 for now...
+ */
+ if (nl++ == 20) {
+ int c;
+
+ db_printf("--More--");
+ c = cngetc();
+ db_printf("\r");
+ /*
+ * A whole screenfull or just one line?
+ */
+ switch (c) {
+ case '\n': /* just one line */
+ nl = 20;
+ break;
+ case ' ':
+ nl = 0; /* another screenfull */
+ break;
+ default: /* exit */
+ db_printf("\n");
+ return;
+ }
+ }
+
+ db_printf("%s%d@pci%d:%d:%d:\tclass=0x%06x card=0x%08x "
+ "chip=0x%08x rev=0x%02x hdr=0x%02x\n",
+ (name && *name) ? name : "none",
+ (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) :
+ none_count++,
+ p->pc_sel.pc_bus, p->pc_sel.pc_dev,
+ p->pc_sel.pc_func, (p->pc_class << 16) |
+ (p->pc_subclass << 8) | p->pc_progif,
+ (p->pc_subdevice << 16) | p->pc_subvendor,
+ (p->pc_device << 16) | p->pc_vendor,
+ p->pc_revid, p->pc_hdr);
+ }
+}
+#endif /* DDB */
+
+struct resource *
+pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
+ u_long start, u_long end, u_long count, u_int flags)
+{
+ struct pci_devinfo *dinfo = device_get_ivars(child);
+ struct resource_list *rl = &dinfo->resources;
+ pcicfgregs *cfg = &dinfo->cfg;
+
+ /*
+ * Perform lazy resource allocation
+ *
+ * XXX add support here for SYS_RES_IOPORT and SYS_RES_MEMORY
+ */
+ if (device_get_parent(child) == dev) {
+ /*
+ * If the child device doesn't have an interrupt routed
+ * and is deserving of an interrupt, try to assign it one.
+ */
+ if ((type == SYS_RES_IRQ) &&
+ !PCI_INTERRUPT_VALID(cfg->intline) &&
+ (cfg->intpin != 0)) {
+ cfg->intline = PCIB_ROUTE_INTERRUPT(
+ device_get_parent(dev), child, cfg->intpin);
+ if (PCI_INTERRUPT_VALID(cfg->intline)) {
+ pci_write_config(child, PCIR_INTLINE,
+ cfg->intline, 1);
+ resource_list_add(rl, SYS_RES_IRQ, 0,
+ cfg->intline, cfg->intline, 1);
+ }
+ }
+ }
+
+ return (resource_list_alloc(rl, dev, child, type, rid,
+ start, end, count, flags));
+}
+
+void
+pci_delete_resource(device_t dev, device_t child, int type, int rid)
+{
+ struct pci_devinfo *dinfo;
+ struct resource_list *rl;
+ struct resource_list_entry *rle;
+
+ if (device_get_parent(child) != dev)
+ return;
+
+ dinfo = device_get_ivars(child);
+ rl = &dinfo->resources;
+ rle = resource_list_find(rl, type, rid);
+ if (rle) {
+ if (rle->res) {
+ if (rle->res->r_dev != dev ||
+ rman_get_flags(rle->res) & RF_ACTIVE) {
+ device_printf(dev, "delete_resource: "
+ "Resource still owned by child, oops. "
+ "(type=%d, rid=%d, addr=%lx)\n",
+ rle->type, rle->rid,
+ rman_get_start(rle->res));
+ return;
+ }
+ bus_release_resource(dev, type, rid, rle->res);
+ }
+ resource_list_delete(rl, type, rid);
+ }
+ /*
+ * Why do we turn off the PCI configuration BAR when we delete a
+ * resource? -- imp
+ */
+ pci_write_config(child, rid, 0, 4);
+ BUS_DELETE_RESOURCE(device_get_parent(dev), child, type, rid);
+}
+
+struct resource_list *
+pci_get_resource_list (device_t dev, device_t child)
+{
+ struct pci_devinfo * dinfo = device_get_ivars(child);
+ struct resource_list * rl = &dinfo->resources;
+
+ if (!rl)
+ return (NULL);
+
+ return (rl);
+}
+
+u_int32_t
+pci_read_config_method(device_t dev, device_t child, int reg, int width)
+{
+ struct pci_devinfo *dinfo = device_get_ivars(child);
+ pcicfgregs *cfg = &dinfo->cfg;
+
+ return (PCIB_READ_CONFIG(device_get_parent(dev),
+ cfg->bus, cfg->slot, cfg->func, reg, width));
+}
+
+void
+pci_write_config_method(device_t dev, device_t child, int reg,
+ u_int32_t val, int width)
+{
+ struct pci_devinfo *dinfo = device_get_ivars(child);
+ pcicfgregs *cfg = &dinfo->cfg;
+
+ PCIB_WRITE_CONFIG(device_get_parent(dev),
+ cfg->bus, cfg->slot, cfg->func, reg, val, width);
+}
+
+static int
+pci_modevent(module_t mod, int what, void *arg)
+{
+ static dev_t pci_cdev;
+
+ switch (what) {
+ case MOD_LOAD:
+ STAILQ_INIT(&pci_devq);
+ pci_generation = 0;
+ pci_cdev = make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644,
+ "pci");
+ pci_load_vendor_data();
+ break;
+
+ case MOD_UNLOAD:
+ destroy_dev(pci_cdev);
+ break;
+ }
+
+ return (0);
+}
diff --git a/sys/dev/pci/pci_if.m b/sys/dev/pci/pci_if.m
new file mode 100644
index 0000000..8dab04e
--- /dev/null
+++ b/sys/dev/pci/pci_if.m
@@ -0,0 +1,79 @@
+#
+# Copyright (c) 1998 Doug Rabson
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+# 1. Redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution.
+#
+# THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+# ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+# OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+# HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+# OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+# SUCH DAMAGE.
+#
+# $FreeBSD$
+#
+
+#include <sys/bus.h>
+
+INTERFACE pci;
+
+METHOD u_int32_t read_config {
+ device_t dev;
+ device_t child;
+ int reg;
+ int width;
+};
+
+METHOD void write_config {
+ device_t dev;
+ device_t child;
+ int reg;
+ u_int32_t val;
+ int width;
+};
+
+METHOD int get_powerstate {
+ device_t dev;
+ device_t child;
+};
+
+METHOD int set_powerstate {
+ device_t dev;
+ device_t child;
+ int state;
+};
+
+METHOD void enable_busmaster {
+ device_t dev;
+ device_t child;
+};
+
+METHOD void disable_busmaster {
+ device_t dev;
+ device_t child;
+};
+
+METHOD void enable_io {
+ device_t dev;
+ device_t child;
+ int space;
+};
+
+METHOD void disable_io {
+ device_t dev;
+ device_t child;
+ int space;
+};
diff --git a/sys/dev/pci/pci_pci.c b/sys/dev/pci/pci_pci.c
new file mode 100644
index 0000000..a0e864a
--- /dev/null
+++ b/sys/dev/pci/pci_pci.c
@@ -0,0 +1,528 @@
+/*-
+ * Copyright (c) 1994,1995 Stefan Esser, Wolfgang StanglMeier
+ * Copyright (c) 2000 Michael Smith <msmith@freebsd.org>
+ * Copyright (c) 2000 BSDi
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+/*
+ * PCI:PCI bridge support.
+ */
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+#include <sys/bus.h>
+#include <sys/sysctl.h>
+
+#include <machine/resource.h>
+
+#include <pci/pcivar.h>
+#include <pci/pcireg.h>
+#include <pci/pcib_private.h>
+
+#include "pcib_if.h"
+
+static int pcib_probe(device_t dev);
+static int pcib_route_interrupt(device_t pcib, device_t dev, int pin);
+
+static device_method_t pcib_methods[] = {
+ /* Device interface */
+ DEVMETHOD(device_probe, pcib_probe),
+ DEVMETHOD(device_attach, pcib_attach),
+ DEVMETHOD(device_shutdown, bus_generic_shutdown),
+ DEVMETHOD(device_suspend, bus_generic_suspend),
+ DEVMETHOD(device_resume, bus_generic_resume),
+
+ /* Bus interface */
+ DEVMETHOD(bus_print_child, bus_generic_print_child),
+ DEVMETHOD(bus_read_ivar, pcib_read_ivar),
+ DEVMETHOD(bus_write_ivar, pcib_write_ivar),
+ DEVMETHOD(bus_alloc_resource, pcib_alloc_resource),
+ DEVMETHOD(bus_release_resource, bus_generic_release_resource),
+ DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
+ DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
+ DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
+ DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
+
+ /* pcib interface */
+ DEVMETHOD(pcib_maxslots, pcib_maxslots),
+ DEVMETHOD(pcib_read_config, pcib_read_config),
+ DEVMETHOD(pcib_write_config, pcib_write_config),
+ DEVMETHOD(pcib_route_interrupt, pcib_route_interrupt),
+
+ { 0, 0 }
+};
+
+static driver_t pcib_driver = {
+ "pcib",
+ pcib_methods,
+ sizeof(struct pcib_softc),
+};
+
+devclass_t pcib_devclass;
+
+DRIVER_MODULE(pcib, pci, pcib_driver, pcib_devclass, 0, 0);
+
+/*
+ * sysctl and tunable vars
+ */
+static int pci_allow_unsupported_io_range = 0;
+TUNABLE_INT("hw.pci.allow_unsupported_io_range",
+ (int *)&pci_allow_unsupported_io_range);
+SYSCTL_DECL(_hw_pci);
+SYSCTL_INT(_hw_pci, OID_AUTO, allow_unsupported_io_range, CTLFLAG_RD,
+ &pci_allow_unsupported_io_range, 0,
+ "Allows the PCI Bridge to pass through an unsupported memory range "
+ "assigned by the BIOS.");
+
+/*
+ * Generic device interface
+ */
+static int
+pcib_probe(device_t dev)
+{
+ if ((pci_get_class(dev) == PCIC_BRIDGE) &&
+ (pci_get_subclass(dev) == PCIS_BRIDGE_PCI)) {
+ device_set_desc(dev, "PCI-PCI bridge");
+ return(-10000);
+ }
+ return(ENXIO);
+}
+
+void
+pcib_attach_common(device_t dev)
+{
+ struct pcib_softc *sc;
+ u_int8_t iolow;
+
+ sc = device_get_softc(dev);
+ sc->dev = dev;
+
+ /*
+ * Get current bridge configuration.
+ */
+ sc->command = pci_read_config(dev, PCIR_COMMAND, 1);
+ sc->secbus = pci_read_config(dev, PCIR_SECBUS_1, 1);
+ sc->subbus = pci_read_config(dev, PCIR_SUBBUS_1, 1);
+ sc->secstat = pci_read_config(dev, PCIR_SECSTAT_1, 2);
+ sc->bridgectl = pci_read_config(dev, PCIR_BRIDGECTL_1, 2);
+ sc->seclat = pci_read_config(dev, PCIR_SECLAT_1, 1);
+
+ /*
+ * Determine current I/O decode.
+ */
+ if (sc->command & PCIM_CMD_PORTEN) {
+ iolow = pci_read_config(dev, PCIR_IOBASEL_1, 1);
+ if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) {
+ sc->iobase = PCI_PPBIOBASE(pci_read_config(dev, PCIR_IOBASEH_1, 2),
+ pci_read_config(dev, PCIR_IOBASEL_1, 1));
+ } else {
+ sc->iobase = PCI_PPBIOBASE(0, pci_read_config(dev, PCIR_IOBASEL_1, 1));
+ }
+
+ iolow = pci_read_config(dev, PCIR_IOLIMITL_1, 1);
+ if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) {
+ sc->iolimit = PCI_PPBIOLIMIT(pci_read_config(dev, PCIR_IOLIMITH_1, 2),
+ pci_read_config(dev, PCIR_IOLIMITL_1, 1));
+ } else {
+ sc->iolimit = PCI_PPBIOLIMIT(0, pci_read_config(dev, PCIR_IOLIMITL_1, 1));
+ }
+ }
+
+ /*
+ * Determine current memory decode.
+ */
+ if (sc->command & PCIM_CMD_MEMEN) {
+ sc->membase = PCI_PPBMEMBASE(0, pci_read_config(dev, PCIR_MEMBASE_1, 2));
+ sc->memlimit = PCI_PPBMEMLIMIT(0, pci_read_config(dev, PCIR_MEMLIMIT_1, 2));
+ sc->pmembase = PCI_PPBMEMBASE((pci_addr_t)pci_read_config(dev, PCIR_PMBASEH_1, 4),
+ pci_read_config(dev, PCIR_PMBASEL_1, 2));
+ sc->pmemlimit = PCI_PPBMEMLIMIT((pci_addr_t)pci_read_config(dev, PCIR_PMLIMITH_1, 4),
+ pci_read_config(dev, PCIR_PMLIMITL_1, 2));
+ }
+
+ /*
+ * Quirk handling.
+ */
+ switch (pci_get_devid(dev)) {
+ case 0x12258086: /* Intel 82454KX/GX (Orion) */
+ {
+ u_int8_t supbus;
+
+ supbus = pci_read_config(dev, 0x41, 1);
+ if (supbus != 0xff) {
+ sc->secbus = supbus + 1;
+ sc->subbus = supbus + 1;
+ }
+ }
+ break;
+ }
+
+ if (bootverbose) {
+ device_printf(dev, " secondary bus %d\n", sc->secbus);
+ device_printf(dev, " subordinate bus %d\n", sc->subbus);
+ device_printf(dev, " I/O decode 0x%x-0x%x\n", sc->iobase, sc->iolimit);
+ device_printf(dev, " memory decode 0x%x-0x%x\n", sc->membase, sc->memlimit);
+ device_printf(dev, " prefetched decode 0x%x-0x%x\n", sc->pmembase, sc->pmemlimit);
+ }
+
+ /*
+ * XXX If the secondary bus number is zero, we should assign a bus number
+ * since the BIOS hasn't, then initialise the bridge.
+ */
+
+ /*
+ * XXX If the subordinate bus number is less than the secondary bus number,
+ * we should pick a better value. One sensible alternative would be to
+ * pick 255; the only tradeoff here is that configuration transactions
+ * would be more widely routed than absolutely necessary.
+ */
+}
+
+int
+pcib_attach(device_t dev)
+{
+ struct pcib_softc *sc;
+ device_t child;
+
+ pcib_attach_common(dev);
+ sc = device_get_softc(dev);
+ if (sc->secbus != 0) {
+ child = device_add_child(dev, "pci", sc->secbus);
+ if (child != NULL)
+ return(bus_generic_attach(dev));
+ }
+
+ /* no secondary bus; we should have fixed this */
+ return(0);
+}
+
+int
+pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
+{
+ struct pcib_softc *sc = device_get_softc(dev);
+
+ switch (which) {
+ case PCIB_IVAR_BUS:
+ *result = sc->secbus;
+ return(0);
+ }
+ return(ENOENT);
+}
+
+int
+pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
+{
+ struct pcib_softc *sc = device_get_softc(dev);
+
+ switch (which) {
+ case PCIB_IVAR_BUS:
+ sc->secbus = value;
+ break;
+ }
+ return(ENOENT);
+}
+
+/*
+ * Is this a decoded ISA I/O port address? Note, we need to do the mask that
+ * we do below because of the ISA alias addresses. I'm not 100% sure that
+ * this is correct.
+ */
+static int
+pcib_is_isa_io(u_long start)
+{
+ if ((start & 0xfffUL) > 0x3ffUL || start == 0)
+ return (0);
+ return (1);
+}
+
+/*
+ * Is this a decoded ISA memory address?
+ */
+static int
+pcib_is_isa_mem(u_long start)
+{
+ if (start > 0xfffffUL || start == 0)
+ return (0);
+ return (1);
+}
+
+/*
+ * We have to trap resource allocation requests and ensure that the bridge
+ * is set up to, or capable of handling them.
+ */
+struct resource *
+pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
+ u_long start, u_long end, u_long count, u_int flags)
+{
+ struct pcib_softc *sc = device_get_softc(dev);
+
+ /*
+ * If this is a "default" allocation against this rid, we can't work
+ * out where it's coming from (we should actually never see these) so we
+ * just have to punt.
+ */
+ if ((start == 0) && (end == ~0)) {
+ device_printf(dev, "can't decode default resource id %d for %s%d, bypassing\n",
+ *rid, device_get_name(child), device_get_unit(child));
+ } else {
+ /*
+ * Fail the allocation for this range if it's not supported.
+ *
+ * XXX we should probably just fix up the bridge decode and soldier on.
+ */
+ switch (type) {
+ case SYS_RES_IOPORT:
+ if (!pcib_is_isa_io(start)) {
+ if (!pci_allow_unsupported_io_range) {
+ if (start < sc->iobase)
+ start = sc->iobase;
+ if (end > sc->iolimit)
+ end = sc->iolimit;
+ if (end < start)
+ start = 0;
+ } else {
+ if (start < sc->iobase)
+ printf("start (%lx) < sc->iobase (%x)\n", start,
+ sc->iobase);
+ if (end > sc->iolimit)
+ printf("end (%lx) > sc->iolimit (%x)\n",
+ end, sc->iolimit);
+ if (end < start)
+ printf("end (%lx) < start (%lx)\n", end, start);
+ }
+ }
+ if (!pcib_is_isa_io(start) &&
+ ((start < sc->iobase) || (end > sc->iolimit))) {
+ device_printf(dev, "device %s%d requested unsupported I/O range 0x%lx-0x%lx"
+ " (decoding 0x%x-0x%x)\n",
+ device_get_name(child), device_get_unit(child), start, end,
+ sc->iobase, sc->iolimit);
+ return (NULL);
+ }
+ if (bootverbose)
+ device_printf(sc->dev, "device %s%d requested decoded I/O range 0x%lx-0x%lx\n",
+ device_get_name(child), device_get_unit(child), start, end);
+ break;
+
+ /*
+ * XXX will have to decide whether the device making the request is asking
+ * for prefetchable memory or not. If it's coming from another bridge
+ * down the line, do we assume not, or ask the bridge to pass in another
+ * flag as the request bubbles up?
+ */
+ case SYS_RES_MEMORY:
+ if (!pcib_is_isa_mem(start)) {
+ if (!pci_allow_unsupported_io_range) {
+ if (start < sc->membase && end >= sc->membase)
+ start = sc->membase;
+ if (end > sc->memlimit)
+ end = sc->memlimit;
+ if (end < start)
+ start = 0;
+ } else {
+ if (start < sc->membase && end > sc->membase)
+ printf("start (%lx) < sc->membase (%x)\n",
+ start, sc->membase);
+ if (end > sc->memlimit)
+ printf("end (%lx) > sc->memlimit (%x)\n",
+ end, sc->memlimit);
+ if (end < start)
+ printf("end (%lx) < start (%lx)\n", end, start);
+ }
+ }
+ if (!pcib_is_isa_mem(start) &&
+ (((start < sc->membase) || (end > sc->memlimit)) &&
+ ((start < sc->pmembase) || (end > sc->pmemlimit)))) {
+ if (bootverbose)
+ device_printf(dev,
+ "device %s%d requested unsupported memory range "
+ "0x%lx-0x%lx (decoding 0x%x-0x%x, 0x%x-0x%x)\n",
+ device_get_name(child), device_get_unit(child), start,
+ end, sc->membase, sc->memlimit, sc->pmembase,
+ sc->pmemlimit);
+ if (!pci_allow_unsupported_io_range)
+ return (NULL);
+ }
+ if (bootverbose)
+ device_printf(sc->dev, "device %s%d requested decoded memory range 0x%lx-0x%lx\n",
+ device_get_name(child), device_get_unit(child), start, end);
+ break;
+
+ default:
+ break;
+ }
+ }
+
+ /*
+ * Bridge is OK decoding this resource, so pass it up.
+ */
+ return(bus_generic_alloc_resource(dev, child, type, rid, start, end, count, flags));
+}
+
+/*
+ * PCIB interface.
+ */
+int
+pcib_maxslots(device_t dev)
+{
+ return(PCI_SLOTMAX);
+}
+
+/*
+ * Since we are a child of a PCI bus, its parent must support the pcib interface.
+ */
+u_int32_t
+pcib_read_config(device_t dev, int b, int s, int f, int reg, int width)
+{
+ return(PCIB_READ_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, width));
+}
+
+void
+pcib_write_config(device_t dev, int b, int s, int f, int reg, u_int32_t val, int width)
+{
+ PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, val, width);
+}
+
+/*
+ * Route an interrupt across a PCI bridge.
+ */
+static int
+pcib_route_interrupt(device_t pcib, device_t dev, int pin)
+{
+ device_t bus;
+ int parent_intpin;
+ int intnum;
+
+ /*
+ *
+ * The PCI standard defines a swizzle of the child-side device/intpin to
+ * the parent-side intpin as follows.
+ *
+ * device = device on child bus
+ * child_intpin = intpin on child bus slot (0-3)
+ * parent_intpin = intpin on parent bus slot (0-3)
+ *
+ * parent_intpin = (device + child_intpin) % 4
+ */
+ parent_intpin = (pci_get_slot(pcib) + (pin - 1)) % 4;
+
+ /*
+ * Our parent is a PCI bus. Its parent must export the pcib interface
+ * which includes the ability to route interrupts.
+ */
+ bus = device_get_parent(pcib);
+ intnum = PCIB_ROUTE_INTERRUPT(device_get_parent(bus), pcib, parent_intpin + 1);
+ if (PCI_INTERRUPT_VALID(intnum)) {
+ device_printf(pcib, "slot %d INT%c is routed to irq %d\n",
+ pci_get_slot(dev), 'A' + pin - 1, intnum);
+ }
+ return(intnum);
+}
+
+/*
+ * Try to read the bus number of a host-PCI bridge using appropriate config
+ * registers.
+ */
+int
+host_pcib_get_busno(pci_read_config_fn read_config, int bus, int slot, int func,
+ u_int8_t *busnum)
+{
+ u_int32_t id;
+
+ id = read_config(bus, slot, func, PCIR_DEVVENDOR, 4);
+ if (id == 0xffffffff)
+ return (0);
+
+ switch (id) {
+ case 0x12258086:
+ /* Intel 824?? */
+ /* XXX This is a guess */
+ /* *busnum = read_config(bus, slot, func, 0x41, 1); */
+ *busnum = bus;
+ break;
+ case 0x84c48086:
+ /* Intel 82454KX/GX (Orion) */
+ *busnum = read_config(bus, slot, func, 0x4a, 1);
+ break;
+ case 0x84ca8086:
+ /*
+ * For the 450nx chipset, there is a whole bundle of
+ * things pretending to be host bridges. The MIOC will
+ * be seen first and isn't really a pci bridge (the
+ * actual busses are attached to the PXB's). We need to
+ * read the registers of the MIOC to figure out the
+ * bus numbers for the PXB channels.
+ *
+ * Since the MIOC doesn't have a pci bus attached, we
+ * pretend it wasn't there.
+ */
+ return (0);
+ case 0x84cb8086:
+ switch (slot) {
+ case 0x12:
+ /* Intel 82454NX PXB#0, Bus#A */
+ *busnum = read_config(bus, 0x10, func, 0xd0, 1);
+ break;
+ case 0x13:
+ /* Intel 82454NX PXB#0, Bus#B */
+ *busnum = read_config(bus, 0x10, func, 0xd1, 1) + 1;
+ break;
+ case 0x14:
+ /* Intel 82454NX PXB#1, Bus#A */
+ *busnum = read_config(bus, 0x10, func, 0xd3, 1);
+ break;
+ case 0x15:
+ /* Intel 82454NX PXB#1, Bus#B */
+ *busnum = read_config(bus, 0x10, func, 0xd4, 1) + 1;
+ break;
+ }
+ break;
+
+ /* ServerWorks -- vendor 0x1166 */
+ case 0x00051166:
+ case 0x00061166:
+ case 0x00081166:
+ case 0x00091166:
+ case 0x00101166:
+ case 0x00111166:
+ case 0x00171166:
+ case 0x01011166:
+ case 0x010f1014:
+ case 0x02011166:
+ case 0x03021014:
+ *busnum = read_config(bus, slot, func, 0x44, 1);
+ break;
+ default:
+ /* Don't know how to read bus number. */
+ return 0;
+ }
+
+ return 1;
+}
diff --git a/sys/dev/pci/pci_private.h b/sys/dev/pci/pci_private.h
new file mode 100644
index 0000000..1b14bc8
--- /dev/null
+++ b/sys/dev/pci/pci_private.h
@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
+ * Copyright (c) 2000, Michael Smith <msmith@freebsd.org>
+ * Copyright (c) 2000, BSDi
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice unmodified, this list of conditions, and the following
+ * disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ *
+ */
+
+#ifndef _PCI_PRIVATE_H_
+#define _PCI_PRIVATE_H_
+
+/*
+ * Export definitions of the pci bus so that we can more easily share
+ * it with "subclass" busses. A more generic subclassing mechanism would
+ * be nice, but is not present in the tree at this time.
+ */
+extern devclass_t pci_devclass;
+
+void pci_add_children(device_t dev, int busno, size_t dinfo_size);
+void pci_add_child(device_t bus, struct pci_devinfo *dinfo);
+int pci_print_child(device_t dev, device_t child);
+void pci_probe_nomatch(device_t dev, device_t child);
+int pci_read_ivar(device_t dev, device_t child, int which,
+ uintptr_t *result);
+int pci_write_ivar(device_t dev, device_t child, int which,
+ uintptr_t value);
+int pci_set_powerstate_method(device_t dev, device_t child,
+ int state);
+int pci_get_powerstate_method(device_t dev, device_t child);
+u_int32_t pci_read_config_method(device_t dev, device_t child,
+ int reg, int width);
+void pci_write_config_method(device_t dev, device_t child,
+ int reg, u_int32_t val, int width);
+void pci_enable_busmaster_method(device_t dev, device_t child);
+void pci_disable_busmaster_method(device_t dev, device_t child);
+void pci_enable_io_method(device_t dev, device_t child, int space);
+void pci_disable_io_method(device_t dev, device_t child, int space);
+struct resource *pci_alloc_resource(device_t dev, device_t child,
+ int type, int *rid, u_long start, u_long end, u_long count,
+ u_int flags);
+void pci_delete_resource(device_t dev, device_t child,
+ int type, int rid);
+struct resource_list *pci_get_resource_list (device_t dev, device_t child);
+struct pci_devinfo *pci_read_device(device_t pcib, int b, int s, int f,
+ size_t size);
+void pci_print_verbose(struct pci_devinfo *dinfo);
+int pci_freecfg(struct pci_devinfo *dinfo);
+
+#endif /* _PCI_PRIVATE_H_ */
diff --git a/sys/dev/pci/pci_user.c b/sys/dev/pci/pci_user.c
new file mode 100644
index 0000000..83b63b3
--- /dev/null
+++ b/sys/dev/pci/pci_user.c
@@ -0,0 +1,492 @@
+/*
+ * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice unmodified, this list of conditions, and the following
+ * disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ *
+ */
+
+#include "opt_bus.h" /* XXX trim includes */
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/malloc.h>
+#include <sys/module.h>
+#include <sys/linker.h>
+#include <sys/fcntl.h>
+#include <sys/conf.h>
+#include <sys/kernel.h>
+#include <sys/proc.h>
+#include <sys/queue.h>
+#include <sys/types.h>
+
+#include <vm/vm.h>
+#include <vm/pmap.h>
+#include <vm/vm_extern.h>
+
+#include <sys/bus.h>
+#include <machine/bus.h>
+#include <sys/rman.h>
+#include <machine/resource.h>
+
+#include <sys/pciio.h>
+#include <pci/pcireg.h>
+#include <pci/pcivar.h>
+
+#include "pcib_if.h"
+#include "pci_if.h"
+
+/*
+ * This is the user interface to PCI configuration space.
+ */
+
+static d_open_t pci_open;
+static d_close_t pci_close;
+static int pci_conf_match(struct pci_match_conf *matches, int num_matches,
+ struct pci_conf *match_buf);
+static d_ioctl_t pci_ioctl;
+
+#define PCI_CDEV 78
+
+struct cdevsw pcicdev = {
+ /* open */ pci_open,
+ /* close */ pci_close,
+ /* read */ noread,
+ /* write */ nowrite,
+ /* ioctl */ pci_ioctl,
+ /* poll */ nopoll,
+ /* mmap */ nommap,
+ /* strategy */ nostrategy,
+ /* name */ "pci",
+ /* maj */ PCI_CDEV,
+ /* dump */ nodump,
+ /* psize */ nopsize,
+ /* flags */ 0,
+};
+
+static int
+pci_open(dev_t dev, int oflags, int devtype, struct thread *td)
+{
+ int error;
+
+ if (oflags & FWRITE) {
+ error = securelevel_gt(td->td_ucred, 0);
+ if (error)
+ return (error);
+ }
+
+ return (0);
+}
+
+static int
+pci_close(dev_t dev, int flag, int devtype, struct thread *td)
+{
+ return 0;
+}
+
+/*
+ * Match a single pci_conf structure against an array of pci_match_conf
+ * structures. The first argument, 'matches', is an array of num_matches
+ * pci_match_conf structures. match_buf is a pointer to the pci_conf
+ * structure that will be compared to every entry in the matches array.
+ * This function returns 1 on failure, 0 on success.
+ */
+static int
+pci_conf_match(struct pci_match_conf *matches, int num_matches,
+ struct pci_conf *match_buf)
+{
+ int i;
+
+ if ((matches == NULL) || (match_buf == NULL) || (num_matches <= 0))
+ return(1);
+
+ for (i = 0; i < num_matches; i++) {
+ /*
+ * I'm not sure why someone would do this...but...
+ */
+ if (matches[i].flags == PCI_GETCONF_NO_MATCH)
+ continue;
+
+ /*
+ * Look at each of the match flags. If it's set, do the
+ * comparison. If the comparison fails, we don't have a
+ * match, go on to the next item if there is one.
+ */
+ if (((matches[i].flags & PCI_GETCONF_MATCH_BUS) != 0)
+ && (match_buf->pc_sel.pc_bus != matches[i].pc_sel.pc_bus))
+ continue;
+
+ if (((matches[i].flags & PCI_GETCONF_MATCH_DEV) != 0)
+ && (match_buf->pc_sel.pc_dev != matches[i].pc_sel.pc_dev))
+ continue;
+
+ if (((matches[i].flags & PCI_GETCONF_MATCH_FUNC) != 0)
+ && (match_buf->pc_sel.pc_func != matches[i].pc_sel.pc_func))
+ continue;
+
+ if (((matches[i].flags & PCI_GETCONF_MATCH_VENDOR) != 0)
+ && (match_buf->pc_vendor != matches[i].pc_vendor))
+ continue;
+
+ if (((matches[i].flags & PCI_GETCONF_MATCH_DEVICE) != 0)
+ && (match_buf->pc_device != matches[i].pc_device))
+ continue;
+
+ if (((matches[i].flags & PCI_GETCONF_MATCH_CLASS) != 0)
+ && (match_buf->pc_class != matches[i].pc_class))
+ continue;
+
+ if (((matches[i].flags & PCI_GETCONF_MATCH_UNIT) != 0)
+ && (match_buf->pd_unit != matches[i].pd_unit))
+ continue;
+
+ if (((matches[i].flags & PCI_GETCONF_MATCH_NAME) != 0)
+ && (strncmp(matches[i].pd_name, match_buf->pd_name,
+ sizeof(match_buf->pd_name)) != 0))
+ continue;
+
+ return(0);
+ }
+
+ return(1);
+}
+
+static int
+pci_ioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct thread *td)
+{
+ device_t pci, pcib;
+ struct pci_io *io;
+ const char *name;
+ int error;
+
+ if (!(flag & FWRITE))
+ return EPERM;
+
+
+ switch(cmd) {
+ case PCIOCGETCONF:
+ {
+ struct pci_devinfo *dinfo;
+ struct pci_conf_io *cio;
+ struct devlist *devlist_head;
+ struct pci_match_conf *pattern_buf;
+ int num_patterns;
+ size_t iolen;
+ int ionum, i;
+
+ cio = (struct pci_conf_io *)data;
+
+ num_patterns = 0;
+ dinfo = NULL;
+
+ /*
+ * Hopefully the user won't pass in a null pointer, but it
+ * can't hurt to check.
+ */
+ if (cio == NULL) {
+ error = EINVAL;
+ break;
+ }
+
+ /*
+ * If the user specified an offset into the device list,
+ * but the list has changed since they last called this
+ * ioctl, tell them that the list has changed. They will
+ * have to get the list from the beginning.
+ */
+ if ((cio->offset != 0)
+ && (cio->generation != pci_generation)){
+ cio->num_matches = 0;
+ cio->status = PCI_GETCONF_LIST_CHANGED;
+ error = 0;
+ break;
+ }
+
+ /*
+ * Check to see whether the user has asked for an offset
+ * past the end of our list.
+ */
+ if (cio->offset >= pci_numdevs) {
+ cio->num_matches = 0;
+ cio->status = PCI_GETCONF_LAST_DEVICE;
+ error = 0;
+ break;
+ }
+
+ /* get the head of the device queue */
+ devlist_head = &pci_devq;
+
+ /*
+ * Determine how much room we have for pci_conf structures.
+ * Round the user's buffer size down to the nearest
+ * multiple of sizeof(struct pci_conf) in case the user
+ * didn't specify a multiple of that size.
+ */
+ iolen = min(cio->match_buf_len -
+ (cio->match_buf_len % sizeof(struct pci_conf)),
+ pci_numdevs * sizeof(struct pci_conf));
+
+ /*
+ * Since we know that iolen is a multiple of the size of
+ * the pciconf union, it's okay to do this.
+ */
+ ionum = iolen / sizeof(struct pci_conf);
+
+ /*
+ * If this test is true, the user wants the pci_conf
+ * structures returned to match the supplied entries.
+ */
+ if ((cio->num_patterns > 0)
+ && (cio->pat_buf_len > 0)) {
+ /*
+ * pat_buf_len needs to be:
+ * num_patterns * sizeof(struct pci_match_conf)
+ * While it is certainly possible the user just
+ * allocated a large buffer, but set the number of
+ * matches correctly, it is far more likely that
+ * their kernel doesn't match the userland utility
+ * they're using. It's also possible that the user
+ * forgot to initialize some variables. Yes, this
+ * may be overly picky, but I hazard to guess that
+ * it's far more likely to just catch folks that
+ * updated their kernel but not their userland.
+ */
+ if ((cio->num_patterns *
+ sizeof(struct pci_match_conf)) != cio->pat_buf_len){
+ /* The user made a mistake, return an error*/
+ cio->status = PCI_GETCONF_ERROR;
+ printf("pci_ioctl: pat_buf_len %d != "
+ "num_patterns (%d) * sizeof(struct "
+ "pci_match_conf) (%d)\npci_ioctl: "
+ "pat_buf_len should be = %d\n",
+ cio->pat_buf_len, cio->num_patterns,
+ (int)sizeof(struct pci_match_conf),
+ (int)sizeof(struct pci_match_conf) *
+ cio->num_patterns);
+ printf("pci_ioctl: do your headers match your "
+ "kernel?\n");
+ cio->num_matches = 0;
+ error = EINVAL;
+ break;
+ }
+
+ /*
+ * Check the user's buffer to make sure it's readable.
+ */
+ if (!useracc((caddr_t)cio->patterns,
+ cio->pat_buf_len, VM_PROT_READ)) {
+ printf("pci_ioctl: pattern buffer %p, "
+ "length %u isn't user accessible for"
+ " READ\n", cio->patterns,
+ cio->pat_buf_len);
+ error = EACCES;
+ break;
+ }
+ /*
+ * Allocate a buffer to hold the patterns.
+ */
+ pattern_buf = malloc(cio->pat_buf_len, M_TEMP,
+ M_WAITOK);
+ error = copyin(cio->patterns, pattern_buf,
+ cio->pat_buf_len);
+ if (error != 0)
+ break;
+ num_patterns = cio->num_patterns;
+
+ } else if ((cio->num_patterns > 0)
+ || (cio->pat_buf_len > 0)) {
+ /*
+ * The user made a mistake, spit out an error.
+ */
+ cio->status = PCI_GETCONF_ERROR;
+ cio->num_matches = 0;
+ printf("pci_ioctl: invalid GETCONF arguments\n");
+ error = EINVAL;
+ break;
+ } else
+ pattern_buf = NULL;
+
+ /*
+ * Make sure we can write to the match buffer.
+ */
+ if (!useracc((caddr_t)cio->matches,
+ cio->match_buf_len, VM_PROT_WRITE)) {
+ printf("pci_ioctl: match buffer %p, length %u "
+ "isn't user accessible for WRITE\n",
+ cio->matches, cio->match_buf_len);
+ error = EACCES;
+ break;
+ }
+
+ /*
+ * Go through the list of devices and copy out the devices
+ * that match the user's criteria.
+ */
+ for (cio->num_matches = 0, error = 0, i = 0,
+ dinfo = STAILQ_FIRST(devlist_head);
+ (dinfo != NULL) && (cio->num_matches < ionum)
+ && (error == 0) && (i < pci_numdevs);
+ dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
+
+ if (i < cio->offset)
+ continue;
+
+ /* Populate pd_name and pd_unit */
+ name = NULL;
+ if (dinfo->cfg.dev && dinfo->conf.pd_name[0] == '\0')
+ name = device_get_name(dinfo->cfg.dev);
+ if (name) {
+ strncpy(dinfo->conf.pd_name, name,
+ sizeof(dinfo->conf.pd_name));
+ dinfo->conf.pd_name[PCI_MAXNAMELEN] = 0;
+ dinfo->conf.pd_unit =
+ device_get_unit(dinfo->cfg.dev);
+ }
+
+ if ((pattern_buf == NULL) ||
+ (pci_conf_match(pattern_buf, num_patterns,
+ &dinfo->conf) == 0)) {
+
+ /*
+ * If we've filled up the user's buffer,
+ * break out at this point. Since we've
+ * got a match here, we'll pick right back
+ * up at the matching entry. We can also
+ * tell the user that there are more matches
+ * left.
+ */
+ if (cio->num_matches >= ionum)
+ break;
+
+ error = copyout(&dinfo->conf,
+ &cio->matches[cio->num_matches],
+ sizeof(struct pci_conf));
+ cio->num_matches++;
+ }
+ }
+
+ /*
+ * Set the pointer into the list, so if the user is getting
+ * n records at a time, where n < pci_numdevs,
+ */
+ cio->offset = i;
+
+ /*
+ * Set the generation, the user will need this if they make
+ * another ioctl call with offset != 0.
+ */
+ cio->generation = pci_generation;
+
+ /*
+ * If this is the last device, inform the user so he won't
+ * bother asking for more devices. If dinfo isn't NULL, we
+ * know that there are more matches in the list because of
+ * the way the traversal is done.
+ */
+ if (dinfo == NULL)
+ cio->status = PCI_GETCONF_LAST_DEVICE;
+ else
+ cio->status = PCI_GETCONF_MORE_DEVS;
+
+ if (pattern_buf != NULL)
+ free(pattern_buf, M_TEMP);
+
+ break;
+ }
+ case PCIOCREAD:
+ io = (struct pci_io *)data;
+ switch(io->pi_width) {
+ case 4:
+ case 2:
+ case 1:
+ /*
+ * Assume that the user-level bus number is
+ * actually the pciN instance number. We map
+ * from that to the real pcib+bus combination.
+ */
+ pci = devclass_get_device(devclass_find("pci"),
+ io->pi_sel.pc_bus);
+ if (pci) {
+ int b = pcib_get_bus(pci);
+ pcib = device_get_parent(pci);
+ io->pi_data =
+ PCIB_READ_CONFIG(pcib,
+ b,
+ io->pi_sel.pc_dev,
+ io->pi_sel.pc_func,
+ io->pi_reg,
+ io->pi_width);
+ error = 0;
+ } else {
+ error = ENODEV;
+ }
+ break;
+ default:
+ error = ENODEV;
+ break;
+ }
+ break;
+
+ case PCIOCWRITE:
+ io = (struct pci_io *)data;
+ switch(io->pi_width) {
+ case 4:
+ case 2:
+ case 1:
+ /*
+ * Assume that the user-level bus number is
+ * actually the pciN instance number. We map
+ * from that to the real pcib+bus combination.
+ */
+ pci = devclass_get_device(devclass_find("pci"),
+ io->pi_sel.pc_bus);
+ if (pci) {
+ int b = pcib_get_bus(pci);
+ pcib = device_get_parent(pci);
+ PCIB_WRITE_CONFIG(pcib,
+ b,
+ io->pi_sel.pc_dev,
+ io->pi_sel.pc_func,
+ io->pi_reg,
+ io->pi_data,
+ io->pi_width);
+ error = 0;
+ } else {
+ error = ENODEV;
+ }
+ break;
+ default:
+ error = ENODEV;
+ break;
+ }
+ break;
+
+ default:
+ error = ENOTTY;
+ break;
+ }
+
+ return (error);
+}
+
diff --git a/sys/dev/pci/pcib_if.m b/sys/dev/pci/pcib_if.m
new file mode 100644
index 0000000..1ea2538
--- /dev/null
+++ b/sys/dev/pci/pcib_if.m
@@ -0,0 +1,81 @@
+#
+# Copyright (c) 2000 Doug Rabson
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+# 1. Redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution.
+#
+# THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+# ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+# OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+# HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+# OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+# SUCH DAMAGE.
+#
+# $FreeBSD$
+#
+
+#include <sys/bus.h>
+
+INTERFACE pcib;
+
+#
+# Return the number of slots on the attached PCI bus.
+#
+METHOD int maxslots {
+ device_t dev;
+};
+
+#
+# Read configuration space on the PCI bus. The bus, slot and func
+# arguments determine the device which is being read and the reg
+# argument is a byte offset into configuration space for that
+# device. The width argument (which should be 1, 2 or 4) specifies how
+# many byte of configuration space to read from that offset.
+#
+METHOD u_int32_t read_config {
+ device_t dev;
+ u_int bus;
+ u_int slot;
+ u_int func;
+ u_int reg;
+ int width;
+};
+
+#
+# Write configuration space on the PCI bus. The bus, slot and func
+# arguments determine the device which is being written and the reg
+# argument is a byte offset into configuration space for that
+# device. The value field is written to the configuration space, with
+# the number of bytes written depending on the width argument.
+#
+METHOD void write_config {
+ device_t dev;
+ u_int bus;
+ u_int slot;
+ u_int func;
+ u_int reg;
+ u_int32_t value;
+ int width;
+};
+
+#
+# Route an interrupt. Returns a value suitable for stuffing into
+# a device's interrupt register.
+#
+METHOD int route_interrupt {
+ device_t pcib;
+ device_t dev;
+ int pin;
+};
diff --git a/sys/dev/pci/pcib_private.h b/sys/dev/pci/pcib_private.h
new file mode 100644
index 0000000..b6ef8b8
--- /dev/null
+++ b/sys/dev/pci/pcib_private.h
@@ -0,0 +1,77 @@
+/*-
+ * Copyright (c) 1994,1995 Stefan Esser, Wolfgang StanglMeier
+ * Copyright (c) 2000 Michael Smith <msmith@freebsd.org>
+ * Copyright (c) 2000 BSDi
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#ifndef __PCIB_PRIVATE_H__
+#define __PCIB_PRIVATE_H__
+
+/*
+ * Export portions of generic PCI:PCI bridge support so that it can be
+ * used by subclasses.
+ */
+
+/*
+ * Bridge-specific data.
+ */
+struct pcib_softc
+{
+ device_t dev;
+ u_int16_t command; /* command register */
+ u_int8_t secbus; /* secondary bus number */
+ u_int8_t subbus; /* subordinate bus number */
+ pci_addr_t pmembase; /* base address of prefetchable memory */
+ pci_addr_t pmemlimit; /* topmost address of prefetchable memory */
+ pci_addr_t membase; /* base address of memory window */
+ pci_addr_t memlimit; /* topmost address of memory window */
+ u_int32_t iobase; /* base address of port window */
+ u_int32_t iolimit; /* topmost address of port window */
+ u_int16_t secstat; /* secondary bus status register */
+ u_int16_t bridgectl; /* bridge control register */
+ u_int8_t seclat; /* secondary bus latency timer */
+};
+
+typedef u_int32_t pci_read_config_fn(int b, int s, int f, int reg, int width);
+
+int host_pcib_get_busno(pci_read_config_fn read_config, int bus,
+ int slot, int func, u_int8_t *busnum);
+int pcib_attach(device_t dev);
+void pcib_attach_common(device_t dev);
+int pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result);
+int pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value);
+struct resource *pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
+ u_long start, u_long end, u_long count, u_int flags);
+int pcib_maxslots(device_t dev);
+u_int32_t pcib_read_config(device_t dev, int b, int s, int f, int reg, int width);
+void pcib_write_config(device_t dev, int b, int s, int f, int reg, u_int32_t val, int width);
+
+extern devclass_t pcib_devclass;
+
+#endif
diff --git a/sys/dev/pci/pcireg.h b/sys/dev/pci/pcireg.h
new file mode 100644
index 0000000..b1a45dd
--- /dev/null
+++ b/sys/dev/pci/pcireg.h
@@ -0,0 +1,319 @@
+/*
+ * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice unmodified, this list of conditions, and the following
+ * disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ *
+ */
+
+/*
+ * PCIM_xxx: mask to locate subfield in register
+ * PCIR_xxx: config register offset
+ * PCIC_xxx: device class
+ * PCIS_xxx: device subclass
+ * PCIP_xxx: device programming interface
+ * PCIV_xxx: PCI vendor ID (only required to fixup ancient devices)
+ * PCID_xxx: device ID
+ */
+
+/* some PCI bus constants */
+
+#define PCI_BUSMAX 255
+#define PCI_SLOTMAX 31
+#define PCI_FUNCMAX 7
+#define PCI_REGMAX 255
+
+/* PCI config header registers for all devices */
+
+#define PCIR_DEVVENDOR 0x00
+#define PCIR_VENDOR 0x00
+#define PCIR_DEVICE 0x02
+#define PCIR_COMMAND 0x04
+#define PCIM_CMD_PORTEN 0x0001
+#define PCIM_CMD_MEMEN 0x0002
+#define PCIM_CMD_BUSMASTEREN 0x0004
+#define PCIM_CMD_SPECIALEN 0x0008
+#define PCIM_CMD_MWRICEN 0x0010
+#define PCIM_CMD_PERRESPEN 0x0040
+#define PCIM_CMD_SERRESPEN 0x0100
+#define PCIM_CMD_BACKTOBACK 0x0200
+#define PCIR_STATUS 0x06
+#define PCIM_STATUS_CAPPRESENT 0x0010
+#define PCIM_STATUS_66CAPABLE 0x0020
+#define PCIM_STATUS_BACKTOBACK 0x0080
+#define PCIM_STATUS_PERRREPORT 0x0100
+#define PCIM_STATUS_SEL_FAST 0x0000
+#define PCIM_STATUS_SEL_MEDIMUM 0x0200
+#define PCIM_STATUS_SEL_SLOW 0x0400
+#define PCIM_STATUS_SEL_MASK 0x0600
+#define PCIM_STATUS_STABORT 0x0800
+#define PCIM_STATUS_RTABORT 0x1000
+#define PCIM_STATUS_RMABORT 0x2000
+#define PCIM_STATUS_SERR 0x4000
+#define PCIM_STATUS_PERR 0x8000
+#define PCIR_REVID 0x08
+#define PCIR_PROGIF 0x09
+#define PCIR_SUBCLASS 0x0a
+#define PCIR_CLASS 0x0b
+#define PCIR_CACHELNSZ 0x0c
+#define PCIR_LATTIMER 0x0d
+#define PCIR_HEADERTYPE 0x0e
+#define PCIM_MFDEV 0x80
+#define PCIR_BIST 0x0f
+
+/* config registers for header type 0 devices */
+
+#define PCIR_MAPS 0x10
+#define PCIR_CARDBUSCIS 0x28
+#define PCIR_SUBVEND_0 0x2c
+#define PCIR_SUBDEV_0 0x2e
+#define PCIR_BIOS 0x30
+#define PCIM_BIOS_ENABLE 0x01
+#define PCIR_CAP_PTR 0x34
+#define PCIR_INTLINE 0x3c
+#define PCIR_INTPIN 0x3d
+#define PCIR_MINGNT 0x3e
+#define PCIR_MAXLAT 0x3f
+
+/* config registers for header type 1 devices */
+
+#define PCIR_SECSTAT_1 0x1e
+
+#define PCIR_PRIBUS_1 0x18
+#define PCIR_SECBUS_1 0x19
+#define PCIR_SUBBUS_1 0x1a
+#define PCIR_SECLAT_1 0x1b
+
+#define PCIR_IOBASEL_1 0x1c
+#define PCIR_IOLIMITL_1 0x1d
+#define PCIR_IOBASEH_1 0x30
+#define PCIR_IOLIMITH_1 0x32
+#define PCIM_BRIO_16 0x0
+#define PCIM_BRIO_32 0x1
+#define PCIM_BRIO_MASK 0xf
+
+#define PCIR_MEMBASE_1 0x20
+#define PCIR_MEMLIMIT_1 0x22
+
+#define PCIR_PMBASEL_1 0x24
+#define PCIR_PMLIMITL_1 0x26
+#define PCIR_PMBASEH_1 0x28
+#define PCIR_PMLIMITH_1 0x2c
+
+#define PCIR_BRIDGECTL_1 0x3e
+
+#define PCIR_SUBVEND_1 0x34
+#define PCIR_SUBDEV_1 0x36
+
+/* config registers for header type 2 devices */
+
+#define PCIR_SECSTAT_2 0x16
+
+#define PCIR_PRIBUS_2 0x18
+#define PCIR_SECBUS_2 0x19
+#define PCIR_SUBBUS_2 0x1a
+#define PCIR_SECLAT_2 0x1b
+
+#define PCIR_MEMBASE0_2 0x1c
+#define PCIR_MEMLIMIT0_2 0x20
+#define PCIR_MEMBASE1_2 0x24
+#define PCIR_MEMLIMIT1_2 0x28
+#define PCIR_IOBASE0_2 0x2c
+#define PCIR_IOLIMIT0_2 0x30
+#define PCIR_IOBASE1_2 0x34
+#define PCIR_IOLIMIT1_2 0x38
+
+#define PCIR_BRIDGECTL_2 0x3e
+
+#define PCIR_SUBVEND_2 0x40
+#define PCIR_SUBDEV_2 0x42
+
+#define PCIR_PCCARDIF_2 0x44
+
+/* PCI device class, subclass and programming interface definitions */
+
+#define PCIC_OLD 0x00
+#define PCIS_OLD_NONVGA 0x00
+#define PCIS_OLD_VGA 0x01
+
+#define PCIC_STORAGE 0x01
+#define PCIS_STORAGE_SCSI 0x00
+#define PCIS_STORAGE_IDE 0x01
+#define PCIP_STORAGE_IDE_MODEPRIM 0x01
+#define PCIP_STORAGE_IDE_PROGINDPRIM 0x02
+#define PCIP_STORAGE_IDE_MODESEC 0x04
+#define PCIP_STORAGE_IDE_PROGINDSEC 0x08
+#define PCIP_STORAGE_IDE_MASTERDEV 0x80
+#define PCIS_STORAGE_FLOPPY 0x02
+#define PCIS_STORAGE_IPI 0x03
+#define PCIS_STORAGE_RAID 0x04
+#define PCIS_STORAGE_OTHER 0x80
+
+#define PCIC_NETWORK 0x02
+#define PCIS_NETWORK_ETHERNET 0x00
+#define PCIS_NETWORK_TOKENRING 0x01
+#define PCIS_NETWORK_FDDI 0x02
+#define PCIS_NETWORK_ATM 0x03
+#define PCIS_NETWORK_OTHER 0x80
+
+#define PCIC_DISPLAY 0x03
+#define PCIS_DISPLAY_VGA 0x00
+#define PCIS_DISPLAY_XGA 0x01
+#define PCIS_DISPLAY_OTHER 0x80
+
+#define PCIC_MULTIMEDIA 0x04
+#define PCIS_MULTIMEDIA_VIDEO 0x00
+#define PCIS_MULTIMEDIA_AUDIO 0x01
+#define PCIS_MULTIMEDIA_OTHER 0x80
+
+#define PCIC_MEMORY 0x05
+#define PCIS_MEMORY_RAM 0x00
+#define PCIS_MEMORY_FLASH 0x01
+#define PCIS_MEMORY_OTHER 0x80
+
+#define PCIC_BRIDGE 0x06
+#define PCIS_BRIDGE_HOST 0x00
+#define PCIS_BRIDGE_ISA 0x01
+#define PCIS_BRIDGE_EISA 0x02
+#define PCIS_BRIDGE_MCA 0x03
+#define PCIS_BRIDGE_PCI 0x04
+#define PCIS_BRIDGE_PCMCIA 0x05
+#define PCIS_BRIDGE_NUBUS 0x06
+#define PCIS_BRIDGE_CARDBUS 0x07
+#define PCIS_BRIDGE_OTHER 0x80
+
+#define PCIC_SIMPLECOMM 0x07
+#define PCIS_SIMPLECOMM_UART 0x00
+#define PCIP_SIMPLECOMM_UART_16550A 0x02
+#define PCIS_SIMPLECOMM_PAR 0x01
+#define PCIS_SIMPLECOMM_OTHER 0x80
+
+#define PCIC_BASEPERIPH 0x08
+#define PCIS_BASEPERIPH_PIC 0x00
+#define PCIS_BASEPERIPH_DMA 0x01
+#define PCIS_BASEPERIPH_TIMER 0x02
+#define PCIS_BASEPERIPH_RTC 0x03
+#define PCIS_BASEPERIPH_OTHER 0x80
+
+#define PCIC_INPUTDEV 0x09
+#define PCIS_INPUTDEV_KEYBOARD 0x00
+#define PCIS_INPUTDEV_DIGITIZER 0x01
+#define PCIS_INPUTDEV_MOUSE 0x02
+#define PCIS_INPUTDEV_OTHER 0x80
+
+#define PCIC_DOCKING 0x0a
+#define PCIS_DOCKING_GENERIC 0x00
+#define PCIS_DOCKING_OTHER 0x80
+
+#define PCIC_PROCESSOR 0x0b
+#define PCIS_PROCESSOR_386 0x00
+#define PCIS_PROCESSOR_486 0x01
+#define PCIS_PROCESSOR_PENTIUM 0x02
+#define PCIS_PROCESSOR_ALPHA 0x10
+#define PCIS_PROCESSOR_POWERPC 0x20
+#define PCIS_PROCESSOR_COPROC 0x40
+
+#define PCIC_SERIALBUS 0x0c
+#define PCIS_SERIALBUS_FW 0x00
+#define PCIS_SERIALBUS_ACCESS 0x01
+#define PCIS_SERIALBUS_SSA 0x02
+#define PCIS_SERIALBUS_USB 0x03
+#define PCIS_SERIALBUS_FC 0x04
+#define PCIS_SERIALBUS_SMBUS 0x05
+
+#define PCIC_OTHER 0xff
+
+/* PCI power manangement */
+
+#define PCIR_POWER_CAP 0x2
+#define PCIM_PCAP_SPEC 0x0007
+#define PCIM_PCAP_PMEREQCLK 0x0008
+#define PCIM_PCAP_PMEREQPWR 0x0010
+#define PCIM_PCAP_DEVSPECINIT 0x0020
+#define PCIM_PCAP_DYNCLOCK 0x0040
+#define PCIM_PCAP_SECCLOCK 0x00c0
+#define PCIM_PCAP_CLOCKMASK 0x00c0
+#define PCIM_PCAP_REQFULLCLOCK 0x0100
+#define PCIM_PCAP_D1SUPP 0x0200
+#define PCIM_PCAP_D2SUPP 0x0400
+#define PCIM_PCAP_D0PME 0x1000
+#define PCIM_PCAP_D1PME 0x2000
+#define PCIM_PCAP_D2PME 0x4000
+
+#define PCIR_POWER_STATUS 0x4
+#define PCIM_PSTAT_D0 0x0000
+#define PCIM_PSTAT_D1 0x0001
+#define PCIM_PSTAT_D2 0x0002
+#define PCIM_PSTAT_D3 0x0003
+#define PCIM_PSTAT_DMASK 0x0003
+#define PCIM_PSTAT_REPENABLE 0x0010
+#define PCIM_PSTAT_PMEENABLE 0x0100
+#define PCIM_PSTAT_D0POWER 0x0000
+#define PCIM_PSTAT_D1POWER 0x0200
+#define PCIM_PSTAT_D2POWER 0x0400
+#define PCIM_PSTAT_D3POWER 0x0600
+#define PCIM_PSTAT_D0HEAT 0x0800
+#define PCIM_PSTAT_D1HEAT 0x1000
+#define PCIM_PSTAT_D2HEAT 0x1200
+#define PCIM_PSTAT_D3HEAT 0x1400
+#define PCIM_PSTAT_DATAUNKN 0x0000
+#define PCIM_PSTAT_DATADIV10 0x2000
+#define PCIM_PSTAT_DATADIV100 0x4000
+#define PCIM_PSTAT_DATADIV1000 0x6000
+#define PCIM_PSTAT_DATADIVMASK 0x6000
+#define PCIM_PSTAT_PME 0x8000
+
+#define PCIR_POWER_PMCSR 0x6
+#define PCIM_PMCSR_DCLOCK 0x10
+#define PCIM_PMCSR_B2SUPP 0x20
+#define PCIM_BMCSR_B3SUPP 0x40
+#define PCIM_BMCSR_BPCE 0x80
+
+#define PCIR_POWER_DATA 0x7
+
+/* PCI-X definitions */
+#define PCIXR_COMMAND 0x96
+#define PCIXR_DEVADDR 0x98
+#define PCIXM_DEVADDR_FNUM 0x0003 /* Function Number */
+#define PCIXM_DEVADDR_DNUM 0x00F8 /* Device Number */
+#define PCIXM_DEVADDR_BNUM 0xFF00 /* Bus Number */
+#define PCIXR_STATUS 0x9A
+#define PCIXM_STATUS_64BIT 0x0001 /* Active 64bit connection to device. */
+#define PCIXM_STATUS_133CAP 0x0002 /* Device is 133MHz capable */
+#define PCIXM_STATUS_SCDISC 0x0004 /* Split Completion Discarded */
+#define PCIXM_STATUS_UNEXPSC 0x0008 /* Unexpected Split Completion */
+#define PCIXM_STATUS_CMPLEXDEV 0x0010 /* Device Complexity (set == bridge) */
+#define PCIXM_STATUS_MAXMRDBC 0x0060 /* Maximum Burst Read Count */
+#define PCIXM_STATUS_MAXSPLITS 0x0380 /* Maximum Split Transactions */
+#define PCIXM_STATUS_MAXCRDS 0x1C00 /* Maximum Cumulative Read Size */
+#define PCIXM_STATUS_RCVDSCEM 0x2000 /* Received a Split Comp w/Error msg */
+
+#if 0
+/* some PCI vendor definitions (only used to identify ancient devices !!! */
+
+#define PCIV_INTEL 0x8086
+
+#define PCID_INTEL_SATURN 0x0483
+#define PCID_INTEL_ORION 0x84c4
+#endif
diff --git a/sys/dev/pci/pcivar.h b/sys/dev/pci/pcivar.h
new file mode 100644
index 0000000..45df9e4
--- /dev/null
+++ b/sys/dev/pci/pcivar.h
@@ -0,0 +1,326 @@
+/*
+ * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice unmodified, this list of conditions, and the following
+ * disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ *
+ */
+
+#ifndef _PCIVAR_H_
+#define _PCIVAR_H_
+
+#include <sys/queue.h>
+
+/* some PCI bus constants */
+
+#define PCI_BUSMAX 255 /* highest supported bus number */
+#define PCI_SLOTMAX 31 /* highest supported slot number */
+#define PCI_FUNCMAX 7 /* highest supported function number */
+#define PCI_REGMAX 255 /* highest supported config register addr. */
+
+#define PCI_MAXMAPS_0 6 /* max. no. of memory/port maps */
+#define PCI_MAXMAPS_1 2 /* max. no. of maps for PCI to PCI bridge */
+#define PCI_MAXMAPS_2 1 /* max. no. of maps for CardBus bridge */
+
+/* pci_addr_t covers this system's PCI bus address space: 32 or 64 bit */
+
+#ifdef PCI_A64
+typedef u_int64_t pci_addr_t; /* u_int64_t for system with 64bit addresses */
+#else
+typedef u_int32_t pci_addr_t; /* u_int64_t for system with 64bit addresses */
+#endif
+
+/* config header information common to all header types */
+
+typedef struct pcicfg {
+ struct device *dev; /* device which owns this */
+
+ u_int16_t subvendor; /* card vendor ID */
+ u_int16_t subdevice; /* card device ID, assigned by card vendor */
+ u_int16_t vendor; /* chip vendor ID */
+ u_int16_t device; /* chip device ID, assigned by chip vendor */
+
+ u_int16_t cmdreg; /* disable/enable chip and PCI options */
+ u_int16_t statreg; /* supported PCI features and error state */
+
+ u_int8_t baseclass; /* chip PCI class */
+ u_int8_t subclass; /* chip PCI subclass */
+ u_int8_t progif; /* chip PCI programming interface */
+ u_int8_t revid; /* chip revision ID */
+
+ u_int8_t hdrtype; /* chip config header type */
+ u_int8_t cachelnsz; /* cache line size in 4byte units */
+ u_int8_t intpin; /* PCI interrupt pin */
+ u_int8_t intline; /* interrupt line (IRQ for PC arch) */
+
+ u_int8_t mingnt; /* min. useful bus grant time in 250ns units */
+ u_int8_t maxlat; /* max. tolerated bus grant latency in 250ns */
+ u_int8_t lattimer; /* latency timer in units of 30ns bus cycles */
+
+ u_int8_t mfdev; /* multi-function device (from hdrtype reg) */
+ u_int8_t nummaps; /* actual number of PCI maps used */
+
+ u_int8_t bus; /* config space bus address */
+ u_int8_t slot; /* config space slot address */
+ u_int8_t func; /* config space function number */
+
+ u_int16_t pp_cap; /* PCI power management capabilities */
+ u_int8_t pp_status; /* config space address of PCI power status reg */
+ u_int8_t pp_pmcsr; /* config space address of PMCSR reg */
+ u_int8_t pp_data; /* config space address of PCI power data reg */
+
+} pcicfgregs;
+
+/* additional type 1 device config header information (PCI to PCI bridge) */
+
+#ifdef PCI_A64
+#define PCI_PPBMEMBASE(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) & ~0xfffff)
+#define PCI_PPBMEMLIMIT(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) | 0xfffff)
+#else
+#define PCI_PPBMEMBASE(h,l) (((l)<<16) & ~0xfffff)
+#define PCI_PPBMEMLIMIT(h,l) (((l)<<16) | 0xfffff)
+#endif /* PCI_A64 */
+
+#define PCI_PPBIOBASE(h,l) ((((h)<<16) + ((l)<<8)) & ~0xfff)
+#define PCI_PPBIOLIMIT(h,l) ((((h)<<16) + ((l)<<8)) | 0xfff)
+
+typedef struct {
+ pci_addr_t pmembase; /* base address of prefetchable memory */
+ pci_addr_t pmemlimit; /* topmost address of prefetchable memory */
+ u_int32_t membase; /* base address of memory window */
+ u_int32_t memlimit; /* topmost address of memory window */
+ u_int32_t iobase; /* base address of port window */
+ u_int32_t iolimit; /* topmost address of port window */
+ u_int16_t secstat; /* secondary bus status register */
+ u_int16_t bridgectl; /* bridge control register */
+ u_int8_t seclat; /* CardBus latency timer */
+} pcih1cfgregs;
+
+/* additional type 2 device config header information (CardBus bridge) */
+
+typedef struct {
+ u_int32_t membase0; /* base address of memory window */
+ u_int32_t memlimit0; /* topmost address of memory window */
+ u_int32_t membase1; /* base address of memory window */
+ u_int32_t memlimit1; /* topmost address of memory window */
+ u_int32_t iobase0; /* base address of port window */
+ u_int32_t iolimit0; /* topmost address of port window */
+ u_int32_t iobase1; /* base address of port window */
+ u_int32_t iolimit1; /* topmost address of port window */
+ u_int32_t pccardif; /* PC Card 16bit IF legacy more base addr. */
+ u_int16_t secstat; /* secondary bus status register */
+ u_int16_t bridgectl; /* bridge control register */
+ u_int8_t seclat; /* CardBus latency timer */
+} pcih2cfgregs;
+
+extern u_int32_t pci_numdevs;
+
+/* Only if the prerequisites are present */
+#if defined(_SYS_BUS_H_) && defined(_SYS_PCIIO_H_)
+struct pci_devinfo {
+ STAILQ_ENTRY(pci_devinfo) pci_links;
+ struct resource_list resources;
+ pcicfgregs cfg;
+ struct pci_conf conf;
+};
+#endif
+
+#ifdef __alpha__
+vm_offset_t pci_cvt_to_dense (vm_offset_t);
+vm_offset_t pci_cvt_to_bwx (vm_offset_t);
+#endif /* __alpha__ */
+
+#ifdef _SYS_BUS_H_
+
+#include "pci_if.h"
+
+/*
+ * Define pci-specific resource flags for accessing memory via dense
+ * or bwx memory spaces. These flags are ignored on i386.
+ */
+#define PCI_RF_DENSE 0x10000
+#define PCI_RF_BWX 0x20000
+
+enum pci_device_ivars {
+ PCI_IVAR_SUBVENDOR,
+ PCI_IVAR_SUBDEVICE,
+ PCI_IVAR_VENDOR,
+ PCI_IVAR_DEVICE,
+ PCI_IVAR_DEVID,
+ PCI_IVAR_CLASS,
+ PCI_IVAR_SUBCLASS,
+ PCI_IVAR_PROGIF,
+ PCI_IVAR_REVID,
+ PCI_IVAR_INTPIN,
+ PCI_IVAR_IRQ,
+ PCI_IVAR_BUS,
+ PCI_IVAR_SLOT,
+ PCI_IVAR_FUNCTION,
+ PCI_IVAR_ETHADDR,
+};
+
+/*
+ * Simplified accessors for pci devices
+ */
+#define PCI_ACCESSOR(var, ivar, type) \
+ __BUS_ACCESSOR(pci, var, PCI, ivar, type)
+
+PCI_ACCESSOR(subvendor, SUBVENDOR, u_int16_t)
+PCI_ACCESSOR(subdevice, SUBDEVICE, u_int16_t)
+PCI_ACCESSOR(vendor, VENDOR, u_int16_t)
+PCI_ACCESSOR(device, DEVICE, u_int16_t)
+PCI_ACCESSOR(devid, DEVID, u_int32_t)
+PCI_ACCESSOR(class, CLASS, u_int8_t)
+PCI_ACCESSOR(subclass, SUBCLASS, u_int8_t)
+PCI_ACCESSOR(progif, PROGIF, u_int8_t)
+PCI_ACCESSOR(revid, REVID, u_int8_t)
+PCI_ACCESSOR(intpin, INTPIN, u_int8_t)
+PCI_ACCESSOR(irq, IRQ, u_int8_t)
+PCI_ACCESSOR(bus, BUS, u_int8_t)
+PCI_ACCESSOR(slot, SLOT, u_int8_t)
+PCI_ACCESSOR(function, FUNCTION, u_int8_t)
+PCI_ACCESSOR(ether, ETHADDR, u_int8_t *)
+
+#undef PCI_ACCESSOR
+
+/*
+ * Operations on configuration space.
+ */
+static __inline u_int32_t
+pci_read_config(device_t dev, int reg, int width)
+{
+ return PCI_READ_CONFIG(device_get_parent(dev), dev, reg, width);
+}
+
+static __inline void
+pci_write_config(device_t dev, int reg, u_int32_t val, int width)
+{
+ PCI_WRITE_CONFIG(device_get_parent(dev), dev, reg, val, width);
+}
+
+/*
+ * Ivars for pci bridges.
+ */
+
+/*typedef enum pci_device_ivars pcib_device_ivars;*/
+enum pcib_device_ivars {
+ PCIB_IVAR_BUS
+};
+
+#define PCIB_ACCESSOR(var, ivar, type) \
+ __BUS_ACCESSOR(pcib, var, PCIB, ivar, type)
+
+PCIB_ACCESSOR(bus, BUS, u_int32_t)
+
+#undef PCIB_ACCESSOR
+
+/*
+ * PCI interrupt validation. Invalid interrupt values such as 0 or 128
+ * on i386 or other platforms should be mapped out in the MD pcireadconf
+ * code and not here, since the only MI invalid IRQ is 255.
+ */
+#define PCI_INVALID_IRQ 255
+#define PCI_INTERRUPT_VALID(x) ((x) != PCI_INVALID_IRQ)
+
+/*
+ * Convenience functions.
+ *
+ * These should be used in preference to manually manipulating
+ * configuration space.
+ */
+static __inline void
+pci_enable_busmaster(device_t dev)
+{
+ PCI_ENABLE_BUSMASTER(device_get_parent(dev), dev);
+}
+
+static __inline void
+pci_disable_busmaster(device_t dev)
+{
+ PCI_DISABLE_BUSMASTER(device_get_parent(dev), dev);
+}
+
+static __inline void
+pci_enable_io(device_t dev, int space)
+{
+ PCI_ENABLE_IO(device_get_parent(dev), dev, space);
+}
+
+static __inline void
+pci_disable_io(device_t dev, int space)
+{
+ PCI_DISABLE_IO(device_get_parent(dev), dev, space);
+}
+
+/*
+ * PCI power states are as defined by ACPI:
+ *
+ * D0 State in which device is on and running. It is receiving full
+ * power from the system and delivering full functionality to the user.
+ * D1 Class-specific low-power state in which device context may or may not
+ * be lost. Buses in D1 cannot do anything to the bus that would force
+ * devices on that bus to loose context.
+ * D2 Class-specific low-power state in which device context may or may
+ * not be lost. Attains greater power savings than D1. Buses in D2
+ * can cause devices on that bus to loose some context. Devices in D2
+ * must be prepared for the bus to be in D2 or higher.
+ * D3 State in which the device is off and not running. Device context is
+ * lost. Power can be removed from the device.
+ */
+#define PCI_POWERSTATE_D0 0
+#define PCI_POWERSTATE_D1 1
+#define PCI_POWERSTATE_D2 2
+#define PCI_POWERSTATE_D3 3
+#define PCI_POWERSTATE_UNKNOWN -1
+
+static __inline int
+pci_set_powerstate(device_t dev, int state)
+{
+ return PCI_SET_POWERSTATE(device_get_parent(dev), dev, state);
+}
+
+static __inline int
+pci_get_powerstate(device_t dev)
+{
+ return PCI_GET_POWERSTATE(device_get_parent(dev), dev);
+}
+
+device_t pci_find_bsf(u_int8_t, u_int8_t, u_int8_t);
+device_t pci_find_device(u_int16_t, u_int16_t);
+#endif /* _SYS_BUS_H_ */
+
+/*
+ * cdev switch for control device, initialised in generic PCI code
+ */
+extern struct cdevsw pcicdev;
+
+/*
+ * List of all PCI devices, generation count for the list.
+ */
+STAILQ_HEAD(devlist, pci_devinfo);
+
+extern struct devlist pci_devq;
+extern u_int32_t pci_generation;
+
+#endif /* _PCIVAR_H_ */
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