diff options
Diffstat (limited to 'sys/dev/mpt')
| -rw-r--r-- | sys/dev/mpt/mpilib/fc_log.h | 110 | ||||
| -rw-r--r-- | sys/dev/mpt/mpilib/mpi.h | 705 | ||||
| -rw-r--r-- | sys/dev/mpt/mpilib/mpi_cnfg.h | 1623 | ||||
| -rw-r--r-- | sys/dev/mpt/mpilib/mpi_fc.h | 381 | ||||
| -rw-r--r-- | sys/dev/mpt/mpilib/mpi_init.h | 344 | ||||
| -rw-r--r-- | sys/dev/mpt/mpilib/mpi_ioc.h | 725 | ||||
| -rw-r--r-- | sys/dev/mpt/mpilib/mpi_lan.h | 234 | ||||
| -rw-r--r-- | sys/dev/mpt/mpilib/mpi_raid.h | 254 | ||||
| -rw-r--r-- | sys/dev/mpt/mpilib/mpi_targ.h | 430 | ||||
| -rw-r--r-- | sys/dev/mpt/mpilib/mpi_type.h | 112 | ||||
| -rw-r--r-- | sys/dev/mpt/mpt.c | 1189 | ||||
| -rw-r--r-- | sys/dev/mpt/mpt.h | 179 | ||||
| -rw-r--r-- | sys/dev/mpt/mpt_debug.c | 608 | ||||
| -rw-r--r-- | sys/dev/mpt/mpt_freebsd.c | 1528 | ||||
| -rw-r--r-- | sys/dev/mpt/mpt_freebsd.h | 359 | ||||
| -rw-r--r-- | sys/dev/mpt/mpt_pci.c | 714 |
16 files changed, 9495 insertions, 0 deletions
diff --git a/sys/dev/mpt/mpilib/fc_log.h b/sys/dev/mpt/mpilib/fc_log.h new file mode 100644 index 0000000..2b02a9a --- /dev/null +++ b/sys/dev/mpt/mpilib/fc_log.h @@ -0,0 +1,110 @@ +/* $FreeBSD$ */ +/* + * Copyright (c) 2000, 2001 by LSI Logic Corporation + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice immediately at the beginning of the file, without modification, + * this list of conditions, and the following disclaimer. + * 2. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * NAME: fc_log.h + * SUMMARY: MPI IocLogInfo definitions for the SYMFC9xx chips + * DESCRIPTION: Contains the enumerated list of values that may be returned + * in the IOCLogInfo field of a MPI Default Reply Message. + * + * CREATION DATE: 6/02/2000 + * ID: $Id: fc_log.h,v 4.6 2001/07/26 14:41:33 sschremm Exp $ + */ + +/* + * MpiIocLogInfo_t enum + * + * These 32 bit values are used in the IOCLogInfo field of the MPI reply + * messages. + * The value is 0xabcccccc where + * a = The type of log info as per the MPI spec. Since these codes are + * all for Fibre Channel this value will always be 2. + * b = Specifies a subclass of the firmware where + * 0 = FCP Initiator + * 1 = FCP Target + * 2 = LAN + * 3 = MPI Message Layer + * 4 = FC Link + * 5 = Context Manager + * 6 = Invalid Field Offset + * 7 = State Change Info + * all others are reserved for future use + * c = A specific value within the subclass. + * + * NOTE: Any new values should be added to the end of each subclass so that the + * codes remain consistent across firmware releases. + */ +typedef enum _MpiIocLogInfoFc +{ + MPI_IOCLOGINFO_FC_INIT_BASE = 0x20000000, + MPI_IOCLOGINFO_FC_INIT_ERROR_OUT_OF_ORDER_FRAME = 0x20000001, /* received an out of order frame - unsupported */ + MPI_IOCLOGINFO_FC_INIT_ERROR_BAD_START_OF_FRAME = 0x20000002, /* Bad Rx Frame, bad start of frame primative */ + MPI_IOCLOGINFO_FC_INIT_ERROR_BAD_END_OF_FRAME = 0x20000003, /* Bad Rx Frame, bad end of frame primative */ + MPI_IOCLOGINFO_FC_INIT_ERROR_OVER_RUN = 0x20000004, /* Bad Rx Frame, overrun */ + MPI_IOCLOGINFO_FC_INIT_ERROR_RX_OTHER = 0x20000005, /* Other errors caught by IOC which require retries */ + MPI_IOCLOGINFO_FC_INIT_ERROR_SUBPROC_DEAD = 0x20000006, /* Main processor could not initialize sub-processor */ + MPI_IOCLOGINFO_FC_INIT_ERROR_RX_OVERRUN = 0x20000007, /* Scatter Gather overrun */ + MPI_IOCLOGINFO_FC_INIT_ERROR_RX_BAD_STATUS = 0x20000008, /* Receiver detected context mismatch via invalid header */ + MPI_IOCLOGINFO_FC_INIT_ERROR_RX_UNEXPECTED_FRAME= 0x20000009, /* CtxMgr detected unsupported frame type */ + MPI_IOCLOGINFO_FC_INIT_ERROR_LINK_FAILURE = 0x2000000A, /* Link failure occurred */ + MPI_IOCLOGINFO_FC_INIT_ERROR_TX_TIMEOUT = 0x2000000B, /* Transmitter timeout error */ + + MPI_IOCLOGINFO_FC_TARGET_BASE = 0x21000000, + MPI_IOCLOGINFO_FC_TARGET_NO_PDISC = 0x21000001, /* not sent because we are waiting for a PDISC from the initiator */ + MPI_IOCLOGINFO_FC_TARGET_NO_LOGIN = 0x21000002, /* not sent because we are not logged in to the remote node */ + MPI_IOCLOGINFO_FC_TARGET_DOAR_KILLED_BY_LIP = 0x21000003, /* Data Out, Auto Response, not sent due to a LIP */ + MPI_IOCLOGINFO_FC_TARGET_DIAR_KILLED_BY_LIP = 0x21000004, /* Data In, Auto Response, not sent due to a LIP */ + MPI_IOCLOGINFO_FC_TARGET_DIAR_MISSING_DATA = 0x21000005, /* Data In, Auto Response, missing data frames */ + MPI_IOCLOGINFO_FC_TARGET_DONR_KILLED_BY_LIP = 0x21000006, /* Data Out, No Response, not sent due to a LIP */ + MPI_IOCLOGINFO_FC_TARGET_WRSP_KILLED_BY_LIP = 0x21000007, /* Auto-response after a write not sent due to a LIP */ + MPI_IOCLOGINFO_FC_TARGET_DINR_KILLED_BY_LIP = 0x21000008, /* Data In, No Response, not completed due to a LIP */ + MPI_IOCLOGINFO_FC_TARGET_DINR_MISSING_DATA = 0x21000009, /* Data In, No Response, missing data frames */ + MPI_IOCLOGINFO_FC_TARGET_MRSP_KILLED_BY_LIP = 0x2100000a, /* Manual Response not sent due to a LIP */ + MPI_IOCLOGINFO_FC_TARGET_NO_CLASS_3 = 0x2100000b, /* not sent because remote node does not support Class 3 */ + MPI_IOCLOGINFO_FC_TARGET_LOGIN_NOT_VALID = 0x2100000c, /* not sent because login to remote node not validated */ + MPI_IOCLOGINFO_FC_TARGET_FROM_OUTBOUND = 0x2100000e, /* cleared from the outbound queue after a logout */ + MPI_IOCLOGINFO_FC_TARGET_WAITING_FOR_DATA_IN = 0x2100000f, /* cleared waiting for data after a logout */ + + MPI_IOCLOGINFO_FC_LAN_BASE = 0x22000000, + MPI_IOCLOGINFO_FC_LAN_TRANS_SGL_MISSING = 0x22000001, /* Transaction Context Sgl Missing */ + MPI_IOCLOGINFO_FC_LAN_TRANS_WRONG_PLACE = 0x22000002, /* Transaction Context found before an EOB */ + MPI_IOCLOGINFO_FC_LAN_TRANS_RES_BITS_SET = 0x22000003, /* Transaction Context value has reserved bits set */ + MPI_IOCLOGINFO_FC_LAN_WRONG_SGL_FLAG = 0x22000004, /* Invalid SGL Flags */ + + MPI_IOCLOGINFO_FC_MSG_BASE = 0x23000000, + + MPI_IOCLOGINFO_FC_LINK_BASE = 0x24000000, + MPI_IOCLOGINFO_FC_LINK_LOOP_INIT_TIMEOUT = 0x24000001, /* Loop initialization timed out */ + MPI_IOCLOGINFO_FC_LINK_ALREADY_INITIALIZED = 0x24000002, /* Another system controller already initialized the loop */ + MPI_IOCLOGINFO_FC_LINK_LINK_NOT_ESTABLISHED = 0x24000003, /* Not synchronized to signal or still negotiating (possible cable problem) */ + MPI_IOCLOGINFO_FC_LINK_CRC_ERROR = 0x24000004, /* CRC check detected error on received frame */ + + MPI_IOCLOGINFO_FC_CTX_BASE = 0x25000000, + + MPI_IOCLOGINFO_FC_INVALID_FIELD_BYTE_OFFSET = 0x26000000, /* The lower 24 bits give the byte offset of the field in the request message that is invalid */ + MPI_IOCLOGINFO_FC_INVALID_FIELD_MAX_OFFSET = 0x26ffffff, + + MPI_IOCLOGINFO_FC_STATE_CHANGE = 0x27000000 /* The lower 24 bits give additional information concerning state change */ + +} MpiIocLogInfoFc_t; diff --git a/sys/dev/mpt/mpilib/mpi.h b/sys/dev/mpt/mpilib/mpi.h new file mode 100644 index 0000000..a3fab3c --- /dev/null +++ b/sys/dev/mpt/mpilib/mpi.h @@ -0,0 +1,705 @@ +/* $FreeBSD$ */ +/* + * Copyright (c) 2000, 2001 by LSI Logic Corporation + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice immediately at the beginning of the file, without modification, + * this list of conditions, and the following disclaimer. + * 2. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * + * Name: MPI.H + * Title: MPI Message independent structures and definitions + * Creation Date: July 27, 2000 + * + * MPI.H Version: 01.02.09 + * + * Version History + * --------------- + * + * Date Version Description + * -------- -------- ------------------------------------------------------ + * 05-08-00 00.10.01 Original release for 0.10 spec dated 4/26/2000. + * 05-24-00 00.10.02 Added MPI_IOCSTATUS_SCSI_RESIDUAL_MISMATCH definition. + * 06-06-00 01.00.01 Update MPI_VERSION_MAJOR and MPI_VERSION_MINOR. + * 06-22-00 01.00.02 Added MPI_IOCSTATUS_LAN_ definitions. + * Removed LAN_SUSPEND function definition. + * Added MPI_MSGFLAGS_CONTINUATION_REPLY definition. + * 06-30-00 01.00.03 Added MPI_CONTEXT_REPLY_TYPE_LAN definition. + * Added MPI_GET/SET_CONTEXT_REPLY_TYPE macros. + * 07-27-00 01.00.04 Added MPI_FAULT_ definitions. + * Removed MPI_IOCSTATUS_MSG/DATA_XFER_ERROR definitions. + * Added MPI_IOCSTATUS_INTERNAL_ERROR definition. + * Added MPI_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH. + * 11-02-00 01.01.01 Original release for post 1.0 work. + * 12-04-00 01.01.02 Added new function codes. + * 01-09-01 01.01.03 Added more definitions to the system interface section + * Added MPI_IOCSTATUS_TARGET_STS_DATA_NOT_SENT. + * 01-25-01 01.01.04 Changed MPI_VERSION_MINOR from 0x00 to 0x01. + * 02-20-01 01.01.05 Started using MPI_POINTER. + * Fixed value for MPI_DIAG_RW_ENABLE. + * Added defines for MPI_DIAG_PREVENT_IOC_BOOT and + * MPI_DIAG_CLEAR_FLASH_BAD_SIG. + * Obsoleted MPI_IOCSTATUS_TARGET_FC_ defines. + * 02-27-01 01.01.06 Removed MPI_HOST_INDEX_REGISTER define. + * Added function codes for RAID. + * 04-09-01 01.01.07 Added alternate define for MPI_DOORBELL_ACTIVE, + * MPI_DOORBELL_USED, to better match the spec. + * 08-08-01 01.02.01 Original release for v1.2 work. + * Changed MPI_VERSION_MINOR from 0x01 to 0x02. + * Added define MPI_FUNCTION_TOOLBOX. + * 09-28-01 01.02.02 New function code MPI_SCSI_ENCLOSURE_PROCESSOR. + * 11-01-01 01.02.03 Changed name to MPI_FUNCTION_SCSI_ENCLOSURE_PROCESSOR. + * 03-14-02 01.02.04 Added MPI_HEADER_VERSION_ defines. + * 05-31-02 01.02.05 Bumped MPI_HEADER_VERSION_UNIT. + * 07-12-02 01.02.06 Added define for MPI_FUNCTION_MAILBOX. + * 09-16-02 01.02.07 Bumped value for MPI_HEADER_VERSION_UNIT. + * 11-15-02 01.02.08 Added define MPI_IOCSTATUS_TARGET_INVALID_IO_INDEX and + * obsoleted define MPI_IOCSTATUS_TARGET_INVALID_IOCINDEX. + * 04-01-03 01.02.09 New IOCStatus code: MPI_IOCSTATUS_FC_EXCHANGE_CANCELED + * -------------------------------------------------------------------------- + */ + +#ifndef MPI_H +#define MPI_H + + +/***************************************************************************** +* +* M P I V e r s i o n D e f i n i t i o n s +* +*****************************************************************************/ + +#define MPI_VERSION_MAJOR (0x01) +#define MPI_VERSION_MINOR (0x02) +#define MPI_VERSION_MAJOR_MASK (0xFF00) +#define MPI_VERSION_MAJOR_SHIFT (8) +#define MPI_VERSION_MINOR_MASK (0x00FF) +#define MPI_VERSION_MINOR_SHIFT (0) +#define MPI_VERSION ((MPI_VERSION_MAJOR << MPI_VERSION_MAJOR_SHIFT) | \ + MPI_VERSION_MINOR) + +#define MPI_VERSION_01_00 (0x0100) +#define MPI_VERSION_01_01 (0x0101) +#define MPI_VERSION_01_02 (0x0102) +/* Note: The major versions of 0xe0 through 0xff are reserved */ + +/* versioning for this MPI header set */ +#define MPI_HEADER_VERSION_UNIT (0x09) +#define MPI_HEADER_VERSION_DEV (0x00) +#define MPI_HEADER_VERSION_UNIT_MASK (0xFF00) +#define MPI_HEADER_VERSION_UNIT_SHIFT (8) +#define MPI_HEADER_VERSION_DEV_MASK (0x00FF) +#define MPI_HEADER_VERSION_DEV_SHIFT (0) +#define MPI_HEADER_VERSION ((MPI_HEADER_VERSION_UNIT << 8) | MPI_HEADER_VERSION_DEV) + +/***************************************************************************** +* +* I O C S t a t e D e f i n i t i o n s +* +*****************************************************************************/ + +#define MPI_IOC_STATE_RESET (0x00000000) +#define MPI_IOC_STATE_READY (0x10000000) +#define MPI_IOC_STATE_OPERATIONAL (0x20000000) +#define MPI_IOC_STATE_FAULT (0x40000000) + +#define MPI_IOC_STATE_MASK (0xF0000000) +#define MPI_IOC_STATE_SHIFT (28) + +/* Fault state codes (product independent range 0x8000-0xFFFF) */ + +#define MPI_FAULT_REQUEST_MESSAGE_PCI_PARITY_ERROR (0x8111) +#define MPI_FAULT_REQUEST_MESSAGE_PCI_BUS_FAULT (0x8112) +#define MPI_FAULT_REPLY_MESSAGE_PCI_PARITY_ERROR (0x8113) +#define MPI_FAULT_REPLY_MESSAGE_PCI_BUS_FAULT (0x8114) +#define MPI_FAULT_DATA_SEND_PCI_PARITY_ERROR (0x8115) +#define MPI_FAULT_DATA_SEND_PCI_BUS_FAULT (0x8116) +#define MPI_FAULT_DATA_RECEIVE_PCI_PARITY_ERROR (0x8117) +#define MPI_FAULT_DATA_RECEIVE_PCI_BUS_FAULT (0x8118) + + +/***************************************************************************** +* +* P C I S y s t e m I n t e r f a c e R e g i s t e r s +* +*****************************************************************************/ + +/* S y s t e m D o o r b e l l */ +#define MPI_DOORBELL_OFFSET (0x00000000) +#define MPI_DOORBELL_ACTIVE (0x08000000) /* DoorbellUsed */ +#define MPI_DOORBELL_USED (MPI_DOORBELL_ACTIVE) +#define MPI_DOORBELL_ACTIVE_SHIFT (27) +#define MPI_DOORBELL_WHO_INIT_MASK (0x07000000) +#define MPI_DOORBELL_WHO_INIT_SHIFT (24) +#define MPI_DOORBELL_FUNCTION_MASK (0xFF000000) +#define MPI_DOORBELL_FUNCTION_SHIFT (24) +#define MPI_DOORBELL_ADD_DWORDS_MASK (0x00FF0000) +#define MPI_DOORBELL_ADD_DWORDS_SHIFT (16) +#define MPI_DOORBELL_DATA_MASK (0x0000FFFF) + + +#define MPI_WRITE_SEQUENCE_OFFSET (0x00000004) +#define MPI_WRSEQ_KEY_VALUE_MASK (0x0000000F) +#define MPI_WRSEQ_1ST_KEY_VALUE (0x04) +#define MPI_WRSEQ_2ND_KEY_VALUE (0x0B) +#define MPI_WRSEQ_3RD_KEY_VALUE (0x02) +#define MPI_WRSEQ_4TH_KEY_VALUE (0x07) +#define MPI_WRSEQ_5TH_KEY_VALUE (0x0D) + +#define MPI_DIAGNOSTIC_OFFSET (0x00000008) +#define MPI_DIAG_CLEAR_FLASH_BAD_SIG (0x00000400) +#define MPI_DIAG_PREVENT_IOC_BOOT (0x00000200) +#define MPI_DIAG_DRWE (0x00000080) +#define MPI_DIAG_FLASH_BAD_SIG (0x00000040) +#define MPI_DIAG_RESET_HISTORY (0x00000020) +#define MPI_DIAG_RW_ENABLE (0x00000010) +#define MPI_DIAG_RESET_ADAPTER (0x00000004) +#define MPI_DIAG_DISABLE_ARM (0x00000002) +#define MPI_DIAG_MEM_ENABLE (0x00000001) + +#define MPI_TEST_BASE_ADDRESS_OFFSET (0x0000000C) + +#define MPI_DIAG_RW_DATA_OFFSET (0x00000010) + +#define MPI_DIAG_RW_ADDRESS_OFFSET (0x00000014) + +#define MPI_HOST_INTERRUPT_STATUS_OFFSET (0x00000030) +#define MPI_HIS_IOP_DOORBELL_STATUS (0x80000000) +#define MPI_HIS_REPLY_MESSAGE_INTERRUPT (0x00000008) +#define MPI_HIS_DOORBELL_INTERRUPT (0x00000001) + +#define MPI_HOST_INTERRUPT_MASK_OFFSET (0x00000034) +#define MPI_HIM_RIM (0x00000008) +#define MPI_HIM_DIM (0x00000001) + +#define MPI_REQUEST_QUEUE_OFFSET (0x00000040) +#define MPI_REQUEST_POST_FIFO_OFFSET (0x00000040) + +#define MPI_REPLY_QUEUE_OFFSET (0x00000044) +#define MPI_REPLY_POST_FIFO_OFFSET (0x00000044) +#define MPI_REPLY_FREE_FIFO_OFFSET (0x00000044) + + + +/***************************************************************************** +* +* M e s s a g e F r a m e D e s c r i p t o r s +* +*****************************************************************************/ + +#define MPI_REQ_MF_DESCRIPTOR_NB_MASK (0x00000003) +#define MPI_REQ_MF_DESCRIPTOR_F_BIT (0x00000004) +#define MPI_REQ_MF_DESCRIPTOR_ADDRESS_MASK (0xFFFFFFF8) + +#define MPI_ADDRESS_REPLY_A_BIT (0x80000000) +#define MPI_ADDRESS_REPLY_ADDRESS_MASK (0x7FFFFFFF) + +#define MPI_CONTEXT_REPLY_A_BIT (0x80000000) +#define MPI_CONTEXT_REPLY_TYPE_MASK (0x60000000) +#define MPI_CONTEXT_REPLY_TYPE_SCSI_INIT (0x00) +#define MPI_CONTEXT_REPLY_TYPE_SCSI_TARGET (0x01) +#define MPI_CONTEXT_REPLY_TYPE_LAN (0x02) +#define MPI_CONTEXT_REPLY_TYPE_SHIFT (29) +#define MPI_CONTEXT_REPLY_CONTEXT_MASK (0x1FFFFFFF) + + +/****************************************************************************/ +/* Context Reply macros */ +/****************************************************************************/ + +#define MPI_GET_CONTEXT_REPLY_TYPE(x) (((x) & MPI_CONTEXT_REPLY_TYPE_MASK) \ + >> MPI_CONTEXT_REPLY_TYPE_SHIFT) + +#define MPI_SET_CONTEXT_REPLY_TYPE(x, typ) \ + ((x) = ((x) & ~MPI_CONTEXT_REPLY_TYPE_MASK) | \ + (((typ) << MPI_CONTEXT_REPLY_TYPE_SHIFT) & \ + MPI_CONTEXT_REPLY_TYPE_MASK)) + + +/***************************************************************************** +* +* M e s s a g e F u n c t i o n s +* 0x80 -> 0x8F reserved for private message use per product +* +* +*****************************************************************************/ + +#define MPI_FUNCTION_SCSI_IO_REQUEST (0x00) +#define MPI_FUNCTION_SCSI_TASK_MGMT (0x01) +#define MPI_FUNCTION_IOC_INIT (0x02) +#define MPI_FUNCTION_IOC_FACTS (0x03) +#define MPI_FUNCTION_CONFIG (0x04) +#define MPI_FUNCTION_PORT_FACTS (0x05) +#define MPI_FUNCTION_PORT_ENABLE (0x06) +#define MPI_FUNCTION_EVENT_NOTIFICATION (0x07) +#define MPI_FUNCTION_EVENT_ACK (0x08) +#define MPI_FUNCTION_FW_DOWNLOAD (0x09) +#define MPI_FUNCTION_TARGET_CMD_BUFFER_POST (0x0A) +#define MPI_FUNCTION_TARGET_ASSIST (0x0B) +#define MPI_FUNCTION_TARGET_STATUS_SEND (0x0C) +#define MPI_FUNCTION_TARGET_MODE_ABORT (0x0D) +#define MPI_FUNCTION_TARGET_FC_BUF_POST_LINK_SRVC (0x0E) /* obsolete name */ +#define MPI_FUNCTION_TARGET_FC_RSP_LINK_SRVC (0x0F) /* obsolete name */ +#define MPI_FUNCTION_TARGET_FC_EX_SEND_LINK_SRVC (0x10) /* obsolete name */ +#define MPI_FUNCTION_TARGET_FC_ABORT (0x11) /* obsolete name */ +#define MPI_FUNCTION_FC_LINK_SRVC_BUF_POST (0x0E) +#define MPI_FUNCTION_FC_LINK_SRVC_RSP (0x0F) +#define MPI_FUNCTION_FC_EX_LINK_SRVC_SEND (0x10) +#define MPI_FUNCTION_FC_ABORT (0x11) +#define MPI_FUNCTION_FW_UPLOAD (0x12) +#define MPI_FUNCTION_FC_COMMON_TRANSPORT_SEND (0x13) +#define MPI_FUNCTION_FC_PRIMITIVE_SEND (0x14) + +#define MPI_FUNCTION_RAID_ACTION (0x15) +#define MPI_FUNCTION_RAID_SCSI_IO_PASSTHROUGH (0x16) + +#define MPI_FUNCTION_TOOLBOX (0x17) + +#define MPI_FUNCTION_SCSI_ENCLOSURE_PROCESSOR (0x18) + +#define MPI_FUNCTION_MAILBOX (0x19) + +#define MPI_FUNCTION_LAN_SEND (0x20) +#define MPI_FUNCTION_LAN_RECEIVE (0x21) +#define MPI_FUNCTION_LAN_RESET (0x22) + +#define MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET (0x40) +#define MPI_FUNCTION_IO_UNIT_RESET (0x41) +#define MPI_FUNCTION_HANDSHAKE (0x42) +#define MPI_FUNCTION_REPLY_FRAME_REMOVAL (0x43) + + + +/***************************************************************************** +* +* S c a t t e r G a t h e r E l e m e n t s +* +*****************************************************************************/ + +/****************************************************************************/ +/* Simple element structures */ +/****************************************************************************/ + +typedef struct _SGE_SIMPLE32 +{ + U32 FlagsLength; + U32 Address; +} SGE_SIMPLE32, MPI_POINTER PTR_SGE_SIMPLE32, + SGESimple32_t, MPI_POINTER pSGESimple32_t; + +typedef struct _SGE_SIMPLE64 +{ + U32 FlagsLength; + U64 Address; +} SGE_SIMPLE64, MPI_POINTER PTR_SGE_SIMPLE64, + SGESimple64_t, MPI_POINTER pSGESimple64_t; + +typedef struct _SGE_SIMPLE_UNION +{ + U32 FlagsLength; + union + { + U32 Address32; + U64 Address64; + } _u; +} SGESimpleUnion_t, MPI_POINTER pSGESimpleUnion_t, + SGE_SIMPLE_UNION, MPI_POINTER PTR_SGE_SIMPLE_UNION; + +/****************************************************************************/ +/* Chain element structures */ +/****************************************************************************/ + +typedef struct _SGE_CHAIN32 +{ + U16 Length; + U8 NextChainOffset; + U8 Flags; + U32 Address; +} SGE_CHAIN32, MPI_POINTER PTR_SGE_CHAIN32, + SGEChain32_t, MPI_POINTER pSGEChain32_t; + +typedef struct _SGE_CHAIN64 +{ + U16 Length; + U8 NextChainOffset; + U8 Flags; + U64 Address; +} SGE_CHAIN64, MPI_POINTER PTR_SGE_CHAIN64, + SGEChain64_t, MPI_POINTER pSGEChain64_t; + +typedef struct _SGE_CHAIN_UNION +{ + U16 Length; + U8 NextChainOffset; + U8 Flags; + union + { + U32 Address32; + U64 Address64; + } _u; +} SGE_CHAIN_UNION, MPI_POINTER PTR_SGE_CHAIN_UNION, + SGEChainUnion_t, MPI_POINTER pSGEChainUnion_t; + +/****************************************************************************/ +/* Transaction Context element */ +/****************************************************************************/ + +typedef struct _SGE_TRANSACTION32 +{ + U8 Reserved; + U8 ContextSize; + U8 DetailsLength; + U8 Flags; + U32 TransactionContext[1]; + U32 TransactionDetails[1]; +} SGE_TRANSACTION32, MPI_POINTER PTR_SGE_TRANSACTION32, + SGETransaction32_t, MPI_POINTER pSGETransaction32_t; + +typedef struct _SGE_TRANSACTION64 +{ + U8 Reserved; + U8 ContextSize; + U8 DetailsLength; + U8 Flags; + U32 TransactionContext[2]; + U32 TransactionDetails[1]; +} SGE_TRANSACTION64, MPI_POINTER PTR_SGE_TRANSACTION64, + SGETransaction64_t, MPI_POINTER pSGETransaction64_t; + +typedef struct _SGE_TRANSACTION96 +{ + U8 Reserved; + U8 ContextSize; + U8 DetailsLength; + U8 Flags; + U32 TransactionContext[3]; + U32 TransactionDetails[1]; +} SGE_TRANSACTION96, MPI_POINTER PTR_SGE_TRANSACTION96, + SGETransaction96_t, MPI_POINTER pSGETransaction96_t; + +typedef struct _SGE_TRANSACTION128 +{ + U8 Reserved; + U8 ContextSize; + U8 DetailsLength; + U8 Flags; + U32 TransactionContext[4]; + U32 TransactionDetails[1]; +} SGE_TRANSACTION128, MPI_POINTER PTR_SGE_TRANSACTION128, + SGETransaction_t128, MPI_POINTER pSGETransaction_t128; + +typedef struct _SGE_TRANSACTION_UNION +{ + U8 Reserved; + U8 ContextSize; + U8 DetailsLength; + U8 Flags; + union + { + U32 TransactionContext32[1]; + U32 TransactionContext64[2]; + U32 TransactionContext96[3]; + U32 TransactionContext128[4]; + } _u; + U32 TransactionDetails[1]; +} SGE_TRANSACTION_UNION, MPI_POINTER PTR_SGE_TRANSACTION_UNION, + SGETransactionUnion_t, MPI_POINTER pSGETransactionUnion_t; + + +/****************************************************************************/ +/* SGE IO types union for IO SGL's */ +/****************************************************************************/ + +typedef struct _SGE_IO_UNION +{ + union + { + SGE_SIMPLE_UNION Simple; + SGE_CHAIN_UNION Chain; + } _u; +} SGE_IO_UNION, MPI_POINTER PTR_SGE_IO_UNION, + SGEIOUnion_t, MPI_POINTER pSGEIOUnion_t; + +/****************************************************************************/ +/* SGE union for SGL's with Simple and Transaction elements */ +/****************************************************************************/ + +typedef struct _SGE_TRANS_SIMPLE_UNION +{ + union + { + SGE_SIMPLE_UNION Simple; + SGE_TRANSACTION_UNION Transaction; + } _u; +} SGE_TRANS_SIMPLE_UNION, MPI_POINTER PTR_SGE_TRANS_SIMPLE_UNION, + SGETransSimpleUnion_t, MPI_POINTER pSGETransSimpleUnion_t; + +/****************************************************************************/ +/* All SGE types union */ +/****************************************************************************/ + +typedef struct _SGE_MPI_UNION +{ + union + { + SGE_SIMPLE_UNION Simple; + SGE_CHAIN_UNION Chain; + SGE_TRANSACTION_UNION Transaction; + } _u; +} SGE_MPI_UNION, MPI_POINTER PTR_SGE_MPI_UNION, + MPI_SGE_UNION_t, MPI_POINTER pMPI_SGE_UNION_t, + SGEAllUnion_t, MPI_POINTER pSGEAllUnion_t; + + +/****************************************************************************/ +/* SGE field definition and masks */ +/****************************************************************************/ + +/* Flags field bit definitions */ + +#define MPI_SGE_FLAGS_LAST_ELEMENT (0x80) +#define MPI_SGE_FLAGS_END_OF_BUFFER (0x40) +#define MPI_SGE_FLAGS_ELEMENT_TYPE_MASK (0x30) +#define MPI_SGE_FLAGS_LOCAL_ADDRESS (0x08) +#define MPI_SGE_FLAGS_DIRECTION (0x04) +#define MPI_SGE_FLAGS_ADDRESS_SIZE (0x02) +#define MPI_SGE_FLAGS_END_OF_LIST (0x01) + +#define MPI_SGE_FLAGS_SHIFT (24) + +#define MPI_SGE_LENGTH_MASK (0x00FFFFFF) +#define MPI_SGE_CHAIN_LENGTH_MASK (0x0000FFFF) + +/* Element Type */ + +#define MPI_SGE_FLAGS_TRANSACTION_ELEMENT (0x00) +#define MPI_SGE_FLAGS_SIMPLE_ELEMENT (0x10) +#define MPI_SGE_FLAGS_CHAIN_ELEMENT (0x30) +#define MPI_SGE_FLAGS_ELEMENT_MASK (0x30) + +/* Address location */ + +#define MPI_SGE_FLAGS_SYSTEM_ADDRESS (0x00) + +/* Direction */ + +#define MPI_SGE_FLAGS_IOC_TO_HOST (0x00) +#define MPI_SGE_FLAGS_HOST_TO_IOC (0x04) + +/* Address Size */ + +#define MPI_SGE_FLAGS_32_BIT_ADDRESSING (0x00) +#define MPI_SGE_FLAGS_64_BIT_ADDRESSING (0x02) + +/* Context Size */ + +#define MPI_SGE_FLAGS_32_BIT_CONTEXT (0x00) +#define MPI_SGE_FLAGS_64_BIT_CONTEXT (0x02) +#define MPI_SGE_FLAGS_96_BIT_CONTEXT (0x04) +#define MPI_SGE_FLAGS_128_BIT_CONTEXT (0x06) + +#define MPI_SGE_CHAIN_OFFSET_MASK (0x00FF0000) +#define MPI_SGE_CHAIN_OFFSET_SHIFT (16) + + +/****************************************************************************/ +/* SGE operation Macros */ +/****************************************************************************/ + + /* SIMPLE FlagsLength manipulations... */ +#define MPI_SGE_SET_FLAGS(f) ((U32)(f) << MPI_SGE_FLAGS_SHIFT) +#define MPI_SGE_GET_FLAGS(fl) (((fl) & ~MPI_SGE_LENGTH_MASK) >> MPI_SGE_FLAGS_SHIFT) +#define MPI_SGE_LENGTH(fl) ((fl) & MPI_SGE_LENGTH_MASK) +#define MPI_SGE_CHAIN_LENGTH(fl) ((fl) & MPI_SGE_CHAIN_LENGTH_MASK) + +#define MPI_SGE_SET_FLAGS_LENGTH(f,l) (MPI_SGE_SET_FLAGS(f) | MPI_SGE_LENGTH(l)) + +#define MPI_pSGE_GET_FLAGS(psg) MPI_SGE_GET_FLAGS((psg)->FlagsLength) +#define MPI_pSGE_GET_LENGTH(psg) MPI_SGE_LENGTH((psg)->FlagsLength) +#define MPI_pSGE_SET_FLAGS_LENGTH(psg,f,l) (psg)->FlagsLength = MPI_SGE_SET_FLAGS_LENGTH(f,l) + /* CAUTION - The following are READ-MODIFY-WRITE! */ +#define MPI_pSGE_SET_FLAGS(psg,f) (psg)->FlagsLength |= MPI_SGE_SET_FLAGS(f) +#define MPI_pSGE_SET_LENGTH(psg,l) (psg)->FlagsLength |= MPI_SGE_LENGTH(l) + +#define MPI_GET_CHAIN_OFFSET(x) ((x&MPI_SGE_CHAIN_OFFSET_MASK)>>MPI_SGE_CHAIN_OFFSET_SHIFT) + + + +/***************************************************************************** +* +* S t a n d a r d M e s s a g e S t r u c t u r e s +* +*****************************************************************************/ + +/****************************************************************************/ +/* Standard message request header for all request messages */ +/****************************************************************************/ + +typedef struct _MSG_REQUEST_HEADER +{ + U8 Reserved[2]; /* function specific */ + U8 ChainOffset; + U8 Function; + U8 Reserved1[3]; /* function specific */ + U8 MsgFlags; + U32 MsgContext; +} MSG_REQUEST_HEADER, MPI_POINTER PTR_MSG_REQUEST_HEADER, + MPIHeader_t, MPI_POINTER pMPIHeader_t; + + +/****************************************************************************/ +/* Default Reply */ +/****************************************************************************/ + +typedef struct _MSG_DEFAULT_REPLY +{ + U8 Reserved[2]; /* function specific */ + U8 MsgLength; + U8 Function; + U8 Reserved1[3]; /* function specific */ + U8 MsgFlags; + U32 MsgContext; + U8 Reserved2[2]; /* function specific */ + U16 IOCStatus; + U32 IOCLogInfo; +} MSG_DEFAULT_REPLY, MPI_POINTER PTR_MSG_DEFAULT_REPLY, + MPIDefaultReply_t, MPI_POINTER pMPIDefaultReply_t; + + +/* MsgFlags definition for all replies */ + +#define MPI_MSGFLAGS_CONTINUATION_REPLY (0x80) + + +/***************************************************************************** +* +* I O C S t a t u s V a l u e s +* +*****************************************************************************/ + +/****************************************************************************/ +/* Common IOCStatus values for all replies */ +/****************************************************************************/ + +#define MPI_IOCSTATUS_SUCCESS (0x0000) +#define MPI_IOCSTATUS_INVALID_FUNCTION (0x0001) +#define MPI_IOCSTATUS_BUSY (0x0002) +#define MPI_IOCSTATUS_INVALID_SGL (0x0003) +#define MPI_IOCSTATUS_INTERNAL_ERROR (0x0004) +#define MPI_IOCSTATUS_RESERVED (0x0005) +#define MPI_IOCSTATUS_INSUFFICIENT_RESOURCES (0x0006) +#define MPI_IOCSTATUS_INVALID_FIELD (0x0007) +#define MPI_IOCSTATUS_INVALID_STATE (0x0008) + +/****************************************************************************/ +/* Config IOCStatus values */ +/****************************************************************************/ + +#define MPI_IOCSTATUS_CONFIG_INVALID_ACTION (0x0020) +#define MPI_IOCSTATUS_CONFIG_INVALID_TYPE (0x0021) +#define MPI_IOCSTATUS_CONFIG_INVALID_PAGE (0x0022) +#define MPI_IOCSTATUS_CONFIG_INVALID_DATA (0x0023) +#define MPI_IOCSTATUS_CONFIG_NO_DEFAULTS (0x0024) +#define MPI_IOCSTATUS_CONFIG_CANT_COMMIT (0x0025) + +/****************************************************************************/ +/* SCSIIO Reply (SPI & FCP) initiator values */ +/****************************************************************************/ + +#define MPI_IOCSTATUS_SCSI_RECOVERED_ERROR (0x0040) +#define MPI_IOCSTATUS_SCSI_INVALID_BUS (0x0041) +#define MPI_IOCSTATUS_SCSI_INVALID_TARGETID (0x0042) +#define MPI_IOCSTATUS_SCSI_DEVICE_NOT_THERE (0x0043) +#define MPI_IOCSTATUS_SCSI_DATA_OVERRUN (0x0044) +#define MPI_IOCSTATUS_SCSI_DATA_UNDERRUN (0x0045) +#define MPI_IOCSTATUS_SCSI_IO_DATA_ERROR (0x0046) +#define MPI_IOCSTATUS_SCSI_PROTOCOL_ERROR (0x0047) +#define MPI_IOCSTATUS_SCSI_TASK_TERMINATED (0x0048) +#define MPI_IOCSTATUS_SCSI_RESIDUAL_MISMATCH (0x0049) +#define MPI_IOCSTATUS_SCSI_TASK_MGMT_FAILED (0x004A) +#define MPI_IOCSTATUS_SCSI_IOC_TERMINATED (0x004B) +#define MPI_IOCSTATUS_SCSI_EXT_TERMINATED (0x004C) + +/****************************************************************************/ +/* SCSI (SPI & FCP) target values */ +/****************************************************************************/ + +#define MPI_IOCSTATUS_TARGET_PRIORITY_IO (0x0060) +#define MPI_IOCSTATUS_TARGET_INVALID_PORT (0x0061) +#define MPI_IOCSTATUS_TARGET_INVALID_IOCINDEX (0x0062) /* obsolete */ +#define MPI_IOCSTATUS_TARGET_INVALID_IO_INDEX (0x0062) +#define MPI_IOCSTATUS_TARGET_ABORTED (0x0063) +#define MPI_IOCSTATUS_TARGET_NO_CONN_RETRYABLE (0x0064) +#define MPI_IOCSTATUS_TARGET_NO_CONNECTION (0x0065) +#define MPI_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH (0x006A) +#define MPI_IOCSTATUS_TARGET_STS_DATA_NOT_SENT (0x006B) + +/****************************************************************************/ +/* Additional FCP target values */ +/****************************************************************************/ + +#define MPI_IOCSTATUS_TARGET_FC_ABORTED (0x0066) /* obsolete */ +#define MPI_IOCSTATUS_TARGET_FC_RX_ID_INVALID (0x0067) /* obsolete */ +#define MPI_IOCSTATUS_TARGET_FC_DID_INVALID (0x0068) /* obsolete */ +#define MPI_IOCSTATUS_TARGET_FC_NODE_LOGGED_OUT (0x0069) /* obsolete */ + +/****************************************************************************/ +/* Fibre Channel Direct Access values */ +/****************************************************************************/ + +#define MPI_IOCSTATUS_FC_ABORTED (0x0066) +#define MPI_IOCSTATUS_FC_RX_ID_INVALID (0x0067) +#define MPI_IOCSTATUS_FC_DID_INVALID (0x0068) +#define MPI_IOCSTATUS_FC_NODE_LOGGED_OUT (0x0069) +#define MPI_IOCSTATUS_FC_EXCHANGE_CANCELED (0x006C) + +/****************************************************************************/ +/* LAN values */ +/****************************************************************************/ + +#define MPI_IOCSTATUS_LAN_DEVICE_NOT_FOUND (0x0080) +#define MPI_IOCSTATUS_LAN_DEVICE_FAILURE (0x0081) +#define MPI_IOCSTATUS_LAN_TRANSMIT_ERROR (0x0082) +#define MPI_IOCSTATUS_LAN_TRANSMIT_ABORTED (0x0083) +#define MPI_IOCSTATUS_LAN_RECEIVE_ERROR (0x0084) +#define MPI_IOCSTATUS_LAN_RECEIVE_ABORTED (0x0085) +#define MPI_IOCSTATUS_LAN_PARTIAL_PACKET (0x0086) +#define MPI_IOCSTATUS_LAN_CANCELED (0x0087) + + +/****************************************************************************/ +/* IOCStatus flag to indicate that log info is available */ +/****************************************************************************/ + +#define MPI_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE (0x8000) +#define MPI_IOCSTATUS_MASK (0x7FFF) + +/****************************************************************************/ +/* LogInfo Types */ +/****************************************************************************/ + +#define MPI_IOCLOGINFO_TYPE_MASK (0xF0000000) +#define MPI_IOCLOGINFO_TYPE_NONE (0x0) +#define MPI_IOCLOGINFO_TYPE_SCSI (0x1) +#define MPI_IOCLOGINFO_TYPE_FC (0x2) +#define MPI_IOCLOGINFO_LOG_DATA_MASK (0x0FFFFFFF) + + +#endif diff --git a/sys/dev/mpt/mpilib/mpi_cnfg.h b/sys/dev/mpt/mpilib/mpi_cnfg.h new file mode 100644 index 0000000..6008f42 --- /dev/null +++ b/sys/dev/mpt/mpilib/mpi_cnfg.h @@ -0,0 +1,1623 @@ +/* $FreeBSD$ */ +/* + * Copyright (c) 2000, 2001 by LSI Logic Corporation + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice immediately at the beginning of the file, without modification, + * this list of conditions, and the following disclaimer. + * 2. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * + * Name: MPI_CNFG.H + * Title: MPI Config message, structures, and Pages + * Creation Date: July 27, 2000 + * + * MPI_CNFG.H Version: 01.02.11 + * + * Version History + * --------------- + * + * Date Version Description + * -------- -------- ------------------------------------------------------ + * 05-08-00 00.10.01 Original release for 0.10 spec dated 4/26/2000. + * 06-06-00 01.00.01 Update version number for 1.0 release. + * 06-08-00 01.00.02 Added _PAGEVERSION definitions for all pages. + * Added FcPhLowestVersion, FcPhHighestVersion, Reserved2 + * fields to FC_DEVICE_0 page, updated the page version. + * Changed _FREE_RUNNING_CLOCK to _PACING_TRANSFERS in + * SCSI_PORT_0, SCSI_DEVICE_0 and SCSI_DEVICE_1 pages + * and updated the page versions. + * Added _RESPONSE_ID_MASK definition to SCSI_PORT_1 + * page and updated the page version. + * Added Information field and _INFO_PARAMS_NEGOTIATED + * definitionto SCSI_DEVICE_0 page. + * 06-22-00 01.00.03 Removed batch controls from LAN_0 page and updated the + * page version. + * Added BucketsRemaining to LAN_1 page, redefined the + * state values, and updated the page version. + * Revised bus width definitions in SCSI_PORT_0, + * SCSI_DEVICE_0 and SCSI_DEVICE_1 pages. + * 06-30-00 01.00.04 Added MaxReplySize to LAN_1 page and updated the page + * version. + * Moved FC_DEVICE_0 PageAddress description to spec. + * 07-27-00 01.00.05 Corrected the SubsystemVendorID and SubsystemID field + * widths in IOC_0 page and updated the page version. + * 11-02-00 01.01.01 Original release for post 1.0 work + * Added Manufacturing pages, IO Unit Page 2, SCSI SPI + * Port Page 2, FC Port Page 4, FC Port Page 5 + * 11-15-00 01.01.02 Interim changes to match proposals + * 12-04-00 01.01.03 Config page changes to match MPI rev 1.00.01. + * 12-05-00 01.01.04 Modified config page actions. + * 01-09-01 01.01.05 Added defines for page address formats. + * Data size for Manufacturing pages 2 and 3 no longer + * defined here. + * Io Unit Page 2 size is fixed at 4 adapters and some + * flags were changed. + * SCSI Port Page 2 Device Settings modified. + * New fields added to FC Port Page 0 and some flags + * cleaned up. + * Removed impedance flash from FC Port Page 1. + * Added FC Port pages 6 and 7. + * 01-25-01 01.01.06 Added MaxInitiators field to FcPortPage0. + * 01-29-01 01.01.07 Changed some defines to make them 32 character unique. + * Added some LinkType defines for FcPortPage0. + * 02-20-01 01.01.08 Started using MPI_POINTER. + * 02-27-01 01.01.09 Replaced MPI_CONFIG_PAGETYPE_SCSI_LUN with + * MPI_CONFIG_PAGETYPE_RAID_VOLUME. + * Added definitions and structures for IOC Page 2 and + * RAID Volume Page 2. + * 03-27-01 01.01.10 Added CONFIG_PAGE_FC_PORT_8 and CONFIG_PAGE_FC_PORT_9. + * CONFIG_PAGE_FC_PORT_3 now supports persistent by DID. + * Added VendorId and ProductRevLevel fields to + * RAIDVOL2_IM_PHYS_ID struct. + * Modified values for MPI_FCPORTPAGE0_FLAGS_ATTACH_ + * defines to make them compatible to MPI version 1.0. + * Added structure offset comments. + * 04-09-01 01.01.11 Added some new defines for the PageAddress field and + * removed some obsolete ones. + * Added IO Unit Page 3. + * Modified defines for Scsi Port Page 2. + * Modified RAID Volume Pages. + * 08-08-01 01.02.01 Original release for v1.2 work. + * Added SepID and SepBus to RVP2 IMPhysicalDisk struct. + * Added defines for the SEP bits in RVP2 VolumeSettings. + * Modified the DeviceSettings field in RVP2 to use the + * proper structure. + * Added defines for SES, SAF-TE, and cross channel for + * IOCPage2 CapabilitiesFlags. + * Removed define for MPI_IOUNITPAGE2_FLAGS_RAID_DISABLE. + * Removed define for + * MPI_SCSIPORTPAGE2_PORT_FLAGS_PARITY_ENABLE. + * Added define for MPI_CONFIG_PAGEATTR_RO_PERSISTENT. + * 08-29-01 01.02.02 Fixed value for MPI_MANUFACTPAGE_DEVID_53C1035. + * Added defines for MPI_FCPORTPAGE1_FLAGS_HARD_ALPA_ONLY + * and MPI_FCPORTPAGE1_FLAGS_IMMEDIATE_ERROR_REPLY. + * Removed MPI_SCSIPORTPAGE0_CAP_PACING_TRANSFERS, + * MPI_SCSIDEVPAGE0_NP_PACING_TRANSFERS, and + * MPI_SCSIDEVPAGE1_RP_PACING_TRANSFERS, and + * MPI_SCSIDEVPAGE1_CONF_PPR_ALLOWED. + * Added defines for MPI_SCSIDEVPAGE1_CONF_WDTR_DISALLOWED + * and MPI_SCSIDEVPAGE1_CONF_SDTR_DISALLOWED. + * Added OnBusTimerValue to CONFIG_PAGE_SCSI_PORT_1. + * Added rejected bits to SCSI Device Page 0 Information. + * Increased size of ALPA array in FC Port Page 2 by one + * and removed a one byte reserved field. + * 09-28-01 01.02.03 Swapped NegWireSpeedLow and NegWireSpeedLow in + * CONFIG_PAGE_LAN_1 to match preferred 64-bit ordering. + * Added structures for Manufacturing Page 4, IO Unit + * Page 3, IOC Page 3, IOC Page 4, RAID Volume Page 0, and + * RAID PhysDisk Page 0. + * 10-04-01 01.02.04 Added define for MPI_CONFIG_PAGETYPE_RAID_PHYSDISK. + * Modified some of the new defines to make them 32 + * character unique. + * Modified how variable length pages (arrays) are defined. + * Added generic defines for hot spare pools and RAID + * volume types. + * 11-01-01 01.02.05 Added define for MPI_IOUNITPAGE1_DISABLE_IR. + * 03-14-02 01.02.06 Added PCISlotNum field to CONFIG_PAGE_IOC_1 along with + * related define, and bumped the page version define. + * 05-31-02 01.02.07 Added a Flags field to CONFIG_PAGE_IOC_2_RAID_VOL in a + * reserved byte and added a define. + * Added define for + * MPI_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE. + * Added new config page: CONFIG_PAGE_IOC_5. + * Added MaxAliases, MaxHardAliases, and NumCurrentAliases + * fields to CONFIG_PAGE_FC_PORT_0. + * Added AltConnector and NumRequestedAliases fields to + * CONFIG_PAGE_FC_PORT_1. + * Added new config page: CONFIG_PAGE_FC_PORT_10. + * 07-12-02 01.02.08 Added more MPI_MANUFACTPAGE_DEVID_ defines. + * Added additional MPI_SCSIDEVPAGE0_NP_ defines. + * Added more MPI_SCSIDEVPAGE1_RP_ defines. + * Added define for + * MPI_SCSIDEVPAGE1_CONF_EXTENDED_PARAMS_ENABLE. + * Added new config page: CONFIG_PAGE_SCSI_DEVICE_3. + * Modified MPI_FCPORTPAGE5_FLAGS_ defines. + * 09-16-02 01.02.09 Added MPI_SCSIDEVPAGE1_CONF_FORCE_PPR_MSG define. + * 11-15-02 01.02.10 Added ConnectedID defines for CONFIG_PAGE_SCSI_PORT_0. + * Added more Flags defines for CONFIG_PAGE_FC_PORT_1. + * Added more Flags defines for CONFIG_PAGE_FC_DEVICE_0. + * 04-01-03 01.02.11 Added RR_TOV field and additional Flags defines for + * CONFIG_PAGE_FC_PORT_1. + * Added define MPI_FCPORTPAGE5_FLAGS_DISABLE to disable + * an alias. + * Added more device id defines. + * -------------------------------------------------------------------------- + */ + +#ifndef MPI_CNFG_H +#define MPI_CNFG_H + + +/***************************************************************************** +* +* C o n f i g M e s s a g e a n d S t r u c t u r e s +* +*****************************************************************************/ + +typedef struct _CONFIG_PAGE_HEADER +{ + U8 PageVersion; /* 00h */ + U8 PageLength; /* 01h */ + U8 PageNumber; /* 02h */ + U8 PageType; /* 03h */ +} CONFIG_PAGE_HEADER, MPI_POINTER PTR_CONFIG_PAGE_HEADER, + ConfigPageHeader_t, MPI_POINTER pConfigPageHeader_t; + +typedef union _CONFIG_PAGE_HEADER_UNION +{ + ConfigPageHeader_t Struct; + U8 Bytes[4]; + U16 Word16[2]; + U32 Word32; +} ConfigPageHeaderUnion, MPI_POINTER pConfigPageHeaderUnion, + CONFIG_PAGE_HEADER_UNION, MPI_POINTER PTR_CONFIG_PAGE_HEADER_UNION; + + +/**************************************************************************** +* PageType field values +****************************************************************************/ +#define MPI_CONFIG_PAGEATTR_READ_ONLY (0x00) +#define MPI_CONFIG_PAGEATTR_CHANGEABLE (0x10) +#define MPI_CONFIG_PAGEATTR_PERSISTENT (0x20) +#define MPI_CONFIG_PAGEATTR_RO_PERSISTENT (0x30) +#define MPI_CONFIG_PAGEATTR_MASK (0xF0) + +#define MPI_CONFIG_PAGETYPE_IO_UNIT (0x00) +#define MPI_CONFIG_PAGETYPE_IOC (0x01) +#define MPI_CONFIG_PAGETYPE_BIOS (0x02) +#define MPI_CONFIG_PAGETYPE_SCSI_PORT (0x03) +#define MPI_CONFIG_PAGETYPE_SCSI_DEVICE (0x04) +#define MPI_CONFIG_PAGETYPE_FC_PORT (0x05) +#define MPI_CONFIG_PAGETYPE_FC_DEVICE (0x06) +#define MPI_CONFIG_PAGETYPE_LAN (0x07) +#define MPI_CONFIG_PAGETYPE_RAID_VOLUME (0x08) +#define MPI_CONFIG_PAGETYPE_MANUFACTURING (0x09) +#define MPI_CONFIG_PAGETYPE_RAID_PHYSDISK (0x0A) +#define MPI_CONFIG_PAGETYPE_MASK (0x0F) + +#define MPI_CONFIG_TYPENUM_MASK (0x0FFF) + + +/**************************************************************************** +* PageAddress field values +****************************************************************************/ +#define MPI_SCSI_PORT_PGAD_PORT_MASK (0x000000FF) + +#define MPI_SCSI_DEVICE_TARGET_ID_MASK (0x000000FF) +#define MPI_SCSI_DEVICE_TARGET_ID_SHIFT (0) +#define MPI_SCSI_DEVICE_BUS_MASK (0x0000FF00) +#define MPI_SCSI_DEVICE_BUS_SHIFT (8) + +#define MPI_FC_PORT_PGAD_PORT_MASK (0xF0000000) +#define MPI_FC_PORT_PGAD_PORT_SHIFT (28) +#define MPI_FC_PORT_PGAD_FORM_MASK (0x0F000000) +#define MPI_FC_PORT_PGAD_FORM_INDEX (0x01000000) +#define MPI_FC_PORT_PGAD_INDEX_MASK (0x0000FFFF) +#define MPI_FC_PORT_PGAD_INDEX_SHIFT (0) + +#define MPI_FC_DEVICE_PGAD_PORT_MASK (0xF0000000) +#define MPI_FC_DEVICE_PGAD_PORT_SHIFT (28) +#define MPI_FC_DEVICE_PGAD_FORM_MASK (0x0F000000) +#define MPI_FC_DEVICE_PGAD_FORM_NEXT_DID (0x00000000) +#define MPI_FC_DEVICE_PGAD_ND_PORT_MASK (0xF0000000) +#define MPI_FC_DEVICE_PGAD_ND_PORT_SHIFT (28) +#define MPI_FC_DEVICE_PGAD_ND_DID_MASK (0x00FFFFFF) +#define MPI_FC_DEVICE_PGAD_ND_DID_SHIFT (0) +#define MPI_FC_DEVICE_PGAD_FORM_BUS_TID (0x01000000) +#define MPI_FC_DEVICE_PGAD_BT_BUS_MASK (0x0000FF00) +#define MPI_FC_DEVICE_PGAD_BT_BUS_SHIFT (8) +#define MPI_FC_DEVICE_PGAD_BT_TID_MASK (0x000000FF) +#define MPI_FC_DEVICE_PGAD_BT_TID_SHIFT (0) + +#define MPI_PHYSDISK_PGAD_PHYSDISKNUM_MASK (0x000000FF) +#define MPI_PHYSDISK_PGAD_PHYSDISKNUM_SHIFT (0) + + + +/**************************************************************************** +* Config Request Message +****************************************************************************/ +typedef struct _MSG_CONFIG +{ + U8 Action; /* 00h */ + U8 Reserved; /* 01h */ + U8 ChainOffset; /* 02h */ + U8 Function; /* 03h */ + U8 Reserved1[3]; /* 04h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ + U8 Reserved2[8]; /* 0Ch */ + CONFIG_PAGE_HEADER Header; /* 14h */ + U32 PageAddress; /* 18h */ + SGE_IO_UNION PageBufferSGE; /* 1Ch */ +} MSG_CONFIG, MPI_POINTER PTR_MSG_CONFIG, + Config_t, MPI_POINTER pConfig_t; + + +/**************************************************************************** +* Action field values +****************************************************************************/ +#define MPI_CONFIG_ACTION_PAGE_HEADER (0x00) +#define MPI_CONFIG_ACTION_PAGE_READ_CURRENT (0x01) +#define MPI_CONFIG_ACTION_PAGE_WRITE_CURRENT (0x02) +#define MPI_CONFIG_ACTION_PAGE_DEFAULT (0x03) +#define MPI_CONFIG_ACTION_PAGE_WRITE_NVRAM (0x04) +#define MPI_CONFIG_ACTION_PAGE_READ_DEFAULT (0x05) +#define MPI_CONFIG_ACTION_PAGE_READ_NVRAM (0x06) + + +/* Config Reply Message */ +typedef struct _MSG_CONFIG_REPLY +{ + U8 Action; /* 00h */ + U8 Reserved; /* 01h */ + U8 MsgLength; /* 02h */ + U8 Function; /* 03h */ + U8 Reserved1[3]; /* 04h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ + U8 Reserved2[2]; /* 0Ch */ + U16 IOCStatus; /* 0Eh */ + U32 IOCLogInfo; /* 10h */ + CONFIG_PAGE_HEADER Header; /* 14h */ +} MSG_CONFIG_REPLY, MPI_POINTER PTR_MSG_CONFIG_REPLY, + ConfigReply_t, MPI_POINTER pConfigReply_t; + + + +/***************************************************************************** +* +* C o n f i g u r a t i o n P a g e s +* +*****************************************************************************/ + +/**************************************************************************** +* Manufacturing Config pages +****************************************************************************/ +#define MPI_MANUFACTPAGE_VENDORID_LSILOGIC (0x1000) +#define MPI_MANUFACTPAGE_VENDORID_TREBIA (0x1783) + +#define MPI_MANUFACTPAGE_DEVICEID_FC909 (0x0621) +#define MPI_MANUFACTPAGE_DEVICEID_FC919 (0x0624) +#define MPI_MANUFACTPAGE_DEVICEID_FC929 (0x0622) +#define MPI_MANUFACTPAGE_DEVICEID_FC919X (0x0628) +#define MPI_MANUFACTPAGE_DEVICEID_FC929X (0x0626) + +#define MPI_MANUFACTPAGE_DEVID_53C1030 (0x0030) +#define MPI_MANUFACTPAGE_DEVID_53C1030ZC (0x0031) +#define MPI_MANUFACTPAGE_DEVID_1030_53C1035 (0x0032) +#define MPI_MANUFACTPAGE_DEVID_1030ZC_53C1035 (0x0033) +#define MPI_MANUFACTPAGE_DEVID_53C1035 (0x0040) +#define MPI_MANUFACTPAGE_DEVID_53C1035ZC (0x0041) + +#define MPI_MANUFACTPAGE_DEVID_SA2010 (0x0804) +#define MPI_MANUFACTPAGE_DEVID_SA2010ZC (0x0805) +#define MPI_MANUFACTPAGE_DEVID_SA2020 (0x0806) +#define MPI_MANUFACTPAGE_DEVID_SA2020ZC (0x0807) + +#define MPI_MANUFACTPAGE_DEVID_SNP1000 (0x0010) +#define MPI_MANUFACTPAGE_DEVID_SNP500 (0x0020) + + + +typedef struct _CONFIG_PAGE_MANUFACTURING_0 +{ + CONFIG_PAGE_HEADER Header; /* 00h */ + U8 ChipName[16]; /* 04h */ + U8 ChipRevision[8]; /* 14h */ + U8 BoardName[16]; /* 1Ch */ + U8 BoardAssembly[16]; /* 2Ch */ + U8 BoardTracerNumber[16]; /* 3Ch */ + +} CONFIG_PAGE_MANUFACTURING_0, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_0, + ManufacturingPage0_t, MPI_POINTER pManufacturingPage0_t; + +#define MPI_MANUFACTURING0_PAGEVERSION (0x00) + + +typedef struct _CONFIG_PAGE_MANUFACTURING_1 +{ + CONFIG_PAGE_HEADER Header; /* 00h */ + U8 VPD[256]; /* 04h */ +} CONFIG_PAGE_MANUFACTURING_1, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_1, + ManufacturingPage1_t, MPI_POINTER pManufacturingPage1_t; + +#define MPI_MANUFACTURING1_PAGEVERSION (0x00) + + +typedef struct _MPI_CHIP_REVISION_ID +{ + U16 DeviceID; /* 00h */ + U8 PCIRevisionID; /* 02h */ + U8 Reserved; /* 03h */ +} MPI_CHIP_REVISION_ID, MPI_POINTER PTR_MPI_CHIP_REVISION_ID, + MpiChipRevisionId_t, MPI_POINTER pMpiChipRevisionId_t; + + +/* + * Host code (drivers, BIOS, utilities, etc.) should leave this define set to + * one and check Header.PageLength at runtime. + */ +#ifndef MPI_MAN_PAGE_2_HW_SETTINGS_WORDS +#define MPI_MAN_PAGE_2_HW_SETTINGS_WORDS (1) +#endif + +typedef struct _CONFIG_PAGE_MANUFACTURING_2 +{ + CONFIG_PAGE_HEADER Header; /* 00h */ + MPI_CHIP_REVISION_ID ChipId; /* 04h */ + U32 HwSettings[MPI_MAN_PAGE_2_HW_SETTINGS_WORDS];/* 08h */ +} CONFIG_PAGE_MANUFACTURING_2, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_2, + ManufacturingPage2_t, MPI_POINTER pManufacturingPage2_t; + +#define MPI_MANUFACTURING2_PAGEVERSION (0x00) + + +/* + * Host code (drivers, BIOS, utilities, etc.) should leave this define set to + * one and check Header.PageLength at runtime. + */ +#ifndef MPI_MAN_PAGE_3_INFO_WORDS +#define MPI_MAN_PAGE_3_INFO_WORDS (1) +#endif + +typedef struct _CONFIG_PAGE_MANUFACTURING_3 +{ + CONFIG_PAGE_HEADER Header; /* 00h */ + MPI_CHIP_REVISION_ID ChipId; /* 04h */ + U32 Info[MPI_MAN_PAGE_3_INFO_WORDS];/* 08h */ +} CONFIG_PAGE_MANUFACTURING_3, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_3, + ManufacturingPage3_t, MPI_POINTER pManufacturingPage3_t; + +#define MPI_MANUFACTURING3_PAGEVERSION (0x00) + + +typedef struct _CONFIG_PAGE_MANUFACTURING_4 +{ + CONFIG_PAGE_HEADER Header; /* 00h */ + U32 Reserved1; /* 04h */ + U8 InfoOffset0; /* 08h */ + U8 InfoSize0; /* 09h */ + U8 InfoOffset1; /* 0Ah */ + U8 InfoSize1; /* 0Bh */ + U8 InquirySize; /* 0Ch */ + U8 Reserved2; /* 0Dh */ + U16 Reserved3; /* 0Eh */ + U8 InquiryData[56]; /* 10h */ + U32 ISVolumeSettings; /* 48h */ + U32 IMEVolumeSettings; /* 4Ch */ + U32 IMVolumeSettings; /* 50h */ +} CONFIG_PAGE_MANUFACTURING_4, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_4, + ManufacturingPage4_t, MPI_POINTER pManufacturingPage4_t; + +#define MPI_MANUFACTURING4_PAGEVERSION (0x00) + + +/**************************************************************************** +* IO Unit Config Pages +****************************************************************************/ + +typedef struct _CONFIG_PAGE_IO_UNIT_0 +{ + CONFIG_PAGE_HEADER Header; /* 00h */ + U64 UniqueValue; /* 04h */ +} CONFIG_PAGE_IO_UNIT_0, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_0, + IOUnitPage0_t, MPI_POINTER pIOUnitPage0_t; + +#define MPI_IOUNITPAGE0_PAGEVERSION (0x00) + + +typedef struct _CONFIG_PAGE_IO_UNIT_1 +{ + CONFIG_PAGE_HEADER Header; /* 00h */ + U32 Flags; /* 04h */ +} CONFIG_PAGE_IO_UNIT_1, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_1, + IOUnitPage1_t, MPI_POINTER pIOUnitPage1_t; + +#define MPI_IOUNITPAGE1_PAGEVERSION (0x00) + +/* IO Unit Page 1 Flags defines */ + +#define MPI_IOUNITPAGE1_MULTI_FUNCTION (0x00000000) +#define MPI_IOUNITPAGE1_SINGLE_FUNCTION (0x00000001) +#define MPI_IOUNITPAGE1_MULTI_PATHING (0x00000002) +#define MPI_IOUNITPAGE1_SINGLE_PATHING (0x00000000) +#define MPI_IOUNITPAGE1_DISABLE_IR (0x00000040) +#define MPI_IOUNITPAGE1_FORCE_32 (0x00000080) + + +typedef struct _MPI_ADAPTER_INFO +{ + U8 PciBusNumber; /* 00h */ + U8 PciDeviceAndFunctionNumber; /* 01h */ + U16 AdapterFlags; /* 02h */ +} MPI_ADAPTER_INFO, MPI_POINTER PTR_MPI_ADAPTER_INFO, + MpiAdapterInfo_t, MPI_POINTER pMpiAdapterInfo_t; + +#define MPI_ADAPTER_INFO_FLAGS_EMBEDDED (0x0001) +#define MPI_ADAPTER_INFO_FLAGS_INIT_STATUS (0x0002) + +typedef struct _CONFIG_PAGE_IO_UNIT_2 +{ + CONFIG_PAGE_HEADER Header; /* 00h */ + U32 Flags; /* 04h */ + U32 BiosVersion; /* 08h */ + MPI_ADAPTER_INFO AdapterOrder[4]; /* 0Ch */ +} CONFIG_PAGE_IO_UNIT_2, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_2, + IOUnitPage2_t, MPI_POINTER pIOUnitPage2_t; + +#define MPI_IOUNITPAGE2_PAGEVERSION (0x00) + +#define MPI_IOUNITPAGE2_FLAGS_PAUSE_ON_ERROR (0x00000002) +#define MPI_IOUNITPAGE2_FLAGS_VERBOSE_ENABLE (0x00000004) +#define MPI_IOUNITPAGE2_FLAGS_COLOR_VIDEO_DISABLE (0x00000008) +#define MPI_IOUNITPAGE2_FLAGS_DONT_HOOK_INT_40 (0x00000010) + + +/* + * Host code (drivers, BIOS, utilities, etc.) should leave this define set to + * one and check Header.PageLength at runtime. + */ +#ifndef MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX +#define MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX (1) +#endif + +typedef struct _CONFIG_PAGE_IO_UNIT_3 +{ + CONFIG_PAGE_HEADER Header; /* 00h */ + U8 GPIOCount; /* 04h */ + U8 Reserved1; /* 05h */ + U16 Reserved2; /* 06h */ + U16 GPIOVal[MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX]; /* 08h */ +} CONFIG_PAGE_IO_UNIT_3, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_3, + IOUnitPage3_t, MPI_POINTER pIOUnitPage3_t; + +#define MPI_IOUNITPAGE3_PAGEVERSION (0x01) + +#define MPI_IOUNITPAGE3_GPIO_FUNCTION_MASK (0xFC) +#define MPI_IOUNITPAGE3_GPIO_FUNCTION_SHIFT (2) +#define MPI_IOUNITPAGE3_GPIO_SETTING_OFF (0x00) +#define MPI_IOUNITPAGE3_GPIO_SETTING_ON (0x01) + + +/**************************************************************************** +* IOC Config Pages +****************************************************************************/ + +typedef struct _CONFIG_PAGE_IOC_0 +{ + CONFIG_PAGE_HEADER Header; /* 00h */ + U32 TotalNVStore; /* 04h */ + U32 FreeNVStore; /* 08h */ + U16 VendorID; /* 0Ch */ + U16 DeviceID; /* 0Eh */ + U8 RevisionID; /* 10h */ + U8 Reserved[3]; /* 11h */ + U32 ClassCode; /* 14h */ + U16 SubsystemVendorID; /* 18h */ + U16 SubsystemID; /* 1Ah */ +} CONFIG_PAGE_IOC_0, MPI_POINTER PTR_CONFIG_PAGE_IOC_0, + IOCPage0_t, MPI_POINTER pIOCPage0_t; + +#define MPI_IOCPAGE0_PAGEVERSION (0x01) + + +typedef struct _CONFIG_PAGE_IOC_1 +{ + CONFIG_PAGE_HEADER Header; /* 00h */ + U32 Flags; /* 04h */ + U32 CoalescingTimeout; /* 08h */ + U8 CoalescingDepth; /* 0Ch */ + U8 PCISlotNum; /* 0Dh */ + U8 Reserved[2]; /* 0Eh */ +} CONFIG_PAGE_IOC_1, MPI_POINTER PTR_CONFIG_PAGE_IOC_1, + IOCPage1_t, MPI_POINTER pIOCPage1_t; + +#define MPI_IOCPAGE1_PAGEVERSION (0x01) + +#define MPI_IOCPAGE1_REPLY_COALESCING (0x00000001) + +#define MPI_IOCPAGE1_PCISLOTNUM_UNKNOWN (0xFF) + + +typedef struct _CONFIG_PAGE_IOC_2_RAID_VOL +{ + U8 VolumeID; /* 00h */ + U8 VolumeBus; /* 01h */ + U8 VolumeIOC; /* 02h */ + U8 VolumePageNumber; /* 03h */ + U8 VolumeType; /* 04h */ + U8 Flags; /* 05h */ + U16 Reserved3; /* 06h */ +} CONFIG_PAGE_IOC_2_RAID_VOL, MPI_POINTER PTR_CONFIG_PAGE_IOC_2_RAID_VOL, + ConfigPageIoc2RaidVol_t, MPI_POINTER pConfigPageIoc2RaidVol_t; + +/* IOC Page 2 Volume RAID Type values, also used in RAID Volume pages */ + +#define MPI_RAID_VOL_TYPE_IS (0x00) +#define MPI_RAID_VOL_TYPE_IME (0x01) +#define MPI_RAID_VOL_TYPE_IM (0x02) + +/* IOC Page 2 Volume Flags values */ + +#define MPI_IOCPAGE2_FLAG_VOLUME_INACTIVE (0x08) + +/* + * Host code (drivers, BIOS, utilities, etc.) should leave this define set to + * one and check Header.PageLength at runtime. + */ +#ifndef MPI_IOC_PAGE_2_RAID_VOLUME_MAX +#define MPI_IOC_PAGE_2_RAID_VOLUME_MAX (1) +#endif + +typedef struct _CONFIG_PAGE_IOC_2 +{ + CONFIG_PAGE_HEADER Header; /* 00h */ + U32 CapabilitiesFlags; /* 04h */ + U8 NumActiveVolumes; /* 08h */ + U8 MaxVolumes; /* 09h */ + U8 NumActivePhysDisks; /* 0Ah */ + U8 MaxPhysDisks; /* 0Bh */ + CONFIG_PAGE_IOC_2_RAID_VOL RaidVolume[MPI_IOC_PAGE_2_RAID_VOLUME_MAX];/* 0Ch */ +} CONFIG_PAGE_IOC_2, MPI_POINTER PTR_CONFIG_PAGE_IOC_2, + IOCPage2_t, MPI_POINTER pIOCPage2_t; + +#define MPI_IOCPAGE2_PAGEVERSION (0x02) + +/* IOC Page 2 Capabilities flags */ + +#define MPI_IOCPAGE2_CAP_FLAGS_IS_SUPPORT (0x00000001) +#define MPI_IOCPAGE2_CAP_FLAGS_IME_SUPPORT (0x00000002) +#define MPI_IOCPAGE2_CAP_FLAGS_IM_SUPPORT (0x00000004) +#define MPI_IOCPAGE2_CAP_FLAGS_SES_SUPPORT (0x20000000) +#define MPI_IOCPAGE2_CAP_FLAGS_SAFTE_SUPPORT (0x40000000) +#define MPI_IOCPAGE2_CAP_FLAGS_CROSS_CHANNEL_SUPPORT (0x80000000) + + +typedef struct _IOC_3_PHYS_DISK +{ + U8 PhysDiskID; /* 00h */ + U8 PhysDiskBus; /* 01h */ + U8 PhysDiskIOC; /* 02h */ + U8 PhysDiskNum; /* 03h */ +} IOC_3_PHYS_DISK, MPI_POINTER PTR_IOC_3_PHYS_DISK, + Ioc3PhysDisk_t, MPI_POINTER pIoc3PhysDisk_t; + +/* + * Host code (drivers, BIOS, utilities, etc.) should leave this define set to + * one and check Header.PageLength at runtime. + */ +#ifndef MPI_IOC_PAGE_3_PHYSDISK_MAX +#define MPI_IOC_PAGE_3_PHYSDISK_MAX (1) +#endif + +typedef struct _CONFIG_PAGE_IOC_3 +{ + CONFIG_PAGE_HEADER Header; /* 00h */ + U8 NumPhysDisks; /* 04h */ + U8 Reserved1; /* 05h */ + U16 Reserved2; /* 06h */ + IOC_3_PHYS_DISK PhysDisk[MPI_IOC_PAGE_3_PHYSDISK_MAX]; /* 08h */ +} CONFIG_PAGE_IOC_3, MPI_POINTER PTR_CONFIG_PAGE_IOC_3, + IOCPage3_t, MPI_POINTER pIOCPage3_t; + +#define MPI_IOCPAGE3_PAGEVERSION (0x00) + + +typedef struct _IOC_4_SEP +{ + U8 SEPTargetID; /* 00h */ + U8 SEPBus; /* 01h */ + U16 Reserved; /* 02h */ +} IOC_4_SEP, MPI_POINTER PTR_IOC_4_SEP, + Ioc4Sep_t, MPI_POINTER pIoc4Sep_t; + +/* + * Host code (drivers, BIOS, utilities, etc.) should leave this define set to + * one and check Header.PageLength at runtime. + */ +#ifndef MPI_IOC_PAGE_4_SEP_MAX +#define MPI_IOC_PAGE_4_SEP_MAX (1) +#endif + +typedef struct _CONFIG_PAGE_IOC_4 +{ + CONFIG_PAGE_HEADER Header; /* 00h */ + U8 ActiveSEP; /* 04h */ + U8 MaxSEP; /* 05h */ + U16 Reserved1; /* 06h */ + IOC_4_SEP SEP[MPI_IOC_PAGE_4_SEP_MAX]; /* 08h */ +} CONFIG_PAGE_IOC_4, MPI_POINTER PTR_CONFIG_PAGE_IOC_4, + IOCPage4_t, MPI_POINTER pIOCPage4_t; + +#define MPI_IOCPAGE4_PAGEVERSION (0x00) + + +typedef struct _IOC_5_HOT_SPARE +{ + U8 PhysDiskNum; /* 00h */ + U8 Reserved; /* 01h */ + U8 HotSparePool; /* 02h */ + U8 Flags; /* 03h */ +} IOC_5_HOT_SPARE, MPI_POINTER PTR_IOC_5_HOT_SPARE, + Ioc5HotSpare_t, MPI_POINTER pIoc5HotSpare_t; + +/* IOC Page 5 HotSpare Flags */ +#define MPI_IOC_PAGE_5_HOT_SPARE_ACTIVE (0x01) + +/* + * Host code (drivers, BIOS, utilities, etc.) should leave this define set to + * one and check Header.PageLength at runtime. + */ +#ifndef MPI_IOC_PAGE_5_HOT_SPARE_MAX +#define MPI_IOC_PAGE_5_HOT_SPARE_MAX (1) +#endif + +typedef struct _CONFIG_PAGE_IOC_5 +{ + CONFIG_PAGE_HEADER Header; /* 00h */ + U32 Reserved1; /* 04h */ + U8 NumHotSpares; /* 08h */ + U8 Reserved2; /* 09h */ + U16 Reserved3; /* 0Ah */ + IOC_5_HOT_SPARE HotSpare[MPI_IOC_PAGE_5_HOT_SPARE_MAX]; /* 0Ch */ +} CONFIG_PAGE_IOC_5, MPI_POINTER PTR_CONFIG_PAGE_IOC_5, + IOCPage5_t, MPI_POINTER pIOCPage5_t; + +#define MPI_IOCPAGE5_PAGEVERSION (0x00) + + + +/**************************************************************************** +* SCSI Port Config Pages +****************************************************************************/ + +typedef struct _CONFIG_PAGE_SCSI_PORT_0 +{ + CONFIG_PAGE_HEADER Header; /* 00h */ + U32 Capabilities; /* 04h */ + U32 PhysicalInterface; /* 08h */ +} CONFIG_PAGE_SCSI_PORT_0, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_0, + SCSIPortPage0_t, MPI_POINTER pSCSIPortPage0_t; + +#define MPI_SCSIPORTPAGE0_PAGEVERSION (0x01) + +#define MPI_SCSIPORTPAGE0_CAP_IU (0x00000001) +#define MPI_SCSIPORTPAGE0_CAP_DT (0x00000002) +#define MPI_SCSIPORTPAGE0_CAP_QAS (0x00000004) +#define MPI_SCSIPORTPAGE0_CAP_MIN_SYNC_PERIOD_MASK (0x0000FF00) +#define MPI_SCSIPORTPAGE0_CAP_MAX_SYNC_OFFSET_MASK (0x00FF0000) +#define MPI_SCSIPORTPAGE0_CAP_WIDE (0x20000000) +#define MPI_SCSIPORTPAGE0_CAP_AIP (0x80000000) + +#define MPI_SCSIPORTPAGE0_PHY_SIGNAL_TYPE_MASK (0x00000003) +#define MPI_SCSIPORTPAGE0_PHY_SIGNAL_HVD (0x01) +#define MPI_SCSIPORTPAGE0_PHY_SIGNAL_SE (0x02) +#define MPI_SCSIPORTPAGE0_PHY_SIGNAL_LVD (0x03) +#define MPI_SCSIPORTPAGE0_PHY_MASK_CONNECTED_ID (0xFF000000) +#define MPI_SCSIPORTPAGE0_PHY_SHIFT_CONNECTED_ID (24) +#define MPI_SCSIPORTPAGE0_PHY_BUS_FREE_CONNECTED_ID (0xFE) +#define MPI_SCSIPORTPAGE0_PHY_UNKNOWN_CONNECTED_ID (0xFF) + + +typedef struct _CONFIG_PAGE_SCSI_PORT_1 +{ + CONFIG_PAGE_HEADER Header; /* 00h */ + U32 Configuration; /* 04h */ + U32 OnBusTimerValue; /* 08h */ +} CONFIG_PAGE_SCSI_PORT_1, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_1, + SCSIPortPage1_t, MPI_POINTER pSCSIPortPage1_t; + +#define MPI_SCSIPORTPAGE1_PAGEVERSION (0x02) + +#define MPI_SCSIPORTPAGE1_CFG_PORT_SCSI_ID_MASK (0x000000FF) +#define MPI_SCSIPORTPAGE1_CFG_PORT_RESPONSE_ID_MASK (0xFFFF0000) + + +typedef struct _MPI_DEVICE_INFO +{ + U8 Timeout; /* 00h */ + U8 SyncFactor; /* 01h */ + U16 DeviceFlags; /* 02h */ +} MPI_DEVICE_INFO, MPI_POINTER PTR_MPI_DEVICE_INFO, + MpiDeviceInfo_t, MPI_POINTER pMpiDeviceInfo_t; + +typedef struct _CONFIG_PAGE_SCSI_PORT_2 +{ + CONFIG_PAGE_HEADER Header; /* 00h */ + U32 PortFlags; /* 04h */ + U32 PortSettings; /* 08h */ + MPI_DEVICE_INFO DeviceSettings[16]; /* 0Ch */ +} CONFIG_PAGE_SCSI_PORT_2, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_2, + SCSIPortPage2_t, MPI_POINTER pSCSIPortPage2_t; + +#define MPI_SCSIPORTPAGE2_PAGEVERSION (0x01) + +#define MPI_SCSIPORTPAGE2_PORT_FLAGS_SCAN_HIGH_TO_LOW (0x00000001) +#define MPI_SCSIPORTPAGE2_PORT_FLAGS_AVOID_SCSI_RESET (0x00000004) +#define MPI_SCSIPORTPAGE2_PORT_FLAGS_ALTERNATE_CHS (0x00000008) +#define MPI_SCSIPORTPAGE2_PORT_FLAGS_TERMINATION_DISABLE (0x00000010) + +#define MPI_SCSIPORTPAGE2_PORT_HOST_ID_MASK (0x0000000F) +#define MPI_SCSIPORTPAGE2_PORT_MASK_INIT_HBA (0x00000030) +#define MPI_SCSIPORTPAGE2_PORT_DISABLE_INIT_HBA (0x00000000) +#define MPI_SCSIPORTPAGE2_PORT_BIOS_INIT_HBA (0x00000010) +#define MPI_SCSIPORTPAGE2_PORT_OS_INIT_HBA (0x00000020) +#define MPI_SCSIPORTPAGE2_PORT_BIOS_OS_INIT_HBA (0x00000030) +#define MPI_SCSIPORTPAGE2_PORT_REMOVABLE_MEDIA (0x000000C0) +#define MPI_SCSIPORTPAGE2_PORT_SPINUP_DELAY_MASK (0x00000F00) +#define MPI_SCSIPORTPAGE2_PORT_MASK_NEGO_MASTER_SETTINGS (0x00003000) +#define MPI_SCSIPORTPAGE2_PORT_NEGO_MASTER_SETTINGS (0x00000000) +#define MPI_SCSIPORTPAGE2_PORT_NONE_MASTER_SETTINGS (0x00001000) +#define MPI_SCSIPORTPAGE2_PORT_ALL_MASTER_SETTINGS (0x00003000) + +#define MPI_SCSIPORTPAGE2_DEVICE_DISCONNECT_ENABLE (0x0001) +#define MPI_SCSIPORTPAGE2_DEVICE_ID_SCAN_ENABLE (0x0002) +#define MPI_SCSIPORTPAGE2_DEVICE_LUN_SCAN_ENABLE (0x0004) +#define MPI_SCSIPORTPAGE2_DEVICE_TAG_QUEUE_ENABLE (0x0008) +#define MPI_SCSIPORTPAGE2_DEVICE_WIDE_DISABLE (0x0010) +#define MPI_SCSIPORTPAGE2_DEVICE_BOOT_CHOICE (0x0020) + + +/**************************************************************************** +* SCSI Target Device Config Pages +****************************************************************************/ + +typedef struct _CONFIG_PAGE_SCSI_DEVICE_0 +{ + CONFIG_PAGE_HEADER Header; /* 00h */ + U32 NegotiatedParameters; /* 04h */ + U32 Information; /* 08h */ +} CONFIG_PAGE_SCSI_DEVICE_0, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_0, + SCSIDevicePage0_t, MPI_POINTER pSCSIDevicePage0_t; + +#define MPI_SCSIDEVPAGE0_PAGEVERSION (0x03) + +#define MPI_SCSIDEVPAGE0_NP_IU (0x00000001) +#define MPI_SCSIDEVPAGE0_NP_DT (0x00000002) +#define MPI_SCSIDEVPAGE0_NP_QAS (0x00000004) +#define MPI_SCSIDEVPAGE0_NP_HOLD_MCS (0x00000008) +#define MPI_SCSIDEVPAGE0_NP_WR_FLOW (0x00000010) +#define MPI_SCSIDEVPAGE0_NP_RD_STRM (0x00000020) +#define MPI_SCSIDEVPAGE0_NP_RTI (0x00000040) +#define MPI_SCSIDEVPAGE0_NP_PCOMP_EN (0x00000080) +#define MPI_SCSIDEVPAGE0_NP_NEG_SYNC_PERIOD_MASK (0x0000FF00) +#define MPI_SCSIDEVPAGE0_NP_NEG_SYNC_OFFSET_MASK (0x00FF0000) +#define MPI_SCSIDEVPAGE0_NP_WIDE (0x20000000) +#define MPI_SCSIDEVPAGE0_NP_AIP (0x80000000) + +#define MPI_SCSIDEVPAGE0_INFO_PARAMS_NEGOTIATED (0x00000001) +#define MPI_SCSIDEVPAGE0_INFO_SDTR_REJECTED (0x00000002) +#define MPI_SCSIDEVPAGE0_INFO_WDTR_REJECTED (0x00000004) +#define MPI_SCSIDEVPAGE0_INFO_PPR_REJECTED (0x00000008) + + +typedef struct _CONFIG_PAGE_SCSI_DEVICE_1 +{ + CONFIG_PAGE_HEADER Header; /* 00h */ + U32 RequestedParameters; /* 04h */ + U32 Reserved; /* 08h */ + U32 Configuration; /* 0Ch */ +} CONFIG_PAGE_SCSI_DEVICE_1, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_1, + SCSIDevicePage1_t, MPI_POINTER pSCSIDevicePage1_t; + +#define MPI_SCSIDEVPAGE1_PAGEVERSION (0x04) + +#define MPI_SCSIDEVPAGE1_RP_IU (0x00000001) +#define MPI_SCSIDEVPAGE1_RP_DT (0x00000002) +#define MPI_SCSIDEVPAGE1_RP_QAS (0x00000004) +#define MPI_SCSIDEVPAGE1_RP_HOLD_MCS (0x00000008) +#define MPI_SCSIDEVPAGE1_RP_WR_FLOW (0x00000010) +#define MPI_SCSIDEVPAGE1_RP_RD_STRM (0x00000020) +#define MPI_SCSIDEVPAGE1_RP_RTI (0x00000040) +#define MPI_SCSIDEVPAGE1_RP_PCOMP_EN (0x00000080) +#define MPI_SCSIDEVPAGE1_RP_MIN_SYNC_PERIOD_MASK (0x0000FF00) +#define MPI_SCSIDEVPAGE1_RP_MAX_SYNC_OFFSET_MASK (0x00FF0000) +#define MPI_SCSIDEVPAGE1_RP_WIDE (0x20000000) +#define MPI_SCSIDEVPAGE1_RP_AIP (0x80000000) + +#define MPI_SCSIDEVPAGE1_CONF_WDTR_DISALLOWED (0x00000002) +#define MPI_SCSIDEVPAGE1_CONF_SDTR_DISALLOWED (0x00000004) +#define MPI_SCSIDEVPAGE1_CONF_EXTENDED_PARAMS_ENABLE (0x00000008) +#define MPI_SCSIDEVPAGE1_CONF_FORCE_PPR_MSG (0x00000010) + + +typedef struct _CONFIG_PAGE_SCSI_DEVICE_2 +{ + CONFIG_PAGE_HEADER Header; /* 00h */ + U32 DomainValidation; /* 04h */ + U32 ParityPipeSelect; /* 08h */ + U32 DataPipeSelect; /* 0Ch */ +} CONFIG_PAGE_SCSI_DEVICE_2, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_2, + SCSIDevicePage2_t, MPI_POINTER pSCSIDevicePage2_t; + +#define MPI_SCSIDEVPAGE2_PAGEVERSION (0x01) + +#define MPI_SCSIDEVPAGE2_DV_ISI_ENABLE (0x00000010) +#define MPI_SCSIDEVPAGE2_DV_SECONDARY_DRIVER_ENABLE (0x00000020) +#define MPI_SCSIDEVPAGE2_DV_SLEW_RATE_CTRL (0x00000380) +#define MPI_SCSIDEVPAGE2_DV_PRIM_DRIVE_STR_CTRL (0x00001C00) +#define MPI_SCSIDEVPAGE2_DV_SECOND_DRIVE_STR_CTRL (0x0000E000) +#define MPI_SCSIDEVPAGE2_DV_XCLKH_ST (0x10000000) +#define MPI_SCSIDEVPAGE2_DV_XCLKS_ST (0x20000000) +#define MPI_SCSIDEVPAGE2_DV_XCLKH_DT (0x40000000) +#define MPI_SCSIDEVPAGE2_DV_XCLKS_DT (0x80000000) + +#define MPI_SCSIDEVPAGE2_PPS_PPS_MASK (0x00000003) + +#define MPI_SCSIDEVPAGE2_DPS_BIT_0_PL_SELECT_MASK (0x00000003) +#define MPI_SCSIDEVPAGE2_DPS_BIT_1_PL_SELECT_MASK (0x0000000C) +#define MPI_SCSIDEVPAGE2_DPS_BIT_2_PL_SELECT_MASK (0x00000030) +#define MPI_SCSIDEVPAGE2_DPS_BIT_3_PL_SELECT_MASK (0x000000C0) +#define MPI_SCSIDEVPAGE2_DPS_BIT_4_PL_SELECT_MASK (0x00000300) +#define MPI_SCSIDEVPAGE2_DPS_BIT_5_PL_SELECT_MASK (0x00000C00) +#define MPI_SCSIDEVPAGE2_DPS_BIT_6_PL_SELECT_MASK (0x00003000) +#define MPI_SCSIDEVPAGE2_DPS_BIT_7_PL_SELECT_MASK (0x0000C000) +#define MPI_SCSIDEVPAGE2_DPS_BIT_8_PL_SELECT_MASK (0x00030000) +#define MPI_SCSIDEVPAGE2_DPS_BIT_9_PL_SELECT_MASK (0x000C0000) +#define MPI_SCSIDEVPAGE2_DPS_BIT_10_PL_SELECT_MASK (0x00300000) +#define MPI_SCSIDEVPAGE2_DPS_BIT_11_PL_SELECT_MASK (0x00C00000) +#define MPI_SCSIDEVPAGE2_DPS_BIT_12_PL_SELECT_MASK (0x03000000) +#define MPI_SCSIDEVPAGE2_DPS_BIT_13_PL_SELECT_MASK (0x0C000000) +#define MPI_SCSIDEVPAGE2_DPS_BIT_14_PL_SELECT_MASK (0x30000000) +#define MPI_SCSIDEVPAGE2_DPS_BIT_15_PL_SELECT_MASK (0xC0000000) + + +typedef struct _CONFIG_PAGE_SCSI_DEVICE_3 +{ + CONFIG_PAGE_HEADER Header; /* 00h */ + U16 MsgRejectCount; /* 04h */ + U16 PhaseErrorCount; /* 06h */ + U16 ParityErrorCount; /* 08h */ + U16 Reserved; /* 0Ah */ +} CONFIG_PAGE_SCSI_DEVICE_3, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_3, + SCSIDevicePage3_t, MPI_POINTER pSCSIDevicePage3_t; + +#define MPI_SCSIDEVPAGE3_PAGEVERSION (0x00) + +#define MPI_SCSIDEVPAGE3_MAX_COUNTER (0xFFFE) +#define MPI_SCSIDEVPAGE3_UNSUPPORTED_COUNTER (0xFFFF) + + +/**************************************************************************** +* FC Port Config Pages +****************************************************************************/ + +typedef struct _CONFIG_PAGE_FC_PORT_0 +{ + CONFIG_PAGE_HEADER Header; /* 00h */ + U32 Flags; /* 04h */ + U8 MPIPortNumber; /* 08h */ + U8 LinkType; /* 09h */ + U8 PortState; /* 0Ah */ + U8 Reserved; /* 0Bh */ + U32 PortIdentifier; /* 0Ch */ + U64 WWNN; /* 10h */ + U64 WWPN; /* 18h */ + U32 SupportedServiceClass; /* 20h */ + U32 SupportedSpeeds; /* 24h */ + U32 CurrentSpeed; /* 28h */ + U32 MaxFrameSize; /* 2Ch */ + U64 FabricWWNN; /* 30h */ + U64 FabricWWPN; /* 38h */ + U32 DiscoveredPortsCount; /* 40h */ + U32 MaxInitiators; /* 44h */ + U8 MaxAliasesSupported; /* 48h */ + U8 MaxHardAliasesSupported; /* 49h */ + U8 NumCurrentAliases; /* 4Ah */ + U8 Reserved1; /* 4Bh */ +} CONFIG_PAGE_FC_PORT_0, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_0, + FCPortPage0_t, MPI_POINTER pFCPortPage0_t; + +#define MPI_FCPORTPAGE0_PAGEVERSION (0x02) + +#define MPI_FCPORTPAGE0_FLAGS_PROT_MASK (0x0000000F) +#define MPI_FCPORTPAGE0_FLAGS_PROT_FCP_INIT (MPI_PORTFACTS_PROTOCOL_INITIATOR) +#define MPI_FCPORTPAGE0_FLAGS_PROT_FCP_TARG (MPI_PORTFACTS_PROTOCOL_TARGET) +#define MPI_FCPORTPAGE0_FLAGS_PROT_LAN (MPI_PORTFACTS_PROTOCOL_LAN) +#define MPI_FCPORTPAGE0_FLAGS_PROT_LOGBUSADDR (MPI_PORTFACTS_PROTOCOL_LOGBUSADDR) + +#define MPI_FCPORTPAGE0_FLAGS_ALIAS_ALPA_SUPPORTED (0x00000010) +#define MPI_FCPORTPAGE0_FLAGS_ALIAS_WWN_SUPPORTED (0x00000020) +#define MPI_FCPORTPAGE0_FLAGS_FABRIC_WWN_VALID (0x00000040) + +#define MPI_FCPORTPAGE0_FLAGS_ATTACH_TYPE_MASK (0x00000F00) +#define MPI_FCPORTPAGE0_FLAGS_ATTACH_NO_INIT (0x00000000) +#define MPI_FCPORTPAGE0_FLAGS_ATTACH_POINT_TO_POINT (0x00000100) +#define MPI_FCPORTPAGE0_FLAGS_ATTACH_PRIVATE_LOOP (0x00000200) +#define MPI_FCPORTPAGE0_FLAGS_ATTACH_FABRIC_DIRECT (0x00000400) +#define MPI_FCPORTPAGE0_FLAGS_ATTACH_PUBLIC_LOOP (0x00000800) + +#define MPI_FCPORTPAGE0_LTYPE_RESERVED (0x00) +#define MPI_FCPORTPAGE0_LTYPE_OTHER (0x01) +#define MPI_FCPORTPAGE0_LTYPE_UNKNOWN (0x02) +#define MPI_FCPORTPAGE0_LTYPE_COPPER (0x03) +#define MPI_FCPORTPAGE0_LTYPE_SINGLE_1300 (0x04) +#define MPI_FCPORTPAGE0_LTYPE_SINGLE_1500 (0x05) +#define MPI_FCPORTPAGE0_LTYPE_50_LASER_MULTI (0x06) +#define MPI_FCPORTPAGE0_LTYPE_50_LED_MULTI (0x07) +#define MPI_FCPORTPAGE0_LTYPE_62_LASER_MULTI (0x08) +#define MPI_FCPORTPAGE0_LTYPE_62_LED_MULTI (0x09) +#define MPI_FCPORTPAGE0_LTYPE_MULTI_LONG_WAVE (0x0A) +#define MPI_FCPORTPAGE0_LTYPE_MULTI_SHORT_WAVE (0x0B) +#define MPI_FCPORTPAGE0_LTYPE_LASER_SHORT_WAVE (0x0C) +#define MPI_FCPORTPAGE0_LTYPE_LED_SHORT_WAVE (0x0D) +#define MPI_FCPORTPAGE0_LTYPE_1300_LONG_WAVE (0x0E) +#define MPI_FCPORTPAGE0_LTYPE_1500_LONG_WAVE (0x0F) + +#define MPI_FCPORTPAGE0_PORTSTATE_UNKNOWN (0x01) /*(SNIA)HBA_PORTSTATE_UNKNOWN 1 Unknown */ +#define MPI_FCPORTPAGE0_PORTSTATE_ONLINE (0x02) /*(SNIA)HBA_PORTSTATE_ONLINE 2 Operational */ +#define MPI_FCPORTPAGE0_PORTSTATE_OFFLINE (0x03) /*(SNIA)HBA_PORTSTATE_OFFLINE 3 User Offline */ +#define MPI_FCPORTPAGE0_PORTSTATE_BYPASSED (0x04) /*(SNIA)HBA_PORTSTATE_BYPASSED 4 Bypassed */ +#define MPI_FCPORTPAGE0_PORTSTATE_DIAGNOST (0x05) /*(SNIA)HBA_PORTSTATE_DIAGNOSTICS 5 In diagnostics mode */ +#define MPI_FCPORTPAGE0_PORTSTATE_LINKDOWN (0x06) /*(SNIA)HBA_PORTSTATE_LINKDOWN 6 Link Down */ +#define MPI_FCPORTPAGE0_PORTSTATE_ERROR (0x07) /*(SNIA)HBA_PORTSTATE_ERROR 7 Port Error */ +#define MPI_FCPORTPAGE0_PORTSTATE_LOOPBACK (0x08) /*(SNIA)HBA_PORTSTATE_LOOPBACK 8 Loopback */ + +#define MPI_FCPORTPAGE0_SUPPORT_CLASS_1 (0x00000001) +#define MPI_FCPORTPAGE0_SUPPORT_CLASS_2 (0x00000002) +#define MPI_FCPORTPAGE0_SUPPORT_CLASS_3 (0x00000004) + +#define MPI_FCPORTPAGE0_SUPPORT_1GBIT_SPEED (0x00000001) /* (SNIA)HBA_PORTSPEED_1GBIT 1 1 GBit/sec */ +#define MPI_FCPORTPAGE0_SUPPORT_2GBIT_SPEED (0x00000002) /* (SNIA)HBA_PORTSPEED_2GBIT 2 2 GBit/sec */ +#define MPI_FCPORTPAGE0_SUPPORT_10GBIT_SPEED (0x00000004) /* (SNIA)HBA_PORTSPEED_10GBIT 4 10 GBit/sec */ + +#define MPI_FCPORTPAGE0_CURRENT_SPEED_1GBIT MPI_FCPORTPAGE0_SUPPORT_1GBIT_SPEED +#define MPI_FCPORTPAGE0_CURRENT_SPEED_2GBIT MPI_FCPORTPAGE0_SUPPORT_2GBIT_SPEED +#define MPI_FCPORTPAGE0_CURRENT_SPEED_10GBIT MPI_FCPORTPAGE0_SUPPORT_10GBIT_SPEED + + +typedef struct _CONFIG_PAGE_FC_PORT_1 +{ + CONFIG_PAGE_HEADER Header; /* 00h */ + U32 Flags; /* 04h */ + U64 NoSEEPROMWWNN; /* 08h */ + U64 NoSEEPROMWWPN; /* 10h */ + U8 HardALPA; /* 18h */ + U8 LinkConfig; /* 19h */ + U8 TopologyConfig; /* 1Ah */ + U8 AltConnector; /* 1Bh */ + U8 NumRequestedAliases; /* 1Ch */ + U8 RR_TOV; /* 1Dh */ + U16 Reserved2; /* 1Eh */ +} CONFIG_PAGE_FC_PORT_1, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_1, + FCPortPage1_t, MPI_POINTER pFCPortPage1_t; + +#define MPI_FCPORTPAGE1_PAGEVERSION (0x05) + +#define MPI_FCPORTPAGE1_FLAGS_EXT_FCP_STATUS_EN (0x08000000) +#define MPI_FCPORTPAGE1_FLAGS_IMMEDIATE_ERROR_REPLY (0x04000000) +#define MPI_FCPORTPAGE1_FLAGS_FORCE_USE_NOSEEPROM_WWNS (0x02000000) +#define MPI_FCPORTPAGE1_FLAGS_VERBOSE_RESCAN_EVENTS (0x01000000) +#define MPI_FCPORTPAGE1_FLAGS_TARGET_MODE_OXID (0x00800000) +#define MPI_FCPORTPAGE1_FLAGS_MASK_RR_TOV_UNITS (0x00000070) +#define MPI_FCPORTPAGE1_FLAGS_MAINTAIN_LOGINS (0x00000002) +#define MPI_FCPORTPAGE1_FLAGS_SORT_BY_DID (0x00000001) +#define MPI_FCPORTPAGE1_FLAGS_SORT_BY_WWN (0x00000000) + +#define MPI_FCPORTPAGE1_FLAGS_PROT_MASK (0xF0000000) +#define MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT (28) +#define MPI_FCPORTPAGE1_FLAGS_PROT_FCP_INIT ((U32)MPI_PORTFACTS_PROTOCOL_INITIATOR << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT) +#define MPI_FCPORTPAGE1_FLAGS_PROT_FCP_TARG ((U32)MPI_PORTFACTS_PROTOCOL_TARGET << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT) +#define MPI_FCPORTPAGE1_FLAGS_PROT_LAN ((U32)MPI_PORTFACTS_PROTOCOL_LAN << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT) +#define MPI_FCPORTPAGE1_FLAGS_PROT_LOGBUSADDR ((U32)MPI_PORTFACTS_PROTOCOL_LOGBUSADDR << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT) + +#define MPI_FCPORTPAGE1_FLAGS_NONE_RR_TOV_UNITS (0x00000000) +#define MPI_FCPORTPAGE1_FLAGS_THOUSANDTH_RR_TOV_UNITS (0x00000010) +#define MPI_FCPORTPAGE1_FLAGS_TENTH_RR_TOV_UNITS (0x00000030) +#define MPI_FCPORTPAGE1_FLAGS_TEN_RR_TOV_UNITS (0x00000050) + +#define MPI_FCPORTPAGE1_HARD_ALPA_NOT_USED (0xFF) + +#define MPI_FCPORTPAGE1_LCONFIG_SPEED_MASK (0x0F) +#define MPI_FCPORTPAGE1_LCONFIG_SPEED_1GIG (0x00) +#define MPI_FCPORTPAGE1_LCONFIG_SPEED_2GIG (0x01) +#define MPI_FCPORTPAGE1_LCONFIG_SPEED_4GIG (0x02) +#define MPI_FCPORTPAGE1_LCONFIG_SPEED_10GIG (0x03) +#define MPI_FCPORTPAGE1_LCONFIG_SPEED_AUTO (0x0F) + +#define MPI_FCPORTPAGE1_TOPOLOGY_MASK (0x0F) +#define MPI_FCPORTPAGE1_TOPOLOGY_NLPORT (0x01) +#define MPI_FCPORTPAGE1_TOPOLOGY_NPORT (0x02) +#define MPI_FCPORTPAGE1_TOPOLOGY_AUTO (0x0F) + +#define MPI_FCPORTPAGE1_ALT_CONN_UNKNOWN (0x00) + + +typedef struct _CONFIG_PAGE_FC_PORT_2 +{ + CONFIG_PAGE_HEADER Header; /* 00h */ + U8 NumberActive; /* 04h */ + U8 ALPA[127]; /* 05h */ +} CONFIG_PAGE_FC_PORT_2, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_2, + FCPortPage2_t, MPI_POINTER pFCPortPage2_t; + +#define MPI_FCPORTPAGE2_PAGEVERSION (0x01) + + +typedef struct _WWN_FORMAT +{ + U64 WWNN; /* 00h */ + U64 WWPN; /* 08h */ +} WWN_FORMAT, MPI_POINTER PTR_WWN_FORMAT, + WWNFormat, MPI_POINTER pWWNFormat; + +typedef union _FC_PORT_PERSISTENT_PHYSICAL_ID +{ + WWN_FORMAT WWN; + U32 Did; +} FC_PORT_PERSISTENT_PHYSICAL_ID, MPI_POINTER PTR_FC_PORT_PERSISTENT_PHYSICAL_ID, + PersistentPhysicalId_t, MPI_POINTER pPersistentPhysicalId_t; + +typedef struct _FC_PORT_PERSISTENT +{ + FC_PORT_PERSISTENT_PHYSICAL_ID PhysicalIdentifier; /* 00h */ + U8 TargetID; /* 10h */ + U8 Bus; /* 11h */ + U16 Flags; /* 12h */ +} FC_PORT_PERSISTENT, MPI_POINTER PTR_FC_PORT_PERSISTENT, + PersistentData_t, MPI_POINTER pPersistentData_t; + +#define MPI_PERSISTENT_FLAGS_SHIFT (16) +#define MPI_PERSISTENT_FLAGS_ENTRY_VALID (0x0001) +#define MPI_PERSISTENT_FLAGS_SCAN_ID (0x0002) +#define MPI_PERSISTENT_FLAGS_SCAN_LUNS (0x0004) +#define MPI_PERSISTENT_FLAGS_BOOT_DEVICE (0x0008) +#define MPI_PERSISTENT_FLAGS_BY_DID (0x0080) + +/* + * Host code (drivers, BIOS, utilities, etc.) should leave this define set to + * one and check Header.PageLength at runtime. + */ +#ifndef MPI_FC_PORT_PAGE_3_ENTRY_MAX +#define MPI_FC_PORT_PAGE_3_ENTRY_MAX (1) +#endif + +typedef struct _CONFIG_PAGE_FC_PORT_3 +{ + CONFIG_PAGE_HEADER Header; /* 00h */ + FC_PORT_PERSISTENT Entry[MPI_FC_PORT_PAGE_3_ENTRY_MAX]; /* 04h */ +} CONFIG_PAGE_FC_PORT_3, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_3, + FCPortPage3_t, MPI_POINTER pFCPortPage3_t; + +#define MPI_FCPORTPAGE3_PAGEVERSION (0x01) + + +typedef struct _CONFIG_PAGE_FC_PORT_4 +{ + CONFIG_PAGE_HEADER Header; /* 00h */ + U32 PortFlags; /* 04h */ + U32 PortSettings; /* 08h */ +} CONFIG_PAGE_FC_PORT_4, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_4, + FCPortPage4_t, MPI_POINTER pFCPortPage4_t; + +#define MPI_FCPORTPAGE4_PAGEVERSION (0x00) + +#define MPI_FCPORTPAGE4_PORT_FLAGS_ALTERNATE_CHS (0x00000008) + +#define MPI_FCPORTPAGE4_PORT_MASK_INIT_HBA (0x00000030) +#define MPI_FCPORTPAGE4_PORT_DISABLE_INIT_HBA (0x00000000) +#define MPI_FCPORTPAGE4_PORT_BIOS_INIT_HBA (0x00000010) +#define MPI_FCPORTPAGE4_PORT_OS_INIT_HBA (0x00000020) +#define MPI_FCPORTPAGE4_PORT_BIOS_OS_INIT_HBA (0x00000030) +#define MPI_FCPORTPAGE4_PORT_REMOVABLE_MEDIA (0x000000C0) +#define MPI_FCPORTPAGE4_PORT_SPINUP_DELAY_MASK (0x00000F00) + + +typedef struct _CONFIG_PAGE_FC_PORT_5_ALIAS_INFO +{ + U8 Flags; /* 00h */ + U8 AliasAlpa; /* 01h */ + U16 Reserved; /* 02h */ + U64 AliasWWNN; /* 04h */ + U64 AliasWWPN; /* 0Ch */ +} CONFIG_PAGE_FC_PORT_5_ALIAS_INFO, + MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_5_ALIAS_INFO, + FcPortPage5AliasInfo_t, MPI_POINTER pFcPortPage5AliasInfo_t; + +typedef struct _CONFIG_PAGE_FC_PORT_5 +{ + CONFIG_PAGE_HEADER Header; /* 00h */ + CONFIG_PAGE_FC_PORT_5_ALIAS_INFO AliasInfo; /* 04h */ +} CONFIG_PAGE_FC_PORT_5, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_5, + FCPortPage5_t, MPI_POINTER pFCPortPage5_t; + +#define MPI_FCPORTPAGE5_PAGEVERSION (0x02) + +#define MPI_FCPORTPAGE5_FLAGS_ALPA_ACQUIRED (0x01) +#define MPI_FCPORTPAGE5_FLAGS_HARD_ALPA (0x02) +#define MPI_FCPORTPAGE5_FLAGS_HARD_WWNN (0x04) +#define MPI_FCPORTPAGE5_FLAGS_HARD_WWPN (0x08) +#define MPI_FCPORTPAGE5_FLAGS_DISABLE (0x10) + +typedef struct _CONFIG_PAGE_FC_PORT_6 +{ + CONFIG_PAGE_HEADER Header; /* 00h */ + U32 Reserved; /* 04h */ + U64 TimeSinceReset; /* 08h */ + U64 TxFrames; /* 10h */ + U64 RxFrames; /* 18h */ + U64 TxWords; /* 20h */ + U64 RxWords; /* 28h */ + U64 LipCount; /* 30h */ + U64 NosCount; /* 38h */ + U64 ErrorFrames; /* 40h */ + U64 DumpedFrames; /* 48h */ + U64 LinkFailureCount; /* 50h */ + U64 LossOfSyncCount; /* 58h */ + U64 LossOfSignalCount; /* 60h */ + U64 PrimativeSeqErrCount; /* 68h */ + U64 InvalidTxWordCount; /* 70h */ + U64 InvalidCrcCount; /* 78h */ + U64 FcpInitiatorIoCount; /* 80h */ +} CONFIG_PAGE_FC_PORT_6, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_6, + FCPortPage6_t, MPI_POINTER pFCPortPage6_t; + +#define MPI_FCPORTPAGE6_PAGEVERSION (0x00) + + +typedef struct _CONFIG_PAGE_FC_PORT_7 +{ + CONFIG_PAGE_HEADER Header; /* 00h */ + U32 Reserved; /* 04h */ + U8 PortSymbolicName[256]; /* 08h */ +} CONFIG_PAGE_FC_PORT_7, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_7, + FCPortPage7_t, MPI_POINTER pFCPortPage7_t; + +#define MPI_FCPORTPAGE7_PAGEVERSION (0x00) + + +typedef struct _CONFIG_PAGE_FC_PORT_8 +{ + CONFIG_PAGE_HEADER Header; /* 00h */ + U32 BitVector[8]; /* 04h */ +} CONFIG_PAGE_FC_PORT_8, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_8, + FCPortPage8_t, MPI_POINTER pFCPortPage8_t; + +#define MPI_FCPORTPAGE8_PAGEVERSION (0x00) + + +typedef struct _CONFIG_PAGE_FC_PORT_9 +{ + CONFIG_PAGE_HEADER Header; /* 00h */ + U32 Reserved; /* 04h */ + U64 GlobalWWPN; /* 08h */ + U64 GlobalWWNN; /* 10h */ + U32 UnitType; /* 18h */ + U32 PhysicalPortNumber; /* 1Ch */ + U32 NumAttachedNodes; /* 20h */ + U16 IPVersion; /* 24h */ + U16 UDPPortNumber; /* 26h */ + U8 IPAddress[16]; /* 28h */ + U16 Reserved1; /* 38h */ + U16 TopologyDiscoveryFlags; /* 3Ah */ +} CONFIG_PAGE_FC_PORT_9, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_9, + FCPortPage9_t, MPI_POINTER pFCPortPage9_t; + +#define MPI_FCPORTPAGE9_PAGEVERSION (0x00) + + +typedef struct _CONFIG_PAGE_FC_PORT_10_BASE_SFP_DATA +{ + U8 Id; /* 10h */ + U8 ExtId; /* 11h */ + U8 Connector; /* 12h */ + U8 Transceiver[8]; /* 13h */ + U8 Encoding; /* 1Bh */ + U8 BitRate_100mbs; /* 1Ch */ + U8 Reserved1; /* 1Dh */ + U8 Length9u_km; /* 1Eh */ + U8 Length9u_100m; /* 1Fh */ + U8 Length50u_10m; /* 20h */ + U8 Length62p5u_10m; /* 21h */ + U8 LengthCopper_m; /* 22h */ + U8 Reseverved2; /* 22h */ + U8 VendorName[16]; /* 24h */ + U8 Reserved3; /* 34h */ + U8 VendorOUI[3]; /* 35h */ + U8 VendorPN[16]; /* 38h */ + U8 VendorRev[4]; /* 48h */ + U16 Reserved4; /* 4Ch */ + U8 Reserved5; /* 4Eh */ + U8 CC_BASE; /* 4Fh */ +} CONFIG_PAGE_FC_PORT_10_BASE_SFP_DATA, + MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_10_BASE_SFP_DATA, + FCPortPage10BaseSfpData_t, MPI_POINTER pFCPortPage10BaseSfpData_t; + +#define MPI_FCPORT10_BASE_ID_UNKNOWN (0x00) +#define MPI_FCPORT10_BASE_ID_GBIC (0x01) +#define MPI_FCPORT10_BASE_ID_FIXED (0x02) +#define MPI_FCPORT10_BASE_ID_SFP (0x03) +#define MPI_FCPORT10_BASE_ID_SFP_MIN (0x04) +#define MPI_FCPORT10_BASE_ID_SFP_MAX (0x7F) +#define MPI_FCPORT10_BASE_ID_VEND_SPEC_MASK (0x80) + +#define MPI_FCPORT10_BASE_EXTID_UNKNOWN (0x00) +#define MPI_FCPORT10_BASE_EXTID_MODDEF1 (0x01) +#define MPI_FCPORT10_BASE_EXTID_MODDEF2 (0x02) +#define MPI_FCPORT10_BASE_EXTID_MODDEF3 (0x03) +#define MPI_FCPORT10_BASE_EXTID_SEEPROM (0x04) +#define MPI_FCPORT10_BASE_EXTID_MODDEF5 (0x05) +#define MPI_FCPORT10_BASE_EXTID_MODDEF6 (0x06) +#define MPI_FCPORT10_BASE_EXTID_MODDEF7 (0x07) +#define MPI_FCPORT10_BASE_EXTID_VNDSPC_MASK (0x80) + +#define MPI_FCPORT10_BASE_CONN_UNKNOWN (0x00) +#define MPI_FCPORT10_BASE_CONN_SC (0x01) +#define MPI_FCPORT10_BASE_CONN_COPPER1 (0x02) +#define MPI_FCPORT10_BASE_CONN_COPPER2 (0x03) +#define MPI_FCPORT10_BASE_CONN_BNC_TNC (0x04) +#define MPI_FCPORT10_BASE_CONN_COAXIAL (0x05) +#define MPI_FCPORT10_BASE_CONN_FIBERJACK (0x06) +#define MPI_FCPORT10_BASE_CONN_LC (0x07) +#define MPI_FCPORT10_BASE_CONN_MT_RJ (0x08) +#define MPI_FCPORT10_BASE_CONN_MU (0x09) +#define MPI_FCPORT10_BASE_CONN_SG (0x0A) +#define MPI_FCPORT10_BASE_CONN_OPT_PIGT (0x0B) +#define MPI_FCPORT10_BASE_CONN_RSV1_MIN (0x0C) +#define MPI_FCPORT10_BASE_CONN_RSV1_MAX (0x1F) +#define MPI_FCPORT10_BASE_CONN_HSSDC_II (0x20) +#define MPI_FCPORT10_BASE_CONN_CPR_PIGT (0x21) +#define MPI_FCPORT10_BASE_CONN_RSV2_MIN (0x22) +#define MPI_FCPORT10_BASE_CONN_RSV2_MAX (0x7F) +#define MPI_FCPORT10_BASE_CONN_VNDSPC_MASK (0x80) + +#define MPI_FCPORT10_BASE_ENCODE_UNSPEC (0x00) +#define MPI_FCPORT10_BASE_ENCODE_8B10B (0x01) +#define MPI_FCPORT10_BASE_ENCODE_4B5B (0x02) +#define MPI_FCPORT10_BASE_ENCODE_NRZ (0x03) +#define MPI_FCPORT10_BASE_ENCODE_MANCHESTER (0x04) + + +typedef struct _CONFIG_PAGE_FC_PORT_10_EXTENDED_SFP_DATA +{ + U8 Options[2]; /* 50h */ + U8 BitRateMax; /* 52h */ + U8 BitRateMin; /* 53h */ + U8 VendorSN[16]; /* 54h */ + U8 DateCode[8]; /* 64h */ + U8 Reserved5[3]; /* 6Ch */ + U8 CC_EXT; /* 6Fh */ +} CONFIG_PAGE_FC_PORT_10_EXTENDED_SFP_DATA, + MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_10_EXTENDED_SFP_DATA, + FCPortPage10ExtendedSfpData_t, MPI_POINTER pFCPortPage10ExtendedSfpData_t; + +#define MPI_FCPORT10_EXT_OPTION1_RATESEL (0x20) +#define MPI_FCPORT10_EXT_OPTION1_TX_DISABLE (0x10) +#define MPI_FCPORT10_EXT_OPTION1_TX_FAULT (0x08) +#define MPI_FCPORT10_EXT_OPTION1_LOS_INVERT (0x04) +#define MPI_FCPORT10_EXT_OPTION1_LOS (0x02) + + +typedef struct _CONFIG_PAGE_FC_PORT_10 +{ + CONFIG_PAGE_HEADER Header; /* 00h */ + U8 Flags; /* 04h */ + U8 Reserved1; /* 05h */ + U16 Reserved2; /* 06h */ + U32 HwConfig1; /* 08h */ + U32 HwConfig2; /* 0Ch */ + CONFIG_PAGE_FC_PORT_10_BASE_SFP_DATA Base; /* 10h */ + CONFIG_PAGE_FC_PORT_10_EXTENDED_SFP_DATA Extended; /* 50h */ + U8 VendorSpecific[32]; /* 70h */ +} CONFIG_PAGE_FC_PORT_10, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_10, + FCPortPage10_t, MPI_POINTER pFCPortPage10_t; + +#define MPI_FCPORTPAGE10_PAGEVERSION (0x00) + +/* standard MODDEF pin definitions (from GBIC spec.) */ +#define MPI_FCPORTPAGE10_FLAGS_MODDEF_MASK (0x00000007) +#define MPI_FCPORTPAGE10_FLAGS_MODDEF2 (0x00000001) +#define MPI_FCPORTPAGE10_FLAGS_MODDEF1 (0x00000002) +#define MPI_FCPORTPAGE10_FLAGS_MODDEF0 (0x00000004) +#define MPI_FCPORTPAGE10_FLAGS_MODDEF_NOGBIC (0x00000007) +#define MPI_FCPORTPAGE10_FLAGS_MODDEF_CPR_IEEE_CX (0x00000006) +#define MPI_FCPORTPAGE10_FLAGS_MODDEF_COPPER (0x00000005) +#define MPI_FCPORTPAGE10_FLAGS_MODDEF_OPTICAL_LW (0x00000004) +#define MPI_FCPORTPAGE10_FLAGS_MODDEF_SEEPROM (0x00000003) +#define MPI_FCPORTPAGE10_FLAGS_MODDEF_SW_OPTICAL (0x00000002) +#define MPI_FCPORTPAGE10_FLAGS_MODDEF_LX_IEEE_OPT_LW (0x00000001) +#define MPI_FCPORTPAGE10_FLAGS_MODDEF_SX_IEEE_OPT_SW (0x00000000) + +#define MPI_FCPORTPAGE10_FLAGS_CC_BASE_OK (0x00000010) +#define MPI_FCPORTPAGE10_FLAGS_CC_EXT_OK (0x00000020) + + +/**************************************************************************** +* FC Device Config Pages +****************************************************************************/ + +typedef struct _CONFIG_PAGE_FC_DEVICE_0 +{ + CONFIG_PAGE_HEADER Header; /* 00h */ + U64 WWNN; /* 04h */ + U64 WWPN; /* 0Ch */ + U32 PortIdentifier; /* 14h */ + U8 Protocol; /* 18h */ + U8 Flags; /* 19h */ + U16 BBCredit; /* 1Ah */ + U16 MaxRxFrameSize; /* 1Ch */ + U8 Reserved1; /* 1Eh */ + U8 PortNumber; /* 1Fh */ + U8 FcPhLowestVersion; /* 20h */ + U8 FcPhHighestVersion; /* 21h */ + U8 CurrentTargetID; /* 22h */ + U8 CurrentBus; /* 23h */ +} CONFIG_PAGE_FC_DEVICE_0, MPI_POINTER PTR_CONFIG_PAGE_FC_DEVICE_0, + FCDevicePage0_t, MPI_POINTER pFCDevicePage0_t; + +#define MPI_FC_DEVICE_PAGE0_PAGEVERSION (0x02) + +#define MPI_FC_DEVICE_PAGE0_FLAGS_TARGETID_BUS_VALID (0x01) +#define MPI_FC_DEVICE_PAGE0_FLAGS_PLOGI_INVALID (0x02) +#define MPI_FC_DEVICE_PAGE0_FLAGS_PRLI_INVALID (0x04) + +#define MPI_FC_DEVICE_PAGE0_PROT_IP (0x01) +#define MPI_FC_DEVICE_PAGE0_PROT_FCP_TARGET (0x02) +#define MPI_FC_DEVICE_PAGE0_PROT_FCP_INITIATOR (0x04) + +#define MPI_FC_DEVICE_PAGE0_PGAD_PORT_MASK (MPI_FC_DEVICE_PGAD_PORT_MASK) +#define MPI_FC_DEVICE_PAGE0_PGAD_FORM_MASK (MPI_FC_DEVICE_PGAD_FORM_MASK) +#define MPI_FC_DEVICE_PAGE0_PGAD_FORM_NEXT_DID (MPI_FC_DEVICE_PGAD_FORM_NEXT_DID) +#define MPI_FC_DEVICE_PAGE0_PGAD_FORM_BUS_TID (MPI_FC_DEVICE_PGAD_FORM_BUS_TID) +#define MPI_FC_DEVICE_PAGE0_PGAD_DID_MASK (MPI_FC_DEVICE_PGAD_ND_DID_MASK) +#define MPI_FC_DEVICE_PAGE0_PGAD_BUS_MASK (MPI_FC_DEVICE_PGAD_BT_BUS_MASK) +#define MPI_FC_DEVICE_PAGE0_PGAD_BUS_SHIFT (MPI_FC_DEVICE_PGAD_BT_BUS_SHIFT) +#define MPI_FC_DEVICE_PAGE0_PGAD_TID_MASK (MPI_FC_DEVICE_PGAD_BT_TID_MASK) + + +/**************************************************************************** +* RAID Volume Config Pages +****************************************************************************/ + +typedef struct _RAID_VOL0_PHYS_DISK +{ + U16 Reserved; /* 00h */ + U8 PhysDiskMap; /* 02h */ + U8 PhysDiskNum; /* 03h */ +} RAID_VOL0_PHYS_DISK, MPI_POINTER PTR_RAID_VOL0_PHYS_DISK, + RaidVol0PhysDisk_t, MPI_POINTER pRaidVol0PhysDisk_t; + +#define MPI_RAIDVOL0_PHYSDISK_PRIMARY (0x01) +#define MPI_RAIDVOL0_PHYSDISK_SECONDARY (0x02) + +typedef struct _RAID_VOL0_STATUS +{ + U8 Flags; /* 00h */ + U8 State; /* 01h */ + U16 Reserved; /* 02h */ +} RAID_VOL0_STATUS, MPI_POINTER PTR_RAID_VOL0_STATUS, + RaidVol0Status_t, MPI_POINTER pRaidVol0Status_t; + +/* RAID Volume Page 0 VolumeStatus defines */ + +#define MPI_RAIDVOL0_STATUS_FLAG_ENABLED (0x01) +#define MPI_RAIDVOL0_STATUS_FLAG_QUIESCED (0x02) +#define MPI_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS (0x04) +#define MPI_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE (0x08) + +#define MPI_RAIDVOL0_STATUS_STATE_OPTIMAL (0x00) +#define MPI_RAIDVOL0_STATUS_STATE_DEGRADED (0x01) +#define MPI_RAIDVOL0_STATUS_STATE_FAILED (0x02) + +typedef struct _RAID_VOL0_SETTINGS +{ + U16 Settings; /* 00h */ + U8 HotSparePool; /* 01h */ /* MPI_RAID_HOT_SPARE_POOL_ */ + U8 Reserved; /* 02h */ +} RAID_VOL0_SETTINGS, MPI_POINTER PTR_RAID_VOL0_SETTINGS, + RaidVol0Settings, MPI_POINTER pRaidVol0Settings; + +/* RAID Volume Page 0 VolumeSettings defines */ + +#define MPI_RAIDVOL0_SETTING_WRITE_CACHING_ENABLE (0x0001) +#define MPI_RAIDVOL0_SETTING_OFFLINE_ON_SMART (0x0002) +#define MPI_RAIDVOL0_SETTING_AUTO_CONFIGURE (0x0004) +#define MPI_RAIDVOL0_SETTING_PRIORITY_RESYNC (0x0008) +#define MPI_RAIDVOL0_SETTING_USE_PRODUCT_ID_SUFFIX (0x0010) +#define MPI_RAIDVOL0_SETTING_USE_DEFAULTS (0x8000) + +/* RAID Volume Page 0 HotSparePool defines, also used in RAID Physical Disk */ +#define MPI_RAID_HOT_SPARE_POOL_0 (0x01) +#define MPI_RAID_HOT_SPARE_POOL_1 (0x02) +#define MPI_RAID_HOT_SPARE_POOL_2 (0x04) +#define MPI_RAID_HOT_SPARE_POOL_3 (0x08) +#define MPI_RAID_HOT_SPARE_POOL_4 (0x10) +#define MPI_RAID_HOT_SPARE_POOL_5 (0x20) +#define MPI_RAID_HOT_SPARE_POOL_6 (0x40) +#define MPI_RAID_HOT_SPARE_POOL_7 (0x80) + +/* + * Host code (drivers, BIOS, utilities, etc.) should leave this define set to + * one and check Header.PageLength at runtime. + */ +#ifndef MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX +#define MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX (1) +#endif + +typedef struct _CONFIG_PAGE_RAID_VOL_0 +{ + CONFIG_PAGE_HEADER Header; /* 00h */ + U8 VolumeID; /* 04h */ + U8 VolumeBus; /* 05h */ + U8 VolumeIOC; /* 06h */ + U8 VolumeType; /* 07h */ /* MPI_RAID_VOL_TYPE_ */ + RAID_VOL0_STATUS VolumeStatus; /* 08h */ + RAID_VOL0_SETTINGS VolumeSettings; /* 0Ch */ + U32 MaxLBA; /* 10h */ + U32 Reserved1; /* 14h */ + U32 StripeSize; /* 18h */ + U32 Reserved2; /* 1Ch */ + U32 Reserved3; /* 20h */ + U8 NumPhysDisks; /* 24h */ + U8 Reserved4; /* 25h */ + U16 Reserved5; /* 26h */ + RAID_VOL0_PHYS_DISK PhysDisk[MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX];/* 28h */ +} CONFIG_PAGE_RAID_VOL_0, MPI_POINTER PTR_CONFIG_PAGE_RAID_VOL_0, + RaidVolumePage0_t, MPI_POINTER pRaidVolumePage0_t; + +#define MPI_RAIDVOLPAGE0_PAGEVERSION (0x01) + + +/**************************************************************************** +* RAID Physical Disk Config Pages +****************************************************************************/ + +typedef struct _RAID_PHYS_DISK0_ERROR_DATA +{ + U8 ErrorCdbByte; /* 00h */ + U8 ErrorSenseKey; /* 01h */ + U16 Reserved; /* 02h */ + U16 ErrorCount; /* 04h */ + U8 ErrorASC; /* 06h */ + U8 ErrorASCQ; /* 07h */ + U16 SmartCount; /* 08h */ + U8 SmartASC; /* 0Ah */ + U8 SmartASCQ; /* 0Bh */ +} RAID_PHYS_DISK0_ERROR_DATA, MPI_POINTER PTR_RAID_PHYS_DISK0_ERROR_DATA, + RaidPhysDisk0ErrorData_t, MPI_POINTER pRaidPhysDisk0ErrorData_t; + +typedef struct _RAID_PHYS_DISK_INQUIRY_DATA +{ + U8 VendorID[8]; /* 00h */ + U8 ProductID[16]; /* 08h */ + U8 ProductRevLevel[4]; /* 18h */ + U8 Info[32]; /* 1Ch */ +} RAID_PHYS_DISK0_INQUIRY_DATA, MPI_POINTER PTR_RAID_PHYS_DISK0_INQUIRY_DATA, + RaidPhysDisk0InquiryData, MPI_POINTER pRaidPhysDisk0InquiryData; + +typedef struct _RAID_PHYS_DISK0_SETTINGS +{ + U8 SepID; /* 00h */ + U8 SepBus; /* 01h */ + U8 HotSparePool; /* 02h */ /* MPI_RAID_HOT_SPARE_POOL_ */ + U8 PhysDiskSettings; /* 03h */ +} RAID_PHYS_DISK0_SETTINGS, MPI_POINTER PTR_RAID_PHYS_DISK0_SETTINGS, + RaidPhysDiskSettings_t, MPI_POINTER pRaidPhysDiskSettings_t; + +typedef struct _RAID_PHYS_DISK0_STATUS +{ + U8 Flags; /* 00h */ + U8 State; /* 01h */ + U16 Reserved; /* 02h */ +} RAID_PHYS_DISK0_STATUS, MPI_POINTER PTR_RAID_PHYS_DISK0_STATUS, + RaidPhysDiskStatus_t, MPI_POINTER pRaidPhysDiskStatus_t; + +/* RAID Volume 2 IM Physical Disk DiskStatus flags */ + +#define MPI_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC (0x01) +#define MPI_PHYSDISK0_STATUS_FLAG_QUIESCED (0x02) + +#define MPI_PHYSDISK0_STATUS_ONLINE (0x00) +#define MPI_PHYSDISK0_STATUS_MISSING (0x01) +#define MPI_PHYSDISK0_STATUS_NOT_COMPATIBLE (0x02) +#define MPI_PHYSDISK0_STATUS_FAILED (0x03) +#define MPI_PHYSDISK0_STATUS_INITIALIZING (0x04) +#define MPI_PHYSDISK0_STATUS_OFFLINE_REQUESTED (0x05) +#define MPI_PHYSDISK0_STATUS_FAILED_REQUESTED (0x06) +#define MPI_PHYSDISK0_STATUS_OTHER_OFFLINE (0xFF) + +typedef struct _CONFIG_PAGE_RAID_PHYS_DISK_0 +{ + CONFIG_PAGE_HEADER Header; /* 00h */ + U8 PhysDiskID; /* 04h */ + U8 PhysDiskBus; /* 05h */ + U8 PhysDiskIOC; /* 06h */ + U8 PhysDiskNum; /* 07h */ + RAID_PHYS_DISK0_SETTINGS PhysDiskSettings; /* 08h */ + U32 Reserved1; /* 0Ch */ + U32 Reserved2; /* 10h */ + U32 Reserved3; /* 14h */ + U8 DiskIdentifier[16]; /* 18h */ + RAID_PHYS_DISK0_INQUIRY_DATA InquiryData; /* 28h */ + RAID_PHYS_DISK0_STATUS PhysDiskStatus; /* 64h */ + U32 MaxLBA; /* 68h */ + RAID_PHYS_DISK0_ERROR_DATA ErrorData; /* 6Ch */ +} CONFIG_PAGE_RAID_PHYS_DISK_0, MPI_POINTER PTR_CONFIG_PAGE_RAID_PHYS_DISK_0, + RaidPhysDiskPage0_t, MPI_POINTER pRaidPhysDiskPage0_t; + +#define MPI_RAIDPHYSDISKPAGE0_PAGEVERSION (0x00) + + +/**************************************************************************** +* LAN Config Pages +****************************************************************************/ + +typedef struct _CONFIG_PAGE_LAN_0 +{ + ConfigPageHeader_t Header; /* 00h */ + U16 TxRxModes; /* 04h */ + U16 Reserved; /* 06h */ + U32 PacketPrePad; /* 08h */ +} CONFIG_PAGE_LAN_0, MPI_POINTER PTR_CONFIG_PAGE_LAN_0, + LANPage0_t, MPI_POINTER pLANPage0_t; + +#define MPI_LAN_PAGE0_PAGEVERSION (0x01) + +#define MPI_LAN_PAGE0_RETURN_LOOPBACK (0x0000) +#define MPI_LAN_PAGE0_SUPPRESS_LOOPBACK (0x0001) +#define MPI_LAN_PAGE0_LOOPBACK_MASK (0x0001) + +typedef struct _CONFIG_PAGE_LAN_1 +{ + ConfigPageHeader_t Header; /* 00h */ + U16 Reserved; /* 04h */ + U8 CurrentDeviceState; /* 06h */ + U8 Reserved1; /* 07h */ + U32 MinPacketSize; /* 08h */ + U32 MaxPacketSize; /* 0Ch */ + U32 HardwareAddressLow; /* 10h */ + U32 HardwareAddressHigh; /* 14h */ + U32 MaxWireSpeedLow; /* 18h */ + U32 MaxWireSpeedHigh; /* 1Ch */ + U32 BucketsRemaining; /* 20h */ + U32 MaxReplySize; /* 24h */ + U32 NegWireSpeedLow; /* 28h */ + U32 NegWireSpeedHigh; /* 2Ch */ +} CONFIG_PAGE_LAN_1, MPI_POINTER PTR_CONFIG_PAGE_LAN_1, + LANPage1_t, MPI_POINTER pLANPage1_t; + +#define MPI_LAN_PAGE1_PAGEVERSION (0x03) + +#define MPI_LAN_PAGE1_DEV_STATE_RESET (0x00) +#define MPI_LAN_PAGE1_DEV_STATE_OPERATIONAL (0x01) + +#endif + diff --git a/sys/dev/mpt/mpilib/mpi_fc.h b/sys/dev/mpt/mpilib/mpi_fc.h new file mode 100644 index 0000000..60487e1 --- /dev/null +++ b/sys/dev/mpt/mpilib/mpi_fc.h @@ -0,0 +1,381 @@ +/* $FreeBSD$ */ +/* + * Copyright (c) 2000, 2001 by LSI Logic Corporation + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice immediately at the beginning of the file, without modification, + * this list of conditions, and the following disclaimer. + * 2. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * + * Name: MPI_FC.H + * Title: MPI Fibre Channel messages and structures + * Creation Date: June 12, 2000 + * + * MPI Version: 01.02.02 + * + * Version History + * --------------- + * + * Date Version Description + * -------- -------- ------------------------------------------------------ + * 05-08-00 00.10.01 Original release for 0.10 spec dated 4/26/2000. + * 06-06-00 01.00.01 Update version number for 1.0 release. + * 06-12-00 01.00.02 Added _MSG_FC_ABORT_REPLY structure. + * 11-02-00 01.01.01 Original release for post 1.0 work + * 12-04-00 01.01.02 Added messages for Common Transport Send and + * Primitive Send. + * 01-09-01 01.01.03 Modifed some of the new flags to have an MPI prefix + * and modified the FcPrimitiveSend flags. + * 01-25-01 01.01.04 Move InitiatorIndex in LinkServiceRsp reply to a larger + * field. + * Added FC_ABORT_TYPE_CT_SEND_REQUEST and + * FC_ABORT_TYPE_EXLINKSEND_REQUEST for FcAbort request. + * Added MPI_FC_PRIM_SEND_FLAGS_STOP_SEND. + * 02-20-01 01.01.05 Started using MPI_POINTER. + * 03-27-01 01.01.06 Added Flags field to MSG_LINK_SERVICE_BUFFER_POST_REPLY + * and defined MPI_LS_BUF_POST_REPLY_FLAG_NO_RSP_NEEDED. + * Added MPI_FC_PRIM_SEND_FLAGS_RESET_LINK define. + * Added structure offset comments. + * 04-09-01 01.01.07 Added RspLength field to MSG_LINK_SERVICE_RSP_REQUEST. + * 08-08-01 01.02.01 Original release for v1.2 work. + * 09-28-01 01.02.02 Change name of reserved field in + * MSG_LINK_SERVICE_RSP_REPLY. + * -------------------------------------------------------------------------- + */ + +#ifndef MPI_FC_H +#define MPI_FC_H + + +/***************************************************************************** +* +* F C T a r g e t M o d e M e s s a g e s +* +*****************************************************************************/ + +/****************************************************************************/ +/* Link Service Buffer Post messages */ +/****************************************************************************/ + +typedef struct _MSG_LINK_SERVICE_BUFFER_POST_REQUEST +{ + U8 BufferPostFlags; /* 00h */ + U8 BufferCount; /* 01h */ + U8 ChainOffset; /* 02h */ + U8 Function; /* 03h */ + U16 Reserved; /* 04h */ + U8 Reserved1; /* 06h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ + SGE_TRANS_SIMPLE_UNION SGL; +} MSG_LINK_SERVICE_BUFFER_POST_REQUEST, + MPI_POINTER PTR_MSG_LINK_SERVICE_BUFFER_POST_REQUEST, + LinkServiceBufferPostRequest_t, MPI_POINTER pLinkServiceBufferPostRequest_t; + +#define LINK_SERVICE_BUFFER_POST_FLAGS_PORT_MASK (0x01) + +typedef struct _WWNFORMAT +{ + U32 PortNameHigh; /* 00h */ + U32 PortNameLow; /* 04h */ + U32 NodeNameHigh; /* 08h */ + U32 NodeNameLow; /* 0Ch */ +} WWNFORMAT, + WwnFormat_t; + +/* Link Service Buffer Post Reply */ +typedef struct _MSG_LINK_SERVICE_BUFFER_POST_REPLY +{ + U8 Flags; /* 00h */ + U8 Reserved; /* 01h */ + U8 MsgLength; /* 02h */ + U8 Function; /* 03h */ + U16 Reserved1; /* 04h */ + U8 PortNumber; /* 06h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ + U16 Reserved2; /* 0Ch */ + U16 IOCStatus; /* 0Eh */ + U32 IOCLogInfo; /* 10h */ + U32 TransferLength; /* 14h */ + U32 TransactionContext; /* 18h */ + U32 Rctl_Did; /* 1Ch */ + U32 Csctl_Sid; /* 20h */ + U32 Type_Fctl; /* 24h */ + U16 SeqCnt; /* 28h */ + U8 Dfctl; /* 2Ah */ + U8 SeqId; /* 2Bh */ + U16 Rxid; /* 2Ch */ + U16 Oxid; /* 2Eh */ + U32 Parameter; /* 30h */ + WWNFORMAT Wwn; /* 34h */ +} MSG_LINK_SERVICE_BUFFER_POST_REPLY, MPI_POINTER PTR_MSG_LINK_SERVICE_BUFFER_POST_REPLY, + LinkServiceBufferPostReply_t, MPI_POINTER pLinkServiceBufferPostReply_t; + +#define MPI_LS_BUF_POST_REPLY_FLAG_NO_RSP_NEEDED (0x80) + +#define MPI_FC_DID_MASK (0x00FFFFFF) +#define MPI_FC_DID_SHIFT (0) +#define MPI_FC_RCTL_MASK (0xFF000000) +#define MPI_FC_RCTL_SHIFT (24) +#define MPI_FC_SID_MASK (0x00FFFFFF) +#define MPI_FC_SID_SHIFT (0) +#define MPI_FC_CSCTL_MASK (0xFF000000) +#define MPI_FC_CSCTL_SHIFT (24) +#define MPI_FC_FCTL_MASK (0x00FFFFFF) +#define MPI_FC_FCTL_SHIFT (0) +#define MPI_FC_TYPE_MASK (0xFF000000) +#define MPI_FC_TYPE_SHIFT (24) + +/* obsolete name for the above */ +#define FCP_TARGET_DID_MASK (0x00FFFFFF) +#define FCP_TARGET_DID_SHIFT (0) +#define FCP_TARGET_RCTL_MASK (0xFF000000) +#define FCP_TARGET_RCTL_SHIFT (24) +#define FCP_TARGET_SID_MASK (0x00FFFFFF) +#define FCP_TARGET_SID_SHIFT (0) +#define FCP_TARGET_CSCTL_MASK (0xFF000000) +#define FCP_TARGET_CSCTL_SHIFT (24) +#define FCP_TARGET_FCTL_MASK (0x00FFFFFF) +#define FCP_TARGET_FCTL_SHIFT (0) +#define FCP_TARGET_TYPE_MASK (0xFF000000) +#define FCP_TARGET_TYPE_SHIFT (24) + + +/****************************************************************************/ +/* Link Service Response messages */ +/****************************************************************************/ + +typedef struct _MSG_LINK_SERVICE_RSP_REQUEST +{ + U8 RspFlags; /* 00h */ + U8 RspLength; /* 01h */ + U8 ChainOffset; /* 02h */ + U8 Function; /* 03h */ + U16 Reserved1; /* 04h */ + U8 Reserved2; /* 06h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ + U32 Rctl_Did; /* 0Ch */ + U32 Csctl_Sid; /* 10h */ + U32 Type_Fctl; /* 14h */ + U16 SeqCnt; /* 18h */ + U8 Dfctl; /* 1Ah */ + U8 SeqId; /* 1Bh */ + U16 Rxid; /* 1Ch */ + U16 Oxid; /* 1Eh */ + U32 Parameter; /* 20h */ + SGE_SIMPLE_UNION SGL; /* 24h */ +} MSG_LINK_SERVICE_RSP_REQUEST, MPI_POINTER PTR_MSG_LINK_SERVICE_RSP_REQUEST, + LinkServiceRspRequest_t, MPI_POINTER pLinkServiceRspRequest_t; + +#define LINK_SERVICE_RSP_FLAGS_IMMEDIATE (0x80) +#define LINK_SERVICE_RSP_FLAGS_PORT_MASK (0x01) + + +/* Link Service Response Reply */ +typedef struct _MSG_LINK_SERVICE_RSP_REPLY +{ + U16 Reserved; /* 00h */ + U8 MsgLength; /* 02h */ + U8 Function; /* 03h */ + U16 Reserved1; /* 04h */ + U8 Reserved_0100_InitiatorIndex; /* 06h */ /* obsolete InitiatorIndex */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ + U16 Reserved3; /* 0Ch */ + U16 IOCStatus; /* 0Eh */ + U32 IOCLogInfo; /* 10h */ + U32 InitiatorIndex; /* 14h */ +} MSG_LINK_SERVICE_RSP_REPLY, MPI_POINTER PTR_MSG_LINK_SERVICE_RSP_REPLY, + LinkServiceRspReply_t, MPI_POINTER pLinkServiceRspReply_t; + + +/****************************************************************************/ +/* Extended Link Service Send messages */ +/****************************************************************************/ + +typedef struct _MSG_EXLINK_SERVICE_SEND_REQUEST +{ + U8 SendFlags; /* 00h */ + U8 Reserved; /* 01h */ + U8 ChainOffset; /* 02h */ + U8 Function; /* 03h */ + U32 MsgFlags_Did; /* 04h */ + U32 MsgContext; /* 08h */ + U32 ElsCommandCode; /* 0Ch */ + SGE_SIMPLE_UNION SGL; /* 10h */ +} MSG_EXLINK_SERVICE_SEND_REQUEST, MPI_POINTER PTR_MSG_EXLINK_SERVICE_SEND_REQUEST, + ExLinkServiceSendRequest_t, MPI_POINTER pExLinkServiceSendRequest_t; + +#define EX_LINK_SERVICE_SEND_DID_MASK (0x00FFFFFF) +#define EX_LINK_SERVICE_SEND_DID_SHIFT (0) +#define EX_LINK_SERVICE_SEND_MSGFLAGS_MASK (0xFF000000) +#define EX_LINK_SERVICE_SEND_MSGFLAGS_SHIFT (24) + + +/* Extended Link Service Send Reply */ +typedef struct _MSG_EXLINK_SERVICE_SEND_REPLY +{ + U16 Reserved; /* 00h */ + U8 MsgLength; /* 02h */ + U8 Function; /* 03h */ + U16 Reserved1; /* 04h */ + U8 Reserved2; /* 06h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ + U16 Reserved3; /* 0Ch */ + U16 IOCStatus; /* 0Eh */ + U32 IOCLogInfo; /* 10h */ + U32 ResponseLength; /* 14h */ +} MSG_EXLINK_SERVICE_SEND_REPLY, MPI_POINTER PTR_MSG_EXLINK_SERVICE_SEND_REPLY, + ExLinkServiceSendReply_t, MPI_POINTER pExLinkServiceSendReply_t; + +/****************************************************************************/ +/* FC Abort messages */ +/****************************************************************************/ + +typedef struct _MSG_FC_ABORT_REQUEST +{ + U8 AbortFlags; /* 00h */ + U8 AbortType; /* 01h */ + U8 ChainOffset; /* 02h */ + U8 Function; /* 03h */ + U16 Reserved1; /* 04h */ + U8 Reserved2; /* 06h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ + U32 TransactionContextToAbort; /* 0Ch */ +} MSG_FC_ABORT_REQUEST, MPI_POINTER PTR_MSG_FC_ABORT_REQUEST, + FcAbortRequest_t, MPI_POINTER pFcAbortRequest_t; + +#define FC_ABORT_FLAG_PORT_MASK (0x01) + +#define FC_ABORT_TYPE_ALL_FC_BUFFERS (0x00) +#define FC_ABORT_TYPE_EXACT_FC_BUFFER (0x01) +#define FC_ABORT_TYPE_CT_SEND_REQUEST (0x02) +#define FC_ABORT_TYPE_EXLINKSEND_REQUEST (0x03) + +/* FC Abort Reply */ +typedef struct _MSG_FC_ABORT_REPLY +{ + U16 Reserved; /* 00h */ + U8 MsgLength; /* 02h */ + U8 Function; /* 03h */ + U16 Reserved1; /* 04h */ + U8 Reserved2; /* 06h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ + U16 Reserved3; /* 0Ch */ + U16 IOCStatus; /* 0Eh */ + U32 IOCLogInfo; /* 10h */ +} MSG_FC_ABORT_REPLY, MPI_POINTER PTR_MSG_FC_ABORT_REPLY, + FcAbortReply_t, MPI_POINTER pFcAbortReply_t; + + +/****************************************************************************/ +/* FC Common Transport Send messages */ +/****************************************************************************/ + +typedef struct _MSG_FC_COMMON_TRANSPORT_SEND_REQUEST +{ + U8 SendFlags; /* 00h */ + U8 Reserved; /* 01h */ + U8 ChainOffset; /* 02h */ + U8 Function; /* 03h */ + U32 MsgFlags_Did; /* 04h */ + U32 MsgContext; /* 08h */ + U16 CTCommandCode; /* 0Ch */ + U8 FsType; /* 0Eh */ + U8 Reserved1; /* 0Fh */ + SGE_SIMPLE_UNION SGL; /* 10h */ +} MSG_FC_COMMON_TRANSPORT_SEND_REQUEST, + MPI_POINTER PTR_MSG_FC_COMMON_TRANSPORT_SEND_REQUEST, + FcCommonTransportSendRequest_t, MPI_POINTER pFcCommonTransportSendRequest_t; + +#define MPI_FC_CT_SEND_DID_MASK (0x00FFFFFF) +#define MPI_FC_CT_SEND_DID_SHIFT (0) +#define MPI_FC_CT_SEND_MSGFLAGS_MASK (0xFF000000) +#define MPI_FC_CT_SEND_MSGFLAGS_SHIFT (24) + + +/* FC Common Transport Send Reply */ +typedef struct _MSG_FC_COMMON_TRANSPORT_SEND_REPLY +{ + U16 Reserved; /* 00h */ + U8 MsgLength; /* 02h */ + U8 Function; /* 03h */ + U16 Reserved1; /* 04h */ + U8 Reserved2; /* 06h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ + U16 Reserved3; /* 0Ch */ + U16 IOCStatus; /* 0Eh */ + U32 IOCLogInfo; /* 10h */ + U32 ResponseLength; /* 14h */ +} MSG_FC_COMMON_TRANSPORT_SEND_REPLY, MPI_POINTER PTR_MSG_FC_COMMON_TRANSPORT_SEND_REPLY, + FcCommonTransportSendReply_t, MPI_POINTER pFcCommonTransportSendReply_t; + + +/****************************************************************************/ +/* FC Primitive Send messages */ +/****************************************************************************/ + +typedef struct _MSG_FC_PRIMITIVE_SEND_REQUEST +{ + U8 SendFlags; /* 00h */ + U8 Reserved; /* 01h */ + U8 ChainOffset; /* 02h */ + U8 Function; /* 03h */ + U16 Reserved1; /* 04h */ + U8 Reserved2; /* 06h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ + U8 FcPrimitive[4]; /* 0Ch */ +} MSG_FC_PRIMITIVE_SEND_REQUEST, MPI_POINTER PTR_MSG_FC_PRIMITIVE_SEND_REQUEST, + FcPrimitiveSendRequest_t, MPI_POINTER pFcPrimitiveSendRequest_t; + +#define MPI_FC_PRIM_SEND_FLAGS_PORT_MASK (0x01) +#define MPI_FC_PRIM_SEND_FLAGS_RESET_LINK (0x04) +#define MPI_FC_PRIM_SEND_FLAGS_STOP_SEND (0x08) +#define MPI_FC_PRIM_SEND_FLAGS_SEND_ONCE (0x10) +#define MPI_FC_PRIM_SEND_FLAGS_SEND_AROUND (0x20) +#define MPI_FC_PRIM_SEND_FLAGS_UNTIL_FULL (0x40) +#define MPI_FC_PRIM_SEND_FLAGS_FOREVER (0x80) + +/* FC Primitive Send Reply */ +typedef struct _MSG_FC_PRIMITIVE_SEND_REPLY +{ + U8 SendFlags; /* 00h */ + U8 Reserved; /* 01h */ + U8 MsgLength; /* 02h */ + U8 Function; /* 03h */ + U16 Reserved1; /* 04h */ + U8 Reserved2; /* 06h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ + U16 Reserved3; /* 0Ch */ + U16 IOCStatus; /* 0Eh */ + U32 IOCLogInfo; /* 10h */ +} MSG_FC_PRIMITIVE_SEND_REPLY, MPI_POINTER PTR_MSG_FC_PRIMITIVE_SEND_REPLY, + FcPrimitiveSendReply_t, MPI_POINTER pFcPrimitiveSendReply_t; + +#endif + diff --git a/sys/dev/mpt/mpilib/mpi_init.h b/sys/dev/mpt/mpilib/mpi_init.h new file mode 100644 index 0000000..7854588 --- /dev/null +++ b/sys/dev/mpt/mpilib/mpi_init.h @@ -0,0 +1,344 @@ +/* $FreeBSD$ */ +/* + * Copyright (c) 2000, 2001 by LSI Logic Corporation + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice immediately at the beginning of the file, without modification, + * this list of conditions, and the following disclaimer. + * 2. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * + * Name: MPI_INIT.H + * Title: MPI initiator mode messages and structures + * Creation Date: June 8, 2000 + * + * MPI_INIT.H Version: 01.02.06 + * + * Version History + * --------------- + * + * Date Version Description + * -------- -------- ------------------------------------------------------ + * 05-08-00 00.10.01 Original release for 0.10 spec dated 4/26/2000. + * 05-24-00 00.10.02 Added SenseBufferLength to _MSG_SCSI_IO_REPLY. + * 06-06-00 01.00.01 Update version number for 1.0 release. + * 06-08-00 01.00.02 Added MPI_SCSI_RSP_INFO_ definitions. + * 11-02-00 01.01.01 Original release for post 1.0 work. + * 12-04-00 01.01.02 Added MPI_SCSIIO_CONTROL_NO_DISCONNECT. + * 02-20-01 01.01.03 Started using MPI_POINTER. + * 03-27-01 01.01.04 Added structure offset comments. + * 04-10-01 01.01.05 Added new MsgFlag for MSG_SCSI_TASK_MGMT. + * 08-08-01 01.02.01 Original release for v1.2 work. + * 08-29-01 01.02.02 Added MPI_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET. + * Added MPI_SCSI_STATE_QUEUE_TAG_REJECTED for + * MSG_SCSI_IO_REPLY. + * 09-28-01 01.02.03 Added structures and defines for SCSI Enclosure + * Processor messages. + * 10-04-01 01.02.04 Added defines for SEP request Action field. + * 05-31-02 01.02.05 Added MPI_SCSIIO_MSGFLGS_CMD_DETERMINES_DATA_DIR define + * for SCSI IO requests. + * 11-15-02 01.02.06 Added special extended SCSI Status defines for FCP. + * -------------------------------------------------------------------------- + */ + +#ifndef MPI_INIT_H +#define MPI_INIT_H + + +/***************************************************************************** +* +* S C S I I n i t i a t o r M e s s a g e s +* +*****************************************************************************/ + +/****************************************************************************/ +/* SCSI IO messages and assocaited structures */ +/****************************************************************************/ + +typedef struct _MSG_SCSI_IO_REQUEST +{ + U8 TargetID; /* 00h */ + U8 Bus; /* 01h */ + U8 ChainOffset; /* 02h */ + U8 Function; /* 03h */ + U8 CDBLength; /* 04h */ + U8 SenseBufferLength; /* 05h */ + U8 Reserved; /* 06h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ + U8 LUN[8]; /* 0Ch */ + U32 Control; /* 14h */ + U8 CDB[16]; /* 18h */ + U32 DataLength; /* 28h */ + U32 SenseBufferLowAddr; /* 2Ch */ + SGE_IO_UNION SGL; /* 30h */ +} MSG_SCSI_IO_REQUEST, MPI_POINTER PTR_MSG_SCSI_IO_REQUEST, + SCSIIORequest_t, MPI_POINTER pSCSIIORequest_t; + + +/* SCSI IO MsgFlags bits */ + +#define MPI_SCSIIO_MSGFLGS_SENSE_WIDTH (0x01) +#define MPI_SCSIIO_MSGFLGS_SENSE_WIDTH_32 (0x00) +#define MPI_SCSIIO_MSGFLGS_SENSE_WIDTH_64 (0x01) +#define MPI_SCSIIO_MSGFLGS_SENSE_LOCATION (0x02) +#define MPI_SCSIIO_MSGFLGS_SENSE_LOC_HOST (0x00) +#define MPI_SCSIIO_MSGFLGS_SENSE_LOC_IOC (0x02) +#define MPI_SCSIIO_MSGFLGS_CMD_DETERMINES_DATA_DIR (0x04) + +/* SCSI IO LUN fields */ + +#define MPI_SCSIIO_LUN_FIRST_LEVEL_ADDRESSING (0x0000FFFF) +#define MPI_SCSIIO_LUN_SECOND_LEVEL_ADDRESSING (0xFFFF0000) +#define MPI_SCSIIO_LUN_THIRD_LEVEL_ADDRESSING (0x0000FFFF) +#define MPI_SCSIIO_LUN_FOURTH_LEVEL_ADDRESSING (0xFFFF0000) +#define MPI_SCSIIO_LUN_LEVEL_1_WORD (0xFF00) +#define MPI_SCSIIO_LUN_LEVEL_1_DWORD (0x0000FF00) + +/* SCSI IO Control bits */ + +#define MPI_SCSIIO_CONTROL_DATADIRECTION_MASK (0x03000000) +#define MPI_SCSIIO_CONTROL_NODATATRANSFER (0x00000000) +#define MPI_SCSIIO_CONTROL_WRITE (0x01000000) +#define MPI_SCSIIO_CONTROL_READ (0x02000000) + +#define MPI_SCSIIO_CONTROL_ADDCDBLEN_MASK (0x3C000000) +#define MPI_SCSIIO_CONTROL_ADDCDBLEN_SHIFT (26) + +#define MPI_SCSIIO_CONTROL_TASKATTRIBUTE_MASK (0x00000700) +#define MPI_SCSIIO_CONTROL_SIMPLEQ (0x00000000) +#define MPI_SCSIIO_CONTROL_HEADOFQ (0x00000100) +#define MPI_SCSIIO_CONTROL_ORDEREDQ (0x00000200) +#define MPI_SCSIIO_CONTROL_ACAQ (0x00000400) +#define MPI_SCSIIO_CONTROL_UNTAGGED (0x00000500) +#define MPI_SCSIIO_CONTROL_NO_DISCONNECT (0x00000700) + +#define MPI_SCSIIO_CONTROL_TASKMANAGE_MASK (0x00FF0000) +#define MPI_SCSIIO_CONTROL_OBSOLETE (0x00800000) +#define MPI_SCSIIO_CONTROL_CLEAR_ACA_RSV (0x00400000) +#define MPI_SCSIIO_CONTROL_TARGET_RESET (0x00200000) +#define MPI_SCSIIO_CONTROL_LUN_RESET_RSV (0x00100000) +#define MPI_SCSIIO_CONTROL_RESERVED (0x00080000) +#define MPI_SCSIIO_CONTROL_CLR_TASK_SET_RSV (0x00040000) +#define MPI_SCSIIO_CONTROL_ABORT_TASK_SET (0x00020000) +#define MPI_SCSIIO_CONTROL_RESERVED2 (0x00010000) + + +/* SCSI IO reply structure */ +typedef struct _MSG_SCSI_IO_REPLY +{ + U8 TargetID; /* 00h */ + U8 Bus; /* 01h */ + U8 MsgLength; /* 02h */ + U8 Function; /* 03h */ + U8 CDBLength; /* 04h */ + U8 SenseBufferLength; /* 05h */ + U8 Reserved; /* 06h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ + U8 SCSIStatus; /* 0Ch */ + U8 SCSIState; /* 0Dh */ + U16 IOCStatus; /* 0Eh */ + U32 IOCLogInfo; /* 10h */ + U32 TransferCount; /* 14h */ + U32 SenseCount; /* 18h */ + U32 ResponseInfo; /* 1Ch */ +} MSG_SCSI_IO_REPLY, MPI_POINTER PTR_MSG_SCSI_IO_REPLY, + SCSIIOReply_t, MPI_POINTER pSCSIIOReply_t; + + +/* SCSI IO Reply SCSIStatus values (SAM-2 status codes) */ + +#define MPI_SCSI_STATUS_SUCCESS (0x00) +#define MPI_SCSI_STATUS_CHECK_CONDITION (0x02) +#define MPI_SCSI_STATUS_CONDITION_MET (0x04) +#define MPI_SCSI_STATUS_BUSY (0x08) +#define MPI_SCSI_STATUS_INTERMEDIATE (0x10) +#define MPI_SCSI_STATUS_INTERMEDIATE_CONDMET (0x14) +#define MPI_SCSI_STATUS_RESERVATION_CONFLICT (0x18) +#define MPI_SCSI_STATUS_COMMAND_TERMINATED (0x22) +#define MPI_SCSI_STATUS_TASK_SET_FULL (0x28) +#define MPI_SCSI_STATUS_ACA_ACTIVE (0x30) + +#define MPI_SCSI_STATUS_FCPEXT_DEVICE_LOGGED_OUT (0x80) +#define MPI_SCSI_STATUS_FCPEXT_NO_LINK (0x81) + + +/* SCSI IO Reply SCSIState values */ + +#define MPI_SCSI_STATE_AUTOSENSE_VALID (0x01) +#define MPI_SCSI_STATE_AUTOSENSE_FAILED (0x02) +#define MPI_SCSI_STATE_NO_SCSI_STATUS (0x04) +#define MPI_SCSI_STATE_TERMINATED (0x08) +#define MPI_SCSI_STATE_RESPONSE_INFO_VALID (0x10) +#define MPI_SCSI_STATE_QUEUE_TAG_REJECTED (0x20) + +/* SCSI IO Reply ResponseInfo values */ +/* (FCP-1 RSP_CODE values and SPI-3 Packetized Failure codes) */ + +#define MPI_SCSI_RSP_INFO_FUNCTION_COMPLETE (0x00000000) +#define MPI_SCSI_RSP_INFO_FCP_BURST_LEN_ERROR (0x01000000) +#define MPI_SCSI_RSP_INFO_CMND_FIELDS_INVALID (0x02000000) +#define MPI_SCSI_RSP_INFO_FCP_DATA_RO_ERROR (0x03000000) +#define MPI_SCSI_RSP_INFO_TASK_MGMT_UNSUPPORTED (0x04000000) +#define MPI_SCSI_RSP_INFO_TASK_MGMT_FAILED (0x05000000) +#define MPI_SCSI_RSP_INFO_SPI_LQ_INVALID_TYPE (0x06000000) + + +/****************************************************************************/ +/* SCSI Task Management messages */ +/****************************************************************************/ + +typedef struct _MSG_SCSI_TASK_MGMT +{ + U8 TargetID; /* 00h */ + U8 Bus; /* 01h */ + U8 ChainOffset; /* 02h */ + U8 Function; /* 03h */ + U8 Reserved; /* 04h */ + U8 TaskType; /* 05h */ + U8 Reserved1; /* 06h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ + U8 LUN[8]; /* 0Ch */ + U32 Reserved2[7]; /* 14h */ + U32 TaskMsgContext; /* 30h */ +} MSG_SCSI_TASK_MGMT, MPI_POINTER PTR_SCSI_TASK_MGMT, + SCSITaskMgmt_t, MPI_POINTER pSCSITaskMgmt_t; + +/* TaskType values */ + +#define MPI_SCSITASKMGMT_TASKTYPE_ABORT_TASK (0x01) +#define MPI_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET (0x02) +#define MPI_SCSITASKMGMT_TASKTYPE_TARGET_RESET (0x03) +#define MPI_SCSITASKMGMT_TASKTYPE_RESET_BUS (0x04) +#define MPI_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET (0x05) + +/* MsgFlags bits */ +#define MPI_SCSITASKMGMT_MSGFLAGS_TARGET_RESET_OPTION (0x00) +#define MPI_SCSITASKMGMT_MSGFLAGS_LIP_RESET_OPTION (0x02) +#define MPI_SCSITASKMGMT_MSGFLAGS_LIPRESET_RESET_OPTION (0x04) + +/* SCSI Task Management Reply */ +typedef struct _MSG_SCSI_TASK_MGMT_REPLY +{ + U8 TargetID; /* 00h */ + U8 Bus; /* 01h */ + U8 MsgLength; /* 02h */ + U8 Function; /* 03h */ + U8 Reserved; /* 04h */ + U8 TaskType; /* 05h */ + U8 Reserved1; /* 06h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ + U8 Reserved2[2]; /* 0Ch */ + U16 IOCStatus; /* 0Eh */ + U32 IOCLogInfo; /* 10h */ + U32 TerminationCount; /* 14h */ +} MSG_SCSI_TASK_MGMT_REPLY, MPI_POINTER PTR_MSG_SCSI_TASK_MGMT_REPLY, + SCSITaskMgmtReply_t, MPI_POINTER pSCSITaskMgmtReply_t; + + +/****************************************************************************/ +/* SCSI Enclosure Processor messages */ +/****************************************************************************/ + +typedef struct _MSG_SEP_REQUEST +{ + U8 TargetID; /* 00h */ + U8 Bus; /* 01h */ + U8 ChainOffset; /* 02h */ + U8 Function; /* 03h */ + U8 Action; /* 04h */ + U8 Reserved1; /* 05h */ + U8 Reserved2; /* 06h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ + U32 SlotStatus; /* 0Ch */ +} MSG_SEP_REQUEST, MPI_POINTER PTR_MSG_SEP_REQUEST, + SEPRequest_t, MPI_POINTER pSEPRequest_t; + +/* Action defines */ +#define MPI_SEP_REQ_ACTION_WRITE_STATUS (0x00) +#define MPI_SEP_REQ_ACTION_READ_STATUS (0x01) + +/* SlotStatus bits for MSG_SEP_REQUEST */ +#define MPI_SEP_REQ_SLOTSTATUS_NO_ERROR (0x00000001) +#define MPI_SEP_REQ_SLOTSTATUS_DEV_FAULTY (0x00000002) +#define MPI_SEP_REQ_SLOTSTATUS_DEV_REBUILDING (0x00000004) +#define MPI_SEP_REQ_SLOTSTATUS_IN_FAILED_ARRAY (0x00000008) +#define MPI_SEP_REQ_SLOTSTATUS_IN_CRITICAL_ARRAY (0x00000010) +#define MPI_SEP_REQ_SLOTSTATUS_PARITY_CHECK (0x00000020) +#define MPI_SEP_REQ_SLOTSTATUS_PREDICTED_FAULT (0x00000040) +#define MPI_SEP_REQ_SLOTSTATUS_UNCONFIGURED (0x00000080) +#define MPI_SEP_REQ_SLOTSTATUS_HOT_SPARE (0x00000100) +#define MPI_SEP_REQ_SLOTSTATUS_REBUILD_STOPPED (0x00000200) +#define MPI_SEP_REQ_SLOTSTATUS_IDENTIFY_REQUEST (0x00020000) +#define MPI_SEP_REQ_SLOTSTATUS_REQUEST_REMOVE (0x00040000) +#define MPI_SEP_REQ_SLOTSTATUS_REQUEST_INSERT (0x00080000) +#define MPI_SEP_REQ_SLOTSTATUS_DO_NOT_MOVE (0x00400000) +#define MPI_SEP_REQ_SLOTSTATUS_B_ENABLE_BYPASS (0x04000000) +#define MPI_SEP_REQ_SLOTSTATUS_A_ENABLE_BYPASS (0x08000000) +#define MPI_SEP_REQ_SLOTSTATUS_DEV_OFF (0x10000000) +#define MPI_SEP_REQ_SLOTSTATUS_SWAP_RESET (0x80000000) + + +typedef struct _MSG_SEP_REPLY +{ + U8 TargetID; /* 00h */ + U8 Bus; /* 01h */ + U8 MsgLength; /* 02h */ + U8 Function; /* 03h */ + U8 Action; /* 04h */ + U8 Reserved1; /* 05h */ + U8 Reserved2; /* 06h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ + U16 Reserved3; /* 0Ch */ + U16 IOCStatus; /* 0Eh */ + U32 IOCLogInfo; /* 10h */ + U32 SlotStatus; /* 14h */ +} MSG_SEP_REPLY, MPI_POINTER PTR_MSG_SEP_REPLY, + SEPReply_t, MPI_POINTER pSEPReply_t; + +/* SlotStatus bits for MSG_SEP_REPLY */ +#define MPI_SEP_REPLY_SLOTSTATUS_NO_ERROR (0x00000001) +#define MPI_SEP_REPLY_SLOTSTATUS_DEV_FAULTY (0x00000002) +#define MPI_SEP_REPLY_SLOTSTATUS_DEV_REBUILDING (0x00000004) +#define MPI_SEP_REPLY_SLOTSTATUS_IN_FAILED_ARRAY (0x00000008) +#define MPI_SEP_REPLY_SLOTSTATUS_IN_CRITICAL_ARRAY (0x00000010) +#define MPI_SEP_REPLY_SLOTSTATUS_PARITY_CHECK (0x00000020) +#define MPI_SEP_REPLY_SLOTSTATUS_PREDICTED_FAULT (0x00000040) +#define MPI_SEP_REPLY_SLOTSTATUS_UNCONFIGURED (0x00000080) +#define MPI_SEP_REPLY_SLOTSTATUS_HOT_SPARE (0x00000100) +#define MPI_SEP_REPLY_SLOTSTATUS_REBUILD_STOPPED (0x00000200) +#define MPI_SEP_REPLY_SLOTSTATUS_REPORT (0x00010000) +#define MPI_SEP_REPLY_SLOTSTATUS_IDENTIFY_REQUEST (0x00020000) +#define MPI_SEP_REPLY_SLOTSTATUS_REMOVE_READY (0x00040000) +#define MPI_SEP_REPLY_SLOTSTATUS_INSERT_READY (0x00080000) +#define MPI_SEP_REPLY_SLOTSTATUS_DO_NOT_REMOVE (0x00400000) +#define MPI_SEP_REPLY_SLOTSTATUS_B_BYPASS_ENABLED (0x01000000) +#define MPI_SEP_REPLY_SLOTSTATUS_A_BYPASS_ENABLED (0x02000000) +#define MPI_SEP_REPLY_SLOTSTATUS_B_ENABLE_BYPASS (0x04000000) +#define MPI_SEP_REPLY_SLOTSTATUS_A_ENABLE_BYPASS (0x08000000) +#define MPI_SEP_REPLY_SLOTSTATUS_DEV_OFF (0x10000000) +#define MPI_SEP_REPLY_SLOTSTATUS_FAULT_SENSED (0x40000000) +#define MPI_SEP_REPLY_SLOTSTATUS_SWAPPED (0x80000000) + +#endif diff --git a/sys/dev/mpt/mpilib/mpi_ioc.h b/sys/dev/mpt/mpilib/mpi_ioc.h new file mode 100644 index 0000000..e2e8f43 --- /dev/null +++ b/sys/dev/mpt/mpilib/mpi_ioc.h @@ -0,0 +1,725 @@ +/* $FreeBSD$ */ +/* + * Copyright (c) 2000, 2001 by LSI Logic Corporation + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice immediately at the beginning of the file, without modification, + * this list of conditions, and the following disclaimer. + * 2. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * + * Name: MPI_IOC.H + * Title: MPI IOC, Port, Event, FW Download, and FW Upload messages + * Creation Date: August 11, 2000 + * + * MPI_IOC.H Version: 01.02.07 + * + * Version History + * --------------- + * + * Date Version Description + * -------- -------- ------------------------------------------------------ + * 05-08-00 00.10.01 Original release for 0.10 spec dated 4/26/2000. + * 05-24-00 00.10.02 Added _MSG_IOC_INIT_REPLY structure. + * 06-06-00 01.00.01 Added CurReplyFrameSize field to _MSG_IOC_FACTS_REPLY. + * 06-12-00 01.00.02 Added _MSG_PORT_ENABLE_REPLY structure. + * Added _MSG_EVENT_ACK_REPLY structure. + * Added _MSG_FW_DOWNLOAD_REPLY structure. + * Added _MSG_TOOLBOX_REPLY structure. + * 06-30-00 01.00.03 Added MaxLanBuckets to _PORT_FACT_REPLY structure. + * 07-27-00 01.00.04 Added _EVENT_DATA structure definitions for _SCSI, + * _LINK_STATUS, _LOOP_STATE and _LOGOUT. + * 08-11-00 01.00.05 Switched positions of MsgLength and Function fields in + * _MSG_EVENT_ACK_REPLY structure to match specification. + * 11-02-00 01.01.01 Original release for post 1.0 work. + * Added a value for Manufacturer to WhoInit. + * 12-04-00 01.01.02 Modified IOCFacts reply, added FWUpload messages, and + * removed toolbox message. + * 01-09-01 01.01.03 Added event enabled and disabled defines. + * Added structures for FwHeader and DataHeader. + * Added ImageType to FwUpload reply. + * 02-20-01 01.01.04 Started using MPI_POINTER. + * 02-27-01 01.01.05 Added event for RAID status change and its event data. + * Added IocNumber field to MSG_IOC_FACTS_REPLY. + * 03-27-01 01.01.06 Added defines for ProductId field of MPI_FW_HEADER. + * Added structure offset comments. + * 04-09-01 01.01.07 Added structure EVENT_DATA_EVENT_CHANGE. + * 08-08-01 01.02.01 Original release for v1.2 work. + * New format for FWVersion and ProductId in + * MSG_IOC_FACTS_REPLY and MPI_FW_HEADER. + * 08-31-01 01.02.02 Addded event MPI_EVENT_SCSI_DEVICE_STATUS_CHANGE and + * related structure and defines. + * Added event MPI_EVENT_ON_BUS_TIMER_EXPIRED. + * Added MPI_IOCINIT_FLAGS_DISCARD_FW_IMAGE. + * Replaced a reserved field in MSG_IOC_FACTS_REPLY with + * IOCExceptions and changed DataImageSize to reserved. + * Added MPI_FW_DOWNLOAD_ITYPE_NVSTORE_DATA and + * MPI_FW_UPLOAD_ITYPE_NVDATA. + * 09-28-01 01.02.03 Modified Event Data for Integrated RAID. + * 11-01-01 01.02.04 Added defines for MPI_EXT_IMAGE_HEADER ImageType field. + * 03-14-02 01.02.05 Added HeaderVersion field to MSG_IOC_FACTS_REPLY. + * 05-31-02 01.02.06 Added define for + * MPI_IOCFACTS_EXCEPT_RAID_CONFIG_INVALID. + * Added AliasIndex to EVENT_DATA_LOGOUT structure. + * 04-01-03 01.02.07 Added defines for MPI_FW_HEADER_SIGNATURE_. + * -------------------------------------------------------------------------- + */ + +#ifndef MPI_IOC_H +#define MPI_IOC_H + + +/***************************************************************************** +* +* I O C M e s s a g e s +* +*****************************************************************************/ + +/****************************************************************************/ +/* IOCInit message */ +/****************************************************************************/ + +typedef struct _MSG_IOC_INIT +{ + U8 WhoInit; /* 00h */ + U8 Reserved; /* 01h */ + U8 ChainOffset; /* 02h */ + U8 Function; /* 03h */ + U8 Flags; /* 04h */ + U8 MaxDevices; /* 05h */ + U8 MaxBuses; /* 06h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ + U16 ReplyFrameSize; /* 0Ch */ + U8 Reserved1[2]; /* 0Eh */ + U32 HostMfaHighAddr; /* 10h */ + U32 SenseBufferHighAddr; /* 14h */ +} MSG_IOC_INIT, MPI_POINTER PTR_MSG_IOC_INIT, + IOCInit_t, MPI_POINTER pIOCInit_t; + +/* WhoInit values */ +#define MPI_WHOINIT_NO_ONE (0x00) +#define MPI_WHOINIT_SYSTEM_BIOS (0x01) +#define MPI_WHOINIT_ROM_BIOS (0x02) +#define MPI_WHOINIT_PCI_PEER (0x03) +#define MPI_WHOINIT_HOST_DRIVER (0x04) +#define MPI_WHOINIT_MANUFACTURER (0x05) + +/* Flags values */ +#define MPI_IOCINIT_FLAGS_DISCARD_FW_IMAGE (0x01) + +typedef struct _MSG_IOC_INIT_REPLY +{ + U8 WhoInit; /* 00h */ + U8 Reserved; /* 01h */ + U8 MsgLength; /* 02h */ + U8 Function; /* 03h */ + U8 Flags; /* 04h */ + U8 MaxDevices; /* 05h */ + U8 MaxBuses; /* 06h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ + U16 Reserved2; /* 0Ch */ + U16 IOCStatus; /* 0Eh */ + U32 IOCLogInfo; /* 10h */ +} MSG_IOC_INIT_REPLY, MPI_POINTER PTR_MSG_IOC_INIT_REPLY, + IOCInitReply_t, MPI_POINTER pIOCInitReply_t; + + + +/****************************************************************************/ +/* IOC Facts message */ +/****************************************************************************/ + +typedef struct _MSG_IOC_FACTS +{ + U8 Reserved[2]; /* 00h */ + U8 ChainOffset; /* 01h */ + U8 Function; /* 02h */ + U8 Reserved1[3]; /* 03h */ + U8 MsgFlags; /* 04h */ + U32 MsgContext; /* 08h */ +} MSG_IOC_FACTS, MPI_POINTER PTR_IOC_FACTS, + IOCFacts_t, MPI_POINTER pIOCFacts_t; + +typedef struct _MPI_FW_VERSION_STRUCT +{ + U8 Dev; /* 00h */ + U8 Unit; /* 01h */ + U8 Minor; /* 02h */ + U8 Major; /* 03h */ +} MPI_FW_VERSION_STRUCT; + +typedef union _MPI_FW_VERSION +{ + MPI_FW_VERSION_STRUCT Struct; + U32 Word; +} MPI_FW_VERSION; + +/* IOC Facts Reply */ +typedef struct _MSG_IOC_FACTS_REPLY +{ + U16 MsgVersion; /* 00h */ + U8 MsgLength; /* 02h */ + U8 Function; /* 03h */ + U16 HeaderVersion; /* 04h */ + U8 IOCNumber; /* 06h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ + U16 IOCExceptions; /* 0Ch */ + U16 IOCStatus; /* 0Eh */ + U32 IOCLogInfo; /* 10h */ + U8 MaxChainDepth; /* 14h */ + U8 WhoInit; /* 15h */ + U8 BlockSize; /* 16h */ + U8 Flags; /* 17h */ + U16 ReplyQueueDepth; /* 18h */ + U16 RequestFrameSize; /* 1Ah */ + U16 Reserved_0101_FWVersion; /* 1Ch */ /* obsolete 16-bit FWVersion */ + U16 ProductID; /* 1Eh */ + U32 CurrentHostMfaHighAddr; /* 20h */ + U16 GlobalCredits; /* 24h */ + U8 NumberOfPorts; /* 26h */ + U8 EventState; /* 27h */ + U32 CurrentSenseBufferHighAddr; /* 28h */ + U16 CurReplyFrameSize; /* 2Ch */ + U8 MaxDevices; /* 2Eh */ + U8 MaxBuses; /* 2Fh */ + U32 FWImageSize; /* 30h */ + U32 Reserved4; /* 34h */ + MPI_FW_VERSION FWVersion; /* 38h */ +} MSG_IOC_FACTS_REPLY, MPI_POINTER PTR_MSG_IOC_FACTS_REPLY, + IOCFactsReply_t, MPI_POINTER pIOCFactsReply_t; + +#define MPI_IOCFACTS_MSGVERSION_MAJOR_MASK (0xFF00) +#define MPI_IOCFACTS_MSGVERSION_MINOR_MASK (0x00FF) + +#define MPI_IOCFACTS_HEADERVERSION_UNIT_MASK (0xFF00) +#define MPI_IOCFACTS_HEADERVERSION_DEV_MASK (0x00FF) + +#define MPI_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL (0x0001) +#define MPI_IOCFACTS_EXCEPT_RAID_CONFIG_INVALID (0x0002) + +#define MPI_IOCFACTS_FLAGS_FW_DOWNLOAD_BOOT (0x01) + +#define MPI_IOCFACTS_EVENTSTATE_DISABLED (0x00) +#define MPI_IOCFACTS_EVENTSTATE_ENABLED (0x01) + + + +/***************************************************************************** +* +* P o r t M e s s a g e s +* +*****************************************************************************/ + +/****************************************************************************/ +/* Port Facts message and Reply */ +/****************************************************************************/ + +typedef struct _MSG_PORT_FACTS +{ + U8 Reserved[2]; /* 00h */ + U8 ChainOffset; /* 02h */ + U8 Function; /* 03h */ + U8 Reserved1[2]; /* 04h */ + U8 PortNumber; /* 06h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ +} MSG_PORT_FACTS, MPI_POINTER PTR_MSG_PORT_FACTS, + PortFacts_t, MPI_POINTER pPortFacts_t; + +typedef struct _MSG_PORT_FACTS_REPLY +{ + U16 Reserved; /* 00h */ + U8 MsgLength; /* 02h */ + U8 Function; /* 03h */ + U16 Reserved1; /* 04h */ + U8 PortNumber; /* 06h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ + U16 Reserved2; /* 0Ch */ + U16 IOCStatus; /* 0Eh */ + U32 IOCLogInfo; /* 10h */ + U8 Reserved3; /* 14h */ + U8 PortType; /* 15h */ + U16 MaxDevices; /* 16h */ + U16 PortSCSIID; /* 18h */ + U16 ProtocolFlags; /* 1Ah */ + U16 MaxPostedCmdBuffers; /* 1Ch */ + U16 MaxPersistentIDs; /* 1Eh */ + U16 MaxLanBuckets; /* 20h */ + U16 Reserved4; /* 22h */ + U32 Reserved5; /* 24h */ +} MSG_PORT_FACTS_REPLY, MPI_POINTER PTR_MSG_PORT_FACTS_REPLY, + PortFactsReply_t, MPI_POINTER pPortFactsReply_t; + + +/* PortTypes values */ + +#define MPI_PORTFACTS_PORTTYPE_INACTIVE (0x00) +#define MPI_PORTFACTS_PORTTYPE_SCSI (0x01) +#define MPI_PORTFACTS_PORTTYPE_FC (0x10) + +/* ProtocolFlags values */ + +#define MPI_PORTFACTS_PROTOCOL_LOGBUSADDR (0x01) +#define MPI_PORTFACTS_PROTOCOL_LAN (0x02) +#define MPI_PORTFACTS_PROTOCOL_TARGET (0x04) +#define MPI_PORTFACTS_PROTOCOL_INITIATOR (0x08) + + +/****************************************************************************/ +/* Port Enable Message */ +/****************************************************************************/ + +typedef struct _MSG_PORT_ENABLE +{ + U8 Reserved[2]; /* 00h */ + U8 ChainOffset; /* 02h */ + U8 Function; /* 03h */ + U8 Reserved1[2]; /* 04h */ + U8 PortNumber; /* 06h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ +} MSG_PORT_ENABLE, MPI_POINTER PTR_MSG_PORT_ENABLE, + PortEnable_t, MPI_POINTER pPortEnable_t; + +typedef struct _MSG_PORT_ENABLE_REPLY +{ + U8 Reserved[2]; /* 00h */ + U8 MsgLength; /* 02h */ + U8 Function; /* 03h */ + U8 Reserved1[2]; /* 04h */ + U8 PortNumber; /* 05h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ + U16 Reserved2; /* 0Ch */ + U16 IOCStatus; /* 0Eh */ + U32 IOCLogInfo; /* 10h */ +} MSG_PORT_ENABLE_REPLY, MPI_POINTER PTR_MSG_PORT_ENABLE_REPLY, + PortEnableReply_t, MPI_POINTER pPortEnableReply_t; + + +/***************************************************************************** +* +* E v e n t M e s s a g e s +* +*****************************************************************************/ + +/****************************************************************************/ +/* Event Notification messages */ +/****************************************************************************/ + +typedef struct _MSG_EVENT_NOTIFY +{ + U8 Switch; /* 00h */ + U8 Reserved; /* 01h */ + U8 ChainOffset; /* 02h */ + U8 Function; /* 03h */ + U8 Reserved1[3]; /* 04h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ +} MSG_EVENT_NOTIFY, MPI_POINTER PTR_MSG_EVENT_NOTIFY, + EventNotification_t, MPI_POINTER pEventNotification_t; + +/* Event Notification Reply */ + +typedef struct _MSG_EVENT_NOTIFY_REPLY +{ + U16 EventDataLength; /* 00h */ + U8 MsgLength; /* 02h */ + U8 Function; /* 03h */ + U8 Reserved1[2]; /* 04h */ + U8 AckRequired; /* 06h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ + U8 Reserved2[2]; /* 0Ch */ + U16 IOCStatus; /* 0Eh */ + U32 IOCLogInfo; /* 10h */ + U32 Event; /* 14h */ + U32 EventContext; /* 18h */ + U32 Data[1]; /* 1Ch */ +} MSG_EVENT_NOTIFY_REPLY, MPI_POINTER PTR_MSG_EVENT_NOTIFY_REPLY, + EventNotificationReply_t, MPI_POINTER pEventNotificationReply_t; + +/* Event Acknowledge */ + +typedef struct _MSG_EVENT_ACK +{ + U8 Reserved[2]; /* 00h */ + U8 ChainOffset; /* 02h */ + U8 Function; /* 03h */ + U8 Reserved1[3]; /* 04h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ + U32 Event; /* 0Ch */ + U32 EventContext; /* 10h */ +} MSG_EVENT_ACK, MPI_POINTER PTR_MSG_EVENT_ACK, + EventAck_t, MPI_POINTER pEventAck_t; + +typedef struct _MSG_EVENT_ACK_REPLY +{ + U8 Reserved[2]; /* 00h */ + U8 MsgLength; /* 02h */ + U8 Function; /* 03h */ + U8 Reserved1[3]; /* 04h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ + U16 Reserved2; /* 0Ch */ + U16 IOCStatus; /* 0Eh */ + U32 IOCLogInfo; /* 10h */ +} MSG_EVENT_ACK_REPLY, MPI_POINTER PTR_MSG_EVENT_ACK_REPLY, + EventAckReply_t, MPI_POINTER pEventAckReply_t; + +/* Switch */ + +#define MPI_EVENT_NOTIFICATION_SWITCH_OFF (0x00) +#define MPI_EVENT_NOTIFICATION_SWITCH_ON (0x01) + +/* Event */ + +#define MPI_EVENT_NONE (0x00000000) +#define MPI_EVENT_LOG_DATA (0x00000001) +#define MPI_EVENT_STATE_CHANGE (0x00000002) +#define MPI_EVENT_UNIT_ATTENTION (0x00000003) +#define MPI_EVENT_IOC_BUS_RESET (0x00000004) +#define MPI_EVENT_EXT_BUS_RESET (0x00000005) +#define MPI_EVENT_RESCAN (0x00000006) +#define MPI_EVENT_LINK_STATUS_CHANGE (0x00000007) +#define MPI_EVENT_LOOP_STATE_CHANGE (0x00000008) +#define MPI_EVENT_LOGOUT (0x00000009) +#define MPI_EVENT_EVENT_CHANGE (0x0000000A) +#define MPI_EVENT_INTEGRATED_RAID (0x0000000B) +#define MPI_EVENT_SCSI_DEVICE_STATUS_CHANGE (0x0000000C) +#define MPI_EVENT_ON_BUS_TIMER_EXPIRED (0x0000000D) + +/* AckRequired field values */ + +#define MPI_EVENT_NOTIFICATION_ACK_NOT_REQUIRED (0x00) +#define MPI_EVENT_NOTIFICATION_ACK_REQUIRED (0x01) + +/* EventChange Event data */ + +typedef struct _EVENT_DATA_EVENT_CHANGE +{ + U8 EventState; /* 00h */ + U8 Reserved; /* 01h */ + U16 Reserved1; /* 02h */ +} EVENT_DATA_EVENT_CHANGE, MPI_POINTER PTR_EVENT_DATA_EVENT_CHANGE, + EventDataEventChange_t, MPI_POINTER pEventDataEventChange_t; + +/* SCSI Event data for Port, Bus and Device forms */ + +typedef struct _EVENT_DATA_SCSI +{ + U8 TargetID; /* 00h */ + U8 BusPort; /* 01h */ + U16 Reserved; /* 02h */ +} EVENT_DATA_SCSI, MPI_POINTER PTR_EVENT_DATA_SCSI, + EventDataScsi_t, MPI_POINTER pEventDataScsi_t; + +/* SCSI Device Status Change Event data */ + +typedef struct _EVENT_DATA_SCSI_DEVICE_STATUS_CHANGE +{ + U8 TargetID; /* 00h */ + U8 Bus; /* 01h */ + U8 ReasonCode; /* 02h */ + U8 LUN; /* 03h */ + U8 ASC; /* 04h */ + U8 ASCQ; /* 05h */ + U16 Reserved; /* 06h */ +} EVENT_DATA_SCSI_DEVICE_STATUS_CHANGE, + MPI_POINTER PTR_EVENT_DATA_SCSI_DEVICE_STATUS_CHANGE, + MpiEventDataScsiDeviceStatusChange_t, + MPI_POINTER pMpiEventDataScsiDeviceStatusChange_t; + +/* MPI SCSI Device Status Change Event data ReasonCode values */ +#define MPI_EVENT_SCSI_DEV_STAT_RC_ADDED (0x03) +#define MPI_EVENT_SCSI_DEV_STAT_RC_NOT_RESPONDING (0x04) +#define MPI_EVENT_SCSI_DEV_STAT_RC_SMART_DATA (0x05) + +/* MPI Link Status Change Event data */ + +typedef struct _EVENT_DATA_LINK_STATUS +{ + U8 State; /* 00h */ + U8 Reserved; /* 01h */ + U16 Reserved1; /* 02h */ + U8 Reserved2; /* 04h */ + U8 Port; /* 05h */ + U16 Reserved3; /* 06h */ +} EVENT_DATA_LINK_STATUS, MPI_POINTER PTR_EVENT_DATA_LINK_STATUS, + EventDataLinkStatus_t, MPI_POINTER pEventDataLinkStatus_t; + +#define MPI_EVENT_LINK_STATUS_FAILURE (0x00000000) +#define MPI_EVENT_LINK_STATUS_ACTIVE (0x00000001) + +/* MPI Loop State Change Event data */ + +typedef struct _EVENT_DATA_LOOP_STATE +{ + U8 Character4; /* 00h */ + U8 Character3; /* 01h */ + U8 Type; /* 02h */ + U8 Reserved; /* 03h */ + U8 Reserved1; /* 04h */ + U8 Port; /* 05h */ + U16 Reserved2; /* 06h */ +} EVENT_DATA_LOOP_STATE, MPI_POINTER PTR_EVENT_DATA_LOOP_STATE, + EventDataLoopState_t, MPI_POINTER pEventDataLoopState_t; + +#define MPI_EVENT_LOOP_STATE_CHANGE_LIP (0x0001) +#define MPI_EVENT_LOOP_STATE_CHANGE_LPE (0x0002) +#define MPI_EVENT_LOOP_STATE_CHANGE_LPB (0x0003) + +/* MPI LOGOUT Event data */ + +typedef struct _EVENT_DATA_LOGOUT +{ + U32 NPortID; /* 00h */ + U8 AliasIndex; /* 04h */ + U8 Port; /* 05h */ + U16 Reserved1; /* 06h */ +} EVENT_DATA_LOGOUT, MPI_POINTER PTR_EVENT_DATA_LOGOUT, + EventDataLogout_t, MPI_POINTER pEventDataLogout_t; + +#define MPI_EVENT_LOGOUT_ALL_ALIASES (0xFF) + + +/* MPI Integrated RAID Event data */ + +typedef struct _EVENT_DATA_RAID +{ + U8 VolumeID; /* 00h */ + U8 VolumeBus; /* 01h */ + U8 ReasonCode; /* 02h */ + U8 PhysDiskNum; /* 03h */ + U8 ASC; /* 04h */ + U8 ASCQ; /* 05h */ + U16 Reserved; /* 06h */ + U32 SettingsStatus; /* 08h */ +} EVENT_DATA_RAID, MPI_POINTER PTR_EVENT_DATA_RAID, + MpiEventDataRaid_t, MPI_POINTER pMpiEventDataRaid_t; + +/* MPI Integrated RAID Event data ReasonCode values */ +#define MPI_EVENT_RAID_RC_VOLUME_CREATED (0x00) +#define MPI_EVENT_RAID_RC_VOLUME_DELETED (0x01) +#define MPI_EVENT_RAID_RC_VOLUME_SETTINGS_CHANGED (0x02) +#define MPI_EVENT_RAID_RC_VOLUME_STATUS_CHANGED (0x03) +#define MPI_EVENT_RAID_RC_VOLUME_PHYSDISK_CHANGED (0x04) +#define MPI_EVENT_RAID_RC_PHYSDISK_CREATED (0x05) +#define MPI_EVENT_RAID_RC_PHYSDISK_DELETED (0x06) +#define MPI_EVENT_RAID_RC_PHYSDISK_SETTINGS_CHANGED (0x07) +#define MPI_EVENT_RAID_RC_PHYSDISK_STATUS_CHANGED (0x08) +#define MPI_EVENT_RAID_RC_DOMAIN_VAL_NEEDED (0x09) +#define MPI_EVENT_RAID_RC_SMART_DATA (0x0A) +#define MPI_EVENT_RAID_RC_REPLACE_ACTION_STARTED (0x0B) + + +/***************************************************************************** +* +* F i r m w a r e L o a d M e s s a g e s +* +*****************************************************************************/ + +/****************************************************************************/ +/* Firmware Download message and associated structures */ +/****************************************************************************/ + +typedef struct _MSG_FW_DOWNLOAD +{ + U8 ImageType; /* 00h */ + U8 Reserved; /* 01h */ + U8 ChainOffset; /* 02h */ + U8 Function; /* 03h */ + U8 Reserved1[3]; /* 04h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ + SGE_MPI_UNION SGL; /* 0Ch */ +} MSG_FW_DOWNLOAD, MPI_POINTER PTR_MSG_FW_DOWNLOAD, + FWDownload_t, MPI_POINTER pFWDownload_t; + +#define MPI_FW_DOWNLOAD_ITYPE_RESERVED (0x00) +#define MPI_FW_DOWNLOAD_ITYPE_FW (0x01) +#define MPI_FW_DOWNLOAD_ITYPE_BIOS (0x02) +#define MPI_FW_DOWNLOAD_ITYPE_NVDATA (0x03) + + +typedef struct _FWDownloadTCSGE +{ + U8 Reserved; /* 00h */ + U8 ContextSize; /* 01h */ + U8 DetailsLength; /* 02h */ + U8 Flags; /* 03h */ + U32 Reserved_0100_Checksum; /* 04h */ /* obsolete Checksum */ + U32 ImageOffset; /* 08h */ + U32 ImageSize; /* 0Ch */ +} FW_DOWNLOAD_TCSGE, MPI_POINTER PTR_FW_DOWNLOAD_TCSGE, + FWDownloadTCSGE_t, MPI_POINTER pFWDownloadTCSGE_t; + +/* Firmware Download reply */ +typedef struct _MSG_FW_DOWNLOAD_REPLY +{ + U8 ImageType; /* 00h */ + U8 Reserved; /* 01h */ + U8 MsgLength; /* 02h */ + U8 Function; /* 03h */ + U8 Reserved1[3]; /* 04h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ + U16 Reserved2; /* 0Ch */ + U16 IOCStatus; /* 0Eh */ + U32 IOCLogInfo; /* 10h */ +} MSG_FW_DOWNLOAD_REPLY, MPI_POINTER PTR_MSG_FW_DOWNLOAD_REPLY, + FWDownloadReply_t, MPI_POINTER pFWDownloadReply_t; + + +/****************************************************************************/ +/* Firmware Upload message and associated structures */ +/****************************************************************************/ + +typedef struct _MSG_FW_UPLOAD +{ + U8 ImageType; /* 00h */ + U8 Reserved; /* 01h */ + U8 ChainOffset; /* 02h */ + U8 Function; /* 03h */ + U8 Reserved1[3]; /* 04h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ + SGE_MPI_UNION SGL; /* 0Ch */ +} MSG_FW_UPLOAD, MPI_POINTER PTR_MSG_FW_UPLOAD, + FWUpload_t, MPI_POINTER pFWUpload_t; + +#define MPI_FW_UPLOAD_ITYPE_FW_IOC_MEM (0x00) +#define MPI_FW_UPLOAD_ITYPE_FW_FLASH (0x01) +#define MPI_FW_UPLOAD_ITYPE_BIOS_FLASH (0x02) +#define MPI_FW_UPLOAD_ITYPE_NVDATA (0x03) + +typedef struct _FWUploadTCSGE +{ + U8 Reserved; /* 00h */ + U8 ContextSize; /* 01h */ + U8 DetailsLength; /* 02h */ + U8 Flags; /* 03h */ + U32 Reserved1; /* 04h */ + U32 ImageOffset; /* 08h */ + U32 ImageSize; /* 0Ch */ +} FW_UPLOAD_TCSGE, MPI_POINTER PTR_FW_UPLOAD_TCSGE, + FWUploadTCSGE_t, MPI_POINTER pFWUploadTCSGE_t; + +/* Firmware Upload reply */ +typedef struct _MSG_FW_UPLOAD_REPLY +{ + U8 ImageType; /* 00h */ + U8 Reserved; /* 01h */ + U8 MsgLength; /* 02h */ + U8 Function; /* 03h */ + U8 Reserved1[3]; /* 04h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ + U16 Reserved2; /* 0Ch */ + U16 IOCStatus; /* 0Eh */ + U32 IOCLogInfo; /* 10h */ + U32 ActualImageSize; /* 14h */ +} MSG_FW_UPLOAD_REPLY, MPI_POINTER PTR_MSG_FW_UPLOAD_REPLY, + FWUploadReply_t, MPI_POINTER pFWUploadReply_t; + + +typedef struct _MPI_FW_HEADER +{ + U32 ArmBranchInstruction0; /* 00h */ + U32 Signature0; /* 04h */ + U32 Signature1; /* 08h */ + U32 Signature2; /* 0Ch */ + U32 ArmBranchInstruction1; /* 10h */ + U32 ArmBranchInstruction2; /* 14h */ + U32 Reserved; /* 18h */ + U32 Checksum; /* 1Ch */ + U16 VendorId; /* 20h */ + U16 ProductId; /* 22h */ + MPI_FW_VERSION FWVersion; /* 24h */ + U32 SeqCodeVersion; /* 28h */ + U32 ImageSize; /* 2Ch */ + U32 NextImageHeaderOffset; /* 30h */ + U32 LoadStartAddress; /* 34h */ + U32 IopResetVectorValue; /* 38h */ + U32 IopResetRegAddr; /* 3Ch */ + U32 VersionNameWhat; /* 40h */ + U8 VersionName[32]; /* 44h */ + U32 VendorNameWhat; /* 64h */ + U8 VendorName[32]; /* 68h */ +} MPI_FW_HEADER, MPI_POINTER PTR_MPI_FW_HEADER, + MpiFwHeader_t, MPI_POINTER pMpiFwHeader_t; + +#define MPI_FW_HEADER_WHAT_SIGNATURE (0x29232840) + +/* defines for using the ProductId field */ +#define MPI_FW_HEADER_PID_TYPE_MASK (0xF000) +#define MPI_FW_HEADER_PID_TYPE_SCSI (0x0000) +#define MPI_FW_HEADER_PID_TYPE_FC (0x1000) + +#define MPI_FW_HEADER_SIGNATURE_0 (0x5AEAA55A) +#define MPI_FW_HEADER_SIGNATURE_1 (0xA55AEAA5) +#define MPI_FW_HEADER_SIGNATURE_2 (0x5AA55AEA) + +#define MPI_FW_HEADER_PID_PROD_MASK (0x0F00) +#define MPI_FW_HEADER_PID_PROD_INITIATOR_SCSI (0x0100) +#define MPI_FW_HEADER_PID_PROD_TARGET_INITIATOR_SCSI (0x0200) +#define MPI_FW_HEADER_PID_PROD_TARGET_SCSI (0x0300) +#define MPI_FW_HEADER_PID_PROD_IM_SCSI (0x0400) +#define MPI_FW_HEADER_PID_PROD_IS_SCSI (0x0500) +#define MPI_FW_HEADER_PID_PROD_CTX_SCSI (0x0600) + +#define MPI_FW_HEADER_PID_FAMILY_MASK (0x00FF) +#define MPI_FW_HEADER_PID_FAMILY_1030A0_SCSI (0x0001) +#define MPI_FW_HEADER_PID_FAMILY_1030B0_SCSI (0x0002) +#define MPI_FW_HEADER_PID_FAMILY_1030B1_SCSI (0x0003) +#define MPI_FW_HEADER_PID_FAMILY_1030C0_SCSI (0x0004) +#define MPI_FW_HEADER_PID_FAMILY_1020A0_SCSI (0x0005) +#define MPI_FW_HEADER_PID_FAMILY_1020B0_SCSI (0x0006) +#define MPI_FW_HEADER_PID_FAMILY_1020B1_SCSI (0x0007) +#define MPI_FW_HEADER_PID_FAMILY_1020C0_SCSI (0x0008) +#define MPI_FW_HEADER_PID_FAMILY_1035A0_SCSI (0x0009) +#define MPI_FW_HEADER_PID_FAMILY_1035B0_SCSI (0x000A) +#define MPI_FW_HEADER_PID_FAMILY_909_FC (0x0000) +#define MPI_FW_HEADER_PID_FAMILY_919_FC (0x0001) +#define MPI_FW_HEADER_PID_FAMILY_919X_FC (0x0002) + +typedef struct _MPI_EXT_IMAGE_HEADER +{ + U8 ImageType; /* 00h */ + U8 Reserved; /* 01h */ + U16 Reserved1; /* 02h */ + U32 Checksum; /* 04h */ + U32 ImageSize; /* 08h */ + U32 NextImageHeaderOffset; /* 0Ch */ + U32 LoadStartAddress; /* 10h */ + U32 Reserved2; /* 14h */ +} MPI_EXT_IMAGE_HEADER, MPI_POINTER PTR_MPI_EXT_IMAGE_HEADER, + MpiExtImageHeader_t, MPI_POINTER pMpiExtImageHeader_t; + +/* defines for the ImageType field */ +#define MPI_EXT_IMAGE_TYPE_UNSPECIFIED (0x00) +#define MPI_EXT_IMAGE_TYPE_FW (0x01) +#define MPI_EXT_IMAGE_TYPE_NVDATA (0x03) + +#endif diff --git a/sys/dev/mpt/mpilib/mpi_lan.h b/sys/dev/mpt/mpilib/mpi_lan.h new file mode 100644 index 0000000..0c2a137 --- /dev/null +++ b/sys/dev/mpt/mpilib/mpi_lan.h @@ -0,0 +1,234 @@ +/* $FreeBSD$ */ +/* + * Copyright (c) 2000, 2001 by LSI Logic Corporation + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice immediately at the beginning of the file, without modification, + * this list of conditions, and the following disclaimer. + * 2. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * + * Name: MPI_LAN.H + * Title: MPI LAN messages and structures + * Creation Date: June 30, 2000 + * + * MPI Version: 01.02.01 + * + * Version History + * --------------- + * + * Date Version Description + * -------- -------- ------------------------------------------------------ + * 05-08-00 00.10.01 Original release for 0.10 spec dated 4/26/2000. + * 05-24-00 00.10.02 Added LANStatus field to _MSG_LAN_SEND_REPLY. + * Added LANStatus field to _MSG_LAN_RECEIVE_POST_REPLY. + * Moved ListCount field in _MSG_LAN_RECEIVE_POST_REPLY. + * 06-06-00 01.00.01 Update version number for 1.0 release. + * 06-12-00 01.00.02 Added MPI_ to BUCKETSTATUS_ definitions. + * 06-22-00 01.00.03 Major changes to match new LAN definition in 1.0 spec. + * 06-30-00 01.00.04 Added Context Reply definitions per revised proposal. + * Changed transaction context usage to bucket/buffer. + * 07-05-00 01.00.05 Removed LAN_RECEIVE_POST_BUCKET_CONTEXT_MASK definition + * to lan private header file + * 11-02-00 01.01.01 Original release for post 1.0 work + * 02-20-01 01.01.02 Started using MPI_POINTER. + * 03-27-01 01.01.03 Added structure offset comments. + * 08-08-01 01.02.01 Original release for v1.2 work. + * -------------------------------------------------------------------------- + */ + +#ifndef MPI_LAN_H +#define MPI_LAN_H + + +/****************************************************************************** +* +* L A N M e s s a g e s +* +*******************************************************************************/ + +/* LANSend messages */ + +typedef struct _MSG_LAN_SEND_REQUEST +{ + U16 Reserved; /* 00h */ + U8 ChainOffset; /* 02h */ + U8 Function; /* 03h */ + U16 Reserved2; /* 04h */ + U8 PortNumber; /* 06h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ + SGE_MPI_UNION SG_List[1]; /* 0Ch */ +} MSG_LAN_SEND_REQUEST, MPI_POINTER PTR_MSG_LAN_SEND_REQUEST, + LANSendRequest_t, MPI_POINTER pLANSendRequest_t; + + +typedef struct _MSG_LAN_SEND_REPLY +{ + U16 Reserved; /* 00h */ + U8 MsgLength; /* 02h */ + U8 Function; /* 03h */ + U8 Reserved2; /* 04h */ + U8 NumberOfContexts; /* 05h */ + U8 PortNumber; /* 06h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ + U16 Reserved3; /* 0Ch */ + U16 IOCStatus; /* 0Eh */ + U32 IOCLogInfo; /* 10h */ + U32 BufferContext; /* 14h */ +} MSG_LAN_SEND_REPLY, MPI_POINTER PTR_MSG_LAN_SEND_REPLY, + LANSendReply_t, MPI_POINTER pLANSendReply_t; + + +/* LANReceivePost */ + +typedef struct _MSG_LAN_RECEIVE_POST_REQUEST +{ + U16 Reserved; /* 00h */ + U8 ChainOffset; /* 02h */ + U8 Function; /* 03h */ + U16 Reserved2; /* 04h */ + U8 PortNumber; /* 06h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ + U32 BucketCount; /* 0Ch */ + SGE_MPI_UNION SG_List[1]; /* 10h */ +} MSG_LAN_RECEIVE_POST_REQUEST, MPI_POINTER PTR_MSG_LAN_RECEIVE_POST_REQUEST, + LANReceivePostRequest_t, MPI_POINTER pLANReceivePostRequest_t; + + +typedef struct _MSG_LAN_RECEIVE_POST_REPLY +{ + U16 Reserved; /* 00h */ + U8 MsgLength; /* 02h */ + U8 Function; /* 03h */ + U8 Reserved2; /* 04h */ + U8 NumberOfContexts; /* 05h */ + U8 PortNumber; /* 06h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ + U16 Reserved3; /* 0Ch */ + U16 IOCStatus; /* 0Eh */ + U32 IOCLogInfo; /* 10h */ + U32 BucketsRemaining; /* 14h */ + U32 PacketOffset; /* 18h */ + U32 PacketLength; /* 1Ch */ + U32 BucketContext[1]; /* 20h */ +} MSG_LAN_RECEIVE_POST_REPLY, MPI_POINTER PTR_MSG_LAN_RECEIVE_POST_REPLY, + LANReceivePostReply_t, MPI_POINTER pLANReceivePostReply_t; + + +/* LANReset */ + +typedef struct _MSG_LAN_RESET_REQUEST +{ + U16 Reserved; /* 00h */ + U8 ChainOffset; /* 02h */ + U8 Function; /* 03h */ + U16 Reserved2; /* 04h */ + U8 PortNumber; /* 05h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ +} MSG_LAN_RESET_REQUEST, MPI_POINTER PTR_MSG_LAN_RESET_REQUEST, + LANResetRequest_t, MPI_POINTER pLANResetRequest_t; + + +typedef struct _MSG_LAN_RESET_REPLY +{ + U16 Reserved; /* 00h */ + U8 MsgLength; /* 02h */ + U8 Function; /* 03h */ + U16 Reserved2; /* 04h */ + U8 PortNumber; /* 06h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ + U16 Reserved3; /* 0Ch */ + U16 IOCStatus; /* 0Eh */ + U32 IOCLogInfo; /* 10h */ +} MSG_LAN_RESET_REPLY, MPI_POINTER PTR_MSG_LAN_RESET_REPLY, + LANResetReply_t, MPI_POINTER pLANResetReply_t; + + +/****************************************************************************/ +/* LAN Context Reply defines and macros */ +/****************************************************************************/ + +#define LAN_REPLY_PACKET_LENGTH_MASK (0x0000FFFF) +#define LAN_REPLY_PACKET_LENGTH_SHIFT (0) +#define LAN_REPLY_BUCKET_CONTEXT_MASK (0x07FF0000) +#define LAN_REPLY_BUCKET_CONTEXT_SHIFT (16) +#define LAN_REPLY_BUFFER_CONTEXT_MASK (0x07FFFFFF) +#define LAN_REPLY_BUFFER_CONTEXT_SHIFT (0) +#define LAN_REPLY_FORM_MASK (0x18000000) +#define LAN_REPLY_FORM_RECEIVE_SINGLE (0x00) +#define LAN_REPLY_FORM_RECEIVE_MULTIPLE (0x01) +#define LAN_REPLY_FORM_SEND_SINGLE (0x02) +#define LAN_REPLY_FORM_MESSAGE_CONTEXT (0x03) +#define LAN_REPLY_FORM_SHIFT (27) + +#define GET_LAN_PACKET_LENGTH(x) (((x) & LAN_REPLY_PACKET_LENGTH_MASK) \ + >> LAN_REPLY_PACKET_LENGTH_SHIFT) + +#define SET_LAN_PACKET_LENGTH(x, lth) \ + ((x) = ((x) & ~LAN_REPLY_PACKET_LENGTH_MASK) | \ + (((lth) << LAN_REPLY_PACKET_LENGTH_SHIFT) & \ + LAN_REPLY_PACKET_LENGTH_MASK)) + +#define GET_LAN_BUCKET_CONTEXT(x) (((x) & LAN_REPLY_BUCKET_CONTEXT_MASK) \ + >> LAN_REPLY_BUCKET_CONTEXT_SHIFT) + +#define SET_LAN_BUCKET_CONTEXT(x, ctx) \ + ((x) = ((x) & ~LAN_REPLY_BUCKET_CONTEXT_MASK) | \ + (((ctx) << LAN_REPLY_BUCKET_CONTEXT_SHIFT) & \ + LAN_REPLY_BUCKET_CONTEXT_MASK)) + +#define GET_LAN_BUFFER_CONTEXT(x) (((x) & LAN_REPLY_BUFFER_CONTEXT_MASK) \ + >> LAN_REPLY_BUFFER_CONTEXT_SHIFT) + +#define SET_LAN_BUFFER_CONTEXT(x, ctx) \ + ((x) = ((x) & ~LAN_REPLY_BUFFER_CONTEXT_MASK) | \ + (((ctx) << LAN_REPLY_BUFFER_CONTEXT_SHIFT) & \ + LAN_REPLY_BUFFER_CONTEXT_MASK)) + +#define GET_LAN_FORM(x) (((x) & LAN_REPLY_FORM_MASK) \ + >> LAN_REPLY_FORM_SHIFT) + +#define SET_LAN_FORM(x, frm) \ + ((x) = ((x) & ~LAN_REPLY_FORM_MASK) | \ + (((frm) << LAN_REPLY_FORM_SHIFT) & \ + LAN_REPLY_FORM_MASK)) + + +/****************************************************************************/ +/* LAN Current Device State defines */ +/****************************************************************************/ + +#define MPI_LAN_DEVICE_STATE_RESET (0x00) +#define MPI_LAN_DEVICE_STATE_OPERATIONAL (0x01) + + +/****************************************************************************/ +/* LAN Loopback defines */ +/****************************************************************************/ + +#define MPI_LAN_TX_MODES_ENABLE_LOOPBACK_SUPPRESSION (0x01) + +#endif + diff --git a/sys/dev/mpt/mpilib/mpi_raid.h b/sys/dev/mpt/mpilib/mpi_raid.h new file mode 100644 index 0000000..c78a600 --- /dev/null +++ b/sys/dev/mpt/mpilib/mpi_raid.h @@ -0,0 +1,254 @@ +/* $FreeBSD$ */ +/* + * Copyright (c) 2000, 2001 by LSI Logic Corporation + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice immediately at the beginning of the file, without modification, + * this list of conditions, and the following disclaimer. + * 2. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * + * Name: MPI_RAID.H + * Title: MPI RAID message and structures + * Creation Date: February 27, 2001 + * + * MPI_RAID.H Version: 01.02.09 + * + * Version History + * --------------- + * + * Date Version Description + * -------- -------- ------------------------------------------------------ + * 02-27-01 01.01.01 Original release for this file. + * 03-27-01 01.01.02 Added structure offset comments. + * 08-08-01 01.02.01 Original release for v1.2 work. + * 09-28-01 01.02.02 Major rework for MPI v1.2 Integrated RAID changes. + * 10-04-01 01.02.03 Added ActionData defines for + * MPI_RAID_ACTION_DELETE_VOLUME action. + * 11-01-01 01.02.04 Added define for MPI_RAID_ACTION_ADATA_DO_NOT_SYNC. + * 03-14-02 01.02.05 Added define for MPI_RAID_ACTION_ADATA_LOW_LEVEL_INIT. + * 05-07-02 01.02.06 Added define for MPI_RAID_ACTION_ACTIVATE_VOLUME, + * MPI_RAID_ACTION_INACTIVATE_VOLUME, and + * MPI_RAID_ACTION_ADATA_INACTIVATE_ALL. + * 07-12-02 01.02.07 Added structures for Mailbox request and reply. + * 11-15-02 01.02.08 Added missing MsgContext field to MSG_MAILBOX_REQUEST. + * 04-01-03 01.02.09 New action data option flag for + * MPI_RAID_ACTION_DELETE_VOLUME. + * -------------------------------------------------------------------------- + */ + +#ifndef MPI_RAID_H +#define MPI_RAID_H + + +/****************************************************************************** +* +* R A I D M e s s a g e s +* +*******************************************************************************/ + + +/****************************************************************************/ +/* RAID Volume Request */ +/****************************************************************************/ + +typedef struct _MSG_RAID_ACTION +{ + U8 Action; /* 00h */ + U8 Reserved1; /* 01h */ + U8 ChainOffset; /* 02h */ + U8 Function; /* 03h */ + U8 VolumeID; /* 04h */ + U8 VolumeBus; /* 05h */ + U8 PhysDiskNum; /* 06h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ + U32 Reserved2; /* 0Ch */ + U32 ActionDataWord; /* 10h */ + SGE_SIMPLE_UNION ActionDataSGE; /* 14h */ +} MSG_RAID_ACTION_REQUEST, MPI_POINTER PTR_MSG_RAID_ACTION_REQUEST, + MpiRaidActionRequest_t , MPI_POINTER pMpiRaidActionRequest_t; + + +/* RAID Action request Action values */ + +#define MPI_RAID_ACTION_STATUS (0x00) +#define MPI_RAID_ACTION_INDICATOR_STRUCT (0x01) +#define MPI_RAID_ACTION_CREATE_VOLUME (0x02) +#define MPI_RAID_ACTION_DELETE_VOLUME (0x03) +#define MPI_RAID_ACTION_DISABLE_VOLUME (0x04) +#define MPI_RAID_ACTION_ENABLE_VOLUME (0x05) +#define MPI_RAID_ACTION_QUIESCE_PHYS_IO (0x06) +#define MPI_RAID_ACTION_ENABLE_PHYS_IO (0x07) +#define MPI_RAID_ACTION_CHANGE_VOLUME_SETTINGS (0x08) +#define MPI_RAID_ACTION_PHYSDISK_OFFLINE (0x0A) +#define MPI_RAID_ACTION_PHYSDISK_ONLINE (0x0B) +#define MPI_RAID_ACTION_CHANGE_PHYSDISK_SETTINGS (0x0C) +#define MPI_RAID_ACTION_CREATE_PHYSDISK (0x0D) +#define MPI_RAID_ACTION_DELETE_PHYSDISK (0x0E) +#define MPI_RAID_ACTION_FAIL_PHYSDISK (0x0F) +#define MPI_RAID_ACTION_REPLACE_PHYSDISK (0x10) +#define MPI_RAID_ACTION_ACTIVATE_VOLUME (0x11) +#define MPI_RAID_ACTION_INACTIVATE_VOLUME (0x12) + +/* ActionDataWord defines for use with MPI_RAID_ACTION_CREATE_VOLUME action */ +#define MPI_RAID_ACTION_ADATA_DO_NOT_SYNC (0x00000001) +#define MPI_RAID_ACTION_ADATA_LOW_LEVEL_INIT (0x00000002) + +/* ActionDataWord defines for use with MPI_RAID_ACTION_DELETE_VOLUME action */ +#define MPI_RAID_ACTION_ADATA_KEEP_PHYS_DISKS (0x00000000) +#define MPI_RAID_ACTION_ADATA_DEL_PHYS_DISKS (0x00000001) + +#define MPI_RAID_ACTION_ADATA_KEEP_LBA0 (0x00000000) +#define MPI_RAID_ACTION_ADATA_ZERO_LBA0 (0x00000002) + +/* ActionDataWord defines for use with MPI_RAID_ACTION_ACTIVATE_VOLUME action */ +#define MPI_RAID_ACTION_ADATA_INACTIVATE_ALL (0x00000001) + + +/* RAID Action reply message */ + +typedef struct _MSG_RAID_ACTION_REPLY +{ + U8 Action; /* 00h */ + U8 Reserved; /* 01h */ + U8 MsgLength; /* 02h */ + U8 Function; /* 03h */ + U8 VolumeID; /* 04h */ + U8 VolumeBus; /* 05h */ + U8 PhysDiskNum; /* 06h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ + U16 ActionStatus; /* 0Ch */ + U16 IOCStatus; /* 0Eh */ + U32 IOCLogInfo; /* 10h */ + U32 VolumeStatus; /* 14h */ + U32 ActionData; /* 18h */ +} MSG_RAID_ACTION_REPLY, MPI_POINTER PTR_MSG_RAID_ACTION_REPLY, + MpiRaidActionReply_t, MPI_POINTER pMpiRaidActionReply_t; + + +/* RAID Volume reply ActionStatus values */ + +#define MPI_RAID_ACTION_ASTATUS_SUCCESS (0x0000) +#define MPI_RAID_ACTION_ASTATUS_INVALID_ACTION (0x0001) +#define MPI_RAID_ACTION_ASTATUS_FAILURE (0x0002) +#define MPI_RAID_ACTION_ASTATUS_IN_PROGRESS (0x0003) + + +/* RAID Volume reply RAID Volume Indicator structure */ + +typedef struct _MPI_RAID_VOL_INDICATOR +{ + U64 TotalBlocks; /* 00h */ + U64 BlocksRemaining; /* 08h */ +} MPI_RAID_VOL_INDICATOR, MPI_POINTER PTR_MPI_RAID_VOL_INDICATOR, + MpiRaidVolIndicator_t, MPI_POINTER pMpiRaidVolIndicator_t; + + +/****************************************************************************/ +/* SCSI IO RAID Passthrough Request */ +/****************************************************************************/ + +typedef struct _MSG_SCSI_IO_RAID_PT_REQUEST +{ + U8 PhysDiskNum; /* 00h */ + U8 Reserved1; /* 01h */ + U8 ChainOffset; /* 02h */ + U8 Function; /* 03h */ + U8 CDBLength; /* 04h */ + U8 SenseBufferLength; /* 05h */ + U8 Reserved2; /* 06h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ + U8 LUN[8]; /* 0Ch */ + U32 Control; /* 14h */ + U8 CDB[16]; /* 18h */ + U32 DataLength; /* 28h */ + U32 SenseBufferLowAddr; /* 2Ch */ + SGE_IO_UNION SGL; /* 30h */ +} MSG_SCSI_IO_RAID_PT_REQUEST, MPI_POINTER PTR_MSG_SCSI_IO_RAID_PT_REQUEST, + SCSIIORaidPassthroughRequest_t, MPI_POINTER pSCSIIORaidPassthroughRequest_t; + + +/* SCSI IO RAID Passthrough reply structure */ + +typedef struct _MSG_SCSI_IO_RAID_PT_REPLY +{ + U8 PhysDiskNum; /* 00h */ + U8 Reserved1; /* 01h */ + U8 MsgLength; /* 02h */ + U8 Function; /* 03h */ + U8 CDBLength; /* 04h */ + U8 SenseBufferLength; /* 05h */ + U8 Reserved2; /* 06h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ + U8 SCSIStatus; /* 0Ch */ + U8 SCSIState; /* 0Dh */ + U16 IOCStatus; /* 0Eh */ + U32 IOCLogInfo; /* 10h */ + U32 TransferCount; /* 14h */ + U32 SenseCount; /* 18h */ + U32 ResponseInfo; /* 1Ch */ +} MSG_SCSI_IO_RAID_PT_REPLY, MPI_POINTER PTR_MSG_SCSI_IO_RAID_PT_REPLY, + SCSIIORaidPassthroughReply_t, MPI_POINTER pSCSIIORaidPassthroughReply_t; + + +/****************************************************************************/ +/* Mailbox reqeust structure */ +/****************************************************************************/ + +typedef struct _MSG_MAILBOX_REQUEST +{ + U16 Reserved1; + U8 ChainOffset; + U8 Function; + U16 Reserved2; + U8 Reserved3; + U8 MsgFlags; + U32 MsgContext; + U8 Command[10]; + U16 Reserved4; + SGE_IO_UNION SGL; +} MSG_MAILBOX_REQUEST, MPI_POINTER PTR_MSG_MAILBOX_REQUEST, + MailboxRequest_t, MPI_POINTER pMailboxRequest_t; + + +/* Mailbox reply structure */ +typedef struct _MSG_MAILBOX_REPLY +{ + U16 Reserved1; /* 00h */ + U8 MsgLength; /* 02h */ + U8 Function; /* 03h */ + U16 Reserved2; /* 04h */ + U8 Reserved3; /* 06h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ + U16 MailboxStatus; /* 0Ch */ + U16 IOCStatus; /* 0Eh */ + U32 IOCLogInfo; /* 10h */ + U32 Reserved4; /* 14h */ +} MSG_MAILBOX_REPLY, MPI_POINTER PTR_MSG_MAILBOX_REPLY, + MailboxReply_t, MPI_POINTER pMailboxReply_t; + +#endif + + + diff --git a/sys/dev/mpt/mpilib/mpi_targ.h b/sys/dev/mpt/mpilib/mpi_targ.h new file mode 100644 index 0000000..f212c62 --- /dev/null +++ b/sys/dev/mpt/mpilib/mpi_targ.h @@ -0,0 +1,430 @@ +/* $FreeBSD$ */ +/* + * Copyright (c) 2000, 2001 by LSI Logic Corporation + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice immediately at the beginning of the file, without modification, + * this list of conditions, and the following disclaimer. + * 2. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * + * Name: MPI_TARG.H + * Title: MPI Target mode messages and structures + * Creation Date: June 22, 2000 + * + * MPI Version: 01.02.04 + * + * Version History + * --------------- + * + * Date Version Description + * -------- -------- ------------------------------------------------------ + * 05-08-00 00.10.01 Original release for 0.10 spec dated 4/26/2000. + * 06-06-00 01.00.01 Update version number for 1.0 release. + * 06-22-00 01.00.02 Added _MSG_TARGET_CMD_BUFFER_POST_REPLY structure. + * Corrected DECSRIPTOR typo to DESCRIPTOR. + * 11-02-00 01.01.01 Original release for post 1.0 work + * Modified target mode to use IoIndex instead of + * HostIndex and IocIndex. Added Alias. + * 01-09-01 01.01.02 Added defines for TARGET_ASSIST_FLAGS_REPOST_CMD_BUFFER + * and TARGET_STATUS_SEND_FLAGS_REPOST_CMD_BUFFER. + * 02-20-01 01.01.03 Started using MPI_POINTER. + * Added structures for MPI_TARGET_SCSI_SPI_CMD_BUFFER and + * MPI_TARGET_FCP_CMD_BUFFER. + * 03-27-01 01.01.04 Added structure offset comments. + * 08-08-01 01.02.01 Original release for v1.2 work. + * 09-28-01 01.02.02 Added structure for MPI_TARGET_SCSI_SPI_STATUS_IU. + * Added PriorityReason field to some replies and + * defined more PriorityReason codes. + * Added some defines for to support previous version + * of MPI. + * 10-04-01 01.02.03 Added PriorityReason to MSG_TARGET_ERROR_REPLY. + * 11-01-01 01.02.04 Added define for TARGET_STATUS_SEND_FLAGS_HIGH_PRIORITY. + * -------------------------------------------------------------------------- + */ + +#ifndef MPI_TARG_H +#define MPI_TARG_H + + +/****************************************************************************** +* +* S C S I T a r g e t M e s s a g e s +* +*******************************************************************************/ + +typedef struct _CMD_BUFFER_DESCRIPTOR +{ + U16 IoIndex; /* 00h */ + U16 Reserved; /* 02h */ + union /* 04h */ + { + U32 PhysicalAddress32; + U64 PhysicalAddress64; + } _u; +} CMD_BUFFER_DESCRIPTOR, MPI_POINTER PTR_CMD_BUFFER_DESCRIPTOR, + CmdBufferDescriptor_t, MPI_POINTER pCmdBufferDescriptor_t; + + +/****************************************************************************/ +/* Target Command Buffer Post Request */ +/****************************************************************************/ + +typedef struct _MSG_TARGET_CMD_BUFFER_POST_REQUEST +{ + U8 BufferPostFlags; /* 00h */ + U8 BufferCount; /* 01h */ + U8 ChainOffset; /* 02h */ + U8 Function; /* 03h */ + U8 BufferLength; /* 04h */ + U8 Reserved; /* 05h */ + U8 Reserved1; /* 06h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ + CMD_BUFFER_DESCRIPTOR Buffer[1]; /* 0Ch */ +} MSG_TARGET_CMD_BUFFER_POST_REQUEST, MPI_POINTER PTR_MSG_TARGET_CMD_BUFFER_POST_REQUEST, + TargetCmdBufferPostRequest_t, MPI_POINTER pTargetCmdBufferPostRequest_t; + +#define CMD_BUFFER_POST_FLAGS_PORT_MASK (0x01) +#define CMD_BUFFER_POST_FLAGS_ADDR_MODE_MASK (0x80) +#define CMD_BUFFER_POST_FLAGS_ADDR_MODE_32 (0) +#define CMD_BUFFER_POST_FLAGS_ADDR_MODE_64 (1) +#define CMD_BUFFER_POST_FLAGS_64_BIT_ADDR (0x80) + +#define CMD_BUFFER_POST_IO_INDEX_MASK (0x00003FFF) +#define CMD_BUFFER_POST_IO_INDEX_MASK_0100 (0x000003FF) /* obsolete */ + + +typedef struct _MSG_TARGET_CMD_BUFFER_POST_REPLY +{ + U8 BufferPostFlags; /* 00h */ + U8 BufferCount; /* 01h */ + U8 MsgLength; /* 02h */ + U8 Function; /* 03h */ + U8 BufferLength; /* 04h */ + U8 Reserved; /* 05h */ + U8 Reserved1; /* 06h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ + U16 Reserved2; /* 0Ch */ + U16 IOCStatus; /* 0Eh */ + U32 IOCLogInfo; /* 10h */ +} MSG_TARGET_CMD_BUFFER_POST_REPLY, MPI_POINTER PTR_MSG_TARGET_CMD_BUFFER_POST_REPLY, + TargetCmdBufferPostReply_t, MPI_POINTER pTargetCmdBufferPostReply_t; + +/* the following structure is obsolete as of MPI v1.2 */ +typedef struct _MSG_PRIORITY_CMD_RECEIVED_REPLY +{ + U16 Reserved; /* 00h */ + U8 MsgLength; /* 02h */ + U8 Function; /* 03h */ + U16 Reserved1; /* 04h */ + U8 Reserved2; /* 06h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ + U8 PriorityReason; /* 0Ch */ + U8 Reserved3; /* 0Dh */ + U16 IOCStatus; /* 0Eh */ + U32 IOCLogInfo; /* 10h */ + U32 ReplyWord; /* 14h */ +} MSG_PRIORITY_CMD_RECEIVED_REPLY, MPI_POINTER PTR_MSG_PRIORITY_CMD_RECEIVED_REPLY, + PriorityCommandReceivedReply_t, MPI_POINTER pPriorityCommandReceivedReply_t; + +#define PRIORITY_REASON_NO_DISCONNECT (0x00) +#define PRIORITY_REASON_SCSI_TASK_MANAGEMENT (0x01) +#define PRIORITY_REASON_CMD_PARITY_ERR (0x02) +#define PRIORITY_REASON_MSG_OUT_PARITY_ERR (0x03) +#define PRIORITY_REASON_LQ_CRC_ERR (0x04) +#define PRIORITY_REASON_CMD_CRC_ERR (0x05) +#define PRIORITY_REASON_PROTOCOL_ERR (0x06) +#define PRIORITY_REASON_DATA_OUT_PARITY_ERR (0x07) +#define PRIORITY_REASON_DATA_OUT_CRC_ERR (0x08) +#define PRIORITY_REASON_UNKNOWN (0xFF) + + +typedef struct _MSG_TARGET_CMD_BUFFER_POST_ERROR_REPLY +{ + U16 Reserved; /* 00h */ + U8 MsgLength; /* 02h */ + U8 Function; /* 03h */ + U16 Reserved1; /* 04h */ + U8 Reserved2; /* 06h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ + U8 PriorityReason; /* 0Ch */ + U8 Reserved3; /* 0Dh */ + U16 IOCStatus; /* 0Eh */ + U32 IOCLogInfo; /* 10h */ + U32 ReplyWord; /* 14h */ +} MSG_TARGET_CMD_BUFFER_POST_ERROR_REPLY, + MPI_POINTER PTR_MSG_TARGET_CMD_BUFFER_POST_ERROR_REPLY, + TargetCmdBufferPostErrorReply_t, MPI_POINTER pTargetCmdBufferPostErrorReply_t; + + +typedef struct _MPI_TARGET_FCP_CMD_BUFFER +{ + U8 FcpLun[8]; /* 00h */ + U8 FcpCntl[4]; /* 08h */ + U8 FcpCdb[16]; /* 0Ch */ + U32 FcpDl; /* 1Ch */ +} MPI_TARGET_FCP_CMD_BUFFER, MPI_POINTER PTR_MPI_TARGET_FCP_CMD_BUFFER, + MpiTargetFcpCmdBuffer, MPI_POINTER pMpiTargetFcpCmdBuffer; + + +typedef struct _MPI_TARGET_SCSI_SPI_CMD_BUFFER +{ + /* SPI L_Q information unit */ + U8 L_QType; /* 00h */ + U8 Reserved; /* 01h */ + U16 Tag; /* 02h */ + U8 LogicalUnitNumber[8]; /* 04h */ + U32 DataLength; /* 0Ch */ + /* SPI command information unit */ + U8 ReservedFirstByteOfCommandIU; /* 10h */ + U8 TaskAttribute; /* 11h */ + U8 TaskManagementFlags; /* 12h */ + U8 AdditionalCDBLength; /* 13h */ + U8 CDB[16]; /* 14h */ +} MPI_TARGET_SCSI_SPI_CMD_BUFFER, + MPI_POINTER PTR_MPI_TARGET_SCSI_SPI_CMD_BUFFER, + MpiTargetScsiSpiCmdBuffer, MPI_POINTER pMpiTargetScsiSpiCmdBuffer; + + +/****************************************************************************/ +/* Target Assist Request */ +/****************************************************************************/ + +typedef struct _MSG_TARGET_ASSIST_REQUEST +{ + U8 StatusCode; /* 00h */ + U8 TargetAssistFlags; /* 01h */ + U8 ChainOffset; /* 02h */ + U8 Function; /* 03h */ + U16 QueueTag; /* 04h */ + U8 Reserved; /* 06h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ + U32 ReplyWord; /* 0Ch */ + U8 LUN[8]; /* 10h */ + U32 RelativeOffset; /* 18h */ + U32 DataLength; /* 1Ch */ + SGE_IO_UNION SGL[1]; /* 20h */ +} MSG_TARGET_ASSIST_REQUEST, MPI_POINTER PTR_MSG_TARGET_ASSIST_REQUEST, + TargetAssistRequest_t, MPI_POINTER pTargetAssistRequest_t; + +#define TARGET_ASSIST_FLAGS_DATA_DIRECTION (0x01) +#define TARGET_ASSIST_FLAGS_AUTO_STATUS (0x02) +#define TARGET_ASSIST_FLAGS_HIGH_PRIORITY (0x04) +#define TARGET_ASSIST_FLAGS_REPOST_CMD_BUFFER (0x80) + + +typedef struct _MSG_TARGET_ERROR_REPLY +{ + U16 Reserved; /* 00h */ + U8 MsgLength; /* 02h */ + U8 Function; /* 03h */ + U16 Reserved1; /* 04h */ + U8 Reserved2; /* 06h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ + U8 PriorityReason; /* 0Ch */ + U8 Reserved3; /* 0Dh */ + U16 IOCStatus; /* 0Eh */ + U32 IOCLogInfo; /* 10h */ + U32 ReplyWord; /* 14h */ + U32 TransferCount; /* 18h */ +} MSG_TARGET_ERROR_REPLY, MPI_POINTER PTR_MSG_TARGET_ERROR_REPLY, + TargetErrorReply_t, MPI_POINTER pTargetErrorReply_t; + + +/****************************************************************************/ +/* Target Status Send Request */ +/****************************************************************************/ + +typedef struct _MSG_TARGET_STATUS_SEND_REQUEST +{ + U8 StatusCode; /* 00h */ + U8 StatusFlags; /* 01h */ + U8 ChainOffset; /* 02h */ + U8 Function; /* 03h */ + U16 QueueTag; /* 04h */ + U8 Reserved; /* 06h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ + U32 ReplyWord; /* 0Ch */ + U8 LUN[8]; /* 10h */ + SGE_SIMPLE_UNION StatusDataSGE; /* 18h */ +} MSG_TARGET_STATUS_SEND_REQUEST, MPI_POINTER PTR_MSG_TARGET_STATUS_SEND_REQUEST, + TargetStatusSendRequest_t, MPI_POINTER pTargetStatusSendRequest_t; + +#define TARGET_STATUS_SEND_FLAGS_AUTO_GOOD_STATUS (0x01) +#define TARGET_STATUS_SEND_FLAGS_HIGH_PRIORITY (0x04) +#define TARGET_STATUS_SEND_FLAGS_REPOST_CMD_BUFFER (0x80) + +typedef struct _MPI_TARGET_FCP_RSP_BUFFER +{ + U8 Reserved0[8]; /* 00h */ + U8 FcpStatus; /* 08h */ + U8 FcpFlags; /* 09h */ + U8 Reserved1[2]; /* 0Ah */ + U32 FcpResid; /* 0Ch */ + U32 FcpSenseLength; /* 10h */ + U32 FcpResponseLength; /* 14h */ + U8 FcpResponseData[8]; /* 18h */ + U8 FcpSenseData[32]; /* Pad to 64 bytes */ /* 20h */ +} MPI_TARGET_FCP_RSP_BUFFER, MPI_POINTER PTR_MPI_TARGET_FCP_RSP_BUFFER, + MpiTargetFcpRspBuffer, MPI_POINTER pMpiTargetFcpRspBuffer; + +typedef struct _MPI_TARGET_SCSI_SPI_STATUS_IU +{ + U8 Reserved0; /* 00h */ + U8 Reserved1; /* 01h */ + U8 Valid; /* 02h */ + U8 Status; /* 03h */ + U32 SenseDataListLength; /* 04h */ + U32 PktFailuresListLength; /* 08h */ + U8 SenseData[52]; /* Pad the IU to 64 bytes */ /* 0Ch */ +} MPI_TARGET_SCSI_SPI_STATUS_IU, MPI_POINTER PTR_MPI_TARGET_SCSI_SPI_STATUS_IU, + TargetScsiSpiStatusIU_t, MPI_POINTER pTargetScsiSpiStatusIU_t; + +/****************************************************************************/ +/* Target Mode Abort Request */ +/****************************************************************************/ + +typedef struct _MSG_TARGET_MODE_ABORT_REQUEST +{ + U8 AbortType; /* 00h */ + U8 Reserved; /* 01h */ + U8 ChainOffset; /* 02h */ + U8 Function; /* 03h */ + U16 Reserved1; /* 04h */ + U8 Reserved2; /* 06h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ + U32 ReplyWord; /* 0Ch */ + U32 MsgContextToAbort; /* 10h */ +} MSG_TARGET_MODE_ABORT, MPI_POINTER PTR_MSG_TARGET_MODE_ABORT, + TargetModeAbort_t, MPI_POINTER pTargetModeAbort_t; + +#define TARGET_MODE_ABORT_TYPE_ALL_CMD_BUFFERS (0x00) +#define TARGET_MODE_ABORT_TYPE_ALL_IO (0x01) +#define TARGET_MODE_ABORT_TYPE_EXACT_IO (0x02) +#define TARGET_MODE_ABORT_TYPE_EXACT_IO_REQUEST (0x03) + +/* Target Mode Abort Reply */ + +typedef struct _MSG_TARGET_MODE_ABORT_REPLY +{ + U16 Reserved; /* 00h */ + U8 MsgLength; /* 02h */ + U8 Function; /* 03h */ + U16 Reserved1; /* 04h */ + U8 Reserved2; /* 06h */ + U8 MsgFlags; /* 07h */ + U32 MsgContext; /* 08h */ + U16 Reserved3; /* 0Ch */ + U16 IOCStatus; /* 0Eh */ + U32 IOCLogInfo; /* 10h */ + U32 AbortCount; /* 14h */ +} MSG_TARGET_MODE_ABORT_REPLY, MPI_POINTER PTR_MSG_TARGET_MODE_ABORT_REPLY, + TargetModeAbortReply_t, MPI_POINTER pTargetModeAbortReply_t; + + +/****************************************************************************/ +/* Target Mode Context Reply */ +/****************************************************************************/ + +#define TARGET_MODE_REPLY_IO_INDEX_MASK (0x00003FFF) +#define TARGET_MODE_REPLY_IO_INDEX_SHIFT (0) +#define TARGET_MODE_REPLY_INITIATOR_INDEX_MASK (0x03FFC000) +#define TARGET_MODE_REPLY_INITIATOR_INDEX_SHIFT (14) +#define TARGET_MODE_REPLY_ALIAS_MASK (0x0C000000) +#define TARGET_MODE_REPLY_ALIAS_SHIFT (26) +#define TARGET_MODE_REPLY_PORT_MASK (0x10000000) +#define TARGET_MODE_REPLY_PORT_SHIFT (28) + + +#define GET_IO_INDEX(x) (((x) & TARGET_MODE_REPLY_IO_INDEX_MASK) \ + >> TARGET_MODE_REPLY_IO_INDEX_SHIFT) + +#define SET_IO_INDEX(t, i) \ + ((t) = ((t) & ~TARGET_MODE_REPLY_IO_INDEX_MASK) | \ + (((i) << TARGET_MODE_REPLY_IO_INDEX_SHIFT) & \ + TARGET_MODE_REPLY_IO_INDEX_MASK)) + +#define GET_INITIATOR_INDEX(x) (((x) & TARGET_MODE_REPLY_INITIATOR_INDEX_MASK) \ + >> TARGET_MODE_REPLY_INITIATOR_INDEX_SHIFT) + +#define SET_INITIATOR_INDEX(t, ii) \ + ((t) = ((t) & ~TARGET_MODE_REPLY_INITIATOR_INDEX_MASK) | \ + (((ii) << TARGET_MODE_REPLY_INITIATOR_INDEX_SHIFT) & \ + TARGET_MODE_REPLY_INITIATOR_INDEX_MASK)) + +#define GET_ALIAS(x) (((x) & TARGET_MODE_REPLY_ALIAS_MASK) \ + >> TARGET_MODE_REPLY_ALIAS_SHIFT) + +#define SET_ALIAS(t, a) ((t) = ((t) & ~TARGET_MODE_REPLY_ALIAS_MASK) | \ + (((a) << TARGET_MODE_REPLY_ALIAS_SHIFT) & \ + TARGET_MODE_REPLY_ALIAS_MASK)) + +#define GET_PORT(x) (((x) & TARGET_MODE_REPLY_PORT_MASK) \ + >> TARGET_MODE_REPLY_PORT_SHIFT) + +#define SET_PORT(t, p) ((t) = ((t) & ~TARGET_MODE_REPLY_PORT_MASK) | \ + (((p) << TARGET_MODE_REPLY_PORT_SHIFT) & \ + TARGET_MODE_REPLY_PORT_MASK)) + +/* the following obsolete values are for MPI v1.0 support */ +#define TARGET_MODE_REPLY_0100_MASK_HOST_INDEX (0x000003FF) +#define TARGET_MODE_REPLY_0100_SHIFT_HOST_INDEX (0) +#define TARGET_MODE_REPLY_0100_MASK_IOC_INDEX (0x001FF800) +#define TARGET_MODE_REPLY_0100_SHIFT_IOC_INDEX (11) +#define TARGET_MODE_REPLY_0100_PORT_MASK (0x00400000) +#define TARGET_MODE_REPLY_0100_PORT_SHIFT (22) +#define TARGET_MODE_REPLY_0100_MASK_INITIATOR_INDEX (0x1F800000) +#define TARGET_MODE_REPLY_0100_SHIFT_INITIATOR_INDEX (23) + +#define GET_HOST_INDEX_0100(x) (((x) & TARGET_MODE_REPLY_0100_MASK_HOST_INDEX) \ + >> TARGET_MODE_REPLY_0100_SHIFT_HOST_INDEX) + +#define SET_HOST_INDEX_0100(t, hi) \ + ((t) = ((t) & ~TARGET_MODE_REPLY_0100_MASK_HOST_INDEX) | \ + (((hi) << TARGET_MODE_REPLY_0100_SHIFT_HOST_INDEX) & \ + TARGET_MODE_REPLY_0100_MASK_HOST_INDEX)) + +#define GET_IOC_INDEX_0100(x) (((x) & TARGET_MODE_REPLY_0100_MASK_IOC_INDEX) \ + >> TARGET_MODE_REPLY_0100_SHIFT_IOC_INDEX) + +#define SET_IOC_INDEX_0100(t, ii) \ + ((t) = ((t) & ~TARGET_MODE_REPLY_0100_MASK_IOC_INDEX) | \ + (((ii) << TARGET_MODE_REPLY_0100_SHIFT_IOC_INDEX) & \ + TARGET_MODE_REPLY_0100_MASK_IOC_INDEX)) + +#define GET_INITIATOR_INDEX_0100(x) \ + (((x) & TARGET_MODE_REPLY_0100_MASK_INITIATOR_INDEX) \ + >> TARGET_MODE_REPLY_0100_SHIFT_INITIATOR_INDEX) + +#define SET_INITIATOR_INDEX_0100(t, ii) \ + ((t) = ((t) & ~TARGET_MODE_REPLY_0100_MASK_INITIATOR_INDEX) | \ + (((ii) << TARGET_MODE_REPLY_0100_SHIFT_INITIATOR_INDEX) & \ + TARGET_MODE_REPLY_0100_MASK_INITIATOR_INDEX)) + + +#endif + diff --git a/sys/dev/mpt/mpilib/mpi_type.h b/sys/dev/mpt/mpilib/mpi_type.h new file mode 100644 index 0000000..040cf96 --- /dev/null +++ b/sys/dev/mpt/mpilib/mpi_type.h @@ -0,0 +1,112 @@ +/* $FreeBSD$ */ +/* + * Copyright (c) 2000, 2001 by LSI Logic Corporation + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice immediately at the beginning of the file, without modification, + * this list of conditions, and the following disclaimer. + * 2. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * + * Name: MPI_TYPE.H + * Title: MPI Basic type definitions + * Creation Date: June 6, 2000 + * + * MPI Version: 01.02.01 + * + * Version History + * --------------- + * + * Date Version Description + * -------- -------- ------------------------------------------------------ + * 05-08-00 00.10.01 Original release for 0.10 spec dated 4/26/2000. + * 06-06-00 01.00.01 Update version number for 1.0 release. + * 11-02-00 01.01.01 Original release for post 1.0 work + * 02-20-01 01.01.02 Added define and ifdef for MPI_POINTER. + * 08-08-01 01.02.01 Original release for v1.2 work. + * -------------------------------------------------------------------------- + */ + +#ifndef MPI_TYPE_H +#define MPI_TYPE_H + + +/******************************************************************************* + * Define MPI_POINTER if it hasn't already been defined. By default MPI_POINTER + * is defined to be a near pointer. MPI_POINTER can be defined as a far pointer + * by defining MPI_POINTER as "far *" before this header file is included. + */ +#ifndef MPI_POINTER +#define MPI_POINTER * +#endif + + +/***************************************************************************** +* +* B a s i c T y p e s +* +*****************************************************************************/ + +typedef signed char S8; +typedef unsigned char U8; +typedef signed short S16; +typedef unsigned short U16; + +#if defined(unix) || defined(__arm) || defined(ALPHA) || defined(__GNUC__) + + typedef signed int S32; + typedef unsigned int U32; + +#else + + typedef signed long S32; + typedef unsigned long U32; + +#endif + + +typedef struct _S64 +{ + U32 Low; + S32 High; +} S64; + +typedef struct _U64 +{ + U32 Low; + U32 High; +} U64; + + +/****************************************************************************/ +/* Pointers */ +/****************************************************************************/ + +typedef S8 *PS8; +typedef U8 *PU8; +typedef S16 *PS16; +typedef U16 *PU16; +typedef S32 *PS32; +typedef U32 *PU32; +typedef S64 *PS64; +typedef U64 *PU64; + + +#endif + diff --git a/sys/dev/mpt/mpt.c b/sys/dev/mpt/mpt.c new file mode 100644 index 0000000..8c99e1c --- /dev/null +++ b/sys/dev/mpt/mpt.c @@ -0,0 +1,1189 @@ +/* + +#include <sys/cdefs.h> +__FBSDID("$FreeBSD$"); + * Generic routines for LSI '909 FC adapters. + * FreeBSD Version. + * + * Copyright (c) 2000, 2001 by Greg Ansley + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice immediately at the beginning of the file, without modification, + * this list of conditions, and the following disclaimer. + * 2. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ +/* + * Additional Copyright (c) 2002 by Matthew Jacob under same license. + */ + +#include <dev/mpt/mpt_freebsd.h> + +#define MPT_MAX_TRYS 3 +#define MPT_MAX_WAIT 300000 + +static int maxwait_ack = 0; +static int maxwait_int = 0; +static int maxwait_state = 0; + +static INLINE u_int32_t mpt_rd_db(mpt_softc_t *mpt); +static INLINE u_int32_t mpt_rd_intr(mpt_softc_t *mpt); + +static INLINE u_int32_t +mpt_rd_db(mpt_softc_t *mpt) +{ + return mpt_read(mpt, MPT_OFFSET_DOORBELL); +} + +static INLINE u_int32_t +mpt_rd_intr(mpt_softc_t *mpt) +{ + return mpt_read(mpt, MPT_OFFSET_INTR_STATUS); +} + +/* Busy wait for a door bell to be read by IOC */ +static int +mpt_wait_db_ack(mpt_softc_t *mpt) +{ + int i; + for (i=0; i < MPT_MAX_WAIT; i++) { + if (!MPT_DB_IS_BUSY(mpt_rd_intr(mpt))) { + maxwait_ack = i > maxwait_ack ? i : maxwait_ack; + return MPT_OK; + } + + DELAY(100); + } + return MPT_FAIL; +} + +/* Busy wait for a door bell interrupt */ +static int +mpt_wait_db_int(mpt_softc_t *mpt) +{ + int i; + for (i=0; i < MPT_MAX_WAIT; i++) { + if (MPT_DB_INTR(mpt_rd_intr(mpt))) { + maxwait_int = i > maxwait_int ? i : maxwait_int; + return MPT_OK; + } + DELAY(100); + } + return MPT_FAIL; +} + +/* Wait for IOC to transition to a give state */ +void +mpt_check_doorbell(mpt_softc_t *mpt) +{ + u_int32_t db = mpt_rd_db(mpt); + if (MPT_STATE(db) != MPT_DB_STATE_RUNNING) { + mpt_prt(mpt, "Device not running"); + mpt_print_db(db); + } +} + +/* Wait for IOC to transition to a give state */ +static int +mpt_wait_state(mpt_softc_t *mpt, enum DB_STATE_BITS state) +{ + int i; + + for (i = 0; i < MPT_MAX_WAIT; i++) { + u_int32_t db = mpt_rd_db(mpt); + if (MPT_STATE(db) == state) { + maxwait_state = i > maxwait_state ? i : maxwait_state; + return (MPT_OK); + } + DELAY(100); + } + return (MPT_FAIL); +} + + +/* Issue the reset COMMAND to the IOC */ +int +mpt_soft_reset(mpt_softc_t *mpt) +{ + if (mpt->verbose) { + mpt_prt(mpt, "soft reset"); + } + + /* Have to use hard reset if we are not in Running state */ + if (MPT_STATE(mpt_rd_db(mpt)) != MPT_DB_STATE_RUNNING) { + mpt_prt(mpt, "soft reset failed: device not running"); + return MPT_FAIL; + } + + /* If door bell is in use we don't have a chance of getting + * a word in since the IOC probably crashed in message + * processing. So don't waste our time. + */ + if (MPT_DB_IS_IN_USE(mpt_rd_db(mpt))) { + mpt_prt(mpt, "soft reset failed: doorbell wedged"); + return MPT_FAIL; + } + + /* Send the reset request to the IOC */ + mpt_write(mpt, MPT_OFFSET_DOORBELL, + MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET << MPI_DOORBELL_FUNCTION_SHIFT); + if (mpt_wait_db_ack(mpt) != MPT_OK) { + mpt_prt(mpt, "soft reset failed: ack timeout"); + return MPT_FAIL; + } + + /* Wait for the IOC to reload and come out of reset state */ + if (mpt_wait_state(mpt, MPT_DB_STATE_READY) != MPT_OK) { + mpt_prt(mpt, "soft reset failed: device did not start running"); + return MPT_FAIL; + } + + return MPT_OK; +} + +/* This is a magic diagnostic reset that resets all the ARM + * processors in the chip. + */ +void +mpt_hard_reset(mpt_softc_t *mpt) +{ + /* This extra read comes for the Linux source + * released by LSI. It's function is undocumented! + */ + if (mpt->verbose) { + mpt_prt(mpt, "hard reset"); + } + mpt_read(mpt, MPT_OFFSET_FUBAR); + + /* Enable diagnostic registers */ + mpt_write(mpt, MPT_OFFSET_SEQUENCE, MPT_DIAG_SEQUENCE_1); + mpt_write(mpt, MPT_OFFSET_SEQUENCE, MPT_DIAG_SEQUENCE_2); + mpt_write(mpt, MPT_OFFSET_SEQUENCE, MPT_DIAG_SEQUENCE_3); + mpt_write(mpt, MPT_OFFSET_SEQUENCE, MPT_DIAG_SEQUENCE_4); + mpt_write(mpt, MPT_OFFSET_SEQUENCE, MPT_DIAG_SEQUENCE_5); + + /* Diag. port is now active so we can now hit the reset bit */ + mpt_write(mpt, MPT_OFFSET_DIAGNOSTIC, MPT_DIAG_RESET_IOC); + + DELAY(10000); + + /* Disable Diagnostic Register */ + mpt_write(mpt, MPT_OFFSET_SEQUENCE, 0xFF); + + /* Restore the config register values */ + /* Hard resets are known to screw up the BAR for diagnostic + memory accesses (Mem1). */ + mpt_set_config_regs(mpt); + if (mpt->mpt2 != NULL) { + mpt_set_config_regs(mpt->mpt2); + } + + /* Note that if there is no valid firmware to run, the doorbell will + remain in the reset state (0x00000000) */ +} + +/* + * Reset the IOC when needed. Try software command first then if needed + * poke at the magic diagnostic reset. Note that a hard reset resets + * *both* IOCs on dual function chips (FC929 && LSI1030) as well as + * fouls up the PCI configuration registers. + */ +int +mpt_reset(mpt_softc_t *mpt) +{ + int ret; + + /* Try a soft reset */ + if ((ret = mpt_soft_reset(mpt)) != MPT_OK) { + /* Failed; do a hard reset */ + mpt_hard_reset(mpt); + + /* Wait for the IOC to reload and come out of reset state */ + ret = mpt_wait_state(mpt, MPT_DB_STATE_READY); + if (ret != MPT_OK) { + mpt_prt(mpt, "failed to reset device"); + } + } + + return ret; +} + +/* Return a command buffer to the free queue */ +void +mpt_free_request(mpt_softc_t *mpt, request_t *req) +{ + if (req == NULL || req != &mpt->request_pool[req->index]) { + panic("mpt_free_request bad req ptr\n"); + return; + } + req->sequence = 0; + req->ccb = NULL; + req->debug = REQ_FREE; + SLIST_INSERT_HEAD(&mpt->request_free_list, req, link); +} + +/* Get a command buffer from the free queue */ +request_t * +mpt_get_request(mpt_softc_t *mpt) +{ + request_t *req; + req = SLIST_FIRST(&mpt->request_free_list); + if (req != NULL) { + if (req != &mpt->request_pool[req->index]) { + panic("mpt_get_request: corrupted request free list\n"); + } + if (req->ccb != NULL) { + panic("mpt_get_request: corrupted request free list (ccb)\n"); + } + SLIST_REMOVE_HEAD(&mpt->request_free_list, link); + req->debug = REQ_IN_PROGRESS; + } + return req; +} + +/* Pass the command to the IOC */ +void +mpt_send_cmd(mpt_softc_t *mpt, request_t *req) +{ + req->sequence = mpt->sequence++; + if (mpt->verbose > 1) { + u_int32_t *pReq; + pReq = req->req_vbuf; + mpt_prt(mpt, "Send Request %d (0x%x):", + req->index, req->req_pbuf); + mpt_prt(mpt, "%08x %08x %08x %08x", + pReq[0], pReq[1], pReq[2], pReq[3]); + mpt_prt(mpt, "%08x %08x %08x %08x", + pReq[4], pReq[5], pReq[6], pReq[7]); + mpt_prt(mpt, "%08x %08x %08x %08x", + pReq[8], pReq[9], pReq[10], pReq[11]); + mpt_prt(mpt, "%08x %08x %08x %08x", + pReq[12], pReq[13], pReq[14], pReq[15]); + } + bus_dmamap_sync(mpt->request_dmat, mpt->request_dmap, + BUS_DMASYNC_PREWRITE); + req->debug = REQ_ON_CHIP; + mpt_write(mpt, MPT_OFFSET_REQUEST_Q, (u_int32_t) req->req_pbuf); +} + +/* + * Give the reply buffer back to the IOC after we have + * finished processing it. + */ +void +mpt_free_reply(mpt_softc_t *mpt, u_int32_t ptr) +{ + mpt_write(mpt, MPT_OFFSET_REPLY_Q, ptr); +} + +/* Get a reply from the IOC */ +u_int32_t +mpt_pop_reply_queue(mpt_softc_t *mpt) +{ + return mpt_read(mpt, MPT_OFFSET_REPLY_Q); +} + +/* + * Send a command to the IOC via the handshake register. + * + * Only done at initialization time and for certain unusual + * commands such as device/bus reset as specified by LSI. + */ +int +mpt_send_handshake_cmd(mpt_softc_t *mpt, size_t len, void *cmd) +{ + int i; + u_int32_t data, *data32; + + /* Check condition of the IOC */ + data = mpt_rd_db(mpt); + if (((MPT_STATE(data) != MPT_DB_STATE_READY) && + (MPT_STATE(data) != MPT_DB_STATE_RUNNING) && + (MPT_STATE(data) != MPT_DB_STATE_FAULT)) || + ( MPT_DB_IS_IN_USE(data) )) { + mpt_prt(mpt, "handshake aborted due to invalid doorbell state"); + mpt_print_db(data); + return(EBUSY); + } + + /* We move things in 32 bit chunks */ + len = (len + 3) >> 2; + data32 = cmd; + + /* Clear any left over pending doorbell interupts */ + if (MPT_DB_INTR(mpt_rd_intr(mpt))) + mpt_write(mpt, MPT_OFFSET_INTR_STATUS, 0); + + /* + * Tell the handshake reg. we are going to send a command + * and how long it is going to be. + */ + data = (MPI_FUNCTION_HANDSHAKE << MPI_DOORBELL_FUNCTION_SHIFT) | + (len << MPI_DOORBELL_ADD_DWORDS_SHIFT); + mpt_write(mpt, MPT_OFFSET_DOORBELL, data); + + /* Wait for the chip to notice */ + if (mpt_wait_db_int(mpt) != MPT_OK) { + mpt_prt(mpt, "mpt_send_handshake_cmd timeout1"); + return ETIMEDOUT; + } + + /* Clear the interrupt */ + mpt_write(mpt, MPT_OFFSET_INTR_STATUS, 0); + + if (mpt_wait_db_ack(mpt) != MPT_OK) { + mpt_prt(mpt, "mpt_send_handshake_cmd timeout2"); + return ETIMEDOUT; + } + + /* Send the command */ + for (i = 0; i < len; i++) { + mpt_write(mpt, MPT_OFFSET_DOORBELL, *data32++); + if (mpt_wait_db_ack(mpt) != MPT_OK) { + mpt_prt(mpt, + "mpt_send_handshake_cmd timeout! index = %d", i); + return ETIMEDOUT; + } + } + return MPT_OK; +} + +/* Get the response from the handshake register */ +int +mpt_recv_handshake_reply(mpt_softc_t *mpt, size_t reply_len, void *reply) +{ + int left, reply_left; + u_int16_t *data16; + MSG_DEFAULT_REPLY *hdr; + + /* We move things out in 16 bit chunks */ + reply_len >>= 1; + data16 = (u_int16_t *)reply; + + hdr = (MSG_DEFAULT_REPLY *)reply; + + /* Get first word */ + if (mpt_wait_db_int(mpt) != MPT_OK) { + mpt_prt(mpt, "mpt_recv_handshake_cmd timeout1"); + return ETIMEDOUT; + } + *data16++ = mpt_read(mpt, MPT_OFFSET_DOORBELL) & MPT_DB_DATA_MASK; + mpt_write(mpt, MPT_OFFSET_INTR_STATUS, 0); + + /* Get Second Word */ + if (mpt_wait_db_int(mpt) != MPT_OK) { + mpt_prt(mpt, "mpt_recv_handshake_cmd timeout2"); + return ETIMEDOUT; + } + *data16++ = mpt_read(mpt, MPT_OFFSET_DOORBELL) & MPT_DB_DATA_MASK; + mpt_write(mpt, MPT_OFFSET_INTR_STATUS, 0); + + /* With the second word, we can now look at the length */ + if (mpt->verbose > 1 && ((reply_len >> 1) != hdr->MsgLength)) { + mpt_prt(mpt, "reply length does not match message length: " + "got 0x%02x, expected 0x%02x", + hdr->MsgLength << 2, reply_len << 1); + } + + /* Get rest of the reply; but don't overflow the provided buffer */ + left = (hdr->MsgLength << 1) - 2; + reply_left = reply_len - 2; + while (left--) { + u_int16_t datum; + + if (mpt_wait_db_int(mpt) != MPT_OK) { + mpt_prt(mpt, "mpt_recv_handshake_cmd timeout3"); + return ETIMEDOUT; + } + datum = mpt_read(mpt, MPT_OFFSET_DOORBELL); + + if (reply_left-- > 0) + *data16++ = datum & MPT_DB_DATA_MASK; + + mpt_write(mpt, MPT_OFFSET_INTR_STATUS, 0); + } + + /* One more wait & clear at the end */ + if (mpt_wait_db_int(mpt) != MPT_OK) { + mpt_prt(mpt, "mpt_recv_handshake_cmd timeout4"); + return ETIMEDOUT; + } + mpt_write(mpt, MPT_OFFSET_INTR_STATUS, 0); + + if ((hdr->IOCStatus & MPI_IOCSTATUS_MASK) != MPI_IOCSTATUS_SUCCESS) { + if (mpt->verbose > 1) + mpt_print_reply(hdr); + return (MPT_FAIL | hdr->IOCStatus); + } + + return (0); +} + +static int +mpt_get_iocfacts(mpt_softc_t *mpt, MSG_IOC_FACTS_REPLY *freplp) +{ + MSG_IOC_FACTS f_req; + int error; + + bzero(&f_req, sizeof f_req); + f_req.Function = MPI_FUNCTION_IOC_FACTS; + f_req.MsgContext = 0x12071942; + error = mpt_send_handshake_cmd(mpt, sizeof f_req, &f_req); + if (error) + return(error); + error = mpt_recv_handshake_reply(mpt, sizeof (*freplp), freplp); + return (error); +} + +static int +mpt_get_portfacts(mpt_softc_t *mpt, MSG_PORT_FACTS_REPLY *freplp) +{ + MSG_PORT_FACTS f_req; + int error; + + /* XXX: Only getting PORT FACTS for Port 0 */ + bzero(&f_req, sizeof f_req); + f_req.Function = MPI_FUNCTION_PORT_FACTS; + f_req.MsgContext = 0x12071943; + error = mpt_send_handshake_cmd(mpt, sizeof f_req, &f_req); + if (error) + return(error); + error = mpt_recv_handshake_reply(mpt, sizeof (*freplp), freplp); + return (error); +} + +/* + * Send the initialization request. This is where we specify how many + * SCSI busses and how many devices per bus we wish to emulate. + * This is also the command that specifies the max size of the reply + * frames from the IOC that we will be allocating. + */ +static int +mpt_send_ioc_init(mpt_softc_t *mpt, u_int32_t who) +{ + int error = 0; + MSG_IOC_INIT init; + MSG_IOC_INIT_REPLY reply; + + bzero(&init, sizeof init); + init.WhoInit = who; + init.Function = MPI_FUNCTION_IOC_INIT; + if (mpt->is_fc) { + init.MaxDevices = 255; + } else { + init.MaxDevices = 16; + } + init.MaxBuses = 1; + init.ReplyFrameSize = MPT_REPLY_SIZE; + init.MsgContext = 0x12071941; + + if ((error = mpt_send_handshake_cmd(mpt, sizeof init, &init)) != 0) { + return(error); + } + + error = mpt_recv_handshake_reply(mpt, sizeof reply, &reply); + return (error); +} + + +/* + * Utiltity routine to read configuration headers and pages + */ + +static int +mpt_read_cfg_header(mpt_softc_t *, int, int, int, CONFIG_PAGE_HEADER *); + +static int +mpt_read_cfg_header(mpt_softc_t *mpt, int PageType, int PageNumber, + int PageAddress, CONFIG_PAGE_HEADER *rslt) +{ + int count; + request_t *req; + MSG_CONFIG *cfgp; + MSG_CONFIG_REPLY *reply; + + req = mpt_get_request(mpt); + + cfgp = req->req_vbuf; + bzero(cfgp, sizeof *cfgp); + + cfgp->Action = MPI_CONFIG_ACTION_PAGE_HEADER; + cfgp->Function = MPI_FUNCTION_CONFIG; + cfgp->Header.PageNumber = (U8) PageNumber; + cfgp->Header.PageType = (U8) PageType; + cfgp->PageAddress = PageAddress; + MPI_pSGE_SET_FLAGS(((SGE_SIMPLE32 *) &cfgp->PageBufferSGE), + (MPI_SGE_FLAGS_LAST_ELEMENT | MPI_SGE_FLAGS_END_OF_BUFFER | + MPI_SGE_FLAGS_SIMPLE_ELEMENT | MPI_SGE_FLAGS_END_OF_LIST)); + cfgp->MsgContext = req->index | 0x80000000; + + mpt_check_doorbell(mpt); + mpt_send_cmd(mpt, req); + count = 0; + do { + DELAY(500); + mpt_intr(mpt); + if (++count == 1000) { + mpt_prt(mpt, "read_cfg_header timed out"); + return (-1); + } + } while (req->debug == REQ_ON_CHIP); + + reply = (MSG_CONFIG_REPLY *) MPT_REPLY_PTOV(mpt, req->sequence); + if ((reply->IOCStatus & MPI_IOCSTATUS_MASK) != MPI_IOCSTATUS_SUCCESS) { + mpt_prt(mpt, "mpt_read_cfg_header: Config Info Status %x", + reply->IOCStatus); + mpt_free_reply(mpt, (req->sequence << 1)); + return (-1); + } + bcopy(&reply->Header, rslt, sizeof (CONFIG_PAGE_HEADER)); + mpt_free_reply(mpt, (req->sequence << 1)); + mpt_free_request(mpt, req); + return (0); +} + +#define CFG_DATA_OFF 128 + +int +mpt_read_cfg_page(mpt_softc_t *mpt, int PageAddress, CONFIG_PAGE_HEADER *hdr) +{ + int count; + request_t *req; + SGE_SIMPLE32 *se; + MSG_CONFIG *cfgp; + size_t amt; + MSG_CONFIG_REPLY *reply; + + req = mpt_get_request(mpt); + + cfgp = req->req_vbuf; + bzero(cfgp, MPT_REQUEST_AREA); + cfgp->Action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT; + cfgp->Function = MPI_FUNCTION_CONFIG; + cfgp->Header = *hdr; + amt = (cfgp->Header.PageLength * sizeof (u_int32_t)); + cfgp->Header.PageType &= MPI_CONFIG_PAGETYPE_MASK; + cfgp->PageAddress = PageAddress; + se = (SGE_SIMPLE32 *) &cfgp->PageBufferSGE; + se->Address = req->req_pbuf + CFG_DATA_OFF; + MPI_pSGE_SET_LENGTH(se, amt); + MPI_pSGE_SET_FLAGS(se, (MPI_SGE_FLAGS_SIMPLE_ELEMENT | + MPI_SGE_FLAGS_LAST_ELEMENT | MPI_SGE_FLAGS_END_OF_BUFFER | + MPI_SGE_FLAGS_END_OF_LIST)); + + cfgp->MsgContext = req->index | 0x80000000; + + mpt_check_doorbell(mpt); + mpt_send_cmd(mpt, req); + count = 0; + do { + DELAY(500); + mpt_intr(mpt); + if (++count == 1000) { + mpt_prt(mpt, "read_cfg_page timed out"); + return (-1); + } + } while (req->debug == REQ_ON_CHIP); + + reply = (MSG_CONFIG_REPLY *) MPT_REPLY_PTOV(mpt, req->sequence); + if ((reply->IOCStatus & MPI_IOCSTATUS_MASK) != MPI_IOCSTATUS_SUCCESS) { + mpt_prt(mpt, "mpt_read_cfg_page: Config Info Status %x", + reply->IOCStatus); + mpt_free_reply(mpt, (req->sequence << 1)); + return (-1); + } + mpt_free_reply(mpt, (req->sequence << 1)); + bus_dmamap_sync(mpt->request_dmat, mpt->request_dmap, + BUS_DMASYNC_POSTREAD); + if (cfgp->Header.PageType == MPI_CONFIG_PAGETYPE_SCSI_PORT && + cfgp->Header.PageNumber == 0) { + amt = sizeof (CONFIG_PAGE_SCSI_PORT_0); + } else if (cfgp->Header.PageType == MPI_CONFIG_PAGETYPE_SCSI_PORT && + cfgp->Header.PageNumber == 1) { + amt = sizeof (CONFIG_PAGE_SCSI_PORT_1); + } else if (cfgp->Header.PageType == MPI_CONFIG_PAGETYPE_SCSI_PORT && + cfgp->Header.PageNumber == 2) { + amt = sizeof (CONFIG_PAGE_SCSI_PORT_2); + } else if (cfgp->Header.PageType == MPI_CONFIG_PAGETYPE_SCSI_DEVICE && + cfgp->Header.PageNumber == 0) { + amt = sizeof (CONFIG_PAGE_SCSI_DEVICE_0); + } else if (cfgp->Header.PageType == MPI_CONFIG_PAGETYPE_SCSI_DEVICE && + cfgp->Header.PageNumber == 1) { + amt = sizeof (CONFIG_PAGE_SCSI_DEVICE_1); + } + bcopy(((caddr_t)req->req_vbuf)+CFG_DATA_OFF, hdr, amt); + mpt_free_request(mpt, req); + return (0); +} + +int +mpt_write_cfg_page(mpt_softc_t *mpt, int PageAddress, CONFIG_PAGE_HEADER *hdr) +{ + int count, hdr_attr; + request_t *req; + SGE_SIMPLE32 *se; + MSG_CONFIG *cfgp; + size_t amt; + MSG_CONFIG_REPLY *reply; + + req = mpt_get_request(mpt); + + cfgp = req->req_vbuf; + bzero(cfgp, sizeof *cfgp); + + hdr_attr = hdr->PageType & MPI_CONFIG_PAGEATTR_MASK; + if (hdr_attr != MPI_CONFIG_PAGEATTR_CHANGEABLE && + hdr_attr != MPI_CONFIG_PAGEATTR_PERSISTENT) { + mpt_prt(mpt, "page type 0x%x not changeable", + hdr->PageType & MPI_CONFIG_PAGETYPE_MASK); + return (-1); + } + hdr->PageType &= MPI_CONFIG_PAGETYPE_MASK; + + cfgp->Action = MPI_CONFIG_ACTION_PAGE_WRITE_CURRENT; + cfgp->Function = MPI_FUNCTION_CONFIG; + cfgp->Header = *hdr; + amt = (cfgp->Header.PageLength * sizeof (u_int32_t)); + cfgp->PageAddress = PageAddress; + + se = (SGE_SIMPLE32 *) &cfgp->PageBufferSGE; + se->Address = req->req_pbuf + CFG_DATA_OFF; + MPI_pSGE_SET_LENGTH(se, amt); + MPI_pSGE_SET_FLAGS(se, (MPI_SGE_FLAGS_SIMPLE_ELEMENT | + MPI_SGE_FLAGS_LAST_ELEMENT | MPI_SGE_FLAGS_END_OF_BUFFER | + MPI_SGE_FLAGS_END_OF_LIST | MPI_SGE_FLAGS_HOST_TO_IOC)); + + cfgp->MsgContext = req->index | 0x80000000; + + if (cfgp->Header.PageType == MPI_CONFIG_PAGETYPE_SCSI_PORT && + cfgp->Header.PageNumber == 0) { + amt = sizeof (CONFIG_PAGE_SCSI_PORT_0); + } else if (cfgp->Header.PageType == MPI_CONFIG_PAGETYPE_SCSI_PORT && + cfgp->Header.PageNumber == 1) { + amt = sizeof (CONFIG_PAGE_SCSI_PORT_1); + } else if (cfgp->Header.PageType == MPI_CONFIG_PAGETYPE_SCSI_PORT && + cfgp->Header.PageNumber == 2) { + amt = sizeof (CONFIG_PAGE_SCSI_PORT_2); + } else if (cfgp->Header.PageType == MPI_CONFIG_PAGETYPE_SCSI_DEVICE && + cfgp->Header.PageNumber == 0) { + amt = sizeof (CONFIG_PAGE_SCSI_DEVICE_0); + } else if (cfgp->Header.PageType == MPI_CONFIG_PAGETYPE_SCSI_DEVICE && + cfgp->Header.PageNumber == 1) { + amt = sizeof (CONFIG_PAGE_SCSI_DEVICE_1); + } + bcopy(hdr, ((caddr_t)req->req_vbuf)+CFG_DATA_OFF, amt); + /* Restore stripped out attributes */ + hdr->PageType |= hdr_attr; + + mpt_check_doorbell(mpt); + mpt_send_cmd(mpt, req); + count = 0; + do { + DELAY(500); + mpt_intr(mpt); + if (++count == 1000) { + hdr->PageType |= hdr_attr; + mpt_prt(mpt, "mpt_write_cfg_page timed out"); + return (-1); + } + } while (req->debug == REQ_ON_CHIP); + + reply = (MSG_CONFIG_REPLY *) MPT_REPLY_PTOV(mpt, req->sequence); + if ((reply->IOCStatus & MPI_IOCSTATUS_MASK) != MPI_IOCSTATUS_SUCCESS) { + mpt_prt(mpt, "mpt_write_cfg_page: Config Info Status %x", + reply->IOCStatus); + mpt_free_reply(mpt, (req->sequence << 1)); + return (-1); + } + mpt_free_reply(mpt, (req->sequence << 1)); + + mpt_free_request(mpt, req); + return (0); +} + +/* + * Read SCSI configuration information + */ +static int +mpt_read_config_info_spi(mpt_softc_t *mpt) +{ + int rv, i; + + rv = mpt_read_cfg_header(mpt, MPI_CONFIG_PAGETYPE_SCSI_PORT, 0, + 0, &mpt->mpt_port_page0.Header); + if (rv) { + return (-1); + } + if (mpt->verbose > 1) { + mpt_prt(mpt, "SPI Port Page 0 Header: %x %x %x %x", + mpt->mpt_port_page0.Header.PageVersion, + mpt->mpt_port_page0.Header.PageLength, + mpt->mpt_port_page0.Header.PageNumber, + mpt->mpt_port_page0.Header.PageType); + } + + rv = mpt_read_cfg_header(mpt, MPI_CONFIG_PAGETYPE_SCSI_PORT, 1, + 0, &mpt->mpt_port_page1.Header); + if (rv) { + return (-1); + } + if (mpt->verbose > 1) { + mpt_prt(mpt, "SPI Port Page 1 Header: %x %x %x %x", + mpt->mpt_port_page1.Header.PageVersion, + mpt->mpt_port_page1.Header.PageLength, + mpt->mpt_port_page1.Header.PageNumber, + mpt->mpt_port_page1.Header.PageType); + } + + rv = mpt_read_cfg_header(mpt, MPI_CONFIG_PAGETYPE_SCSI_PORT, 2, + 0, &mpt->mpt_port_page2.Header); + if (rv) { + return (-1); + } + + if (mpt->verbose > 1) { + mpt_prt(mpt, "SPI Port Page 2 Header: %x %x %x %x", + mpt->mpt_port_page1.Header.PageVersion, + mpt->mpt_port_page1.Header.PageLength, + mpt->mpt_port_page1.Header.PageNumber, + mpt->mpt_port_page1.Header.PageType); + } + + for (i = 0; i < 16; i++) { + rv = mpt_read_cfg_header(mpt, MPI_CONFIG_PAGETYPE_SCSI_DEVICE, + 0, i, &mpt->mpt_dev_page0[i].Header); + if (rv) { + return (-1); + } + if (mpt->verbose > 1) { + mpt_prt(mpt, + "SPI Target %d Device Page 0 Header: %x %x %x %x", + i, mpt->mpt_dev_page0[i].Header.PageVersion, + mpt->mpt_dev_page0[i].Header.PageLength, + mpt->mpt_dev_page0[i].Header.PageNumber, + mpt->mpt_dev_page0[i].Header.PageType); + } + + rv = mpt_read_cfg_header(mpt, MPI_CONFIG_PAGETYPE_SCSI_DEVICE, + 1, i, &mpt->mpt_dev_page1[i].Header); + if (rv) { + return (-1); + } + if (mpt->verbose > 1) { + mpt_prt(mpt, + "SPI Target %d Device Page 1 Header: %x %x %x %x", + i, mpt->mpt_dev_page1[i].Header.PageVersion, + mpt->mpt_dev_page1[i].Header.PageLength, + mpt->mpt_dev_page1[i].Header.PageNumber, + mpt->mpt_dev_page1[i].Header.PageType); + } + } + + /* + * At this point, we don't *have* to fail. As long as we have + * valid config header information, we can (barely) lurch + * along. + */ + + rv = mpt_read_cfg_page(mpt, 0, &mpt->mpt_port_page0.Header); + if (rv) { + mpt_prt(mpt, "failed to read SPI Port Page 0"); + } else if (mpt->verbose > 1) { + mpt_prt(mpt, + "SPI Port Page 0: Capabilities %x PhysicalInterface %x", + mpt->mpt_port_page0.Capabilities, + mpt->mpt_port_page0.PhysicalInterface); + } + + rv = mpt_read_cfg_page(mpt, 0, &mpt->mpt_port_page1.Header); + if (rv) { + mpt_prt(mpt, "failed to read SPI Port Page 1"); + } else if (mpt->verbose > 1) { + mpt_prt(mpt, + "SPI Port Page 1: Configuration %x OnBusTimerValue %x", + mpt->mpt_port_page1.Configuration, + mpt->mpt_port_page1.OnBusTimerValue); + } + + rv = mpt_read_cfg_page(mpt, 0, &mpt->mpt_port_page2.Header); + if (rv) { + mpt_prt(mpt, "failed to read SPI Port Page 2"); + } else if (mpt->verbose > 1) { + mpt_prt(mpt, + "SPI Port Page 2: Flags %x Settings %x", + mpt->mpt_port_page2.PortFlags, + mpt->mpt_port_page2.PortSettings); + for (i = 0; i < 16; i++) { + mpt_prt(mpt, + "SPI Port Page 2 Tgt %d: timo %x SF %x Flags %x", + i, mpt->mpt_port_page2.DeviceSettings[i].Timeout, + mpt->mpt_port_page2.DeviceSettings[i].SyncFactor, + mpt->mpt_port_page2.DeviceSettings[i].DeviceFlags); + } + } + + for (i = 0; i < 16; i++) { + rv = mpt_read_cfg_page(mpt, i, &mpt->mpt_dev_page0[i].Header); + if (rv) { + mpt_prt(mpt, "cannot read SPI Tgt %d Device Page 0", i); + continue; + } + if (mpt->verbose > 1) { + mpt_prt(mpt, + "SPI Tgt %d Page 0: NParms %x Information %x", + i, mpt->mpt_dev_page0[i].NegotiatedParameters, + mpt->mpt_dev_page0[i].Information); + } + rv = mpt_read_cfg_page(mpt, i, &mpt->mpt_dev_page1[i].Header); + if (rv) { + mpt_prt(mpt, "cannot read SPI Tgt %d Device Page 1", i); + continue; + } + if (mpt->verbose > 1) { + mpt_prt(mpt, + "SPI Tgt %d Page 1: RParms %x Configuration %x", + i, mpt->mpt_dev_page1[i].RequestedParameters, + mpt->mpt_dev_page1[i].Configuration); + } + } + return (0); +} + +/* + * Validate SPI configuration information. + * + * In particular, validate SPI Port Page 1. + */ +static int +mpt_set_initial_config_spi(mpt_softc_t *mpt) +{ + int i, pp1val = ((1 << mpt->mpt_ini_id) << 16) | mpt->mpt_ini_id; + + mpt->mpt_disc_enable = 0xff; + mpt->mpt_tag_enable = 0; + + if (mpt->mpt_port_page1.Configuration != pp1val) { + CONFIG_PAGE_SCSI_PORT_1 tmp; + mpt_prt(mpt, + "SPI Port Page 1 Config value bad (%x)- should be %x", + mpt->mpt_port_page1.Configuration, pp1val); + tmp = mpt->mpt_port_page1; + tmp.Configuration = pp1val; + if (mpt_write_cfg_page(mpt, 0, &tmp.Header)) { + return (-1); + } + if (mpt_read_cfg_page(mpt, 0, &tmp.Header)) { + return (-1); + } + if (tmp.Configuration != pp1val) { + mpt_prt(mpt, + "failed to reset SPI Port Page 1 Config value"); + return (-1); + } + mpt->mpt_port_page1 = tmp; + } + + for (i = 0; i < 16; i++) { + CONFIG_PAGE_SCSI_DEVICE_1 tmp; + tmp = mpt->mpt_dev_page1[i]; + tmp.RequestedParameters = 0; + tmp.Configuration = 0; + if (mpt->verbose > 1) { + mpt_prt(mpt, + "Set Tgt %d SPI DevicePage 1 values to %x 0 %x", + i, tmp.RequestedParameters, tmp.Configuration); + } + if (mpt_write_cfg_page(mpt, i, &tmp.Header)) { + return (-1); + } + if (mpt_read_cfg_page(mpt, i, &tmp.Header)) { + return (-1); + } + mpt->mpt_dev_page1[i] = tmp; + if (mpt->verbose > 1) { + mpt_prt(mpt, + "SPI Tgt %d Page 1: RParm %x Configuration %x", i, + mpt->mpt_dev_page1[i].RequestedParameters, + mpt->mpt_dev_page1[i].Configuration); + } + } + return (0); +} + +/* + * Enable IOC port + */ +static int +mpt_send_port_enable(mpt_softc_t *mpt, int port) +{ + int count; + request_t *req; + MSG_PORT_ENABLE *enable_req; + + req = mpt_get_request(mpt); + + enable_req = req->req_vbuf; + bzero(enable_req, sizeof *enable_req); + + enable_req->Function = MPI_FUNCTION_PORT_ENABLE; + enable_req->MsgContext = req->index | 0x80000000; + enable_req->PortNumber = port; + + mpt_check_doorbell(mpt); + if (mpt->verbose > 1) { + mpt_prt(mpt, "enabling port %d", port); + } + mpt_send_cmd(mpt, req); + + count = 0; + do { + DELAY(500); + mpt_intr(mpt); + if (++count == 100000) { + mpt_prt(mpt, "port enable timed out"); + return (-1); + } + } while (req->debug == REQ_ON_CHIP); + mpt_free_request(mpt, req); + return (0); +} + +/* + * Enable/Disable asynchronous event reporting. + * + * NB: this is the first command we send via shared memory + * instead of the handshake register. + */ +static int +mpt_send_event_request(mpt_softc_t *mpt, int onoff) +{ + request_t *req; + MSG_EVENT_NOTIFY *enable_req; + + req = mpt_get_request(mpt); + + enable_req = req->req_vbuf; + bzero(enable_req, sizeof *enable_req); + + enable_req->Function = MPI_FUNCTION_EVENT_NOTIFICATION; + enable_req->MsgContext = req->index | 0x80000000; + enable_req->Switch = onoff; + + mpt_check_doorbell(mpt); + if (mpt->verbose > 1) { + mpt_prt(mpt, "%sabling async events", onoff? "en" : "dis"); + } + mpt_send_cmd(mpt, req); + + return (0); +} + +/* + * Un-mask the interupts on the chip. + */ +void +mpt_enable_ints(mpt_softc_t *mpt) +{ + /* Unmask every thing except door bell int */ + mpt_write(mpt, MPT_OFFSET_INTR_MASK, MPT_INTR_DB_MASK); +} + +/* + * Mask the interupts on the chip. + */ +void +mpt_disable_ints(mpt_softc_t *mpt) +{ + /* Mask all interrupts */ + mpt_write(mpt, MPT_OFFSET_INTR_MASK, + MPT_INTR_REPLY_MASK | MPT_INTR_DB_MASK); +} + +/* (Re)Initialize the chip for use */ +int +mpt_init(mpt_softc_t *mpt, u_int32_t who) +{ + int try; + MSG_IOC_FACTS_REPLY facts; + MSG_PORT_FACTS_REPLY pfp; + u_int32_t pptr; + int val; + + /* Put all request buffers (back) on the free list */ + SLIST_INIT(&mpt->request_free_list); + for (val = 0; val < MPT_MAX_REQUESTS(mpt); val++) { + mpt_free_request(mpt, &mpt->request_pool[val]); + } + + if (mpt->verbose > 1) { + mpt_prt(mpt, "doorbell req = %s", + mpt_ioc_diag(mpt_read(mpt, MPT_OFFSET_DOORBELL))); + } + + /* + * Start by making sure we're not at FAULT or RESET state + */ + switch (mpt_rd_db(mpt) & MPT_DB_STATE_MASK) { + case MPT_DB_STATE_RESET: + case MPT_DB_STATE_FAULT: + if (mpt_reset(mpt) != MPT_OK) { + return (EIO); + } + default: + break; + } + + for (try = 0; try < MPT_MAX_TRYS; try++) { + /* + * No need to reset if the IOC is already in the READY state. + * + * Force reset if initialization failed previously. + * Note that a hard_reset of the second channel of a '929 + * will stop operation of the first channel. Hopefully, if the + * first channel is ok, the second will not require a hard + * reset. + */ + if ((mpt_rd_db(mpt) & MPT_DB_STATE_MASK) != + MPT_DB_STATE_READY) { + if (mpt_reset(mpt) != MPT_OK) { + DELAY(10000); + continue; + } + } + + if (mpt_get_iocfacts(mpt, &facts) != MPT_OK) { + mpt_prt(mpt, "mpt_get_iocfacts failed"); + continue; + } + + if (mpt->verbose > 1) { + mpt_prt(mpt, + "IOCFACTS: GlobalCredits=%d BlockSize=%u " + "Request Frame Size %u\n", facts.GlobalCredits, + facts.BlockSize, facts.RequestFrameSize); + } + mpt->mpt_global_credits = facts.GlobalCredits; + mpt->request_frame_size = facts.RequestFrameSize; + + if (mpt_get_portfacts(mpt, &pfp) != MPT_OK) { + mpt_prt(mpt, "mpt_get_portfacts failed"); + continue; + } + + if (mpt->verbose > 1) { + mpt_prt(mpt, + "PORTFACTS: Type %x PFlags %x IID %d MaxDev %d\n", + pfp.PortType, pfp.ProtocolFlags, pfp.PortSCSIID, + pfp.MaxDevices); + } + + if (pfp.PortType != MPI_PORTFACTS_PORTTYPE_SCSI && + pfp.PortType != MPI_PORTFACTS_PORTTYPE_FC) { + mpt_prt(mpt, "Unsupported Port Type (%x)", + pfp.PortType); + return (ENXIO); + } + if (!(pfp.ProtocolFlags & MPI_PORTFACTS_PROTOCOL_INITIATOR)) { + mpt_prt(mpt, "initiator role unsupported"); + return (ENXIO); + } + if (pfp.PortType == MPI_PORTFACTS_PORTTYPE_FC) { + mpt->is_fc = 1; + } else { + mpt->is_fc = 0; + } + mpt->mpt_ini_id = pfp.PortSCSIID; + + if (mpt_send_ioc_init(mpt, who) != MPT_OK) { + mpt_prt(mpt, "mpt_send_ioc_init failed"); + continue; + } + + if (mpt->verbose > 1) { + mpt_prt(mpt, "mpt_send_ioc_init ok"); + } + + if (mpt_wait_state(mpt, MPT_DB_STATE_RUNNING) != MPT_OK) { + mpt_prt(mpt, "IOC failed to go to run state"); + continue; + } + if (mpt->verbose > 1) { + mpt_prt(mpt, "IOC now at RUNSTATE"); + } + + /* + * Give it reply buffers + * + * Do *not* except global credits. + */ + for (val = 0, pptr = mpt->reply_phys; + (pptr + MPT_REPLY_SIZE) < (mpt->reply_phys + PAGE_SIZE); + pptr += MPT_REPLY_SIZE) { + mpt_free_reply(mpt, pptr); + if (++val == mpt->mpt_global_credits - 1) + break; + } + + /* + * Enable asynchronous event reporting + */ + mpt_send_event_request(mpt, 1); + + + /* + * Read set up initial configuration information + * (SPI only for now) + */ + + if (mpt->is_fc == 0) { + if (mpt_read_config_info_spi(mpt)) { + return (EIO); + } + if (mpt_set_initial_config_spi(mpt)) { + return (EIO); + } + } + + /* + * Now enable the port + */ + if (mpt_send_port_enable(mpt, 0) != MPT_OK) { + mpt_prt(mpt, "failed to enable port 0"); + continue; + } + + if (mpt->verbose > 1) { + mpt_prt(mpt, "enabled port 0"); + } + + /* Everything worked */ + break; + } + + if (try >= MPT_MAX_TRYS) { + mpt_prt(mpt, "failed to initialize IOC"); + return (EIO); + } + + if (mpt->verbose > 1) { + mpt_prt(mpt, "enabling interrupts"); + } + + mpt_enable_ints(mpt); + return (0); +} diff --git a/sys/dev/mpt/mpt.h b/sys/dev/mpt/mpt.h new file mode 100644 index 0000000..82e8cf5 --- /dev/null +++ b/sys/dev/mpt/mpt.h @@ -0,0 +1,179 @@ +/* $FreeBSD$ */ +/* + * Generic defines for LSI '909 FC adapters. + * FreeBSD Version. + * + * Copyright (c) 2000, 2001 by Greg Ansley + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice immediately at the beginning of the file, without modification, + * this list of conditions, and the following disclaimer. + * 2. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ +/* + * Additional Copyright (c) 2002 by Matthew Jacob under same license. + */ + +#ifndef _MPT_H_ +#define _MPT_H_ +#include <dev/mpt/mpt_freebsd.h> +#define MPT_OK (0) +#define MPT_FAIL (0x10000) + +/* Register Offset to chip registers */ +#define MPT_OFFSET_DOORBELL 0x00 +#define MPT_OFFSET_SEQUENCE 0x04 +#define MPT_OFFSET_DIAGNOSTIC 0x08 +#define MPT_OFFSET_TEST 0x0C +#define MPT_OFFSET_INTR_STATUS 0x30 +#define MPT_OFFSET_INTR_MASK 0x34 +#define MPT_OFFSET_REQUEST_Q 0x40 +#define MPT_OFFSET_REPLY_Q 0x44 +#define MPT_OFFSET_HOST_INDEX 0x50 +#define MPT_OFFSET_FUBAR 0x90 + +#define MPT_DIAG_SEQUENCE_1 0x04 +#define MPT_DIAG_SEQUENCE_2 0x0b +#define MPT_DIAG_SEQUENCE_3 0x02 +#define MPT_DIAG_SEQUENCE_4 0x07 +#define MPT_DIAG_SEQUENCE_5 0x0d + +/* Bit Maps for DOORBELL register */ +enum DB_STATE_BITS { + MPT_DB_STATE_RESET = 0x00000000, + MPT_DB_STATE_READY = 0x10000000, + MPT_DB_STATE_RUNNING = 0x20000000, + MPT_DB_STATE_FAULT = 0x40000000, + MPT_DB_STATE_MASK = 0xf0000000 +}; + +#define MPT_STATE(v) ((enum DB_STATE_BITS)((v) & MPT_DB_STATE_MASK)) + +#define MPT_DB_LENGTH_SHIFT (16) +#define MPT_DB_DATA_MASK (0xffff) + +#define MPT_DB_DB_USED 0x08000000 +#define MPT_DB_IS_IN_USE(v) (((v) & MPT_DB_DB_USED) != 0) + +/* + * "Whom" initializor values + */ +#define MPT_DB_INIT_NOONE 0x00 +#define MPT_DB_INIT_BIOS 0x01 +#define MPT_DB_INIT_ROMBIOS 0x02 +#define MPT_DB_INIT_PCIPEER 0x03 +#define MPT_DB_INIT_HOST 0x04 +#define MPT_DB_INIT_MANUFACTURE 0x05 + +#define MPT_WHO(v) \ + ((v & MPI_DOORBELL_WHO_INIT_MASK) >> MPI_DOORBELL_WHO_INIT_SHIFT) + +/* Function Maps for DOORBELL register */ +enum DB_FUNCTION_BITS { + MPT_FUNC_IOC_RESET = 0x40000000, + MPT_FUNC_UNIT_RESET = 0x41000000, + MPT_FUNC_HANDSHAKE = 0x42000000, + MPT_FUNC_REPLY_REMOVE = 0x43000000, + MPT_FUNC_MASK = 0xff000000 +}; + +/* Function Maps for INTERRUPT request register */ +enum _MPT_INTR_REQ_BITS { + MPT_INTR_DB_BUSY = 0x80000000, + MPT_INTR_REPLY_READY = 0x00000008, + MPT_INTR_DB_READY = 0x00000001 +}; + +#define MPT_DB_IS_BUSY(v) (((v) & MPT_INTR_DB_BUSY) != 0) +#define MPT_DB_INTR(v) (((v) & MPT_INTR_DB_READY) != 0) +#define MPT_REPLY_INTR(v) (((v) & MPT_INTR_REPLY_READY) != 0) + +/* Function Maps for INTERRUPT make register */ +enum _MPT_INTR_MASK_BITS { + MPT_INTR_REPLY_MASK = 0x00000008, + MPT_INTR_DB_MASK = 0x00000001 +}; + +/* Function Maps for DIAGNOSTIC make register */ +enum _MPT_DIAG_BITS { + MPT_DIAG_ENABLED = 0x00000080, + MPT_DIAG_FLASHBAD = 0x00000040, + MPT_DIAG_RESET_HIST = 0x00000020, + MPT_DIAG_TTLI = 0x00000008, + MPT_DIAG_RESET_IOC = 0x00000004, + MPT_DIAG_ARM_DISABLE = 0x00000002, + MPT_DIAG_DME = 0x00000001 +}; + +/* Magic addresses in diagnostic memory space */ +#define MPT_DIAG_IOP_BASE (0x00000000) +#define MPT_DIAG_IOP_SIZE (0x00002000) +#define MPT_DIAG_GPIO (0x00030010) +#define MPT_DIAG_IOPQ_REG_BASE0 (0x00050004) +#define MPT_DIAG_IOPQ_REG_BASE1 (0x00051004) +#define MPT_DIAG_MEM_CFG_BASE (0x00040000) +#define MPT_DIAG_CTX0_BASE (0x000E0000) +#define MPT_DIAG_CTX0_SIZE (0x00002000) +#define MPT_DIAG_CTX1_BASE (0x001E0000) +#define MPT_DIAG_CTX1_SIZE (0x00002000) +#define MPT_DIAG_FLASH_BASE (0x00800000) +#define MPT_DIAG_RAM_BASE (0x01000000) +#define MPT_DIAG_RAM_SIZE (0x00400000) + +/* GPIO bit assignments */ +#define MPT_DIAG_GPIO_SCL (0x00010000) +#define MPT_DIAG_GPIO_SDA_OUT (0x00008000) +#define MPT_DIAG_GPIO_SDA_IN (0x00004000) + +#define MPT_REPLY_EMPTY (0xffffffff) /* Reply Queue Empty Symbol */ +#define MPT_CONTEXT_REPLY (0x80000000) +#define MPT_CONTEXT_MASK (~0xE0000000) + +#ifdef _KERNEL +int mpt_soft_reset(mpt_softc_t *mpt); +void mpt_hard_reset(mpt_softc_t *mpt); +int mpt_recv_handshake_reply(mpt_softc_t *mpt, size_t reply_len, void *reply); + +void mpt_send_cmd(mpt_softc_t *mpt, request_t *req); +void mpt_free_reply(mpt_softc_t *mpt, u_int32_t ptr); +void mpt_enable_ints(mpt_softc_t *mpt); +void mpt_disable_ints(mpt_softc_t *mpt); +u_int32_t mpt_pop_reply_queue(mpt_softc_t *mpt); +int mpt_init(mpt_softc_t *mpt, u_int32_t who); +int mpt_reset(mpt_softc_t *mpt); +int mpt_send_handshake_cmd(mpt_softc_t *mpt, size_t len, void *cmd); +request_t * mpt_get_request(mpt_softc_t *mpt); +void mpt_free_request(mpt_softc_t *mpt, request_t *req); +int mpt_intr(void *dummy); +void mpt_check_doorbell(mpt_softc_t * mpt); + +int mpt_read_cfg_page(mpt_softc_t *, int, CONFIG_PAGE_HEADER *); +int mpt_write_cfg_page(mpt_softc_t *, int, CONFIG_PAGE_HEADER *); + +/* mpt_debug.c functions */ +void mpt_print_reply(void *vmsg); +void mpt_print_db(u_int32_t mb); +void mpt_print_config_reply(void *vmsg); +char *mpt_ioc_diag(u_int32_t diag); +char *mpt_req_state(enum mpt_req_state state); +void mpt_print_scsi_io_request(MSG_SCSI_IO_REQUEST *msg); +void mpt_print_config_request(void *vmsg); +void mpt_print_request(void *vmsg); +#endif +#endif /* _MPT_H_ */ diff --git a/sys/dev/mpt/mpt_debug.c b/sys/dev/mpt/mpt_debug.c new file mode 100644 index 0000000..bbab51b --- /dev/null +++ b/sys/dev/mpt/mpt_debug.c @@ -0,0 +1,608 @@ +/* + +#include <sys/cdefs.h> +__FBSDID("$FreeBSD$"); + * Debug routines for LSI '909 FC adapters. + * FreeBSD Version. + * + * Copyright (c) 2000, 2001 by Greg Ansley + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice immediately at the beginning of the file, without modification, + * this list of conditions, and the following disclaimer. + * 2. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ +/* + * Additional Copyright (c) 2002 by Matthew Jacob under same license. + */ + +#include <dev/mpt/mpt_freebsd.h> +#include <machine/stdarg.h> /* for use by mpt_prt below */ + +struct Error_Map { + int Error_Code; + char *Error_String; +}; + +static const struct Error_Map IOC_Status[] = { +{ MPI_IOCSTATUS_SUCCESS, "Success" }, +{ MPI_IOCSTATUS_INVALID_FUNCTION, "IOC: Invalid Function" }, +{ MPI_IOCSTATUS_BUSY, "IOC: Busy" }, +{ MPI_IOCSTATUS_INVALID_SGL, "IOC: Invalid SGL" }, +{ MPI_IOCSTATUS_INTERNAL_ERROR, "IOC: Internal Error" }, +{ MPI_IOCSTATUS_RESERVED, "IOC: Reserved" }, +{ MPI_IOCSTATUS_INSUFFICIENT_RESOURCES, "IOC: Insufficient Resources" }, +{ MPI_IOCSTATUS_INVALID_FIELD, "IOC: Invalid Field" }, +{ MPI_IOCSTATUS_INVALID_STATE, "IOC: Invalid State" }, +{ MPI_IOCSTATUS_CONFIG_INVALID_ACTION, "Invalid Action" }, +{ MPI_IOCSTATUS_CONFIG_INVALID_TYPE, "Invalid Type" }, +{ MPI_IOCSTATUS_CONFIG_INVALID_PAGE, "Invalid Page" }, +{ MPI_IOCSTATUS_CONFIG_INVALID_DATA, "Invalid Data" }, +{ MPI_IOCSTATUS_CONFIG_NO_DEFAULTS, "No Defaults" }, +{ MPI_IOCSTATUS_CONFIG_CANT_COMMIT, "Can't Commit" }, +{ MPI_IOCSTATUS_SCSI_RECOVERED_ERROR, "SCSI: Recoverd Error" }, +{ MPI_IOCSTATUS_SCSI_INVALID_BUS, "SCSI: Invalid Bus" }, +{ MPI_IOCSTATUS_SCSI_INVALID_TARGETID, "SCSI: Invalid Target ID" }, +{ MPI_IOCSTATUS_SCSI_DEVICE_NOT_THERE, "SCSI: Device Not There" }, +{ MPI_IOCSTATUS_SCSI_DATA_OVERRUN, "SCSI: Data Overrun" }, +{ MPI_IOCSTATUS_SCSI_DATA_UNDERRUN, "SCSI: Data Underrun" }, +{ MPI_IOCSTATUS_SCSI_IO_DATA_ERROR, "SCSI: Data Error" }, +{ MPI_IOCSTATUS_SCSI_PROTOCOL_ERROR, "SCSI: Protocol Error" }, +{ MPI_IOCSTATUS_SCSI_TASK_TERMINATED, "SCSI: Task Terminated" }, +{ MPI_IOCSTATUS_SCSI_RESIDUAL_MISMATCH, "SCSI: Residual Mismatch" }, +{ MPI_IOCSTATUS_SCSI_TASK_MGMT_FAILED, "SCSI: Task Management Failed" }, +{ MPI_IOCSTATUS_SCSI_IOC_TERMINATED, "SCSI: IOC Bus Reset" }, +{ MPI_IOCSTATUS_SCSI_EXT_TERMINATED, "SCSI: External Bus Reset" }, +{ MPI_IOCSTATUS_TARGET_PRIORITY_IO, "SCSI Target: Priority I/O" }, +{ MPI_IOCSTATUS_TARGET_INVALID_PORT, "SCSI Target: Invalid Port" }, +{ MPI_IOCSTATUS_TARGET_INVALID_IOCINDEX, "SCSI Target: Invalid IOC Index" }, +{ MPI_IOCSTATUS_TARGET_ABORTED, "SCSI Target: Aborted" }, +{ MPI_IOCSTATUS_TARGET_NO_CONN_RETRYABLE, "SCSI Target: No Connection (Retryable)" }, +{ MPI_IOCSTATUS_TARGET_NO_CONNECTION, "SCSI Target: No Connection" }, +{ MPI_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH,"SCSI Target: Transfer Count Mismatch" }, +{ MPI_IOCSTATUS_TARGET_FC_ABORTED, "FC: Aborted" }, +{ MPI_IOCSTATUS_TARGET_FC_RX_ID_INVALID, "FC: Recieve ID Invalid" }, +{ MPI_IOCSTATUS_TARGET_FC_DID_INVALID, "FC: Recieve DID Invalid" }, +{ MPI_IOCSTATUS_TARGET_FC_NODE_LOGGED_OUT,"FC: Node Logged Out" }, +{ MPI_IOCSTATUS_LAN_DEVICE_NOT_FOUND, "LAN: Device Not Found" }, +{ MPI_IOCSTATUS_LAN_DEVICE_FAILURE, "LAN: Device Not Failure" }, +{ MPI_IOCSTATUS_LAN_TRANSMIT_ERROR, "LAN: Transmit Error" }, +{ MPI_IOCSTATUS_LAN_TRANSMIT_ABORTED, "LAN: Transmit Aborted" }, +{ MPI_IOCSTATUS_LAN_RECEIVE_ERROR, "LAN: Recieve Error" }, +{ MPI_IOCSTATUS_LAN_RECEIVE_ABORTED, "LAN: Recieve Aborted" }, +{ MPI_IOCSTATUS_LAN_PARTIAL_PACKET, "LAN: Partial Packet" }, +{ MPI_IOCSTATUS_LAN_CANCELED, "LAN: Canceled" }, +{ -1, 0}, +}; + +static const struct Error_Map IOC_Func[] = { +{ MPI_FUNCTION_SCSI_IO_REQUEST, "SCSI IO Request" }, +{ MPI_FUNCTION_SCSI_TASK_MGMT, "SCSI Task Management" }, +{ MPI_FUNCTION_IOC_INIT, "IOC Init" }, +{ MPI_FUNCTION_IOC_FACTS, "IOC Facts" }, +{ MPI_FUNCTION_CONFIG, "Config" }, +{ MPI_FUNCTION_PORT_FACTS, "Port Facts" }, +{ MPI_FUNCTION_PORT_ENABLE, "Port Enable" }, +{ MPI_FUNCTION_EVENT_NOTIFICATION, "Event Notification" }, +{ MPI_FUNCTION_FW_DOWNLOAD, "FW Download" }, +{ MPI_FUNCTION_TARGET_CMD_BUFFER_POST, "SCSI Target Command Buffer" }, +{ MPI_FUNCTION_TARGET_ASSIST, "Target Assist" }, +{ MPI_FUNCTION_TARGET_STATUS_SEND, "Target Status Send" }, +{ MPI_FUNCTION_TARGET_MODE_ABORT, "Target Mode Abort" }, +{ MPI_FUNCTION_TARGET_FC_BUF_POST_LINK_SRVC, "FC: Link Service Buffers" }, +{ MPI_FUNCTION_TARGET_FC_RSP_LINK_SRVC, "FC: Link Service Response" }, +{ MPI_FUNCTION_TARGET_FC_EX_SEND_LINK_SRVC, "FC: Send Extended Link Service" }, +{ MPI_FUNCTION_TARGET_FC_ABORT, "FC: Abort" }, +{ MPI_FUNCTION_LAN_SEND, "LAN Send" }, +{ MPI_FUNCTION_LAN_RECEIVE, "LAN Recieve" }, +{ MPI_FUNCTION_LAN_RESET, "LAN Reset" }, +{ -1, 0}, +}; + +static const struct Error_Map IOC_Event[] = { +{ MPI_EVENT_NONE, "None" }, +{ MPI_EVENT_LOG_DATA, "LogData" }, +{ MPI_EVENT_STATE_CHANGE, "State Change" }, +{ MPI_EVENT_UNIT_ATTENTION, "Unit Attention" }, +{ MPI_EVENT_IOC_BUS_RESET, "IOC Bus Reset" }, +{ MPI_EVENT_EXT_BUS_RESET, "External Bus Reset" }, +{ MPI_EVENT_RESCAN, "Rescan" }, +{ MPI_EVENT_LINK_STATUS_CHANGE, "Link Status Change" }, +{ MPI_EVENT_LOOP_STATE_CHANGE, "Loop State Change" }, +{ MPI_EVENT_LOGOUT, "Logout" }, +{ MPI_EVENT_EVENT_CHANGE, "EventChange" }, +{ -1, 0}, +}; + +static const struct Error_Map IOC_SCSIState[] = { +{ MPI_SCSI_STATE_AUTOSENSE_VALID, "AutoSense_Valid" }, +{ MPI_SCSI_STATE_AUTOSENSE_FAILED, "AutoSense_Failed" }, +{ MPI_SCSI_STATE_NO_SCSI_STATUS, "No_SCSI_Status" }, +{ MPI_SCSI_STATE_TERMINATED, "State_Terminated" }, +{ MPI_SCSI_STATE_RESPONSE_INFO_VALID, "Repsonse_Info_Valid" }, +{ MPI_SCSI_STATE_QUEUE_TAG_REJECTED, "Queue Tag Rejected" }, +{ -1, 0}, +}; + +static const struct Error_Map IOC_SCSIStatus[] = { +{ SCSI_STATUS_OK, "OK" }, +{ SCSI_STATUS_CHECK_COND, "Check Condition" }, +{ SCSI_STATUS_COND_MET, "Check Condition Met" }, +{ SCSI_STATUS_BUSY, "Busy" }, +{ SCSI_STATUS_INTERMED, "Intermidiate Condition" }, +{ SCSI_STATUS_INTERMED_COND_MET, "Intermidiate Condition Met" }, +{ SCSI_STATUS_RESERV_CONFLICT, "Reservation Conflict" }, +{ SCSI_STATUS_CMD_TERMINATED, "Command Terminated" }, +{ SCSI_STATUS_QUEUE_FULL, "Queue Full" }, +{ -1, 0}, +}; + +static const struct Error_Map IOC_Diag[] = { +{ MPT_DIAG_ENABLED, "DWE" }, +{ MPT_DIAG_FLASHBAD, "FLASH_Bad" }, +{ MPT_DIAG_TTLI, "TTLI" }, +{ MPT_DIAG_RESET_IOC, "Reset" }, +{ MPT_DIAG_ARM_DISABLE, "DisARM" }, +{ MPT_DIAG_DME, "DME" }, +{ -1, 0 }, +}; + + +static void mpt_dump_sgl(SGE_IO_UNION *sgl); + +static char * +mpt_ioc_status(int code) +{ + const struct Error_Map *status = IOC_Status; + static char buf[64]; + while (status->Error_Code >= 0) { + if (status->Error_Code == (code & MPI_IOCSTATUS_MASK)) + return status->Error_String; + status++; + } + snprintf(buf, sizeof buf, "Unknown (0x%08x)", code); + return buf; +} + +char * +mpt_ioc_diag(u_int32_t code) +{ + const struct Error_Map *status = IOC_Diag; + static char buf[128]; + char *ptr = buf; + char *end = &buf[128]; + buf[0] = '\0'; + ptr += snprintf(buf, sizeof buf, "(0x%08x)", code); + while (status->Error_Code >= 0) { + if ((status->Error_Code & code) != 0) + ptr += snprintf(ptr, (size_t)(end-ptr), "%s ", + status->Error_String); + status++; + } + return buf; +} + +static char * +mpt_ioc_function(int code) +{ + const struct Error_Map *status = IOC_Func; + static char buf[64]; + while (status->Error_Code >= 0) { + if (status->Error_Code == code) + return status->Error_String; + status++; + } + snprintf(buf, sizeof buf, "Unknown (0x%08x)", code); + return buf; +} +static char * +mpt_ioc_event(int code) +{ + const struct Error_Map *status = IOC_Event; + static char buf[64]; + while (status->Error_Code >= 0) { + if (status->Error_Code == code) + return status->Error_String; + status++; + } + snprintf(buf, sizeof buf, "Unknown (0x%08x)", code); + return buf; +} +static char * +mpt_scsi_state(int code) +{ + const struct Error_Map *status = IOC_SCSIState; + static char buf[128]; + char *ptr = buf; + char *end = &buf[128]; + buf[0] = '\0'; + ptr += snprintf(buf, sizeof buf, "(0x%08x)", code); + while (status->Error_Code >= 0) { + if ((status->Error_Code & code) != 0) + ptr += snprintf(ptr, (size_t)(end-ptr), "%s ", + status->Error_String); + status++; + } + return buf; +} +static char * +mpt_scsi_status(int code) +{ + const struct Error_Map *status = IOC_SCSIStatus; + static char buf[64]; + while (status->Error_Code >= 0) { + if (status->Error_Code == code) + return status->Error_String; + status++; + } + snprintf(buf, sizeof buf, "Unknown (0x%08x)", code); + return buf; +} +static char * +mpt_who(int who_init) +{ + char *who; + + switch (who_init) { + case MPT_DB_INIT_NOONE: who = "No One"; break; + case MPT_DB_INIT_BIOS: who = "BIOS"; break; + case MPT_DB_INIT_ROMBIOS: who = "ROM BIOS"; break; + case MPT_DB_INIT_PCIPEER: who = "PCI Peer"; break; + case MPT_DB_INIT_HOST: who = "Host Driver"; break; + case MPT_DB_INIT_MANUFACTURE: who = "Manufacturing"; break; + default: who = "Unknown"; break; + } + return who; +} + +static char * +mpt_state(u_int32_t mb) +{ + char *text; + + switch (MPT_STATE(mb)) { + case MPT_DB_STATE_RESET: text = "Reset"; break; + case MPT_DB_STATE_READY: text = "Ready"; break; + case MPT_DB_STATE_RUNNING:text = "Running"; break; + case MPT_DB_STATE_FAULT: text = "Fault"; break; + default: text = "Unknown"; break; + } + return text; +}; + +void +mpt_print_db(u_int32_t mb) +{ + printf("mpt mailbox: (0x%x) State %s WhoInit %s\n", + mb, mpt_state(mb), mpt_who(MPT_WHO(mb))); +} + +/*****************************************************************************/ +/* Reply functions */ +/*****************************************************************************/ +static void +mpt_print_reply_hdr(MSG_DEFAULT_REPLY *msg) +{ + printf("%s Reply @ %p\n", mpt_ioc_function(msg->Function), msg); + printf("\tIOC Status %s\n", mpt_ioc_status(msg->IOCStatus)); + printf("\tIOCLogInfo 0x%08x\n", msg->IOCLogInfo); + printf("\tMsgLength 0x%02x\n", msg->MsgLength); + printf("\tMsgFlags 0x%02x\n", msg->MsgFlags); + printf("\tMsgContext 0x%08x\n", msg->MsgContext); +} + +static void +mpt_print_init_reply(MSG_IOC_INIT_REPLY *msg) +{ + mpt_print_reply_hdr((MSG_DEFAULT_REPLY *)msg); + printf("\tWhoInit %s\n", mpt_who(msg->WhoInit)); + printf("\tMaxDevices 0x%02x\n", msg->MaxDevices); + printf("\tMaxBuses 0x%02x\n", msg->MaxBuses); +} + +static void +mpt_print_ioc_facts(MSG_IOC_FACTS_REPLY *msg) +{ + mpt_print_reply_hdr((MSG_DEFAULT_REPLY *)msg); + printf("\tIOCNumber %d\n", msg->IOCNumber); + printf("\tMaxChainDepth %d\n", msg->MaxChainDepth); + printf("\tWhoInit %s\n", mpt_who(msg->WhoInit)); + printf("\tBlockSize %d\n", msg->BlockSize); + printf("\tFlags %d\n", msg->Flags); + printf("\tReplyQueueDepth %d\n", msg->ReplyQueueDepth); + printf("\tReqFrameSize 0x%04x\n", msg->RequestFrameSize); + printf("\tFW Version 0x%08x\n", msg->FWVersion.Word); + printf("\tProduct ID 0x%04x\n", msg->ProductID); + printf("\tCredits 0x%04x\n", msg->GlobalCredits); + printf("\tPorts %d\n", msg->NumberOfPorts); + printf("\tEventState 0x%02x\n", msg->EventState); + printf("\tHostMFA_HA 0x%08x\n", msg->CurrentHostMfaHighAddr); + printf("\tSenseBuf_HA 0x%08x\n", + msg->CurrentSenseBufferHighAddr); + printf("\tRepFrameSize 0x%04x\n", msg->CurReplyFrameSize); + printf("\tMaxDevices 0x%02x\n", msg->MaxDevices); + printf("\tMaxBuses 0x%02x\n", msg->MaxBuses); + printf("\tFWImageSize 0x%04x\n", msg->FWImageSize); +} + +static void +mpt_print_enable_reply(MSG_PORT_ENABLE_REPLY *msg) +{ + mpt_print_reply_hdr((MSG_DEFAULT_REPLY *)msg); + printf("\tPort: %d\n", msg->PortNumber); +} + +static void +mpt_print_scsi_io_reply(MSG_SCSI_IO_REPLY *msg) +{ + mpt_print_reply_hdr((MSG_DEFAULT_REPLY *)msg); + printf("\tBus: %d\n", msg->Bus); + printf("\tTargetID %d\n", msg->TargetID); + printf("\tCDBLength %d\n", msg->CDBLength); + printf("\tSCSI Status: %s\n", mpt_scsi_status(msg->SCSIStatus)); + printf("\tSCSI State: %s\n", mpt_scsi_state(msg->SCSIState)); + printf("\tTransferCnt 0x%04x\n", msg->TransferCount); + printf("\tSenseCnt 0x%04x\n", msg->SenseCount); + printf("\tResponseInfo 0x%08x\n", msg->ResponseInfo); +} + + + +static void +mpt_print_event_notice(MSG_EVENT_NOTIFY_REPLY *msg) +{ + mpt_print_reply_hdr((MSG_DEFAULT_REPLY *)msg); + printf("\tEvent: %s\n", mpt_ioc_event(msg->Event)); + printf("\tEventContext 0x%04x\n", msg->EventContext); + printf("\tAckRequired %d\n", msg->AckRequired); + printf("\tEventDataLength %d\n", msg->EventDataLength); + printf("\tContinuation %d\n", msg->MsgFlags & 0x80); + switch(msg->Event) { + case MPI_EVENT_LOG_DATA: + printf("\tEvtLogData: 0x%04x\n", msg->Data[0]); + break; + + case MPI_EVENT_UNIT_ATTENTION: + printf("\tTargetID: 0x%04x\n", + msg->Data[0] & 0xff); + printf("\tBus: 0x%04x\n", + (msg->Data[0] >> 8) & 0xff); + break; + + case MPI_EVENT_IOC_BUS_RESET: + case MPI_EVENT_EXT_BUS_RESET: + case MPI_EVENT_RESCAN: + printf("\tPort: %d\n", + (msg->Data[0] >> 8) & 0xff); + break; + + case MPI_EVENT_LINK_STATUS_CHANGE: + printf("\tLinkState: %d\n", + msg->Data[0] & 0xff); + printf("\tPort: %d\n", + (msg->Data[1] >> 8) & 0xff); + break; + + case MPI_EVENT_LOOP_STATE_CHANGE: + printf("\tType: %d\n", + (msg->Data[0] >> 16) & 0xff); + printf("\tChar3: 0x%02x\n", + (msg->Data[0] >> 8) & 0xff); + printf("\tChar4: 0x%02x\n", + (msg->Data[0] ) & 0xff); + printf("\tPort: %d\n", + (msg->Data[1] >> 8) & 0xff); + break; + + case MPI_EVENT_LOGOUT: + printf("\tN_PortId: 0x%04x\n", msg->Data[0]); + printf("\tPort: %d\n", + (msg->Data[1] >> 8) & 0xff); + break; + } + +} + +void +mpt_print_reply(void *vmsg) +{ + MSG_DEFAULT_REPLY *msg = vmsg; + + switch (msg->Function) { + case MPI_FUNCTION_EVENT_NOTIFICATION: + mpt_print_event_notice((MSG_EVENT_NOTIFY_REPLY *)msg); + break; + case MPI_FUNCTION_PORT_ENABLE: + mpt_print_enable_reply((MSG_PORT_ENABLE_REPLY *)msg); + break; + case MPI_FUNCTION_IOC_FACTS: + mpt_print_ioc_facts((MSG_IOC_FACTS_REPLY *)msg); + break; + case MPI_FUNCTION_IOC_INIT: + mpt_print_init_reply((MSG_IOC_INIT_REPLY *)msg); + break; + case MPI_FUNCTION_SCSI_IO_REQUEST: + mpt_print_scsi_io_reply((MSG_SCSI_IO_REPLY *)msg); + break; + default: + mpt_print_reply_hdr((MSG_DEFAULT_REPLY *)msg); + break; + } +} + +/*****************************************************************************/ +/* Request functions */ +/*****************************************************************************/ +static void +mpt_print_request_hdr(MSG_REQUEST_HEADER *req) +{ + printf("%s @ %p\n", mpt_ioc_function(req->Function), req); + printf("\tChain Offset 0x%02x\n", req->ChainOffset); + printf("\tMsgFlags 0x%02x\n", req->MsgFlags); + printf("\tMsgContext 0x%08x\n", req->MsgContext); +} + +void +mpt_print_scsi_io_request(MSG_SCSI_IO_REQUEST *orig_msg) +{ + MSG_SCSI_IO_REQUEST local, *msg = &local; + int i; + + bcopy(orig_msg, msg, sizeof (MSG_SCSI_IO_REQUEST)); + mpt_print_request_hdr((MSG_REQUEST_HEADER *)msg); + printf("\tBus: %d\n", msg->Bus); + printf("\tTargetID %d\n", msg->TargetID); + printf("\tSenseBufferLength %d\n", msg->SenseBufferLength); + printf("\tLUN: 0x%0x\n", msg->LUN[1]); + printf("\tControl 0x%08x ", msg->Control); +#define MPI_PRINT_FIELD(x) \ + case MPI_SCSIIO_CONTROL_ ## x : \ + printf(" " #x " "); \ + break + + switch (msg->Control & MPI_SCSIIO_CONTROL_DATADIRECTION_MASK) { + MPI_PRINT_FIELD(NODATATRANSFER); + MPI_PRINT_FIELD(WRITE); + MPI_PRINT_FIELD(READ); + default: + printf(" Invalid DIR! "); + break; + } + switch (msg->Control & MPI_SCSIIO_CONTROL_TASKATTRIBUTE_MASK) { + MPI_PRINT_FIELD(SIMPLEQ); + MPI_PRINT_FIELD(HEADOFQ); + MPI_PRINT_FIELD(ORDEREDQ); + MPI_PRINT_FIELD(ACAQ); + MPI_PRINT_FIELD(UNTAGGED); + MPI_PRINT_FIELD(NO_DISCONNECT); + default: + printf(" Unknown attribute! "); + break; + } + + printf("\n"); +#undef MPI_PRINT_FIELD + + printf("\tDataLength\t0x%08x\n", msg->DataLength); + printf("\tSenseBufAddr\t0x%08x\n", msg->SenseBufferLowAddr); + printf("\tCDB[0:%d]\t", msg->CDBLength); + for (i = 0; i < msg->CDBLength; i++) + printf("%02x ", msg->CDB[i]); + printf("\n"); + mpt_dump_sgl(&orig_msg->SGL); +} + +void +mpt_print_request(void *vreq) +{ + MSG_REQUEST_HEADER *req = vreq; + + switch (req->Function) { + case MPI_FUNCTION_SCSI_IO_REQUEST: + mpt_print_scsi_io_request((MSG_SCSI_IO_REQUEST *)req); + break; + default: + mpt_print_request_hdr(req); + break; + } +} + +char * +mpt_req_state(enum mpt_req_state state) +{ + char *text; + + switch (state) { + case REQ_FREE: text = "Free"; break; + case REQ_IN_PROGRESS: text = "In Progress"; break; + case REQ_ON_CHIP: text = "On Chip"; break; + case REQ_TIMEOUT: text = "Timeout"; break; + default: text = "Unknown"; break; + } + return text; +}; + +static void +mpt_dump_sgl(SGE_IO_UNION *su) +{ + SGE_SIMPLE32 *se = (SGE_SIMPLE32 *) su; + int iCount, flags; + + iCount = MPT_SGL_MAX; + do { + int iprt; + + printf("\t"); + flags = MPI_SGE_GET_FLAGS(se->FlagsLength); + switch (flags & MPI_SGE_FLAGS_ELEMENT_MASK) { + case MPI_SGE_FLAGS_SIMPLE_ELEMENT: + { + printf("SE32 %p: Addr=0x%0x FlagsLength=0x%0x\n", + se, se->Address, se->FlagsLength); + printf(" "); + break; + } + case MPI_SGE_FLAGS_CHAIN_ELEMENT: + { + SGE_CHAIN32 *ce = (SGE_CHAIN32 *) se; + printf("CE32 %p: Addr=0x%0x NxtChnO=0x%x Flgs=0x%x " + "Len=0x%0x\n", ce, ce->Address, ce->NextChainOffset, + ce->Flags, ce->Length); + flags = 0; + break; + } + case MPI_SGE_FLAGS_TRANSACTION_ELEMENT: + printf("TE32 @ %p\n", se); + flags = 0; + break; + } + iprt = 0; +#define MPT_PRINT_FLAG(x) \ + if (flags & MPI_SGE_FLAGS_ ## x ) { \ + if (iprt == 0) { \ + printf("\t"); \ + } \ + printf(" "); \ + printf( #x ); \ + iprt++; \ + } + MPT_PRINT_FLAG(LOCAL_ADDRESS); + MPT_PRINT_FLAG(HOST_TO_IOC); + MPT_PRINT_FLAG(64_BIT_ADDRESSING); + MPT_PRINT_FLAG(LAST_ELEMENT); + MPT_PRINT_FLAG(END_OF_BUFFER); + MPT_PRINT_FLAG(END_OF_LIST); +#undef MPT_PRINT_FLAG + if (iprt) + printf("\n"); + se++; + iCount -= 1; + } while ((flags & MPI_SGE_FLAGS_END_OF_LIST) == 0 && iCount != 0); +} + +void +mpt_prt(mpt_softc_t *mpt, const char *fmt, ...) +{ + va_list ap; + printf("%s: ", device_get_nameunit(mpt->dev)); + va_start(ap, fmt); + vprintf(fmt, ap); + va_end(ap); + printf("\n"); +} diff --git a/sys/dev/mpt/mpt_freebsd.c b/sys/dev/mpt/mpt_freebsd.c new file mode 100644 index 0000000..c564bdf --- /dev/null +++ b/sys/dev/mpt/mpt_freebsd.c @@ -0,0 +1,1528 @@ +/* + +#include <sys/cdefs.h> +__FBSDID("$FreeBSD$"); + * FreeBSD/CAM specific routines for LSI '909 FC adapters. + * FreeBSD Version. + * + * Copyright (c) 2000, 2001 by Greg Ansley + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice immediately at the beginning of the file, without modification, + * this list of conditions, and the following disclaimer. + * 2. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ +/* + * Additional Copyright (c) 2002 by Matthew Jacob under same license. + */ + +#include <dev/mpt/mpt_freebsd.h> + +static void mpt_poll(struct cam_sim *); +static timeout_t mpttimeout; +static timeout_t mpttimeout2; +static void mpt_action(struct cam_sim *, union ccb *); +static int mpt_setwidth(mpt_softc_t *, int, int); +static int mpt_setsync(mpt_softc_t *, int, int, int); + +void +mpt_cam_attach(mpt_softc_t *mpt) +{ + struct cam_devq *devq; + struct cam_sim *sim; + int maxq; + + mpt->bus = 0; + maxq = (mpt->mpt_global_credits < MPT_MAX_REQUESTS(mpt))? + mpt->mpt_global_credits : MPT_MAX_REQUESTS(mpt); + + + /* + * Create the device queue for our SIM(s). + */ + + devq = cam_simq_alloc(maxq); + if (devq == NULL) { + return; + } + + /* + * Construct our SIM entry. + */ + sim = cam_sim_alloc(mpt_action, mpt_poll, "mpt", mpt, + mpt->unit, 1, maxq, devq); + if (sim == NULL) { + cam_simq_free(devq); + return; + } + + /* + * Register exactly the bus. + */ + + if (xpt_bus_register(sim, 0) != CAM_SUCCESS) { + cam_sim_free(sim, TRUE); + return; + } + + if (xpt_create_path(&mpt->path, NULL, cam_sim_path(sim), + CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { + xpt_bus_deregister(cam_sim_path(sim)); + cam_sim_free(sim, TRUE); + return; + } + mpt->sim = sim; +} + +void +mpt_cam_detach(mpt_softc_t *mpt) +{ + if (mpt->sim != NULL) { + xpt_free_path(mpt->path); + xpt_bus_deregister(cam_sim_path(mpt->sim)); + cam_sim_free(mpt->sim, TRUE); + mpt->sim = NULL; + } +} + +/* This routine is used after a system crash to dump core onto the + * swap device. + */ +static void +mpt_poll(struct cam_sim *sim) +{ + mpt_softc_t *mpt = (mpt_softc_t *) cam_sim_softc(sim); + MPT_LOCK(mpt); + mpt_intr(mpt); + MPT_UNLOCK(mpt); +} + +/* + * This routine is called if the 9x9 does not return completion status + * for a command after a CAM specified time. + */ +static void +mpttimeout(void *arg) +{ + request_t *req; + union ccb *ccb = arg; + u_int32_t oseq; + mpt_softc_t *mpt; + + mpt = ccb->ccb_h.ccb_mpt_ptr; + MPT_LOCK(mpt); + req = ccb->ccb_h.ccb_req_ptr; + oseq = req->sequence; + mpt->timeouts++; + if (mpt_intr(mpt)) { + if (req->sequence != oseq) { + mpt_prt(mpt, "bullet missed in timeout"); + MPT_UNLOCK(mpt); + return; + } + mpt_prt(mpt, "bullet U-turned in timeout: got us"); + } + mpt_prt(mpt, + "time out on request index = 0x%02x sequence = 0x%08x", + req->index, req->sequence); + mpt_check_doorbell(mpt); + mpt_prt(mpt, "Status %08x; Mask %08x; Doorbell %08x", + mpt_read(mpt, MPT_OFFSET_INTR_STATUS), + mpt_read(mpt, MPT_OFFSET_INTR_MASK), + mpt_read(mpt, MPT_OFFSET_DOORBELL) ); + printf("request state %s\n", mpt_req_state(req->debug)); + if (ccb != req->ccb) { + printf("time out: ccb %p != req->ccb %p\n", + ccb,req->ccb); + } + mpt_print_scsi_io_request((MSG_SCSI_IO_REQUEST *)req->req_vbuf); + req->debug = REQ_TIMEOUT; + req->ccb = NULL; + req->link.sle_next = (void *) mpt; + (void) timeout(mpttimeout2, (caddr_t)req, hz / 10); + ccb->ccb_h.status = CAM_CMD_TIMEOUT; + ccb->ccb_h.status |= CAM_RELEASE_SIMQ; + mpt->outofbeer = 0; + MPTLOCK_2_CAMLOCK(mpt); + xpt_done(ccb); + CAMLOCK_2_MPTLOCK(mpt); + MPT_UNLOCK(mpt); +} + +static void +mpttimeout2(void *arg) +{ + request_t *req = arg; + if (req->debug == REQ_TIMEOUT) { + mpt_softc_t *mpt = (mpt_softc_t *) req->link.sle_next; + MPT_LOCK(mpt); + mpt_free_request(mpt, req); + MPT_UNLOCK(mpt); + } +} + +/* + * Callback routine from "bus_dmamap_load" or in simple case called directly. + * + * Takes a list of physical segments and builds the SGL for SCSI IO command + * and forwards the commard to the IOC after one last check that CAM has not + * aborted the transaction. + */ +static void +mpt_execute_req(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) +{ + request_t *req; + union ccb *ccb; + mpt_softc_t *mpt; + MSG_SCSI_IO_REQUEST *mpt_req; + SGE_SIMPLE32 *se; + + req = (request_t *)arg; + ccb = req->ccb; + + mpt = ccb->ccb_h.ccb_mpt_ptr; + req = ccb->ccb_h.ccb_req_ptr; + mpt_req = req->req_vbuf; + + if (error == 0 && nseg > MPT_SGL_MAX) { + error = EFBIG; + } + + if (error != 0) { + if (error != EFBIG) + mpt_prt(mpt, "bus_dmamap_load returned %d", error); + if (ccb->ccb_h.status == CAM_REQ_INPROG) { + xpt_freeze_devq(ccb->ccb_h.path, 1); + ccb->ccb_h.status = CAM_DEV_QFRZN; + if (error == EFBIG) + ccb->ccb_h.status |= CAM_REQ_TOO_BIG; + else + ccb->ccb_h.status |= CAM_REQ_CMP_ERR; + } + ccb->ccb_h.status &= ~CAM_SIM_QUEUED; + xpt_done(ccb); + CAMLOCK_2_MPTLOCK(mpt); + mpt_free_request(mpt, req); + MPTLOCK_2_CAMLOCK(mpt); + return; + } + + if (nseg > MPT_NSGL_FIRST(mpt)) { + int i, nleft = nseg; + u_int32_t flags; + bus_dmasync_op_t op; + SGE_CHAIN32 *ce; + + mpt_req->DataLength = ccb->csio.dxfer_len; + flags = MPI_SGE_FLAGS_SIMPLE_ELEMENT; + if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) + flags |= MPI_SGE_FLAGS_HOST_TO_IOC; + + se = (SGE_SIMPLE32 *) &mpt_req->SGL; + for (i = 0; i < MPT_NSGL_FIRST(mpt) - 1; i++, se++, dm_segs++) { + u_int32_t tf; + + bzero(se, sizeof (*se)); + se->Address = dm_segs->ds_addr; + MPI_pSGE_SET_LENGTH(se, dm_segs->ds_len); + tf = flags; + if (i == MPT_NSGL_FIRST(mpt) - 2) { + tf |= MPI_SGE_FLAGS_LAST_ELEMENT; + } + MPI_pSGE_SET_FLAGS(se, tf); + nleft -= 1; + } + + /* + * Tell the IOC where to find the first chain element + */ + mpt_req->ChainOffset = ((char *)se - (char *)mpt_req) >> 2; + + /* + * Until we're finished with all segments... + */ + while (nleft) { + int ntodo; + /* + * Construct the chain element that point to the + * next segment. + */ + ce = (SGE_CHAIN32 *) se++; + if (nleft > MPT_NSGL(mpt)) { + ntodo = MPT_NSGL(mpt) - 1; + ce->NextChainOffset = (MPT_RQSL(mpt) - + sizeof (SGE_SIMPLE32)) >> 2; + } else { + ntodo = nleft; + ce->NextChainOffset = 0; + } + ce->Length = ntodo * sizeof (SGE_SIMPLE32); + ce->Address = req->req_pbuf + + ((char *)se - (char *)mpt_req); + ce->Flags = MPI_SGE_FLAGS_CHAIN_ELEMENT; + for (i = 0; i < ntodo; i++, se++, dm_segs++) { + u_int32_t tf; + + bzero(se, sizeof (*se)); + se->Address = dm_segs->ds_addr; + MPI_pSGE_SET_LENGTH(se, dm_segs->ds_len); + tf = flags; + if (i == ntodo - 1) { + tf |= MPI_SGE_FLAGS_LAST_ELEMENT; + if (ce->NextChainOffset == 0) { + tf |= + MPI_SGE_FLAGS_END_OF_LIST | + MPI_SGE_FLAGS_END_OF_BUFFER; + } + } + MPI_pSGE_SET_FLAGS(se, tf); + nleft -= 1; + } + + } + + if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) + op = BUS_DMASYNC_PREREAD; + else + op = BUS_DMASYNC_PREWRITE; + if (!(ccb->ccb_h.flags & (CAM_SG_LIST_PHYS|CAM_DATA_PHYS))) { + bus_dmamap_sync(mpt->buffer_dmat, req->dmap, op); + } + } else if (nseg > 0) { + int i; + u_int32_t flags; + bus_dmasync_op_t op; + + mpt_req->DataLength = ccb->csio.dxfer_len; + flags = MPI_SGE_FLAGS_SIMPLE_ELEMENT; + if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) + flags |= MPI_SGE_FLAGS_HOST_TO_IOC; + + /* Copy the segments into our SG list */ + se = (SGE_SIMPLE32 *) &mpt_req->SGL; + for (i = 0; i < nseg; i++, se++, dm_segs++) { + u_int32_t tf; + + bzero(se, sizeof (*se)); + se->Address = dm_segs->ds_addr; + MPI_pSGE_SET_LENGTH(se, dm_segs->ds_len); + tf = flags; + if (i == nseg - 1) { + tf |= + MPI_SGE_FLAGS_LAST_ELEMENT | + MPI_SGE_FLAGS_END_OF_BUFFER | + MPI_SGE_FLAGS_END_OF_LIST; + } + MPI_pSGE_SET_FLAGS(se, tf); + } + + if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) + op = BUS_DMASYNC_PREREAD; + else + op = BUS_DMASYNC_PREWRITE; + if (!(ccb->ccb_h.flags & (CAM_SG_LIST_PHYS|CAM_DATA_PHYS))) { + bus_dmamap_sync(mpt->buffer_dmat, req->dmap, op); + } + } else { + se = (SGE_SIMPLE32 *) &mpt_req->SGL; + /* + * No data to transfer so we just make a single simple SGL + * with zero length. + */ + MPI_pSGE_SET_FLAGS(se, + (MPI_SGE_FLAGS_LAST_ELEMENT | MPI_SGE_FLAGS_END_OF_BUFFER | + MPI_SGE_FLAGS_SIMPLE_ELEMENT | MPI_SGE_FLAGS_END_OF_LIST)); + } + + /* + * Last time we need to check if this CCB needs to be aborted. + */ + if (ccb->ccb_h.status != CAM_REQ_INPROG) { + if (nseg && (ccb->ccb_h.flags & CAM_SG_LIST_PHYS) == 0) + bus_dmamap_unload(mpt->buffer_dmat, req->dmap); + CAMLOCK_2_MPTLOCK(mpt); + mpt_free_request(mpt, req); + MPTLOCK_2_CAMLOCK(mpt); + xpt_done(ccb); + return; + } + + ccb->ccb_h.status |= CAM_SIM_QUEUED; + MPTLOCK_2_CAMLOCK(mpt); + if (ccb->ccb_h.timeout != CAM_TIME_INFINITY) { + ccb->ccb_h.timeout_ch = + timeout(mpttimeout, (caddr_t)ccb, + (ccb->ccb_h.timeout * hz) / 1000); + } else { + callout_handle_init(&ccb->ccb_h.timeout_ch); + } + if (mpt->verbose > 1) + mpt_print_scsi_io_request(mpt_req); + mpt_send_cmd(mpt, req); + MPTLOCK_2_CAMLOCK(mpt); +} + +static void +mpt_start(union ccb *ccb) +{ + request_t *req; + struct mpt_softc *mpt; + MSG_SCSI_IO_REQUEST *mpt_req; + struct ccb_scsiio *csio = &ccb->csio; + struct ccb_hdr *ccbh = &ccb->ccb_h; + + /* Get the pointer for the physical addapter */ + mpt = ccb->ccb_h.ccb_mpt_ptr; + + CAMLOCK_2_MPTLOCK(mpt); + /* Get a request structure off the free list */ + if ((req = mpt_get_request(mpt)) == NULL) { + if (mpt->outofbeer == 0) { + mpt->outofbeer = 1; + xpt_freeze_simq(mpt->sim, 1); + if (mpt->verbose > 1) { + mpt_prt(mpt, "FREEZEQ"); + } + } + MPTLOCK_2_CAMLOCK(mpt); + ccb->ccb_h.status = CAM_REQUEUE_REQ; + xpt_done(ccb); + return; + } + MPTLOCK_2_CAMLOCK(mpt); + + /* Link the ccb and the request structure so we can find */ + /* the other knowing either the request or the ccb */ + req->ccb = ccb; + ccb->ccb_h.ccb_req_ptr = req; + + /* Now we build the command for the IOC */ + mpt_req = req->req_vbuf; + bzero(mpt_req, sizeof *mpt_req); + + mpt_req->Function = MPI_FUNCTION_SCSI_IO_REQUEST; + mpt_req->Bus = mpt->bus; + + mpt_req->SenseBufferLength = + (csio->sense_len < MPT_SENSE_SIZE) ? + csio->sense_len : MPT_SENSE_SIZE; + + /* We use the message context to find the request structure when we */ + /* Get the command competion interrupt from the FC IOC. */ + mpt_req->MsgContext = req->index; + + /* Which physical device to do the I/O on */ + mpt_req->TargetID = ccb->ccb_h.target_id; + mpt_req->LUN[1] = ccb->ccb_h.target_lun; + + /* Set the direction of the transfer */ + if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) + mpt_req->Control = MPI_SCSIIO_CONTROL_READ; + else if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) + mpt_req->Control = MPI_SCSIIO_CONTROL_WRITE; + else + mpt_req->Control = MPI_SCSIIO_CONTROL_NODATATRANSFER; + + if ((ccb->ccb_h.flags & CAM_TAG_ACTION_VALID) != 0) { + switch(ccb->csio.tag_action) { + case MSG_HEAD_OF_Q_TAG: + mpt_req->Control |= MPI_SCSIIO_CONTROL_HEADOFQ; + break; + case MSG_ACA_TASK: + mpt_req->Control |= MPI_SCSIIO_CONTROL_ACAQ; + break; + case MSG_ORDERED_Q_TAG: + mpt_req->Control |= MPI_SCSIIO_CONTROL_ORDEREDQ; + break; + case MSG_SIMPLE_Q_TAG: + default: + mpt_req->Control |= MPI_SCSIIO_CONTROL_SIMPLEQ; + break; + } + } else { + if (mpt->is_fc) + mpt_req->Control |= MPI_SCSIIO_CONTROL_SIMPLEQ; + else + mpt_req->Control |= MPI_SCSIIO_CONTROL_UNTAGGED; + } + + if (mpt->is_fc == 0) { + if (ccb->ccb_h.flags & CAM_DIS_DISCONNECT) { + mpt_req->Control |= MPI_SCSIIO_CONTROL_NO_DISCONNECT; + } + } + + /* Copy the scsi command block into place */ + if ((ccb->ccb_h.flags & CAM_CDB_POINTER) != 0) + bcopy(csio->cdb_io.cdb_ptr, mpt_req->CDB, csio->cdb_len); + else + bcopy(csio->cdb_io.cdb_bytes, mpt_req->CDB, csio->cdb_len); + + mpt_req->CDBLength = csio->cdb_len; + mpt_req->DataLength = csio->dxfer_len; + mpt_req->SenseBufferLowAddr = req->sense_pbuf; + + /* + * If we have any data to send with this command, + * map it into bus space. + */ + + if ((ccbh->flags & CAM_DIR_MASK) != CAM_DIR_NONE) { + if ((ccbh->flags & CAM_SCATTER_VALID) == 0) { + /* + * We've been given a pointer to a single buffer. + */ + if ((ccbh->flags & CAM_DATA_PHYS) == 0) { + /* + * Virtual address that needs to translated into + * one or more physical pages. + */ + int error; + + error = bus_dmamap_load(mpt->buffer_dmat, + req->dmap, csio->data_ptr, csio->dxfer_len, + mpt_execute_req, req, 0); + if (error == EINPROGRESS) { + /* + * So as to maintain ordering, + * freeze the controller queue + * until our mapping is + * returned. + */ + xpt_freeze_simq(mpt->sim, 1); + ccbh->status |= CAM_RELEASE_SIMQ; + } + } else { + /* + * We have been given a pointer to single + * physical buffer. + */ + struct bus_dma_segment seg; + seg.ds_addr = + (bus_addr_t)(vm_offset_t)csio->data_ptr; + seg.ds_len = csio->dxfer_len; + mpt_execute_req(req, &seg, 1, 0); + } + } else { + /* + * We have been given a list of addresses. + * These case could be easily done but they are not + * currently generated by the CAM subsystem so there + * is no point in wasting the time right now. + */ + struct bus_dma_segment *segs; + if ((ccbh->flags & CAM_SG_LIST_PHYS) == 0) { + mpt_execute_req(req, NULL, 0, EFAULT); + } else { + /* Just use the segments provided */ + segs = (struct bus_dma_segment *)csio->data_ptr; + mpt_execute_req(req, segs, csio->sglist_cnt, + (csio->sglist_cnt < MPT_SGL_MAX)? + 0 : EFBIG); + } + } + } else { + mpt_execute_req(req, NULL, 0, 0); + } +} + +static int +mpt_bus_reset(union ccb *ccb) +{ + int error; + request_t *req; + mpt_softc_t *mpt; + MSG_SCSI_TASK_MGMT *reset_req; + + /* Get the pointer for the physical adapter */ + mpt = ccb->ccb_h.ccb_mpt_ptr; + + /* Get a request structure off the free list */ + if ((req = mpt_get_request(mpt)) == NULL) { + return (CAM_REQUEUE_REQ); + } + + /* Link the ccb and the request structure so we can find */ + /* the other knowing either the request or the ccb */ + req->ccb = ccb; + ccb->ccb_h.ccb_req_ptr = req; + + reset_req = req->req_vbuf; + bzero(reset_req, sizeof *reset_req); + + reset_req->Function = MPI_FUNCTION_SCSI_TASK_MGMT; + reset_req->MsgContext = req->index; + reset_req->TaskType = MPI_SCSITASKMGMT_TASKTYPE_RESET_BUS; + if (mpt->is_fc) { + /* + * Should really be TARGET_RESET_OPTION + */ + reset_req->MsgFlags = + MPI_SCSITASKMGMT_MSGFLAGS_LIP_RESET_OPTION; + } + /* Which physical device Reset */ + reset_req->TargetID = ccb->ccb_h.target_id; + reset_req->LUN[1] = ccb->ccb_h.target_lun; + + ccb->ccb_h.status |= CAM_SIM_QUEUED; + + error = mpt_send_handshake_cmd(mpt, + sizeof (MSG_SCSI_TASK_MGMT), reset_req); + if (error) { + mpt_prt(mpt, + "mpt_bus_reset: mpt_send_handshake return %d", error); + return (CAM_REQ_CMP_ERR); + } else { + return (CAM_REQ_CMP); + } +} + +/* + * Process an asynchronous event from the IOC. + */ +static void mpt_ctlop(mpt_softc_t *, void *, u_int32_t); +static void mpt_event_notify_reply(mpt_softc_t *mpt, MSG_EVENT_NOTIFY_REPLY *); + +static void +mpt_ctlop(mpt_softc_t *mpt, void *vmsg, u_int32_t reply) +{ + MSG_DEFAULT_REPLY *dmsg = vmsg; + + if (dmsg->Function == MPI_FUNCTION_EVENT_NOTIFICATION) { + mpt_event_notify_reply(mpt, vmsg); + mpt_free_reply(mpt, (reply << 1)); + } else if (dmsg->Function == MPI_FUNCTION_EVENT_ACK) { + mpt_free_reply(mpt, (reply << 1)); + } else if (dmsg->Function == MPI_FUNCTION_PORT_ENABLE) { + MSG_PORT_ENABLE_REPLY *msg = vmsg; + int index = msg->MsgContext & ~0x80000000; + if (mpt->verbose > 1) { + mpt_prt(mpt, "enable port reply idx %d", index); + } + if (index >= 0 && index < MPT_MAX_REQUESTS(mpt)) { + request_t *req = &mpt->request_pool[index]; + req->debug = REQ_DONE; + } + mpt_free_reply(mpt, (reply << 1)); + } else if (dmsg->Function == MPI_FUNCTION_CONFIG) { + MSG_CONFIG_REPLY *msg = vmsg; + int index = msg->MsgContext & ~0x80000000; + if (index >= 0 && index < MPT_MAX_REQUESTS(mpt)) { + request_t *req = &mpt->request_pool[index]; + req->debug = REQ_DONE; + req->sequence = reply; + } else { + mpt_free_reply(mpt, (reply << 1)); + } + } else { + mpt_prt(mpt, "unknown mpt_ctlop: %x", dmsg->Function); + } +} + +static void +mpt_event_notify_reply(mpt_softc_t *mpt, MSG_EVENT_NOTIFY_REPLY *msg) +{ + switch(msg->Event) { + case MPI_EVENT_LOG_DATA: + /* Some error occured that LSI wants logged */ + printf("\tEvtLogData: IOCLogInfo: 0x%08x\n", msg->IOCLogInfo); + printf("\tEvtLogData: Event Data:"); + { + int i; + for (i = 0; i < msg->EventDataLength; i++) { + printf(" %08x", msg->Data[i]); + } + } + printf("\n"); + break; + + case MPI_EVENT_UNIT_ATTENTION: + mpt_prt(mpt, "Bus: 0x%02x TargetID: 0x%02x", + (msg->Data[0] >> 8) & 0xff, msg->Data[0] & 0xff); + break; + + case MPI_EVENT_IOC_BUS_RESET: + /* We generated a bus reset */ + mpt_prt(mpt, "IOC Bus Reset Port: %d", + (msg->Data[0] >> 8) & 0xff); + break; + + case MPI_EVENT_EXT_BUS_RESET: + /* Someone else generated a bus reset */ + mpt_prt(mpt, "Ext Bus Reset"); + /* + * These replies don't return EventData like the MPI + * spec says they do + */ +/* xpt_async(AC_BUS_RESET, path, NULL); */ + break; + + case MPI_EVENT_RESCAN: + /* + * In general this means a device has been added + * to the loop. + */ + mpt_prt(mpt, "Rescan Port: %d", (msg->Data[0] >> 8) & 0xff); +/* xpt_async(AC_FOUND_DEVICE, path, NULL); */ + break; + + case MPI_EVENT_LINK_STATUS_CHANGE: + mpt_prt(mpt, "Port %d: LinkState: %s", + (msg->Data[1] >> 8) & 0xff, + ((msg->Data[0] & 0xff) == 0)? "Failed" : "Active"); + break; + + case MPI_EVENT_LOOP_STATE_CHANGE: + switch ((msg->Data[0] >> 16) & 0xff) { + case 0x01: + mpt_prt(mpt, + "Port 0x%x: FC LinkEvent: LIP(%02x,%02x) (Loop Initialization)\n", + (msg->Data[1] >> 8) & 0xff, + (msg->Data[0] >> 8) & 0xff, + (msg->Data[0] ) & 0xff); + switch ((msg->Data[0] >> 8) & 0xff) { + case 0xF7: + if ((msg->Data[0] & 0xff) == 0xF7) { + printf("Device needs AL_PA\n"); + } else { + printf("Device %02x doesn't like FC performance\n", + msg->Data[0] & 0xFF); + } + break; + case 0xF8: + if ((msg->Data[0] & 0xff) == 0xF7) { + printf("Device had loop failure at its receiver prior to acquiring AL_PA\n"); + } else { + printf("Device %02x detected loop failure at its receiver\n", + msg->Data[0] & 0xFF); + } + break; + default: + printf("Device %02x requests that device %02x reset itself\n", + msg->Data[0] & 0xFF, + (msg->Data[0] >> 8) & 0xFF); + break; + } + break; + case 0x02: + mpt_prt(mpt, "Port 0x%x: FC LinkEvent: LPE(%02x,%02x) (Loop Port Enable)", + (msg->Data[1] >> 8) & 0xff, /* Port */ + (msg->Data[0] >> 8) & 0xff, /* Character 3 */ + (msg->Data[0] ) & 0xff /* Character 4 */ + ); + break; + case 0x03: + mpt_prt(mpt, "Port 0x%x: FC LinkEvent: LPB(%02x,%02x) (Loop Port Bypass)", + (msg->Data[1] >> 8) & 0xff, /* Port */ + (msg->Data[0] >> 8) & 0xff, /* Character 3 */ + (msg->Data[0] ) & 0xff /* Character 4 */ + ); + break; + default: + mpt_prt(mpt, "Port 0x%x: FC LinkEvent: Unknown FC event (%02x %02x %02x)", + (msg->Data[1] >> 8) & 0xff, /* Port */ + (msg->Data[0] >> 16) & 0xff, /* Event */ + (msg->Data[0] >> 8) & 0xff, /* Character 3 */ + (msg->Data[0] ) & 0xff /* Character 4 */ + ); + } + break; + + case MPI_EVENT_LOGOUT: + mpt_prt(mpt, "FC Logout Port: %d N_PortID: %02x", + (msg->Data[1] >> 8) & 0xff, msg->Data[0]); + break; + case MPI_EVENT_EVENT_CHANGE: + /* This is just an acknowledgement of our + mpt_send_event_request */ + break; + default: + mpt_prt(mpt, "Unknown event 0x%x\n", msg->Event); + } + if (msg->AckRequired) { + MSG_EVENT_ACK *ackp; + request_t *req; + if ((req = mpt_get_request(mpt)) == NULL) { + panic("unable to get request to acknowledge notify"); + } + ackp = (MSG_EVENT_ACK *) req->req_vbuf; + bzero(ackp, sizeof *ackp); + ackp->Function = MPI_FUNCTION_EVENT_ACK; + ackp->Event = msg->Event; + ackp->EventContext = msg->EventContext; + ackp->MsgContext = req->index | 0x80000000; + mpt_check_doorbell(mpt); + mpt_send_cmd(mpt, req); + } +} + +void +mpt_done(mpt_softc_t *mpt, u_int32_t reply) +{ + int index; + request_t *req; + union ccb *ccb; + MSG_REQUEST_HEADER *mpt_req; + MSG_SCSI_IO_REPLY *mpt_reply; + + index = -1; /* Shutup the complier */ + + if ((reply & MPT_CONTEXT_REPLY) == 0) { + /* context reply */ + mpt_reply = NULL; + index = reply & MPT_CONTEXT_MASK; + } else { + unsigned *pReply; + + bus_dmamap_sync(mpt->reply_dmat, mpt->reply_dmap, + BUS_DMASYNC_POSTREAD); + /* address reply (Error) */ + mpt_reply = MPT_REPLY_PTOV(mpt, reply); + if (mpt->verbose > 1) { + pReply = (unsigned *) mpt_reply; + mpt_prt(mpt, "Address Reply (index %u)", + mpt_reply->MsgContext & 0xffff); + printf("%08x %08x %08x %08x\n", + pReply[0], pReply[1], pReply[2], pReply[3]); + printf("%08x %08x %08x %08x\n", + pReply[4], pReply[5], pReply[6], pReply[7]); + printf("%08x %08x %08x %08x\n\n", + pReply[8], pReply[9], pReply[10], pReply[11]); + } + index = mpt_reply->MsgContext; + } + + /* + * Address reply with MessageContext high bit set + * This is most likely a notify message so we try + * to process it then free it + */ + if ((index & 0x80000000) != 0) { + if (mpt_reply != NULL) { + mpt_ctlop(mpt, mpt_reply, reply); + } else { + mpt_prt(mpt, "mpt_done: index 0x%x, NULL reply", index); + } + return; + } + + /* Did we end up with a valid index into the table? */ + if (index < 0 || index >= MPT_MAX_REQUESTS(mpt)) { + mpt_prt(mpt, "mpt_done: invalid index (%x) in reply", index); + return; + } + + req = &mpt->request_pool[index]; + + /* Make sure memory hasn't been trashed */ + if (req->index != index) { + printf("mpt_done: corrupted request struct"); + return; + } + + /* Short cut for task management replys; nothing more for us to do */ + mpt_req = req->req_vbuf; + if (mpt_req->Function == MPI_FUNCTION_SCSI_TASK_MGMT) { + if (mpt->verbose > 1) { + mpt_prt(mpt, "mpt_done: TASK MGMT"); + } + goto done; + } + + if (mpt_req->Function == MPI_FUNCTION_PORT_ENABLE) { + goto done; + } + + /* + * At this point it better be a SCSI IO command, but don't + * crash if it isn't + */ + if (mpt_req->Function != MPI_FUNCTION_SCSI_IO_REQUEST) { + goto done; + } + + /* Recover the CAM control block from the request structure */ + ccb = req->ccb; + + /* Can't have had a SCSI command with out a CAM control block */ + if (ccb == NULL || (ccb->ccb_h.status & CAM_SIM_QUEUED) == 0) { + mpt_prt(mpt, + "mpt_done: corrupted ccb, index = 0x%02x seq = 0x%08x", + req->index, req->sequence); + printf(" request state %s\nmpt_request:\n", + mpt_req_state(req->debug)); + mpt_print_scsi_io_request((MSG_SCSI_IO_REQUEST *)req->req_vbuf); + + if (mpt_reply != NULL) { + printf("\nmpt_done: reply:\n"); + mpt_print_reply(MPT_REPLY_PTOV(mpt, reply)); + } else { + printf("\nmpt_done: context reply: 0x%08x\n", reply); + } + goto done; + } + + untimeout(mpttimeout, ccb, ccb->ccb_h.timeout_ch); + + if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { + bus_dmasync_op_t op; + + if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { + op = BUS_DMASYNC_POSTREAD; + } else { + op = BUS_DMASYNC_POSTWRITE; + } + bus_dmamap_sync(mpt->buffer_dmat, req->dmap, op); + bus_dmamap_unload(mpt->buffer_dmat, req->dmap); + } + ccb->csio.resid = 0; + + if (mpt_reply == NULL) { + /* Context reply; report that the command was successfull */ + ccb->ccb_h.status = CAM_REQ_CMP; + ccb->csio.scsi_status = SCSI_STATUS_OK; + ccb->ccb_h.status &= ~CAM_SIM_QUEUED; + if (mpt->outofbeer) { + ccb->ccb_h.status |= CAM_RELEASE_SIMQ; + mpt->outofbeer = 0; + if (mpt->verbose > 1) { + mpt_prt(mpt, "THAWQ"); + } + } + MPTLOCK_2_CAMLOCK(mpt); + xpt_done(ccb); + CAMLOCK_2_MPTLOCK(mpt); + goto done; + } + + ccb->csio.scsi_status = mpt_reply->SCSIStatus; + switch(mpt_reply->IOCStatus) { + case MPI_IOCSTATUS_SCSI_DATA_OVERRUN: + ccb->ccb_h.status = CAM_DATA_RUN_ERR; + break; + + case MPI_IOCSTATUS_SCSI_DATA_UNDERRUN: + /* + * Yikes, Tagged queue full comes through this path! + * + * So we'll change it to a status error and anything + * that returns status should probably be a status + * error as well. + */ + ccb->csio.resid = + ccb->csio.dxfer_len - mpt_reply->TransferCount; + if (mpt_reply->SCSIState & MPI_SCSI_STATE_NO_SCSI_STATUS) { + ccb->ccb_h.status = CAM_DATA_RUN_ERR; + break; + } + /* Fall through */ + case MPI_IOCSTATUS_SUCCESS: + case MPI_IOCSTATUS_SCSI_RECOVERED_ERROR: + switch (ccb->csio.scsi_status) { + case SCSI_STATUS_OK: + ccb->ccb_h.status = CAM_REQ_CMP; + break; + default: + ccb->ccb_h.status = CAM_SCSI_STATUS_ERROR; + break; + } + break; + case MPI_IOCSTATUS_BUSY: + case MPI_IOCSTATUS_INSUFFICIENT_RESOURCES: + ccb->ccb_h.status = CAM_BUSY; + break; + + case MPI_IOCSTATUS_SCSI_INVALID_BUS: + case MPI_IOCSTATUS_SCSI_INVALID_TARGETID: + case MPI_IOCSTATUS_SCSI_DEVICE_NOT_THERE: + ccb->ccb_h.status = CAM_DEV_NOT_THERE; + break; + + case MPI_IOCSTATUS_SCSI_RESIDUAL_MISMATCH: + ccb->ccb_h.status = CAM_DATA_RUN_ERR; + break; + + case MPI_IOCSTATUS_SCSI_PROTOCOL_ERROR: + case MPI_IOCSTATUS_SCSI_IO_DATA_ERROR: + ccb->ccb_h.status = CAM_UNCOR_PARITY; + break; + + case MPI_IOCSTATUS_SCSI_TASK_TERMINATED: + ccb->ccb_h.status = CAM_REQ_CMP; + break; + + case MPI_IOCSTATUS_SCSI_TASK_MGMT_FAILED: + ccb->ccb_h.status = CAM_UA_TERMIO; + break; + + case MPI_IOCSTATUS_SCSI_IOC_TERMINATED: + ccb->ccb_h.status = CAM_REQ_TERMIO; + break; + + case MPI_IOCSTATUS_SCSI_EXT_TERMINATED: + ccb->ccb_h.status = CAM_SCSI_BUS_RESET; + break; + + default: + ccb->ccb_h.status = CAM_UNREC_HBA_ERROR; + break; + } + + if ((mpt_reply->SCSIState & MPI_SCSI_STATE_AUTOSENSE_VALID) != 0) { + if (ccb->ccb_h.flags & (CAM_SENSE_PHYS | CAM_SENSE_PTR)) { + ccb->ccb_h.status |= CAM_AUTOSENSE_FAIL; + } else { + ccb->ccb_h.status |= CAM_AUTOSNS_VALID; + ccb->csio.sense_resid = mpt_reply->SenseCount; + bcopy(req->sense_vbuf, &ccb->csio.sense_data, + ccb->csio.sense_len); + } + } else if (mpt_reply->SCSIState & MPI_SCSI_STATE_AUTOSENSE_FAILED) { + ccb->ccb_h.status &= ~CAM_STATUS_MASK; + ccb->ccb_h.status |= CAM_AUTOSENSE_FAIL; + } + + if ((ccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_CMP) { + if ((ccb->ccb_h.status & CAM_DEV_QFRZN) == 0) { + ccb->ccb_h.status |= CAM_DEV_QFRZN; + xpt_freeze_devq(ccb->ccb_h.path, 1); + } + } + + + ccb->ccb_h.status &= ~CAM_SIM_QUEUED; + if (mpt->outofbeer) { + ccb->ccb_h.status |= CAM_RELEASE_SIMQ; + mpt->outofbeer = 0; + if (mpt->verbose > 1) { + mpt_prt(mpt, "THAWQ"); + } + } + MPTLOCK_2_CAMLOCK(mpt); + xpt_done(ccb); + CAMLOCK_2_MPTLOCK(mpt); + +done: + /* If IOC done with this request free it up */ + if (mpt_reply == NULL || (mpt_reply->MsgFlags & 0x80) == 0) + mpt_free_request(mpt, req); + + /* If address reply; give the buffer back to the IOC */ + if (mpt_reply != NULL) + mpt_free_reply(mpt, (reply << 1)); +} + +static void +mpt_action(struct cam_sim *sim, union ccb *ccb) +{ + int tgt, error; + mpt_softc_t *mpt; + struct ccb_trans_settings *cts; + + CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("mpt_action\n")); + + mpt = (mpt_softc_t *)cam_sim_softc(sim); + + ccb->ccb_h.ccb_mpt_ptr = mpt; + + switch (ccb->ccb_h.func_code) { + case XPT_RESET_BUS: + if (mpt->verbose > 1) + mpt_prt(mpt, "XPT_RESET_BUS"); + CAMLOCK_2_MPTLOCK(mpt); + error = mpt_bus_reset(ccb); + switch (error) { + case CAM_REQ_INPROG: + MPTLOCK_2_CAMLOCK(mpt); + break; + case CAM_REQUEUE_REQ: + if (mpt->outofbeer == 0) { + mpt->outofbeer = 1; + xpt_freeze_simq(sim, 1); + if (mpt->verbose > 1) { + mpt_prt(mpt, "FREEZEQ"); + } + } + ccb->ccb_h.status = CAM_REQUEUE_REQ; + MPTLOCK_2_CAMLOCK(mpt); + xpt_done(ccb); + break; + + case CAM_REQ_CMP: + ccb->ccb_h.status &= ~CAM_SIM_QUEUED; + ccb->ccb_h.status |= CAM_REQ_CMP; + if (mpt->outofbeer) { + ccb->ccb_h.status |= CAM_RELEASE_SIMQ; + mpt->outofbeer = 0; + if (mpt->verbose > 1) { + mpt_prt(mpt, "THAWQ"); + } + } + MPTLOCK_2_CAMLOCK(mpt); + xpt_done(ccb); + break; + + default: + ccb->ccb_h.status = CAM_REQ_CMP_ERR; + MPTLOCK_2_CAMLOCK(mpt); + xpt_done(ccb); + } + break; + + case XPT_SCSI_IO: /* Execute the requested I/O operation */ + /* + * Do a couple of preliminary checks... + */ + if ((ccb->ccb_h.flags & CAM_CDB_POINTER) != 0) { + if ((ccb->ccb_h.flags & CAM_CDB_PHYS) != 0) { + ccb->ccb_h.status = CAM_REQ_INVALID; + xpt_done(ccb); + break; + } + } + /* Max supported CDB length is 16 bytes */ + if (ccb->csio.cdb_len > + sizeof (((PTR_MSG_SCSI_IO_REQUEST)0)->CDB)) { + ccb->ccb_h.status = CAM_REQ_INVALID; + xpt_done(ccb); + return; + } + ccb->csio.scsi_status = SCSI_STATUS_OK; + mpt_start(ccb); + break; + + case XPT_ABORT: + /* + * XXX: Need to implement + */ + ccb->ccb_h.status = CAM_UA_ABORT; + xpt_done(ccb); + break; + +#ifdef CAM_NEW_TRAN_CODE +#define IS_CURRENT_SETTINGS(c) (c->type == CTS_TYPE_CURRENT_SETTINGS) +#else +#define IS_CURRENT_SETTINGS(c) (c->flags & CCB_TRANS_CURRENT_SETTINGS) +#endif +#define DP_DISC_ENABLE 0x1 +#define DP_DISC_DISABL 0x2 +#define DP_DISC (DP_DISC_ENABLE|DP_DISC_DISABL) + +#define DP_TQING_ENABLE 0x4 +#define DP_TQING_DISABL 0x8 +#define DP_TQING (DP_TQING_ENABLE|DP_TQING_DISABL) + +#define DP_WIDE 0x10 +#define DP_NARROW 0x20 +#define DP_WIDTH (DP_WIDE|DP_NARROW) + +#define DP_SYNC 0x40 + + case XPT_SET_TRAN_SETTINGS: /* Nexus Settings */ + cts = &ccb->cts; + if (!IS_CURRENT_SETTINGS(cts)) { + ccb->ccb_h.status = CAM_REQ_INVALID; + xpt_done(ccb); + break; + } + tgt = cts->ccb_h.target_id; + if (mpt->is_fc == 0) { + u_int8_t dval = 0; + u_int period = 0, offset = 0; +#ifndef CAM_NEW_TRAN_CODE + if (cts->valid & CCB_TRANS_DISC_VALID) { + dval |= DP_DISC_ENABLE; + } + if (cts->valid & CCB_TRANS_TQ_VALID) { + dval |= DP_TQING_ENABLE; + } + if (cts->valid & CCB_TRANS_BUS_WIDTH_VALID) { + if (cts->bus_width) + dval |= DP_WIDE; + else + dval |= DP_NARROW; + } + /* + * Any SYNC RATE of nonzero and SYNC_OFFSET + * of nonzero will cause us to go to the + * selected (from NVRAM) maximum value for + * this device. At a later point, we'll + * allow finer control. + */ + if ((cts->valid & CCB_TRANS_SYNC_RATE_VALID) && + (cts->valid & CCB_TRANS_SYNC_OFFSET_VALID)) { + dval |= DP_SYNC; + period = cts->sync_period; + offset = cts->sync_offset; + } +#else + struct ccb_trans_settings_scsi *scsi = + &cts->proto_specific.scsi; + struct ccb_trans_settings_spi *spi = + &cts->xport_specific.spi; + + if ((spi->valid & CTS_SPI_VALID_DISC) != 0) { + if ((spi->flags & CTS_SPI_FLAGS_DISC_ENB) != 0) + dval |= DP_DISC_ENABLE; + else + dval |= DP_DISC_DISABL; + } + + if ((scsi->valid & CTS_SCSI_VALID_TQ) != 0) { + if ((scsi->flags & CTS_SCSI_FLAGS_TAG_ENB) != 0) + dval |= DP_TQING_ENABLE; + else + dval |= DP_TQING_DISABL; + } + + if ((spi->valid & CTS_SPI_VALID_BUS_WIDTH) != 0) { + if (spi->bus_width == MSG_EXT_WDTR_BUS_16_BIT) + dval |= DP_WIDE; + else + dval |= DP_NARROW; + } + + if ((spi->valid & CTS_SPI_VALID_SYNC_OFFSET) && + (spi->valid & CTS_SPI_VALID_SYNC_RATE) && + (spi->sync_period && spi->sync_offset)) { + dval |= DP_SYNC; + period = spi->sync_period; + offset = spi->sync_offset; + } +#endif + CAMLOCK_2_MPTLOCK(mpt); + if (dval & DP_DISC_ENABLE) { + mpt->mpt_disc_enable |= (1 << tgt); + } else if (dval & DP_DISC_DISABL) { + mpt->mpt_disc_enable &= ~(1 << tgt); + } + if (dval & DP_TQING_ENABLE) { + mpt->mpt_tag_enable |= (1 << tgt); + } else if (dval & DP_TQING_DISABL) { + mpt->mpt_tag_enable &= ~(1 << tgt); + } + if (dval & DP_WIDTH) { + if (mpt_setwidth(mpt, tgt, dval & DP_WIDE)) { + ccb->ccb_h.status = CAM_REQ_CMP_ERR; + MPTLOCK_2_CAMLOCK(mpt); + xpt_done(ccb); + break; + } + } + if (dval & DP_SYNC) { + if (mpt_setsync(mpt, tgt, period, offset)) { + ccb->ccb_h.status = CAM_REQ_CMP_ERR; + MPTLOCK_2_CAMLOCK(mpt); + xpt_done(ccb); + break; + } + } + MPTLOCK_2_CAMLOCK(mpt); + if (mpt->verbose > 1) { + mpt_prt(mpt, + "SET tgt %d flags %x period %x off %x", + tgt, dval, period, offset); + } + } + ccb->ccb_h.status = CAM_REQ_CMP; + xpt_done(ccb); + break; + + case XPT_GET_TRAN_SETTINGS: + cts = &ccb->cts; + tgt = cts->ccb_h.target_id; + if (mpt->is_fc) { +#ifndef CAM_NEW_TRAN_CODE + /* + * a lot of normal SCSI things don't make sense. + */ + cts->flags = CCB_TRANS_TAG_ENB | CCB_TRANS_DISC_ENB; + cts->valid = CCB_TRANS_DISC_VALID | CCB_TRANS_TQ_VALID; + /* + * How do you measure the width of a high + * speed serial bus? Well, in bytes. + * + * Offset and period make no sense, though, so we set + * (above) a 'base' transfer speed to be gigabit. + */ + cts->bus_width = MSG_EXT_WDTR_BUS_8_BIT; +#else + struct ccb_trans_settings_fc *fc = + &cts->xport_specific.fc; + + cts->protocol = PROTO_SCSI; + cts->protocol_version = SCSI_REV_2; + cts->transport = XPORT_FC; + cts->transport_version = 0; + + fc->valid = CTS_FC_VALID_SPEED; + fc->bitrate = 100000; /* XXX: Need for 2Gb/s */ + /* XXX: need a port database for each target */ +#endif + } else { +#ifdef CAM_NEW_TRAN_CODE + struct ccb_trans_settings_scsi *scsi = + &cts->proto_specific.scsi; + struct ccb_trans_settings_spi *spi = + &cts->xport_specific.spi; +#endif + u_int8_t dval, pval, oval; + + /* + * We aren't going off of Port PAGE2 params for + * tagged queuing or disconnect capabilities + * for current settings. For goal settings, + * we assert all capabilities- we've had some + * problems with reading NVRAM data. + */ + if (IS_CURRENT_SETTINGS(cts)) { + CONFIG_PAGE_SCSI_DEVICE_0 tmp; + dval = 0; + + tmp = mpt->mpt_dev_page0[tgt]; + CAMLOCK_2_MPTLOCK(mpt); + if (mpt_read_cfg_page(mpt, tgt, &tmp.Header)) { + mpt_prt(mpt, + "cannot get target %d DP0", tgt); + } else { + if (mpt->verbose > 1) { + mpt_prt(mpt, + "SPI Tgt %d Page 0: NParms %x Information %x", + tgt, + tmp.NegotiatedParameters, + tmp.Information); + } + } + MPTLOCK_2_CAMLOCK(mpt); + + if (tmp.NegotiatedParameters & + MPI_SCSIDEVPAGE0_NP_WIDE) + dval |= DP_WIDE; + + if (mpt->mpt_disc_enable & (1 << tgt)) { + dval |= DP_DISC_ENABLE; + } + if (mpt->mpt_tag_enable & (1 << tgt)) { + dval |= DP_TQING_ENABLE; + } + oval = (tmp.NegotiatedParameters >> 16) & 0xff; + pval = (tmp.NegotiatedParameters >> 8) & 0xff; + } else { + /* + * XXX: Fix wrt NVRAM someday. Attempts + * XXX: to read port page2 device data + * XXX: just returns zero in these areas. + */ + dval = DP_WIDE|DP_DISC|DP_TQING; + oval = (mpt->mpt_port_page0.Capabilities >> 16); + pval = (mpt->mpt_port_page0.Capabilities >> 8); + } +#ifndef CAM_NEW_TRAN_CODE + cts->flags &= ~(CCB_TRANS_DISC_ENB|CCB_TRANS_TAG_ENB); + if (dval & DP_DISC_ENABLE) { + cts->flags |= CCB_TRANS_DISC_ENB; + } + if (dval & DP_TQING_ENABLE) { + cts->flags |= CCB_TRANS_TAG_ENB; + } + if (dval & DP_WIDE) { + cts->bus_width = MSG_EXT_WDTR_BUS_16_BIT; + } else { + cts->bus_width = MSG_EXT_WDTR_BUS_8_BIT; + } + cts->valid = CCB_TRANS_BUS_WIDTH_VALID | + CCB_TRANS_DISC_VALID | CCB_TRANS_TQ_VALID; + if (oval) { + cts->sync_period = pval; + cts->sync_offset = oval; + cts->valid |= + CCB_TRANS_SYNC_RATE_VALID | + CCB_TRANS_SYNC_OFFSET_VALID; + } +#else + cts->protocol = PROTO_SCSI; + cts->protocol_version = SCSI_REV_2; + cts->transport = XPORT_SPI; + cts->transport_version = 2; + + scsi->flags &= ~CTS_SCSI_FLAGS_TAG_ENB; + spi->flags &= ~CTS_SPI_FLAGS_DISC_ENB; + if (dval & DP_DISC_ENABLE) { + spi->flags |= CTS_SPI_FLAGS_DISC_ENB; + } + if (dval & DP_TQING_ENABLE) { + scsi->flags |= CTS_SCSI_FLAGS_TAG_ENB; + } + if (oval && pval) { + spi->sync_offset = oval; + spi->sync_period = pval; + spi->valid |= CTS_SPI_VALID_SYNC_OFFSET; + spi->valid |= CTS_SPI_VALID_SYNC_RATE; + } + spi->valid |= CTS_SPI_VALID_BUS_WIDTH; + if (dval & DP_WIDE) { + spi->bus_width = MSG_EXT_WDTR_BUS_16_BIT; + } else { + spi->bus_width = MSG_EXT_WDTR_BUS_8_BIT; + } + if (cts->ccb_h.target_lun != CAM_LUN_WILDCARD) { + scsi->valid = CTS_SCSI_VALID_TQ; + spi->valid |= CTS_SPI_VALID_DISC; + } else { + scsi->valid = 0; + } +#endif + if (mpt->verbose > 1) { + mpt_prt(mpt, + "GET %s tgt %d flags %x period %x off %x", + IS_CURRENT_SETTINGS(cts)? "ACTIVE" : + "NVRAM", tgt, dval, pval, oval); + } + } + ccb->ccb_h.status = CAM_REQ_CMP; + xpt_done(ccb); + break; + + case XPT_CALC_GEOMETRY: + { + struct ccb_calc_geometry *ccg; + + ccg = &ccb->ccg; + if (ccg->block_size == 0) { + ccb->ccb_h.status = CAM_REQ_INVALID; + xpt_done(ccb); + break; + } + + cam_calc_geometry(ccg, /*extended*/1); + xpt_done(ccb); + break; + } + case XPT_PATH_INQ: /* Path routing inquiry */ + { + struct ccb_pathinq *cpi = &ccb->cpi; + + cpi->version_num = 1; + cpi->target_sprt = 0; + cpi->hba_eng_cnt = 0; + cpi->max_lun = 7; + cpi->bus_id = cam_sim_bus(sim); + if (mpt->is_fc) { + cpi->max_target = 255; + cpi->hba_misc = PIM_NOBUSRESET; + cpi->initiator_id = cpi->max_target + 1; + cpi->base_transfer_speed = 100000; + cpi->hba_inquiry = PI_TAG_ABLE; + } else { + cpi->initiator_id = mpt->mpt_ini_id; + cpi->base_transfer_speed = 3300; + cpi->hba_inquiry = PI_SDTR_ABLE|PI_TAG_ABLE|PI_WIDE_16; + cpi->hba_misc = 0; + cpi->max_target = 15; + } + + strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); + strncpy(cpi->hba_vid, "LSI", HBA_IDLEN); + strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); + cpi->unit_number = cam_sim_unit(sim); + cpi->ccb_h.status = CAM_REQ_CMP; + xpt_done(ccb); + break; + } + default: + ccb->ccb_h.status = CAM_REQ_INVALID; + xpt_done(ccb); + break; + } +} + +static int +mpt_setwidth(mpt_softc_t *mpt, int tgt, int onoff) +{ + CONFIG_PAGE_SCSI_DEVICE_1 tmp; + tmp = mpt->mpt_dev_page1[tgt]; + if (onoff) { + tmp.RequestedParameters |= MPI_SCSIDEVPAGE1_RP_WIDE; + } else { + tmp.RequestedParameters &= ~MPI_SCSIDEVPAGE1_RP_WIDE; + } + if (mpt_write_cfg_page(mpt, tgt, &tmp.Header)) { + return (-1); + } + if (mpt_read_cfg_page(mpt, tgt, &tmp.Header)) { + return (-1); + } + mpt->mpt_dev_page1[tgt] = tmp; + if (mpt->verbose > 1) { + mpt_prt(mpt, + "SPI Target %d Page 1: RequestedParameters %x Config %x", + tgt, mpt->mpt_dev_page1[tgt].RequestedParameters, + mpt->mpt_dev_page1[tgt].Configuration); + } + return (0); +} + +static int +mpt_setsync(mpt_softc_t *mpt, int tgt, int period, int offset) +{ + CONFIG_PAGE_SCSI_DEVICE_1 tmp; + tmp = mpt->mpt_dev_page1[tgt]; + tmp.RequestedParameters &= + ~MPI_SCSIDEVPAGE1_RP_MIN_SYNC_PERIOD_MASK; + tmp.RequestedParameters &= + ~MPI_SCSIDEVPAGE1_RP_MAX_SYNC_OFFSET_MASK; + tmp.RequestedParameters &= + ~MPI_SCSIDEVPAGE1_RP_DT; + tmp.RequestedParameters &= + ~MPI_SCSIDEVPAGE1_RP_QAS; + tmp.RequestedParameters &= + ~MPI_SCSIDEVPAGE1_RP_IU; + /* + * XXX: For now, we're ignoring specific settings + */ + if (period && offset) { + int factor, offset, np; + factor = (mpt->mpt_port_page0.Capabilities >> 8) & 0xff; + offset = (mpt->mpt_port_page0.Capabilities >> 16) & 0xff; + np = 0; + if (factor < 0x9) { + np |= MPI_SCSIDEVPAGE1_RP_QAS; + np |= MPI_SCSIDEVPAGE1_RP_IU; + } + if (factor < 0xa) { + np |= MPI_SCSIDEVPAGE1_RP_DT; + } + np |= (factor << 8) | (offset << 16); + tmp.RequestedParameters |= np; + } + if (mpt_write_cfg_page(mpt, tgt, &tmp.Header)) { + return (-1); + } + if (mpt_read_cfg_page(mpt, tgt, &tmp.Header)) { + return (-1); + } + mpt->mpt_dev_page1[tgt] = tmp; + if (mpt->verbose > 1) { + mpt_prt(mpt, + "SPI Target %d Page 1: RParams %x Config %x", + tgt, mpt->mpt_dev_page1[tgt].RequestedParameters, + mpt->mpt_dev_page1[tgt].Configuration); + } + return (0); +} diff --git a/sys/dev/mpt/mpt_freebsd.h b/sys/dev/mpt/mpt_freebsd.h new file mode 100644 index 0000000..991e56e --- /dev/null +++ b/sys/dev/mpt/mpt_freebsd.h @@ -0,0 +1,359 @@ +/* $FreeBSD$ */ +/* + * LSI MPT Host Adapter FreeBSD Wrapper Definitions (CAM version) + * + * Copyright (c) 2000, 2001 by Greg Ansley, Adam Prewett + * + * Partially derived from Matty Jacobs ISP driver. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice immediately at the beginning of the file, without modification, + * this list of conditions, and the following disclaimer. + * 2. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + */ +/* + * Additional Copyright (c) 2002 by Matthew Jacob under same license. + */ + +#ifndef _MPT_FREEBSD_H_ +#define _MPT_FREEBSD_H_ + +/* #define RELENG_4 1 */ + +#include <sys/param.h> +#include <sys/systm.h> +#ifdef RELENG_4 +#include <sys/kernel.h> +#include <sys/queue.h> +#include <sys/malloc.h> +#else +#include <sys/endian.h> +#include <sys/lock.h> +#include <sys/kernel.h> +#include <sys/queue.h> +#include <sys/malloc.h> +#include <sys/mutex.h> +#include <sys/condvar.h> +#endif +#include <sys/proc.h> +#include <sys/bus.h> + +#include <machine/bus_memio.h> +#include <machine/bus_pio.h> +#include <machine/bus.h> +#include <machine/clock.h> +#include <machine/cpu.h> + +#include <cam/cam.h> +#include <cam/cam_debug.h> +#include <cam/cam_ccb.h> +#include <cam/cam_sim.h> +#include <cam/cam_xpt.h> +#include <cam/cam_xpt_sim.h> +#include <cam/cam_debug.h> +#include <cam/scsi/scsi_all.h> +#include <cam/scsi/scsi_message.h> + +#include "opt_ddb.h" + +#include "dev/mpt/mpilib/mpi_type.h" +#include "dev/mpt/mpilib/mpi.h" +#include "dev/mpt/mpilib/mpi_cnfg.h" +#include "dev/mpt/mpilib/mpi_fc.h" +#include "dev/mpt/mpilib/mpi_init.h" +#include "dev/mpt/mpilib/mpi_ioc.h" +#include "dev/mpt/mpilib/mpi_lan.h" +#include "dev/mpt/mpilib/mpi_targ.h" + + +#define INLINE __inline + +#ifdef RELENG_4 +#define MPT_IFLAGS INTR_TYPE_CAM +#define MPT_LOCK(mpt) mpt_lockspl(mpt) +#define MPT_UNLOCK(mpt) mpt_unlockspl(mpt) +#define MPTLOCK_2_CAMLOCK MPT_UNLOCK +#define CAMLOCK_2_MPTLOCK MPT_LOCK +#define MPT_LOCK_SETUP(mpt) +#define MPT_LOCK_DESTROY(mpt) +#else +#if LOCKING_WORKED_AS_IT_SHOULD +#define MPT_IFLAGS INTR_TYPE_CAM | INTR_ENTROPY | INTR_MPSAFE +#define MPT_LOCK_SETUP(mpt) \ + mtx_init(&mpt->mpt_lock, "mpt", NULL, MTX_DEF); \ + mpt->mpt_locksetup = 1 +#define MPT_LOCK_DESTROY(mpt) \ + if (mpt->mpt_locksetup) { \ + mtx_destroy(&mpt->mpt_lock); \ + mpt->mpt_locksetup = 0; \ + } + +#define MPT_LOCK(mpt) mtx_lock(&(mpt)->mpt_lock) +#define MPT_UNLOCK(mpt) mtx_unlock(&(mpt)->mpt_lock) +#define MPTLOCK_2_CAMLOCK(mpt) \ + mtx_unlock(&(mpt)->mpt_lock); mtx_lock(&Giant) +#define CAMLOCK_2_MPTLOCK(mpt) \ + mtx_unlock(&Giant); mtx_lock(&(mpt)->mpt_lock) +#else +#define MPT_IFLAGS INTR_TYPE_CAM | INTR_ENTROPY +#define MPT_LOCK_SETUP(mpt) do { } while (0) +#define MPT_LOCK_DESTROY(mpt) do { } while (0) +#define MPT_LOCK(mpt) do { } while (0) +#define MPT_UNLOCK(mpt) do { } while (0) +#define MPTLOCK_2_CAMLOCK(mpt) do { } while (0) +#define CAMLOCK_2_MPTLOCK(mpt) do { } while (0) +#endif +#endif + + + +/* Max MPT Reply we are willing to accept (must be power of 2) */ +#define MPT_REPLY_SIZE 128 + +#define MPT_MAX_REQUESTS(mpt) ((mpt)->is_fc? 1024 : 256) +#define MPT_REQUEST_AREA 512 +#define MPT_SENSE_SIZE 32 /* included in MPT_REQUEST_SIZE */ +#define MPT_REQ_MEM_SIZE(mpt) (MPT_MAX_REQUESTS(mpt) * MPT_REQUEST_AREA) + +/* + * We cannot tell prior to getting IOC facts how big the IOC's request + * area is. Because of this we cannot tell at compile time how many + * simple SG elements we can fit within an IOC request prior to having + * to put in a chain element. + * + * Experimentally we know that the Ultra4 parts have a 96 byte request + * element size and the Fibre Channel units have a 144 byte request + * element size. Therefore, if we have 512-32 (== 480) bytes of request + * area to play with, we have room for between 3 and 5 request sized + * regions- the first of which is the command plus a simple SG list, + * the rest of which are chained continuation SG lists. Given that the + * normal request we use is 48 bytes w/o the first SG element, we can + * assume we have 480-48 == 432 bytes to have simple SG elements and/or + * chain elements. If we assume 32 bit addressing, this works out to + * 54 SG or chain elements. If we assume 5 chain elements, then we have + * a maximum of 49 seperate actual SG segments. + */ + +#define MPT_SGL_MAX 49 + +#define MPT_RQSL(mpt) (mpt->request_frame_size << 2) +#define MPT_NSGL(mpt) (MPT_RQSL(mpt) / sizeof (SGE_SIMPLE32)) + +#define MPT_NSGL_FIRST(mpt) \ + (((mpt->request_frame_size << 2) - \ + sizeof (MSG_SCSI_IO_REQUEST) - \ + sizeof (SGE_IO_UNION)) / sizeof (SGE_SIMPLE32)) + +/* + * Convert a physical address returned from IOC to kvm address + * needed to access the data. + */ +#define MPT_REPLY_PTOV(m, x) \ + ((void *)(&m->reply[((x << 1) - m->reply_phys)])) + +#define ccb_mpt_ptr sim_priv.entries[0].ptr +#define ccb_req_ptr sim_priv.entries[1].ptr + +enum mpt_req_state { + REQ_FREE, REQ_IN_PROGRESS, REQ_TIMEOUT, REQ_ON_CHIP, REQ_DONE +}; +typedef struct req_entry { + u_int16_t index; /* Index of this entry */ + union ccb * ccb; /* CAM request */ + void * req_vbuf; /* Virtual Address of Entry */ + void * sense_vbuf; /* Virtual Address of sense data */ + bus_addr_t req_pbuf; /* Physical Address of Entry */ + bus_addr_t sense_pbuf; /* Physical Address of sense data */ + bus_dmamap_t dmap; /* DMA map for data buffer */ + SLIST_ENTRY(req_entry) link; /* Pointer to next in list */ + enum mpt_req_state debug; /* Debugging */ + u_int32_t sequence; /* Sequence Number */ +} request_t; + + +/* Structure for saving proper values for modifyable PCI configuration registers */ +struct mpt_pci_cfg { + u_int16_t Command; + u_int16_t LatencyTimer_LineSize; + u_int32_t IO_BAR; + u_int32_t Mem0_BAR[2]; + u_int32_t Mem1_BAR[2]; + u_int32_t ROM_BAR; + u_int8_t IntLine; + u_int32_t PMCSR; +}; + +typedef struct mpt_softc { + device_t dev; +#ifdef RELENG_4 + int mpt_splsaved; + u_int32_t mpt_islocked; +#else + struct mtx mpt_lock; +#endif + u_int32_t : 16, + unit : 8, + verbose : 3, + outofbeer : 1, + mpt_locksetup : 1, + disabled : 1, + is_fc : 1, + bus : 1; /* FC929/1030 have two busses */ + + /* + * IOC Facts + */ + u_int16_t mpt_global_credits; + u_int16_t request_frame_size; + u_int8_t mpt_max_devices; + u_int8_t mpt_max_buses; + + /* + * Port Facts + */ + u_int16_t mpt_ini_id; + + + /* + * Device Configuration Information + */ + union { + struct mpt_spi_cfg { + CONFIG_PAGE_SCSI_PORT_0 _port_page0; + CONFIG_PAGE_SCSI_PORT_1 _port_page1; + CONFIG_PAGE_SCSI_PORT_2 _port_page2; + CONFIG_PAGE_SCSI_DEVICE_0 _dev_page0[16]; + CONFIG_PAGE_SCSI_DEVICE_1 _dev_page1[16]; + uint16_t _tag_enable; + uint16_t _disc_enable; + uint16_t _update_params0; + uint16_t _update_params1; + } spi; +#define mpt_port_page0 cfg.spi._port_page0 +#define mpt_port_page1 cfg.spi._port_page1 +#define mpt_port_page2 cfg.spi._port_page2 +#define mpt_dev_page0 cfg.spi._dev_page0 +#define mpt_dev_page1 cfg.spi._dev_page1 +#define mpt_tag_enable cfg.spi._tag_enable +#define mpt_disc_enable cfg.spi._disc_enable +#define mpt_update_params0 cfg.spi._update_params0 +#define mpt_update_params1 cfg.spi._update_params1 + struct mpi_fc_cfg { + u_int8_t nada; + } fc; + } cfg; + + /* + * PCI Hardware info + */ + struct resource * pci_irq; /* Interrupt map for chip */ + void * ih; /* Interupt handle */ + struct mpt_pci_cfg pci_cfg; /* saved PCI conf registers */ + + /* + * DMA Mapping Stuff + */ + + struct resource * pci_reg; /* Register map for chip */ + int pci_reg_id; /* Resource ID */ + bus_space_tag_t pci_st; /* Bus tag for registers */ + bus_space_handle_t pci_sh; /* Bus handle for registers */ + vm_offset_t pci_pa; /* Physical Address */ + + bus_dma_tag_t parent_dmat; /* DMA tag for parent PCI bus */ + bus_dma_tag_t reply_dmat; /* DMA tag for reply memory */ + bus_dmamap_t reply_dmap; /* DMA map for reply memory */ + char * reply; /* KVA of reply memory */ + bus_addr_t reply_phys; /* BusAddr of reply memory */ + + + bus_dma_tag_t buffer_dmat; /* DMA tag for buffers */ + bus_dma_tag_t request_dmat; /* DMA tag for request memroy */ + bus_dmamap_t request_dmap; /* DMA map for request memroy */ + char * request; /* KVA of Request memory */ + bus_addr_t request_phys; /* BusADdr of request memory */ + + /* + * CAM && Software Management + */ + + request_t * request_pool; + SLIST_HEAD(req_queue, req_entry) request_free_list; + + struct cam_sim * sim; + struct cam_path * path; + + u_int32_t sequence; /* Sequence Number */ + u_int32_t timeouts; /* timeout count */ + u_int32_t success; /* successes afer timeout */ + + /* Opposing port in a 929 or 1030, or NULL */ + struct mpt_softc * mpt2; + +} mpt_softc_t; + +#include <dev/mpt/mpt.h> + + +static INLINE void mpt_write(mpt_softc_t *, size_t, u_int32_t); +static INLINE u_int32_t mpt_read(mpt_softc_t *, int); + +static INLINE void +mpt_write(mpt_softc_t *mpt, size_t offset, u_int32_t val) +{ + bus_space_write_4(mpt->pci_st, mpt->pci_sh, offset, val); +} + +static INLINE u_int32_t +mpt_read(mpt_softc_t *mpt, int offset) +{ + return (bus_space_read_4(mpt->pci_st, mpt->pci_sh, offset)); +} + +void mpt_cam_attach(mpt_softc_t *); +void mpt_cam_detach(mpt_softc_t *); +void mpt_done(mpt_softc_t *, u_int32_t); +void mpt_prt(mpt_softc_t *, const char *, ...); +void mpt_set_config_regs(mpt_softc_t *); + +#ifdef RELENG_4 +static INLINE void mpt_lockspl(mpt_softc_t *); +static INLINE void mpt_unlockspl(mpt_softc_t *); + +static INLINE void +mpt_lockspl(mpt_softc_t *mpt) +{ + int s = splcam(); + if (mpt->mpt_islocked++ == 0) { + mpt->mpt_splsaved = s; + } else { + splx(s); + } +} + +static INLINE void +mpt_unlockspl(mpt_softc_t *mpt) +{ + if (mpt->mpt_islocked) { + if (--mpt->mpt_islocked == 0) { + splx(mpt->mpt_splsaved); + } + } +} +#endif + +#endif /* _MPT_FREEBSD_H */ diff --git a/sys/dev/mpt/mpt_pci.c b/sys/dev/mpt/mpt_pci.c new file mode 100644 index 0000000..f0b8003 --- /dev/null +++ b/sys/dev/mpt/mpt_pci.c @@ -0,0 +1,714 @@ +/*- + * PCI specific probe and attach routines for LSI Fusion Adapters + * FreeBSD Version. + * + * Copyright (c) 2000, 2001 by Greg Ansley + * Partially derived from Matt Jacob's ISP driver. + * Copyright (c) 1997, 1998, 1999, 2000, 2001, 2002 by Matthew Jacob + * Feral Software + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice immediately at the beginning of the file, without modification, + * this list of conditions, and the following disclaimer. + * 2. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <sys/cdefs.h> +__FBSDID("$FreeBSD$"); + +#include <sys/param.h> +#include <sys/systm.h> +#include <sys/kernel.h> +#include <sys/module.h> +#include <sys/bus.h> + +#include <dev/pci/pcireg.h> +#include <dev/pci/pcivar.h> + +#include <machine/bus_memio.h> +#include <machine/bus_pio.h> +#include <machine/bus.h> +#include <machine/resource.h> +#include <sys/rman.h> +#include <sys/malloc.h> + +#include <dev/mpt/mpt_freebsd.h> + +#ifndef PCI_VENDOR_LSI +#define PCI_VENDOR_LSI 0x1000 +#endif + +#ifndef PCI_PRODUCT_LSI_FC909 +#define PCI_PRODUCT_LSI_FC909 0x0620 +#endif + +#ifndef PCI_PRODUCT_LSI_FC909A +#define PCI_PRODUCT_LSI_FC909A 0x0621 +#endif + +#ifndef PCI_PRODUCT_LSI_FC919 +#define PCI_PRODUCT_LSI_FC919 0x0624 +#endif + +#ifndef PCI_PRODUCT_LSI_FC929 +#define PCI_PRODUCT_LSI_FC929 0x0622 +#endif + +#ifndef PCI_PRODUCT_LSI_1030 +#define PCI_PRODUCT_LSI_1030 0x0030 +#endif + +#ifndef PCIM_CMD_SERRESPEN +#define PCIM_CMD_SERRESPEN 0x0100 +#endif + + + +#define MEM_MAP_REG 0x14 +#define MEM_MAP_SRAM 0x1C + +static int mpt_probe(device_t); +static int mpt_attach(device_t); +static void mpt_free_bus_resources(mpt_softc_t *mpt); +static int mpt_detach(device_t); +static int mpt_shutdown(device_t); +static int mpt_dma_mem_alloc(mpt_softc_t *mpt); +static void mpt_dma_mem_free(mpt_softc_t *mpt); +static void mpt_read_config_regs(mpt_softc_t *mpt); +static void mpt_pci_intr(void *); + +static device_method_t mpt_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, mpt_probe), + DEVMETHOD(device_attach, mpt_attach), + DEVMETHOD(device_detach, mpt_detach), + DEVMETHOD(device_shutdown, mpt_shutdown), + { 0, 0 } +}; + +static driver_t mpt_driver = { + "mpt", mpt_methods, sizeof (mpt_softc_t) +}; +static devclass_t mpt_devclass; +DRIVER_MODULE(mpt, pci, mpt_driver, mpt_devclass, 0, 0); +MODULE_VERSION(mpt, 1); + +int +mpt_intr(void *dummy) +{ + int nrepl = 0; + u_int32_t reply; + mpt_softc_t *mpt = (mpt_softc_t *)dummy; + + if ((mpt_read(mpt, MPT_OFFSET_INTR_STATUS) & MPT_INTR_REPLY_READY) == 0) + return (0); + reply = mpt_pop_reply_queue(mpt); + while (reply != MPT_REPLY_EMPTY) { + nrepl++; + if (mpt->verbose > 1) { + if ((reply & MPT_CONTEXT_REPLY) != 0) { + /* Address reply; IOC has something to say */ + mpt_print_reply(MPT_REPLY_PTOV(mpt, reply)); + } else { + /* Context reply ; all went well */ + mpt_prt(mpt, "context %u reply OK", reply); + } + } + mpt_done(mpt, reply); + reply = mpt_pop_reply_queue(mpt); + } + return (nrepl != 0); +} + +static int +mpt_probe(device_t dev) +{ + char *desc; + + if (pci_get_vendor(dev) != PCI_VENDOR_LSI) + return (ENXIO); + + switch ((pci_get_device(dev) & ~1)) { + case PCI_PRODUCT_LSI_FC909: + desc = "LSILogic FC909 FC Adapter"; + break; + case PCI_PRODUCT_LSI_FC909A: + desc = "LSILogic FC909A FC Adapter"; + break; + case PCI_PRODUCT_LSI_FC919: + desc = "LSILogic FC919 FC Adapter"; + break; + case PCI_PRODUCT_LSI_FC929: + desc = "LSILogic FC929 FC Adapter"; + break; + case PCI_PRODUCT_LSI_1030: + desc = "LSILogic 1030 Ultra4 Adapter"; + break; + default: + return (ENXIO); + } + + device_set_desc(dev, desc); + return (0); +} + +#ifdef RELENG_4 +static void +mpt_set_options(mpt_softc_t *mpt) +{ + int bitmap; + + bitmap = 0; + if (getenv_int("mpt_disable", &bitmap)) { + if (bitmap & (1 << mpt->unit)) { + mpt->disabled = 1; + } + } + + bitmap = 0; + if (getenv_int("mpt_debug", &bitmap)) { + if (bitmap & (1 << mpt->unit)) { + mpt->verbose = 2; + } + } + +} +#else +static void +mpt_set_options(mpt_softc_t *mpt) +{ + int tval; + + tval = 0; + if (resource_int_value(device_get_name(mpt->dev), + device_get_unit(mpt->dev), "disable", &tval) == 0 && tval != 0) { + mpt->disabled = 1; + } + tval = 0; + if (resource_int_value(device_get_name(mpt->dev), + device_get_unit(mpt->dev), "debug", &tval) == 0 && tval != 0) { + mpt->verbose += tval; + } +} +#endif + + +static void +mpt_link_peer(mpt_softc_t *mpt) +{ + mpt_softc_t *mpt2; + + if (mpt->unit == 0) { + return; + } + + /* + * XXX: depends on probe order + */ + mpt2 = (mpt_softc_t *) devclass_get_softc(mpt_devclass, mpt->unit-1); + + if (mpt2 == NULL) { + return; + } + if (pci_get_vendor(mpt2->dev) != pci_get_vendor(mpt->dev)) { + return; + } + if (pci_get_device(mpt2->dev) != pci_get_device(mpt->dev)) { + return; + } + mpt->mpt2 = mpt2; + mpt2->mpt2 = mpt; + if (mpt->verbose) { + mpt_prt(mpt, "linking with peer (mpt%d)", + device_get_unit(mpt2->dev)); + } +} + + +static int +mpt_attach(device_t dev) +{ + int iqd; + u_int32_t data, cmd; + mpt_softc_t *mpt; + + /* Allocate the softc structure */ + mpt = (mpt_softc_t*) device_get_softc(dev); + if (mpt == NULL) { + device_printf(dev, "cannot allocate softc\n"); + return (ENOMEM); + } + bzero(mpt, sizeof (mpt_softc_t)); + switch ((pci_get_device(dev) & ~1)) { + case PCI_PRODUCT_LSI_FC909: + case PCI_PRODUCT_LSI_FC909A: + case PCI_PRODUCT_LSI_FC919: + case PCI_PRODUCT_LSI_FC929: + mpt->is_fc = 1; + break; + default: + break; + } + mpt->dev = dev; + mpt->unit = device_get_unit(dev); + mpt_set_options(mpt); + mpt->verbose += (bootverbose != 0)? 1 : 0; + + /* Make sure memory access decoders are enabled */ + cmd = pci_read_config(dev, PCIR_COMMAND, 2); + if ((cmd & PCIM_CMD_MEMEN) == 0) { + device_printf(dev, "Memory accesses disabled"); + goto bad; + } + + /* + * Make sure that SERR, PERR, WRITE INVALIDATE and BUSMASTER are set. + */ + cmd |= + PCIM_CMD_SERRESPEN | PCIM_CMD_PERRESPEN | + PCIM_CMD_BUSMASTEREN | PCIM_CMD_MWRICEN; + pci_write_config(dev, PCIR_COMMAND, cmd, 2); + + /* + * Make sure we've disabled the ROM. + */ + data = pci_read_config(dev, PCIR_BIOS, 4); + data &= ~1; + pci_write_config(dev, PCIR_BIOS, data, 4); + + + /* + * Is this part a dual? + * If so, link with our partner (around yet) + */ + if ((pci_get_device(dev) & ~1) == PCI_PRODUCT_LSI_FC929 || + (pci_get_device(dev) & ~1) == PCI_PRODUCT_LSI_1030) { + mpt_link_peer(mpt); + } + + /* Set up the memory regions */ + /* Allocate kernel virtual memory for the 9x9's Mem0 region */ + mpt->pci_reg_id = MEM_MAP_REG; + mpt->pci_reg = bus_alloc_resource(dev, SYS_RES_MEMORY, + &mpt->pci_reg_id, 0, ~0, 0, RF_ACTIVE); + if (mpt->pci_reg == NULL) { + device_printf(dev, "unable to map any ports\n"); + goto bad; + } + mpt->pci_st = rman_get_bustag(mpt->pci_reg); + mpt->pci_sh = rman_get_bushandle(mpt->pci_reg); + /* Get the Physical Address */ + mpt->pci_pa = rman_get_start(mpt->pci_reg); + + /* Get a handle to the interrupt */ + iqd = 0; + mpt->pci_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &iqd, 0, ~0, + 1, RF_ACTIVE | RF_SHAREABLE); + if (mpt->pci_irq == NULL) { + device_printf(dev, "could not allocate interrupt\n"); + goto bad; + } + + /* Register the interrupt handler */ + if (bus_setup_intr(dev, mpt->pci_irq, MPT_IFLAGS, mpt_pci_intr, + mpt, &mpt->ih)) { + device_printf(dev, "could not setup interrupt\n"); + goto bad; + } + + MPT_LOCK_SETUP(mpt); + + /* Disable interrupts at the part */ + mpt_disable_ints(mpt); + + /* Allocate dma memory */ + if (mpt_dma_mem_alloc(mpt)) { + device_printf(dev, "Could not allocate DMA memory\n"); + goto bad; + } + + /* + * Save the PCI config register values + * + * Hard resets are known to screw up the BAR for diagnostic + * memory accesses (Mem1). + * + * Using Mem1 is known to make the chip stop responding to + * configuration space transfers, so we need to save it now + */ + + mpt_read_config_regs(mpt); + + /* Initialize the hardware */ + if (mpt->disabled == 0) { + MPT_LOCK(mpt); + if (mpt_init(mpt, MPT_DB_INIT_HOST) != 0) { + MPT_UNLOCK(mpt); + goto bad; + } + + /* + * Attach to CAM + */ + MPTLOCK_2_CAMLOCK(mpt); + mpt_cam_attach(mpt); + CAMLOCK_2_MPTLOCK(mpt); + MPT_UNLOCK(mpt); + } + + return (0); + +bad: + mpt_dma_mem_free(mpt); + mpt_free_bus_resources(mpt); + + /* + * but return zero to preserve unit numbering + */ + return (0); +} + +/* + * Free bus resources + */ +static void +mpt_free_bus_resources(mpt_softc_t *mpt) +{ + if (mpt->ih) { + bus_teardown_intr(mpt->dev, mpt->pci_irq, mpt->ih); + mpt->ih = 0; + } + + if (mpt->pci_irq) { + bus_release_resource(mpt->dev, SYS_RES_IRQ, 0, mpt->pci_irq); + mpt->pci_irq = 0; + } + + if (mpt->pci_reg) { + bus_release_resource(mpt->dev, SYS_RES_MEMORY, mpt->pci_reg_id, + mpt->pci_reg); + mpt->pci_reg = 0; + } + MPT_LOCK_DESTROY(mpt); +} + + +/* + * Disconnect ourselves from the system. + */ +static int +mpt_detach(device_t dev) +{ + mpt_softc_t *mpt; + mpt = (mpt_softc_t*) device_get_softc(dev); + + mpt_prt(mpt, "mpt_detach"); + + if (mpt) { + mpt_disable_ints(mpt); + mpt_cam_detach(mpt); + mpt_reset(mpt); + mpt_dma_mem_free(mpt); + mpt_free_bus_resources(mpt); + } + return(0); +} + + +/* + * Disable the hardware + */ +static int +mpt_shutdown(device_t dev) +{ + mpt_softc_t *mpt; + mpt = (mpt_softc_t*) device_get_softc(dev); + + if (mpt) { + mpt_reset(mpt); + } + return(0); +} + + +struct imush { + mpt_softc_t *mpt; + int error; + u_int32_t phys; +}; + +static void +mpt_map_rquest(void *arg, bus_dma_segment_t *segs, int nseg, int error) +{ + struct imush *imushp = (struct imush *) arg; + imushp->error = error; + imushp->phys = segs->ds_addr; +} + + +static int +mpt_dma_mem_alloc(mpt_softc_t *mpt) +{ + int i, error; + u_char *vptr; + u_int32_t pptr, end; + size_t len; + struct imush im; + device_t dev = mpt->dev; + + /* Check if we alreay have allocated the reply memory */ + if (mpt->reply_phys != 0) { + return 0; + } + + len = sizeof (request_t *) * MPT_REQ_MEM_SIZE(mpt); +#ifdef RELENG_4 + mpt->request_pool = (request_t *) malloc(len, M_DEVBUF, M_WAITOK); + if (mpt->request_pool == NULL) { + device_printf(dev, "cannot allocate request pool\n"); + return (1); + } + bzero(mpt->request_pool, len); +#else + mpt->request_pool = (request_t *) + malloc(len, M_DEVBUF, M_WAITOK | M_ZERO); + if (mpt->request_pool == NULL) { + device_printf(dev, "cannot allocate request pool\n"); + return (1); + } +#endif + + /* + * Create a dma tag for this device + * + * Align at page boundaries, limit to 32-bit addressing + * (The chip supports 64-bit addressing, but this driver doesn't) + */ + if (bus_dma_tag_create(NULL, PAGE_SIZE, 0, BUS_SPACE_MAXADDR_32BIT, + BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE_32BIT, + BUS_SPACE_MAXSIZE_32BIT, BUS_SPACE_UNRESTRICTED, 0, + busdma_lock_mutex, &Giant, &mpt->parent_dmat) != 0) { + device_printf(dev, "cannot create parent dma tag\n"); + return (1); + } + + /* Create a child tag for reply buffers */ + if (bus_dma_tag_create(mpt->parent_dmat, PAGE_SIZE, + 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, + NULL, NULL, PAGE_SIZE, 1, BUS_SPACE_MAXSIZE_32BIT, 0, + busdma_lock_mutex, &Giant, &mpt->reply_dmat) != 0) { + device_printf(dev, "cannot create a dma tag for replies\n"); + return (1); + } + + /* Allocate some DMA accessable memory for replies */ + if (bus_dmamem_alloc(mpt->reply_dmat, (void **)&mpt->reply, + BUS_DMA_NOWAIT, &mpt->reply_dmap) != 0) { + device_printf(dev, "cannot allocate %lu bytes of reply memory\n", + (u_long)PAGE_SIZE); + return (1); + } + + im.mpt = mpt; + im.error = 0; + + /* Load and lock it into "bus space" */ + bus_dmamap_load(mpt->reply_dmat, mpt->reply_dmap, mpt->reply, + PAGE_SIZE, mpt_map_rquest, &im, 0); + + if (im.error) { + device_printf(dev, + "error %d loading dma map for DMA reply queue\n", im.error); + return (1); + } + mpt->reply_phys = im.phys; + + /* Create a child tag for data buffers */ + if (bus_dma_tag_create(mpt->parent_dmat, PAGE_SIZE, + 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, + NULL, NULL, MAXBSIZE, MPT_SGL_MAX, BUS_SPACE_MAXSIZE_32BIT, 0, + busdma_lock_mutex, &Giant, &mpt->buffer_dmat) != 0) { + device_printf(dev, + "cannot create a dma tag for data buffers\n"); + return (1); + } + + /* Create a child tag for request buffers */ + if (bus_dma_tag_create(mpt->parent_dmat, PAGE_SIZE, + 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, + NULL, NULL, MPT_REQ_MEM_SIZE(mpt), 1, BUS_SPACE_MAXSIZE_32BIT, 0, + busdma_lock_mutex, &Giant, &mpt->request_dmat) != 0) { + device_printf(dev, "cannot create a dma tag for requests\n"); + return (1); + } + + /* Allocate some DMA accessable memory for requests */ + if (bus_dmamem_alloc(mpt->request_dmat, (void **)&mpt->request, + BUS_DMA_NOWAIT, &mpt->request_dmap) != 0) { + device_printf(dev, + "cannot allocate %d bytes of request memory\n", + MPT_REQ_MEM_SIZE(mpt)); + return (1); + } + + im.mpt = mpt; + im.error = 0; + + /* Load and lock it into "bus space" */ + bus_dmamap_load(mpt->request_dmat, mpt->request_dmap, mpt->request, + MPT_REQ_MEM_SIZE(mpt), mpt_map_rquest, &im, 0); + + if (im.error) { + device_printf(dev, + "error %d loading dma map for DMA request queue\n", + im.error); + return (1); + } + mpt->request_phys = im.phys; + + i = 0; + pptr = mpt->request_phys; + vptr = mpt->request; + end = pptr + MPT_REQ_MEM_SIZE(mpt); + while(pptr < end) { + request_t *req = &mpt->request_pool[i]; + req->index = i++; + + /* Store location of Request Data */ + req->req_pbuf = pptr; + req->req_vbuf = vptr; + + pptr += MPT_REQUEST_AREA; + vptr += MPT_REQUEST_AREA; + + req->sense_pbuf = (pptr - MPT_SENSE_SIZE); + req->sense_vbuf = (vptr - MPT_SENSE_SIZE); + + error = bus_dmamap_create(mpt->buffer_dmat, 0, &req->dmap); + if (error) { + device_printf(dev, + "error %d creating per-cmd DMA maps\n", error); + return (1); + } + } + return (0); +} + + + +/* Deallocate memory that was allocated by mpt_dma_mem_alloc + */ +static void +mpt_dma_mem_free(mpt_softc_t *mpt) +{ + int i; + + /* Make sure we aren't double destroying */ + if (mpt->reply_dmat == 0) { + if (mpt->verbose) + device_printf(mpt->dev,"Already released dma memory\n"); + return; + } + + for (i = 0; i < MPT_MAX_REQUESTS(mpt); i++) { + bus_dmamap_destroy(mpt->buffer_dmat, mpt->request_pool[i].dmap); + } + bus_dmamap_unload(mpt->request_dmat, mpt->request_dmap); + bus_dmamem_free(mpt->request_dmat, mpt->request, mpt->request_dmap); + bus_dma_tag_destroy(mpt->request_dmat); + bus_dma_tag_destroy(mpt->buffer_dmat); + bus_dmamap_unload(mpt->reply_dmat, mpt->reply_dmap); + bus_dmamem_free(mpt->reply_dmat, mpt->reply, mpt->reply_dmap); + bus_dma_tag_destroy(mpt->reply_dmat); + bus_dma_tag_destroy(mpt->parent_dmat); + mpt->reply_dmat = 0; + free(mpt->request_pool, M_DEVBUF); + mpt->request_pool = 0; + +} + + + +/* Reads modifiable (via PCI transactions) config registers */ +static void +mpt_read_config_regs(mpt_softc_t *mpt) +{ + mpt->pci_cfg.Command = pci_read_config(mpt->dev, PCIR_COMMAND, 2); + mpt->pci_cfg.LatencyTimer_LineSize = + pci_read_config(mpt->dev, PCIR_CACHELNSZ, 2); + mpt->pci_cfg.IO_BAR = pci_read_config(mpt->dev, PCIR_BAR(0), 4); + mpt->pci_cfg.Mem0_BAR[0] = pci_read_config(mpt->dev, PCIR_BAR(1), 4); + mpt->pci_cfg.Mem0_BAR[1] = pci_read_config(mpt->dev, PCIR_BAR(2), 4); + mpt->pci_cfg.Mem1_BAR[0] = pci_read_config(mpt->dev, PCIR_BAR(3), 4); + mpt->pci_cfg.Mem1_BAR[1] = pci_read_config(mpt->dev, PCIR_BAR(4), 4); + mpt->pci_cfg.ROM_BAR = pci_read_config(mpt->dev, PCIR_BIOS, 4); + mpt->pci_cfg.IntLine = pci_read_config(mpt->dev, PCIR_INTLINE, 1); + mpt->pci_cfg.PMCSR = pci_read_config(mpt->dev, 0x44, 4); +} + +/* Sets modifiable config registers */ +void +mpt_set_config_regs(mpt_softc_t *mpt) +{ + u_int32_t val; + +#define MPT_CHECK(reg, offset, size) \ + val = pci_read_config(mpt->dev, offset, size); \ + if (mpt->pci_cfg.reg != val) { \ + mpt_prt(mpt, \ + "Restoring " #reg " to 0x%X from 0x%X\n", \ + mpt->pci_cfg.reg, val); \ + } + + if (mpt->verbose) { + MPT_CHECK(Command, PCIR_COMMAND, 2); + MPT_CHECK(LatencyTimer_LineSize, PCIR_CACHELNSZ, 2); + MPT_CHECK(IO_BAR, PCIR_BAR(0), 4); + MPT_CHECK(Mem0_BAR[0], PCIR_BAR(1), 4); + MPT_CHECK(Mem0_BAR[1], PCIR_BAR(2), 4); + MPT_CHECK(Mem1_BAR[0], PCIR_BAR(3), 4); + MPT_CHECK(Mem1_BAR[1], PCIR_BAR(4), 4); + MPT_CHECK(ROM_BAR, PCIR_BIOS, 4); + MPT_CHECK(IntLine, PCIR_INTLINE, 1); + MPT_CHECK(PMCSR, 0x44, 4); + } +#undef MPT_CHECK + + pci_write_config(mpt->dev, PCIR_COMMAND, mpt->pci_cfg.Command, 2); + pci_write_config(mpt->dev, PCIR_CACHELNSZ, + mpt->pci_cfg.LatencyTimer_LineSize, 2); + pci_write_config(mpt->dev, PCIR_BAR(0), mpt->pci_cfg.IO_BAR, 4); + pci_write_config(mpt->dev, PCIR_BAR(1), mpt->pci_cfg.Mem0_BAR[0], 4); + pci_write_config(mpt->dev, PCIR_BAR(2), mpt->pci_cfg.Mem0_BAR[1], 4); + pci_write_config(mpt->dev, PCIR_BAR(3), mpt->pci_cfg.Mem1_BAR[0], 4); + pci_write_config(mpt->dev, PCIR_BAR(4), mpt->pci_cfg.Mem1_BAR[1], 4); + pci_write_config(mpt->dev, PCIR_BIOS, mpt->pci_cfg.ROM_BAR, 4); + pci_write_config(mpt->dev, PCIR_INTLINE, mpt->pci_cfg.IntLine, 1); + pci_write_config(mpt->dev, 0x44, mpt->pci_cfg.PMCSR, 4); +} + +static void +mpt_pci_intr(void *arg) +{ + mpt_softc_t *mpt = arg; + MPT_LOCK(mpt); + (void) mpt_intr(mpt); + MPT_UNLOCK(mpt); +} |
