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path: root/sys/dev/hwpmc/hwpmc_armv7.c
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Diffstat (limited to 'sys/dev/hwpmc/hwpmc_armv7.c')
-rw-r--r--sys/dev/hwpmc/hwpmc_armv7.c90
1 files changed, 25 insertions, 65 deletions
diff --git a/sys/dev/hwpmc/hwpmc_armv7.c b/sys/dev/hwpmc/hwpmc_armv7.c
index 66d4971..469eca8 100644
--- a/sys/dev/hwpmc/hwpmc_armv7.c
+++ b/sys/dev/hwpmc/hwpmc_armv7.c
@@ -39,9 +39,6 @@ __FBSDID("$FreeBSD$");
#include <machine/pmc_mdep.h>
#include <machine/cpu.h>
-#define CPU_ID_CORTEX_VER_MASK 0xff
-#define CPU_ID_CORTEX_VER_SHIFT 4
-
static int armv7_npmcs;
struct armv7_event_code_map {
@@ -49,49 +46,11 @@ struct armv7_event_code_map {
uint8_t pe_code;
};
-const struct armv7_event_code_map armv7_event_codes[] = {
- { PMC_EV_ARMV7_PMNC_SW_INCR, 0x00 },
- { PMC_EV_ARMV7_L1_ICACHE_REFILL, 0x01 },
- { PMC_EV_ARMV7_ITLB_REFILL, 0x02 },
- { PMC_EV_ARMV7_L1_DCACHE_REFILL, 0x03 },
- { PMC_EV_ARMV7_L1_DCACHE_ACCESS, 0x04 },
- { PMC_EV_ARMV7_DTLB_REFILL, 0x05 },
- { PMC_EV_ARMV7_MEM_READ, 0x06 },
- { PMC_EV_ARMV7_MEM_WRITE, 0x07 },
- { PMC_EV_ARMV7_INSTR_EXECUTED, 0x08 },
- { PMC_EV_ARMV7_EXC_TAKEN, 0x09 },
- { PMC_EV_ARMV7_EXC_EXECUTED, 0x0A },
- { PMC_EV_ARMV7_CID_WRITE, 0x0B },
- { PMC_EV_ARMV7_PC_WRITE, 0x0C },
- { PMC_EV_ARMV7_PC_IMM_BRANCH, 0x0D },
- { PMC_EV_ARMV7_PC_PROC_RETURN, 0x0E },
- { PMC_EV_ARMV7_MEM_UNALIGNED_ACCESS, 0x0F },
- { PMC_EV_ARMV7_PC_BRANCH_MIS_PRED, 0x10 },
- { PMC_EV_ARMV7_CLOCK_CYCLES, 0x11 },
- { PMC_EV_ARMV7_PC_BRANCH_PRED, 0x12 },
- { PMC_EV_ARMV7_MEM_ACCESS, 0x13 },
- { PMC_EV_ARMV7_L1_ICACHE_ACCESS, 0x14 },
- { PMC_EV_ARMV7_L1_DCACHE_WB, 0x15 },
- { PMC_EV_ARMV7_L2_CACHE_ACCESS, 0x16 },
- { PMC_EV_ARMV7_L2_CACHE_REFILL, 0x17 },
- { PMC_EV_ARMV7_L2_CACHE_WB, 0x18 },
- { PMC_EV_ARMV7_BUS_ACCESS, 0x19 },
- { PMC_EV_ARMV7_MEM_ERROR, 0x1A },
- { PMC_EV_ARMV7_INSTR_SPEC, 0x1B },
- { PMC_EV_ARMV7_TTBR_WRITE, 0x1C },
- { PMC_EV_ARMV7_BUS_CYCLES, 0x1D },
- { PMC_EV_ARMV7_CPU_CYCLES, 0xFF },
-};
-
-const int armv7_event_codes_size =
- sizeof(armv7_event_codes) / sizeof(armv7_event_codes[0]);
-
/*
* Per-processor information.
*/
struct armv7_cpu {
struct pmc_hw *pc_armv7pmcs;
- int cortex_ver;
};
static struct armv7_cpu **armv7_pcpu;
@@ -173,10 +132,10 @@ static int
armv7_allocate_pmc(int cpu, int ri, struct pmc *pm,
const struct pmc_op_pmcallocate *a)
{
- uint32_t caps, config;
struct armv7_cpu *pac;
enum pmc_event pe;
- int i;
+ uint32_t config;
+ uint32_t caps;
KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
("[armv7,%d] illegal CPU value %d", __LINE__, cpu));
@@ -190,18 +149,10 @@ armv7_allocate_pmc(int cpu, int ri, struct pmc *pm,
return (EINVAL);
pe = a->pm_ev;
- for (i = 0; i < armv7_event_codes_size; i++) {
- if (armv7_event_codes[i].pe_ev == pe) {
- config = armv7_event_codes[i].pe_code;
- break;
- }
- }
- if (i == armv7_event_codes_size)
- return EINVAL;
-
+ config = (pe & EVENT_ID_MASK);
pm->pm_md.pm_armv7.pm_armv7_evsel = config;
- PMCDBG2(MDP,ALL,2,"armv7-allocate ri=%d -> config=0x%x", ri, config);
+ PMCDBG2(MDP, ALL, 2, "armv7-allocate ri=%d -> config=0x%x", ri, config);
return 0;
}
@@ -225,7 +176,7 @@ armv7_read_pmc(int cpu, int ri, pmc_value_t *v)
else
tmp = armv7_pmcn_read(ri);
- PMCDBG2(MDP,REA,2,"armv7-read id=%d -> %jd", ri, tmp);
+ PMCDBG2(MDP, REA, 2, "armv7-read id=%d -> %jd", ri, tmp);
if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
*v = ARMV7_PERFCTR_VALUE_TO_RELOAD_COUNT(tmp);
else
@@ -249,7 +200,7 @@ armv7_write_pmc(int cpu, int ri, pmc_value_t v)
if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
v = ARMV7_RELOAD_COUNT_TO_PERFCTR_VALUE(v);
- PMCDBG3(MDP,WRI,1,"armv7-write cpu=%d ri=%d v=%jx", cpu, ri, v);
+ PMCDBG3(MDP, WRI, 1, "armv7-write cpu=%d ri=%d v=%jx", cpu, ri, v);
if (pm->pm_md.pm_armv7.pm_armv7_evsel == 0xFF)
cp15_pmccntr_set(v);
@@ -264,7 +215,7 @@ armv7_config_pmc(int cpu, int ri, struct pmc *pm)
{
struct pmc_hw *phw;
- PMCDBG3(MDP,CFG,1, "cpu=%d ri=%d pm=%p", cpu, ri, pm);
+ PMCDBG3(MDP, CFG, 1, "cpu=%d ri=%d pm=%p", cpu, ri, pm);
KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
("[armv7,%d] illegal CPU value %d", __LINE__, cpu));
@@ -457,20 +408,15 @@ armv7_pcpu_init(struct pmc_mdep *md, int cpu)
struct pmc_cpu *pc;
uint32_t pmnc;
int first_ri;
- int cpuid;
int i;
KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
("[armv7,%d] wrong cpu number %d", __LINE__, cpu));
- PMCDBG1(MDP,INI,1,"armv7-init cpu=%d", cpu);
+ PMCDBG1(MDP, INI, 1, "armv7-init cpu=%d", cpu);
armv7_pcpu[cpu] = pac = malloc(sizeof(struct armv7_cpu), M_PMC,
M_WAITOK|M_ZERO);
- cpuid = cpu_ident();
- pac->cortex_ver = (cpuid >> CPU_ID_CORTEX_VER_SHIFT) & \
- CPU_ID_CORTEX_VER_MASK;
-
pac->pc_armv7pmcs = malloc(sizeof(struct pmc_hw) * armv7_npmcs,
M_PMC, M_WAITOK|M_ZERO);
pc = pmc_pcpu[cpu];
@@ -509,14 +455,15 @@ pmc_armv7_initialize()
{
struct pmc_mdep *pmc_mdep;
struct pmc_classdep *pcd;
+ int idcode;
int reg;
reg = cp15_pmcr_get();
-
armv7_npmcs = (reg >> ARMV7_PMNC_N_SHIFT) & \
ARMV7_PMNC_N_MASK;
+ idcode = (reg & ARMV7_IDCODE_MASK) >> ARMV7_IDCODE_SHIFT;
- PMCDBG1(MDP,INI,1,"armv7-init npmcs=%d", armv7_npmcs);
+ PMCDBG1(MDP, INI, 1, "armv7-init npmcs=%d", armv7_npmcs);
/*
* Allocate space for pointers to PMC HW descriptors and for
@@ -527,7 +474,20 @@ pmc_armv7_initialize()
/* Just one class */
pmc_mdep = pmc_mdep_alloc(1);
- pmc_mdep->pmd_cputype = PMC_CPU_ARMV7;
+
+ switch (idcode) {
+ case ARMV7_IDCODE_CORTEX_A9:
+ pmc_mdep->pmd_cputype = PMC_CPU_ARMV7_CORTEX_A9;
+ break;
+ default:
+ case ARMV7_IDCODE_CORTEX_A8:
+ /*
+ * On A8 we implemented common events only,
+ * so use it for the rest of machines.
+ */
+ pmc_mdep->pmd_cputype = PMC_CPU_ARMV7_CORTEX_A8;
+ break;
+ }
pcd = &pmc_mdep->pmd_classdep[PMC_MDEP_CLASS_INDEX_ARMV7];
pcd->pcd_caps = ARMV7_PMC_CAPS;
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