diff options
Diffstat (limited to 'sys/dev/et/if_etreg.h')
| -rw-r--r-- | sys/dev/et/if_etreg.h | 308 |
1 files changed, 136 insertions, 172 deletions
diff --git a/sys/dev/et/if_etreg.h b/sys/dev/et/if_etreg.h index 136f6fb..637c194 100644 --- a/sys/dev/et/if_etreg.h +++ b/sys/dev/et/if_etreg.h @@ -73,50 +73,6 @@ #ifndef _IF_ETREG_H #define _IF_ETREG_H -/* - * __BIT(n): Return a bitmask with bit n set, where the least - * significant bit is bit 0. - * - * __BITS(m, n): Return a bitmask with bits m through n, inclusive, - * set. It does not matter whether m>n or m<=n. The - * least significant bit is bit 0. - * - * A "bitfield" is a span of consecutive bits defined by a bitmask, - * where 1s select the bits in the bitfield. __SHIFTIN, __SHIFTOUT, - * and __SHIFTOUT_MASK help read and write bitfields from device - * registers. - * - * __SHIFTIN(v, mask): Left-shift bits `v' into the bitfield - * defined by `mask', and return them. No - * side-effects. - * - * __SHIFTOUT(v, mask): Extract and return the bitfield selected - * by `mask' from `v', right-shifting the - * bits so that the rightmost selected bit - * is at bit 0. No side-effects. - * - * __SHIFTOUT_MASK(mask): Right-shift the bits in `mask' so that - * the rightmost non-zero bit is at bit - * 0. This is useful for finding the - * greatest unsigned value that a bitfield - * can hold. No side-effects. Note that - * __SHIFTOUT_MASK(m) = __SHIFTOUT(m, m). - */ - -/* __BIT(n): nth bit, where __BIT(0) == 0x1. */ -#define __BIT(__n) (((__n) == 32) ? 0 : ((uint32_t)1 << (__n))) - -/* __BITS(m, n): bits m through n, m < n. */ -#define __BITS(__m, __n) \ - ((__BIT(MAX((__m), (__n)) + 1) - 1) ^ (__BIT(MIN((__m), (__n))) - 1)) - -/* Find least significant bit that is set */ -#define __LOWEST_SET_BIT(__mask) ((((__mask) - 1) & (__mask)) ^ (__mask)) - -#define __SHIFTOUT(__x, __mask) (((__x) & (__mask)) / __LOWEST_SET_BIT(__mask)) -#define __SHIFTIN(__x, __mask) ((__x) * __LOWEST_SET_BIT(__mask)) -#define __SHIFTOUT_MASK(__mask) __SHIFTOUT((__mask), (__mask)) - #define ET_MEM_TXSIZE_EX 182 #define ET_MEM_RXSIZE_MIN 608 #define ET_MEM_RXSIZE_DEFAULT 11216 @@ -159,10 +115,6 @@ #define ET_PCIV_REPLAY_TIMER_256 (1248 + ET_REPLAY_TIMER_RX_L0S_ADJ) #define ET_PCIR_L0S_L1_LATENCY 0xcf -#define ET_PCIM_L0S_LATENCY __BITS(2, 0) -#define ET_PCIM_L1_LATENCY __BITS(5, 3) -#define ET_PCIV_L0S_LATENCY(l) __SHIFTIN((l) - 1, ET_PCIM_L0S_LATENCY) -#define ET_PCIV_L1_LATENCY(l) __SHIFTIN((l) - 1, ET_PCIM_L1_LATENCY) /* * CSR @@ -176,22 +128,22 @@ #define ET_QUEUE_ADDR_END ET_QUEUE_ADDR(ET_MEM_SIZE) #define ET_PM 0x0010 -#define ET_PM_SYSCLK_GATE __BIT(3) -#define ET_PM_TXCLK_GATE __BIT(4) -#define ET_PM_RXCLK_GATE __BIT(5) +#define ET_PM_SYSCLK_GATE 0x00000008 +#define ET_PM_TXCLK_GATE 0x00000010 +#define ET_PM_RXCLK_GATE 0x00000020 #define ET_INTR_STATUS 0x0018 #define ET_INTR_MASK 0x001c #define ET_SWRST 0x0028 -#define ET_SWRST_TXDMA __BIT(0) -#define ET_SWRST_RXDMA __BIT(1) -#define ET_SWRST_TXMAC __BIT(2) -#define ET_SWRST_RXMAC __BIT(3) -#define ET_SWRST_MAC __BIT(4) -#define ET_SWRST_MAC_STAT __BIT(5) -#define ET_SWRST_MMC __BIT(6) -#define ET_SWRST_SELFCLR_DISABLE __BIT(31) +#define ET_SWRST_TXDMA 0x00000001 +#define ET_SWRST_RXDMA 0x00000002 +#define ET_SWRST_TXMAC 0x00000004 +#define ET_SWRST_RXMAC 0x00000008 +#define ET_SWRST_MAC 0x00000010 +#define ET_SWRST_MAC_STAT 0x00000020 +#define ET_SWRST_MMC 0x00000040 +#define ET_SWRST_SELFCLR_DISABLE 0x80000000 #define ET_MSI_CFG 0x0030 @@ -200,9 +152,9 @@ #define ET_TIMER 0x0038 #define ET_TXDMA_CTRL 0x1000 -#define ET_TXDMA_CTRL_HALT __BIT(0) -#define ET_TXDMA_CTRL_CACHE_THR __BITS(7, 4) -#define ET_TXDMA_CTRL_SINGLE_EPKT __BIT(8) /* ??? */ +#define ET_TXDMA_CTRL_HALT 0x00000001 +#define ET_TXDMA_CTRL_CACHE_THR_MASK 0x000000F0 +#define ET_TXDMA_CTRL_SINGLE_EPKT 0x00000100 /* ??? */ #define ET_TX_RING_HI 0x1004 #define ET_TX_RING_LO 0x1008 @@ -212,28 +164,28 @@ #define ET_TX_STATUS_LO 0x1020 #define ET_TX_READY_POS 0x1024 -#define ET_TX_READY_POS_INDEX __BITS(9, 0) -#define ET_TX_READY_POS_WRAP __BIT(10) +#define ET_TX_READY_POS_INDEX_MASK 0x000003FF +#define ET_TX_READY_POS_WRAP 0x00000400 #define ET_TX_DONE_POS 0x1060 -#define ET_TX_DONE_POS_INDEX __BITS(9, 0) -#define ET_TX_DONE_POS_WRAP __BIT(10) +#define ET_TX_DONE_POS_INDEX_MASK 0x0000003FF +#define ET_TX_DONE_POS_WRAP 0x000000400 #define ET_RXDMA_CTRL 0x2000 -#define ET_RXDMA_CTRL_HALT __BIT(0) -#define ET_RXDMA_CTRL_RING0_SIZE __BITS(9, 8) -#define ET_RXDMA_CTRL_RING0_128 0 /* 127 */ -#define ET_RXDMA_CTRL_RING0_256 1 /* 255 */ -#define ET_RXDMA_CTRL_RING0_512 2 /* 511 */ -#define ET_RXDMA_CTRL_RING0_1024 3 /* 1023 */ -#define ET_RXDMA_CTRL_RING0_ENABLE __BIT(10) -#define ET_RXDMA_CTRL_RING1_SIZE __BITS(12, 11) -#define ET_RXDMA_CTRL_RING1_2048 0 /* 2047 */ -#define ET_RXDMA_CTRL_RING1_4096 1 /* 4095 */ -#define ET_RXDMA_CTRL_RING1_8192 2 /* 8191 */ -#define ET_RXDMA_CTRL_RING1_16384 3 /* 16383 (9022?) */ -#define ET_RXDMA_CTRL_RING1_ENABLE __BIT(13) -#define ET_RXDMA_CTRL_HALTED __BIT(17) +#define ET_RXDMA_CTRL_HALT 0x00000001 +#define ET_RXDMA_CTRL_RING0_SIZE_MASK 0x00000300 +#define ET_RXDMA_CTRL_RING0_128 0x00000000 /* 127 */ +#define ET_RXDMA_CTRL_RING0_256 0x00000100 /* 255 */ +#define ET_RXDMA_CTRL_RING0_512 0x00000200 /* 511 */ +#define ET_RXDMA_CTRL_RING0_1024 0x00000300 /* 1023 */ +#define ET_RXDMA_CTRL_RING0_ENABLE 0x00000400 +#define ET_RXDMA_CTRL_RING1_SIZE_MASK 0x00001800 +#define ET_RXDMA_CTRL_RING1_2048 0x00000000 /* 2047 */ +#define ET_RXDMA_CTRL_RING1_4096 0x00000800 /* 4095 */ +#define ET_RXDMA_CTRL_RING1_8192 0x00001000 /* 8191 */ +#define ET_RXDMA_CTRL_RING1_16384 0x00001800 /* 16383 (9022?) */ +#define ET_RXDMA_CTRL_RING1_ENABLE 0x00002000 +#define ET_RXDMA_CTRL_HALTED 0x00020000 #define ET_RX_STATUS_LO 0x2004 #define ET_RX_STATUS_HI 0x2008 @@ -246,8 +198,8 @@ #define ET_RXSTAT_CNT 0x2028 #define ET_RXSTAT_POS 0x2030 -#define ET_RXSTAT_POS_INDEX __BITS(11, 0) -#define ET_RXSTAT_POS_WRAP __BIT(12) +#define ET_RXSTAT_POS_INDEX_MASK 0x00000FFF +#define ET_RXSTAT_POS_WRAP 0x00001000 #define ET_RXSTAT_MINCNT 0x2038 @@ -256,8 +208,8 @@ #define ET_RX_RING0_CNT 0x2044 #define ET_RX_RING0_POS 0x204c -#define ET_RX_RING0_POS_INDEX __BITS(9, 0) -#define ET_RX_RING0_POS_WRAP __BIT(10) +#define ET_RX_RING0_POS_INDEX_MASK 0x000003FF +#define ET_RX_RING0_POS_WRAP 0x00000400 #define ET_RX_RING0_MINCNT 0x2054 @@ -266,21 +218,21 @@ #define ET_RX_RING1_CNT 0x2060 #define ET_RX_RING1_POS 0x2068 -#define ET_RX_RING1_POS_INDEX __BITS(9, 0) -#define ET_RX_RING1_POS_WRAP __BIT(10) +#define ET_RX_RING1_POS_INDEX 0x000003FF +#define ET_RX_RING1_POS_WRAP 0x00000400 #define ET_RX_RING1_MINCNT 0x2070 #define ET_TXMAC_CTRL 0x3000 -#define ET_TXMAC_CTRL_ENABLE __BIT(0) -#define ET_TXMAC_CTRL_FC_DISABLE __BIT(3) +#define ET_TXMAC_CTRL_ENABLE 0x00000001 +#define ET_TXMAC_CTRL_FC_DISABLE 0x00000008 #define ET_TXMAC_FLOWCTRL 0x3010 #define ET_RXMAC_CTRL 0x4000 -#define ET_RXMAC_CTRL_ENABLE __BIT(0) -#define ET_RXMAC_CTRL_NO_PKTFILT __BIT(2) -#define ET_RXMAC_CTRL_WOL_DISABLE __BIT(3) +#define ET_RXMAC_CTRL_ENABLE 0x00000001 +#define ET_RXMAC_CTRL_NO_PKTFILT 0x00000004 +#define ET_RXMAC_CTRL_WOL_DISABLE 0x00000008 #define ET_WOL_CRC 0x4004 #define ET_WOL_SA_LO 0x4010 @@ -294,16 +246,17 @@ #define ET_MULTI_HASH 0x4074 #define ET_PKTFILT 0x4084 -#define ET_PKTFILT_BCAST __BIT(0) -#define ET_PKTFILT_MCAST __BIT(1) -#define ET_PKTFILT_UCAST __BIT(2) -#define ET_PKTFILT_FRAG __BIT(3) -#define ET_PKTFILT_MINLEN __BITS(22, 16) +#define ET_PKTFILT_BCAST 0x00000001 +#define ET_PKTFILT_MCAST 0x00000002 +#define ET_PKTFILT_UCAST 0x00000004 +#define ET_PKTFILT_FRAG 0x00000008 +#define ET_PKTFILT_MINLEN_MASK 0x007F0000 +#define ET_PKTFILT_MINLEN_SHIFT 16 #define ET_RXMAC_MC_SEGSZ 0x4088 -#define ET_RXMAC_MC_SEGSZ_ENABLE __BIT(0) -#define ET_RXMAC_MC_SEGSZ_FC __BIT(1) -#define ET_RXMAC_MC_SEGSZ_MAX __BITS(9, 2) +#define ET_RXMAC_MC_SEGSZ_ENABLE 0x00000001 +#define ET_RXMAC_MC_SEGSZ_FC 0x00000002 +#define ET_RXMAC_MC_SEGSZ_MAX_MASK 0x000003FC #define ET_RXMAC_SEGSZ(segsz) ((segsz) / ET_MEM_UNIT) #define ET_RXMAC_CUT_THRU_FRMLEN 8074 @@ -311,110 +264,121 @@ #define ET_RXMAC_SPACE_AVL 0x4094 #define ET_RXMAC_MGT 0x4098 -#define ET_RXMAC_MGT_PASS_ECRC __BIT(4) -#define ET_RXMAC_MGT_PASS_ELEN __BIT(5) -#define ET_RXMAC_MGT_PASS_ETRUNC __BIT(16) -#define ET_RXMAC_MGT_CHECK_PKT __BIT(17) +#define ET_RXMAC_MGT_PASS_ECRC 0x00000010 +#define ET_RXMAC_MGT_PASS_ELEN 0x00000020 +#define ET_RXMAC_MGT_PASS_ETRUNC 0x00010000 +#define ET_RXMAC_MGT_CHECK_PKT 0x00020000 #define ET_MAC_CFG1 0x5000 -#define ET_MAC_CFG1_TXEN __BIT(0) -#define ET_MAC_CFG1_SYNC_TXEN __BIT(1) -#define ET_MAC_CFG1_RXEN __BIT(2) -#define ET_MAC_CFG1_SYNC_RXEN __BIT(3) -#define ET_MAC_CFG1_TXFLOW __BIT(4) -#define ET_MAC_CFG1_RXFLOW __BIT(5) -#define ET_MAC_CFG1_LOOPBACK __BIT(8) -#define ET_MAC_CFG1_RST_TXFUNC __BIT(16) -#define ET_MAC_CFG1_RST_RXFUNC __BIT(17) -#define ET_MAC_CFG1_RST_TXMC __BIT(18) -#define ET_MAC_CFG1_RST_RXMC __BIT(19) -#define ET_MAC_CFG1_SIM_RST __BIT(30) -#define ET_MAC_CFG1_SOFT_RST __BIT(31) +#define ET_MAC_CFG1_TXEN 0x00000001 +#define ET_MAC_CFG1_SYNC_TXEN 0x00000002 +#define ET_MAC_CFG1_RXEN 0x00000004 +#define ET_MAC_CFG1_SYNC_RXEN 0x00000008 +#define ET_MAC_CFG1_TXFLOW 0x00000010 +#define ET_MAC_CFG1_RXFLOW 0x00000020 +#define ET_MAC_CFG1_LOOPBACK 0x00000100 +#define ET_MAC_CFG1_RST_TXFUNC 0x00010000 +#define ET_MAC_CFG1_RST_RXFUNC 0x00020000 +#define ET_MAC_CFG1_RST_TXMC 0x00040000 +#define ET_MAC_CFG1_RST_RXMC 0x00080000 +#define ET_MAC_CFG1_SIM_RST 0x40000000 +#define ET_MAC_CFG1_SOFT_RST 0x80000000 #define ET_MAC_CFG2 0x5004 -#define ET_MAC_CFG2_FDX __BIT(0) -#define ET_MAC_CFG2_CRC __BIT(1) -#define ET_MAC_CFG2_PADCRC __BIT(2) -#define ET_MAC_CFG2_LENCHK __BIT(4) -#define ET_MAC_CFG2_BIGFRM __BIT(5) -#define ET_MAC_CFG2_MODE_MII __BIT(8) -#define ET_MAC_CFG2_MODE_GMII __BIT(9) -#define ET_MAC_CFG2_PREAMBLE_LEN __BITS(15, 12) +#define ET_MAC_CFG2_FDX 0x00000001 +#define ET_MAC_CFG2_CRC 0x00000002 +#define ET_MAC_CFG2_PADCRC 0x00000004 +#define ET_MAC_CFG2_LENCHK 0x00000010 +#define ET_MAC_CFG2_BIGFRM 0x00000020 +#define ET_MAC_CFG2_MODE_MII 0x00000100 +#define ET_MAC_CFG2_MODE_GMII 0x00000200 +#define ET_MAC_CFG2_PREAMBLE_LEN_MASK 0x0000F000 +#define ET_MAC_CFG2_PREAMBLE_LEN_SHIFT 12 #define ET_IPG 0x5008 -#define ET_IPG_B2B __BITS(6, 0) -#define ET_IPG_MINIFG __BITS(15, 8) -#define ET_IPG_NONB2B_2 __BITS(22, 16) -#define ET_IPG_NONB2B_1 __BITS(30, 24) +#define ET_IPG_B2B_MASK 0x0000007F +#define ET_IPG_MINIFG_MASK 0x0000FF00 +#define ET_IPG_NONB2B_2_MASK 0x007F0000 +#define ET_IPG_NONB2B_1_MASK 0x7F000000 +#define ET_IPG_B2B_SHIFT 0 +#define ET_IPG_MINIFG_SHIFT 8 +#define ET_IPG_NONB2B_2_SHIFT 16 +#define ET_IPG_NONB2B_1_SHIFT 24 #define ET_MAC_HDX 0x500c -#define ET_MAC_HDX_COLLWIN __BITS(9, 0) -#define ET_MAC_HDX_REXMIT_MAX __BITS(15, 12) -#define ET_MAC_HDX_EXC_DEFER __BIT(16) -#define ET_MAC_HDX_NOBACKOFF __BIT(17) -#define ET_MAC_HDX_BP_NOBACKOFF __BIT(18) -#define ET_MAC_HDX_ALT_BEB __BIT(19) -#define ET_MAC_HDX_ALT_BEB_TRUNC __BITS(23, 20) +#define ET_MAC_HDX_COLLWIN_MASK 0x000003FF +#define ET_MAC_HDX_REXMIT_MAX_MASK 0x0000F000 +#define ET_MAC_HDX_EXC_DEFER 0x00010000 +#define ET_MAC_HDX_NOBACKOFF 0x00020000 +#define ET_MAC_HDX_BP_NOBACKOFF 0x00040000 +#define ET_MAC_HDX_ALT_BEB 0x00080000 +#define ET_MAC_HDX_ALT_BEB_TRUNC_MASK 0x00F00000 +#define ET_MAC_HDX_COLLWIN_SHIFT 0 +#define ET_MAC_HDX_REXMIT_MAX_SHIFT 12 +#define ET_MAC_HDX_ALT_BEB_TRUNC_SHIFT 20 #define ET_MAX_FRMLEN 0x5010 #define ET_MII_CFG 0x5020 -#define ET_MII_CFG_CLKRST __BITS(2, 0) -#define ET_MII_CFG_PREAMBLE_SUP __BIT(4) -#define ET_MII_CFG_SCAN_AUTOINC __BIT(5) -#define ET_MII_CFG_RST __BIT(31) +#define ET_MII_CFG_CLKRST 0x00000007 +#define ET_MII_CFG_PREAMBLE_SUP 0x00000010 +#define ET_MII_CFG_SCAN_AUTOINC 0x00000020 +#define ET_MII_CFG_RST 0x80000000 #define ET_MII_CMD 0x5024 -#define ET_MII_CMD_READ __BIT(0) +#define ET_MII_CMD_READ 0x00000001 #define ET_MII_ADDR 0x5028 -#define ET_MII_ADDR_REG __BITS(4, 0) -#define ET_MII_ADDR_PHY __BITS(12, 8) +#define ET_MII_ADDR_REG_MASK 0x0000001F +#define ET_MII_ADDR_PHY_MASK 0x00001F00 +#define ET_MII_ADDR_REG_SHIFT 0 +#define ET_MII_ADDR_PHY_SHIFT 8 #define ET_MII_CTRL 0x502c -#define ET_MII_CTRL_VALUE __BITS(15, 0) +#define ET_MII_CTRL_VALUE_MASK 0x0000FFFF +#define ET_MII_CTRL_VALUE_SHIFT 0 #define ET_MII_STAT 0x5030 -#define ET_MII_STAT_VALUE __BITS(15, 0) +#define ET_MII_STAT_VALUE_MASK 0x0000FFFF #define ET_MII_IND 0x5034 -#define ET_MII_IND_BUSY __BIT(0) -#define ET_MII_IND_INVALID __BIT(2) +#define ET_MII_IND_BUSY 0x00000001 +#define ET_MII_IND_INVALID 0x00000004 #define ET_MAC_CTRL 0x5038 -#define ET_MAC_CTRL_MODE_MII __BIT(24) -#define ET_MAC_CTRL_LHDX __BIT(25) -#define ET_MAC_CTRL_GHDX __BIT(26) +#define ET_MAC_CTRL_MODE_MII 0x01000000 +#define ET_MAC_CTRL_LHDX 0x02000000 +#define ET_MAC_CTRL_GHDX 0x04000000 #define ET_MAC_ADDR1 0x5040 #define ET_MAC_ADDR2 0x5044 #define ET_MMC_CTRL 0x7000 -#define ET_MMC_CTRL_ENABLE __BIT(0) -#define ET_MMC_CTRL_ARB_DISABLE __BIT(1) -#define ET_MMC_CTRL_RXMAC_DISABLE __BIT(2) -#define ET_MMC_CTRL_TXMAC_DISABLE __BIT(3) -#define ET_MMC_CTRL_TXDMA_DISABLE __BIT(4) -#define ET_MMC_CTRL_RXDMA_DISABLE __BIT(5) -#define ET_MMC_CTRL_FORCE_CE __BIT(6) +#define ET_MMC_CTRL_ENABLE 0x00000001 +#define ET_MMC_CTRL_ARB_DISABLE 0x00000002 +#define ET_MMC_CTRL_RXMAC_DISABLE 0x00000004 +#define ET_MMC_CTRL_TXMAC_DISABLE 0x00000008 +#define ET_MMC_CTRL_TXDMA_DISABLE 0x00000010 +#define ET_MMC_CTRL_RXDMA_DISABLE 0x00000020 +#define ET_MMC_CTRL_FORCE_CE 0x00000040 /* * Interrupts */ -#define ET_INTR_TXEOF __BIT(3) -#define ET_INTR_TXDMA_ERROR __BIT(4) -#define ET_INTR_RXEOF __BIT(5) -#define ET_INTR_RXRING0_LOW __BIT(6) -#define ET_INTR_RXRING1_LOW __BIT(7) -#define ET_INTR_RXSTAT_LOW __BIT(8) -#define ET_INTR_RXDMA_ERROR __BIT(9) -#define ET_INTR_TIMER __BIT(14) -#define ET_INTR_WOL __BIT(15) -#define ET_INTR_PHY __BIT(16) -#define ET_INTR_TXMAC __BIT(17) -#define ET_INTR_RXMAC __BIT(18) -#define ET_INTR_MAC_STATS __BIT(19) -#define ET_INTR_SLAVE_TO __BIT(20) +#define ET_INTR_TXEOF 0x00000008 +#define ET_INTR_TXDMA_ERROR 0x00000010 +#define ET_INTR_RXEOF 0x00000020 +#define ET_INTR_RXRING0_LOW 0x00000040 +#define ET_INTR_RXRING1_LOW 0x00000080 +#define ET_INTR_RXSTAT_LOW 0x00000100 +#define ET_INTR_RXDMA_ERROR 0x00000200 +#define ET_INTR_TIMER 0x00004000 +#define ET_INTR_WOL 0x00008000 +#define ET_INTR_PHY 0x00010000 +#define ET_INTR_TXMAC 0x00020000 +#define ET_INTR_RXMAC 0x00040000 +#define ET_INTR_MAC_STATS 0x00080000 +#define ET_INTR_SLAVE_TO 0x00100000 #define ET_INTRS (ET_INTR_TXEOF | \ ET_INTR_RXEOF | \ @@ -423,8 +387,8 @@ /* * RX ring position uses same layout */ -#define ET_RX_RING_POS_INDEX __BITS(9, 0) -#define ET_RX_RING_POS_WRAP __BIT(10) +#define ET_RX_RING_POS_INDEX_MASK 0x000003FF +#define ET_RX_RING_POS_WRAP 0x00000400 /* * PCI IDs |
