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Diffstat (limited to 'sys/dev/em/e1000_ich8lan.c')
-rw-r--r--sys/dev/em/e1000_ich8lan.c447
1 files changed, 187 insertions, 260 deletions
diff --git a/sys/dev/em/e1000_ich8lan.c b/sys/dev/em/e1000_ich8lan.c
index 29b80e9..149d66b 100644
--- a/sys/dev/em/e1000_ich8lan.c
+++ b/sys/dev/em/e1000_ich8lan.c
@@ -1,4 +1,4 @@
-/*******************************************************************************
+/******************************************************************************
Copyright (c) 2001-2008, Intel Corporation
All rights reserved.
@@ -29,9 +29,8 @@
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
-*******************************************************************************/
-/* $FreeBSD$ */
-
+******************************************************************************/
+/*$FreeBSD$*/
/* e1000_ich8lan
* e1000_ich9lan
@@ -40,60 +39,58 @@
#include "e1000_api.h"
#include "e1000_ich8lan.h"
-STATIC s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw);
-STATIC s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw);
-STATIC s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw);
-STATIC s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw);
-STATIC void e1000_release_swflag_ich8lan(struct e1000_hw *hw);
-STATIC bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
-STATIC s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw);
-STATIC s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw);
-STATIC s32 e1000_phy_force_speed_duplex_ich8lan(struct e1000_hw *hw);
-STATIC s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw);
-STATIC s32 e1000_get_phy_info_ich8lan(struct e1000_hw *hw);
-STATIC s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw,
+static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw);
+static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw);
+static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw);
+static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw);
+static void e1000_release_swflag_ich8lan(struct e1000_hw *hw);
+static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
+static s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw);
+static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw);
+static s32 e1000_phy_force_speed_duplex_ich8lan(struct e1000_hw *hw);
+static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw);
+static s32 e1000_get_phy_info_ich8lan(struct e1000_hw *hw);
+static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw,
bool active);
-STATIC s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw,
+static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw,
bool active);
-STATIC s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
+static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
u16 words, u16 *data);
-STATIC s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
+static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
u16 words, u16 *data);
-STATIC s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw);
-STATIC s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw);
-STATIC s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw,
+static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw);
+static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw);
+static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw,
u16 *data);
-STATIC s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw);
-STATIC s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw);
-STATIC s32 e1000_init_hw_ich8lan(struct e1000_hw *hw);
-STATIC s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
-STATIC s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
-STATIC s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw,
+static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw);
+static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw);
+static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw);
+static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
+static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
+static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw,
u16 *speed, u16 *duplex);
-STATIC s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
-STATIC s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
-STATIC s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
-STATIC void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
-STATIC s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
+static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
+static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
+static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
+static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
+static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout);
static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw);
static s32 e1000_get_phy_info_ife_ich8lan(struct e1000_hw *hw);
static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
-STATIC s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw,
- u32 offset, u8* data);
static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
u8 size, u16* data);
-STATIC s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw,
+static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw,
u32 offset, u16 *data);
static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
u32 offset, u8 byte);
-STATIC s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw,
+static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw,
u32 offset, u8 data);
static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
u8 size, u16 data);
-STATIC s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
-STATIC void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
+static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
+static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
/* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
/* Offset 04h HSFSTS */
@@ -152,33 +149,32 @@ struct e1000_dev_spec_ich8lan {
*
* Initialize family-specific PHY parameters and function pointers.
**/
-STATIC s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
+static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
{
struct e1000_phy_info *phy = &hw->phy;
- struct e1000_functions *func = &hw->func;
s32 ret_val = E1000_SUCCESS;
u16 i = 0;
DEBUGFUNC("e1000_init_phy_params_ich8lan");
- phy->addr = 1;
- phy->reset_delay_us = 100;
-
- func->acquire_phy = e1000_acquire_swflag_ich8lan;
- func->check_polarity = e1000_check_polarity_ife_ich8lan;
- func->check_reset_block = e1000_check_reset_block_ich8lan;
- func->force_speed_duplex = e1000_phy_force_speed_duplex_ich8lan;
- func->get_cable_length = e1000_get_cable_length_igp_2;
- func->get_cfg_done = e1000_get_cfg_done_ich8lan;
- func->get_phy_info = e1000_get_phy_info_ich8lan;
- func->read_phy_reg = e1000_read_phy_reg_igp;
- func->release_phy = e1000_release_swflag_ich8lan;
- func->reset_phy = e1000_phy_hw_reset_ich8lan;
- func->set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan;
- func->set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan;
- func->write_phy_reg = e1000_write_phy_reg_igp;
- func->power_up_phy = e1000_power_up_phy_copper;
- func->power_down_phy = e1000_power_down_phy_copper_ich8lan;
+ phy->addr = 1;
+ phy->reset_delay_us = 100;
+
+ phy->ops.acquire = e1000_acquire_swflag_ich8lan;
+ phy->ops.check_polarity = e1000_check_polarity_ife_ich8lan;
+ phy->ops.check_reset_block = e1000_check_reset_block_ich8lan;
+ phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ich8lan;
+ phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
+ phy->ops.get_cfg_done = e1000_get_cfg_done_ich8lan;
+ phy->ops.get_info = e1000_get_phy_info_ich8lan;
+ phy->ops.read_reg = e1000_read_phy_reg_igp;
+ phy->ops.release = e1000_release_swflag_ich8lan;
+ phy->ops.reset = e1000_phy_hw_reset_ich8lan;
+ phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan;
+ phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan;
+ phy->ops.write_reg = e1000_write_phy_reg_igp;
+ phy->ops.power_up = e1000_power_up_phy_copper;
+ phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
/*
* We may need to do this twice - once for IGP and if that fails,
@@ -186,8 +182,8 @@ STATIC s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
*/
ret_val = e1000_determine_phy_address(hw);
if (ret_val) {
- func->write_phy_reg = e1000_write_phy_reg_bm;
- func->read_phy_reg = e1000_read_phy_reg_bm;
+ phy->ops.write_reg = e1000_write_phy_reg_bm;
+ phy->ops.read_reg = e1000_read_phy_reg_bm;
ret_val = e1000_determine_phy_address(hw);
if (ret_val) {
DEBUGOUT("Cannot determine PHY address. Erroring out\n");
@@ -219,9 +215,9 @@ STATIC s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
case BME1000_E_PHY_ID:
phy->type = e1000_phy_bm;
phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
- func->read_phy_reg = e1000_read_phy_reg_bm;
- func->write_phy_reg = e1000_write_phy_reg_bm;
- func->commit_phy = e1000_phy_sw_reset_generic;
+ phy->ops.read_reg = e1000_read_phy_reg_bm;
+ phy->ops.write_reg = e1000_write_phy_reg_bm;
+ phy->ops.commit = e1000_phy_sw_reset_generic;
break;
default:
ret_val = -E1000_ERR_PHY;
@@ -239,10 +235,9 @@ out:
* Initialize family-specific NVM parameters and function
* pointers.
**/
-STATIC s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
+static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
{
struct e1000_nvm_info *nvm = &hw->nvm;
- struct e1000_functions *func = &hw->func;
struct e1000_dev_spec_ich8lan *dev_spec;
u32 gfpreg, sector_base_addr, sector_end_addr;
s32 ret_val = E1000_SUCCESS;
@@ -299,13 +294,13 @@ STATIC s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
}
/* Function Pointers */
- func->acquire_nvm = e1000_acquire_swflag_ich8lan;
- func->read_nvm = e1000_read_nvm_ich8lan;
- func->release_nvm = e1000_release_swflag_ich8lan;
- func->update_nvm = e1000_update_nvm_checksum_ich8lan;
- func->valid_led_default = e1000_valid_led_default_ich8lan;
- func->validate_nvm = e1000_validate_nvm_checksum_ich8lan;
- func->write_nvm = e1000_write_nvm_ich8lan;
+ nvm->ops.acquire = e1000_acquire_swflag_ich8lan;
+ nvm->ops.read = e1000_read_nvm_ich8lan;
+ nvm->ops.release = e1000_release_swflag_ich8lan;
+ nvm->ops.update = e1000_update_nvm_checksum_ich8lan;
+ nvm->ops.valid_led_default = e1000_valid_led_default_ich8lan;
+ nvm->ops.validate = e1000_validate_nvm_checksum_ich8lan;
+ nvm->ops.write = e1000_write_nvm_ich8lan;
out:
return ret_val;
@@ -318,10 +313,9 @@ out:
* Initialize family-specific MAC parameters and function
* pointers.
**/
-STATIC s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
+static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
{
struct e1000_mac_info *mac = &hw->mac;
- struct e1000_functions *func = &hw->func;
s32 ret_val = E1000_SUCCESS;
DEBUGFUNC("e1000_init_mac_params_ich8lan");
@@ -343,38 +337,38 @@ STATIC s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
/* Function pointers */
/* bus type/speed/width */
- func->get_bus_info = e1000_get_bus_info_ich8lan;
+ mac->ops.get_bus_info = e1000_get_bus_info_ich8lan;
/* reset */
- func->reset_hw = e1000_reset_hw_ich8lan;
+ mac->ops.reset_hw = e1000_reset_hw_ich8lan;
/* hw initialization */
- func->init_hw = e1000_init_hw_ich8lan;
+ mac->ops.init_hw = e1000_init_hw_ich8lan;
/* link setup */
- func->setup_link = e1000_setup_link_ich8lan;
+ mac->ops.setup_link = e1000_setup_link_ich8lan;
/* physical interface setup */
- func->setup_physical_interface = e1000_setup_copper_link_ich8lan;
+ mac->ops.setup_physical_interface = e1000_setup_copper_link_ich8lan;
/* check for link */
- func->check_for_link = e1000_check_for_copper_link_generic;
+ mac->ops.check_for_link = e1000_check_for_copper_link_generic;
/* check management mode */
- func->check_mng_mode = e1000_check_mng_mode_ich8lan;
+ mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
/* link info */
- func->get_link_up_info = e1000_get_link_up_info_ich8lan;
+ mac->ops.get_link_up_info = e1000_get_link_up_info_ich8lan;
/* multicast address update */
- func->update_mc_addr_list = e1000_update_mc_addr_list_generic;
+ mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
/* setting MTA */
- func->mta_set = e1000_mta_set_generic;
+ mac->ops.mta_set = e1000_mta_set_generic;
/* blink LED */
- func->blink_led = e1000_blink_led_generic;
+ mac->ops.blink_led = e1000_blink_led_generic;
/* setup LED */
- func->setup_led = e1000_setup_led_generic;
+ mac->ops.setup_led = e1000_setup_led_generic;
/* cleanup LED */
- func->cleanup_led = e1000_cleanup_led_ich8lan;
+ mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
/* turn on/off LED */
- func->led_on = e1000_led_on_ich8lan;
- func->led_off = e1000_led_off_ich8lan;
+ mac->ops.led_on = e1000_led_on_ich8lan;
+ mac->ops.led_off = e1000_led_off_ich8lan;
/* remove device */
- func->remove_device = e1000_remove_device_generic;
+ mac->ops.remove_device = e1000_remove_device_generic;
/* clear hardware counters */
- func->clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan;
+ mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan;
hw->dev_spec_size = sizeof(struct e1000_dev_spec_ich8lan);
@@ -402,9 +396,9 @@ void e1000_init_function_pointers_ich8lan(struct e1000_hw *hw)
{
DEBUGFUNC("e1000_init_function_pointers_ich8lan");
- hw->func.init_mac_params = e1000_init_mac_params_ich8lan;
- hw->func.init_nvm_params = e1000_init_nvm_params_ich8lan;
- hw->func.init_phy_params = e1000_init_phy_params_ich8lan;
+ hw->mac.ops.init_params = e1000_init_mac_params_ich8lan;
+ hw->nvm.ops.init_params = e1000_init_nvm_params_ich8lan;
+ hw->phy.ops.init_params = e1000_init_phy_params_ich8lan;
}
/**
@@ -415,7 +409,7 @@ void e1000_init_function_pointers_ich8lan(struct e1000_hw *hw)
* operations. This is a function pointer entry point only called by
* read/write routines for the PHY and NVM parts.
**/
-STATIC s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
+static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
{
u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
s32 ret_val = E1000_SUCCESS;
@@ -454,7 +448,7 @@ out:
* This is a function pointer entry point only called by read/write
* routines for the PHY and NVM parts.
**/
-STATIC void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
+static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
{
u32 extcnf_ctrl;
@@ -475,7 +469,7 @@ STATIC void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
* This is a function pointer entry point only called by read/write
* routines for the PHY and NVM parts.
**/
-STATIC bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
+static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
{
u32 fwsm;
@@ -495,7 +489,7 @@ STATIC bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
* This is a function pointer entry point only called by
* reset routines.
**/
-STATIC s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
+static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
{
u32 fwsm;
@@ -515,7 +509,7 @@ STATIC s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
* This is a function pointer entry point only called by
* PHY setup routines.
**/
-STATIC s32 e1000_phy_force_speed_duplex_ich8lan(struct e1000_hw *hw)
+static s32 e1000_phy_force_speed_duplex_ich8lan(struct e1000_hw *hw)
{
struct e1000_phy_info *phy = &hw->phy;
s32 ret_val;
@@ -529,25 +523,25 @@ STATIC s32 e1000_phy_force_speed_duplex_ich8lan(struct e1000_hw *hw)
goto out;
}
- ret_val = e1000_read_phy_reg(hw, PHY_CONTROL, &data);
+ ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &data);
if (ret_val)
goto out;
e1000_phy_force_speed_duplex_setup(hw, &data);
- ret_val = e1000_write_phy_reg(hw, PHY_CONTROL, data);
+ ret_val = phy->ops.write_reg(hw, PHY_CONTROL, data);
if (ret_val)
goto out;
/* Disable MDI-X support for 10/100 */
- ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
+ ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
if (ret_val)
goto out;
data &= ~IFE_PMC_AUTO_MDIX;
data &= ~IFE_PMC_FORCE_MDIX;
- ret_val = e1000_write_phy_reg(hw, IFE_PHY_MDIX_CONTROL, data);
+ ret_val = phy->ops.write_reg(hw, IFE_PHY_MDIX_CONTROL, data);
if (ret_val)
goto out;
@@ -590,9 +584,10 @@ out:
* This is a function pointer entry point called by drivers
* or other shared routines.
**/
-STATIC s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
+static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
{
struct e1000_phy_info *phy = &hw->phy;
+ struct e1000_nvm_info *nvm = &hw->nvm;
u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
s32 ret_val;
u16 loop = E1000_ICH8_LAN_INIT_TIMEOUT;
@@ -670,14 +665,14 @@ STATIC s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
word_addr = (u16)(cnf_base_addr << 1);
for (i = 0; i < cnf_size; i++) {
- ret_val = e1000_read_nvm(hw,
+ ret_val = nvm->ops.read(hw,
(word_addr + i * 2),
1,
&reg_data);
if (ret_val)
goto out;
- ret_val = e1000_read_nvm(hw,
+ ret_val = nvm->ops.read(hw,
(word_addr + i * 2 + 1),
1,
&reg_addr);
@@ -692,7 +687,7 @@ STATIC s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
reg_addr |= phy_page;
- ret_val = e1000_write_phy_reg(hw,
+ ret_val = phy->ops.write_reg(hw,
(u32)reg_addr,
reg_data);
if (ret_val)
@@ -712,7 +707,7 @@ out:
* This is a function pointer entry point called by drivers
* or other shared routines.
**/
-STATIC s32 e1000_get_phy_info_ich8lan(struct e1000_hw *hw)
+static s32 e1000_get_phy_info_ich8lan(struct e1000_hw *hw)
{
s32 ret_val = -E1000_ERR_PHY_TYPE;
@@ -760,7 +755,7 @@ static s32 e1000_get_phy_info_ife_ich8lan(struct e1000_hw *hw)
goto out;
}
- ret_val = e1000_read_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, &data);
+ ret_val = phy->ops.read_reg(hw, IFE_PHY_SPECIAL_CONTROL, &data);
if (ret_val)
goto out;
phy->polarity_correction = (data & IFE_PSC_AUTO_POLARITY_DISABLE)
@@ -777,7 +772,7 @@ static s32 e1000_get_phy_info_ife_ich8lan(struct e1000_hw *hw)
: e1000_rev_polarity_normal;
}
- ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
+ ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
if (ret_val)
goto out;
@@ -800,7 +795,7 @@ out:
* This function is only called by other family-specific
* routines.
**/
-STATIC s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw)
+static s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw)
{
struct e1000_phy_info *phy = &hw->phy;
s32 ret_val;
@@ -820,7 +815,7 @@ STATIC s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw)
mask = IFE_PSC_FORCE_POLARITY;
}
- ret_val = e1000_read_phy_reg(hw, offset, &phy_data);
+ ret_val = phy->ops.read_reg(hw, offset, &phy_data);
if (!ret_val)
phy->cable_polarity = (phy_data & mask)
@@ -843,7 +838,7 @@ STATIC s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw)
* This is a function pointer entry point only called by
* PHY setup routines.
**/
-STATIC s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw,
+static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw,
bool active)
{
struct e1000_phy_info *phy = &hw->phy;
@@ -871,11 +866,11 @@ STATIC s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw,
e1000_gig_downshift_workaround_ich8lan(hw);
/* When LPLU is enabled, we should disable SmartSpeed */
- ret_val = e1000_read_phy_reg(hw,
+ ret_val = phy->ops.read_reg(hw,
IGP01E1000_PHY_PORT_CONFIG,
&data);
data &= ~IGP01E1000_PSCFR_SMART_SPEED;
- ret_val = e1000_write_phy_reg(hw,
+ ret_val = phy->ops.write_reg(hw,
IGP01E1000_PHY_PORT_CONFIG,
data);
if (ret_val)
@@ -891,27 +886,27 @@ STATIC s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw,
* SmartSpeed, so performance is maintained.
*/
if (phy->smart_speed == e1000_smart_speed_on) {
- ret_val = e1000_read_phy_reg(hw,
+ ret_val = phy->ops.read_reg(hw,
IGP01E1000_PHY_PORT_CONFIG,
&data);
if (ret_val)
goto out;
data |= IGP01E1000_PSCFR_SMART_SPEED;
- ret_val = e1000_write_phy_reg(hw,
+ ret_val = phy->ops.write_reg(hw,
IGP01E1000_PHY_PORT_CONFIG,
data);
if (ret_val)
goto out;
} else if (phy->smart_speed == e1000_smart_speed_off) {
- ret_val = e1000_read_phy_reg(hw,
+ ret_val = phy->ops.read_reg(hw,
IGP01E1000_PHY_PORT_CONFIG,
&data);
if (ret_val)
goto out;
data &= ~IGP01E1000_PSCFR_SMART_SPEED;
- ret_val = e1000_write_phy_reg(hw,
+ ret_val = phy->ops.write_reg(hw,
IGP01E1000_PHY_PORT_CONFIG,
data);
if (ret_val)
@@ -936,7 +931,7 @@ out:
* This is a function pointer entry point only called by
* PHY setup routines.
**/
-STATIC s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw,
+static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw,
bool active)
{
struct e1000_phy_info *phy = &hw->phy;
@@ -958,27 +953,27 @@ STATIC s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw,
* SmartSpeed, so performance is maintained.
*/
if (phy->smart_speed == e1000_smart_speed_on) {
- ret_val = e1000_read_phy_reg(hw,
+ ret_val = phy->ops.read_reg(hw,
IGP01E1000_PHY_PORT_CONFIG,
&data);
if (ret_val)
goto out;
data |= IGP01E1000_PSCFR_SMART_SPEED;
- ret_val = e1000_write_phy_reg(hw,
+ ret_val = phy->ops.write_reg(hw,
IGP01E1000_PHY_PORT_CONFIG,
data);
if (ret_val)
goto out;
} else if (phy->smart_speed == e1000_smart_speed_off) {
- ret_val = e1000_read_phy_reg(hw,
+ ret_val = phy->ops.read_reg(hw,
IGP01E1000_PHY_PORT_CONFIG,
&data);
if (ret_val)
goto out;
data &= ~IGP01E1000_PSCFR_SMART_SPEED;
- ret_val = e1000_write_phy_reg(hw,
+ ret_val = phy->ops.write_reg(hw,
IGP01E1000_PHY_PORT_CONFIG,
data);
if (ret_val)
@@ -999,14 +994,14 @@ STATIC s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw,
e1000_gig_downshift_workaround_ich8lan(hw);
/* When LPLU is enabled, we should disable SmartSpeed */
- ret_val = e1000_read_phy_reg(hw,
+ ret_val = phy->ops.read_reg(hw,
IGP01E1000_PHY_PORT_CONFIG,
&data);
if (ret_val)
goto out;
data &= ~IGP01E1000_PSCFR_SMART_SPEED;
- ret_val = e1000_write_phy_reg(hw,
+ ret_val = phy->ops.write_reg(hw,
IGP01E1000_PHY_PORT_CONFIG,
data);
}
@@ -1022,49 +1017,13 @@ out:
*
* Reads signature byte from the NVM using the flash access registers.
**/
-STATIC s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
+static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
{
s32 ret_val = E1000_SUCCESS;
- struct e1000_nvm_info *nvm = &hw->nvm;
- /* flash bank size is in words */
- u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
- u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
- u8 bank_high_byte = 0;
-
- if (hw->mac.type != e1000_ich10lan) {
- if (E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_SEC1VAL)
- *bank = 1;
- else
- *bank = 0;
- } else if (hw->dev_spec != NULL) {
- /*
- * Make sure the signature for bank 0 is valid,
- * if not check for bank1
- */
- e1000_read_flash_byte_ich8lan(hw, act_offset, &bank_high_byte);
- if ((bank_high_byte & 0xC0) == 0x80) {
- *bank = 0;
- } else {
- /*
- * find if segment 1 is valid by verifying
- * bit 15:14 = 10b in word 0x13
- */
- e1000_read_flash_byte_ich8lan(hw,
- act_offset + bank1_offset,
- &bank_high_byte);
-
- /* bank1 has a valid signature equivalent to SEC1V */
- if ((bank_high_byte & 0xC0) == 0x80) {
- *bank = 1;
- } else {
- DEBUGOUT("ERROR: EEPROM not present\n");
- ret_val = -E1000_ERR_NVM;
- }
- }
- } else {
- DEBUGOUT("DEV SPEC is NULL\n");
- ret_val = -E1000_ERR_NVM;
- }
+ if (E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_SEC1VAL)
+ *bank = 1;
+ else
+ *bank = 0;
return ret_val;
}
@@ -1078,7 +1037,7 @@ STATIC s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
*
* Reads a word(s) from the NVM using the flash access registers.
**/
-STATIC s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
+static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
u16 *data)
{
struct e1000_nvm_info *nvm = &hw->nvm;
@@ -1105,7 +1064,7 @@ STATIC s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
goto out;
}
- ret_val = e1000_acquire_nvm(hw);
+ ret_val = nvm->ops.acquire(hw);
if (ret_val)
goto out;
@@ -1130,7 +1089,7 @@ STATIC s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
}
}
- e1000_release_nvm(hw);
+ nvm->ops.release(hw);
out:
return ret_val;
@@ -1260,7 +1219,7 @@ static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
* Reads the flash word at offset into data. Offset is converted
* to bytes before read.
**/
-STATIC s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
+static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
u16 *data)
{
s32 ret_val;
@@ -1282,30 +1241,6 @@ out:
}
/**
- * e1000_read_flash_byte_ich8lan - Read byte from flash
- * @hw: pointer to the HW structure
- * @offset: The offset of the byte to read.
- * @data: Pointer to a byte to store the value read.
- *
- * Reads a single byte from the NVM using the flash access registers.
- **/
-STATIC s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
- u8* data)
-{
- s32 ret_val = E1000_SUCCESS;
- u16 word = 0;
-
- ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
- if (ret_val)
- goto out;
-
- *data = (u8)word;
-
-out:
- return ret_val;
-}
-
-/**
* e1000_read_flash_data_ich8lan - Read byte or word from NVM
* @hw: pointer to the HW structure
* @offset: The offset (in bytes) of the byte or word to read.
@@ -1397,7 +1332,7 @@ out:
*
* Writes a byte or word to the NVM using the flash access registers.
**/
-STATIC s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
+static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
u16 *data)
{
struct e1000_nvm_info *nvm = &hw->nvm;
@@ -1422,7 +1357,7 @@ STATIC s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
goto out;
}
- ret_val = e1000_acquire_nvm(hw);
+ ret_val = nvm->ops.acquire(hw);
if (ret_val)
goto out;
@@ -1431,7 +1366,7 @@ STATIC s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
dev_spec->shadow_ram[offset+i].value = data[i];
}
- e1000_release_nvm(hw);
+ nvm->ops.release(hw);
out:
return ret_val;
@@ -1448,7 +1383,7 @@ out:
* After a successful commit, the shadow ram is cleared and is ready for
* future writes.
**/
-STATIC s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
+static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
{
struct e1000_nvm_info *nvm = &hw->nvm;
struct e1000_dev_spec_ich8lan *dev_spec;
@@ -1467,7 +1402,7 @@ STATIC s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
if (nvm->type != e1000_nvm_flash_sw)
goto out;
- ret_val = e1000_acquire_nvm(hw);
+ ret_val = nvm->ops.acquire(hw);
if (ret_val)
goto out;
@@ -1540,7 +1475,7 @@ STATIC s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
*/
if (ret_val) {
DEBUGOUT("Flash commit failed.\n");
- e1000_release_nvm(hw);
+ nvm->ops.release(hw);
goto out;
}
@@ -1557,7 +1492,7 @@ STATIC s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
act_offset * 2 + 1,
(u8)(data >> 8));
if (ret_val) {
- e1000_release_nvm(hw);
+ nvm->ops.release(hw);
goto out;
}
@@ -1570,7 +1505,7 @@ STATIC s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
if (ret_val) {
- e1000_release_nvm(hw);
+ nvm->ops.release(hw);
goto out;
}
@@ -1580,13 +1515,13 @@ STATIC s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
dev_spec->shadow_ram[i].value = 0xFFFF;
}
- e1000_release_nvm(hw);
+ nvm->ops.release(hw);
/*
* Reload the EEPROM, or else modifications will not appear
* until after the next adapter reset.
*/
- e1000_reload_nvm(hw);
+ nvm->ops.reload(hw);
msec_delay(10);
out:
@@ -1602,7 +1537,7 @@ out:
* not calculated, in which case we need to calculate the checksum and set
* bit 6.
**/
-STATIC s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
+static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
{
s32 ret_val = E1000_SUCCESS;
u16 data;
@@ -1615,16 +1550,16 @@ STATIC s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
* was prepared by OEM software and did not calculate the
* checksum...a likely scenario.
*/
- ret_val = e1000_read_nvm(hw, 0x19, 1, &data);
+ ret_val = hw->nvm.ops.read(hw, 0x19, 1, &data);
if (ret_val)
goto out;
if ((data & 0x40) == 0) {
data |= 0x40;
- ret_val = e1000_write_nvm(hw, 0x19, 1, &data);
+ ret_val = hw->nvm.ops.write(hw, 0x19, 1, &data);
if (ret_val)
goto out;
- ret_val = e1000_update_nvm_checksum(hw);
+ ret_val = hw->nvm.ops.update(hw);
if (ret_val)
goto out;
}
@@ -1725,7 +1660,7 @@ out:
*
* Writes a single byte to the NVM using the flash access registers.
**/
-STATIC s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
+static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
u8 data)
{
u16 word = (u16)data;
@@ -1780,7 +1715,7 @@ out:
* Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
* bank N is 4096 * N + flash_reg_addr.
**/
-STATIC s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
+static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
{
struct e1000_nvm_info *nvm = &hw->nvm;
union ich8_hws_flash_status hsfsts;
@@ -1906,13 +1841,13 @@ out:
* settings is all 0's or F's, set the LED default to a valid LED default
* setting.
**/
-STATIC s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
+static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
{
s32 ret_val;
DEBUGFUNC("e1000_valid_led_default_ich8lan");
- ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
+ ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
if (ret_val) {
DEBUGOUT("NVM Read Error\n");
goto out;
@@ -1933,7 +1868,7 @@ out:
* ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
* register, so the the bus width is hard coded.
**/
-STATIC s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
+static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
{
struct e1000_bus_info *bus = &hw->bus;
s32 ret_val;
@@ -1961,7 +1896,7 @@ STATIC s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
* Does a full reset of the hardware which includes a reset of the PHY and
* MAC.
**/
-STATIC s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
+static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
{
u32 ctrl, icr, kab;
s32 ret_val;
@@ -2001,7 +1936,7 @@ STATIC s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
ctrl = E1000_READ_REG(hw, E1000_CTRL);
- if (!e1000_check_reset_block(hw) && !hw->phy.reset_disable) {
+ if (!hw->phy.ops.check_reset_block(hw) && !hw->phy.reset_disable) {
/*
* PHY HW reset requires MAC CORE reset at the same
* time to make sure the interface between MAC and the
@@ -2046,7 +1981,7 @@ STATIC s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
* - setup transmit descriptors
* - clear statistics
**/
-STATIC s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
+static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
{
struct e1000_mac_info *mac = &hw->mac;
u32 ctrl_ext, txdctl, snoop;
@@ -2073,7 +2008,7 @@ STATIC s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
/* Setup link and flow control */
- ret_val = e1000_setup_link(hw);
+ ret_val = mac->ops.setup_link(hw);
/* Set the transmit descriptor write-back policy for both queues */
txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0));
@@ -2181,14 +2116,13 @@ out:
* should be established. Assumes the hardware has previously been reset
* and the transmitter and receiver are not enabled.
**/
-STATIC s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
+static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
{
- struct e1000_functions *func = &hw->func;
s32 ret_val = E1000_SUCCESS;
DEBUGFUNC("e1000_setup_link_ich8lan");
- if (e1000_check_reset_block(hw))
+ if (hw->phy.ops.check_reset_block(hw))
goto out;
/*
@@ -2204,7 +2138,7 @@ STATIC s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc.type);
/* Continue to configure the copper link. */
- ret_val = func->setup_physical_interface(hw);
+ ret_val = hw->mac.ops.setup_physical_interface(hw);
if (ret_val)
goto out;
@@ -2224,7 +2158,7 @@ out:
* when polling the PHY, then call the generic setup_copper_link to finish
* configuring the copper link.
**/
-STATIC s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
+static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
{
u32 ctrl;
s32 ret_val;
@@ -2264,7 +2198,8 @@ STATIC s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
}
if (hw->phy.type == e1000_phy_ife) {
- ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &reg_data);
+ ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL,
+ &reg_data);
if (ret_val)
goto out;
@@ -2282,7 +2217,8 @@ STATIC s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
reg_data |= IFE_PMC_AUTO_MDIX;
break;
}
- ret_val = e1000_write_phy_reg(hw, IFE_PHY_MDIX_CONTROL, reg_data);
+ ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL,
+ reg_data);
if (ret_val)
goto out;
}
@@ -2302,7 +2238,7 @@ out:
* information and then calls the Kumeran lock loss workaround for links at
* gigabit speeds.
**/
-STATIC s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
+static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
u16 *duplex)
{
s32 ret_val;
@@ -2372,11 +2308,11 @@ static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
for (i = 0; i < 10; i++) {
/* read once to clear */
- ret_val = e1000_read_phy_reg(hw, IGP3_KMRN_DIAG, &data);
+ ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);
if (ret_val)
goto out;
/* and again to get new status */
- ret_val = e1000_read_phy_reg(hw, IGP3_KMRN_DIAG, &data);
+ ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);
if (ret_val)
goto out;
@@ -2387,7 +2323,7 @@ static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
}
/* Issue PHY reset */
- e1000_phy_hw_reset(hw);
+ hw->phy.ops.reset(hw);
msec_delay_irq(5);
}
/* Disable GigE link negotiation */
@@ -2479,14 +2415,14 @@ void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
e1000_gig_downshift_workaround_ich8lan(hw);
/* Write VR power-down enable */
- e1000_read_phy_reg(hw, IGP3_VR_CTRL, &data);
+ hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);
data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
- e1000_write_phy_reg(hw,
+ hw->phy.ops.write_reg(hw,
IGP3_VR_CTRL,
data | IGP3_VR_CTRL_MODE_SHUTDOWN);
/* Read it back and test */
- e1000_read_phy_reg(hw, IGP3_VR_CTRL, &data);
+ hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);
data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
break;
@@ -2547,16 +2483,13 @@ out:
* 'LPLU Enabled' and 'Gig Disable' to force link speed negotiation
* to a lower speed.
*
- * Should only be called for ICH9m and ICH10 devices.
+ * Should only be called for ICH9.
**/
void e1000_disable_gig_wol_ich8lan(struct e1000_hw *hw)
{
u32 phy_ctrl;
- if ((hw->mac.type == e1000_ich10lan) ||
- ((hw->mac.type == e1000_ich9lan) &&
- ((hw->device_id == E1000_DEV_ID_ICH9_IGP_M) ||
- (hw->device_id == E1000_DEV_ID_ICH9_IGP_M_AMT)))) {
+ if (hw->mac.type == e1000_ich9lan) {
phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU |
E1000_PHY_CTRL_GBE_DISABLE;
@@ -2572,14 +2505,14 @@ void e1000_disable_gig_wol_ich8lan(struct e1000_hw *hw)
*
* Return the LED back to the default configuration.
**/
-STATIC s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
+static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
{
s32 ret_val = E1000_SUCCESS;
DEBUGFUNC("e1000_cleanup_led_ich8lan");
if (hw->phy.type == e1000_phy_ife)
- ret_val = e1000_write_phy_reg(hw,
+ ret_val = hw->phy.ops.write_reg(hw,
IFE_PHY_SPECIAL_CONTROL_LED,
0);
else
@@ -2594,14 +2527,14 @@ STATIC s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
*
* Turn on the LEDs.
**/
-STATIC s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
+static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
{
s32 ret_val = E1000_SUCCESS;
DEBUGFUNC("e1000_led_on_ich8lan");
if (hw->phy.type == e1000_phy_ife)
- ret_val = e1000_write_phy_reg(hw,
+ ret_val = hw->phy.ops.write_reg(hw,
IFE_PHY_SPECIAL_CONTROL_LED,
(IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
else
@@ -2616,14 +2549,14 @@ STATIC s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
*
* Turn off the LEDs.
**/
-STATIC s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
+static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
{
s32 ret_val = E1000_SUCCESS;
DEBUGFUNC("e1000_led_off_ich8lan");
if (hw->phy.type == e1000_phy_ife)
- ret_val = e1000_write_phy_reg(hw,
+ ret_val = hw->phy.ops.write_reg(hw,
IFE_PHY_SPECIAL_CONTROL_LED,
(IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
else
@@ -2642,25 +2575,16 @@ STATIC s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
* E1000_SUCCESS. If we were to return with error, EEPROM-less silicon
* would not be able to be reset or change link.
**/
-STATIC s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
+static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
{
s32 ret_val = E1000_SUCCESS;
- u32 bank = 0;
e1000_get_cfg_done_generic(hw);
/* If EEPROM is not marked present, init the IGP 3 PHY manually */
- if (hw->mac.type != e1000_ich10lan) {
- if (((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0) &&
- (hw->phy.type == e1000_phy_igp_3)) {
- e1000_phy_init_script_igp3(hw);
- }
- } else {
- if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
- /* Maybe we should do a basic Boazman config */
- DEBUGOUT("EEPROM not present\n");
- ret_val = -E1000_ERR_CONFIG;
- }
+ if (((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0) &&
+ (hw->phy.type == e1000_phy_igp_3)) {
+ e1000_phy_init_script_igp3(hw);
}
return ret_val;
@@ -2673,10 +2597,13 @@ STATIC s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
* In the case of a PHY power down to save power, or to turn off link during a
* driver unload, or wake on lan is not enabled, remove the link.
**/
-STATIC void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
+static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
{
+ struct e1000_phy_info *phy = &hw->phy;
+ struct e1000_mac_info *mac = &hw->mac;
+
/* If the management interface is not enabled, then power down */
- if (!(e1000_check_mng_mode(hw) || e1000_check_reset_block(hw)))
+ if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw)))
e1000_power_down_phy_copper(hw);
return;
@@ -2689,7 +2616,7 @@ STATIC void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
* Clears hardware counters specific to the silicon family and calls
* clear_hw_cntrs_generic to clear all general purpose counters.
**/
-STATIC void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
+static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
{
volatile u32 temp;
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