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-rw-r--r--sys/dev/ct/bshw_machdep.c799
-rw-r--r--sys/dev/ct/bshwvar.h96
-rw-r--r--sys/dev/ct/ct.c1309
-rw-r--r--sys/dev/ct/ct_isa.c420
-rw-r--r--sys/dev/ct/ct_machdep.h216
-rw-r--r--sys/dev/ct/ctvar.h145
6 files changed, 2985 insertions, 0 deletions
diff --git a/sys/dev/ct/bshw_machdep.c b/sys/dev/ct/bshw_machdep.c
new file mode 100644
index 0000000..9dc6fc1
--- /dev/null
+++ b/sys/dev/ct/bshw_machdep.c
@@ -0,0 +1,799 @@
+/* $NecBSD: bshw_machdep.c,v 1.8.12.6 2001/06/29 06:28:05 honda Exp $ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+/* $NetBSD$ */
+
+/*
+ * [NetBSD for NEC PC-98 series]
+ * Copyright (c) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
+ * NetBSD/pc98 porting staff. All rights reserved.
+ *
+ * Copyright (c) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
+ * Naofumi HONDA. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "opt_ddb.h"
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+#if defined(__FreeBSD__) && __FreeBSD_version > 500001
+#include <sys/bio.h>
+#endif /* __ FreeBSD__ */
+#include <sys/buf.h>
+#include <sys/queue.h>
+#include <sys/malloc.h>
+#include <sys/errno.h>
+
+#include <vm/vm.h>
+
+#ifdef __NetBSD__
+#include <sys/device.h>
+
+#include <machine/bus.h>
+#include <machine/intr.h>
+
+#include <dev/scsipi/scsi_all.h>
+#include <dev/scsipi/scsipi_all.h>
+#include <dev/scsipi/scsiconf.h>
+#include <dev/scsipi/scsi_disk.h>
+
+#include <machine/dvcfg.h>
+#include <machine/physio_proc.h>
+
+#include <i386/Cbus/dev/scsi_low.h>
+
+#include <dev/ic/wd33c93reg.h>
+#include <i386/Cbus/dev/ct/ctvar.h>
+#include <i386/Cbus/dev/ct/ct_machdep.h>
+#include <i386/Cbus/dev/ct/bshwvar.h>
+#endif /* __NetBSD__ */
+
+#ifdef __FreeBSD__
+#include <machine/bus.h>
+#include <machine/clock.h>
+#include <machine/md_var.h>
+
+#include <machine/dvcfg.h>
+#include <machine/physio_proc.h>
+
+#include <cam/scsi/scsi_low.h>
+
+#include <dev/ic/wd33c93reg.h>
+#include <dev/ct/ctvar.h>
+#include <dev/ct/ct_machdep.h>
+#include <dev/ct/bshwvar.h>
+
+#include <vm/pmap.h>
+#endif /* __FreeBSD__ */
+
+#define BSHW_IO_CONTROL_FLAGS 0
+
+u_int bshw_io_control = BSHW_IO_CONTROL_FLAGS;
+int bshw_data_read_bytes = 4096;
+int bshw_data_write_bytes = 4096;
+
+/*********************************************************
+ * OS dep part
+ *********************************************************/
+#ifdef __NetBSD__
+#define BSHW_PAGE_SIZE NBPG
+#endif /* __NetBSD__ */
+
+#ifdef __FreeBSD__
+#define BSHW_PAGE_SIZE PAGE_SIZE
+typedef unsigned long vaddr_t;
+#endif /* __FreeBSD__ */
+
+/*********************************************************
+ * GENERIC MACHDEP FUNCTIONS
+ *********************************************************/
+void
+bshw_synch_setup(ct, ti)
+ struct ct_softc *ct;
+ struct targ_info *ti;
+{
+ struct ct_bus_access_handle *chp = &ct->sc_ch;
+ struct ct_targ_info *cti = (void *) ti;
+ struct bshw_softc *bs = ct->ct_hw;
+ struct bshw *hw = bs->sc_hw;
+
+ if (hw->hw_sregaddr == 0)
+ return;
+
+ ct_cr_write_1(chp, hw->hw_sregaddr + ti->ti_id, cti->cti_syncreg);
+ if (hw->hw_flags & BSHW_DOUBLE_DMACHAN)
+ {
+ ct_cr_write_1(chp, hw->hw_sregaddr + ti->ti_id + 8,
+ cti->cti_syncreg);
+ }
+}
+
+void
+bshw_bus_reset(ct)
+ struct ct_softc *ct;
+{
+ struct scsi_low_softc *slp = &ct->sc_sclow;
+ struct ct_bus_access_handle *chp = &ct->sc_ch;
+ struct bshw_softc *bs = ct->ct_hw;
+ struct bshw *hw = bs->sc_hw;
+ bus_addr_t offs;
+ u_int8_t regv;
+ int i;
+
+ /* open hardware busmaster mode */
+ if (hw->hw_dma_init != NULL && ((*hw->hw_dma_init)(ct)) != 0)
+ {
+ printf("%s: change mode using external DMA (%x)\n",
+ slp->sl_xname, (u_int)ct_cr_read_1(chp, 0x37));
+ }
+
+ /* clear hardware synch registers */
+ offs = hw->hw_sregaddr;
+ if (offs != 0)
+ {
+ for (i = 0; i < 8; i ++, offs ++)
+ {
+ ct_cr_write_1(chp, offs, 0);
+ if ((hw->hw_flags & BSHW_DOUBLE_DMACHAN) != 0)
+ ct_cr_write_1(chp, offs + 8, 0);
+ }
+ }
+
+ /* disable interrupt & assert reset */
+ regv = ct_cr_read_1(chp, wd3s_mbank);
+ regv |= MBR_RST;
+ regv &= ~MBR_IEN;
+ ct_cr_write_1(chp, wd3s_mbank, regv);
+
+ SCSI_LOW_DELAY(500000);
+
+ /* reset signal off */
+ regv &= ~MBR_RST;
+ ct_cr_write_1(chp, wd3s_mbank, regv);
+
+ /* interrupt enable */
+ regv |= MBR_IEN;
+ ct_cr_write_1(chp, wd3s_mbank, regv);
+}
+
+/* probe */
+int
+bshw_read_settings(chp, bs)
+ struct ct_bus_access_handle *chp;
+ struct bshw_softc *bs;
+{
+ static int irq_tbl[] = { 3, 5, 6, 9, 12, 13 };
+
+ bs->sc_hostid = (ct_cr_read_1(chp, wd3s_auxc) & AUXCR_HIDM);
+ bs->sc_irq = irq_tbl[(ct_cr_read_1(chp, wd3s_auxc) >> 3) & 7];
+ bs->sc_drq = ct_cmdp_read_1(chp) & 3;
+ return 0;
+}
+
+/*********************************************************
+ * DMA PIO TRANSFER (SMIT)
+ *********************************************************/
+#define LC_SMIT_TIMEOUT 2 /* 2 sec: timeout for a fifo status ready */
+#define LC_SMIT_OFFSET 0x1000
+#define LC_FSZ DEV_BSIZE
+#define LC_SFSZ 0x0c
+#define LC_REST (LC_FSZ - LC_SFSZ)
+
+#define BSHW_LC_FSET 0x36
+#define BSHW_LC_FCTRL 0x44
+#define FCTRL_EN 0x01
+#define FCTRL_WRITE 0x02
+
+#define SF_ABORT 0x08
+#define SF_RDY 0x10
+
+static __inline void bshw_lc_smit_start(struct ct_softc *, int, u_int);
+static __inline void bshw_lc_smit_stop(struct ct_softc *);
+static int bshw_lc_smit_fstat(struct ct_softc *, int, int);
+
+static __inline void
+bshw_lc_smit_stop(ct)
+ struct ct_softc *ct;
+{
+ struct ct_bus_access_handle *chp = &ct->sc_ch;
+
+ ct_cr_write_1(chp, BSHW_LC_FCTRL, 0);
+ ct_cmdp_write_1(chp, CMDP_DMER);
+}
+
+static __inline void
+bshw_lc_smit_start(ct, count, direction)
+ struct ct_softc *ct;
+ int count;
+ u_int direction;
+{
+ struct ct_bus_access_handle *chp = &ct->sc_ch;
+ u_int8_t pval, val;
+
+ val = ct_cr_read_1(chp, BSHW_LC_FSET);
+ cthw_set_count(chp, count);
+
+ pval = FCTRL_EN;
+ if (direction == SCSI_LOW_WRITE)
+ pval |= (val & 0xe0) | FCTRL_WRITE;
+ ct_cr_write_1(chp, BSHW_LC_FCTRL, pval);
+ ct_cr_write_1(chp, wd3s_cmd, WD3S_TFR_INFO);
+}
+
+static int
+bshw_lc_smit_fstat(ct, wc, read)
+ struct ct_softc *ct;
+ int wc, read;
+{
+ struct ct_bus_access_handle *chp = &ct->sc_ch;
+ u_int8_t stat;
+
+ while (wc -- > 0)
+ {
+ chp->ch_bus_weight(chp);
+ stat = ct_cmdp_read_1(chp);
+ if (read == SCSI_LOW_READ)
+ {
+ if ((stat & SF_RDY) != 0)
+ return 0;
+ if ((stat & SF_ABORT) != 0)
+ return EIO;
+ }
+ else
+ {
+ if ((stat & SF_ABORT) != 0)
+ return EIO;
+ if ((stat & SF_RDY) != 0)
+ return 0;
+ }
+ }
+
+ printf("%s: SMIT fifo status timeout\n", ct->sc_sclow.sl_xname);
+ return EIO;
+}
+
+void
+bshw_smit_xfer_stop(ct)
+ struct ct_softc *ct;
+{
+ struct scsi_low_softc *slp = &ct->sc_sclow;
+ struct bshw_softc *bs = ct->ct_hw;
+ struct targ_info *ti;
+ struct sc_p *sp = &slp->sl_scp;
+ u_int count;
+
+ bshw_lc_smit_stop(ct);
+
+ ti = slp->sl_Tnexus;
+ if (ti == NULL)
+ return;
+
+ if (ti->ti_phase == PH_DATA)
+ {
+ count = cthw_get_count(&ct->sc_ch);
+ if (count < bs->sc_sdatalen)
+ {
+ if (sp->scp_direction == SCSI_LOW_READ &&
+ count != bs->sc_edatalen)
+ goto bad;
+
+ count = bs->sc_sdatalen - count;
+ if (count > (u_int) sp->scp_datalen)
+ goto bad;
+
+ sp->scp_data += count;
+ sp->scp_datalen -= count;
+ }
+ else if (count > bs->sc_sdatalen)
+ {
+bad:
+ printf("%s: smit_xfer_end: cnt error\n", slp->sl_xname);
+ slp->sl_error |= PDMAERR;
+ }
+ scsi_low_data_finish(slp);
+ }
+ else
+ {
+ printf("%s: smit_xfer_end: phase miss\n", slp->sl_xname);
+ slp->sl_error |= PDMAERR;
+ }
+}
+
+int
+bshw_smit_xfer_start(ct)
+ struct ct_softc *ct;
+{
+ struct scsi_low_softc *slp = &ct->sc_sclow;
+ struct ct_bus_access_handle *chp = &ct->sc_ch;
+ struct bshw_softc *bs = ct->ct_hw;
+ struct sc_p *sp = &slp->sl_scp;
+ struct targ_info *ti = slp->sl_Tnexus;
+ struct ct_targ_info *cti = (void *) ti;
+ u_int datalen, count, io_control;
+ int wc;
+ u_int8_t *data;
+
+ io_control = bs->sc_io_control | bshw_io_control;
+ if ((io_control & BSHW_SMIT_BLOCK) != 0)
+ return EINVAL;
+
+ if ((slp->sl_scp.scp_datalen % DEV_BSIZE) != 0)
+ return EINVAL;
+
+ datalen = sp->scp_datalen;
+ if (slp->sl_scp.scp_direction == SCSI_LOW_READ)
+ {
+ if ((io_control & BSHW_READ_INTERRUPT_DRIVEN) != 0 &&
+ datalen > bshw_data_read_bytes)
+ datalen = bshw_data_read_bytes;
+ }
+ else
+ {
+ if ((io_control & BSHW_WRITE_INTERRUPT_DRIVEN) != 0 &&
+ datalen > bshw_data_write_bytes)
+ datalen = bshw_data_write_bytes;
+ }
+
+ bs->sc_sdatalen = datalen;
+ data = sp->scp_data;
+ wc = LC_SMIT_TIMEOUT * 1024 * 1024;
+
+ ct_cr_write_1(chp, wd3s_ctrl, ct->sc_creg | CR_DMA);
+ bshw_lc_smit_start(ct, datalen, sp->scp_direction);
+
+ if (sp->scp_direction == SCSI_LOW_READ)
+ {
+ do
+ {
+ if (bshw_lc_smit_fstat(ct, wc, SCSI_LOW_READ))
+ break;
+
+ count = (datalen > LC_FSZ ? LC_FSZ : datalen);
+ bus_space_read_region_4(chp->ch_memt, chp->ch_memh,
+ LC_SMIT_OFFSET, (u_int32_t *) data, count >> 2);
+ data += count;
+ datalen -= count;
+ }
+ while (datalen > 0);
+
+ bs->sc_edatalen = datalen;
+ }
+ else
+ {
+ do
+ {
+ if (bshw_lc_smit_fstat(ct, wc, SCSI_LOW_WRITE))
+ break;
+ if (cti->cti_syncreg == 0)
+ {
+ /* XXX:
+ * If async transfer, reconfirm a scsi phase
+ * again. Unless C bus might hang up.
+ */
+ if (bshw_lc_smit_fstat(ct, wc, SCSI_LOW_WRITE))
+ break;
+ }
+
+ count = (datalen > LC_SFSZ ? LC_SFSZ : datalen);
+ bus_space_write_region_4(chp->ch_memt, chp->ch_memh,
+ LC_SMIT_OFFSET, (u_int32_t *) data, count >> 2);
+ data += count;
+ datalen -= count;
+
+ if (bshw_lc_smit_fstat(ct, wc, SCSI_LOW_WRITE))
+ break;
+
+ count = (datalen > LC_REST ? LC_REST : datalen);
+ bus_space_write_region_4(chp->ch_memt, chp->ch_memh,
+ LC_SMIT_OFFSET + LC_SFSZ,
+ (u_int32_t *) data, count >> 2);
+ data += count;
+ datalen -= count;
+ }
+ while (datalen > 0);
+ }
+ return 0;
+}
+
+/*********************************************************
+ * DMA TRANSFER (BS)
+ *********************************************************/
+static __inline void bshw_dma_write_1 \
+ (struct ct_bus_access_handle *, bus_addr_t, u_int8_t);
+static void bshw_dmastart(struct ct_softc *);
+static void bshw_dmadone(struct ct_softc *);
+
+int
+bshw_dma_xfer_start(ct)
+ struct ct_softc *ct;
+{
+ struct scsi_low_softc *slp = &ct->sc_sclow;
+ struct sc_p *sp = &slp->sl_scp;
+ struct ct_bus_access_handle *chp = &ct->sc_ch;
+ struct bshw_softc *bs = ct->ct_hw;
+ vaddr_t va, endva, phys, nphys;
+ u_int io_control;
+
+ io_control = bs->sc_io_control | bshw_io_control;
+ if ((io_control & BSHW_DMA_BLOCK) != 0 && sp->scp_datalen < 256)
+ return EINVAL;
+
+ ct_cr_write_1(chp, wd3s_ctrl, ct->sc_creg | CR_DMA);
+ phys = vtophys((vaddr_t) sp->scp_data);
+ if (phys >= bs->sc_minphys)
+ {
+ /* setup segaddr */
+ bs->sc_segaddr = bs->sc_bounce_phys;
+ /* setup seglen */
+ bs->sc_seglen = sp->scp_datalen;
+ if (bs->sc_seglen > bs->sc_bounce_size)
+ bs->sc_seglen = bs->sc_bounce_size;
+ /* setup bufp */
+ bs->sc_bufp = bs->sc_bounce_addr;
+ if (sp->scp_direction == SCSI_LOW_WRITE)
+ bcopy(sp->scp_data, bs->sc_bufp, bs->sc_seglen);
+ }
+ else
+ {
+ /* setup segaddr */
+ bs->sc_segaddr = (u_int8_t *) phys;
+ /* setup seglen */
+ endva = (vaddr_t) round_page((vaddr_t) sp->scp_data + sp->scp_datalen);
+ for (va = (vaddr_t) sp->scp_data; ; phys = nphys)
+ {
+ if ((va += BSHW_PAGE_SIZE) >= endva)
+ {
+ bs->sc_seglen = sp->scp_datalen;
+ break;
+ }
+
+ nphys = vtophys(va);
+ if (phys + BSHW_PAGE_SIZE != nphys || nphys >= bs->sc_minphys)
+ {
+ bs->sc_seglen =
+ (u_int8_t *) trunc_page(va) - sp->scp_data;
+ break;
+ }
+ }
+ /* setup bufp */
+ bs->sc_bufp = NULL;
+ }
+
+ bshw_dmastart(ct);
+ cthw_set_count(chp, bs->sc_seglen);
+ ct_cr_write_1(chp, wd3s_cmd, WD3S_TFR_INFO);
+ return 0;
+}
+
+void
+bshw_dma_xfer_stop(ct)
+ struct ct_softc *ct;
+{
+ struct scsi_low_softc *slp = &ct->sc_sclow;
+ struct sc_p *sp = &slp->sl_scp;
+ struct bshw_softc *bs = ct->ct_hw;
+ struct targ_info *ti;
+ u_int count, transbytes;
+
+ bshw_dmadone(ct);
+
+ ti = slp->sl_Tnexus;
+ if (ti == NULL)
+ return;
+
+ if (ti->ti_phase == PH_DATA)
+ {
+ count = cthw_get_count(&ct->sc_ch);
+ if (count < (u_int) bs->sc_seglen)
+ {
+ transbytes = bs->sc_seglen - count;
+ if (bs->sc_bufp != NULL &&
+ sp->scp_direction == SCSI_LOW_READ)
+ bcopy(bs->sc_bufp, sp->scp_data, transbytes);
+
+ sp->scp_data += transbytes;
+ sp->scp_datalen -= transbytes;
+ }
+ else if (count > (u_int) bs->sc_seglen)
+ {
+ printf("%s: port data %x != seglen %x\n",
+ slp->sl_xname, count, bs->sc_seglen);
+ slp->sl_error |= PDMAERR;
+ }
+
+ scsi_low_data_finish(slp);
+ }
+ else
+ {
+ printf("%s: extra DMA interrupt\n", slp->sl_xname);
+ slp->sl_error |= PDMAERR;
+ }
+
+ bs->sc_bufp = NULL;
+}
+
+/* common dma settings */
+#undef DMA1_SMSK
+#define DMA1_SMSK (0x15)
+#undef DMA1_MODE
+#define DMA1_MODE (0x17)
+#undef DMA1_FFC
+#define DMA1_FFC (0x19)
+#undef DMA1_CHN
+#define DMA1_CHN(c) (0x01 + ((c) << 2))
+
+#define DMA37SM_SET 0x04
+#define DMA37MD_WRITE 0x04
+#define DMA37MD_READ 0x08
+#define DMA37MD_SINGLE 0x40
+
+static bus_addr_t dmapageport[4] = { 0x27, 0x21, 0x23, 0x25 };
+
+static __inline void
+bshw_dma_write_1(chp, port, val)
+ struct ct_bus_access_handle *chp;
+ bus_addr_t port;
+ u_int8_t val;
+{
+
+ CT_BUS_WEIGHT(chp);
+ outb(port, val);
+}
+
+static void
+bshw_dmastart(ct)
+ struct ct_softc *ct;
+{
+ struct scsi_low_softc *slp = &ct->sc_sclow;
+ struct bshw_softc *bs = ct->ct_hw;
+ struct ct_bus_access_handle *chp = &ct->sc_ch;
+ int chan = bs->sc_drq;
+ bus_addr_t waport;
+ u_int8_t regv, *phys = bs->sc_segaddr;
+ u_int nbytes = bs->sc_seglen;
+
+ /* flush cpu cache */
+ (*bs->sc_dmasync_before) (ct);
+
+ /*
+ * Program one of DMA channels 0..3. These are
+ * byte mode channels.
+ */
+ /* set dma channel mode, and reset address ff */
+
+ if (slp->sl_scp.scp_direction == SCSI_LOW_READ)
+ regv = DMA37MD_WRITE | DMA37MD_SINGLE | chan;
+ else
+ regv = DMA37MD_READ | DMA37MD_SINGLE | chan;
+
+ bshw_dma_write_1(chp, DMA1_MODE, regv);
+ bshw_dma_write_1(chp, DMA1_FFC, 0);
+
+ /* send start address */
+ waport = DMA1_CHN(chan);
+ bshw_dma_write_1(chp, waport, (u_int) phys);
+ bshw_dma_write_1(chp, waport, ((u_int) phys) >> 8);
+ bshw_dma_write_1(chp, dmapageport[chan], ((u_int) phys) >> 16);
+
+ /* send count */
+ bshw_dma_write_1(chp, waport + 2, --nbytes);
+ bshw_dma_write_1(chp, waport + 2, nbytes >> 8);
+
+ /* vendor unique hook */
+ if (bs->sc_hw->hw_dma_start)
+ (*bs->sc_hw->hw_dma_start)(ct);
+
+ bshw_dma_write_1(chp, DMA1_SMSK, chan);
+ ct_cmdp_write_1(chp, CMDP_DMES);
+}
+
+static void
+bshw_dmadone(ct)
+ struct ct_softc *ct;
+{
+ struct bshw_softc *bs = ct->ct_hw;
+ struct ct_bus_access_handle *chp = &ct->sc_ch;
+
+ bshw_dma_write_1(chp, DMA1_SMSK, (bs->sc_drq | DMA37SM_SET));
+ ct_cmdp_write_1(chp, CMDP_DMER);
+
+ /* vendor unique hook */
+ if (bs->sc_hw->hw_dma_stop)
+ (*bs->sc_hw->hw_dma_stop) (ct);
+
+ /* flush cpu cache */
+ (*bs->sc_dmasync_after) (ct);
+}
+
+/**********************************************
+ * VENDOR UNIQUE DMA FUNCS
+ **********************************************/
+static int bshw_dma_init_sc98(struct ct_softc *);
+static void bshw_dma_start_sc98(struct ct_softc *);
+static void bshw_dma_stop_sc98(struct ct_softc *);
+static int bshw_dma_init_texa(struct ct_softc *);
+static void bshw_dma_start_elecom(struct ct_softc *);
+static void bshw_dma_stop_elecom(struct ct_softc *);
+
+static int
+bshw_dma_init_texa(ct)
+ struct ct_softc *ct;
+{
+ struct ct_bus_access_handle *chp = &ct->sc_ch;
+ u_int8_t regval;
+
+ if ((regval = ct_cr_read_1(chp, 0x37)) & 0x08)
+ return 0;
+
+ ct_cr_write_1(chp, 0x37, regval | 0x08);
+ regval = ct_cr_read_1(chp, 0x3f);
+ ct_cr_write_1(chp, 0x3f, regval | 0x08);
+ return 1;
+}
+
+static int
+bshw_dma_init_sc98(ct)
+ struct ct_softc *ct;
+{
+ struct ct_bus_access_handle *chp = &ct->sc_ch;
+
+ if (ct_cr_read_1(chp, 0x37) & 0x08)
+ return 0;
+
+ /* If your card is SC98 with bios ver 1.01 or 1.02 under no PCI */
+ ct_cr_write_1(chp, 0x37, 0x1a);
+ ct_cr_write_1(chp, 0x3f, 0x1a);
+#if 0
+ /* only valid for IO */
+ ct_cr_write_1(chp, 0x40, 0xf4);
+ ct_cr_write_1(chp, 0x41, 0x9);
+ ct_cr_write_1(chp, 0x43, 0xff);
+ ct_cr_write_1(chp, 0x46, 0x4e);
+
+ ct_cr_write_1(chp, 0x48, 0xf4);
+ ct_cr_write_1(chp, 0x49, 0x9);
+ ct_cr_write_1(chp, 0x4b, 0xff);
+ ct_cr_write_1(chp, 0x4e, 0x4e);
+#endif
+ return 1;
+}
+
+static void
+bshw_dma_start_sc98(ct)
+ struct ct_softc *ct;
+{
+ struct ct_bus_access_handle *chp = &ct->sc_ch;
+
+ ct_cr_write_1(chp, 0x73, 0x32);
+ ct_cr_write_1(chp, 0x74, 0x23);
+}
+
+static void
+bshw_dma_stop_sc98(ct)
+ struct ct_softc *ct;
+{
+ struct ct_bus_access_handle *chp = &ct->sc_ch;
+
+ ct_cr_write_1(chp, 0x73, 0x43);
+ ct_cr_write_1(chp, 0x74, 0x34);
+}
+
+static void
+bshw_dma_start_elecom(ct)
+ struct ct_softc *ct;
+{
+ struct ct_bus_access_handle *chp = &ct->sc_ch;
+ u_int8_t tmp = ct_cr_read_1(chp, 0x4c);
+
+ ct_cr_write_1(chp, 0x32, tmp & 0xdf);
+}
+
+static void
+bshw_dma_stop_elecom(ct)
+ struct ct_softc *ct;
+{
+ struct ct_bus_access_handle *chp = &ct->sc_ch;
+ u_int8_t tmp = ct_cr_read_1(chp, 0x4c);
+
+ ct_cr_write_1(chp, 0x32, tmp | 0x20);
+}
+
+static struct bshw bshw_generic = {
+ BSHW_SYNC_RELOAD,
+
+ 0,
+
+ NULL,
+ NULL,
+ NULL,
+};
+
+static struct bshw bshw_sc98 = {
+ BSHW_DOUBLE_DMACHAN,
+
+ 0x60,
+
+ bshw_dma_init_sc98,
+ bshw_dma_start_sc98,
+ bshw_dma_stop_sc98,
+};
+
+static struct bshw bshw_texa = {
+ BSHW_DOUBLE_DMACHAN,
+
+ 0x60,
+
+ bshw_dma_init_texa,
+ NULL,
+ NULL,
+};
+
+static struct bshw bshw_elecom = {
+ 0,
+
+ 0x38,
+
+ NULL,
+ bshw_dma_start_elecom,
+ bshw_dma_stop_elecom,
+};
+
+static struct bshw bshw_lc_smit = {
+ BSHW_SMFIFO | BSHW_DOUBLE_DMACHAN,
+
+ 0x60,
+
+ NULL,
+ NULL,
+ NULL,
+};
+
+static struct bshw bshw_lha20X = {
+ BSHW_DOUBLE_DMACHAN,
+
+ 0x60,
+
+ NULL,
+ NULL,
+ NULL,
+};
+
+/* hw tabs */
+static dvcfg_hw_t bshw_hwsel_array[] = {
+/* 0x00 */ &bshw_generic,
+/* 0x01 */ &bshw_sc98,
+/* 0x02 */ &bshw_texa,
+/* 0x03 */ &bshw_elecom,
+/* 0x04 */ &bshw_lc_smit,
+/* 0x05 */ &bshw_lha20X,
+};
+
+struct dvcfg_hwsel bshw_hwsel = {
+ DVCFG_HWSEL_SZ(bshw_hwsel_array),
+ bshw_hwsel_array
+};
diff --git a/sys/dev/ct/bshwvar.h b/sys/dev/ct/bshwvar.h
new file mode 100644
index 0000000..9e2259c
--- /dev/null
+++ b/sys/dev/ct/bshwvar.h
@@ -0,0 +1,96 @@
+/* $FreeBSD$ */
+/* $NecBSD: bshwvar.h,v 1.3.14.3 2001/06/21 04:07:37 honda Exp $ */
+/* $NetBSD$ */
+
+/*
+ * [NetBSD for NEC PC-98 series]
+ * Copyright (c) 1994, 1995, 1996, 1997, 1998
+ * NetBSD/pc98 porting staff. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _BSHWVAR_H_
+#define _BSHWVAR_H_
+
+/*
+ * bshwvar.h
+ * NEC 55 compatible board specific definitions
+ */
+
+#define BSHW_DEFAULT_CHIPCLK 20 /* 20MHz */
+#define BSHW_DEFAULT_HOSTID 7
+
+struct bshw {
+#define BSHW_SYNC_RELOAD 0x01
+#define BSHW_SMFIFO 0x02
+#define BSHW_DOUBLE_DMACHAN 0x04
+ u_int hw_flags;
+ u_int hw_sregaddr;
+
+ int ((*hw_dma_init)(struct ct_softc *));
+ void ((*hw_dma_start)(struct ct_softc *));
+ void ((*hw_dma_stop)(struct ct_softc *));
+};
+
+struct bshw_softc {
+ int sc_hostid;
+ int sc_irq; /* irq */
+ int sc_drq; /* drq */
+
+ /* dma transfer */
+ u_int8_t *sc_segaddr;
+ u_int8_t *sc_bufp;
+ int sc_seglen;
+ u_int sc_sdatalen; /* SMIT */
+ u_int sc_edatalen; /* SMIT */
+
+ /* private bounce */
+ u_int8_t *sc_bounce_phys;
+ u_int8_t *sc_bounce_addr;
+ u_int sc_bounce_size;
+ bus_addr_t sc_minphys;
+
+ /* io control */
+#define BSHW_READ_INTERRUPT_DRIVEN 0x0001
+#define BSHW_WRITE_INTERRUPT_DRIVEN 0x0002
+#define BSHW_DMA_BLOCK 0x0010
+#define BSHW_SMIT_BLOCK 0x0020
+ u_int sc_io_control;
+
+ /* hardware */
+ struct bshw *sc_hw;
+ void ((*sc_dmasync_before))(struct ct_softc *);
+ void ((*sc_dmasync_after))(struct ct_softc *);
+};
+
+void bshw_synch_setup(struct ct_softc *, struct targ_info *);
+void bshw_bus_reset(struct ct_softc *);
+int bshw_read_settings(struct ct_bus_access_handle *, struct bshw_softc *);
+int bshw_smit_xfer_start(struct ct_softc *);
+void bshw_smit_xfer_stop(struct ct_softc *);
+int bshw_dma_xfer_start(struct ct_softc *);
+void bshw_dma_xfer_stop(struct ct_softc *);
+
+extern struct dvcfg_hwsel bshw_hwsel;
+#endif /* !_BSHWVAR_H_ */
diff --git a/sys/dev/ct/ct.c b/sys/dev/ct/ct.c
new file mode 100644
index 0000000..00ef8c1
--- /dev/null
+++ b/sys/dev/ct/ct.c
@@ -0,0 +1,1309 @@
+/* $NecBSD: ct.c,v 1.13.12.5 2001/06/26 07:31:53 honda Exp $ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+/* $NetBSD$ */
+
+#define CT_DEBUG
+#define CT_IO_CONTROL_FLAGS (CT_USE_CCSEQ | CT_FAST_INTR)
+
+/*
+ * [NetBSD for NEC PC-98 series]
+ * Copyright (c) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
+ * NetBSD/pc98 porting staff. All rights reserved.
+ *
+ * Copyright (c) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
+ * Naofumi HONDA. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "opt_ddb.h"
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+#if defined(__FreeBSD__) && __FreeBSD_version > 500001
+#include <sys/bio.h>
+#endif /* __ FreeBSD__ */
+#include <sys/buf.h>
+#include <sys/queue.h>
+#include <sys/malloc.h>
+#include <sys/errno.h>
+
+#ifdef __NetBSD__
+#include <sys/device.h>
+
+#include <machine/bus.h>
+#include <machine/intr.h>
+
+#include <dev/scsipi/scsi_all.h>
+#include <dev/scsipi/scsipi_all.h>
+#include <dev/scsipi/scsiconf.h>
+#include <dev/scsipi/scsi_disk.h>
+
+#include <machine/dvcfg.h>
+#include <machine/physio_proc.h>
+
+#include <i386/Cbus/dev/scsi_low.h>
+
+#include <dev/ic/wd33c93reg.h>
+#include <i386/Cbus/dev/ct/ctvar.h>
+#include <i386/Cbus/dev/ct/ct_machdep.h>
+#endif /* __NetBSD__ */
+
+#ifdef __FreeBSD__
+#include <machine/bus.h>
+
+#include <machine/dvcfg.h>
+#include <machine/physio_proc.h>
+
+#include <cam/scsi/scsi_low.h>
+
+#include <dev/ic/wd33c93reg.h>
+#include <dev/ct/ctvar.h>
+#include <dev/ct/ct_machdep.h>
+#endif /* __FreeBSD__ */
+
+#define CT_NTARGETS 8
+#define CT_NLUNS 8
+#define CT_RESET_DEFAULT 2000
+#define CT_DELAY_MAX (2 * 1000 * 1000)
+#define CT_DELAY_INTERVAL (1)
+
+/***************************************************
+ * DEBUG
+ ***************************************************/
+#ifdef CT_DEBUG
+int ct_debug;
+#endif /* CT_DEBUG */
+
+/***************************************************
+ * IO control
+ ***************************************************/
+#define CT_USE_CCSEQ 0x0100
+#define CT_FAST_INTR 0x0200
+
+u_int ct_io_control = CT_IO_CONTROL_FLAGS;
+
+/***************************************************
+ * default data
+ ***************************************************/
+u_int8_t cthw_cmdlevel[256] = {
+/* 0 1 2 3 4 5 6 7 8 9 A B C E D F */
+/*0*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,1 ,0 ,1 ,0 ,0 ,0 ,0 ,0 ,
+/*1*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
+/*2*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,1 ,0 ,1 ,0 ,0 ,0 ,0 ,0 ,
+/*3*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
+/*4*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
+/*5*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
+/*6*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
+/*7*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
+/*8*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
+/*9*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
+/*A*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
+/*B*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
+/*C*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
+/*D*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
+/*E*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
+/*F*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
+};
+
+#if 0
+/* default synch data table */
+/* A 10 6.6 5.0 4.0 3.3 2.8 2.5 2.0 M/s */
+/* X 100 150 200 250 300 350 400 500 ns */
+static struct ct_synch_data ct_synch_data_FSCSI[] = {
+ {25, 0xa0}, {37, 0xb0}, {50, 0x20}, {62, 0xd0}, {75, 0x30},
+ {87, 0xf0}, {100, 0x40}, {125, 0x50}, {0, 0}
+};
+
+static struct ct_synch_data ct_synch_data_SCSI[] = {
+ {50, 0x20}, {75, 0x30}, {100, 0x40}, {125, 0x50}, {0, 0}
+};
+#endif
+/***************************************************
+ * DEVICE STRUCTURE
+ ***************************************************/
+extern struct cfdriver ct_cd;
+
+/*****************************************************************
+ * Interface functions
+ *****************************************************************/
+static int ct_xfer(struct ct_softc *, u_int8_t *, int, int, u_int *);
+static void ct_io_xfer(struct ct_softc *);
+static int ct_reselected(struct ct_softc *, u_int8_t);
+static void ct_phase_error(struct ct_softc *, u_int8_t);
+static int ct_start_selection(struct ct_softc *, struct slccb *);
+static int ct_msg(struct ct_softc *, struct targ_info *, u_int);
+static int ct_world_start(struct ct_softc *, int);
+static __inline void cthw_phase_bypass(struct ct_softc *, u_int8_t);
+static int cthw_chip_reset(struct ct_bus_access_handle *, int *, int, int);
+static void cthw_bus_reset(struct ct_softc *);
+static int ct_ccb_nexus_establish(struct ct_softc *);
+static int ct_lun_nexus_establish(struct ct_softc *);
+static int ct_target_nexus_establish(struct ct_softc *, int, int);
+static void cthw_attention(struct ct_softc *);
+static int ct_targ_init(struct ct_softc *, struct targ_info *, int);
+static int ct_unbusy(struct ct_softc *);
+static void ct_attention(struct ct_softc *);
+static struct ct_synch_data *ct_make_synch_table(struct ct_softc *);
+static int ct_catch_intr(struct ct_softc *);
+
+struct scsi_low_funcs ct_funcs = {
+ SC_LOW_INIT_T ct_world_start,
+ SC_LOW_BUSRST_T cthw_bus_reset,
+ SC_LOW_TARG_INIT_T ct_targ_init,
+ SC_LOW_LUN_INIT_T NULL,
+
+ SC_LOW_SELECT_T ct_start_selection,
+ SC_LOW_NEXUS_T ct_lun_nexus_establish,
+ SC_LOW_NEXUS_T ct_ccb_nexus_establish,
+
+ SC_LOW_ATTEN_T cthw_attention,
+ SC_LOW_MSG_T ct_msg,
+
+ SC_LOW_TIMEOUT_T NULL,
+ SC_LOW_POLL_T ctintr,
+
+ NULL, /* SC_LOW_POWER_T cthw_power, */
+};
+
+/**************************************************
+ * HW functions
+ **************************************************/
+static __inline void
+cthw_phase_bypass(ct, ph)
+ struct ct_softc *ct;
+ u_int8_t ph;
+{
+ struct ct_bus_access_handle *chp = &ct->sc_ch;
+
+ ct_cr_write_1(chp, wd3s_cph, ph);
+ ct_cr_write_1(chp, wd3s_cmd, WD3S_SELECT_ATN_TFR);
+}
+
+static void
+cthw_bus_reset(ct)
+ struct ct_softc *ct;
+{
+
+ /*
+ * wd33c93 does not have bus reset function.
+ */
+ if (ct->ct_bus_reset != NULL)
+ ((*ct->ct_bus_reset) (ct));
+}
+
+static int
+cthw_chip_reset(chp, chiprevp, chipclk, hostid)
+ struct ct_bus_access_handle *chp;
+ int *chiprevp;
+ int chipclk, hostid;
+{
+#define CT_SELTIMEOUT_20MHz_REGV (0x80)
+ u_int8_t aux, regv;
+ u_int seltout;
+ int wc;
+
+ /* issue abort cmd */
+ ct_cr_write_1(chp, wd3s_cmd, WD3S_ABORT);
+ SCSI_LOW_DELAY(1000); /* 1ms wait */
+ (void) ct_stat_read_1(chp);
+ (void) ct_cr_read_1(chp, wd3s_stat);
+
+ /* setup chip registers */
+ regv = 0;
+ seltout = CT_SELTIMEOUT_20MHz_REGV;
+ switch (chipclk)
+ {
+ case 8:
+ case 10:
+ seltout = (seltout * chipclk) / 20;
+ regv = IDR_FS_8_10;
+ break;
+
+ case 12:
+ case 15:
+ seltout = (seltout * chipclk) / 20;
+ regv = IDR_FS_12_15;
+ break;
+
+ case 16:
+ case 20:
+ seltout = (seltout * chipclk) / 20;
+ regv = IDR_FS_16_20;
+ break;
+
+ default:
+ panic("ct: illegal chip clk rate");
+ break;
+ }
+
+ regv |= IDR_EHP | hostid | IDR_RAF | IDR_EAF;
+ ct_cr_write_1(chp, wd3s_oid, regv);
+
+ ct_cr_write_1(chp, wd3s_cmd, WD3S_RESET);
+ for (wc = CT_RESET_DEFAULT; wc > 0; wc --)
+ {
+ aux = ct_stat_read_1(chp);
+ if (aux != 0xff && (aux & STR_INT))
+ {
+ regv = ct_cr_read_1(chp, wd3s_stat);
+ if (regv == BSR_RESET || regv == BSR_AFM_RESET)
+ break;
+
+ ct_cr_write_1(chp, wd3s_cmd, WD3S_RESET);
+ }
+ SCSI_LOW_DELAY(1);
+ }
+ if (wc == 0)
+ return ENXIO;
+
+ ct_cr_write_1(chp, wd3s_tout, seltout);
+ ct_cr_write_1(chp, wd3s_sid, SIDR_RESEL);
+ ct_cr_write_1(chp, wd3s_ctrl, CR_DEFAULT);
+ ct_cr_write_1(chp, wd3s_synch, 0);
+ if (chiprevp != NULL)
+ {
+ *chiprevp = CT_WD33C93;
+ if (regv == BSR_RESET)
+ goto out;
+
+ *chiprevp = CT_WD33C93_A;
+ ct_cr_write_1(chp, wd3s_qtag, 0xaa);
+ if (ct_cr_read_1(chp, wd3s_qtag) != 0xaa)
+ {
+ ct_cr_write_1(chp, wd3s_qtag, 0x0);
+ goto out;
+ }
+ ct_cr_write_1(chp, wd3s_qtag, 0x55);
+ if (ct_cr_read_1(chp, wd3s_qtag) != 0x55)
+ {
+ ct_cr_write_1(chp, wd3s_qtag, 0x0);
+ goto out;
+ }
+ ct_cr_write_1(chp, wd3s_qtag, 0x0);
+ *chiprevp = CT_WD33C93_B;
+ }
+
+out:
+ (void) ct_stat_read_1(chp);
+ (void) ct_cr_read_1(chp, wd3s_stat);
+ return 0;
+}
+
+static struct ct_synch_data *
+ct_make_synch_table(ct)
+ struct ct_softc *ct;
+{
+ struct ct_synch_data *sdtp, *sdp;
+ u_int base, i, period;
+
+ sdtp = sdp = &ct->sc_default_sdt[0];
+
+ if ((ct->sc_chipclk % 5) == 0)
+ base = 1000 / (5 * 2); /* 5 MHz type */
+ else
+ base = 1000 / (4 * 2); /* 4 MHz type */
+
+ if (ct->sc_chiprev >= CT_WD33C93_B)
+ {
+ /* fast scsi */
+ for (i = 2; i < 8; i ++, sdp ++)
+ {
+ period = (base * i) / 2;
+ if (period >= 200) /* 5 MHz */
+ break;
+ sdp->cs_period = period / 4;
+ sdp->cs_syncr = (i * 0x10) | 0x80;
+ }
+ }
+
+ for (i = 2; i < 8; i ++, sdp ++)
+ {
+ period = (base * i);
+ if (period > 500) /* 2 MHz */
+ break;
+ sdp->cs_period = period / 4;
+ sdp->cs_syncr = (i * 0x10);
+ }
+
+ sdp->cs_period = 0;
+ sdp->cs_syncr = 0;
+ return sdtp;
+}
+
+/**************************************************
+ * Attach & Probe
+ **************************************************/
+int
+ctprobesubr(chp, dvcfg, hsid, chipclk, chiprevp)
+ struct ct_bus_access_handle *chp;
+ u_int dvcfg, chipclk;
+ int hsid;
+ int *chiprevp;
+{
+
+#if 0
+ if ((ct_stat_read_1(chp) & STR_BSY) != 0)
+ return 0;
+#endif
+ if (cthw_chip_reset(chp, chiprevp, chipclk, hsid) != 0)
+ return 0;
+ return 1;
+}
+
+int
+ctprint(aux, name)
+ void *aux;
+ const char *name;
+{
+
+ if (name != NULL)
+ printf("%s: scsibus ", name);
+ return UNCONF;
+}
+
+void
+ctattachsubr(ct)
+ struct ct_softc *ct;
+{
+ struct scsi_low_softc *slp = &ct->sc_sclow;
+
+ ct->sc_tmaxcnt = SCSI_LOW_MIN_TOUT * 1000 * 1000; /* default */
+ slp->sl_funcs = &ct_funcs;
+ slp->sl_flags |= HW_READ_PADDING;
+ (void) scsi_low_attach(slp, 0, CT_NTARGETS, CT_NLUNS,
+ sizeof(struct ct_targ_info), 0);
+}
+
+/**************************************************
+ * SCSI LOW interface functions
+ **************************************************/
+static void
+cthw_attention(ct)
+ struct ct_softc *ct;
+{
+ struct ct_bus_access_handle *chp = &ct->sc_ch;
+
+ ct->sc_atten = 1;
+ if ((ct_stat_read_1(chp) & (STR_BSY | STR_CIP)) != 0)
+ return;
+
+ ct_cr_write_1(chp, wd3s_cmd, WD3S_ASSERT_ATN);
+ SCSI_LOW_DELAY(10);
+ if ((ct_stat_read_1(chp) & STR_LCI) == 0)
+ ct->sc_atten = 0;
+ ct_unbusy(ct);
+ return;
+}
+
+static void
+ct_attention(ct)
+ struct ct_softc *ct;
+{
+ struct scsi_low_softc *slp = &ct->sc_sclow;
+
+ if (slp->sl_atten == 0)
+ {
+ ct_unbusy(ct);
+ scsi_low_attention(slp);
+ }
+ else if (ct->sc_atten != 0)
+ {
+ ct_unbusy(ct);
+ cthw_attention(ct);
+ }
+}
+
+static int
+ct_targ_init(ct, ti, action)
+ struct ct_softc *ct;
+ struct targ_info *ti;
+ int action;
+{
+ struct ct_targ_info *cti = (void *) ti;
+
+ if (action == SCSI_LOW_INFO_ALLOC || action == SCSI_LOW_INFO_REVOKE)
+ {
+ if (ct->sc_sdp == NULL)
+ {
+ ct->sc_sdp = ct_make_synch_table(ct);
+ }
+
+ switch (ct->sc_chiprev)
+ {
+ default:
+ ti->ti_maxsynch.offset = 5;
+ break;
+
+ case CT_WD33C93_A:
+ case CT_AM33C93_A:
+ ti->ti_maxsynch.offset = 12;
+ break;
+
+ case CT_WD33C93_B:
+ case CT_WD33C93_C:
+ ti->ti_maxsynch.offset = 12;
+ break;
+ }
+
+ ti->ti_maxsynch.period = ct->sc_sdp[0].cs_period;
+ ti->ti_width = SCSI_LOW_BUS_WIDTH_8;
+ cti->cti_syncreg = 0;
+ }
+
+ return 0;
+}
+
+static int
+ct_world_start(ct, fdone)
+ struct ct_softc *ct;
+ int fdone;
+{
+ struct scsi_low_softc *slp = &ct->sc_sclow;
+ struct ct_bus_access_handle *chp = &ct->sc_ch;
+
+ if (ct->sc_sdp == NULL)
+ {
+ ct->sc_sdp = ct_make_synch_table(ct);
+ }
+
+ if (slp->sl_cfgflags & CFG_NOPARITY)
+ ct->sc_creg = CR_DEFAULT;
+ else
+ ct->sc_creg = CR_DEFAULT_HP;
+
+ if (ct->sc_dma & CT_DMA_DMASTART)
+ (*ct->ct_dma_xfer_stop) (ct);
+ if (ct->sc_dma & CT_DMA_PIOSTART)
+ (*ct->ct_pio_xfer_stop) (ct);
+ ct->sc_dma = 0;
+ ct->sc_atten = 0;
+
+ cthw_chip_reset(chp, NULL, ct->sc_chipclk, slp->sl_hostid);
+ scsi_low_bus_reset(slp);
+ cthw_chip_reset(chp, NULL, ct->sc_chipclk, slp->sl_hostid);
+
+ SOFT_INTR_REQUIRED(slp);
+ return 0;
+}
+
+static int
+ct_start_selection(ct, cb)
+ struct ct_softc *ct;
+ struct slccb *cb;
+{
+ struct scsi_low_softc *slp = &ct->sc_sclow;
+ struct ct_bus_access_handle *chp = &ct->sc_ch;
+
+ struct targ_info *ti = slp->sl_Tnexus;
+ struct lun_info *li = slp->sl_Lnexus;
+ int s, satok;
+ u_int8_t cmd;
+
+ ct->sc_tmaxcnt = cb->ccb_tcmax * 1000 * 1000;
+ ct->sc_atten = 0;
+ satok = 0;
+
+ if (scsi_low_is_disconnect_ok(cb) != 0)
+ {
+ if (ct->sc_chiprev >= CT_WD33C93_A)
+ satok = 1;
+ else if (cthw_cmdlevel[slp->sl_scp.scp_cmd[0]] != 0)
+ satok = 1;
+ }
+
+ if (satok != 0 &&
+ scsi_low_is_msgout_continue(ti, SCSI_LOW_MSG_IDENTIFY) == 0)
+ {
+ cmd = WD3S_SELECT_ATN_TFR;
+ ct->sc_satgo = CT_SAT_GOING;
+ }
+ else
+ {
+ cmd = WD3S_SELECT_ATN;
+ ct->sc_satgo = 0;
+ }
+
+ if ((ct_stat_read_1(chp) & (STR_BSY | STR_INT | STR_CIP)) != 0)
+ return SCSI_LOW_START_FAIL;
+
+ if ((ct->sc_satgo & CT_SAT_GOING) != 0)
+ {
+ (void) scsi_low_msgout(slp, ti, SCSI_LOW_MSGOUT_INIT);
+ scsi_low_cmd(slp, ti);
+ ct_cr_write_1(chp, wd3s_oid, slp->sl_scp.scp_cmdlen);
+ ct_write_cmds(chp, slp->sl_scp.scp_cmd, slp->sl_scp.scp_cmdlen);
+ }
+ else
+ {
+ /* anyway attention assert */
+ SCSI_LOW_ASSERT_ATN(slp);
+ }
+
+ ct_target_nexus_establish(ct, li->li_lun, slp->sl_scp.scp_direction);
+
+ s = splhigh();
+ if ((ct_stat_read_1(chp) & (STR_BSY | STR_INT | STR_CIP)) == 0)
+ {
+ /* XXX:
+ * Reload a lun again here.
+ */
+ ct_cr_write_1(chp, wd3s_lun, li->li_lun);
+ ct_cr_write_1(chp, wd3s_cmd, cmd);
+ if ((ct_stat_read_1(chp) & STR_LCI) == 0)
+ {
+ splx(s);
+ SCSI_LOW_SETUP_PHASE(ti, PH_SELSTART);
+ return SCSI_LOW_START_OK;
+ }
+ }
+ splx(s);
+ return SCSI_LOW_START_FAIL;
+}
+
+static int
+ct_msg(ct, ti, msg)
+ struct ct_softc *ct;
+ struct targ_info *ti;
+ u_int msg;
+{
+ struct ct_bus_access_handle *chp = &ct->sc_ch;
+ struct ct_targ_info *cti = (void *) ti;
+ struct ct_synch_data *csp = ct->sc_sdp;
+ u_int offset, period;
+ int error;
+
+ if ((msg & SCSI_LOW_MSG_WIDE) != 0)
+ {
+ if (ti->ti_width != SCSI_LOW_BUS_WIDTH_8)
+ {
+ ti->ti_width = SCSI_LOW_BUS_WIDTH_8;
+ return EINVAL;
+ }
+ return 0;
+ }
+
+ if ((msg & SCSI_LOW_MSG_SYNCH) == 0)
+ return 0;
+
+ offset = ti->ti_maxsynch.offset;
+ period = ti->ti_maxsynch.period;
+ for ( ; csp->cs_period != 0; csp ++)
+ {
+ if (period == csp->cs_period)
+ break;
+ }
+
+ if (ti->ti_maxsynch.period != 0 && csp->cs_period == 0)
+ {
+ ti->ti_maxsynch.period = 0;
+ ti->ti_maxsynch.offset = 0;
+ cti->cti_syncreg = 0;
+ error = EINVAL;
+ }
+ else
+ {
+ cti->cti_syncreg = ((offset & 0x0f) | csp->cs_syncr);
+ error = 0;
+ }
+
+ if (ct->ct_synch_setup != 0)
+ (*ct->ct_synch_setup) (ct, ti);
+ ct_cr_write_1(chp, wd3s_synch, cti->cti_syncreg);
+ return error;
+}
+
+/*************************************************
+ * <DATA PHASE>
+ *************************************************/
+static int
+ct_xfer(ct, data, len, direction, statp)
+ struct ct_softc *ct;
+ u_int8_t *data;
+ int len, direction;
+ u_int *statp;
+{
+ struct ct_bus_access_handle *chp = &ct->sc_ch;
+ int wc;
+ register u_int8_t aux;
+
+ *statp = 0;
+ if (len == 1)
+ {
+ ct_cr_write_1(chp, wd3s_cmd, WD3S_SBT | WD3S_TFR_INFO);
+ }
+ else
+ {
+ cthw_set_count(chp, len);
+ ct_cr_write_1(chp, wd3s_cmd, WD3S_TFR_INFO);
+ }
+
+ aux = ct_stat_read_1(chp);
+ if ((aux & STR_LCI) != 0)
+ {
+ cthw_set_count(chp, 0);
+ return len;
+ }
+
+ for (wc = 0; wc < ct->sc_tmaxcnt; wc ++)
+ {
+ /* check data ready */
+ if ((aux & (STR_BSY | STR_DBR)) == (STR_BSY | STR_DBR))
+ {
+ if (direction == SCSI_LOW_READ)
+ {
+ *data = ct_cr_read_1(chp, wd3s_data);
+ if ((aux & STR_PE) != 0)
+ *statp |= SCSI_LOW_DATA_PE;
+ }
+ else
+ {
+ ct_cr_write_1(chp, wd3s_data, *data);
+ }
+ len --;
+ if (len <= 0)
+ break;
+ data ++;
+ }
+ else
+ {
+ SCSI_LOW_DELAY(1);
+ }
+
+ /* check phase miss */
+ aux = ct_stat_read_1(chp);
+ if ((aux & STR_INT) != 0)
+ break;
+ }
+ return len;
+}
+
+#define CT_PADDING_BUF_SIZE 32
+
+static void
+ct_io_xfer(ct)
+ struct ct_softc *ct;
+{
+ struct scsi_low_softc *slp = &ct->sc_sclow;
+ struct ct_bus_access_handle *chp = &ct->sc_ch;
+ struct sc_p *sp = &slp->sl_scp;
+ u_int stat;
+ int len;
+ u_int8_t pbuf[CT_PADDING_BUF_SIZE];
+
+ /* polling mode */
+ ct_cr_write_1(chp, wd3s_ctrl, ct->sc_creg);
+
+ if (sp->scp_datalen <= 0)
+ {
+ slp->sl_error |= PDMAERR;
+
+ if (slp->sl_scp.scp_direction == SCSI_LOW_WRITE)
+ SCSI_LOW_BZERO(pbuf, CT_PADDING_BUF_SIZE);
+ ct_xfer(ct, pbuf, CT_PADDING_BUF_SIZE,
+ sp->scp_direction, &stat);
+ }
+ else
+ {
+ len = ct_xfer(ct, sp->scp_data, sp->scp_datalen,
+ sp->scp_direction, &stat);
+ sp->scp_data += (sp->scp_datalen - len);
+ sp->scp_datalen = len;
+ }
+}
+
+/**************************************************
+ * <PHASE ERROR>
+ **************************************************/
+struct ct_err {
+ u_char *pe_msg;
+ u_int pe_err;
+ u_int pe_errmsg;
+ int pe_done;
+};
+
+struct ct_err ct_cmderr[] = {
+/*0*/ { "illegal cmd", FATALIO, SCSI_LOW_MSG_ABORT, 1},
+/*1*/ { "unexpected bus free", FATALIO, 0, 1},
+/*2*/ { NULL, SELTIMEOUTIO, 0, 1},
+/*3*/ { "scsi bus parity error", PARITYERR, SCSI_LOW_MSG_ERROR, 0},
+/*4*/ { "scsi bus parity error", PARITYERR, SCSI_LOW_MSG_ERROR, 0},
+/*5*/ { "unknown" , FATALIO, SCSI_LOW_MSG_ABORT, 1},
+/*6*/ { "miss reselection (target mode)", FATALIO, SCSI_LOW_MSG_ABORT, 0},
+/*7*/ { "wrong status byte", PARITYERR, SCSI_LOW_MSG_ERROR, 0},
+};
+
+static void
+ct_phase_error(ct, scsi_status)
+ struct ct_softc *ct;
+ u_int8_t scsi_status;
+{
+ struct scsi_low_softc *slp = &ct->sc_sclow;
+ struct targ_info *ti = slp->sl_Tnexus;
+ struct ct_err *pep;
+ u_int msg = 0;
+
+ if ((scsi_status & BSR_CM) == BSR_CMDERR &&
+ (scsi_status & BSR_PHVALID) == 0)
+ {
+ pep = &ct_cmderr[scsi_status & BSR_PM];
+ slp->sl_error |= pep->pe_err;
+ if ((pep->pe_err & PARITYERR) != 0)
+ {
+ if (ti->ti_phase == PH_MSGIN)
+ msg = SCSI_LOW_MSG_PARITY;
+ else
+ msg = SCSI_LOW_MSG_ERROR;
+ }
+ else
+ msg = pep->pe_errmsg;
+
+ if (msg != 0)
+ scsi_low_assert_msg(slp, slp->sl_Tnexus, msg, 1);
+
+ if (pep->pe_msg != NULL)
+ {
+ printf("%s: phase error: %s",
+ slp->sl_xname, pep->pe_msg);
+ scsi_low_print(slp, slp->sl_Tnexus);
+ }
+
+ if (pep->pe_done != 0)
+ scsi_low_disconnected(slp, ti);
+ }
+ else
+ {
+ slp->sl_error |= FATALIO;
+ scsi_low_restart(slp, SCSI_LOW_RESTART_HARD, "phase error");
+ }
+}
+
+/**************************************************
+ * ### SCSI PHASE SEQUENCER ###
+ **************************************************/
+static int
+ct_reselected(ct, scsi_status)
+ struct ct_softc *ct;
+ u_int8_t scsi_status;
+{
+ struct scsi_low_softc *slp = &ct->sc_sclow;
+ struct ct_bus_access_handle *chp = &ct->sc_ch;
+ struct targ_info *ti;
+ u_int sid;
+ u_int8_t regv;
+
+ ct->sc_atten = 0;
+ ct->sc_satgo &= ~CT_SAT_GOING;
+ regv = ct_cr_read_1(chp, wd3s_sid);
+ if ((regv & SIDR_VALID) == 0)
+ return EJUSTRETURN;
+
+ sid = regv & SIDR_IDM;
+ if ((ti = scsi_low_reselected(slp, sid)) == NULL)
+ return EJUSTRETURN;
+
+ ct_target_nexus_establish(ct, 0, SCSI_LOW_READ);
+ if (scsi_status != BSR_AFM_RESEL)
+ return EJUSTRETURN;
+
+ SCSI_LOW_SETUP_PHASE(ti, PH_MSGIN);
+ regv = ct_cr_read_1(chp, wd3s_data);
+ if (scsi_low_msgin(slp, ti, (u_int) regv) == 0)
+ {
+ if (scsi_low_is_msgout_continue(ti, 0) != 0)
+ {
+ /* XXX: scsi_low_attetion */
+ scsi_low_attention(slp);
+ }
+ }
+
+ if (ct->sc_atten != 0)
+ {
+ ct_attention(ct);
+ }
+
+ ct_cr_write_1(chp, wd3s_cmd, WD3S_NEGATE_ACK);
+ return EJUSTRETURN;
+}
+
+static int
+ct_target_nexus_establish(ct, lun, dir)
+ struct ct_softc *ct;
+ int lun, dir;
+{
+ struct scsi_low_softc *slp = &ct->sc_sclow;
+ struct ct_bus_access_handle *chp = &ct->sc_ch;
+ struct targ_info *ti = slp->sl_Tnexus;
+ struct ct_targ_info *cti = (void *) ti;
+
+ if (dir == SCSI_LOW_WRITE)
+ ct_cr_write_1(chp, wd3s_did, ti->ti_id);
+ else
+ ct_cr_write_1(chp, wd3s_did, ti->ti_id | DIDR_DPD);
+ ct_cr_write_1(chp, wd3s_lun, lun);
+ ct_cr_write_1(chp, wd3s_ctrl, ct->sc_creg | CR_DMA);
+ ct_cr_write_1(chp, wd3s_cph, 0);
+ ct_cr_write_1(chp, wd3s_synch, cti->cti_syncreg);
+ cthw_set_count(chp, 0);
+ return 0;
+}
+
+static int
+ct_lun_nexus_establish(ct)
+ struct ct_softc *ct;
+{
+ struct scsi_low_softc *slp = &ct->sc_sclow;
+ struct ct_bus_access_handle *chp = &ct->sc_ch;
+ struct lun_info *li = slp->sl_Lnexus;
+
+ ct_cr_write_1(chp, wd3s_lun, li->li_lun);
+ return 0;
+}
+
+static int
+ct_ccb_nexus_establish(ct)
+ struct ct_softc *ct;
+{
+ struct scsi_low_softc *slp = &ct->sc_sclow;
+ struct ct_bus_access_handle *chp = &ct->sc_ch;
+ struct lun_info *li = slp->sl_Lnexus;
+ struct targ_info *ti = slp->sl_Tnexus;
+ struct ct_targ_info *cti = (void *) ti;
+ struct slccb *cb = slp->sl_Qnexus;
+
+ ct->sc_tmaxcnt = cb->ccb_tcmax * 1000 * 1000;
+
+ if ((ct->sc_satgo & CT_SAT_GOING) != 0)
+ {
+ ct_cr_write_1(chp, wd3s_oid, slp->sl_scp.scp_cmdlen);
+ ct_write_cmds(chp, slp->sl_scp.scp_cmd, slp->sl_scp.scp_cmdlen);
+ }
+ if (slp->sl_scp.scp_direction == SCSI_LOW_WRITE)
+ ct_cr_write_1(chp, wd3s_did, ti->ti_id);
+ else
+ ct_cr_write_1(chp, wd3s_did, ti->ti_id | DIDR_DPD);
+ ct_cr_write_1(chp, wd3s_lun, li->li_lun);
+ ct_cr_write_1(chp, wd3s_synch, cti->cti_syncreg);
+ return 0;
+}
+
+static int
+ct_unbusy(ct)
+ struct ct_softc *ct;
+{
+ struct scsi_low_softc *slp = &ct->sc_sclow;
+ struct ct_bus_access_handle *chp = &ct->sc_ch;
+ int wc;
+ register u_int8_t regv;
+
+ for (wc = 0; wc < CT_DELAY_MAX / CT_DELAY_INTERVAL; wc ++)
+ {
+ regv = ct_stat_read_1(chp);
+ if ((regv & (STR_BSY | STR_CIP)) == 0)
+ return 0;
+ if (regv == (u_int8_t) -1)
+ return EIO;
+
+ SCSI_LOW_DELAY(CT_DELAY_INTERVAL);
+ }
+
+ printf("%s: unbusy timeout\n", slp->sl_xname);
+ return EBUSY;
+}
+
+static int
+ct_catch_intr(ct)
+ struct ct_softc *ct;
+{
+ struct ct_bus_access_handle *chp = &ct->sc_ch;
+ int wc;
+ register u_int8_t regv;
+
+ for (wc = 0; wc < CT_DELAY_MAX / CT_DELAY_INTERVAL; wc ++)
+ {
+ regv = ct_stat_read_1(chp);
+ if ((regv & (STR_INT | STR_BSY | STR_CIP)) == STR_INT)
+ return 0;
+
+ SCSI_LOW_DELAY(CT_DELAY_INTERVAL);
+ }
+ return EJUSTRETURN;
+}
+
+int
+ctintr(arg)
+ void *arg;
+{
+ struct ct_softc *ct = arg;
+ struct scsi_low_softc *slp = &ct->sc_sclow;
+ struct ct_bus_access_handle *chp = &ct->sc_ch;
+ struct targ_info *ti;
+ struct physio_proc *pp;
+ struct buf *bp;
+ u_int derror, flags;
+ int len, satgo, error;
+ u_int8_t scsi_status, regv;
+
+again:
+ if (slp->sl_flags & HW_INACTIVE)
+ return 0;
+
+ /**************************************************
+ * Get status & bus phase
+ **************************************************/
+ if ((ct_stat_read_1(chp) & STR_INT) == 0)
+ return 0;
+
+ scsi_status = ct_cr_read_1(chp, wd3s_stat);
+ if (scsi_status == ((u_int8_t) -1))
+ return 1;
+
+ /**************************************************
+ * Check reselection, or nexus
+ **************************************************/
+ if (scsi_status == BSR_RESEL || scsi_status == BSR_AFM_RESEL)
+ {
+ if (ct_reselected(ct, scsi_status) == EJUSTRETURN)
+ return 1;
+ }
+
+ if ((ti = slp->sl_Tnexus) == NULL)
+ return 1;
+
+ /**************************************************
+ * Debug section
+ **************************************************/
+#ifdef CT_DEBUG
+ if (ct_debug > 0)
+ {
+ scsi_low_print(slp, NULL);
+ printf("%s: scsi_status 0x%x\n\n", slp->sl_xname,
+ (u_int) scsi_status);
+#ifdef DDB
+ if (ct_debug > 1)
+ SCSI_LOW_DEBUGGER("ct");
+#endif /* DDB */
+ }
+#endif /* CT_DEBUG */
+
+ /**************************************************
+ * Internal scsi phase
+ **************************************************/
+ satgo = ct->sc_satgo;
+ ct->sc_satgo &= ~CT_SAT_GOING;
+
+ switch (ti->ti_phase)
+ {
+ case PH_SELSTART:
+ if ((satgo & CT_SAT_GOING) == 0)
+ {
+ if (scsi_status != BSR_SELECTED)
+ {
+ ct_phase_error(ct, scsi_status);
+ return 1;
+ }
+ scsi_low_arbit_win(slp);
+ SCSI_LOW_SETUP_PHASE(ti, PH_SELECTED);
+ return 1;
+ }
+ else
+ {
+ scsi_low_arbit_win(slp);
+ SCSI_LOW_SETUP_PHASE(ti, PH_MSGOUT); /* XXX */
+ }
+ break;
+
+ case PH_RESEL:
+ if ((scsi_status & BSR_PHVALID) == 0 ||
+ (scsi_status & BSR_PM) != BSR_MSGIN)
+ {
+ scsi_low_restart(slp, SCSI_LOW_RESTART_HARD,
+ "phase miss after reselect");
+ return 1;
+ }
+ break;
+
+ default:
+ if (slp->sl_flags & HW_PDMASTART)
+ {
+ slp->sl_flags &= ~HW_PDMASTART;
+ if (ct->sc_dma & CT_DMA_DMASTART)
+ {
+ (*ct->ct_dma_xfer_stop) (ct);
+ ct->sc_dma &= ~CT_DMA_DMASTART;
+ }
+ else if (ct->sc_dma & CT_DMA_PIOSTART)
+ {
+ (*ct->ct_pio_xfer_stop) (ct);
+ ct->sc_dma &= ~CT_DMA_PIOSTART;
+ }
+ else
+ {
+ scsi_low_data_finish(slp);
+ }
+ }
+ break;
+ }
+
+ /**************************************************
+ * parse scsi phase
+ **************************************************/
+ if (scsi_status & BSR_PHVALID)
+ {
+ /**************************************************
+ * Normal SCSI phase.
+ **************************************************/
+ if ((scsi_status & BSR_CM) == BSR_CMDABT)
+ {
+ ct_phase_error(ct, scsi_status);
+ return 1;
+ }
+
+ switch (scsi_status & BSR_PM)
+ {
+ case BSR_DATAOUT:
+ SCSI_LOW_SETUP_PHASE(ti, PH_DATA);
+ if (scsi_low_data(slp, ti, &bp, SCSI_LOW_WRITE) != 0)
+ {
+ ct_attention(ct);
+ }
+ goto common_data_phase;
+
+ case BSR_DATAIN:
+ SCSI_LOW_SETUP_PHASE(ti, PH_DATA);
+ if (scsi_low_data(slp, ti, &bp, SCSI_LOW_READ) != 0)
+ {
+ ct_attention(ct);
+ }
+
+common_data_phase:
+ if (slp->sl_scp.scp_datalen > 0)
+ {
+ slp->sl_flags |= HW_PDMASTART;
+ if ((ct->sc_xmode & CT_XMODE_PIO) != 0)
+ {
+ pp = physio_proc_enter(bp);
+ error = (*ct->ct_pio_xfer_start) (ct);
+ physio_proc_leave(pp);
+ if (error == 0)
+ {
+ ct->sc_dma |= CT_DMA_PIOSTART;
+ return 1;
+ }
+ }
+
+ if ((ct->sc_xmode & CT_XMODE_DMA) != 0)
+ {
+ error = (*ct->ct_dma_xfer_start) (ct);
+ if (error == 0)
+ {
+ ct->sc_dma |= CT_DMA_DMASTART;
+ return 1;
+ }
+ }
+ }
+ else
+ {
+ if (slp->sl_scp.scp_direction == SCSI_LOW_READ)
+ {
+ if (!(slp->sl_flags & HW_READ_PADDING))
+ {
+ printf("%s: read padding required\n", slp->sl_xname);
+ return 1;
+ }
+ }
+ else
+ {
+ if (!(slp->sl_flags & HW_WRITE_PADDING))
+ {
+ printf("%s: write padding required\n", slp->sl_xname);
+ return 1;
+ }
+ }
+ slp->sl_flags |= HW_PDMASTART;
+ }
+
+ ct_io_xfer(ct);
+ return 1;
+
+ case BSR_CMDOUT:
+ SCSI_LOW_SETUP_PHASE(ti, PH_CMD);
+ if (scsi_low_cmd(slp, ti) != 0)
+ {
+ ct_attention(ct);
+ }
+
+ if (ct_xfer(ct, slp->sl_scp.scp_cmd,
+ slp->sl_scp.scp_cmdlen,
+ SCSI_LOW_WRITE, &derror) != 0)
+ {
+ printf("%s: scsi cmd xfer short\n",
+ slp->sl_xname);
+ }
+ return 1;
+
+ case BSR_STATIN:
+ SCSI_LOW_SETUP_PHASE(ti, PH_STAT);
+ if ((ct_io_control & CT_USE_CCSEQ) != 0)
+ {
+ if (scsi_low_is_msgout_continue(ti, 0) != 0 ||
+ ct->sc_atten != 0)
+ {
+ ct_xfer(ct, &regv, 1, SCSI_LOW_READ,
+ &derror);
+ scsi_low_statusin(slp, ti,
+ regv | derror);
+ }
+ else
+ {
+ ct->sc_satgo |= CT_SAT_GOING;
+ cthw_set_count(chp, 0);
+ cthw_phase_bypass(ct, 0x41);
+ }
+ }
+ else
+ {
+ ct_xfer(ct, &regv, 1, SCSI_LOW_READ, &derror);
+ scsi_low_statusin(slp, ti, regv | derror);
+ }
+ return 1;
+
+ case BSR_UNSPINFO0:
+ case BSR_UNSPINFO1:
+ printf("%s: illegal bus phase (0x%x)\n", slp->sl_xname,
+ (u_int) scsi_status);
+ scsi_low_print(slp, ti);
+ return 1;
+
+ case BSR_MSGOUT:
+ SCSI_LOW_SETUP_PHASE(ti, PH_MSGOUT);
+ flags = SCSI_LOW_MSGOUT_UNIFY;
+ if (ti->ti_ophase != ti->ti_phase)
+ flags |= SCSI_LOW_MSGOUT_INIT;
+ len = scsi_low_msgout(slp, ti, flags);
+
+ if (len > 1 && slp->sl_atten == 0)
+ {
+ ct_attention(ct);
+ }
+
+ if (ct_xfer(ct, ti->ti_msgoutstr, len,
+ SCSI_LOW_WRITE, &derror) != 0)
+ {
+ printf("%s: scsi msgout xfer short\n",
+ slp->sl_xname);
+ }
+ SCSI_LOW_DEASSERT_ATN(slp);
+ ct->sc_atten = 0;
+ return 1;
+
+ case BSR_MSGIN:/* msg in */
+ SCSI_LOW_SETUP_PHASE(ti, PH_MSGIN);
+
+ ct_xfer(ct, &regv, 1, SCSI_LOW_READ, &derror);
+ if (scsi_low_msgin(slp, ti, regv | derror) == 0)
+ {
+ if (scsi_low_is_msgout_continue(ti, 0) != 0)
+ {
+ /* XXX: scsi_low_attetion */
+ scsi_low_attention(slp);
+ }
+ }
+
+ if ((ct_io_control & CT_FAST_INTR) != 0)
+ {
+ if (ct_catch_intr(ct) == 0)
+ goto again;
+ }
+ return 1;
+ }
+ }
+ else
+ {
+ /**************************************************
+ * Special SCSI phase
+ **************************************************/
+ switch (scsi_status)
+ {
+ case BSR_SATSDP: /* SAT with save data pointer */
+ SCSI_LOW_SETUP_PHASE(ti, PH_MSGIN);
+ ct->sc_satgo |= CT_SAT_GOING;
+ scsi_low_msgin(slp, ti, MSG_SAVESP);
+ cthw_phase_bypass(ct, 0x41);
+ return 1;
+
+ case BSR_SATFIN: /* SAT COMPLETE */
+ /*
+ * emulate statusin => msgin
+ */
+ SCSI_LOW_SETUP_PHASE(ti, PH_STAT);
+ scsi_low_statusin(slp, ti, ct_cr_read_1(chp, wd3s_lun));
+
+ SCSI_LOW_SETUP_PHASE(ti, PH_MSGIN);
+ scsi_low_msgin(slp, ti, MSG_COMP);
+
+ scsi_low_disconnected(slp, ti);
+ return 1;
+
+ case BSR_ACKREQ: /* negate ACK */
+ if (ct->sc_atten != 0)
+ {
+ ct_attention(ct);
+ }
+
+ ct_cr_write_1(chp, wd3s_cmd, WD3S_NEGATE_ACK);
+ if ((ct_io_control & CT_FAST_INTR) != 0)
+ {
+ /* XXX:
+ * Should clear a pending interrupt and
+ * sync with a next interrupt!
+ */
+ ct_catch_intr(ct);
+ }
+ return 1;
+
+ case BSR_DISC: /* disconnect */
+ if (slp->sl_msgphase == MSGPH_NULL &&
+ (satgo & CT_SAT_GOING) != 0)
+ {
+ /*
+ * emulate disconnect msg
+ */
+ SCSI_LOW_SETUP_PHASE(ti, PH_MSGIN);
+ scsi_low_msgin(slp, ti, MSG_DISCON);
+ }
+ scsi_low_disconnected(slp, ti);
+ return 1;
+
+ default:
+ break;
+ }
+ }
+
+ ct_phase_error(ct, scsi_status);
+ return 1;
+}
diff --git a/sys/dev/ct/ct_isa.c b/sys/dev/ct/ct_isa.c
new file mode 100644
index 0000000..9592f36
--- /dev/null
+++ b/sys/dev/ct/ct_isa.c
@@ -0,0 +1,420 @@
+/* $NecBSD: ct_isa.c,v 1.6 1999/07/26 06:32:01 honda Exp $ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+/* $NetBSD$ */
+
+/*
+ * [NetBSD for NEC PC-98 series]
+ * Copyright (c) 1995, 1996, 1997, 1998
+ * NetBSD/pc98 porting staff. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#define SCSIBUS_RESCAN
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+#include <sys/bio.h>
+#include <sys/buf.h>
+#include <sys/queue.h>
+#include <sys/malloc.h>
+#include <sys/device_port.h>
+#include <sys/errno.h>
+
+#include <vm/vm.h>
+
+#ifdef __NetBSD__
+#include <machine/bus.h>
+#include <machine/intr.h>
+
+#include <dev/scsipi/scsi_all.h>
+#include <dev/scsipi/scsipi_all.h>
+#include <dev/scsipi/scsiconf.h>
+#include <dev/scsipi/scsi_disk.h>
+
+#include <dev/isa/isareg.h>
+#include <dev/isa/isavar.h>
+#include <dev/isa/isadmavar.h>
+
+#include <machine/dvcfg.h>
+#include <machine/physio_proc.h>
+#include <machine/syspmgr.h>
+
+#include <i386/Cbus/dev/scsi_low.h>
+
+#include <dev/ic/wd33c93reg.h>
+#include <i386/Cbus/dev/ct/ctvar.h>
+#include <i386/Cbus/dev/ct/bshwvar.h>
+#endif /* __NetBSD__ */
+
+#ifdef __FreeBSD__
+#include <machine/bus.h>
+#include <machine/resource.h>
+#include <sys/bus.h>
+#include <sys/rman.h>
+#include <machine/md_var.h>
+
+#include <pc98/pc98/pc98.h>
+#include <isa/isavar.h>
+
+#include <machine/dvcfg.h>
+#include <machine/physio_proc.h>
+
+#include <cam/scsi/scsi_low.h>
+
+#include <dev/ic/wd33c93reg.h>
+#include <dev/ct/ctvar.h>
+#include <dev/ct/bshwvar.h>
+#endif /* __FreeBSD__ */
+
+#define BSHW_IOSZ 0x08
+#define BSHW_IOBASE 0xcc0
+#define BSHW_MEMSZ (PAGE_SIZE * 2)
+
+static int ct_isa_match(device_t);
+static int ct_isa_attach(device_t);
+static int ct_space_map(device_t, struct bshw *,
+ struct resource **, struct resource **);
+static void ct_space_unmap(device_t, struct ct_softc *);
+static struct bshw *ct_find_hw(device_t);
+static void ct_dmamap(void *, bus_dma_segment_t *, int, int);
+static void ct_isa_bus_access_weight(struct ct_bus_access_handle *);
+static void ct_isa_dmasync_before(struct ct_softc *);
+static void ct_isa_dmasync_after(struct ct_softc *);
+
+struct ct_isa_softc {
+ struct ct_softc sc_ct;
+ struct bshw_softc sc_bshw;
+};
+
+static struct isa_pnp_id ct_pnp_ids[] = {
+ { 0x0100e7b1, "Logitec LHA-301" },
+ { 0x110154dc, "I-O DATA SC-98III" },
+ { 0x4120acb4, "MELCO IFC-NN" },
+ { 0, NULL }
+};
+
+static device_method_t ct_isa_methods[] = {
+ /* Device interface */
+ DEVMETHOD(device_probe, ct_isa_match),
+ DEVMETHOD(device_attach, ct_isa_attach),
+ { 0, 0 }
+};
+
+static driver_t ct_isa_driver = {
+ "ct", ct_isa_methods, sizeof(struct ct_isa_softc),
+};
+
+static devclass_t ct_devclass;
+
+DRIVER_MODULE(ct, isa, ct_isa_driver, ct_devclass, 0, 0);
+
+static int
+ct_isa_match(device_t dev)
+{
+ struct bshw *hw;
+ struct resource *port_res, *mem_res;
+ struct ct_bus_access_handle ch;
+ int rv;
+
+ if (ISA_PNP_PROBE(device_get_parent(dev), dev, ct_pnp_ids) == ENXIO)
+ return ENXIO;
+
+ switch (isa_get_logicalid(dev)) {
+ case 0x0100e7b1: /* LHA-301 */
+ case 0x110154dc: /* SC-98III */
+ case 0x4120acb4: /* IFC-NN */
+ /* XXX - force to SMIT mode */
+ device_set_flags(dev, device_get_flags(dev) | 0x40000);
+ break;
+ }
+
+ if (isa_get_port(dev) == -1)
+ bus_set_resource(dev, SYS_RES_IOPORT, 0,
+ BSHW_IOBASE, BSHW_IOSZ);
+
+ if ((hw = ct_find_hw(dev)) == NULL)
+ return ENXIO;
+ if (ct_space_map(dev, hw, &port_res, &mem_res) != 0)
+ return ENXIO;
+
+ bzero(&ch, sizeof(ch));
+ ch.ch_iot = rman_get_bustag(port_res);
+ ch.ch_ioh = rman_get_bushandle(port_res),
+ ch.ch_bus_weight = ct_isa_bus_access_weight;
+
+ rv = ctprobesubr(&ch, 0, BSHW_DEFAULT_HOSTID,
+ BSHW_DEFAULT_CHIPCLK, NULL);
+ if (rv != 0)
+ {
+ struct bshw_softc bshw_tab;
+ struct bshw_softc *bs = &bshw_tab;
+
+ memset(bs, 0, sizeof(*bs));
+ bshw_read_settings(&ch, bs);
+ bus_set_resource(dev, SYS_RES_IRQ, 0, bs->sc_irq, 1);
+ bus_set_resource(dev, SYS_RES_DRQ, 0, bs->sc_drq, 1);
+ }
+
+ bus_release_resource(dev, SYS_RES_IOPORT, 0, port_res);
+ if (mem_res != NULL)
+ bus_release_resource(dev, SYS_RES_MEMORY, 0, mem_res);
+
+ if (rv != 0)
+ return 0;
+ return ENXIO;
+}
+
+static int
+ct_isa_attach(device_t dev)
+{
+ struct ct_isa_softc *pct = device_get_softc(dev);
+ struct ct_softc *ct = &pct->sc_ct;
+ struct ct_bus_access_handle *chp = &ct->sc_ch;
+ struct scsi_low_softc *slp = &ct->sc_sclow;
+ struct bshw_softc *bs = &pct->sc_bshw;
+ struct bshw *hw;
+ int irq_rid, drq_rid, chiprev;
+ u_int8_t *vaddr;
+ bus_addr_t addr;
+ intrmask_t s;
+
+ hw = ct_find_hw(dev);
+ if (ct_space_map(dev, hw, &ct->port_res, &ct->mem_res) != 0) {
+ device_printf(dev, "bus io mem map failed\n");
+ return ENXIO;
+ }
+
+ bzero(chp, sizeof(*chp));
+ chp->ch_iot = rman_get_bustag(ct->port_res);
+ chp->ch_ioh = rman_get_bushandle(ct->port_res);
+ if (ct->mem_res) {
+ chp->ch_memt = rman_get_bustag(ct->mem_res);
+ chp->ch_memh = rman_get_bushandle(ct->mem_res);
+ }
+ chp->ch_bus_weight = ct_isa_bus_access_weight;
+
+ irq_rid = 0;
+ ct->irq_res = bus_alloc_resource(dev, SYS_RES_IRQ, &irq_rid, 0, ~0,
+ 1, RF_ACTIVE);
+ drq_rid = 0;
+ ct->drq_res = bus_alloc_resource(dev, SYS_RES_DRQ, &drq_rid, 0, ~0,
+ 1, RF_ACTIVE);
+ if (ct->irq_res == NULL || ct->drq_res == NULL) {
+ ct_space_unmap(dev, ct);
+ return ENXIO;
+ }
+
+ if (ctprobesubr(chp, 0, BSHW_DEFAULT_HOSTID,
+ BSHW_DEFAULT_CHIPCLK, &chiprev) == 0)
+ {
+ device_printf(dev, "hardware missing\n");
+ ct_space_unmap(dev, ct);
+ return ENXIO;
+ }
+
+ /* setup DMA map */
+ if (bus_dma_tag_create(NULL, 1, 0,
+ BUS_SPACE_MAXADDR_24BIT, BUS_SPACE_MAXADDR,
+ NULL, NULL, MAXBSIZE, 1,
+ BUS_SPACE_MAXSIZE_32BIT,
+ BUS_DMA_ALLOCNOW, NULL, NULL,
+ &ct->sc_dmat) != 0) {
+ device_printf(dev, "can't set up ISA DMA map\n");
+ ct_space_unmap(dev, ct);
+ return ENXIO;
+ }
+
+ if (bus_dmamem_alloc(ct->sc_dmat, (void **)&vaddr, BUS_DMA_NOWAIT,
+ &ct->sc_dmamapt) != 0) {
+ device_printf(dev, "can't set up ISA DMA map\n");
+ ct_space_unmap(dev, ct);
+ return ENXIO;
+ }
+
+ bus_dmamap_load(ct->sc_dmat, ct->sc_dmamapt, vaddr, MAXBSIZE,
+ ct_dmamap, &addr, BUS_DMA_NOWAIT);
+
+ /* setup machdep softc */
+ bs->sc_hw = hw;
+ bs->sc_io_control = 0;
+ bs->sc_bounce_phys = (u_int8_t *)addr;
+ bs->sc_bounce_addr = vaddr;
+ bs->sc_bounce_size = MAXBSIZE;
+ bs->sc_minphys = (1 << 24);
+ bs->sc_dmasync_before = ct_isa_dmasync_before;
+ bs->sc_dmasync_after = ct_isa_dmasync_after;
+ bshw_read_settings(chp, bs);
+
+ /* setup ct driver softc */
+ ct->ct_hw = bs;
+ ct->ct_dma_xfer_start = bshw_dma_xfer_start;
+ ct->ct_pio_xfer_start = bshw_smit_xfer_start;
+ ct->ct_dma_xfer_stop = bshw_dma_xfer_stop;
+ ct->ct_pio_xfer_stop = bshw_smit_xfer_stop;
+ ct->ct_bus_reset = bshw_bus_reset;
+ ct->ct_synch_setup = bshw_synch_setup;
+
+ ct->sc_xmode = CT_XMODE_DMA;
+ if (chp->ch_memh != NULL)
+ ct->sc_xmode |= CT_XMODE_PIO;
+
+ ct->sc_chiprev = chiprev;
+ switch (chiprev)
+ {
+ case CT_WD33C93:
+ /* s = "WD33C93"; */
+ ct->sc_chipclk = 8;
+ break;
+ case CT_WD33C93_A:
+ if (DVCFG_MAJOR(device_get_flags(dev)) > 0)
+ {
+ /* s = "AM33C93_A"; */
+ ct->sc_chipclk = 20;
+ ct->sc_chiprev = CT_AM33C93_A;
+ }
+ else
+ {
+ /* s = "WD33C93_A"; */
+ ct->sc_chipclk = 10;
+ }
+ break;
+
+ case CT_AM33C93_A:
+ /* s = "AM33C93_A"; */
+ ct->sc_chipclk = 20;
+ break;
+
+ default:
+ case CT_WD33C93_B:
+ /* s = "WD33C93_B"; */
+ ct->sc_chipclk = 20;
+ break;
+ }
+#if 0
+ printf("%s: chiprev %s chipclk %d Mhz\n",
+ slp->sl_dev.dv_xname, s, ct->sc_chipclk);
+#endif
+
+ slp->sl_dev = dev;
+ slp->sl_hostid = bs->sc_hostid;
+ slp->sl_irq = isa_get_irq(dev);
+ slp->sl_cfgflags = device_get_flags(dev);
+
+ s = splcam();
+ ctattachsubr(ct);
+ splx(s);
+
+ if (bus_setup_intr(dev, ct->irq_res, INTR_TYPE_CAM,
+ (driver_intr_t *)ctintr, ct, &ct->sc_ih)) {
+ ct_space_unmap(dev, ct);
+ return ENXIO;
+ }
+
+ return 0;
+}
+
+static struct bshw *
+ct_find_hw(device_t dev)
+{
+ return DVCFG_HW(&bshw_hwsel, DVCFG_MAJOR(device_get_flags(dev)));
+}
+
+static int
+ct_space_map(device_t dev, struct bshw *hw,
+ struct resource **iohp, struct resource **memhp)
+{
+ int port_rid, mem_rid;
+
+ *memhp = NULL;
+
+ port_rid = 0;
+ *iohp = bus_alloc_resource(dev, SYS_RES_IOPORT, &port_rid, 0, ~0,
+ BSHW_IOSZ, RF_ACTIVE);
+ if (*iohp == NULL)
+ return ENXIO;
+
+ if ((hw->hw_flags & BSHW_SMFIFO) == 0 || isa_get_maddr(dev) == -1)
+ return 0;
+
+ mem_rid = 0;
+ *memhp = bus_alloc_resource(dev, SYS_RES_MEMORY, &mem_rid, 0, ~0,
+ BSHW_MEMSZ, RF_ACTIVE);
+ if (*memhp == NULL) {
+ bus_release_resource(dev, SYS_RES_IOPORT, port_rid, *iohp);
+ return ENXIO;
+ }
+
+ return 0;
+}
+
+static void
+ct_space_unmap(device_t dev, struct ct_softc *ct)
+{
+ if (ct->port_res != NULL)
+ bus_release_resource(dev, SYS_RES_IOPORT, 0, ct->port_res);
+ if (ct->mem_res != NULL)
+ bus_release_resource(dev, SYS_RES_MEMORY, 0, ct->mem_res);
+ if (ct->irq_res != NULL)
+ bus_release_resource(dev, SYS_RES_IRQ, 0, ct->irq_res);
+ if (ct->drq_res != NULL)
+ bus_release_resource(dev, SYS_RES_DRQ, 0, ct->drq_res);
+}
+
+static void
+ct_dmamap(void *arg, bus_dma_segment_t *seg, int nseg, int error)
+{
+ bus_addr_t *addr = (bus_addr_t *)arg;
+
+ *addr = seg->ds_addr;
+}
+
+static void
+ct_isa_bus_access_weight(chp)
+ struct ct_bus_access_handle *chp;
+{
+
+ outb(0x5f, 0);
+}
+
+static void
+ct_isa_dmasync_before(ct)
+ struct ct_softc *ct;
+{
+
+ if (need_pre_dma_flush)
+ wbinvd();
+}
+
+static void
+ct_isa_dmasync_after(ct)
+ struct ct_softc *ct;
+{
+
+ if (need_post_dma_flush)
+ invd();
+}
diff --git a/sys/dev/ct/ct_machdep.h b/sys/dev/ct/ct_machdep.h
new file mode 100644
index 0000000..18a9ec8
--- /dev/null
+++ b/sys/dev/ct/ct_machdep.h
@@ -0,0 +1,216 @@
+/* $FreeBSD$ */
+/* $NecBSD: ct_machdep.h,v 1.4.12.2 2001/06/20 06:13:34 honda Exp $ */
+/* $NetBSD$ */
+
+/*
+ * [NetBSD for NEC PC-98 series]
+ * Copyright (c) 1995, 1996, 1997, 1998, 1999, 2000, 2001
+ * NetBSD/pc98 porting staff. All rights reserved.
+ * Copyright (c) 1995, 1996, 1997, 1998, 1999, 2000, 2001
+ * Naofumi HONDA. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _CT_MACHDEP_H_
+#define _CT_MACHDEP_H_
+
+#include "opt_ct.h"
+
+/*
+ * Principal rules:
+ * 1) do not use bus_space_write/read_X directly in ct.c.
+ * 2) do not use port offset defs directly in ct.c.
+ */
+
+/* special weight if requried */
+#ifdef CT_BUS_WEIGHT
+#undef CT_BUS_WEIGHT
+#define CT_BUS_WEIGHT(chp) \
+{ \
+ if ((chp)->ch_bus_weight != NULL) \
+ (chp)->ch_bus_weight((chp)); \
+}
+#else /* !CT_BUS_WEIGHT */
+#define CT_BUS_WEIGHT(chp)
+#endif /* !CT_BUS_WEIGHT */
+
+/* port offset */
+#ifndef CT_USE_RELOCATE_OFFSET
+#define addr_port 0
+#define stat_port 0
+#define ctrl_port 2
+#define cmd_port 4
+#else /* CT_USE_RELOCATE_OFFSET */
+#define addr_port ((chp)->ch_offset[0])
+#define stat_port ((chp)->ch_offset[1])
+#define ctrl_port ((chp)->ch_offset[2])
+#define cmd_port ((chp)->ch_offset[3])
+#endif /* CT_USE_RELOCATE_OFFSET */
+
+/*
+ * All port accesses primitive methods
+ */
+static __inline u_int8_t ct_stat_read_1
+ (struct ct_bus_access_handle *);
+static __inline u_int8_t ct_cmdp_read_1
+ (struct ct_bus_access_handle *);
+static __inline void ct_cmdp_write_1
+ (struct ct_bus_access_handle *, u_int8_t);
+static __inline u_int8_t ct_cr_read_1
+ (struct ct_bus_access_handle *, bus_addr_t);
+static __inline void ct_cr_write_1
+ (struct ct_bus_access_handle *, bus_addr_t, u_int8_t);
+static __inline void ct_write_cmds
+ (struct ct_bus_access_handle *, u_int8_t *, int);
+static __inline u_int cthw_get_count
+ (struct ct_bus_access_handle *);
+static __inline void cthw_set_count
+ (struct ct_bus_access_handle *, u_int);
+
+static __inline u_int8_t
+ct_stat_read_1(chp)
+ struct ct_bus_access_handle *chp;
+{
+ u_int8_t regv;
+
+ regv = bus_space_read_1(chp->ch_iot, chp->ch_ioh, stat_port);
+ CT_BUS_WEIGHT(chp)
+ return regv;
+}
+
+static __inline void
+cthw_set_count(chp, count)
+ struct ct_bus_access_handle *chp;
+ u_int count;
+{
+ bus_space_tag_t bst = chp->ch_iot;
+ bus_space_handle_t bsh = chp->ch_ioh;
+
+ bus_space_write_1(bst, bsh, addr_port, wd3s_cnt);
+ CT_BUS_WEIGHT(chp)
+ bus_space_write_1(bst, bsh, ctrl_port, count >> 16);
+ CT_BUS_WEIGHT(chp)
+ bus_space_write_1(bst, bsh, ctrl_port, count >> 8);
+ CT_BUS_WEIGHT(chp)
+ bus_space_write_1(bst, bsh, ctrl_port, count);
+ CT_BUS_WEIGHT(chp)
+}
+
+static __inline u_int
+cthw_get_count(chp)
+ struct ct_bus_access_handle *chp;
+{
+ bus_space_tag_t bst = chp->ch_iot;
+ bus_space_handle_t bsh = chp->ch_ioh;
+ u_int count;
+
+ bus_space_write_1(bst, bsh, addr_port, wd3s_cnt);
+ CT_BUS_WEIGHT(chp)
+ count = (((u_int) bus_space_read_1(bst, bsh, ctrl_port)) << 16);
+ CT_BUS_WEIGHT(chp)
+ count += (((u_int) bus_space_read_1(bst, bsh, ctrl_port)) << 8);
+ CT_BUS_WEIGHT(chp)
+ count += ((u_int) bus_space_read_1(bst, bsh, ctrl_port));
+ CT_BUS_WEIGHT(chp)
+ return count;
+}
+
+static __inline void
+ct_write_cmds(chp, cmd, len)
+ struct ct_bus_access_handle *chp;
+ u_int8_t *cmd;
+ int len;
+{
+ bus_space_tag_t bst = chp->ch_iot;
+ bus_space_handle_t bsh = chp->ch_ioh;
+ int i;
+
+ bus_space_write_1(bst, bsh, addr_port, wd3s_cdb);
+ CT_BUS_WEIGHT(chp)
+ for (i = 0; i < len; i ++)
+ {
+ bus_space_write_1(bst, bsh, ctrl_port, cmd[i]);
+ CT_BUS_WEIGHT(chp)
+ }
+}
+
+static __inline u_int8_t
+ct_cr_read_1(chp, offs)
+ struct ct_bus_access_handle *chp;
+ bus_addr_t offs;
+{
+ bus_space_tag_t bst = chp->ch_iot;
+ bus_space_handle_t bsh = chp->ch_ioh;
+ u_int8_t regv;
+
+ bus_space_write_1(bst, bsh, addr_port, offs);
+ CT_BUS_WEIGHT(chp)
+ regv = bus_space_read_1(bst, bsh, ctrl_port);
+ CT_BUS_WEIGHT(chp)
+ return regv;
+}
+
+static __inline void
+ct_cr_write_1(chp, offs, val)
+ struct ct_bus_access_handle *chp;
+ bus_addr_t offs;
+ u_int8_t val;
+{
+ bus_space_tag_t bst = chp->ch_iot;
+ bus_space_handle_t bsh = chp->ch_ioh;
+
+ bus_space_write_1(bst, bsh, addr_port, offs);
+ CT_BUS_WEIGHT(chp)
+ bus_space_write_1(bst, bsh, ctrl_port, val);
+ CT_BUS_WEIGHT(chp)
+}
+
+static __inline u_int8_t
+ct_cmdp_read_1(chp)
+ struct ct_bus_access_handle *chp;
+{
+ u_int8_t regv;
+
+ regv = bus_space_read_1(chp->ch_iot, chp->ch_ioh, cmd_port);
+ CT_BUS_WEIGHT(chp)
+ return regv;
+}
+
+static __inline void
+ct_cmdp_write_1(chp, val)
+ struct ct_bus_access_handle *chp;
+ u_int8_t val;
+{
+
+ bus_space_write_1(chp->ch_iot, chp->ch_ioh, cmd_port, val);
+ CT_BUS_WEIGHT(chp)
+}
+
+#if defined(__i386__) && 0
+#define SOFT_INTR_REQUIRED(slp) (softintr((slp)->sl_irq))
+#else /* !__i386__ */
+#define SOFT_INTR_REQUIRED(slp)
+#endif /* !__i386__ */
+#endif /* !_CT_MACHDEP_H_ */
diff --git a/sys/dev/ct/ctvar.h b/sys/dev/ct/ctvar.h
new file mode 100644
index 0000000..4e7ba15
--- /dev/null
+++ b/sys/dev/ct/ctvar.h
@@ -0,0 +1,145 @@
+/* $FreeBSD$ */
+/* $NecBSD: ctvar.h,v 1.4.14.3 2001/06/20 06:13:34 honda Exp $ */
+/* $NetBSD$ */
+
+/*
+ * [NetBSD for NEC PC-98 series]
+ * Copyright (c) 1995, 1996, 1997, 1998, 1999, 2000, 2001
+ * NetBSD/pc98 porting staff. All rights reserved.
+ * Copyright (c) 1995, 1996, 1997, 1998, 1999, 2000, 2001
+ * Naofumi HONDA. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _CTVAR_H_
+#define _CTVAR_H_
+/*
+ * ctvar.h
+ * Generic wd33c93 chip driver's definitions
+ */
+
+/*****************************************************************
+ * Host adapter structure
+ *****************************************************************/
+struct ct_bus_access_handle {
+ bus_space_tag_t ch_iot; /* core chip ctrl port tag */
+ bus_space_tag_t ch_delayt; /* delay port tag */
+ bus_space_tag_t ch_datat; /* data port tag (pio) */
+ bus_space_tag_t ch_memt; /* data port tag (shm) */
+
+ bus_space_handle_t ch_ioh;
+ bus_space_handle_t ch_delaybah;
+ bus_space_handle_t ch_datah;
+ bus_space_handle_t ch_memh;
+
+ void (*ch_bus_weight)(struct ct_bus_access_handle *);
+
+#ifdef CT_USE_RELOCATE_OFFSET
+ bus_addr_t ch_offset[4];
+#endif /* CT_USE_RELOCATE_OFFSET */
+};
+
+struct ct_softc {
+ struct scsi_low_softc sc_sclow; /* generic data */
+
+ struct ct_bus_access_handle sc_ch; /* bus access handle */
+
+#ifdef __NetBSD__
+ bus_dma_tag_t sc_dmat; /* data DMA tag */
+
+ void *sc_ih;
+#endif /* __NetBSD__ */
+
+#ifdef __FreeBSD__
+ struct resource *port_res;
+ struct resource *mem_res;
+ struct resource *irq_res;
+ struct resource *drq_res;
+
+ bus_dma_tag_t sc_dmat; /* data DMA tag */
+ bus_dmamap_t sc_dmamapt; /* data DMAMAP tag */
+
+ void *sc_ih;
+#endif /* __FreeBSD__ */
+
+ int sc_chiprev; /* chip version */
+#define CT_WD33C93 0x00000
+#define CT_WD33C93_A 0x10000
+#define CT_AM33C93_A 0x10001
+#define CT_WD33C93_B 0x20000
+#define CT_WD33C93_C 0x30000
+
+ int sc_xmode;
+#define CT_XMODE_PIO 1
+#define CT_XMODE_DMA 2
+
+ int sc_dma; /* dma transfer start */
+#define CT_DMA_PIOSTART 1
+#define CT_DMA_DMASTART 2
+
+ int sc_satgo; /* combination cmd start */
+#define CT_SAT_GOING 1
+
+ int sc_tmaxcnt;
+ int sc_atten; /* attention */
+ u_int8_t sc_creg; /* control register value */
+
+ int sc_chipclk; /* chipclk 0, 10, 15, 20 */
+ struct ct_synch_data {
+ u_int cs_period;
+ u_int cs_syncr;
+ } *sc_sdp; /* synchronous data table pt */
+
+ struct ct_synch_data sc_default_sdt[16];
+
+ /*
+ * Machdep stuff.
+ */
+ void *ct_hw; /* point to bshw_softc etc ... */
+ int (*ct_dma_xfer_start)(struct ct_softc *);
+ int (*ct_pio_xfer_start)(struct ct_softc *);
+ void (*ct_dma_xfer_stop)(struct ct_softc *);
+ void (*ct_pio_xfer_stop)(struct ct_softc *);
+ void (*ct_bus_reset)(struct ct_softc *);
+ void (*ct_synch_setup)(struct ct_softc *, struct targ_info *);
+};
+
+/*****************************************************************
+ * Lun information
+ *****************************************************************/
+struct ct_targ_info {
+ struct targ_info cti_ti;
+
+ u_int8_t cti_syncreg;
+};
+
+/*****************************************************************
+ * PROTO
+ *****************************************************************/
+int ctprobesubr(struct ct_bus_access_handle *, u_int, int, u_int, int *);
+void ctattachsubr(struct ct_softc *);
+int ctprint(void *, const char *);
+int ctintr(void *);
+#endif /* !_CTVAR_H_ */
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