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-rw-r--r--sys/dev/ata/ata-all.h102
1 files changed, 66 insertions, 36 deletions
diff --git a/sys/dev/ata/ata-all.h b/sys/dev/ata/ata-all.h
index 52d4348..7bb9189 100644
--- a/sys/dev/ata/ata-all.h
+++ b/sys/dev/ata/ata-all.h
@@ -109,7 +109,7 @@
#define ATA_S_READY 0x40 /* drive ready */
#define ATA_S_BUSY 0x80 /* busy */
-#define ATA_ALTSTAT 0x00 /* alternate status register */
+#define ATA_ALTSTAT 0x08 /* alternate status register */
#define ATA_ALTOFFSET 0x206 /* alternate registers offset */
#define ATA_PCCARD_ALTOFFSET 0x0e /* do for PCCARD devices */
#define ATA_PC98_ALTOFFSET 0x10c /* do for PC98 devices */
@@ -122,6 +122,7 @@
#define ATA_SECONDARY 0x170
#define ATA_PC98_BANK 0x432
#define ATA_IOSIZE 0x08
+#define ATA_PC98_IOSIZE 0x10
#define ATA_ALTIOSIZE 0x01
#define ATA_BMIOSIZE 0x08
#define ATA_PC98_BANKIOSIZE 0x01
@@ -129,7 +130,7 @@
#define ATA_OP_CONTINUES 0x01
#define ATA_IOADDR_RID 0
#define ATA_ALTADDR_RID 1
-#define ATA_BMADDR_RID 2
+#define ATA_BMADDR_RID 0x20
#define ATA_PC98_ALTADDR_RID 8
#define ATA_PC98_BANKADDR_RID 9
@@ -140,12 +141,12 @@
#define ATA_DMA_ENTRIES 256
#define ATA_DMA_EOT 0x80000000
-#define ATA_BMCMD_PORT 0x00
+#define ATA_BMCMD_PORT 0x09
#define ATA_BMCMD_START_STOP 0x01
#define ATA_BMCMD_WRITE_READ 0x08
-#define ATA_BMDEVSPEC_0 0x01
-#define ATA_BMSTAT_PORT 0x02
+#define ATA_BMDEVSPEC_0 0x0a
+#define ATA_BMSTAT_PORT 0x0b
#define ATA_BMSTAT_ACTIVE 0x01
#define ATA_BMSTAT_ERROR 0x02
#define ATA_BMSTAT_INTERRUPT 0x04
@@ -154,8 +155,10 @@
#define ATA_BMSTAT_DMA_SLAVE 0x40
#define ATA_BMSTAT_DMA_SIMPLEX 0x80
-#define ATA_BMDEVSPEC_1 0x03
-#define ATA_BMDTP_PORT 0x04
+#define ATA_BMDEVSPEC_1 0x0c
+#define ATA_BMDTP_PORT 0x0d
+
+#define ATA_MAX_RES 0x10
/* structure for holding DMA address data */
struct ata_dmaentry {
@@ -163,18 +166,6 @@ struct ata_dmaentry {
u_int32_t count;
};
-struct ata_dmastate {
- bus_dma_tag_t ddmatag; /* data DMA tag */
- bus_dmamap_t ddmamap; /* data DMA map */
- bus_dma_tag_t cdmatag; /* control DMA tag */
- bus_dmamap_t cdmamap; /* control DMA map */
- struct ata_dmaentry *dmatab; /* DMA transfer table */
- bus_addr_t mdmatab; /* bus address of dmatab */
- int flags; /* debugging */
-#define ATA_DS_ACTIVE 0x01 /* debugging */
-#define ATA_DS_READ 0x02 /* transaction is a read */
-};
-
/* structure describing an ATA/ATAPI device */
struct ata_device {
struct ata_channel *channel;
@@ -195,33 +186,44 @@ struct ata_device {
void *result; /* misc data */
int mode; /* transfermode */
void (*setmode)(struct ata_device *, int);
- struct ata_dmastate dmastate; /* dma state */
};
-/* structure holding DMA function pointers */
-struct ata_dma_funcs {
- void (*create)(struct ata_channel *);
- void (*destroy)(struct ata_channel *);
- int (*alloc)(struct ata_device *);
- void (*free)(struct ata_device *);
+/* structure holding DMA related information */
+struct ata_dma_data {
+ bus_dma_tag_t dmatag; /* parent DMA tag */
+ bus_dma_tag_t cdmatag; /* control DMA tag */
+ bus_dmamap_t cdmamap; /* control DMA map */
+ bus_dma_tag_t ddmatag; /* data DMA tag */
+ bus_dmamap_t ddmamap; /* data DMA map */
+ struct ata_dmaentry *dmatab; /* DMA transfer table */
+ bus_addr_t mdmatab; /* bus address of dmatab */
+ u_int32_t alignment; /* DMA engine alignment */
+ int flags;
+#define ATA_DMA_ACTIVE 0x01 /* DMA transfer in progress */
+#define ATA_DMA_READ 0x02 /* transaction is a read */
+
+ int (*alloc)(struct ata_channel *);
+ void (*free)(struct ata_channel *);
int (*setup)(struct ata_device *, caddr_t, int32_t);
- int (*start)(struct ata_device *, caddr_t, int32_t, int);
- int (*stop)(struct ata_device *);
+ int (*start)(struct ata_channel *, caddr_t, int32_t, int);
+ int (*stop)(struct ata_channel *);
int (*status)(struct ata_channel *);
- u_int32_t alignment; /* dma engine alignment */
+};
+
+/* structure holding resources for an ATA channel */
+struct ata_resource {
+ struct resource *res;
+ int offset;
};
/* structure describing an ATA channel */
struct ata_channel {
struct device *dev; /* device handle */
int unit; /* channel number */
- struct resource *r_io; /* io addr resource handle */
- struct resource *r_altio; /* altio addr resource handle */
- struct resource *r_bmio; /* bmio addr resource handle */
- bus_dma_tag_t dmatag; /* parent dma tag */
+ struct ata_resource r_io[ATA_MAX_RES];/* I/O resources */
struct resource *r_irq; /* interrupt of this channel */
void *ih; /* interrupt handle */
- struct ata_dma_funcs *dma; /* DMA functions */
+ struct ata_dma_data *dma; /* DMA data / functions */
u_int32_t chiptype; /* controller chip PCI id */
int flags; /* channel flags */
#define ATA_NO_SLAVE 0x01
@@ -229,8 +231,7 @@ struct ata_channel {
#define ATA_USE_PC98GEOM 0x04
#define ATA_ATAPI_DMA_RO 0x08
#define ATA_QUEUED 0x10
-#define ATA_DMA_ACTIVE 0x20
-#define ATA_48BIT_ACTIVE 0x40
+#define ATA_48BIT_ACTIVE 0x20
struct ata_device device[2]; /* devices on this channel */
#define MASTER 0x00
@@ -316,6 +317,7 @@ int ata_limit_mode(struct ata_device *, int, int);
#define ATA_INB(res, offset) \
bus_space_read_1(rman_get_bustag((res)), \
rman_get_bushandle((res)), (offset))
+
#define ATA_INW(res, offset) \
bus_space_read_2(rman_get_bustag((res)), \
rman_get_bushandle((res)), (offset))
@@ -363,3 +365,31 @@ int ata_limit_mode(struct ata_device *, int, int);
bus_space_write_multi_stream_4(rman_get_bustag((res)), \
rman_get_bushandle((res)), \
(offset), (addr), (count))
+#define ATA_IDX_INB(ch, idx) \
+ ATA_INB(ch->r_io[idx].res, ch->r_io[idx].offset)
+#define ATA_IDX_INW(ch, idx) \
+ ATA_INW(ch->r_io[idx].res, ch->r_io[idx].offset)
+#define ATA_IDX_INL(ch, idx) \
+ ATA_INL(ch->r_io[idx].res, ch->r_io[idx].offset)
+#define ATA_IDX_INSW(ch, idx, addr, count) \
+ ATA_INSW(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count)
+#define ATA_IDX_INSW_STRM(ch, idx, addr, count) \
+ ATA_INSW_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count)
+#define ATA_IDX_INSL(ch, idx, addr, count) \
+ ATA_INSL(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count)
+#define ATA_IDX_INSL_STRM(ch, idx, addr, count) \
+ ATA_INSL_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count)
+#define ATA_IDX_OUTB(ch, idx, value) \
+ ATA_OUTB(ch->r_io[idx].res, ch->r_io[idx].offset, value)
+#define ATA_IDX_OUTW(ch, idx, value) \
+ ATA_OUTW(ch->r_io[idx].res, ch->r_io[idx].offset, value)
+#define ATA_IDX_OUTL(ch, idx, value) \
+ ATA_OUTL(ch->r_io[idx].res, ch->r_io[idx].offset, value)
+#define ATA_IDX_OUTSW(ch, idx, addr, count) \
+ ATA_OUTSW(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count)
+#define ATA_IDX_OUTSW_STRM(ch, idx, addr, count) \
+ ATA_OUTSW_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count)
+#define ATA_IDX_OUTSL(ch, idx, addr, count) \
+ ATA_OUTSL(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count)
+#define ATA_IDX_OUTSL_STRM(ch, idx, addr, count) \
+ ATA_OUTSL_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count)
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