diff options
Diffstat (limited to 'sys/dev/arcmsr/arcmsr.h')
| -rw-r--r-- | sys/dev/arcmsr/arcmsr.h | 613 |
1 files changed, 397 insertions, 216 deletions
diff --git a/sys/dev/arcmsr/arcmsr.h b/sys/dev/arcmsr/arcmsr.h index ed8feb9..219372e 100644 --- a/sys/dev/arcmsr/arcmsr.h +++ b/sys/dev/arcmsr/arcmsr.h @@ -44,7 +44,7 @@ #define ARCMSR_MAX_TARGETLUN 8 /*8*/ #define ARCMSR_MAX_CHIPTYPE_NUM 4 #define ARCMSR_MAX_OUTSTANDING_CMD 256 -#define ARCMSR_MAX_START_JOB 257 +#define ARCMSR_MAX_START_JOB 256 #define ARCMSR_MAX_CMD_PERLUN ARCMSR_MAX_OUTSTANDING_CMD #define ARCMSR_MAX_FREESRB_NUM 384 #define ARCMSR_MAX_QBUFFER 4096 /* ioctl QBUFFER */ @@ -52,6 +52,7 @@ #define ARCMSR_MAX_ADAPTER 4 #define ARCMSR_RELEASE_SIMQ_LEVEL 230 #define ARCMSR_MAX_HBB_POSTQUEUE 264 /* (ARCMSR_MAX_OUTSTANDING_CMD+8) */ +#define ARCMSR_MAX_HBD_POSTQUEUE 256 #define ARCMSR_TIMEOUT_DELAY 60 /* in sec */ /* ********************************************************************* @@ -69,6 +70,25 @@ #ifndef offsetof #define offsetof(type, member) ((size_t)(&((type *)0)->member)) #endif + +#if __FreeBSD_version >= 500005 + #define ARCMSR_LOCK_INIT(l, s) mtx_init(l, s, NULL, MTX_DEF) + #define ARCMSR_LOCK_DESTROY(l) mtx_destroy(l) + #define ARCMSR_LOCK_ACQUIRE(l) mtx_lock(l) + #define ARCMSR_LOCK_RELEASE(l) mtx_unlock(l) + #define ARCMSR_LOCK_TRY(l) mtx_trylock(l) + #define arcmsr_htole32(x) htole32(x) + typedef struct mtx arcmsr_lock_t; +#else + #define ARCMSR_LOCK_INIT(l, s) simple_lock_init(l) + #define ARCMSR_LOCK_DESTROY(l) + #define ARCMSR_LOCK_ACQUIRE(l) simple_lock(l) + #define ARCMSR_LOCK_RELEASE(l) simple_unlock(l) + #define ARCMSR_LOCK_TRY(l) simple_lock_try(l) + #define arcmsr_htole32(x) (x) + typedef struct simplelock arcmsr_lock_t; +#endif + /* ********************************************************************************** ** @@ -84,6 +104,7 @@ #define PCI_DEVICE_ID_ARECA_1201 0x1201 /* Device ID */ #define PCI_DEVICE_ID_ARECA_1210 0x1210 /* Device ID */ #define PCI_DEVICE_ID_ARECA_1212 0x1212 /* Device ID */ +#define PCI_DEVICE_ID_ARECA_1214 0x1214 /* Device ID */ #define PCI_DEVICE_ID_ARECA_1220 0x1220 /* Device ID */ #define PCI_DEVICE_ID_ARECA_1222 0x1222 /* Device ID */ #define PCI_DEVICE_ID_ARECA_1230 0x1230 /* Device ID */ @@ -115,6 +136,7 @@ #define PCIDevVenIDARC1210 0x121017D3 /* Vendor Device ID */ #define PCIDevVenIDARC1212 0x121217D3 /* Vendor Device ID */ #define PCIDevVenIDARC1213 0x121317D3 /* Vendor Device ID */ +#define PCIDevVenIDARC1214 0x121417D3 /* Vendor Device ID */ #define PCIDevVenIDARC1220 0x122017D3 /* Vendor Device ID */ #define PCIDevVenIDARC1222 0x122217D3 /* Vendor Device ID */ #define PCIDevVenIDARC1223 0x122317D3 /* Vendor Device ID */ @@ -163,8 +185,14 @@ #define get_min(x,y) ((x) < (y) ? (x) : (y)) #define get_max(x,y) ((x) < (y) ? (y) : (x)) /* +************************************************************************** +************************************************************************** +*/ +#define CHIP_REG_READ32(s, b, r) bus_space_read_4(acb->btag[b], acb->bhandle[b], offsetof(struct s, r)) +#define CHIP_REG_WRITE32(s, b, r, d) bus_space_write_4(acb->btag[b], acb->bhandle[b], offsetof(struct s, r), d) +/* ********************************************************************************** -** +** IOCTL CONTROL Mail Box ********************************************************************************** */ struct CMD_MESSAGE { @@ -211,7 +239,7 @@ struct CMD_MESSAGE_FIELD { #define FUNCTION_FLUSH_ADAPTER_CACHE 0x0809 /* ************************************************************************ -** IOCTL CONTROL CODE +** IOCTL CONTROL CODE ************************************************************************ */ /* ARECA IO CONTROL CODE*/ @@ -232,6 +260,40 @@ struct CMD_MESSAGE_FIELD { #define ARCMSR_IOCTL_RETURNCODE_BUS_HANG_ON 0x00000088 /* ************************************************************************ +** SPEC. for Areca HBA adapter +************************************************************************ +*/ +/* signature of set and get firmware config */ +#define ARCMSR_SIGNATURE_GET_CONFIG 0x87974060 +#define ARCMSR_SIGNATURE_SET_CONFIG 0x87974063 +/* message code of inbound message register */ +#define ARCMSR_INBOUND_MESG0_NOP 0x00000000 +#define ARCMSR_INBOUND_MESG0_GET_CONFIG 0x00000001 +#define ARCMSR_INBOUND_MESG0_SET_CONFIG 0x00000002 +#define ARCMSR_INBOUND_MESG0_ABORT_CMD 0x00000003 +#define ARCMSR_INBOUND_MESG0_STOP_BGRB 0x00000004 +#define ARCMSR_INBOUND_MESG0_FLUSH_CACHE 0x00000005 +#define ARCMSR_INBOUND_MESG0_START_BGRB 0x00000006 +#define ARCMSR_INBOUND_MESG0_CHK331PENDING 0x00000007 +#define ARCMSR_INBOUND_MESG0_SYNC_TIMER 0x00000008 +/* doorbell interrupt generator */ +#define ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK 0x00000001 +#define ARCMSR_INBOUND_DRIVER_DATA_READ_OK 0x00000002 +#define ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK 0x00000001 +#define ARCMSR_OUTBOUND_IOP331_DATA_READ_OK 0x00000002 +/* srb areca cdb flag */ +#define ARCMSR_SRBPOST_FLAG_SGL_BSIZE 0x80000000 +#define ARCMSR_SRBPOST_FLAG_IAM_BIOS 0x40000000 +#define ARCMSR_SRBREPLY_FLAG_IAM_BIOS 0x40000000 +#define ARCMSR_SRBREPLY_FLAG_ERROR 0x10000000 +#define ARCMSR_SRBREPLY_FLAG_ERROR_MODE0 0x10000000 +#define ARCMSR_SRBREPLY_FLAG_ERROR_MODE1 0x00000001 +/* outbound firmware ok */ +#define ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK 0x80000000 + +#define ARCMSR_ARC1680_BUS_RESET 0x00000003 +/* +************************************************************************ ** SPEC. for Areca HBB adapter ************************************************************************ */ @@ -324,7 +386,303 @@ struct CMD_MESSAGE_FIELD { #define ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE 0x00000008/*outbound message 0 ready*/ #define ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR 0x00000008/*outbound message cmd isr door bell clear*/ #define ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK 0x80000000/*ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK*/ +#define ARCMSR_HBCMU_RESET_ADAPTER 0x00000024 +#define ARCMSR_HBCMU_DiagWrite_ENABLE 0x00000080 + +/* +************************************************************************ +** SPEC. for Areca HBD adapter +************************************************************************ +*/ +#define ARCMSR_HBDMU_CHIP_ID 0x00004 +#define ARCMSR_HBDMU_CPU_MEMORY_CONFIGURATION 0x00008 +#define ARCMSR_HBDMU_I2_HOST_INTERRUPT_MASK 0x00034 +#define ARCMSR_HBDMU_MAIN_INTERRUPT_STATUS 0x00200 +#define ARCMSR_HBDMU_PCIE_F0_INTERRUPT_ENABLE 0x0020C +#define ARCMSR_HBDMU_INBOUND_MESSAGE0 0x00400 +#define ARCMSR_HBDMU_INBOUND_MESSAGE1 0x00404 +#define ARCMSR_HBDMU_OUTBOUND_MESSAGE0 0x00420 +#define ARCMSR_HBDMU_OUTBOUND_MESSAGE1 0x00424 +#define ARCMSR_HBDMU_INBOUND_DOORBELL 0x00460 +#define ARCMSR_HBDMU_OUTBOUND_DOORBELL 0x00480 +#define ARCMSR_HBDMU_OUTBOUND_DOORBELL_ENABLE 0x00484 +#define ARCMSR_HBDMU_INBOUND_LIST_BASE_LOW 0x01000 +#define ARCMSR_HBDMU_INBOUND_LIST_BASE_HIGH 0x01004 +#define ARCMSR_HBDMU_INBOUND_LIST_WRITE_POINTER 0x01018 +#define ARCMSR_HBDMU_OUTBOUND_LIST_BASE_LOW 0x01060 +#define ARCMSR_HBDMU_OUTBOUND_LIST_BASE_HIGH 0x01064 +#define ARCMSR_HBDMU_OUTBOUND_LIST_COPY_POINTER 0x0106C +#define ARCMSR_HBDMU_OUTBOUND_LIST_READ_POINTER 0x01070 +#define ARCMSR_HBDMU_OUTBOUND_INTERRUPT_CAUSE 0x01088 +#define ARCMSR_HBDMU_OUTBOUND_INTERRUPT_ENABLE 0x0108C + +#define ARCMSR_HBDMU_MESSAGE_WBUFFER 0x02000 +#define ARCMSR_HBDMU_MESSAGE_RBUFFER 0x02100 +#define ARCMSR_HBDMU_MESSAGE_RWBUFFER 0x02200 + +#define ARCMSR_HBDMU_ISR_THROTTLING_LEVEL 16 +#define ARCMSR_HBDMU_ISR_MAX_DONE_QUEUE 20 + +/* Host Interrupt Mask */ +#define ARCMSR_HBDMU_ALL_INT_ENABLE 0x00001010 /* enable all ISR */ +#define ARCMSR_HBDMU_ALL_INT_DISABLE 0x00000000 /* disable all ISR */ + +/* Host Interrupt Status */ +#define ARCMSR_HBDMU_OUTBOUND_INT 0x00001010 +#define ARCMSR_HBDMU_OUTBOUND_DOORBELL_INT 0x00001000 +#define ARCMSR_HBDMU_OUTBOUND_POSTQUEUE_INT 0x00000010 + +/* DoorBell*/ +#define ARCMSR_HBDMU_DRV2IOP_DATA_IN_READY 0x00000001 +#define ARCMSR_HBDMU_DRV2IOP_DATA_OUT_READ 0x00000002 + +#define ARCMSR_HBDMU_IOP2DRV_DATA_WRITE_OK 0x00000001 +#define ARCMSR_HBDMU_IOP2DRV_DATA_READ_OK 0x00000002 + +/*outbound message 0 ready*/ +#define ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE 0x02000000 + +#define ARCMSR_HBDMU_F0_DOORBELL_CAUSE 0x02000003 + +/*outbound message cmd isr door bell clear*/ +#define ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR 0x02000000 + +/*outbound list */ +#define ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT 0x00000001 +#define ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT_CLEAR 0x00000001 + +/*ARCMSR_HBAMU_MESSAGE_FIRMWARE_OK*/ +#define ARCMSR_HBDMU_MESSAGE_FIRMWARE_OK 0x80000000 +/* +********************************************************************* +** Message Unit structure +********************************************************************* +*/ +struct HBA_MessageUnit +{ + u_int32_t resrved0[4]; /*0000 000F*/ + u_int32_t inbound_msgaddr0; /*0010 0013*/ + u_int32_t inbound_msgaddr1; /*0014 0017*/ + u_int32_t outbound_msgaddr0; /*0018 001B*/ + u_int32_t outbound_msgaddr1; /*001C 001F*/ + u_int32_t inbound_doorbell; /*0020 0023*/ + u_int32_t inbound_intstatus; /*0024 0027*/ + u_int32_t inbound_intmask; /*0028 002B*/ + u_int32_t outbound_doorbell; /*002C 002F*/ + u_int32_t outbound_intstatus; /*0030 0033*/ + u_int32_t outbound_intmask; /*0034 0037*/ + u_int32_t reserved1[2]; /*0038 003F*/ + u_int32_t inbound_queueport; /*0040 0043*/ + u_int32_t outbound_queueport; /*0044 0047*/ + u_int32_t reserved2[2]; /*0048 004F*/ + u_int32_t reserved3[492]; /*0050 07FF ......local_buffer 492*/ + u_int32_t reserved4[128]; /*0800 09FF 128*/ + u_int32_t msgcode_rwbuffer[256]; /*0a00 0DFF 256*/ + u_int32_t message_wbuffer[32]; /*0E00 0E7F 32*/ + u_int32_t reserved5[32]; /*0E80 0EFF 32*/ + u_int32_t message_rbuffer[32]; /*0F00 0F7F 32*/ + u_int32_t reserved6[32]; /*0F80 0FFF 32*/ +}; +/* +********************************************************************* +** +********************************************************************* +*/ +struct HBB_DOORBELL +{ + u_int8_t doorbell_reserved[ARCMSR_DRV2IOP_DOORBELL]; /*reserved */ + u_int32_t drv2iop_doorbell; /*offset 0x00020400:00,01,02,03: window of "instruction flags" from driver to iop */ + u_int32_t drv2iop_doorbell_mask; /* 04,05,06,07: doorbell mask */ + u_int32_t iop2drv_doorbell; /* 08,09,10,11: window of "instruction flags" from iop to driver */ + u_int32_t iop2drv_doorbell_mask; /* 12,13,14,15: doorbell mask */ +}; +/* +********************************************************************* +** +********************************************************************* +*/ +struct HBB_RWBUFFER +{ + u_int8_t message_reserved0[ARCMSR_MSGCODE_RWBUFFER]; /*reserved */ + u_int32_t msgcode_rwbuffer[256]; /*offset 0x0000fa00: 0, 1, 2, 3,...,1023: message code read write 1024bytes */ + u_int32_t message_wbuffer[32]; /*offset 0x0000fe00:1024,1025,1026,1027,...,1151: user space data to iop 128bytes */ + u_int32_t message_reserved1[32]; /* 1152,1153,1154,1155,...,1279: message reserved*/ + u_int32_t message_rbuffer[32]; /*offset 0x0000ff00:1280,1281,1282,1283,...,1407: iop data to user space 128bytes */ +}; +/* +********************************************************************* +** +********************************************************************* +*/ +struct HBB_MessageUnit +{ + u_int32_t post_qbuffer[ARCMSR_MAX_HBB_POSTQUEUE]; /* post queue buffer for iop */ + u_int32_t done_qbuffer[ARCMSR_MAX_HBB_POSTQUEUE]; /* done queue buffer for iop */ + int32_t postq_index; /* post queue index */ + int32_t doneq_index; /* done queue index */ + struct HBB_DOORBELL *hbb_doorbell; + struct HBB_RWBUFFER *hbb_rwbuffer; +}; +/* +********************************************************************* +** +********************************************************************* +*/ +struct HBC_MessageUnit { + u_int32_t message_unit_status; /*0000 0003*/ + u_int32_t slave_error_attribute; /*0004 0007*/ + u_int32_t slave_error_address; /*0008 000B*/ + u_int32_t posted_outbound_doorbell; /*000C 000F*/ + u_int32_t master_error_attribute; /*0010 0013*/ + u_int32_t master_error_address_low; /*0014 0017*/ + u_int32_t master_error_address_high; /*0018 001B*/ + u_int32_t hcb_size; /*001C 001F size of the PCIe window used for HCB_Mode accesses*/ + u_int32_t inbound_doorbell; /*0020 0023*/ + u_int32_t diagnostic_rw_data; /*0024 0027*/ + u_int32_t diagnostic_rw_address_low; /*0028 002B*/ + u_int32_t diagnostic_rw_address_high; /*002C 002F*/ + u_int32_t host_int_status; /*0030 0033 host interrupt status*/ + u_int32_t host_int_mask; /*0034 0037 host interrupt mask*/ + u_int32_t dcr_data; /*0038 003B*/ + u_int32_t dcr_address; /*003C 003F*/ + u_int32_t inbound_queueport; /*0040 0043 port32 host inbound queue port*/ + u_int32_t outbound_queueport; /*0044 0047 port32 host outbound queue port*/ + u_int32_t hcb_pci_address_low; /*0048 004B*/ + u_int32_t hcb_pci_address_high; /*004C 004F*/ + u_int32_t iop_int_status; /*0050 0053*/ + u_int32_t iop_int_mask; /*0054 0057*/ + u_int32_t iop_inbound_queue_port; /*0058 005B*/ + u_int32_t iop_outbound_queue_port; /*005C 005F*/ + u_int32_t inbound_free_list_index; /*0060 0063 inbound free list producer consumer index*/ + u_int32_t inbound_post_list_index; /*0064 0067 inbound post list producer consumer index*/ + u_int32_t outbound_free_list_index; /*0068 006B outbound free list producer consumer index*/ + u_int32_t outbound_post_list_index; /*006C 006F outbound post list producer consumer index*/ + u_int32_t inbound_doorbell_clear; /*0070 0073*/ + u_int32_t i2o_message_unit_control; /*0074 0077*/ + u_int32_t last_used_message_source_address_low; /*0078 007B*/ + u_int32_t last_used_message_source_address_high; /*007C 007F*/ + u_int32_t pull_mode_data_byte_count[4]; /*0080 008F pull mode data byte count0..count7*/ + u_int32_t message_dest_address_index; /*0090 0093*/ + u_int32_t done_queue_not_empty_int_counter_timer; /*0094 0097*/ + u_int32_t utility_A_int_counter_timer; /*0098 009B*/ + u_int32_t outbound_doorbell; /*009C 009F*/ + u_int32_t outbound_doorbell_clear; /*00A0 00A3*/ + u_int32_t message_source_address_index; /*00A4 00A7 message accelerator source address consumer producer index*/ + u_int32_t message_done_queue_index; /*00A8 00AB message accelerator completion queue consumer producer index*/ + u_int32_t reserved0; /*00AC 00AF*/ + u_int32_t inbound_msgaddr0; /*00B0 00B3 scratchpad0*/ + u_int32_t inbound_msgaddr1; /*00B4 00B7 scratchpad1*/ + u_int32_t outbound_msgaddr0; /*00B8 00BB scratchpad2*/ + u_int32_t outbound_msgaddr1; /*00BC 00BF scratchpad3*/ + u_int32_t inbound_queueport_low; /*00C0 00C3 port64 host inbound queue port low*/ + u_int32_t inbound_queueport_high; /*00C4 00C7 port64 host inbound queue port high*/ + u_int32_t outbound_queueport_low; /*00C8 00CB port64 host outbound queue port low*/ + u_int32_t outbound_queueport_high; /*00CC 00CF port64 host outbound queue port high*/ + u_int32_t iop_inbound_queue_port_low; /*00D0 00D3*/ + u_int32_t iop_inbound_queue_port_high; /*00D4 00D7*/ + u_int32_t iop_outbound_queue_port_low; /*00D8 00DB*/ + u_int32_t iop_outbound_queue_port_high; /*00DC 00DF*/ + u_int32_t message_dest_queue_port_low; /*00E0 00E3 message accelerator destination queue port low*/ + u_int32_t message_dest_queue_port_high; /*00E4 00E7 message accelerator destination queue port high*/ + u_int32_t last_used_message_dest_address_low; /*00E8 00EB last used message accelerator destination address low*/ + u_int32_t last_used_message_dest_address_high; /*00EC 00EF last used message accelerator destination address high*/ + u_int32_t message_done_queue_base_address_low; /*00F0 00F3 message accelerator completion queue base address low*/ + u_int32_t message_done_queue_base_address_high; /*00F4 00F7 message accelerator completion queue base address high*/ + u_int32_t host_diagnostic; /*00F8 00FB*/ + u_int32_t write_sequence; /*00FC 00FF*/ + u_int32_t reserved1[34]; /*0100 0187*/ + u_int32_t reserved2[1950]; /*0188 1FFF*/ + u_int32_t message_wbuffer[32]; /*2000 207F*/ + u_int32_t reserved3[32]; /*2080 20FF*/ + u_int32_t message_rbuffer[32]; /*2100 217F*/ + u_int32_t reserved4[32]; /*2180 21FF*/ + u_int32_t msgcode_rwbuffer[256]; /*2200 23FF*/ +}; +/* +********************************************************************* +** +********************************************************************* +*/ +struct InBound_SRB { + uint32_t addressLow; //pointer to SRB block + uint32_t addressHigh; + uint32_t length; // in DWORDs + uint32_t reserved0; +}; + +struct OutBound_SRB { + uint32_t addressLow; //pointer to SRB block + uint32_t addressHigh; +}; + +struct HBD_MessageUnit { + uint32_t reserved0; + uint32_t chip_id; //0x0004 + uint32_t cpu_mem_config; //0x0008 + uint32_t reserved1[10]; //0x000C + uint32_t i2o_host_interrupt_mask; //0x0034 + uint32_t reserved2[114]; //0x0038 + uint32_t host_int_status; //0x0200 + uint32_t host_int_enable; //0x0204 + uint32_t reserved3[1]; //0x0208 + uint32_t pcief0_int_enable; //0x020C + uint32_t reserved4[124]; //0x0210 + uint32_t inbound_msgaddr0; //0x0400 + uint32_t inbound_msgaddr1; //0x0404 + uint32_t reserved5[6]; //0x0408 + uint32_t outbound_msgaddr0; //0x0420 + uint32_t outbound_msgaddr1; //0x0424 + uint32_t reserved6[14]; //0x0428 + uint32_t inbound_doorbell; //0x0460 + uint32_t reserved7[7]; //0x0464 + uint32_t outbound_doorbell; //0x0480 + uint32_t outbound_doorbell_enable; //0x0484 + uint32_t reserved8[734]; //0x0488 + uint32_t inboundlist_base_low; //0x1000 + uint32_t inboundlist_base_high; //0x1004 + uint32_t reserved9[4]; //0x1008 + uint32_t inboundlist_write_pointer; //0x1018 + uint32_t inboundlist_read_pointer; //0x101C + uint32_t reserved10[16]; //0x1020 + uint32_t outboundlist_base_low; //0x1060 + uint32_t outboundlist_base_high; //0x1064 + uint32_t reserved11; //0x1068 + uint32_t outboundlist_copy_pointer; //0x106C + uint32_t outboundlist_read_pointer; //0x1070 0x1072 + uint32_t reserved12[5]; //0x1074 + uint32_t outboundlist_interrupt_cause; //0x1088 + uint32_t outboundlist_interrupt_enable; //0x108C + uint32_t reserved13[988]; //0x1090 + uint32_t message_wbuffer[32]; //0x2000 + uint32_t reserved14[32]; //0x2080 + uint32_t message_rbuffer[32]; //0x2100 + uint32_t reserved15[32]; //0x2180 + uint32_t msgcode_rwbuffer[256]; //0x2200 +}; + +struct HBD_MessageUnit0 { + struct InBound_SRB post_qbuffer[ARCMSR_MAX_HBD_POSTQUEUE]; + struct OutBound_SRB done_qbuffer[ARCMSR_MAX_HBD_POSTQUEUE+1]; + uint16_t postq_index; + uint16_t doneq_index; + struct HBD_MessageUnit *phbdmu; +}; + +/* +********************************************************************* +** +********************************************************************* +*/ +struct MessageUnit_UNION +{ + union { + struct HBA_MessageUnit hbamu; + struct HBB_MessageUnit hbbmu; + struct HBC_MessageUnit hbcmu; + struct HBD_MessageUnit0 hbdmu; + } muu; +}; /* ************************************************************* ** structure for holding DMA address data @@ -543,38 +901,8 @@ struct CMD_MESSAGE_FIELD { ** LSI2108 support I/O register ** All driver functionality is supported through I/O address ** -** For further spec, refer to -** \spec\lsi\2108 for Areca\2108\LSISAS2108_PG_NoEncryption.pdf : Chapter 8 (8-11/8-28) -** \spec\lsi\2108 for Areca\2108\SAS2108_RM_20.pdf : for configuration space ************************************************************************************************ */ -/* signature of set and get firmware config */ -#define ARCMSR_SIGNATURE_GET_CONFIG 0x87974060 -#define ARCMSR_SIGNATURE_SET_CONFIG 0x87974063 -/* message code of inbound message register */ -#define ARCMSR_INBOUND_MESG0_NOP 0x00000000 -#define ARCMSR_INBOUND_MESG0_GET_CONFIG 0x00000001 -#define ARCMSR_INBOUND_MESG0_SET_CONFIG 0x00000002 -#define ARCMSR_INBOUND_MESG0_ABORT_CMD 0x00000003 -#define ARCMSR_INBOUND_MESG0_STOP_BGRB 0x00000004 -#define ARCMSR_INBOUND_MESG0_FLUSH_CACHE 0x00000005 -#define ARCMSR_INBOUND_MESG0_START_BGRB 0x00000006 -#define ARCMSR_INBOUND_MESG0_CHK331PENDING 0x00000007 -#define ARCMSR_INBOUND_MESG0_SYNC_TIMER 0x00000008 -/* doorbell interrupt generator */ -#define ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK 0x00000001 -#define ARCMSR_INBOUND_DRIVER_DATA_READ_OK 0x00000002 -#define ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK 0x00000001 -#define ARCMSR_OUTBOUND_IOP331_DATA_READ_OK 0x00000002 -/* srb areca cdb flag */ -#define ARCMSR_SRBPOST_FLAG_SGL_BSIZE 0x80000000 -#define ARCMSR_SRBPOST_FLAG_IAM_BIOS 0x40000000 -#define ARCMSR_SRBREPLY_FLAG_IAM_BIOS 0x40000000 -#define ARCMSR_SRBREPLY_FLAG_ERROR 0x10000000 -#define ARCMSR_SRBREPLY_FLAG_ERROR_MODE0 0x10000000 -#define ARCMSR_SRBREPLY_FLAG_ERROR_MODE1 0x00000001 -/* outbound firmware ok */ -#define ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK 0x80000000 /* ********************************** ** @@ -609,6 +937,13 @@ struct QBUFFER { u_int8_t data[124]; }; /* +********************************** +*/ +typedef struct PHYS_ADDR64 { + u_int32_t phyadd_low; + u_int32_t phyadd_high; +}PHYSADDR64; +/* ************************************************************************************************ ** FIRMWARE INFO ************************************************************************************************ @@ -673,12 +1008,6 @@ struct ARCMSR_CDB { u_int8_t CdbLength; /* 04h not used now */ u_int8_t sgcount; /* 05h */ u_int8_t Flags; /* 06h */ -#define ARCMSR_CDB_FLAG_SGL_BSIZE 0x01 /* bit 0: 0(256) / 1(512) bytes */ -#define ARCMSR_CDB_FLAG_BIOS 0x02 /* bit 1: 0(from driver) / 1(from BIOS) */ -#define ARCMSR_CDB_FLAG_WRITE 0x04 /* bit 2: 0(Data in) / 1(Data out) */ -#define ARCMSR_CDB_FLAG_SIMPLEQ 0x00 /* bit 4/3 ,00 : simple Q,01 : head of Q,10 : ordered Q */ -#define ARCMSR_CDB_FLAG_HEADQ 0x08 -#define ARCMSR_CDB_FLAG_ORDEREDQ 0x10 u_int8_t msgPages; /* 07h */ u_int32_t Context; /* 08h Address of this request */ @@ -687,11 +1016,27 @@ struct ARCMSR_CDB { u_int8_t Cdb[16]; /* 10h SCSI CDB */ /* ******************************************************** - **Device Status : the same from SCSI bus if error occur + ** Device Status : the same from SCSI bus if error occur ** SCSI bus status codes. ******************************************************** */ u_int8_t DeviceStatus; /* 20h if error */ + + u_int8_t SenseData[15]; /* 21h output */ + + union { + struct SG32ENTRY sg32entry[ARCMSR_MAX_SG_ENTRIES]; /* 30h Scatter gather address */ + struct SG64ENTRY sg64entry[ARCMSR_MAX_SG_ENTRIES]; /* 30h */ + } u; +}; +/* CDB flag */ +#define ARCMSR_CDB_FLAG_SGL_BSIZE 0x01 /* bit 0: 0(256) / 1(512) bytes */ +#define ARCMSR_CDB_FLAG_BIOS 0x02 /* bit 1: 0(from driver) / 1(from BIOS) */ +#define ARCMSR_CDB_FLAG_WRITE 0x04 /* bit 2: 0(Data in) / 1(Data out) */ +#define ARCMSR_CDB_FLAG_SIMPLEQ 0x00 /* bit 4/3 ,00 : simple Q,01 : head of Q,10 : ordered Q */ +#define ARCMSR_CDB_FLAG_HEADQ 0x08 +#define ARCMSR_CDB_FLAG_ORDEREDQ 0x10 +/* scsi status */ #define SCSISTAT_GOOD 0x00 #define SCSISTAT_CHECK_CONDITION 0x02 #define SCSISTAT_CONDITION_MET 0x04 @@ -701,17 +1046,10 @@ struct ARCMSR_CDB { #define SCSISTAT_RESERVATION_CONFLICT 0x18 #define SCSISTAT_COMMAND_TERMINATED 0x22 #define SCSISTAT_QUEUE_FULL 0x28 +/* DeviceStatus */ #define ARCMSR_DEV_SELECT_TIMEOUT 0xF0 #define ARCMSR_DEV_ABORTED 0xF1 #define ARCMSR_DEV_INIT_FAIL 0xF2 - - u_int8_t SenseData[15]; /* 21h output */ - - union { - struct SG32ENTRY sg32entry[ARCMSR_MAX_SG_ENTRIES]; /* 30h Scatter gather address */ - struct SG64ENTRY sg64entry[ARCMSR_MAX_SG_ENTRIES]; /* 30h */ - } u; -}; /* ********************************************************************* ** Command Control Block (SrbExtension) @@ -722,14 +1060,15 @@ struct ARCMSR_CDB { */ struct CommandControlBlock { struct ARCMSR_CDB arcmsr_cdb; /* 0 -503 (size of CDB=504): arcmsr messenger scsi command descriptor size 504 bytes */ - u_int32_t cdb_shifted_phyaddr; /* 504-507 */ + u_int32_t cdb_phyaddr_low; /* 504-507 */ u_int32_t arc_cdb_size; /* 508-511 */ /* ======================512+32 bytes============================ */ union ccb *pccb; /* 512-515 516-519 pointer of freebsd scsi command */ struct AdapterControlBlock *acb; /* 520-523 524-527 */ bus_dmamap_t dm_segs_dmamap; /* 528-531 532-535 */ u_int16_t srb_flags; /* 536-537 */ - u_int16_t srb_state; /* 538-539 */ + u_int16_t srb_state; /* 538-539 */ + u_int32_t cdb_phyaddr_high; /* 540-543 */ struct callout ccb_callout; /* ========================================================== */ }; @@ -754,6 +1093,10 @@ struct CommandControlBlock { #define ARCMSR_SRB_RESET 0xA5A5 #define ARCMSR_SRB_ABORTED 0x5A5A #define ARCMSR_SRB_ILLEGAL 0xFFFF + +#define SRB_SIZE ((sizeof(struct CommandControlBlock)+0x1f) & 0xffe0) +#define ARCMSR_SRBS_POOL_SIZE (SRB_SIZE * ARCMSR_MAX_FREESRB_NUM) + /* ********************************************************************* ** Adapter Control Block @@ -762,7 +1105,7 @@ struct CommandControlBlock { #define ACB_ADAPTER_TYPE_A 0x00000001 /* hba I IOP */ #define ACB_ADAPTER_TYPE_B 0x00000002 /* hbb M IOP */ #define ACB_ADAPTER_TYPE_C 0x00000004 /* hbc L IOP */ -#define ACB_ADAPTER_TYPE_D 0x00000008 /* hbd A IOP */ +#define ACB_ADAPTER_TYPE_D 0x00000008 /* hbd M IOP */ struct AdapterControlBlock { u_int32_t adapter_type; /* adapter A,B..... */ @@ -821,8 +1164,9 @@ struct AdapterControlBlock { u_int32_t wqbuf_firstindex; /* first of write buffer */ u_int32_t wqbuf_lastindex; /* last of write buffer */ - arcmsr_lock_t workingQ_done_lock; - arcmsr_lock_t workingQ_start_lock; + arcmsr_lock_t isr_lock; + arcmsr_lock_t srb_lock; + arcmsr_lock_t postDone_lock; arcmsr_lock_t qbuffer_lock; u_int8_t devstate[ARCMSR_MAX_TARGETID][ARCMSR_MAX_TARGETLUN]; /* id0 ..... id15,lun0...lun7 */ @@ -837,10 +1181,8 @@ struct AdapterControlBlock { char firm_version[20]; /*17,68-83*/ char device_map[20]; /*21,84-99 */ struct callout devmap_callout; -#ifdef ARCMSR_DEBUG1 u_int32_t pktRequestCount; u_int32_t pktReturnCount; -#endif u_int32_t vendor_device_id; u_int32_t adapter_bus_speed; };/* HW_DEVICE_EXTENSION */ @@ -866,167 +1208,6 @@ struct AdapterControlBlock { #define ACB_BUS_SPEED_6G 1 #define ACB_BUS_SPEED_12G 2 /* -********************************************************************* -** Message Unit structure -********************************************************************* -*/ -struct HBA_MessageUnit -{ - u_int32_t resrved0[4]; /*0000 000F*/ - u_int32_t inbound_msgaddr0; /*0010 0013*/ - u_int32_t inbound_msgaddr1; /*0014 0017*/ - u_int32_t outbound_msgaddr0; /*0018 001B*/ - u_int32_t outbound_msgaddr1; /*001C 001F*/ - u_int32_t inbound_doorbell; /*0020 0023*/ - u_int32_t inbound_intstatus; /*0024 0027*/ - u_int32_t inbound_intmask; /*0028 002B*/ - u_int32_t outbound_doorbell; /*002C 002F*/ - u_int32_t outbound_intstatus; /*0030 0033*/ - u_int32_t outbound_intmask; /*0034 0037*/ - u_int32_t reserved1[2]; /*0038 003F*/ - u_int32_t inbound_queueport; /*0040 0043*/ - u_int32_t outbound_queueport; /*0044 0047*/ - u_int32_t reserved2[2]; /*0048 004F*/ - u_int32_t reserved3[492]; /*0050 07FF ......local_buffer 492*/ - u_int32_t reserved4[128]; /*0800 09FF 128*/ - u_int32_t msgcode_rwbuffer[256]; /*0a00 0DFF 256*/ - u_int32_t message_wbuffer[32]; /*0E00 0E7F 32*/ - u_int32_t reserved5[32]; /*0E80 0EFF 32*/ - u_int32_t message_rbuffer[32]; /*0F00 0F7F 32*/ - u_int32_t reserved6[32]; /*0F80 0FFF 32*/ -}; -/* -********************************************************************* -** -********************************************************************* -*/ -struct HBB_DOORBELL -{ - u_int8_t doorbell_reserved[ARCMSR_DRV2IOP_DOORBELL]; /*reserved */ - u_int32_t drv2iop_doorbell; /*offset 0x00020400:00,01,02,03: window of "instruction flags" from driver to iop */ - u_int32_t drv2iop_doorbell_mask; /* 04,05,06,07: doorbell mask */ - u_int32_t iop2drv_doorbell; /* 08,09,10,11: window of "instruction flags" from iop to driver */ - u_int32_t iop2drv_doorbell_mask; /* 12,13,14,15: doorbell mask */ -}; -/* -********************************************************************* -** -********************************************************************* -*/ -struct HBB_RWBUFFER -{ - u_int8_t message_reserved0[ARCMSR_MSGCODE_RWBUFFER]; /*reserved */ - u_int32_t msgcode_rwbuffer[256]; /*offset 0x0000fa00: 0, 1, 2, 3,...,1023: message code read write 1024bytes */ - u_int32_t message_wbuffer[32]; /*offset 0x0000fe00:1024,1025,1026,1027,...,1151: user space data to iop 128bytes */ - u_int32_t message_reserved1[32]; /* 1152,1153,1154,1155,...,1279: message reserved*/ - u_int32_t message_rbuffer[32]; /*offset 0x0000ff00:1280,1281,1282,1283,...,1407: iop data to user space 128bytes */ -}; -/* -********************************************************************* -** -********************************************************************* -*/ -struct HBB_MessageUnit -{ - u_int32_t post_qbuffer[ARCMSR_MAX_HBB_POSTQUEUE]; /* post queue buffer for iop */ - u_int32_t done_qbuffer[ARCMSR_MAX_HBB_POSTQUEUE]; /* done queue buffer for iop */ - int32_t postq_index; /* post queue index */ - int32_t doneq_index; /* done queue index */ - struct HBB_DOORBELL *hbb_doorbell; - struct HBB_RWBUFFER *hbb_rwbuffer; -}; - -/* -********************************************************************* -** -********************************************************************* -*/ -struct HBC_MessageUnit { - u_int32_t message_unit_status; /*0000 0003*/ - u_int32_t slave_error_attribute; /*0004 0007*/ - u_int32_t slave_error_address; /*0008 000B*/ - u_int32_t posted_outbound_doorbell; /*000C 000F*/ - u_int32_t master_error_attribute; /*0010 0013*/ - u_int32_t master_error_address_low; /*0014 0017*/ - u_int32_t master_error_address_high; /*0018 001B*/ - u_int32_t hcb_size; /*001C 001F size of the PCIe window used for HCB_Mode accesses*/ - u_int32_t inbound_doorbell; /*0020 0023*/ - u_int32_t diagnostic_rw_data; /*0024 0027*/ - u_int32_t diagnostic_rw_address_low; /*0028 002B*/ - u_int32_t diagnostic_rw_address_high; /*002C 002F*/ - u_int32_t host_int_status; /*0030 0033 host interrupt status*/ - u_int32_t host_int_mask; /*0034 0037 host interrupt mask*/ - u_int32_t dcr_data; /*0038 003B*/ - u_int32_t dcr_address; /*003C 003F*/ - u_int32_t inbound_queueport; /*0040 0043 port32 host inbound queue port*/ - u_int32_t outbound_queueport; /*0044 0047 port32 host outbound queue port*/ - u_int32_t hcb_pci_address_low; /*0048 004B*/ - u_int32_t hcb_pci_address_high; /*004C 004F*/ - u_int32_t iop_int_status; /*0050 0053*/ - u_int32_t iop_int_mask; /*0054 0057*/ - u_int32_t iop_inbound_queue_port; /*0058 005B*/ - u_int32_t iop_outbound_queue_port; /*005C 005F*/ - u_int32_t inbound_free_list_index; /*0060 0063 inbound free list producer consumer index*/ - u_int32_t inbound_post_list_index; /*0064 0067 inbound post list producer consumer index*/ - u_int32_t outbound_free_list_index; /*0068 006B outbound free list producer consumer index*/ - u_int32_t outbound_post_list_index; /*006C 006F outbound post list producer consumer index*/ - u_int32_t inbound_doorbell_clear; /*0070 0073*/ - u_int32_t i2o_message_unit_control; /*0074 0077*/ - u_int32_t last_used_message_source_address_low; /*0078 007B*/ - u_int32_t last_used_message_source_address_high; /*007C 007F*/ - u_int32_t pull_mode_data_byte_count[4]; /*0080 008F pull mode data byte count0..count7*/ - u_int32_t message_dest_address_index; /*0090 0093*/ - u_int32_t done_queue_not_empty_int_counter_timer; /*0094 0097*/ - u_int32_t utility_A_int_counter_timer; /*0098 009B*/ - u_int32_t outbound_doorbell; /*009C 009F*/ - u_int32_t outbound_doorbell_clear; /*00A0 00A3*/ - u_int32_t message_source_address_index; /*00A4 00A7 message accelerator source address consumer producer index*/ - u_int32_t message_done_queue_index; /*00A8 00AB message accelerator completion queue consumer producer index*/ - u_int32_t reserved0; /*00AC 00AF*/ - u_int32_t inbound_msgaddr0; /*00B0 00B3 scratchpad0*/ - u_int32_t inbound_msgaddr1; /*00B4 00B7 scratchpad1*/ - u_int32_t outbound_msgaddr0; /*00B8 00BB scratchpad2*/ - u_int32_t outbound_msgaddr1; /*00BC 00BF scratchpad3*/ - u_int32_t inbound_queueport_low; /*00C0 00C3 port64 host inbound queue port low*/ - u_int32_t inbound_queueport_high; /*00C4 00C7 port64 host inbound queue port high*/ - u_int32_t outbound_queueport_low; /*00C8 00CB port64 host outbound queue port low*/ - u_int32_t outbound_queueport_high; /*00CC 00CF port64 host outbound queue port high*/ - u_int32_t iop_inbound_queue_port_low; /*00D0 00D3*/ - u_int32_t iop_inbound_queue_port_high; /*00D4 00D7*/ - u_int32_t iop_outbound_queue_port_low; /*00D8 00DB*/ - u_int32_t iop_outbound_queue_port_high; /*00DC 00DF*/ - u_int32_t message_dest_queue_port_low; /*00E0 00E3 message accelerator destination queue port low*/ - u_int32_t message_dest_queue_port_high; /*00E4 00E7 message accelerator destination queue port high*/ - u_int32_t last_used_message_dest_address_low; /*00E8 00EB last used message accelerator destination address low*/ - u_int32_t last_used_message_dest_address_high; /*00EC 00EF last used message accelerator destination address high*/ - u_int32_t message_done_queue_base_address_low; /*00F0 00F3 message accelerator completion queue base address low*/ - u_int32_t message_done_queue_base_address_high; /*00F4 00F7 message accelerator completion queue base address high*/ - u_int32_t host_diagnostic; /*00F8 00FB*/ - u_int32_t write_sequence; /*00FC 00FF*/ - u_int32_t reserved1[34]; /*0100 0187*/ - u_int32_t reserved2[1950]; /*0188 1FFF*/ - u_int32_t message_wbuffer[32]; /*2000 207F*/ - u_int32_t reserved3[32]; /*2080 20FF*/ - u_int32_t message_rbuffer[32]; /*2100 217F*/ - u_int32_t reserved4[32]; /*2180 21FF*/ - u_int32_t msgcode_rwbuffer[256]; /*2200 23FF*/ -}; - -/* -********************************************************************* -** -********************************************************************* -*/ -struct MessageUnit_UNION -{ - union { - struct HBA_MessageUnit hbamu; - struct HBB_MessageUnit hbbmu; - struct HBC_MessageUnit hbcmu; - } muu; -}; - -/* ************************************************************* ************************************************************* */ |
