diff options
Diffstat (limited to 'sys/contrib/dev/acpica/common/dmtbinfo.c')
| -rw-r--r-- | sys/contrib/dev/acpica/common/dmtbinfo.c | 967 |
1 files changed, 967 insertions, 0 deletions
diff --git a/sys/contrib/dev/acpica/common/dmtbinfo.c b/sys/contrib/dev/acpica/common/dmtbinfo.c new file mode 100644 index 0000000..5454005 --- /dev/null +++ b/sys/contrib/dev/acpica/common/dmtbinfo.c @@ -0,0 +1,967 @@ +/****************************************************************************** + * + * Module Name: dmtbinfo - Table info for non-AML tables + * $Revision: 1.13 $ + * + *****************************************************************************/ + +/****************************************************************************** + * + * 1. Copyright Notice + * + * Some or all of this work - Copyright (c) 1999 - 2007, Intel Corp. + * All rights reserved. + * + * 2. License + * + * 2.1. This is your license from Intel Corp. under its intellectual property + * rights. You may have additional license terms from the party that provided + * you this software, covering your right to use that party's intellectual + * property rights. + * + * 2.2. Intel grants, free of charge, to any person ("Licensee") obtaining a + * copy of the source code appearing in this file ("Covered Code") an + * irrevocable, perpetual, worldwide license under Intel's copyrights in the + * base code distributed originally by Intel ("Original Intel Code") to copy, + * make derivatives, distribute, use and display any portion of the Covered + * Code in any form, with the right to sublicense such rights; and + * + * 2.3. Intel grants Licensee a non-exclusive and non-transferable patent + * license (with the right to sublicense), under only those claims of Intel + * patents that are infringed by the Original Intel Code, to make, use, sell, + * offer to sell, and import the Covered Code and derivative works thereof + * solely to the minimum extent necessary to exercise the above copyright + * license, and in no event shall the patent license extend to any additions + * to or modifications of the Original Intel Code. No other license or right + * is granted directly or by implication, estoppel or otherwise; + * + * The above copyright and patent license is granted only if the following + * conditions are met: + * + * 3. Conditions + * + * 3.1. Redistribution of Source with Rights to Further Distribute Source. + * Redistribution of source code of any substantial portion of the Covered + * Code or modification with rights to further distribute source must include + * the above Copyright Notice, the above License, this list of Conditions, + * and the following Disclaimer and Export Compliance provision. In addition, + * Licensee must cause all Covered Code to which Licensee contributes to + * contain a file documenting the changes Licensee made to create that Covered + * Code and the date of any change. Licensee must include in that file the + * documentation of any changes made by any predecessor Licensee. Licensee + * must include a prominent statement that the modification is derived, + * directly or indirectly, from Original Intel Code. + * + * 3.2. Redistribution of Source with no Rights to Further Distribute Source. + * Redistribution of source code of any substantial portion of the Covered + * Code or modification without rights to further distribute source must + * include the following Disclaimer and Export Compliance provision in the + * documentation and/or other materials provided with distribution. In + * addition, Licensee may not authorize further sublicense of source of any + * portion of the Covered Code, and must include terms to the effect that the + * license from Licensee to its licensee is limited to the intellectual + * property embodied in the software Licensee provides to its licensee, and + * not to intellectual property embodied in modifications its licensee may + * make. + * + * 3.3. Redistribution of Executable. Redistribution in executable form of any + * substantial portion of the Covered Code or modification must reproduce the + * above Copyright Notice, and the following Disclaimer and Export Compliance + * provision in the documentation and/or other materials provided with the + * distribution. + * + * 3.4. Intel retains all right, title, and interest in and to the Original + * Intel Code. + * + * 3.5. Neither the name Intel nor any other trademark owned or controlled by + * Intel shall be used in advertising or otherwise to promote the sale, use or + * other dealings in products derived from or relating to the Covered Code + * without prior written authorization from Intel. + * + * 4. Disclaimer and Export Compliance + * + * 4.1. INTEL MAKES NO WARRANTY OF ANY KIND REGARDING ANY SOFTWARE PROVIDED + * HERE. ANY SOFTWARE ORIGINATING FROM INTEL OR DERIVED FROM INTEL SOFTWARE + * IS PROVIDED "AS IS," AND INTEL WILL NOT PROVIDE ANY SUPPORT, ASSISTANCE, + * INSTALLATION, TRAINING OR OTHER SERVICES. INTEL WILL NOT PROVIDE ANY + * UPDATES, ENHANCEMENTS OR EXTENSIONS. INTEL SPECIFICALLY DISCLAIMS ANY + * IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT AND FITNESS FOR A + * PARTICULAR PURPOSE. + * + * 4.2. IN NO EVENT SHALL INTEL HAVE ANY LIABILITY TO LICENSEE, ITS LICENSEES + * OR ANY OTHER THIRD PARTY, FOR ANY LOST PROFITS, LOST DATA, LOSS OF USE OR + * COSTS OF PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES, OR FOR ANY INDIRECT, + * SPECIAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THIS AGREEMENT, UNDER ANY + * CAUSE OF ACTION OR THEORY OF LIABILITY, AND IRRESPECTIVE OF WHETHER INTEL + * HAS ADVANCE NOTICE OF THE POSSIBILITY OF SUCH DAMAGES. THESE LIMITATIONS + * SHALL APPLY NOTWITHSTANDING THE FAILURE OF THE ESSENTIAL PURPOSE OF ANY + * LIMITED REMEDY. + * + * 4.3. Licensee shall not export, either directly or indirectly, any of this + * software or system incorporating such software without first obtaining any + * required license or other approval from the U. S. Department of Commerce or + * any other agency or department of the United States Government. In the + * event Licensee exports any such software from the United States or + * re-exports any such software from a foreign destination, Licensee shall + * ensure that the distribution and export/re-export of the software is in + * compliance with all laws, regulations, orders, or other restrictions of the + * U.S. Export Administration Regulations. Licensee agrees that neither it nor + * any of its subsidiaries will export/re-export any technical data, process, + * software, or service, directly or indirectly, to any country for which the + * United States government or any agency thereof requires an export license, + * other governmental approval, or letter of assurance, without first obtaining + * such license, approval or letter. + * + *****************************************************************************/ + +#include <contrib/dev/acpica/acpi.h> +#include <contrib/dev/acpica/acdisasm.h> + +/* This module used for application-level code only */ + +#define _COMPONENT ACPI_CA_DISASSEMBLER + ACPI_MODULE_NAME ("dmtbinfo") + +/* + * Macros used to generate offsets to specific table fields + */ +#define ACPI_FACS_OFFSET(f) (UINT8) ACPI_OFFSET (ACPI_TABLE_FACS,f) +#define ACPI_GAS_OFFSET(f) (UINT8) ACPI_OFFSET (ACPI_GENERIC_ADDRESS,f) +#define ACPI_HDR_OFFSET(f) (UINT8) ACPI_OFFSET (ACPI_TABLE_HEADER,f) +#define ACPI_RSDP_OFFSET(f) (UINT8) ACPI_OFFSET (ACPI_TABLE_RSDP,f) +#define ACPI_BOOT_OFFSET(f) (UINT8) ACPI_OFFSET (ACPI_TABLE_BOOT,f) +#define ACPI_CPEP_OFFSET(f) (UINT8) ACPI_OFFSET (ACPI_TABLE_CPEP,f) +#define ACPI_DBGP_OFFSET(f) (UINT8) ACPI_OFFSET (ACPI_TABLE_DBGP,f) +#define ACPI_DMAR_OFFSET(f) (UINT8) ACPI_OFFSET (ACPI_TABLE_DMAR,f) +#define ACPI_ECDT_OFFSET(f) (UINT8) ACPI_OFFSET (ACPI_TABLE_ECDT,f) +#define ACPI_HPET_OFFSET(f) (UINT8) ACPI_OFFSET (ACPI_TABLE_HPET,f) +#define ACPI_MADT_OFFSET(f) (UINT8) ACPI_OFFSET (ACPI_TABLE_MADT,f) +#define ACPI_MCFG_OFFSET(f) (UINT8) ACPI_OFFSET (ACPI_TABLE_MCFG,f) +#define ACPI_SBST_OFFSET(f) (UINT8) ACPI_OFFSET (ACPI_TABLE_SBST,f) +#define ACPI_SLIT_OFFSET(f) (UINT8) ACPI_OFFSET (ACPI_TABLE_SLIT,f) +#define ACPI_SPCR_OFFSET(f) (UINT8) ACPI_OFFSET (ACPI_TABLE_SPCR,f) +#define ACPI_SPMI_OFFSET(f) (UINT8) ACPI_OFFSET (ACPI_TABLE_SPMI,f) +#define ACPI_SRAT_OFFSET(f) (UINT8) ACPI_OFFSET (ACPI_TABLE_SRAT,f) +#define ACPI_TCPA_OFFSET(f) (UINT8) ACPI_OFFSET (ACPI_TABLE_TCPA,f) +#define ACPI_WDRT_OFFSET(f) (UINT8) ACPI_OFFSET (ACPI_TABLE_WDRT,f) + +/* Sub-tables */ + +#define ACPI_ASF0_OFFSET(f) (UINT8) ACPI_OFFSET (ACPI_ASF_INFO,f) +#define ACPI_ASF1_OFFSET(f) (UINT8) ACPI_OFFSET (ACPI_ASF_ALERT,f) +#define ACPI_ASF1a_OFFSET(f) (UINT8) ACPI_OFFSET (ACPI_ASF_ALERT_DATA,f) +#define ACPI_ASF2_OFFSET(f) (UINT8) ACPI_OFFSET (ACPI_ASF_REMOTE,f) +#define ACPI_ASF2a_OFFSET(f) (UINT8) ACPI_OFFSET (ACPI_ASF_CONTROL_DATA,f) +#define ACPI_ASF3_OFFSET(f) (UINT8) ACPI_OFFSET (ACPI_ASF_RMCP,f) +#define ACPI_ASF4_OFFSET(f) (UINT8) ACPI_OFFSET (ACPI_ASF_ADDRESS,f) +#define ACPI_CPEP0_OFFSET(f) (UINT8) ACPI_OFFSET (ACPI_CPEP_POLLING,f) +#define ACPI_DMARS_OFFSET(f) (UINT8) ACPI_OFFSET (ACPI_DMAR_DEVICE_SCOPE,f) +#define ACPI_DMAR0_OFFSET(f) (UINT8) ACPI_OFFSET (ACPI_DMAR_HARDWARE_UNIT,f) +#define ACPI_DMAR1_OFFSET(f) (UINT8) ACPI_OFFSET (ACPI_DMAR_RESERVED_MEMORY,f) +#define ACPI_MADT0_OFFSET(f) (UINT8) ACPI_OFFSET (ACPI_MADT_LOCAL_APIC,f) +#define ACPI_MADT1_OFFSET(f) (UINT8) ACPI_OFFSET (ACPI_MADT_IO_APIC,f) +#define ACPI_MADT2_OFFSET(f) (UINT8) ACPI_OFFSET (ACPI_MADT_INTERRUPT_OVERRIDE,f) +#define ACPI_MADT3_OFFSET(f) (UINT8) ACPI_OFFSET (ACPI_MADT_NMI_SOURCE,f) +#define ACPI_MADT4_OFFSET(f) (UINT8) ACPI_OFFSET (ACPI_MADT_LOCAL_APIC_NMI,f) +#define ACPI_MADT5_OFFSET(f) (UINT8) ACPI_OFFSET (ACPI_MADT_LOCAL_APIC_OVERRIDE,f) +#define ACPI_MADT6_OFFSET(f) (UINT8) ACPI_OFFSET (ACPI_MADT_IO_SAPIC,f) +#define ACPI_MADT7_OFFSET(f) (UINT8) ACPI_OFFSET (ACPI_MADT_LOCAL_SAPIC,f) +#define ACPI_MADT8_OFFSET(f) (UINT8) ACPI_OFFSET (ACPI_MADT_INTERRUPT_SOURCE,f) +#define ACPI_MADTH_OFFSET(f) (UINT8) ACPI_OFFSET (ACPI_SUBTABLE_HEADER,f) +#define ACPI_MCFG0_OFFSET(f) (UINT8) ACPI_OFFSET (ACPI_MCFG_ALLOCATION,f) +#define ACPI_SRAT0_OFFSET(f) (UINT8) ACPI_OFFSET (ACPI_SRAT_CPU_AFFINITY,f) +#define ACPI_SRAT1_OFFSET(f) (UINT8) ACPI_OFFSET (ACPI_SRAT_MEM_AFFINITY,f) + +/* + * Simplify access to flag fields by breaking them up into bytes + */ +#define ACPI_FLAG_OFFSET(d,f,o) (UINT8) (ACPI_OFFSET (d,f) + o) + +/* Flags */ + +#define ACPI_FADT_FLAG_OFFSET(f,o) ACPI_FLAG_OFFSET (ACPI_TABLE_FADT,f,o) +#define ACPI_FACS_FLAG_OFFSET(f,o) ACPI_FLAG_OFFSET (ACPI_TABLE_FACS,f,o) +#define ACPI_HPET_FLAG_OFFSET(f,o) ACPI_FLAG_OFFSET (ACPI_TABLE_HPET,f,o) +#define ACPI_SRAT0_FLAG_OFFSET(f,o) ACPI_FLAG_OFFSET (ACPI_SRAT_CPU_AFFINITY,f,o) +#define ACPI_SRAT1_FLAG_OFFSET(f,o) ACPI_FLAG_OFFSET (ACPI_SRAT_MEM_AFFINITY,f,o) +#define ACPI_MADT_FLAG_OFFSET(f,o) ACPI_FLAG_OFFSET (ACPI_TABLE_MADT,f,o) +#define ACPI_MADT0_FLAG_OFFSET(f,o) ACPI_FLAG_OFFSET (ACPI_MADT_LOCAL_APIC,f,o) +#define ACPI_MADT2_FLAG_OFFSET(f,o) ACPI_FLAG_OFFSET (ACPI_MADT_INTERRUPT_OVERRIDE,f,o) +#define ACPI_MADT3_FLAG_OFFSET(f,o) ACPI_FLAG_OFFSET (ACPI_MADT_NMI_SOURCE,f,o) +#define ACPI_MADT4_FLAG_OFFSET(f,o) ACPI_FLAG_OFFSET (ACPI_MADT_LOCAL_APIC_NMI,f,o) +#define ACPI_MADT7_FLAG_OFFSET(f,o) ACPI_FLAG_OFFSET (ACPI_MADT_LOCAL_SAPIC,f,o) +#define ACPI_MADT8_FLAG_OFFSET(f,o) ACPI_FLAG_OFFSET (ACPI_MADT_INTERRUPT_SOURCE,f,o) + + +/* + * ACPI Table Information, used to dump formatted ACPI tables + * + * Each entry is of the form: <Field Type, Field Offset, Field Name> + */ + +/******************************************************************************* + * + * Common ACPI table header + * + ******************************************************************************/ + +ACPI_DMTABLE_INFO AcpiDmTableInfoHeader[] = +{ + {ACPI_DMT_SIG, ACPI_HDR_OFFSET (Signature[0]), "Signature"}, + {ACPI_DMT_UINT32, ACPI_HDR_OFFSET (Length), "Table Length"}, + {ACPI_DMT_UINT8, ACPI_HDR_OFFSET (Revision), "Revision"}, + {ACPI_DMT_CHKSUM, ACPI_HDR_OFFSET (Checksum), "Checksum"}, + {ACPI_DMT_NAME6, ACPI_HDR_OFFSET (OemId[0]), "Oem ID"}, + {ACPI_DMT_NAME8, ACPI_HDR_OFFSET (OemTableId[0]), "Oem Table ID"}, + {ACPI_DMT_UINT32, ACPI_HDR_OFFSET (OemRevision), "Oem Revision"}, + {ACPI_DMT_NAME4, ACPI_HDR_OFFSET (AslCompilerId[0]), "Asl Compiler ID"}, + {ACPI_DMT_UINT32, ACPI_HDR_OFFSET (AslCompilerRevision), "Asl Compiler Revision"}, + {ACPI_DMT_EXIT, 0, NULL} +}; + + +/******************************************************************************* + * + * GAS - Generic Address Structure + * + ******************************************************************************/ + +ACPI_DMTABLE_INFO AcpiDmTableInfoGas[] = +{ + {ACPI_DMT_SPACEID, ACPI_GAS_OFFSET (SpaceId), "Space ID"}, + {ACPI_DMT_UINT8, ACPI_GAS_OFFSET (BitWidth), "Bit Width"}, + {ACPI_DMT_UINT8, ACPI_GAS_OFFSET (BitOffset), "Bit Offset"}, + {ACPI_DMT_UINT8, ACPI_GAS_OFFSET (AccessWidth), "Access Width"}, + {ACPI_DMT_UINT64, ACPI_GAS_OFFSET (Address), "Address"}, + {ACPI_DMT_EXIT, 0, NULL} +}; + + +/******************************************************************************* + * + * RSDP - Root System Description Pointer (Signature is "RSD PTR ") + * + ******************************************************************************/ + +ACPI_DMTABLE_INFO AcpiDmTableInfoRsdp1[] = +{ + {ACPI_DMT_NAME8, ACPI_RSDP_OFFSET (Signature[0]), "Signature"}, + {ACPI_DMT_UINT8, ACPI_RSDP_OFFSET (Checksum), "Checksum"}, + {ACPI_DMT_NAME6, ACPI_RSDP_OFFSET (OemId[0]), "Oem ID"}, + {ACPI_DMT_UINT8, ACPI_RSDP_OFFSET (Revision), "Revision"}, + {ACPI_DMT_UINT32, ACPI_RSDP_OFFSET (RsdtPhysicalAddress), "RSDT Address"}, + {ACPI_DMT_EXIT, 0, NULL} +}; + +/* ACPI 2.0+ Extensions */ + +ACPI_DMTABLE_INFO AcpiDmTableInfoRsdp2[] = +{ + {ACPI_DMT_UINT32, ACPI_RSDP_OFFSET (Length), "Length"}, + {ACPI_DMT_UINT64, ACPI_RSDP_OFFSET (XsdtPhysicalAddress), "XSDT Address"}, + {ACPI_DMT_UINT8, ACPI_RSDP_OFFSET (ExtendedChecksum), "Extended Checksum"}, + {ACPI_DMT_UINT24, ACPI_RSDP_OFFSET (Reserved[0]), "Reserved"}, + {ACPI_DMT_EXIT, 0, NULL} +}; + + +/******************************************************************************* + * + * FACS - Firmware ACPI Control Structure + * + ******************************************************************************/ + +ACPI_DMTABLE_INFO AcpiDmTableInfoFacs[] = +{ + {ACPI_DMT_NAME4, ACPI_FACS_OFFSET (Signature[0]), "Signature"}, + {ACPI_DMT_UINT32, ACPI_FACS_OFFSET (Length), "Length"}, + {ACPI_DMT_UINT32, ACPI_FACS_OFFSET (HardwareSignature), "Hardware Signature"}, + {ACPI_DMT_UINT32, ACPI_FACS_OFFSET (FirmwareWakingVector), "Firmware Waking Vector(32)"}, + {ACPI_DMT_UINT32, ACPI_FACS_OFFSET (GlobalLock), "Global Lock"}, + {ACPI_DMT_UINT32, ACPI_FACS_OFFSET (Flags), "Flags (decoded below)"}, + {ACPI_DMT_FLAG0, ACPI_FACS_FLAG_OFFSET (Flags,0), "S4BIOS Support Present"}, + {ACPI_DMT_UINT64, ACPI_FACS_OFFSET (XFirmwareWakingVector), "Firmware Waking Vector(64)"}, + {ACPI_DMT_UINT8, ACPI_FACS_OFFSET (Version), "Version"}, + {ACPI_DMT_EXIT, 0, NULL} +}; + + +/******************************************************************************* + * + * FADT - Fixed ACPI Description Table (Signature is FACP) + * + ******************************************************************************/ + +ACPI_DMTABLE_INFO AcpiDmTableInfoFadt1[] = +{ + {ACPI_DMT_UINT32, ACPI_FADT_OFFSET (Facs), "FACS Address"}, + {ACPI_DMT_UINT32, ACPI_FADT_OFFSET (Dsdt), "DSDT Address"}, + {ACPI_DMT_UINT8, ACPI_FADT_OFFSET (Model), "Model"}, + {ACPI_DMT_UINT8, ACPI_FADT_OFFSET (PreferredProfile), "PM Profile"}, + {ACPI_DMT_UINT16, ACPI_FADT_OFFSET (SciInterrupt), "SCI Interrupt"}, + {ACPI_DMT_UINT32, ACPI_FADT_OFFSET (SmiCommand), "SMI Command Port"}, + {ACPI_DMT_UINT8, ACPI_FADT_OFFSET (AcpiEnable), "ACPI Enable Value"}, + {ACPI_DMT_UINT8, ACPI_FADT_OFFSET (AcpiDisable), "ACPI Disable Value"}, + {ACPI_DMT_UINT8, ACPI_FADT_OFFSET (S4BiosRequest), "S4BIOS Command"}, + {ACPI_DMT_UINT8, ACPI_FADT_OFFSET (PstateControl), "P-State Control"}, + {ACPI_DMT_UINT32, ACPI_FADT_OFFSET (Pm1aEventBlock), "PM1A Event Block Address"}, + {ACPI_DMT_UINT32, ACPI_FADT_OFFSET (Pm1bEventBlock), "PM1B Event Block Address"}, + {ACPI_DMT_UINT32, ACPI_FADT_OFFSET (Pm1aControlBlock), "PM1A Control Block Address"}, + {ACPI_DMT_UINT32, ACPI_FADT_OFFSET (Pm1bControlBlock), "PM1B Control Block Address"}, + {ACPI_DMT_UINT32, ACPI_FADT_OFFSET (Pm2ControlBlock), "PM2 Control Block Address"}, + {ACPI_DMT_UINT32, ACPI_FADT_OFFSET (PmTimerBlock), "PM Timer Block Address"}, + {ACPI_DMT_UINT32, ACPI_FADT_OFFSET (Gpe0Block), "GPE0 Block Address"}, + {ACPI_DMT_UINT32, ACPI_FADT_OFFSET (Gpe1Block), "GPE1 Block Address"}, + {ACPI_DMT_UINT8, ACPI_FADT_OFFSET (Pm1EventLength), "PM1 Event Block Length"}, + {ACPI_DMT_UINT8, ACPI_FADT_OFFSET (Pm1ControlLength), "PM1 Control Block Length"}, + {ACPI_DMT_UINT8, ACPI_FADT_OFFSET (Pm2ControlLength), "PM2 Control Block Length"}, + {ACPI_DMT_UINT8, ACPI_FADT_OFFSET (PmTimerLength), "PM Timer Block Length"}, + {ACPI_DMT_UINT8, ACPI_FADT_OFFSET (Gpe0BlockLength), "GPE0 Block Length"}, + {ACPI_DMT_UINT8, ACPI_FADT_OFFSET (Gpe1BlockLength), "GPE1 Block Length"}, + {ACPI_DMT_UINT8, ACPI_FADT_OFFSET (Gpe1Base), "GPE1 Base Offset"}, + {ACPI_DMT_UINT8, ACPI_FADT_OFFSET (CstControl), "_CST Support"}, + {ACPI_DMT_UINT16, ACPI_FADT_OFFSET (C2Latency), "C2 Latency"}, + {ACPI_DMT_UINT16, ACPI_FADT_OFFSET (C3Latency), "C3 Latency"}, + {ACPI_DMT_UINT16, ACPI_FADT_OFFSET (FlushSize), "CPU Cache Size"}, + {ACPI_DMT_UINT16, ACPI_FADT_OFFSET (FlushStride), "Cache Flush Stride"}, + {ACPI_DMT_UINT8, ACPI_FADT_OFFSET (DutyOffset), "Duty Cycle Offset"}, + {ACPI_DMT_UINT8, ACPI_FADT_OFFSET (DutyWidth), "Duty Cycle Width"}, + {ACPI_DMT_UINT8, ACPI_FADT_OFFSET (DayAlarm), "RTC Day Alarm Index"}, + {ACPI_DMT_UINT8, ACPI_FADT_OFFSET (MonthAlarm), "RTC Month Alarm Index"}, + {ACPI_DMT_UINT8, ACPI_FADT_OFFSET (Century), "RTC Century Index"}, + {ACPI_DMT_UINT16, ACPI_FADT_OFFSET (BootFlags), "Boot Architecture Flags"}, + {ACPI_DMT_UINT8, ACPI_FADT_OFFSET (Reserved), "Reserved"}, + {ACPI_DMT_UINT32, ACPI_FADT_OFFSET (Flags), "Flags (decoded below)"}, + + /* Flags byte 0 */ + + {ACPI_DMT_FLAG0, ACPI_FADT_FLAG_OFFSET (Flags,0), "WBINVD is operational"}, + {ACPI_DMT_FLAG1, ACPI_FADT_FLAG_OFFSET (Flags,0), "WBINVD does not invalidate"}, + {ACPI_DMT_FLAG2, ACPI_FADT_FLAG_OFFSET (Flags,0), "All CPUs support C1"}, + {ACPI_DMT_FLAG3, ACPI_FADT_FLAG_OFFSET (Flags,0), "C2 works on MP system"}, + {ACPI_DMT_FLAG4, ACPI_FADT_FLAG_OFFSET (Flags,0), "Power button is generic"}, + {ACPI_DMT_FLAG5, ACPI_FADT_FLAG_OFFSET (Flags,0), "Sleep button is generic"}, + {ACPI_DMT_FLAG6, ACPI_FADT_FLAG_OFFSET (Flags,0), "RTC wakeup not fixed"}, + {ACPI_DMT_FLAG7, ACPI_FADT_FLAG_OFFSET (Flags,0), "RTC wakeup/S4 not possible"}, + + /* Flags byte 1 */ + + {ACPI_DMT_FLAG0, ACPI_FADT_FLAG_OFFSET (Flags,1), "32-bit PM Timer"}, + {ACPI_DMT_FLAG1, ACPI_FADT_FLAG_OFFSET (Flags,1), "Docking Supported"}, + {ACPI_DMT_EXIT, 0, NULL} +}; + +/* ACPI 2.0+ Extensions */ + +ACPI_DMTABLE_INFO AcpiDmTableInfoFadt2[] = +{ + {ACPI_DMT_FLAG2, ACPI_FADT_FLAG_OFFSET (Flags,1), "Reset Register Supported"}, + {ACPI_DMT_FLAG3, ACPI_FADT_FLAG_OFFSET (Flags,1), "Sealed Case"}, + {ACPI_DMT_FLAG4, ACPI_FADT_FLAG_OFFSET (Flags,1), "Headless - No Video"}, + {ACPI_DMT_FLAG5, ACPI_FADT_FLAG_OFFSET (Flags,1), "Native instr after SLP_TYP"}, + {ACPI_DMT_FLAG6, ACPI_FADT_FLAG_OFFSET (Flags,1), "PCIEXP_WAK Supported"}, + {ACPI_DMT_FLAG7, ACPI_FADT_FLAG_OFFSET (Flags,1), "Use Platform Timer"}, + + /* Flags byte 2 */ + + {ACPI_DMT_FLAG0, ACPI_FADT_FLAG_OFFSET (Flags,2), "RTC_STS valid after S4"}, + {ACPI_DMT_FLAG1, ACPI_FADT_FLAG_OFFSET (Flags,2), "Remote Power-on capable"}, + {ACPI_DMT_FLAG2, ACPI_FADT_FLAG_OFFSET (Flags,2), "APIC Cluster Model"}, + {ACPI_DMT_FLAG3, ACPI_FADT_FLAG_OFFSET (Flags,2), "APIC Physical Dest Mode"}, + + {ACPI_DMT_GAS, ACPI_FADT_OFFSET (ResetRegister), "Reset Register"}, + {ACPI_DMT_UINT8, ACPI_FADT_OFFSET (ResetValue), "Value to cause reset"}, + {ACPI_DMT_UINT24, ACPI_FADT_OFFSET (Reserved4[0]), "Reserved"}, + {ACPI_DMT_UINT64, ACPI_FADT_OFFSET (XFacs), "FACS Address"}, + {ACPI_DMT_UINT64, ACPI_FADT_OFFSET (XDsdt), "DSDT Address"}, + {ACPI_DMT_GAS, ACPI_FADT_OFFSET (XPm1aEventBlock), "PM1A Event Block"}, + {ACPI_DMT_GAS, ACPI_FADT_OFFSET (XPm1bEventBlock), "PM1B Event Block"}, + {ACPI_DMT_GAS, ACPI_FADT_OFFSET (XPm1aControlBlock), "PM1A Control Block"}, + {ACPI_DMT_GAS, ACPI_FADT_OFFSET (XPm1bControlBlock), "PM1B Control Block"}, + {ACPI_DMT_GAS, ACPI_FADT_OFFSET (XPm2ControlBlock), "PM2 Control Block"}, + {ACPI_DMT_GAS, ACPI_FADT_OFFSET (XPmTimerBlock), "PM Timer Block"}, + {ACPI_DMT_GAS, ACPI_FADT_OFFSET (XGpe0Block), "GPE0 Block"}, + {ACPI_DMT_GAS, ACPI_FADT_OFFSET (XGpe1Block), "GPE1 Block"}, + {ACPI_DMT_EXIT, 0, NULL} +}; + + +/* + * Remaining tables are not consumed directly by the ACPICA subsystem + */ + +/******************************************************************************* + * + * ASF - Alert Standard Format table (Signature "ASF!") + * + ******************************************************************************/ + +/* Common sub-table header (one per sub-table) */ + +ACPI_DMTABLE_INFO AcpiDmTableInfoAsfHdr[] = +{ + {ACPI_DMT_UINT8, ACPI_ASF0_OFFSET (Header.Type), "Sub-Table Type"}, + {ACPI_DMT_UINT8, ACPI_ASF0_OFFSET (Header.Reserved), "Reserved"}, + {ACPI_DMT_UINT16, ACPI_ASF0_OFFSET (Header.Length), "Length"}, + {ACPI_DMT_EXIT, 0, NULL} +}; + +/* 0: ASF Information */ + +ACPI_DMTABLE_INFO AcpiDmTableInfoAsf0[] = +{ + {ACPI_DMT_UINT8, ACPI_ASF0_OFFSET (MinResetValue), "Minimum Reset Value"}, + {ACPI_DMT_UINT8, ACPI_ASF0_OFFSET (MinResetValue), "Minimum Polling Interval"}, + {ACPI_DMT_UINT16, ACPI_ASF0_OFFSET (SystemId), "System ID"}, + {ACPI_DMT_UINT32, ACPI_ASF0_OFFSET (SystemId), "Manufacturer ID"}, + {ACPI_DMT_UINT8, ACPI_ASF0_OFFSET (Flags), "Flags"}, + {ACPI_DMT_UINT24, ACPI_ASF0_OFFSET (Reserved2[0]), "Reserved"}, + {ACPI_DMT_EXIT, 0, NULL} +}; + +/* 1: ASF Alerts */ + +ACPI_DMTABLE_INFO AcpiDmTableInfoAsf1[] = +{ + {ACPI_DMT_UINT8, ACPI_ASF1_OFFSET (AssertMask), "AssertMask"}, + {ACPI_DMT_UINT8, ACPI_ASF1_OFFSET (DeassertMask), "DeassertMask"}, + {ACPI_DMT_UINT8, ACPI_ASF1_OFFSET (Alerts), "Alert Count"}, + {ACPI_DMT_UINT8, ACPI_ASF1_OFFSET (DataLength), "Alert Data Length"}, + {ACPI_DMT_EXIT, 0, NULL} +}; + +/* 1a: ASF Alert data */ + +ACPI_DMTABLE_INFO AcpiDmTableInfoAsf1a[] = +{ + {ACPI_DMT_UINT8, ACPI_ASF1a_OFFSET (Address), "Address"}, + {ACPI_DMT_UINT8, ACPI_ASF1a_OFFSET (Command), "Command"}, + {ACPI_DMT_UINT8, ACPI_ASF1a_OFFSET (Mask), "Mask"}, + {ACPI_DMT_UINT8, ACPI_ASF1a_OFFSET (Value), "Value"}, + {ACPI_DMT_UINT8, ACPI_ASF1a_OFFSET (SensorType), "SensorType"}, + {ACPI_DMT_UINT8, ACPI_ASF1a_OFFSET (Type), "Type"}, + {ACPI_DMT_UINT8, ACPI_ASF1a_OFFSET (Offset), "Offset"}, + {ACPI_DMT_UINT8, ACPI_ASF1a_OFFSET (SourceType), "SourceType"}, + {ACPI_DMT_UINT8, ACPI_ASF1a_OFFSET (Severity), "Severity"}, + {ACPI_DMT_UINT8, ACPI_ASF1a_OFFSET (SensorNumber), "SensorNumber"}, + {ACPI_DMT_UINT8, ACPI_ASF1a_OFFSET (Entity), "Entity"}, + {ACPI_DMT_UINT8, ACPI_ASF1a_OFFSET (Instance), "Instance"}, + {ACPI_DMT_EXIT, 0, NULL} +}; + +/* 2: ASF Remote Control */ + +ACPI_DMTABLE_INFO AcpiDmTableInfoAsf2[] = +{ + {ACPI_DMT_UINT8, ACPI_ASF2_OFFSET (Controls), "Control Count"}, + {ACPI_DMT_UINT8, ACPI_ASF2_OFFSET (DataLength), "Control Data Length"}, + {ACPI_DMT_UINT16, ACPI_ASF2_OFFSET (Reserved2), "Reserved"}, + {ACPI_DMT_EXIT, 0, NULL} +}; + +/* 2a: ASF Control data */ + +ACPI_DMTABLE_INFO AcpiDmTableInfoAsf2a[] = +{ + {ACPI_DMT_UINT8, ACPI_ASF2a_OFFSET (Function), "Function"}, + {ACPI_DMT_UINT8, ACPI_ASF2a_OFFSET (Address), "Address"}, + {ACPI_DMT_UINT8, ACPI_ASF2a_OFFSET (Command), "Command"}, + {ACPI_DMT_UINT8, ACPI_ASF2a_OFFSET (Value), "Value"}, + {ACPI_DMT_EXIT, 0, NULL} +}; + +/* 3: ASF RMCP Boot Options */ + +ACPI_DMTABLE_INFO AcpiDmTableInfoAsf3[] = +{ + {ACPI_DMT_UINT56, ACPI_ASF3_OFFSET (Capabilities[0]), "Capabilites"}, + {ACPI_DMT_UINT8, ACPI_ASF3_OFFSET (CompletionCode), "Completion Code"}, + {ACPI_DMT_UINT32, ACPI_ASF3_OFFSET (EnterpriseId), "Enterprise ID"}, + {ACPI_DMT_UINT8, ACPI_ASF3_OFFSET (Command), "Command"}, + {ACPI_DMT_UINT16, ACPI_ASF3_OFFSET (Parameter), "Parameter"}, + {ACPI_DMT_UINT16, ACPI_ASF3_OFFSET (BootOptions), "Boot Options"}, + {ACPI_DMT_UINT16, ACPI_ASF3_OFFSET (OemParameters), "Oem Parameters"}, + {ACPI_DMT_EXIT, 0, NULL} +}; + +/* 4: ASF Address */ + +ACPI_DMTABLE_INFO AcpiDmTableInfoAsf4[] = +{ + {ACPI_DMT_UINT8, ACPI_ASF4_OFFSET (EpromAddress), "Eprom Address"}, + {ACPI_DMT_UINT8, ACPI_ASF4_OFFSET (Devices), "Device Count"}, + {ACPI_DMT_EXIT, 0, NULL} +}; + + +/******************************************************************************* + * + * BOOT - Simple Boot Flag Table + * + ******************************************************************************/ + +ACPI_DMTABLE_INFO AcpiDmTableInfoBoot[] = +{ + {ACPI_DMT_UINT8, ACPI_BOOT_OFFSET (CmosIndex), "Boot Register Index"}, + {ACPI_DMT_UINT24, ACPI_BOOT_OFFSET (Reserved[0]), "Reserved"}, + {ACPI_DMT_EXIT, 0, NULL} +}; + + +/******************************************************************************* + * + * CPEP - Corrected Platform Error Polling table + * + ******************************************************************************/ + +ACPI_DMTABLE_INFO AcpiDmTableInfoCpep[] = +{ + {ACPI_DMT_UINT64, ACPI_CPEP_OFFSET (Reserved), "Reserved"}, + {ACPI_DMT_EXIT, 0, NULL} +}; + +ACPI_DMTABLE_INFO AcpiDmTableInfoCpep0[] = +{ + {ACPI_DMT_UINT8, ACPI_CPEP0_OFFSET (Type), "Sub-Table Type"}, + {ACPI_DMT_UINT8, ACPI_CPEP0_OFFSET (Length), "Length"}, + {ACPI_DMT_UINT8, ACPI_CPEP0_OFFSET (Id), "Processor ID"}, + {ACPI_DMT_UINT8, ACPI_CPEP0_OFFSET (Eid), "Processor EID"}, + {ACPI_DMT_UINT32, ACPI_CPEP0_OFFSET (Interval), "Polling Interval"}, + {ACPI_DMT_EXIT, 0, NULL} +}; + + +/******************************************************************************* + * + * DBGP - Debug Port + * + ******************************************************************************/ + +ACPI_DMTABLE_INFO AcpiDmTableInfoDbgp[] = +{ + {ACPI_DMT_UINT8, ACPI_DBGP_OFFSET (Type), "Interface Type"}, + {ACPI_DMT_UINT24, ACPI_DBGP_OFFSET (Reserved[0]), "Reserved"}, + {ACPI_DMT_GAS, ACPI_DBGP_OFFSET (DebugPort), "Debug Port Register"}, + {ACPI_DMT_EXIT, 0, NULL} +}; + + +/******************************************************************************* + * + * DMAR - DMA Remapping table + * + ******************************************************************************/ + +ACPI_DMTABLE_INFO AcpiDmTableInfoDmar[] = +{ + {ACPI_DMT_UINT8, ACPI_DMAR_OFFSET (Width), "Host Address Width"}, + {ACPI_DMT_EXIT, 0, NULL} +}; + +/* Common sub-table header (one per sub-table) */ + +ACPI_DMTABLE_INFO AcpiDmTableInfoDmarHdr[] = +{ + {ACPI_DMT_DMAR, ACPI_DMAR0_OFFSET (Header.Type), "Sub-Table Type"}, + {ACPI_DMT_UINT16, ACPI_DMAR0_OFFSET (Header.Length), "Length"}, + {ACPI_DMT_UINT8, ACPI_DMAR0_OFFSET (Header.Flags), "Flags"}, + {ACPI_DMT_UINT24, ACPI_DMAR0_OFFSET (Header.Reserved[0]), "Reserved"}, + {ACPI_DMT_EXIT, 0, NULL} +}; + +/* Common device scope entry */ + +ACPI_DMTABLE_INFO AcpiDmTableInfoDmarScope[] = +{ + {ACPI_DMT_UINT8, ACPI_DMARS_OFFSET (EntryType), "Device Scope Entry Type"}, + {ACPI_DMT_UINT8, ACPI_DMARS_OFFSET (Length), "Entry Length"}, + {ACPI_DMT_UINT8, ACPI_DMARS_OFFSET (Segment), "PCI Segment Number"}, + {ACPI_DMT_UINT8, ACPI_DMARS_OFFSET (Bus), "PCI Bus Number"}, + {ACPI_DMT_EXIT, 0, NULL} +}; + +/* DMAR sub-tables */ + +/* 0: Hardware Unit Definition */ + +ACPI_DMTABLE_INFO AcpiDmTableInfoDmar0[] = +{ + {ACPI_DMT_UINT64, ACPI_DMAR0_OFFSET (Address), "Register Base Address"}, + {ACPI_DMT_EXIT, 0, NULL} +}; + +/* 1: Reserved Memory Defininition */ + +ACPI_DMTABLE_INFO AcpiDmTableInfoDmar1[] = +{ + {ACPI_DMT_UINT64, ACPI_DMAR1_OFFSET (Address), "Base Address"}, + {ACPI_DMT_UINT64, ACPI_DMAR1_OFFSET (EndAddress), "End Address (limit)"}, + {ACPI_DMT_EXIT, 0, NULL} +}; + + +/******************************************************************************* + * + * ECDT - Embedded Controller Boot Resources Table + * + ******************************************************************************/ + +ACPI_DMTABLE_INFO AcpiDmTableInfoEcdt[] = +{ + {ACPI_DMT_GAS, ACPI_ECDT_OFFSET (Control), "Command/Status Register"}, + {ACPI_DMT_GAS, ACPI_ECDT_OFFSET (Data), "Data Register"}, + {ACPI_DMT_UINT32, ACPI_ECDT_OFFSET (Uid), "UID"}, + {ACPI_DMT_UINT8, ACPI_ECDT_OFFSET (Gpe), "GPE Number"}, + {ACPI_DMT_STRING, ACPI_ECDT_OFFSET (Id[0]), "Namepath"}, + {ACPI_DMT_EXIT, 0, NULL} +}; + + +/******************************************************************************* + * + * HPET - High Precision Event Timer table + * + ******************************************************************************/ + +ACPI_DMTABLE_INFO AcpiDmTableInfoHpet[] = +{ + {ACPI_DMT_UINT32, ACPI_HPET_OFFSET (Id), "Hardware Block ID"}, + {ACPI_DMT_GAS, ACPI_HPET_OFFSET (Address), "Timer Block Register"}, + {ACPI_DMT_UINT8, ACPI_HPET_OFFSET (Sequence), "Sequence Number"}, + {ACPI_DMT_UINT16, ACPI_HPET_OFFSET (MinimumTick), "Minimum Clock Ticks"}, + {ACPI_DMT_UINT8, ACPI_HPET_OFFSET (Flags), "Flags (decoded below)"}, + {ACPI_DMT_FLAG0, ACPI_HPET_FLAG_OFFSET (Flags,0), "Page Protect"}, + {ACPI_DMT_FLAG1, ACPI_HPET_FLAG_OFFSET (Flags,0), "4K Page Protect"}, + {ACPI_DMT_FLAG2, ACPI_HPET_FLAG_OFFSET (Flags,0), "64K Page Protect"}, + {ACPI_DMT_EXIT, 0, NULL} +}; + + +/******************************************************************************* + * + * MADT - Multiple APIC Description Table and subtables + * + ******************************************************************************/ + +ACPI_DMTABLE_INFO AcpiDmTableInfoMadt[] = +{ + {ACPI_DMT_UINT32, ACPI_MADT_OFFSET (Address), "Local Apic Address"}, + {ACPI_DMT_UINT32, ACPI_MADT_OFFSET (Flags), "Flags (decoded below)"}, + {ACPI_DMT_FLAG0, ACPI_MADT_FLAG_OFFSET (Flags,0), "PC-AT Compatibility"}, + {ACPI_DMT_EXIT, 0, NULL} +}; + +/* Common sub-table header (one per sub-table) */ + +ACPI_DMTABLE_INFO AcpiDmTableInfoMadtHdr[] = +{ + {ACPI_DMT_MADT, ACPI_MADTH_OFFSET (Type), "Sub-Table Type"}, + {ACPI_DMT_UINT8, ACPI_MADTH_OFFSET (Length), "Length"}, + {ACPI_DMT_EXIT, 0, NULL} +}; + +/* MADT sub-tables */ + +/* 0: processor APIC */ + +ACPI_DMTABLE_INFO AcpiDmTableInfoMadt0[] = +{ + {ACPI_DMT_UINT8, ACPI_MADT0_OFFSET (ProcessorId), "Processor ID"}, + {ACPI_DMT_UINT8, ACPI_MADT0_OFFSET (Id), "Local Apic ID"}, + {ACPI_DMT_UINT32, ACPI_MADT0_OFFSET (LapicFlags), "Flags (decoded below)"}, + {ACPI_DMT_FLAG0, ACPI_MADT0_FLAG_OFFSET (LapicFlags,0), "Processor Enabled"}, + {ACPI_DMT_EXIT, 0, NULL} +}; + +/* 1: IO APIC */ + +ACPI_DMTABLE_INFO AcpiDmTableInfoMadt1[] = +{ + {ACPI_DMT_UINT8, ACPI_MADT1_OFFSET (Id), "I/O Apic ID"}, + {ACPI_DMT_UINT8, ACPI_MADT1_OFFSET (Reserved), "Reserved"}, + {ACPI_DMT_UINT32, ACPI_MADT1_OFFSET (Address), "Address"}, + {ACPI_DMT_UINT32, ACPI_MADT1_OFFSET (GlobalIrqBase), "Interrupt"}, + {ACPI_DMT_EXIT, 0, NULL} +}; + +/* 2: Interrupt Override */ + +ACPI_DMTABLE_INFO AcpiDmTableInfoMadt2[] = +{ + {ACPI_DMT_UINT8, ACPI_MADT2_OFFSET (Bus), "Bus"}, + {ACPI_DMT_UINT8, ACPI_MADT2_OFFSET (SourceIrq), "Source"}, + {ACPI_DMT_UINT32, ACPI_MADT2_OFFSET (GlobalIrq), "Interrupt"}, + {ACPI_DMT_UINT16, ACPI_MADT2_OFFSET (IntiFlags), "Flags (decoded below)"}, + {ACPI_DMT_FLAGS0, ACPI_MADT2_FLAG_OFFSET (IntiFlags,0), "Polarity"}, + {ACPI_DMT_FLAGS2, ACPI_MADT2_FLAG_OFFSET (IntiFlags,0), "Trigger Mode"}, + {ACPI_DMT_EXIT, 0, NULL} +}; + +/* 3: NMI Sources */ + +ACPI_DMTABLE_INFO AcpiDmTableInfoMadt3[] = +{ + {ACPI_DMT_UINT16, ACPI_MADT3_OFFSET (IntiFlags), "Flags (decoded below)"}, + {ACPI_DMT_FLAGS0, ACPI_MADT3_FLAG_OFFSET (IntiFlags,0), "Polarity"}, + {ACPI_DMT_FLAGS2, ACPI_MADT3_FLAG_OFFSET (IntiFlags,0), "Trigger Mode"}, + {ACPI_DMT_UINT32, ACPI_MADT3_OFFSET (GlobalIrq), "Interrupt"}, + {ACPI_DMT_EXIT, 0, NULL} +}; + +/* 4: Local APIC NMI */ + +ACPI_DMTABLE_INFO AcpiDmTableInfoMadt4[] = +{ + {ACPI_DMT_UINT8, ACPI_MADT4_OFFSET (ProcessorId), "Processor ID"}, + {ACPI_DMT_UINT16, ACPI_MADT4_OFFSET (IntiFlags), "Flags (decoded below)"}, + {ACPI_DMT_FLAGS0, ACPI_MADT4_FLAG_OFFSET (IntiFlags,0), "Polarity"}, + {ACPI_DMT_FLAGS2, ACPI_MADT4_FLAG_OFFSET (IntiFlags,0), "Trigger Mode"}, + {ACPI_DMT_UINT8, ACPI_MADT4_OFFSET (Lint), "Interrupt Input LINT"}, + {ACPI_DMT_EXIT, 0, NULL} +}; + +/* 5: Address Override */ + +ACPI_DMTABLE_INFO AcpiDmTableInfoMadt5[] = +{ + {ACPI_DMT_UINT16, ACPI_MADT5_OFFSET (Reserved), "Reserved"}, + {ACPI_DMT_UINT64, ACPI_MADT5_OFFSET (Address), "APIC Address"}, + {ACPI_DMT_EXIT, 0, NULL} +}; + +/* 6: I/O Sapic */ + +ACPI_DMTABLE_INFO AcpiDmTableInfoMadt6[] = +{ + {ACPI_DMT_UINT8, ACPI_MADT6_OFFSET (Id), "I/O Sapic ID"}, + {ACPI_DMT_UINT8, ACPI_MADT6_OFFSET (Reserved), "Reserved"}, + {ACPI_DMT_UINT32, ACPI_MADT6_OFFSET (GlobalIrqBase), "Interrupt Base"}, + {ACPI_DMT_UINT64, ACPI_MADT6_OFFSET (Address), "Address"}, + {ACPI_DMT_EXIT, 0, NULL} +}; + +/* 7: Local Sapic */ + +ACPI_DMTABLE_INFO AcpiDmTableInfoMadt7[] = +{ + {ACPI_DMT_UINT8, ACPI_MADT7_OFFSET (ProcessorId), "Processor ID"}, + {ACPI_DMT_UINT8, ACPI_MADT7_OFFSET (Id), "Local Sapic ID"}, + {ACPI_DMT_UINT8, ACPI_MADT7_OFFSET (Eid), "Local Sapic EID"}, + {ACPI_DMT_UINT24, ACPI_MADT7_OFFSET (Reserved[0]), "Reserved"}, + {ACPI_DMT_UINT32, ACPI_MADT7_OFFSET (LapicFlags), "Flags (decoded below)"}, + {ACPI_DMT_FLAG0, ACPI_MADT7_FLAG_OFFSET (LapicFlags,0), "Processor Enabled"}, + {ACPI_DMT_UINT32, ACPI_MADT7_OFFSET (Uid), "Processor UID"}, + {ACPI_DMT_STRING, ACPI_MADT7_OFFSET (UidString[0]), "Processor UID String"}, + {ACPI_DMT_EXIT, 0, NULL} +}; + +/* 8: Platform Interrupt Source */ + +ACPI_DMTABLE_INFO AcpiDmTableInfoMadt8[] = +{ + {ACPI_DMT_UINT16, ACPI_MADT8_OFFSET (IntiFlags), "Flags (decoded below)"}, + {ACPI_DMT_FLAGS0, ACPI_MADT8_FLAG_OFFSET (IntiFlags,0), "Polarity"}, + {ACPI_DMT_FLAGS2, ACPI_MADT8_FLAG_OFFSET (IntiFlags,0), "Trigger Mode"}, + {ACPI_DMT_UINT8, ACPI_MADT8_OFFSET (Type), "InterruptType"}, + {ACPI_DMT_UINT8, ACPI_MADT8_OFFSET (Id), "Processor ID"}, + {ACPI_DMT_UINT8, ACPI_MADT8_OFFSET (Eid), "Processor EID"}, + {ACPI_DMT_UINT8, ACPI_MADT8_OFFSET (IoSapicVector), "I/O Sapic Vector"}, + {ACPI_DMT_UINT32, ACPI_MADT8_OFFSET (GlobalIrq), "Interrupt"}, + {ACPI_DMT_UINT32, ACPI_MADT8_OFFSET (Flags), "Flags (decoded below)"}, + {ACPI_DMT_FLAG0, ACPI_MADT8_OFFSET (Flags), "CPEI Override"}, + {ACPI_DMT_EXIT, 0, NULL} +}; + + +/******************************************************************************* + * + * MCFG - PCI Memory Mapped Configuration table and sub-table + * + ******************************************************************************/ + +ACPI_DMTABLE_INFO AcpiDmTableInfoMcfg[] = +{ + {ACPI_DMT_UINT64, ACPI_MCFG_OFFSET (Reserved[0]), "Reserved"}, + {ACPI_DMT_EXIT, 0, NULL} +}; + +ACPI_DMTABLE_INFO AcpiDmTableInfoMcfg0[] = +{ + {ACPI_DMT_UINT64, ACPI_MCFG0_OFFSET (Address), "Base Address"}, + {ACPI_DMT_UINT16, ACPI_MCFG0_OFFSET (PciSegment), "Segment Group Number"}, + {ACPI_DMT_UINT8, ACPI_MCFG0_OFFSET (StartBusNumber), "Start Bus Number"}, + {ACPI_DMT_UINT8, ACPI_MCFG0_OFFSET (EndBusNumber), "End Bus Number"}, + {ACPI_DMT_UINT32, ACPI_MCFG0_OFFSET (Reserved), "Reserved"}, + {ACPI_DMT_EXIT, 0, NULL} +}; + + +/******************************************************************************* + * + * SBST - Smart Battery Specification Table + * + ******************************************************************************/ + +ACPI_DMTABLE_INFO AcpiDmTableInfoSbst[] = +{ + {ACPI_DMT_UINT32, ACPI_SBST_OFFSET (WarningLevel), "Warning Level"}, + {ACPI_DMT_UINT32, ACPI_SBST_OFFSET (LowLevel), "Low Level"}, + {ACPI_DMT_UINT32, ACPI_SBST_OFFSET (CriticalLevel), "Critical Level"}, + {ACPI_DMT_EXIT, 0, NULL} +}; + + +/******************************************************************************* + * + * SLIT - System Locality Information Table + * + ******************************************************************************/ + +ACPI_DMTABLE_INFO AcpiDmTableInfoSlit[] = +{ + {ACPI_DMT_UINT64, ACPI_SLIT_OFFSET (LocalityCount), "Localities"}, + {ACPI_DMT_EXIT, 0, NULL} +}; + + +/******************************************************************************* + * + * SPCR - Serial Port Console Redirection table + * + ******************************************************************************/ + +ACPI_DMTABLE_INFO AcpiDmTableInfoSpcr[] = +{ + {ACPI_DMT_UINT8, ACPI_SPCR_OFFSET (InterfaceType), "Interface Type"}, + {ACPI_DMT_UINT24, ACPI_SPCR_OFFSET (Reserved[0]), "Reserved"}, + {ACPI_DMT_GAS, ACPI_SPCR_OFFSET (SerialPort), "Serial Port Register"}, + {ACPI_DMT_UINT8, ACPI_SPCR_OFFSET (InterruptType), "Interrupt Type"}, + {ACPI_DMT_UINT8, ACPI_SPCR_OFFSET (PcInterrupt), "PCAT-compatible IRQ"}, + {ACPI_DMT_UINT32, ACPI_SPCR_OFFSET (Interrupt), "Interrupt"}, + {ACPI_DMT_UINT8, ACPI_SPCR_OFFSET (BaudRate), "Baud Rate"}, + {ACPI_DMT_UINT8, ACPI_SPCR_OFFSET (Parity), "Parity"}, + {ACPI_DMT_UINT8, ACPI_SPCR_OFFSET (StopBits), "Stop Bits"}, + {ACPI_DMT_UINT8, ACPI_SPCR_OFFSET (FlowControl), "Flow Control"}, + {ACPI_DMT_UINT8, ACPI_SPCR_OFFSET (TerminalType), "Terminal Type"}, + {ACPI_DMT_UINT8, ACPI_SPCR_OFFSET (Reserved2), "Reserved"}, + {ACPI_DMT_UINT16, ACPI_SPCR_OFFSET (PciDeviceId), "PCI Device ID"}, + {ACPI_DMT_UINT16, ACPI_SPCR_OFFSET (PciVendorId), "PCI Vendor ID"}, + {ACPI_DMT_UINT8, ACPI_SPCR_OFFSET (PciBus), "PCI Bus"}, + {ACPI_DMT_UINT8, ACPI_SPCR_OFFSET (PciDevice), "PCI Device"}, + {ACPI_DMT_UINT8, ACPI_SPCR_OFFSET (PciFunction), "PCI Function"}, + {ACPI_DMT_UINT32, ACPI_SPCR_OFFSET (PciFlags), "PCI Flags"}, + {ACPI_DMT_UINT8, ACPI_SPCR_OFFSET (PciSegment), "PCI Segment"}, + {ACPI_DMT_UINT32, ACPI_SPCR_OFFSET (Reserved2), "Reserved"}, + {ACPI_DMT_EXIT, 0, NULL} +}; + + +/******************************************************************************* + * + * SPMI - Server Platform Management Interface table + * + ******************************************************************************/ + +ACPI_DMTABLE_INFO AcpiDmTableInfoSpmi[] = +{ + {ACPI_DMT_UINT8, ACPI_SPMI_OFFSET (Reserved), "Reserved"}, + {ACPI_DMT_UINT8, ACPI_SPMI_OFFSET (InterfaceType), "Interface Type"}, + {ACPI_DMT_UINT16, ACPI_SPMI_OFFSET (SpecRevision), "IPMI Spec Version"}, + {ACPI_DMT_UINT8, ACPI_SPMI_OFFSET (InterruptType), "Interrupt Type"}, + {ACPI_DMT_UINT8, ACPI_SPMI_OFFSET (GpeNumber), "GPE Number"}, + {ACPI_DMT_UINT8, ACPI_SPMI_OFFSET (Reserved1), "Reserved"}, + {ACPI_DMT_UINT8, ACPI_SPMI_OFFSET (PciDeviceFlag), "PCI Device Flag"}, + {ACPI_DMT_UINT32, ACPI_SPMI_OFFSET (Interrupt), "Interrupt"}, + {ACPI_DMT_GAS, ACPI_SPMI_OFFSET (IpmiRegister), "IPMI Register"}, + {ACPI_DMT_UINT8, ACPI_SPMI_OFFSET (PciSegment), "PCI Segment"}, + {ACPI_DMT_UINT8, ACPI_SPMI_OFFSET (PciBus), "PCI Bus"}, + {ACPI_DMT_UINT8, ACPI_SPMI_OFFSET (PciDevice), "PCI Device"}, + {ACPI_DMT_UINT8, ACPI_SPMI_OFFSET (PciFunction), "PCI Function"}, + {ACPI_DMT_EXIT, 0, NULL} +}; + + +/******************************************************************************* + * + * SRAT - System Resource Affinity Table and sub-tables + * + ******************************************************************************/ + +ACPI_DMTABLE_INFO AcpiDmTableInfoSrat[] = +{ + {ACPI_DMT_UINT32, ACPI_SRAT_OFFSET (TableRevision), "Table Revision"}, + {ACPI_DMT_UINT64, ACPI_SRAT_OFFSET (Reserved), "Reserved"}, + {ACPI_DMT_EXIT, 0, NULL} +}; + +ACPI_DMTABLE_INFO AcpiDmTableInfoSrat0[] = +{ + {ACPI_DMT_SRAT, ACPI_SRAT0_OFFSET (Header.Type), "Sub-Table Type"}, + {ACPI_DMT_UINT8, ACPI_SRAT0_OFFSET (Header.Length), "Length"}, + {ACPI_DMT_UINT8, ACPI_SRAT0_OFFSET (ProximityDomainLo), "Proximity Domain Low(8)"}, + {ACPI_DMT_UINT8, ACPI_SRAT0_OFFSET (ApicId), "Apic ID"}, + {ACPI_DMT_UINT32, ACPI_SRAT0_OFFSET (Flags), "Flags (decoded below)"}, + {ACPI_DMT_FLAG0, ACPI_SRAT0_FLAG_OFFSET (Flags,0), "Enabled"}, + {ACPI_DMT_UINT8, ACPI_SRAT0_OFFSET (LocalSapicEid), "Local Sapic EID"}, + {ACPI_DMT_UINT24, ACPI_SRAT0_OFFSET (ProximityDomainHi[0]), "Proximity Domain High(24)"}, + {ACPI_DMT_UINT32, ACPI_SRAT0_OFFSET (Reserved), "Reserved"}, + {ACPI_DMT_EXIT, 0, NULL} +}; + +ACPI_DMTABLE_INFO AcpiDmTableInfoSrat1[] = +{ + {ACPI_DMT_SRAT, ACPI_SRAT1_OFFSET (Header.Type), "Sub-Table Type"}, + {ACPI_DMT_UINT8, ACPI_SRAT1_OFFSET (Header.Length), "Length"}, + {ACPI_DMT_UINT32, ACPI_SRAT1_OFFSET (ProximityDomain), "Proximity Domain"}, + {ACPI_DMT_UINT16, ACPI_SRAT1_OFFSET (Reserved), "Reserved"}, + {ACPI_DMT_UINT64, ACPI_SRAT1_OFFSET (BaseAddress), "Base Address"}, + {ACPI_DMT_UINT64, ACPI_SRAT1_OFFSET (Length), "Address Length"}, + {ACPI_DMT_UINT32, ACPI_SRAT1_OFFSET (MemoryType), "Memory Type"}, + {ACPI_DMT_UINT32, ACPI_SRAT1_OFFSET (Flags), "Flags (decoded below)"}, + {ACPI_DMT_FLAG0, ACPI_SRAT1_FLAG_OFFSET (Flags,0), "Enabled"}, + {ACPI_DMT_FLAG1, ACPI_SRAT1_FLAG_OFFSET (Flags,0), "Hot Pluggable"}, + {ACPI_DMT_FLAG2, ACPI_SRAT1_FLAG_OFFSET (Flags,0), "Non-Volatile"}, + {ACPI_DMT_UINT64, ACPI_SRAT1_OFFSET (Reserved1), "Reserved"}, + {ACPI_DMT_EXIT, 0, NULL} +}; + + +/******************************************************************************* + * + * TCPA - Trusted Computing Platform Alliance table + * + ******************************************************************************/ + +ACPI_DMTABLE_INFO AcpiDmTableInfoTcpa[] = +{ + {ACPI_DMT_UINT16, ACPI_TCPA_OFFSET (Reserved), "Reserved"}, + {ACPI_DMT_UINT32, ACPI_TCPA_OFFSET (MaxLogLength), "Max Event Log Length"}, + {ACPI_DMT_UINT64, ACPI_TCPA_OFFSET (LogAddress), "Event Log Address"}, + {ACPI_DMT_EXIT, 0, NULL} +}; + + +/******************************************************************************* + * + * WDRT - Watchdog Resource Table + * + ******************************************************************************/ + +ACPI_DMTABLE_INFO AcpiDmTableInfoWdrt[] = +{ + {ACPI_DMT_UINT32, ACPI_WDRT_OFFSET (HeaderLength), "Header Length"}, + {ACPI_DMT_UINT8, ACPI_WDRT_OFFSET (PciSegment), "PCI Segment"}, + {ACPI_DMT_UINT8, ACPI_WDRT_OFFSET (PciBus), "PCI Bus"}, + {ACPI_DMT_UINT8, ACPI_WDRT_OFFSET (PciDevice), "PCI Device"}, + {ACPI_DMT_UINT8, ACPI_WDRT_OFFSET (PciFunction), "PCI Function"}, + {ACPI_DMT_UINT32, ACPI_WDRT_OFFSET (TimerPeriod), "Timer Period"}, + {ACPI_DMT_UINT32, ACPI_WDRT_OFFSET (MaxCount), "Max Count"}, + {ACPI_DMT_UINT32, ACPI_WDRT_OFFSET (MinCount), "Min Count"}, + {ACPI_DMT_UINT8, ACPI_WDRT_OFFSET (Flags), "Flags (decoded below)"}, + {ACPI_DMT_FLAG0, ACPI_WDRT_OFFSET (Flags), "Enabled"}, + {ACPI_DMT_FLAG7, ACPI_WDRT_OFFSET (Flags), "Stopped When Asleep"}, + {ACPI_DMT_UINT24, ACPI_WDRT_OFFSET (Reserved[0]), "Reserved"}, + {ACPI_DMT_UINT32, ACPI_WDRT_OFFSET (Entries), "Watchdog Entries"}, + {ACPI_DMT_EXIT, 0, NULL} +}; + |
