diff options
Diffstat (limited to 'sys/conf/NOTES')
| -rw-r--r-- | sys/conf/NOTES | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/sys/conf/NOTES b/sys/conf/NOTES index b8bb5a2..2db3cfa 100644 --- a/sys/conf/NOTES +++ b/sys/conf/NOTES @@ -2,7 +2,7 @@ # LINT -- config file for checking all the sources, tries to pull in # as much of the source tree as it can. # -# $Id: LINT,v 1.369 1997/09/23 08:42:42 jkh Exp $ +# $Id: LINT,v 1.370 1997/09/23 16:28:00 jkh Exp $ # # NB: You probably don't want to try running a kernel built from this # file. Instead, you should start from GENERIC, and add options from @@ -132,6 +132,10 @@ cpu "I686_CPU" # aka Pentium Pro(tm) # CPU_DIRECT_MAPPED_CACHE sets L1 cache of Cyrix 486DLC CPU in direct # mapped mode. Default is 2-way set associative mode. # +# CPU_CYRIX_NO_LOCK enables weak locking for the entire address space +# of Cyrix 6x86 and 6x86MX CPUs. If this option is not set and +# FAILESAFE is defined, NO_LOCK bit of CCR1 is cleared. (NOTE 3) +# # CPU_DISABLE_5X86_LSSER disables load store serialize (i.e. enables # reorder). This option should not be used if you use memory mapped # I/O device(s). @@ -154,6 +158,8 @@ cpu "I686_CPU" # aka Pentium Pro(tm) # CPU_SUSP_HLT enables suspend on HALT. If this option is set, CPU # enters suspend mode following execution of HALT instruction. # +# CPU_WT_ALLOC enables write-through allocation. +# # CYRIX_CACHE_WORKS enables CPU cache on Cyrix 486 CPUs with cache # flush at hold state. # @@ -169,6 +175,9 @@ cpu "I686_CPU" # aka Pentium Pro(tm) # in write-through mode when revision < 2.7. If revision of Cyrix # 6x86 >= 2.7, CPU cache is always enabled in write-back mode. # +# NOTE 3: This option may cause failures for software that requires +# locked cycles in order to operate correctly. +# options "CPU_BLUELIGHTNING_FPU_OP_CACHE" options "CPU_BLUELIGHTNING_3X" options "CPU_BTB_EN" |
