diff options
Diffstat (limited to 'sys/arm')
108 files changed, 640 insertions, 1855 deletions
diff --git a/sys/arm/allwinner/a10_common.c b/sys/arm/allwinner/a10_common.c index 82be0c0..6b3fded 100644 --- a/sys/arm/allwinner/a10_common.c +++ b/sys/arm/allwinner/a10_common.c @@ -38,10 +38,6 @@ __FBSDID("$FreeBSD$"); #include <machine/bus.h> #include <machine/vmparam.h> -struct fdt_fixup_entry fdt_fixup_table[] = { - { NULL, NULL } -}; - #ifndef INTRNG static int diff --git a/sys/arm/allwinner/aw_machdep.c b/sys/arm/allwinner/aw_machdep.c index 3fab0a1..ce761c8 100644 --- a/sys/arm/allwinner/aw_machdep.c +++ b/sys/arm/allwinner/aw_machdep.c @@ -36,7 +36,6 @@ #include <sys/cdefs.h> __FBSDID("$FreeBSD$"); -#define _ARM32_BUS_DMA_PRIVATE #include <sys/param.h> #include <sys/systm.h> #include <sys/bus.h> @@ -147,18 +146,6 @@ allwinner_devmap_init(platform_t plat) return (0); } -struct arm32_dma_range * -bus_dma_get_range(void) -{ - return (NULL); -} - -int -bus_dma_get_range_nb(void) -{ - return (0); -} - void cpu_reset() { diff --git a/sys/arm/allwinner/aw_wdog.c b/sys/arm/allwinner/aw_wdog.c index 4dcefd4..6dd68b4 100644 --- a/sys/arm/allwinner/aw_wdog.c +++ b/sys/arm/allwinner/aw_wdog.c @@ -238,7 +238,7 @@ aw_wdog_shutdown_fn(void *private, int howto) } void -aw_wdog_watchdog_reset() +aw_wdog_watchdog_reset(void) { if (aw_wdog_sc == NULL) { diff --git a/sys/arm/altera/socfpga/socfpga_common.c b/sys/arm/altera/socfpga/socfpga_common.c index 740d342..1e6df97 100644 --- a/sys/arm/altera/socfpga/socfpga_common.c +++ b/sys/arm/altera/socfpga/socfpga_common.c @@ -36,7 +36,6 @@ __FBSDID("$FreeBSD$"); #include <sys/bus.h> #include <sys/kernel.h> -#include <dev/fdt/fdt_common.h> #include <dev/ofw/openfirm.h> #include <machine/bus.h> @@ -47,7 +46,7 @@ __FBSDID("$FreeBSD$"); void cpu_reset(void) { - uint32_t addr, paddr; + uint32_t paddr; bus_addr_t vaddr; phandle_t node; @@ -58,9 +57,8 @@ cpu_reset(void) if (node == -1) goto end; - if ((OF_getprop(node, "reg", &paddr, sizeof(paddr))) > 0) { - addr = fdt32_to_cpu(paddr); - if (bus_space_map(fdtbus_bs_tag, addr, 0x8, 0, &vaddr) == 0) { + if ((OF_getencprop(node, "reg", &paddr, sizeof(paddr))) > 0) { + if (bus_space_map(fdtbus_bs_tag, paddr, 0x8, 0, &vaddr) == 0) { bus_space_write_4(fdtbus_bs_tag, vaddr, RSTMGR_CTRL, CTRL_SWWARMRSTREQ); } @@ -70,10 +68,6 @@ end: while (1); } -struct fdt_fixup_entry fdt_fixup_table[] = { - { NULL, NULL } -}; - #ifndef INTRNG static int fdt_pic_decode_ic(phandle_t node, pcell_t *intr, int *interrupt, int *trig, diff --git a/sys/arm/altera/socfpga/socfpga_machdep.c b/sys/arm/altera/socfpga/socfpga_machdep.c index 9ae868a..bcfdd5c 100644 --- a/sys/arm/altera/socfpga/socfpga_machdep.c +++ b/sys/arm/altera/socfpga/socfpga_machdep.c @@ -34,7 +34,6 @@ #include <sys/cdefs.h> __FBSDID("$FreeBSD$"); -#define _ARM32_BUS_DMA_PRIVATE #include <sys/param.h> #include <sys/systm.h> #include <sys/bus.h> @@ -100,17 +99,3 @@ platform_devmap_init(void) return (0); } - -struct arm32_dma_range * -bus_dma_get_range(void) -{ - - return (NULL); -} - -int -bus_dma_get_range_nb(void) -{ - - return (0); -} diff --git a/sys/arm/altera/socfpga/socfpga_rstmgr.c b/sys/arm/altera/socfpga/socfpga_rstmgr.c index 49db05e..d5f773f 100644 --- a/sys/arm/altera/socfpga/socfpga_rstmgr.c +++ b/sys/arm/altera/socfpga/socfpga_rstmgr.c @@ -47,7 +47,6 @@ __FBSDID("$FreeBSD$"); #include <sys/timetc.h> #include <sys/sysctl.h> -#include <dev/fdt/fdt_common.h> #include <dev/ofw/openfirm.h> #include <dev/ofw/ofw_bus.h> #include <dev/ofw/ofw_bus_subr.h> @@ -84,7 +83,7 @@ enum { static int l3remap(struct rstmgr_softc *sc, int remap, int enable) { - uint32_t addr, paddr; + uint32_t paddr; bus_addr_t vaddr; phandle_t node; int reg; @@ -106,9 +105,8 @@ l3remap(struct rstmgr_softc *sc, int remap, int enable) return (1); } - if ((OF_getprop(node, "reg", &paddr, sizeof(paddr))) > 0) { - addr = fdt32_to_cpu(paddr); - if (bus_space_map(fdtbus_bs_tag, addr, 0x4, 0, &vaddr) == 0) { + if ((OF_getencprop(node, "reg", &paddr, sizeof(paddr))) > 0) { + if (bus_space_map(fdtbus_bs_tag, paddr, 0x4, 0, &vaddr) == 0) { bus_space_write_4(fdtbus_bs_tag, vaddr, L3REGS_REMAP, reg); return (0); diff --git a/sys/arm/amlogic/aml8726/aml8726_identsoc.c b/sys/arm/amlogic/aml8726/aml8726_identsoc.c index b10ad16..64c6687 100644 --- a/sys/arm/amlogic/aml8726/aml8726_identsoc.c +++ b/sys/arm/amlogic/aml8726/aml8726_identsoc.c @@ -87,7 +87,7 @@ static const struct { }; void -aml8726_identify_soc() +aml8726_identify_soc(void) { int err; struct resource res; diff --git a/sys/arm/amlogic/aml8726/aml8726_machdep.c b/sys/arm/amlogic/aml8726/aml8726_machdep.c index ee2ffd7..0929528 100644 --- a/sys/arm/amlogic/aml8726/aml8726_machdep.c +++ b/sys/arm/amlogic/aml8726/aml8726_machdep.c @@ -31,7 +31,6 @@ __FBSDID("$FreeBSD$"); #include "opt_platform.h" -#define _ARM32_BUS_DMA_PRIVATE #include <sys/param.h> #include <sys/systm.h> #include <sys/bus.h> @@ -57,7 +56,7 @@ vm_offset_t aml8726_aobus_kva_base; #endif static void -aml8726_fixup_busfreq() +aml8726_fixup_busfreq(void) { phandle_t node; pcell_t freq, prop; @@ -165,24 +164,6 @@ platform_devmap_init(void) return (0); } -struct arm32_dma_range * -bus_dma_get_range(void) -{ - - return (NULL); -} - -int -bus_dma_get_range_nb(void) -{ - - return (0); -} - -struct fdt_fixup_entry fdt_fixup_table[] = { - { NULL, NULL } -}; - #ifndef INTRNG #ifndef DEV_GIC static int diff --git a/sys/arm/amlogic/aml8726/aml8726_wdt.c b/sys/arm/amlogic/aml8726/aml8726_wdt.c index cd78c93..1e6cb97 100644 --- a/sys/arm/amlogic/aml8726/aml8726_wdt.c +++ b/sys/arm/amlogic/aml8726/aml8726_wdt.c @@ -290,7 +290,7 @@ EARLY_DRIVER_MODULE(wdt, simplebus, aml8726_wdt_driver, aml8726_wdt_devclass, 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LATE); void -cpu_reset() +cpu_reset(void) { /* Watchdog has not yet been initialized */ diff --git a/sys/arm/annapurna/alpine/alpine_machdep.c b/sys/arm/annapurna/alpine/alpine_machdep.c index acb9ba2..dd26571 100644 --- a/sys/arm/annapurna/alpine/alpine_machdep.c +++ b/sys/arm/annapurna/alpine/alpine_machdep.c @@ -29,7 +29,6 @@ #include <sys/cdefs.h> __FBSDID("$FreeBSD$"); -#define _ARM32_BUS_DMA_PRIVATE #include <sys/param.h> #include <sys/systm.h> #include <sys/bus.h> @@ -131,17 +130,3 @@ platform_devmap_init(void) devmap_add_entry(al_devmap_pa, al_devmap_size); return (0); } - -struct arm32_dma_range * -bus_dma_get_range(void) -{ - - return (NULL); -} - -int -bus_dma_get_range_nb(void) -{ - - return (0); -} diff --git a/sys/arm/annapurna/alpine/common.c b/sys/arm/annapurna/alpine/common.c index cf90556..b03c3a4 100644 --- a/sys/arm/annapurna/alpine/common.c +++ b/sys/arm/annapurna/alpine/common.c @@ -56,9 +56,6 @@ __FBSDID("$FreeBSD$"); #define LOCK 0x00000001 extern bus_addr_t al_devmap_pa; -struct fdt_fixup_entry fdt_fixup_table[] = { - { NULL, NULL } -}; static int alpine_get_wdt_base(uint32_t *pbase, uint32_t *psize); static int alpine_pic_decode_fdt(uint32_t iparent, uint32_t *intr, diff --git a/sys/arm/arm/bus_space_asm_generic.S b/sys/arm/arm/bus_space_asm_generic.S index 9d2b11d..711f921 100644 --- a/sys/arm/arm/bus_space_asm_generic.S +++ b/sys/arm/arm/bus_space_asm_generic.S @@ -36,7 +36,6 @@ */ #include <machine/asm.h> -#include <machine/cpuconf.h> __FBSDID("$FreeBSD$"); /* diff --git a/sys/arm/arm/busdma_machdep-v6.c b/sys/arm/arm/busdma_machdep-v6.c index 0a1331f..5bf4626 100644 --- a/sys/arm/arm/busdma_machdep-v6.c +++ b/sys/arm/arm/busdma_machdep-v6.c @@ -33,7 +33,6 @@ #include <sys/cdefs.h> __FBSDID("$FreeBSD$"); -#define _ARM32_BUS_DMA_PRIVATE #include <sys/param.h> #include <sys/systm.h> #include <sys/malloc.h> @@ -90,14 +89,6 @@ struct bus_dma_tag { bus_dma_lock_t *lockfunc; void *lockfuncarg; struct bounce_zone *bounce_zone; - /* - * DMA range for this tag. If the page doesn't fall within - * one of these ranges, an error is returned. The caller - * may then decide what to do with the transfer. If the - * range pointer is NULL, it is ignored. - */ - struct arm32_dma_range *ranges; - int _nranges; }; struct bounce_page { @@ -402,22 +393,6 @@ must_bounce(bus_dma_tag_t dmat, bus_dmamap_t map, bus_addr_t paddr, return (0); } -static __inline struct arm32_dma_range * -_bus_dma_inrange(struct arm32_dma_range *ranges, int nranges, - bus_addr_t curaddr) -{ - struct arm32_dma_range *dr; - int i; - - for (i = 0, dr = ranges; i < nranges; i++, dr++) { - if (curaddr >= dr->dr_sysbase && - round_page(curaddr) <= (dr->dr_sysbase + dr->dr_len)) - return (dr); - } - - return (NULL); -} - /* * Convenience function for manipulating driver locks from busdma (during * busdma_swi, for example). Drivers that don't provide their own locks @@ -502,8 +477,6 @@ bus_dma_tag_create(bus_dma_tag_t parent, bus_size_t alignment, newtag->flags = flags; newtag->ref_count = 1; /* Count ourself */ newtag->map_count = 0; - newtag->ranges = bus_dma_get_range(); - newtag->_nranges = bus_dma_get_range_nb(); if (lockfunc != NULL) { newtag->lockfunc = lockfunc; newtag->lockfuncarg = lockfuncarg; @@ -987,22 +960,6 @@ _bus_dmamap_addseg(bus_dma_tag_t dmat, bus_dmamap_t map, bus_addr_t curaddr, sgsize = (baddr - curaddr); } - if (dmat->ranges) { - struct arm32_dma_range *dr; - - dr = _bus_dma_inrange(dmat->ranges, dmat->_nranges, - curaddr); - if (dr == NULL) { - _bus_dmamap_unload(dmat, map); - return (0); - } - /* - * In a valid DMA range. Translate the physical - * memory address to an address in the DMA window. - */ - curaddr = (curaddr - dr->dr_sysbase) + dr->dr_busbase; - } - /* * Insert chunk into a segment, coalescing with * previous segment if possible. diff --git a/sys/arm/arm/cpufunc.c b/sys/arm/arm/cpufunc.c index 9a848f5..aae8dc0 100644 --- a/sys/arm/arm/cpufunc.c +++ b/sys/arm/arm/cpufunc.c @@ -57,7 +57,6 @@ __FBSDID("$FreeBSD$"); #include <vm/pmap.h> #include <vm/uma.h> -#include <machine/cpuconf.h> #include <machine/cpufunc.h> #if defined(CPU_XSCALE_81342) @@ -585,7 +584,7 @@ static int arm_dcache_l2_assoc; static int arm_dcache_l2_linesize; static void -get_cachetype_cp15() +get_cachetype_cp15(void) { u_int ctype, isize, dsize, cpuid; u_int clevel, csize, i, sel; @@ -700,7 +699,7 @@ get_cachetype_cp15() */ int -set_cpufuncs() +set_cpufuncs(void) { cputype = cpu_ident(); cputype &= CPU_ID_CPU_MASK; diff --git a/sys/arm/arm/cpuinfo.c b/sys/arm/arm/cpuinfo.c index 2b734f4..8099882 100644 --- a/sys/arm/arm/cpuinfo.c +++ b/sys/arm/arm/cpuinfo.c @@ -111,6 +111,10 @@ cpuinfo_init(void) /* Not yet - CBAR only exist on ARM SMP Cortex A CPUs cpuinfo.cbar = cp15_cbar_get(); */ + if (CPU_CT_FORMAT(cpuinfo.ctr) == CPU_CT_ARMV7) { + cpuinfo.ccsidr = cp15_ccsidr_get(); + cpuinfo.clidr = cp15_clidr_get(); + } /* Test if revidr is implemented */ if (cpuinfo.revidr == cpuinfo.midr) @@ -163,6 +167,7 @@ cpuinfo_get_actlr_modifier(uint32_t *actlr_mask, uint32_t *actlr_set) if (cpuinfo.implementer == CPU_IMPLEMENTER_ARM) { switch (cpuinfo.part_number) { + case CPU_ARCH_CORTEX_A73: case CPU_ARCH_CORTEX_A72: case CPU_ARCH_CORTEX_A57: case CPU_ARCH_CORTEX_A53: diff --git a/sys/arm/arm/db_trace.c b/sys/arm/arm/db_trace.c index 846ad4e..c2b1ed2 100644 --- a/sys/arm/arm/db_trace.c +++ b/sys/arm/arm/db_trace.c @@ -130,7 +130,7 @@ db_stack_trace_cmd(struct unwind_state *state) } void -db_md_list_watchpoints() +db_md_list_watchpoints(void) { dbg_show_watchpoint(); diff --git a/sys/arm/arm/identcpu.c b/sys/arm/arm/identcpu-v4.c index 2b7fec4..769f0b3 100644 --- a/sys/arm/arm/identcpu.c +++ b/sys/arm/arm/identcpu-v4.c @@ -43,18 +43,14 @@ #include <sys/cdefs.h> __FBSDID("$FreeBSD$"); -#include <sys/systm.h> #include <sys/param.h> -#include <sys/malloc.h> -#include <sys/time.h> -#include <sys/proc.h> +#include <sys/systm.h> #include <sys/conf.h> #include <sys/kernel.h> #include <sys/sysctl.h> #include <machine/cpu.h> #include <machine/endian.h> -#include <machine/cpuconf.h> #include <machine/md_var.h> char machine[] = "arm"; @@ -169,39 +165,6 @@ const struct cpuidtab cpuids[] = { { CPU_ID_ARM1026EJS, CPU_CLASS_ARM10EJ, "ARM1026EJ-S", generic_steppings }, - { CPU_ID_CORTEXA5, CPU_CLASS_CORTEXA, "Cortex A5", - generic_steppings }, - { CPU_ID_CORTEXA7, CPU_CLASS_CORTEXA, "Cortex A7", - generic_steppings }, - { CPU_ID_CORTEXA8R1, CPU_CLASS_CORTEXA, "Cortex A8-r1", - generic_steppings }, - { CPU_ID_CORTEXA8R2, CPU_CLASS_CORTEXA, "Cortex A8-r2", - generic_steppings }, - { CPU_ID_CORTEXA8R3, CPU_CLASS_CORTEXA, "Cortex A8-r3", - generic_steppings }, - { CPU_ID_CORTEXA9R1, CPU_CLASS_CORTEXA, "Cortex A9-r1", - generic_steppings }, - { CPU_ID_CORTEXA9R2, CPU_CLASS_CORTEXA, "Cortex A9-r2", - generic_steppings }, - { CPU_ID_CORTEXA9R3, CPU_CLASS_CORTEXA, "Cortex A9-r3", - generic_steppings }, - { CPU_ID_CORTEXA9R4, CPU_CLASS_CORTEXA, "Cortex A9-r4", - generic_steppings }, - { CPU_ID_CORTEXA12R0, CPU_CLASS_CORTEXA, "Cortex A12-r0", - generic_steppings }, - { CPU_ID_CORTEXA15R0, CPU_CLASS_CORTEXA, "Cortex A15-r0", - generic_steppings }, - { CPU_ID_CORTEXA15R1, CPU_CLASS_CORTEXA, "Cortex A15-r1", - generic_steppings }, - { CPU_ID_CORTEXA15R2, CPU_CLASS_CORTEXA, "Cortex A15-r2", - generic_steppings }, - { CPU_ID_CORTEXA15R3, CPU_CLASS_CORTEXA, "Cortex A15-r3", - generic_steppings }, - { CPU_ID_KRAIT300R0, CPU_CLASS_KRAIT, "Krait 300-r0", - generic_steppings }, - { CPU_ID_KRAIT300R1, CPU_CLASS_KRAIT, "Krait 300-r1", - generic_steppings }, - { CPU_ID_80200, CPU_CLASS_XSCALE, "i80200", xscale_steppings }, @@ -248,24 +211,11 @@ const struct cpuidtab cpuids[] = { { CPU_ID_IXP435, CPU_CLASS_XSCALE, "IXP435", ixp425_steppings }, - { CPU_ID_ARM1136JS, CPU_CLASS_ARM11J, "ARM1136J-S", - generic_steppings }, - { CPU_ID_ARM1136JSR1, CPU_CLASS_ARM11J, "ARM1136J-S R1", - generic_steppings }, - { CPU_ID_ARM1176JZS, CPU_CLASS_ARM11J, "ARM1176JZ-S", - generic_steppings }, - { CPU_ID_MV88FR131, CPU_CLASS_MARVELL, "Feroceon 88FR131", generic_steppings }, { CPU_ID_MV88FR571_VD, CPU_CLASS_MARVELL, "Feroceon 88FR571-VD", generic_steppings }, - { CPU_ID_MV88SV581X_V7, CPU_CLASS_MARVELL, "Sheeva 88SV581x", - generic_steppings }, - { CPU_ID_ARM_88SV581X_V7, CPU_CLASS_MARVELL, "Sheeva 88SV581x", - generic_steppings }, - { CPU_ID_MV88SV584X_V7, CPU_CLASS_MARVELL, "Sheeva 88SV584x", - generic_steppings }, { 0, CPU_CLASS_NONE, NULL, NULL } }; @@ -282,10 +232,7 @@ const struct cpu_classtab cpu_classes[] = { { "ARM9EJ-S", "CPU_ARM9E" }, /* CPU_CLASS_ARM9EJS */ { "ARM10E", "CPU_ARM10" }, /* CPU_CLASS_ARM10E */ { "ARM10EJ", "CPU_ARM10" }, /* CPU_CLASS_ARM10EJ */ - { "Cortex-A", "CPU_CORTEXA" }, /* CPU_CLASS_CORTEXA */ - { "Krait", "CPU_KRAIT" }, /* CPU_CLASS_KRAIT */ { "XScale", "CPU_XSCALE_..." }, /* CPU_CLASS_XSCALE */ - { "ARM11J", "CPU_ARM11" }, /* CPU_CLASS_ARM11J */ { "Marvell", "CPU_MARVELL" }, /* CPU_CLASS_MARVELL */ }; @@ -344,50 +291,11 @@ u_int cpu_pfr(int num) return (feat); } -static -void identify_armv7(void) -{ - u_int feature; - - printf("Supported features:"); - /* Get Processor Feature Register 0 */ - feature = cpu_pfr(0); - - if (feature & ARM_PFR0_ARM_ISA_MASK) - printf(" ARM_ISA"); - - if (feature & ARM_PFR0_THUMB2) - printf(" THUMB2"); - else if (feature & ARM_PFR0_THUMB) - printf(" THUMB"); - - if (feature & ARM_PFR0_JAZELLE_MASK) - printf(" JAZELLE"); - - if (feature & ARM_PFR0_THUMBEE_MASK) - printf(" THUMBEE"); - - - /* Get Processor Feature Register 1 */ - feature = cpu_pfr(1); - - if (feature & ARM_PFR1_ARMV4_MASK) - printf(" ARMv4"); - - if (feature & ARM_PFR1_SEC_EXT_MASK) - printf(" Security_Ext"); - - if (feature & ARM_PFR1_MICROCTRL_MASK) - printf(" M_profile"); - - printf("\n"); -} - void identify_arm_cpu(void) { - u_int cpuid, reg, size, sets, ways; - u_int8_t type, linesize, ctrl; + u_int cpuid; + u_int8_t ctrl; int i; ctrl = cpu_get_control(); @@ -413,43 +321,38 @@ identify_arm_cpu(void) printf(" "); - if ((cpuid & CPU_ID_ARCH_MASK) == CPU_ID_CPUID_SCHEME) { - identify_armv7(); - } else { - if (ctrl & CPU_CONTROL_BEND_ENABLE) - printf(" Big-endian"); - else - printf(" Little-endian"); - - switch (cpu_class) { - case CPU_CLASS_ARM9TDMI: - case CPU_CLASS_ARM9ES: - case CPU_CLASS_ARM9EJS: - case CPU_CLASS_ARM10E: - case CPU_CLASS_ARM10EJ: - case CPU_CLASS_XSCALE: - case CPU_CLASS_ARM11J: - case CPU_CLASS_MARVELL: - print_enadis(ctrl & CPU_CONTROL_DC_ENABLE, "DC"); - print_enadis(ctrl & CPU_CONTROL_IC_ENABLE, "IC"); + if (ctrl & CPU_CONTROL_BEND_ENABLE) + printf(" Big-endian"); + else + printf(" Little-endian"); + + switch (cpu_class) { + case CPU_CLASS_ARM9TDMI: + case CPU_CLASS_ARM9ES: + case CPU_CLASS_ARM9EJS: + case CPU_CLASS_ARM10E: + case CPU_CLASS_ARM10EJ: + case CPU_CLASS_XSCALE: + case CPU_CLASS_MARVELL: + print_enadis(ctrl & CPU_CONTROL_DC_ENABLE, "DC"); + print_enadis(ctrl & CPU_CONTROL_IC_ENABLE, "IC"); #ifdef CPU_XSCALE_81342 - print_enadis(ctrl & CPU_CONTROL_L2_ENABLE, "L2"); + print_enadis(ctrl & CPU_CONTROL_L2_ENABLE, "L2"); #endif #if defined(SOC_MV_KIRKWOOD) || defined(SOC_MV_DISCOVERY) - i = sheeva_control_ext(0, 0); - print_enadis(i & MV_WA_ENABLE, "WA"); - print_enadis(i & MV_DC_STREAM_ENABLE, "DC streaming"); - printf("\n "); - print_enadis((i & MV_BTB_DISABLE) == 0, "BTB"); - print_enadis(i & MV_L2_ENABLE, "L2"); - print_enadis((i & MV_L2_PREFETCH_DISABLE) == 0, - "L2 prefetch"); - printf("\n "); + i = sheeva_control_ext(0, 0); + print_enadis(i & MV_WA_ENABLE, "WA"); + print_enadis(i & MV_DC_STREAM_ENABLE, "DC streaming"); + printf("\n "); + print_enadis((i & MV_BTB_DISABLE) == 0, "BTB"); + print_enadis(i & MV_L2_ENABLE, "L2"); + print_enadis((i & MV_L2_PREFETCH_DISABLE) == 0, + "L2 prefetch"); + printf("\n "); #endif - break; - default: - break; - } + break; + default: + break; } print_enadis(ctrl & CPU_CONTROL_WBUF_ENABLE, "WB"); @@ -461,74 +364,22 @@ identify_arm_cpu(void) print_enadis(ctrl & CPU_CONTROL_BPRD_ENABLE, "branch prediction"); printf("\n"); - if (arm_cache_level) { - printf("LoUU:%d LoC:%d LoUIS:%d \n", CPU_CLIDR_LOUU(arm_cache_level) + 1, - arm_cache_loc + 1, CPU_CLIDR_LOUIS(arm_cache_level) + 1); - i = 0; - while (((type = CPU_CLIDR_CTYPE(arm_cache_level, i)) != 0) && i < 7) { - printf("Cache level %d: \n", i + 1); - if (type == CACHE_DCACHE || type == CACHE_UNI_CACHE || - type == CACHE_SEP_CACHE) { - reg = arm_cache_type[2 * i]; - ways = CPUV7_CT_xSIZE_ASSOC(reg) + 1; - sets = CPUV7_CT_xSIZE_SET(reg) + 1; - linesize = 1 << (CPUV7_CT_xSIZE_LEN(reg) + 4); - size = (ways * sets * linesize) / 1024; - - if (type == CACHE_UNI_CACHE) - printf(" %dKB/%dB %d-way unified cache", size, linesize,ways); - else - printf(" %dKB/%dB %d-way data cache", size, linesize, ways); - if (reg & CPUV7_CT_CTYPE_WT) - printf(" WT"); - if (reg & CPUV7_CT_CTYPE_WB) - printf(" WB"); - if (reg & CPUV7_CT_CTYPE_RA) - printf(" Read-Alloc"); - if (reg & CPUV7_CT_CTYPE_WA) - printf(" Write-Alloc"); - printf("\n"); - } - - if (type == CACHE_ICACHE || type == CACHE_SEP_CACHE) { - reg = arm_cache_type[(2 * i) + 1]; - - ways = CPUV7_CT_xSIZE_ASSOC(reg) + 1; - sets = CPUV7_CT_xSIZE_SET(reg) + 1; - linesize = 1 << (CPUV7_CT_xSIZE_LEN(reg) + 4); - size = (ways * sets * linesize) / 1024; - - printf(" %dKB/%dB %d-way instruction cache", size, linesize, ways); - if (reg & CPUV7_CT_CTYPE_WT) - printf(" WT"); - if (reg & CPUV7_CT_CTYPE_WB) - printf(" WB"); - if (reg & CPUV7_CT_CTYPE_RA) - printf(" Read-Alloc"); - if (reg & CPUV7_CT_CTYPE_WA) - printf(" Write-Alloc"); - printf("\n"); - } - i++; - } + /* Print cache info. */ + if (arm_picache_line_size == 0 && arm_pdcache_line_size == 0) + return; + + if (arm_pcache_unified) { + printf(" %dKB/%dB %d-way %s unified cache\n", + arm_pdcache_size / 1024, + arm_pdcache_line_size, arm_pdcache_ways, + wtnames[arm_pcache_type]); } else { - /* Print cache info. */ - if (arm_picache_line_size == 0 && arm_pdcache_line_size == 0) - return; - - if (arm_pcache_unified) { - printf(" %dKB/%dB %d-way %s unified cache\n", - arm_pdcache_size / 1024, - arm_pdcache_line_size, arm_pdcache_ways, - wtnames[arm_pcache_type]); - } else { - printf(" %dKB/%dB %d-way instruction cache\n", - arm_picache_size / 1024, - arm_picache_line_size, arm_picache_ways); - printf(" %dKB/%dB %d-way %s data cache\n", - arm_pdcache_size / 1024, - arm_pdcache_line_size, arm_pdcache_ways, - wtnames[arm_pcache_type]); - } + printf(" %dKB/%dB %d-way instruction cache\n", + arm_picache_size / 1024, + arm_picache_line_size, arm_picache_ways); + printf(" %dKB/%dB %d-way %s data cache\n", + arm_pdcache_size / 1024, + arm_pdcache_line_size, arm_pdcache_ways, + wtnames[arm_pcache_type]); } } diff --git a/sys/arm/arm/identcpu-v6.c b/sys/arm/arm/identcpu-v6.c new file mode 100644 index 0000000..7cc8170 --- /dev/null +++ b/sys/arm/arm/identcpu-v6.c @@ -0,0 +1,360 @@ +/* $NetBSD: cpu.c,v 1.55 2004/02/13 11:36:10 wiz Exp $ */ + +/*- + * Copyright (c) 1995 Mark Brinicombe. + * Copyright (c) 1995 Brini. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Brini. + * 4. The name of the company nor the name of the author may be used to + * endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * RiscBSD kernel project + * + * cpu.c + * + * Probing and configuration for the master CPU + * + * Created : 10/10/95 + */ + +#include <sys/cdefs.h> +__FBSDID("$FreeBSD$"); +#include <sys/param.h> +#include <sys/systm.h> +#include <sys/conf.h> +#include <sys/kernel.h> +#include <sys/sysctl.h> +#include <machine/cpu.h> +#include <machine/md_var.h> + +char machine[] = "arm"; + +SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD, + machine, 0, "Machine class"); + +static char hw_buf[81]; +static int hw_buf_idx; +static bool hw_buf_newline; + +static struct { + int implementer; + int part_number; + char *impl_name; + char *core_name; +} cpu_names[] = { + {CPU_IMPLEMENTER_ARM, CPU_ARCH_ARM1176, "ARM", "ARM1176"}, + {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A5 , "ARM", "Cortex-A5"}, + {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A7 , "ARM", "Cortex-A7"}, + {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A8 , "ARM", "Cortex-A8"}, + {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A9 , "ARM", "Cortex-A9"}, + {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A12, "ARM", "Cortex-A12"}, + {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A15, "ARM", "Cortex-A15"}, + {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A17, "ARM", "Cortex-A17"}, + {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A53, "ARM", "Cortex-A53"}, + {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A57, "ARM", "Cortex-A57"}, + {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A72, "ARM", "Cortex-A72"}, + {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A73, "ARM", "Cortex-A73"}, + + {CPU_IMPLEMENTER_MRVL, CPU_ARCH_SHEEVA_581, "Marwell", "PJ4 v7"}, + {CPU_IMPLEMENTER_MRVL, CPU_ARCH_SHEEVA_584, "Marwell", "PJ4MP v7"}, + + {CPU_IMPLEMENTER_QCOM, CPU_ARCH_KRAIT_300, "Qualcomm", "Krait 300"}, +}; + + +static void +print_v5_cache(void) +{ + uint32_t isize, dsize; + uint32_t multiplier; + int pcache_type; + int pcache_unified; + int picache_size; + int picache_line_size; + int picache_ways; + int pdcache_size; + int pdcache_line_size; + int pdcache_ways; + + pcache_unified = 0; + picache_size = 0 ; + picache_line_size = 0 ; + picache_ways = 0 ; + pdcache_size = 0; + pdcache_line_size = 0; + pdcache_ways = 0; + + if ((cpuinfo.ctr & CPU_CT_S) == 0) + pcache_unified = 1; + + /* + * If you want to know how this code works, go read the ARM ARM. + */ + pcache_type = CPU_CT_CTYPE(cpuinfo.ctr); + + if (pcache_unified == 0) { + isize = CPU_CT_ISIZE(cpuinfo.ctr); + multiplier = (isize & CPU_CT_xSIZE_M) ? 3 : 2; + picache_line_size = 1U << (CPU_CT_xSIZE_LEN(isize) + 3); + if (CPU_CT_xSIZE_ASSOC(isize) == 0) { + if (isize & CPU_CT_xSIZE_M) + picache_line_size = 0; /* not present */ + else + picache_ways = 1; + } else { + picache_ways = multiplier << + (CPU_CT_xSIZE_ASSOC(isize) - 1); + } + picache_size = multiplier << (CPU_CT_xSIZE_SIZE(isize) + 8); + } + + dsize = CPU_CT_DSIZE(cpuinfo.ctr); + multiplier = (dsize & CPU_CT_xSIZE_M) ? 3 : 2; + pdcache_line_size = 1U << (CPU_CT_xSIZE_LEN(dsize) + 3); + if (CPU_CT_xSIZE_ASSOC(dsize) == 0) { + if (dsize & CPU_CT_xSIZE_M) + pdcache_line_size = 0; /* not present */ + else + pdcache_ways = 1; + } else { + pdcache_ways = multiplier << + (CPU_CT_xSIZE_ASSOC(dsize) - 1); + } + pdcache_size = multiplier << (CPU_CT_xSIZE_SIZE(dsize) + 8); + + + /* Print cache info. */ + if (picache_line_size == 0 && pdcache_line_size == 0) + return; + + if (pcache_unified) { + printf(" %dKB/%dB %d-way %s unified cache\n", + pdcache_size / 1024, + pdcache_line_size, pdcache_ways, + pcache_type == 0 ? "WT" : "WB"); + } else { + printf(" %dKB/%dB %d-way instruction cache\n", + picache_size / 1024, + picache_line_size, picache_ways); + printf(" %dKB/%dB %d-way %s data cache\n", + pdcache_size / 1024, + pdcache_line_size, pdcache_ways, + pcache_type == 0 ? "WT" : "WB"); + } +} + +static void +print_v7_cache(void ) +{ + uint32_t type, val, size, sets, ways, linesize; + int i; + + printf("LoUU:%d LoC:%d LoUIS:%d \n", + CPU_CLIDR_LOUU(cpuinfo.clidr) + 1, + CPU_CLIDR_LOC(cpuinfo.clidr) + 1, + CPU_CLIDR_LOUIS(cpuinfo.clidr) + 1); + + for (i = 0; i < 7; i++) { + type = CPU_CLIDR_CTYPE(cpuinfo.clidr, i); + if (type == 0) + break; + printf("Cache level %d:\n", i + 1); + if (type == CACHE_DCACHE || type == CACHE_UNI_CACHE || + type == CACHE_SEP_CACHE) { + cp15_csselr_set(i << 1); + val = cp15_ccsidr_get(); + ways = CPUV7_CT_xSIZE_ASSOC(val) + 1; + sets = CPUV7_CT_xSIZE_SET(val) + 1; + linesize = 1 << (CPUV7_CT_xSIZE_LEN(val) + 4); + size = (ways * sets * linesize) / 1024; + + if (type == CACHE_UNI_CACHE) + printf(" %dKB/%dB %d-way unified cache", + size, linesize,ways); + else + printf(" %dKB/%dB %d-way data cache", + size, linesize, ways); + if (val & CPUV7_CT_CTYPE_WT) + printf(" WT"); + if (val & CPUV7_CT_CTYPE_WB) + printf(" WB"); + if (val & CPUV7_CT_CTYPE_RA) + printf(" Read-Alloc"); + if (val & CPUV7_CT_CTYPE_WA) + printf(" Write-Alloc"); + printf("\n"); + } + + if (type == CACHE_ICACHE || type == CACHE_SEP_CACHE) { + cp15_csselr_set(i << 1 | 1); + val = cp15_ccsidr_get(); + ways = CPUV7_CT_xSIZE_ASSOC(val) + 1; + sets = CPUV7_CT_xSIZE_SET(val) + 1; + linesize = 1 << (CPUV7_CT_xSIZE_LEN(val) + 4); + size = (ways * sets * linesize) / 1024; + printf(" %dKB/%dB %d-way instruction cache", + size, linesize, ways); + if (val & CPUV7_CT_CTYPE_WT) + printf(" WT"); + if (val & CPUV7_CT_CTYPE_WB) + printf(" WB"); + if (val & CPUV7_CT_CTYPE_RA) + printf(" Read-Alloc"); + if (val & CPUV7_CT_CTYPE_WA) + printf(" Write-Alloc"); + printf("\n"); + } + } + cp15_csselr_set(0); +} + +static void +add_cap(char *cap) +{ + int len; + + len = strlen(cap); + + if ((hw_buf_idx + len + 2) >= 79) { + printf("%s,\n", hw_buf); + hw_buf_idx = 0; + hw_buf_newline = true; + } + if (hw_buf_newline) + hw_buf_idx += sprintf(hw_buf + hw_buf_idx, " "); + else + hw_buf_idx += sprintf(hw_buf + hw_buf_idx, ", "); + hw_buf_newline = false; + + + hw_buf_idx += sprintf(hw_buf + hw_buf_idx, "%s", cap); +} + +void +identify_arm_cpu(void) +{ + int i; + u_int val; + + /* + * CPU + */ + for(i = 0; i < nitems(cpu_names); i++) { + if (cpu_names[i].implementer == cpuinfo.implementer && + cpu_names[i].part_number == cpuinfo.part_number) { + printf("CPU: %s %s r%dp%d (ECO: 0x%08X)\n", + cpu_names[i].impl_name, cpu_names[i].core_name, + cpuinfo.revision, cpuinfo.patch, + cpuinfo.midr != cpuinfo.revidr ? + cpuinfo.revidr : 0); + break; + } + + } + if (i >= nitems(cpu_names)) + printf("unknown CPU (ID = 0x%x)\n", cpuinfo.midr); + + printf("CPU Features: \n"); + hw_buf_idx = 0; + hw_buf_newline = true; + + val = (cpuinfo.mpidr >> 4)& 0xF; + if (cpuinfo.mpidr & (1 << 31U)) + add_cap("Multiprocessing"); + val = (cpuinfo.id_pfr0 >> 4)& 0xF; + if (val == 1) + add_cap("Thumb"); + else if (val == 3) + add_cap("Thumb2"); + + val = (cpuinfo.id_pfr1 >> 4)& 0xF; + if (val == 1 || val == 2) + add_cap("Security"); + + val = (cpuinfo.id_pfr1 >> 12)& 0xF; + if (val == 1) + add_cap("Virtualization"); + + val = (cpuinfo.id_pfr1 >> 16)& 0xF; + if (val == 1) + add_cap("Generic Timer"); + + val = (cpuinfo.id_mmfr0 >> 0)& 0xF; + if (val == 2) { + add_cap("VMSAv6"); + } else if (val >= 3) { + add_cap("VMSAv7"); + if (val >= 4) + add_cap("PXN"); + if (val >= 5) + add_cap("LPAE"); + } + + val = (cpuinfo.id_mmfr3 >> 20)& 0xF; + if (val == 1) + add_cap("Coherent Walk"); + + if (hw_buf_idx != 0) + printf("%s\n", hw_buf); + + printf("Optional instructions: \n"); + hw_buf_idx = 0; + hw_buf_newline = true; + val = (cpuinfo.id_isar0 >> 24)& 0xF; + if (val == 1) + add_cap("SDIV/UDIV (Thumb)"); + else if (val == 2) + add_cap("SDIV/UDIV"); + + val = (cpuinfo.id_isar2 >> 20)& 0xF; + if (val == 1 || val == 2) + add_cap("UMULL"); + + val = (cpuinfo.id_isar2 >> 16)& 0xF; + if (val == 1 || val == 2 || val == 3) + add_cap("SMULL"); + + val = (cpuinfo.id_isar2 >> 12)& 0xF; + if (val == 1) + add_cap("MLA"); + + val = (cpuinfo.id_isar3 >> 4)& 0xF; + if (val == 1) + add_cap("SIMD"); + else if (val == 3) + add_cap("SIMD(ext)"); + if (hw_buf_idx != 0) + printf("%s\n", hw_buf); + + /* + * Cache + */ + if (CPU_CT_FORMAT(cpuinfo.ctr) == CPU_CT_ARMV7) + print_v7_cache(); + else + print_v5_cache(); +} diff --git a/sys/arm/arm/locore-v4.S b/sys/arm/arm/locore-v4.S index bd39ae1..afba08e 100644 --- a/sys/arm/arm/locore-v4.S +++ b/sys/arm/arm/locore-v4.S @@ -37,7 +37,6 @@ #include <sys/syscall.h> #include <machine/asm.h> #include <machine/armreg.h> -#include <machine/cpuconf.h> #include <machine/pte-v4.h> __FBSDID("$FreeBSD$"); diff --git a/sys/arm/arm/locore-v6.S b/sys/arm/arm/locore-v6.S index cdca461..fabe450 100644 --- a/sys/arm/arm/locore-v6.S +++ b/sys/arm/arm/locore-v6.S @@ -34,7 +34,6 @@ #include <machine/asmacros.h> #include <machine/armreg.h> #include <machine/sysreg.h> -#include <machine/cpuconf.h> #include <machine/pte-v6.h> __FBSDID("$FreeBSD$"); diff --git a/sys/arm/arm/physmem.c b/sys/arm/arm/physmem.c index f6222c3..ec68c36 100644 --- a/sys/arm/arm/physmem.c +++ b/sys/arm/arm/physmem.c @@ -145,7 +145,7 @@ physmem_dump_tables(int (*prfunc)(const char *, ...)) * Print the contents of the static mapping table. Used for bootverbose. */ void -arm_physmem_print_tables() +arm_physmem_print_tables(void) { physmem_dump_tables(printf); diff --git a/sys/arm/arm/platform.c b/sys/arm/arm/platform.c index 85e60c6..64e8a30 100644 --- a/sys/arm/arm/platform.c +++ b/sys/arm/arm/platform.c @@ -34,7 +34,6 @@ __FBSDID("$FreeBSD$"); * through a previously registered kernel object. */ -#define _ARM32_BUS_DMA_PRIVATE #include <sys/param.h> #include <sys/bus.h> #include <sys/kernel.h> diff --git a/sys/arm/arm/pmap-v6.c b/sys/arm/arm/pmap-v6.c index 3a13e8a..2894c35 100644 --- a/sys/arm/arm/pmap-v6.c +++ b/sys/arm/arm/pmap-v6.c @@ -4806,12 +4806,11 @@ pmap_protect_pte1(pmap_t pmap, pt1_entry_t *pte1p, vm_offset_t sva, ("%s: sva is not 1mpage aligned", __func__)); opte1 = npte1 = pte1_load(pte1p); - if (pte1_is_managed(opte1)) { + if (pte1_is_managed(opte1) && pte1_is_dirty(opte1)) { eva = sva + PTE1_SIZE; for (va = sva, m = PHYS_TO_VM_PAGE(pte1_pa(opte1)); va < eva; va += PAGE_SIZE, m++) - if (pte1_is_dirty(opte1)) - vm_page_dirty(m); + vm_page_dirty(m); } if ((prot & VM_PROT_WRITE) == 0) npte1 |= PTE1_RO | PTE1_NM; diff --git a/sys/arm/arm/stack_machdep.c b/sys/arm/arm/stack_machdep.c index 6d23be6..df232a9 100644 --- a/sys/arm/arm/stack_machdep.c +++ b/sys/arm/arm/stack_machdep.c @@ -27,8 +27,8 @@ #include <sys/cdefs.h> __FBSDID("$FreeBSD$"); -#include <sys/systm.h> #include <sys/param.h> +#include <sys/systm.h> #include <sys/proc.h> #include <sys/stack.h> diff --git a/sys/arm/arm/trap-v4.c b/sys/arm/arm/trap-v4.c index 024c911..7f0adbe 100644 --- a/sys/arm/arm/trap-v4.c +++ b/sys/arm/arm/trap-v4.c @@ -139,11 +139,7 @@ static const struct data_abort data_aborts[] = { {dab_align, "Alignment Fault 3"}, {dab_buserr, "External Linefetch Abort (S)"}, {NULL, "Translation Fault (S)"}, -#if (ARM_MMU_V6 + ARM_MMU_V7) != 0 - {NULL, "Translation Flag Fault"}, -#else {dab_buserr, "External Linefetch Abort (P)"}, -#endif {NULL, "Translation Fault (P)"}, {dab_buserr, "External Non-Linefetch Abort (S)"}, {NULL, "Domain Fault (S)"}, diff --git a/sys/arm/arm/undefined.c b/sys/arm/arm/undefined.c index fec194e6..5dfa0d4 100644 --- a/sys/arm/arm/undefined.c +++ b/sys/arm/arm/undefined.c @@ -165,7 +165,7 @@ gdb_trapper(u_int addr, u_int insn, struct trapframe *frame, int code) static struct undefined_handler gdb_uh; void -undefined_init() +undefined_init(void) { int loop; diff --git a/sys/arm/at91/at91_common.c b/sys/arm/at91/at91_common.c index 49ad065..696161f 100644 --- a/sys/arm/at91/at91_common.c +++ b/sys/arm/at91/at91_common.c @@ -49,10 +49,6 @@ __FBSDID("$FreeBSD$"); extern const struct devmap_entry at91_devmap[]; -struct fdt_fixup_entry fdt_fixup_table[] = { - { NULL, NULL } -}; - #ifndef INTRNG static int fdt_aic_decode_ic(phandle_t node, pcell_t *intr, int *interrupt, int *trig, diff --git a/sys/arm/broadcom/bcm2835/bcm2835_common.c b/sys/arm/broadcom/bcm2835/bcm2835_common.c index 123dce1..7d2ef76 100644 --- a/sys/arm/broadcom/bcm2835/bcm2835_common.c +++ b/sys/arm/broadcom/bcm2835/bcm2835_common.c @@ -46,10 +46,6 @@ __FBSDID("$FreeBSD$"); #include <machine/bus.h> #include <machine/vmparam.h> -struct fdt_fixup_entry fdt_fixup_table[] = { - { NULL, NULL } -}; - #ifndef INTRNG static int fdt_intc_decode_ic(phandle_t node, pcell_t *intr, int *interrupt, int *trig, diff --git a/sys/arm/broadcom/bcm2835/bcm2835_fb.c b/sys/arm/broadcom/bcm2835/bcm2835_fb.c index 58caac2..15746ec 100644 --- a/sys/arm/broadcom/bcm2835/bcm2835_fb.c +++ b/sys/arm/broadcom/bcm2835/bcm2835_fb.c @@ -474,15 +474,15 @@ bcmfb_configure(int flags) if ((root != 0) && (display = fdt_find_compatible(root, "broadcom,bcm2835-fb", 1))) { if (sc->width == 0) { - if ((OF_getprop(display, "broadcom,width", + if ((OF_getencprop(display, "broadcom,width", &cell, sizeof(cell))) > 0) - sc->width = (int)fdt32_to_cpu(cell); + sc->width = cell; } if (sc->height == 0) { if ((OF_getprop(display, "broadcom,height", &cell, sizeof(cell))) > 0) - sc->height = (int)fdt32_to_cpu(cell); + sc->height = cell; } } diff --git a/sys/arm/broadcom/bcm2835/bcm2835_machdep.c b/sys/arm/broadcom/bcm2835/bcm2835_machdep.c index 811c108..840b71b 100644 --- a/sys/arm/broadcom/bcm2835/bcm2835_machdep.c +++ b/sys/arm/broadcom/bcm2835/bcm2835_machdep.c @@ -42,7 +42,6 @@ #include <sys/cdefs.h> __FBSDID("$FreeBSD$"); -#define _ARM32_BUS_DMA_PRIVATE #include <sys/param.h> #include <sys/systm.h> #include <sys/bus.h> @@ -78,13 +77,15 @@ bcm2835_late_init(platform_t plat) system = OF_finddevice("/system"); if (system != 0) { - len = OF_getprop(system, "linux,serial", &cells, sizeof(cells)); + len = OF_getencprop(system, "linux,serial", cells, + sizeof(cells)); if (len > 0) - board_set_serial(fdt64_to_cpu(*((uint64_t *)cells))); + board_set_serial(((uint64_t)cells[0]) << 32 | cells[1]); - len = OF_getprop(system, "linux,revision", &cells, sizeof(cells)); + len = OF_getencprop(system, "linux,revision", cells, + sizeof(cells)); if (len > 0) - board_set_revision(fdt32_to_cpu(*((uint32_t *)cells))); + board_set_revision(cells[0]); } } @@ -113,19 +114,7 @@ bcm2836_devmap_init(platform_t plat) } #endif -struct arm32_dma_range * -bus_dma_get_range(void) -{ - - return (NULL); -} -int -bus_dma_get_range_nb(void) -{ - - return (0); -} void cpu_reset() diff --git a/sys/arm/broadcom/bcm2835/bcm2835_wdog.c b/sys/arm/broadcom/bcm2835/bcm2835_wdog.c index 39b16e3..c1152a2 100644 --- a/sys/arm/broadcom/bcm2835/bcm2835_wdog.c +++ b/sys/arm/broadcom/bcm2835/bcm2835_wdog.c @@ -191,7 +191,7 @@ bcmwd_watchdog_fn(void *private, u_int cmd, int *error) } void -bcmwd_watchdog_reset() +bcmwd_watchdog_reset(void) { if (bcmwd_lsc == NULL) diff --git a/sys/arm/conf/ALLWINNER b/sys/arm/conf/ALLWINNER index b3258e5..ae7e416 100644 --- a/sys/arm/conf/ALLWINNER +++ b/sys/arm/conf/ALLWINNER @@ -32,7 +32,6 @@ options SOC_ALLWINNER_A31S options SOC_ALLWINNER_A83T options SOC_ALLWINNER_H3 -options HZ=100 options SCHED_ULE # ULE scheduler options SMP # Enable multiple cores options PLATFORM diff --git a/sys/arm/conf/ALPINE b/sys/arm/conf/ALPINE index 4160f95..64a9f6a 100644 --- a/sys/arm/conf/ALPINE +++ b/sys/arm/conf/ALPINE @@ -25,7 +25,6 @@ include "../annapurna/alpine/std.alpine" makeoptions MODULES_OVERRIDE="" makeoptions WERROR="-Werror" -options HZ=100 options SCHED_4BSD # 4BSD scheduler options SMP # Enable multiple cores diff --git a/sys/arm/conf/AML8726 b/sys/arm/conf/AML8726 index a90cccf..e41c05a 100644 --- a/sys/arm/conf/AML8726 +++ b/sys/arm/conf/AML8726 @@ -23,7 +23,6 @@ ident AML8726 include "std.armv6" include "../amlogic/aml8726/std.aml8726" -options HZ=100 options SCHED_ULE # ULE scheduler options PRINTF_BUFR_SIZE=128 # Prevent printf output being interspersed. options LINUX_BOOT_ABI diff --git a/sys/arm/conf/ARMADA38X b/sys/arm/conf/ARMADA38X index 3176a81..aa5f23d 100644 --- a/sys/arm/conf/ARMADA38X +++ b/sys/arm/conf/ARMADA38X @@ -19,8 +19,6 @@ options MD_ROOT options ROOTDEVNAME=\"/dev/da0s1a\" options SCHED_ULE # ULE scheduler -#options SCHED_4BSD # 4BSD scheduler - options SMP # Pseudo devices diff --git a/sys/arm/conf/ARMADAXP b/sys/arm/conf/ARMADAXP index 5e107dd..19a11ea 100644 --- a/sys/arm/conf/ARMADAXP +++ b/sys/arm/conf/ARMADAXP @@ -27,7 +27,6 @@ options SOC_MV_ARMADAXP makeoptions WERROR="-Werror" -options HZ=1000 options SCHED_ULE # ULE scheduler options SMP # Enable multiple cores diff --git a/sys/arm/conf/BEAGLEBONE b/sys/arm/conf/BEAGLEBONE index 2fbe219..8010aee 100644 --- a/sys/arm/conf/BEAGLEBONE +++ b/sys/arm/conf/BEAGLEBONE @@ -30,7 +30,6 @@ makeoptions MODULES_EXTRA="dtb/am335x am335x_dmtpps" options INTRNG -options HZ=100 options SCHED_4BSD # 4BSD scheduler options PLATFORM diff --git a/sys/arm/conf/EXYNOS5.common b/sys/arm/conf/EXYNOS5.common index ad42056..b5102dd 100644 --- a/sys/arm/conf/EXYNOS5.common +++ b/sys/arm/conf/EXYNOS5.common @@ -21,7 +21,6 @@ makeoptions WERROR="-Werror" include "std.armv6" -options HZ=100 options SCHED_ULE # ULE scheduler options PREEMPTION # Enable kernel thread preemption options INET # InterNETworking diff --git a/sys/arm/conf/IMX53-QSB b/sys/arm/conf/IMX53-QSB index 5fa907c..8d25ea6 100644 --- a/sys/arm/conf/IMX53-QSB +++ b/sys/arm/conf/IMX53-QSB @@ -22,8 +22,6 @@ include "IMX53" ident IMX53-QSB -options HZ=250 # 4ms scheduling quantum - # required for netbooting #options BOOTP #options BOOTP_COMPAT diff --git a/sys/arm/conf/IMX6 b/sys/arm/conf/IMX6 index 6000566..f834033 100644 --- a/sys/arm/conf/IMX6 +++ b/sys/arm/conf/IMX6 @@ -26,7 +26,6 @@ options INTRNG options SOC_IMX6 -options HZ=500 # Scheduling quantum is 2 milliseconds. options SCHED_ULE # ULE scheduler #options NFSD # Network Filesystem Server options INCLUDE_CONFIG_FILE # Include this file in kernel diff --git a/sys/arm/conf/PANDABOARD b/sys/arm/conf/PANDABOARD index 158a9b7..b98c4b0 100644 --- a/sys/arm/conf/PANDABOARD +++ b/sys/arm/conf/PANDABOARD @@ -30,7 +30,6 @@ hints "PANDABOARD.hints" include "std.armv6" include "../ti/omap4/pandaboard/std.pandaboard" -options HZ=100 options SCHED_ULE # ULE scheduler options PLATFORM options SMP # Enable multiple cores diff --git a/sys/arm/conf/RK3188 b/sys/arm/conf/RK3188 index 7528c0c..7f77159 100644 --- a/sys/arm/conf/RK3188 +++ b/sys/arm/conf/RK3188 @@ -23,7 +23,6 @@ ident RK3188 include "std.armv6" include "../rockchip/std.rk30xx" -options HZ=100 options SCHED_ULE # ULE scheduler options SMP # Enable multiple cores diff --git a/sys/arm/conf/RPI-B b/sys/arm/conf/RPI-B index 5e8aee2..ce408ab 100644 --- a/sys/arm/conf/RPI-B +++ b/sys/arm/conf/RPI-B @@ -26,7 +26,6 @@ include "../broadcom/bcm2835/std.bcm2835" options INTRNG -options HZ=100 options SCHED_4BSD # 4BSD scheduler options PLATFORM diff --git a/sys/arm/conf/RPI2 b/sys/arm/conf/RPI2 index 82293ad..b2dc8f1 100644 --- a/sys/arm/conf/RPI2 +++ b/sys/arm/conf/RPI2 @@ -26,7 +26,6 @@ include "../broadcom/bcm2835/std.bcm2836" options INTRNG -options HZ=100 options SCHED_ULE # ULE scheduler options SMP # Enable multiple cores options PLATFORM diff --git a/sys/arm/conf/SOCKIT.common b/sys/arm/conf/SOCKIT.common index 964c98a..9102002 100644 --- a/sys/arm/conf/SOCKIT.common +++ b/sys/arm/conf/SOCKIT.common @@ -25,7 +25,6 @@ makeoptions MODULES_OVERRIDE="" makeoptions WERROR="-Werror" -options HZ=100 options SCHED_ULE # ULE scheduler options SMP # Enable multiple cores diff --git a/sys/arm/conf/TEGRA124 b/sys/arm/conf/TEGRA124 index 663a948..34e8409 100644 --- a/sys/arm/conf/TEGRA124 +++ b/sys/arm/conf/TEGRA124 @@ -23,7 +23,6 @@ include "../nvidia/tegra124/std.tegra124" ident TEGRA124 -options HZ=100 # Scheduling quantum is 10 milliseconds. options SCHED_ULE # ULE scheduler options PLATFORM # Platform based SoC options PLATFORM_SMP diff --git a/sys/arm/conf/VERSATILEPB b/sys/arm/conf/VERSATILEPB index 63feaff..7cfc5f6 100644 --- a/sys/arm/conf/VERSATILEPB +++ b/sys/arm/conf/VERSATILEPB @@ -29,7 +29,6 @@ makeoptions MODULES_OVERRIDE="" options KERNVIRTADDR=0xc0100000 makeoptions KERNVIRTADDR=0xc0100000 -options HZ=100 options SCHED_4BSD # 4BSD scheduler options LINUX_BOOT_ABI # Process metadata passed from Linux boot loaders diff --git a/sys/arm/conf/VIRT b/sys/arm/conf/VIRT index 007e24c..ad266c7 100644 --- a/sys/arm/conf/VIRT +++ b/sys/arm/conf/VIRT @@ -23,8 +23,7 @@ ident VIRT include "std.armv6" include "../qemu/std.virt" -options HZ=100 -options SCHED_ULE # 4BSD scheduler +options SCHED_ULE # ULE scheduler options PLATFORM options PLATFORM_SMP options SMP # Enable multiple cores diff --git a/sys/arm/conf/VYBRID b/sys/arm/conf/VYBRID index d834b55..2174aee 100644 --- a/sys/arm/conf/VYBRID +++ b/sys/arm/conf/VYBRID @@ -24,7 +24,6 @@ include "../freescale/vybrid/std.vybrid" makeoptions WERROR="-Werror" -options HZ=100 options SCHED_4BSD # 4BSD scheduler #options NANDFS # NAND Filesystem #options SMP # Enable multiple cores diff --git a/sys/arm/freescale/imx/files.imx5 b/sys/arm/freescale/imx/files.imx5 index aaea851..c2214c1 100644 --- a/sys/arm/freescale/imx/files.imx5 +++ b/sys/arm/freescale/imx/files.imx5 @@ -32,7 +32,7 @@ arm/freescale/imx/imx51_ccm.c standard dev/ata/chipsets/ata-fsl.c optional imxata # SDHCI/MMC -arm/freescale/imx/imx_sdhci.c optional sdhci +dev/sdhci/fsl_sdhci.c optional sdhci # USB OH3 controller (1 OTG, 3 EHCI) arm/freescale/imx/imx_nop_usbphy.c optional ehci diff --git a/sys/arm/freescale/imx/files.imx6 b/sys/arm/freescale/imx/files.imx6 index de4ff6e..6fb8e2f 100644 --- a/sys/arm/freescale/imx/files.imx6 +++ b/sys/arm/freescale/imx/files.imx6 @@ -32,7 +32,7 @@ arm/freescale/imx/imx6_ipu.c optional vt # # Optional devices. # -arm/freescale/imx/imx_sdhci.c optional sdhci +dev/sdhci/fsl_sdhci.c optional sdhci arm/freescale/imx/imx_wdog.c optional imxwdt diff --git a/sys/arm/freescale/imx/imx51_ipuv3.c b/sys/arm/freescale/imx/imx51_ipuv3.c index a96b185..b88bb3f 100644 --- a/sys/arm/freescale/imx/imx51_ipuv3.c +++ b/sys/arm/freescale/imx/imx51_ipuv3.c @@ -61,7 +61,6 @@ __FBSDID("$FreeBSD$"); #include <machine/resource.h> #include <machine/intr.h> -#include <dev/fdt/fdt_common.h> #include <dev/ofw/ofw_bus.h> #include <dev/ofw/ofw_bus_subr.h> @@ -313,10 +312,10 @@ ipu3_fb_attach(device_t dev) * On i.MX53, the offset is 0. */ node = ofw_bus_get_node(dev); - if ((OF_getprop(node, "reg", ®, sizeof(reg))) <= 0) + if ((OF_getencprop(node, "reg", ®, sizeof(reg))) <= 0) base = 0; else - base = fdt32_to_cpu(reg) - IPU_CM_BASE(0); + base = reg - IPU_CM_BASE(0); /* map controller registers */ err = bus_space_map(iot, IPU_CM_BASE(base), IPU_CM_SIZE, 0, &ioh); if (err) diff --git a/sys/arm/freescale/imx/imx51_ipuv3_fbd.c b/sys/arm/freescale/imx/imx51_ipuv3_fbd.c index 800244a..4f44e9c 100644 --- a/sys/arm/freescale/imx/imx51_ipuv3_fbd.c +++ b/sys/arm/freescale/imx/imx51_ipuv3_fbd.c @@ -222,10 +222,10 @@ ipu3_fb_attach(device_t dev) * On i.MX53, the offset is 0. */ node = ofw_bus_get_node(dev); - if ((OF_getprop(node, "reg", ®, sizeof(reg))) <= 0) + if ((OF_getencprop(node, "reg", ®, sizeof(reg))) <= 0) base = 0; else - base = fdt32_to_cpu(reg) - IPU_CM_BASE(0); + base = reg - IPU_CM_BASE(0); /* map controller registers */ err = bus_space_map(iot, IPU_CM_BASE(base), IPU_CM_SIZE, 0, &ioh); if (err) diff --git a/sys/arm/freescale/imx/imx6_anatop.c b/sys/arm/freescale/imx/imx6_anatop.c index 62c5a64..689df94 100644 --- a/sys/arm/freescale/imx/imx6_anatop.c +++ b/sys/arm/freescale/imx/imx6_anatop.c @@ -776,7 +776,7 @@ imx6_anatop_probe(device_t dev) } uint32_t -imx6_get_cpu_clock() +imx6_get_cpu_clock(void) { uint32_t corediv, plldiv; diff --git a/sys/arm/freescale/imx/imx6_machdep.c b/sys/arm/freescale/imx/imx6_machdep.c index 2379810..6d2ad22 100644 --- a/sys/arm/freescale/imx/imx6_machdep.c +++ b/sys/arm/freescale/imx/imx6_machdep.c @@ -52,10 +52,6 @@ __FBSDID("$FreeBSD$"); #include "platform_if.h" -struct fdt_fixup_entry fdt_fixup_table[] = { - { NULL, NULL } -}; - static uint32_t gpio1_node; #ifndef INTRNG diff --git a/sys/arm/freescale/imx/imx6_src.c b/sys/arm/freescale/imx/imx6_src.c index 400357a..325c8be 100644 --- a/sys/arm/freescale/imx/imx6_src.c +++ b/sys/arm/freescale/imx/imx6_src.c @@ -70,7 +70,7 @@ WR4(struct src_softc *sc, bus_size_t off, uint32_t val) } int -src_reset_ipu() +src_reset_ipu(void) { uint32_t reg; int timeout = 10000; diff --git a/sys/arm/freescale/imx/imx6_ssi.c b/sys/arm/freescale/imx/imx6_ssi.c index 9000ae3..0f916fe 100644 --- a/sys/arm/freescale/imx/imx6_ssi.c +++ b/sys/arm/freescale/imx/imx6_ssi.c @@ -447,12 +447,12 @@ find_sdma_controller(struct sc_info *sc) if ((len = OF_getproplen(node, "dmas")) <= 0) return (ENXIO); - OF_getprop(node, "dmas", &dts_value, len); + OF_getencprop(node, "dmas", &dts_value, len); - sc->sdma_ev_rx = fdt32_to_cpu(dts_value[1]); - sc->sdma_ev_tx = fdt32_to_cpu(dts_value[5]); + sc->sdma_ev_rx = dts_value[1]; + sc->sdma_ev_tx = dts_value[5]; - sdma_node = OF_node_from_xref(fdt32_to_cpu(dts_value[0])); + sdma_node = OF_node_from_xref(dts_value[0]); sdma_sc = NULL; diff --git a/sys/arm/freescale/imx/imx6_usbphy.c b/sys/arm/freescale/imx/imx6_usbphy.c index a338737..806659b 100644 --- a/sys/arm/freescale/imx/imx6_usbphy.c +++ b/sys/arm/freescale/imx/imx6_usbphy.c @@ -143,6 +143,10 @@ usbphy_attach(device_t dev) bus_write_4(sc->mem_res, CTRL_SET_REG, CTRL_SFTRST); bus_write_4(sc->mem_res, CTRL_CLR_REG, CTRL_SFTRST | CTRL_CLKGATE); + /* Set UTMI+ level 2+3 bits to enable low and full speed devices. */ + bus_write_4(sc->mem_res, CTRL_SET_REG, + CTRL_ENUTMILEVEL2 | CTRL_ENUTMILEVEL3); + /* Power up: clear all bits in the powerdown register. */ bus_write_4(sc->mem_res, PWD_REG, 0); diff --git a/sys/arm/freescale/imx/imx_common.c b/sys/arm/freescale/imx/imx_common.c index c423873..3eb076e 100644 --- a/sys/arm/freescale/imx/imx_common.c +++ b/sys/arm/freescale/imx/imx_common.c @@ -50,10 +50,6 @@ __FBSDID("$FreeBSD$"); #include <machine/bus.h> #include <machine/vmparam.h> -struct fdt_fixup_entry fdt_fixup_table[] = { - { NULL, NULL } -}; - #ifndef INTRNG static int fdt_intc_decode_ic(phandle_t node, pcell_t *intr, int *interrupt, int *trig, diff --git a/sys/arm/freescale/imx/imx_gpio.c b/sys/arm/freescale/imx/imx_gpio.c index 922548e..7da47e6 100644 --- a/sys/arm/freescale/imx/imx_gpio.c +++ b/sys/arm/freescale/imx/imx_gpio.c @@ -728,7 +728,7 @@ imx51_gpio_attach(device_t dev) (READ4(sc, IMX_GPIO_OE_REG) & (1U << i)) ? GPIO_PIN_OUTPUT : GPIO_PIN_INPUT; snprintf(sc->gpio_pins[i].gp_name, GPIOMAXNAME, - "imx_gpio%d.%d", unit, i); + "GPIO%d_IO%02d", unit + 1, i); } #ifdef INTRNG diff --git a/sys/arm/freescale/imx/imx_machdep.c b/sys/arm/freescale/imx/imx_machdep.c index 6ef44a4..12e4172 100644 --- a/sys/arm/freescale/imx/imx_machdep.c +++ b/sys/arm/freescale/imx/imx_machdep.c @@ -29,7 +29,6 @@ #include <sys/cdefs.h> __FBSDID("$FreeBSD$"); -#define _ARM32_BUS_DMA_PRIVATE #include <sys/param.h> #include <sys/systm.h> #include <sys/reboot.h> @@ -54,20 +53,6 @@ SYSCTL_UINT(_hw_imx, OID_AUTO, last_reset_status, CTLFLAG_RD, SYSCTL_STRING(_hw_imx, OID_AUTO, last_reset_reason, CTLFLAG_RD, "unknown", 0, "Last reset reason"); -struct arm32_dma_range * -bus_dma_get_range(void) -{ - - return (NULL); -} - -int -bus_dma_get_range_nb(void) -{ - - return (0); -} - /* * This code which manipulates the watchdog hardware is here to implement * cpu_reset() because the watchdog is the only way for software to reset the @@ -84,11 +69,18 @@ imx_wdog_cpu_reset(vm_offset_t wdcr_physaddr) * Trigger an immediate reset by clearing the SRS bit in the watchdog * control register. The reset happens on the next cycle of the wdog * 32KHz clock, so hang out in a spin loop until the reset takes effect. + * + * Imx6 erratum ERR004346 says the SRS bit has to be cleared twice + * within the same cycle of the 32khz clock to reliably trigger the + * reset. Writing it 3 times in a row ensures at least 2 of the writes + * happen in the same 32k clock cycle. */ if ((pcr = devmap_ptov(wdcr_physaddr, sizeof(*pcr))) == NULL) { printf("cpu_reset() can't find its control register... locking up now."); } else { *pcr &= ~WDOG_CR_SRS; + *pcr &= ~WDOG_CR_SRS; + *pcr &= ~WDOG_CR_SRS; } for (;;) continue; diff --git a/sys/arm/freescale/imx/imx_sdhci.c b/sys/arm/freescale/imx/imx_sdhci.c deleted file mode 100644 index 39c9508..0000000 --- a/sys/arm/freescale/imx/imx_sdhci.c +++ /dev/null @@ -1,917 +0,0 @@ -/*- - * Copyright (c) 2013 Ian Lepore <ian@freebsd.org> - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - */ -#include <sys/cdefs.h> -__FBSDID("$FreeBSD$"); - -/* - * SDHCI driver glue for Freescale i.MX SoC family. - * - * This supports both eSDHC (earlier SoCs) and uSDHC (more recent SoCs). - */ - -#include <sys/param.h> -#include <sys/systm.h> -#include <sys/types.h> -#include <sys/bus.h> -#include <sys/callout.h> -#include <sys/kernel.h> -#include <sys/libkern.h> -#include <sys/lock.h> -#include <sys/malloc.h> -#include <sys/module.h> -#include <sys/mutex.h> -#include <sys/resource.h> -#include <sys/rman.h> -#include <sys/sysctl.h> -#include <sys/taskqueue.h> -#include <sys/time.h> - -#include <machine/bus.h> -#include <machine/resource.h> -#include <machine/intr.h> - -#include <arm/freescale/imx/imx_ccmvar.h> - -#include <dev/ofw/ofw_bus.h> -#include <dev/ofw/ofw_bus_subr.h> - -#include <dev/mmc/bridge.h> -#include <dev/mmc/mmcreg.h> -#include <dev/mmc/mmcbrvar.h> - -#include <dev/sdhci/sdhci.h> -#include "sdhci_if.h" - -struct imx_sdhci_softc { - device_t dev; - struct resource * mem_res; - struct resource * irq_res; - void * intr_cookie; - struct sdhci_slot slot; - struct callout r1bfix_callout; - sbintime_t r1bfix_timeout_at; - uint32_t baseclk_hz; - uint32_t cmd_and_mode; - uint32_t r1bfix_intmask; - boolean_t force_card_present; - uint16_t sdclockreg_freq_bits; - uint8_t r1bfix_type; - uint8_t hwtype; -}; - -#define R1BFIX_NONE 0 /* No fix needed at next interrupt. */ -#define R1BFIX_NODATA 1 /* Synthesize DATA_END for R1B w/o data. */ -#define R1BFIX_AC12 2 /* Wait for busy after auto command 12. */ - -#define HWTYPE_NONE 0 /* Hardware not recognized/supported. */ -#define HWTYPE_ESDHC 1 /* imx5x and earlier. */ -#define HWTYPE_USDHC 2 /* imx6. */ - -/* - * Freescale-specific registers, or in some cases the layout of bits within the - * sdhci-defined register is different on Freescale. These names all begin with - * SDHC_ (not SDHCI_). - */ - -#define SDHC_WTMK_LVL 0x44 /* Watermark Level register. */ -#define USDHC_MIX_CONTROL 0x48 /* Mix(ed) Control register. */ -#define SDHC_VEND_SPEC 0xC0 /* Vendor-specific register. */ -#define SDHC_VEND_FRC_SDCLK_ON (1 << 8) -#define SDHC_VEND_IPGEN (1 << 11) -#define SDHC_VEND_HCKEN (1 << 12) -#define SDHC_VEND_PEREN (1 << 13) - -#define SDHC_PRES_STATE 0x24 -#define SDHC_PRES_CIHB (1 << 0) -#define SDHC_PRES_CDIHB (1 << 1) -#define SDHC_PRES_DLA (1 << 2) -#define SDHC_PRES_SDSTB (1 << 3) -#define SDHC_PRES_IPGOFF (1 << 4) -#define SDHC_PRES_HCKOFF (1 << 5) -#define SDHC_PRES_PEROFF (1 << 6) -#define SDHC_PRES_SDOFF (1 << 7) -#define SDHC_PRES_WTA (1 << 8) -#define SDHC_PRES_RTA (1 << 9) -#define SDHC_PRES_BWEN (1 << 10) -#define SDHC_PRES_BREN (1 << 11) -#define SDHC_PRES_RTR (1 << 12) -#define SDHC_PRES_CINST (1 << 16) -#define SDHC_PRES_CDPL (1 << 18) -#define SDHC_PRES_WPSPL (1 << 19) -#define SDHC_PRES_CLSL (1 << 23) -#define SDHC_PRES_DLSL_SHIFT 24 -#define SDHC_PRES_DLSL_MASK (0xffU << SDHC_PRES_DLSL_SHIFT) - -#define SDHC_PROT_CTRL 0x28 -#define SDHC_PROT_LED (1 << 0) -#define SDHC_PROT_WIDTH_1BIT (0 << 1) -#define SDHC_PROT_WIDTH_4BIT (1 << 1) -#define SDHC_PROT_WIDTH_8BIT (2 << 1) -#define SDHC_PROT_WIDTH_MASK (3 << 1) -#define SDHC_PROT_D3CD (1 << 3) -#define SDHC_PROT_EMODE_BIG (0 << 4) -#define SDHC_PROT_EMODE_HALF (1 << 4) -#define SDHC_PROT_EMODE_LITTLE (2 << 4) -#define SDHC_PROT_EMODE_MASK (3 << 4) -#define SDHC_PROT_SDMA (0 << 8) -#define SDHC_PROT_ADMA1 (1 << 8) -#define SDHC_PROT_ADMA2 (2 << 8) -#define SDHC_PROT_ADMA264 (3 << 8) -#define SDHC_PROT_DMA_MASK (3 << 8) -#define SDHC_PROT_CDTL (1 << 6) -#define SDHC_PROT_CDSS (1 << 7) - -#define SDHC_SYS_CTRL 0x2c -#define SDHC_INT_STATUS 0x30 - -/* - * The clock enable bits exist in different registers for ESDHC vs USDHC, but - * they are the same bits in both cases. The divisor values go into the - * standard sdhci clock register, but in different bit positions and meanings - than the sdhci spec values. - */ -#define SDHC_CLK_IPGEN (1 << 0) -#define SDHC_CLK_HCKEN (1 << 1) -#define SDHC_CLK_PEREN (1 << 2) -#define SDHC_CLK_SDCLKEN (1 << 3) -#define SDHC_CLK_ENABLE_MASK 0x0000000f -#define SDHC_CLK_DIVISOR_MASK 0x000000f0 -#define SDHC_CLK_DIVISOR_SHIFT 4 -#define SDHC_CLK_PRESCALE_MASK 0x0000ff00 -#define SDHC_CLK_PRESCALE_SHIFT 8 - -static struct ofw_compat_data compat_data[] = { - {"fsl,imx6q-usdhc", HWTYPE_USDHC}, - {"fsl,imx6sl-usdhc", HWTYPE_USDHC}, - {"fsl,imx53-esdhc", HWTYPE_ESDHC}, - {"fsl,imx51-esdhc", HWTYPE_ESDHC}, - {NULL, HWTYPE_NONE}, -}; - -static uint16_t imx_sdhc_get_clock(struct imx_sdhci_softc *sc); -static void imx_sdhc_set_clock(struct imx_sdhci_softc *sc, uint16_t val); -static void imx_sdhci_r1bfix_func(void *arg); - -static inline uint32_t -RD4(struct imx_sdhci_softc *sc, bus_size_t off) -{ - - return (bus_read_4(sc->mem_res, off)); -} - -static inline void -WR4(struct imx_sdhci_softc *sc, bus_size_t off, uint32_t val) -{ - - bus_write_4(sc->mem_res, off, val); -} - -static uint8_t -imx_sdhci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off) -{ - struct imx_sdhci_softc *sc = device_get_softc(dev); - uint32_t val32, wrk32; - - /* - * Most of the things in the standard host control register are in the - * hardware's wider protocol control register, but some of the bits are - * moved around. - */ - if (off == SDHCI_HOST_CONTROL) { - wrk32 = RD4(sc, SDHC_PROT_CTRL); - val32 = wrk32 & (SDHCI_CTRL_LED | SDHCI_CTRL_CARD_DET | - SDHCI_CTRL_FORCE_CARD); - switch (wrk32 & SDHC_PROT_WIDTH_MASK) { - case SDHC_PROT_WIDTH_1BIT: - /* Value is already 0. */ - break; - case SDHC_PROT_WIDTH_4BIT: - val32 |= SDHCI_CTRL_4BITBUS; - break; - case SDHC_PROT_WIDTH_8BIT: - val32 |= SDHCI_CTRL_8BITBUS; - break; - } - switch (wrk32 & SDHC_PROT_DMA_MASK) { - case SDHC_PROT_SDMA: - /* Value is already 0. */ - break; - case SDHC_PROT_ADMA1: - /* This value is deprecated, should never appear. */ - break; - case SDHC_PROT_ADMA2: - val32 |= SDHCI_CTRL_ADMA2; - break; - case SDHC_PROT_ADMA264: - val32 |= SDHCI_CTRL_ADMA264; - break; - } - return val32; - } - - /* - * XXX can't find the bus power on/off knob. For now we have to say the - * power is always on and always set to the same voltage. - */ - if (off == SDHCI_POWER_CONTROL) { - return (SDHCI_POWER_ON | SDHCI_POWER_300); - } - - - return ((RD4(sc, off & ~3) >> (off & 3) * 8) & 0xff); -} - -static uint16_t -imx_sdhci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off) -{ - struct imx_sdhci_softc *sc = device_get_softc(dev); - uint32_t val32; - - if (sc->hwtype == HWTYPE_USDHC) { - /* - * The USDHC hardware has nothing in the version register, but - * it's v3 compatible with all our translation code. - */ - if (off == SDHCI_HOST_VERSION) { - return (SDHCI_SPEC_300 << SDHCI_SPEC_VER_SHIFT); - } - /* - * The USDHC hardware moved the transfer mode bits to the mixed - * control register, fetch them from there. - */ - if (off == SDHCI_TRANSFER_MODE) - return (RD4(sc, USDHC_MIX_CONTROL) & 0x37); - - } else if (sc->hwtype == HWTYPE_ESDHC) { - - /* - * The ESDHC hardware has the typical 32-bit combined "command - * and mode" register that we have to cache so that command - * isn't written until after mode. On a read, just retrieve the - * cached values last written. - */ - if (off == SDHCI_TRANSFER_MODE) { - return (sc->cmd_and_mode & 0x0000ffff); - } else if (off == SDHCI_COMMAND_FLAGS) { - return (sc->cmd_and_mode >> 16); - } - } - - /* - * This hardware only manages one slot. Synthesize a slot interrupt - * status register... if there are any enabled interrupts active they - * must be coming from our one and only slot. - */ - if (off == SDHCI_SLOT_INT_STATUS) { - val32 = RD4(sc, SDHCI_INT_STATUS); - val32 &= RD4(sc, SDHCI_SIGNAL_ENABLE); - return (val32 ? 1 : 0); - } - - /* - * Clock bits are scattered into various registers which differ by - * hardware type, complex enough to have their own function. - */ - if (off == SDHCI_CLOCK_CONTROL) { - return (imx_sdhc_get_clock(sc)); - } - - return ((RD4(sc, off & ~3) >> (off & 3) * 8) & 0xffff); -} - -static uint32_t -imx_sdhci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off) -{ - struct imx_sdhci_softc *sc = device_get_softc(dev); - uint32_t val32, wrk32; - - val32 = RD4(sc, off); - - /* - * The hardware leaves the base clock frequency out of the capabilities - * register, but we filled it in by setting slot->max_clk at attach time - * rather than here, because we can't represent frequencies above 63MHz - * in an sdhci 2.0 capabliities register. The timeout clock is the same - * as the active output sdclock; we indicate that with a quirk setting - * so don't populate the timeout frequency bits. - * - * XXX Turn off (for now) features the hardware can do but this driver - * doesn't yet handle (1.8v, suspend/resume, etc). - */ - if (off == SDHCI_CAPABILITIES) { - val32 &= ~SDHCI_CAN_VDD_180; - val32 &= ~SDHCI_CAN_DO_SUSPEND; - val32 |= SDHCI_CAN_DO_8BITBUS; - return (val32); - } - - /* - * The hardware moves bits around in the present state register to make - * room for all 8 data line state bits. To translate, mask out all the - * bits which are not in the same position in both registers (this also - * masks out some Freescale-specific bits in locations defined as - * reserved by sdhci), then shift the data line and retune request bits - * down to their standard locations. - */ - if (off == SDHCI_PRESENT_STATE) { - wrk32 = val32; - val32 &= 0x000F0F07; - val32 |= (wrk32 >> 4) & SDHCI_STATE_DAT_MASK; - val32 |= (wrk32 >> 9) & SDHCI_RETUNE_REQUEST; - if (sc->force_card_present) - val32 |= SDHCI_CARD_PRESENT; - return (val32); - } - - /* - * imx_sdhci_intr() can synthesize a DATA_END interrupt following a - * command with an R1B response, mix it into the hardware status. - */ - if (off == SDHCI_INT_STATUS) { - return (val32 | sc->r1bfix_intmask); - } - - return val32; -} - -static void -imx_sdhci_read_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, - uint32_t *data, bus_size_t count) -{ - struct imx_sdhci_softc *sc = device_get_softc(dev); - - bus_read_multi_4(sc->mem_res, off, data, count); -} - -static void -imx_sdhci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint8_t val) -{ - struct imx_sdhci_softc *sc = device_get_softc(dev); - uint32_t val32; - - /* - * Most of the things in the standard host control register are in the - * hardware's wider protocol control register, but some of the bits are - * moved around. - */ - if (off == SDHCI_HOST_CONTROL) { - val32 = RD4(sc, SDHC_PROT_CTRL); - val32 &= ~(SDHC_PROT_LED | SDHC_PROT_DMA_MASK | - SDHC_PROT_WIDTH_MASK | SDHC_PROT_CDTL | SDHC_PROT_CDSS); - val32 |= (val & SDHCI_CTRL_LED); - if (val & SDHCI_CTRL_8BITBUS) - val32 |= SDHC_PROT_WIDTH_8BIT; - else - val32 |= (val & SDHCI_CTRL_4BITBUS); - val32 |= (val & (SDHCI_CTRL_SDMA | SDHCI_CTRL_ADMA2)) << 4; - val32 |= (val & (SDHCI_CTRL_CARD_DET | SDHCI_CTRL_FORCE_CARD)); - WR4(sc, SDHC_PROT_CTRL, val32); - return; - } - - /* XXX I can't find the bus power on/off knob; do nothing. */ - if (off == SDHCI_POWER_CONTROL) { - return; - } - - val32 = RD4(sc, off & ~3); - val32 &= ~(0xff << (off & 3) * 8); - val32 |= (val << (off & 3) * 8); - - WR4(sc, off & ~3, val32); -} - -static void -imx_sdhci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint16_t val) -{ - struct imx_sdhci_softc *sc = device_get_softc(dev); - uint32_t val32; - - /* - * The clock control stuff is complex enough to have its own function - * that can handle the ESDHC versus USDHC differences. - */ - if (off == SDHCI_CLOCK_CONTROL) { - imx_sdhc_set_clock(sc, val); - return; - } - - /* - * Figure out whether we need to check the DAT0 line for busy status at - * interrupt time. The controller should be doing this, but for some - * reason it doesn't. There are two cases: - * - R1B response with no data transfer should generate a DATA_END (aka - * TRANSFER_COMPLETE) interrupt after waiting for busy, but if - * there's no data transfer there's no DATA_END interrupt. This is - * documented; they seem to think it's a feature. - * - R1B response after Auto-CMD12 appears to not work, even though - * there's a control bit for it (bit 3) in the vendor register. - * When we're starting a command that needs a manual DAT0 line check at - * interrupt time, we leave ourselves a note in r1bfix_type so that we - * can do the extra work in imx_sdhci_intr(). - */ - if (off == SDHCI_COMMAND_FLAGS) { - if (val & SDHCI_CMD_DATA) { - const uint32_t MBAUTOCMD = SDHCI_TRNS_ACMD12 | SDHCI_TRNS_MULTI; - val32 = RD4(sc, USDHC_MIX_CONTROL); - if ((val32 & MBAUTOCMD) == MBAUTOCMD) - sc->r1bfix_type = R1BFIX_AC12; - } else { - if ((val & SDHCI_CMD_RESP_MASK) == SDHCI_CMD_RESP_SHORT_BUSY) { - WR4(sc, SDHCI_INT_ENABLE, slot->intmask | SDHCI_INT_RESPONSE); - WR4(sc, SDHCI_SIGNAL_ENABLE, slot->intmask | SDHCI_INT_RESPONSE); - sc->r1bfix_type = R1BFIX_NODATA; - } - } - } - - /* - * The USDHC hardware moved the transfer mode bits to mixed control; we - * just write them there and we're done. The ESDHC hardware has the - * typical combined cmd-and-mode register that allows only 32-bit - * access, so when writing the mode bits just save them, then later when - * writing the command bits, add in the saved mode bits. - */ - if (sc->hwtype == HWTYPE_USDHC) { - if (off == SDHCI_TRANSFER_MODE) { - val32 = RD4(sc, USDHC_MIX_CONTROL); - val32 &= ~0x3f; - val32 |= val & 0x37; - // XXX acmd23 not supported here (or by sdhci driver) - WR4(sc, USDHC_MIX_CONTROL, val32); - return; - } - } else if (sc->hwtype == HWTYPE_ESDHC) { - if (off == SDHCI_TRANSFER_MODE) { - sc->cmd_and_mode = - (sc->cmd_and_mode & 0xffff0000) | val; - return; - } else if (off == SDHCI_COMMAND_FLAGS) { - sc->cmd_and_mode = - (sc->cmd_and_mode & 0xffff) | (val << 16); - WR4(sc, SDHCI_TRANSFER_MODE, sc->cmd_and_mode); - return; - } - } - - val32 = RD4(sc, off & ~3); - val32 &= ~(0xffff << (off & 3) * 8); - val32 |= ((val & 0xffff) << (off & 3) * 8); - WR4(sc, off & ~3, val32); -} - -static void -imx_sdhci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint32_t val) -{ - struct imx_sdhci_softc *sc = device_get_softc(dev); - - /* Clear synthesized interrupts, then pass the value to the hardware. */ - if (off == SDHCI_INT_STATUS) { - sc->r1bfix_intmask &= ~val; - } - - WR4(sc, off, val); -} - -static void -imx_sdhci_write_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, - uint32_t *data, bus_size_t count) -{ - struct imx_sdhci_softc *sc = device_get_softc(dev); - - bus_write_multi_4(sc->mem_res, off, data, count); -} - -static uint16_t -imx_sdhc_get_clock(struct imx_sdhci_softc *sc) -{ - uint16_t val; - - /* - * Whenever the sdhci driver writes the clock register we save a - * snapshot of just the frequency bits, so that we can play them back - * here on a register read without recalculating the frequency from the - * prescalar and divisor bits in the real register. We'll start with - * those bits, and mix in the clock status and enable bits that come - * from different places depending on which hardware we've got. - */ - val = sc->sdclockreg_freq_bits; - - /* - * The internal clock is always enabled (actually, the hardware manages - * it). Whether the internal clock is stable yet after a frequency - * change comes from the present-state register on both hardware types. - */ - val |= SDHCI_CLOCK_INT_EN; - if (RD4(sc, SDHC_PRES_STATE) & SDHC_PRES_SDSTB) - val |= SDHCI_CLOCK_INT_STABLE; - - /* - * On ESDHC hardware the card bus clock enable is in the usual sdhci - * register but it's a different bit, so transcribe it (note the - * difference between standard SDHCI_ and Freescale SDHC_ prefixes - * here). On USDHC hardware there is a force-on bit, but no force-off - * for the card bus clock (the hardware runs the clock when transfers - * are active no matter what), so we always say the clock is on. - * XXX Maybe we should say it's in whatever state the sdhci driver last - * set it to. - */ - if (sc->hwtype == HWTYPE_ESDHC) { - if (RD4(sc, SDHC_SYS_CTRL) & SDHC_CLK_SDCLKEN) - val |= SDHCI_CLOCK_CARD_EN; - } else { - val |= SDHCI_CLOCK_CARD_EN; - } - - return (val); -} - -static void -imx_sdhc_set_clock(struct imx_sdhci_softc *sc, uint16_t val) -{ - uint32_t divisor, freq, prescale, val32; - - val32 = RD4(sc, SDHCI_CLOCK_CONTROL); - - /* - * Save the frequency-setting bits in SDHCI format so that we can play - * them back in get_clock without complex decoding of hardware regs, - * then deal with the freqency part of the value based on hardware type. - */ - sc->sdclockreg_freq_bits = val & SDHCI_DIVIDERS_MASK; - if (sc->hwtype == HWTYPE_ESDHC) { - /* - * The ESDHC hardware requires the driver to manually start and - * stop the sd bus clock. If the enable bit is not set, turn - * off the clock in hardware and we're done, otherwise decode - * the requested frequency. ESDHC hardware is sdhci 2.0; the - * sdhci driver will use the original 8-bit divisor field and - * the "base / 2^N" divisor scheme. - */ - if ((val & SDHCI_CLOCK_CARD_EN) == 0) { - WR4(sc, SDHCI_CLOCK_CONTROL, val32 & ~SDHC_CLK_SDCLKEN); - return; - - } - divisor = (val >> SDHCI_DIVIDER_SHIFT) & SDHCI_DIVIDER_MASK; - freq = sc->baseclk_hz >> ffs(divisor); - } else { - /* - * The USDHC hardware provides only "force always on" control - * over the sd bus clock, but no way to turn it off. (If a cmd - * or data transfer is in progress the clock is on, otherwise it - * is off.) If the clock is being disabled, we can just return - * now, otherwise we decode the requested frequency. USDHC - * hardware is sdhci 3.0; the sdhci driver will use a 10-bit - * divisor using the "base / 2*N" divisor scheme. - */ - if ((val & SDHCI_CLOCK_CARD_EN) == 0) - return; - divisor = ((val >> SDHCI_DIVIDER_SHIFT) & SDHCI_DIVIDER_MASK) | - ((val >> SDHCI_DIVIDER_HI_SHIFT) & SDHCI_DIVIDER_HI_MASK) << - SDHCI_DIVIDER_MASK_LEN; - if (divisor == 0) - freq = sc->baseclk_hz; - else - freq = sc->baseclk_hz / (2 * divisor); - } - - /* - * Get a prescaler and final divisor to achieve the desired frequency. - */ - for (prescale = 2; freq < sc->baseclk_hz / (prescale * 16);) - prescale <<= 1; - - for (divisor = 1; freq < sc->baseclk_hz / (prescale * divisor);) - ++divisor; - -#ifdef DEBUG - device_printf(sc->dev, - "desired SD freq: %d, actual: %d; base %d prescale %d divisor %d\n", - freq, sc->baseclk_hz / (prescale * divisor), sc->baseclk_hz, - prescale, divisor); -#endif - - /* - * Adjust to zero-based values, and store them to the hardware. - */ - prescale >>= 1; - divisor -= 1; - - val32 &= ~(SDHC_CLK_DIVISOR_MASK | SDHC_CLK_PRESCALE_MASK); - val32 |= divisor << SDHC_CLK_DIVISOR_SHIFT; - val32 |= prescale << SDHC_CLK_PRESCALE_SHIFT; - WR4(sc, SDHCI_CLOCK_CONTROL, val32); -} - -static boolean_t -imx_sdhci_r1bfix_is_wait_done(struct imx_sdhci_softc *sc) -{ - uint32_t inhibit; - - mtx_assert(&sc->slot.mtx, MA_OWNED); - - /* - * Check the DAT0 line status using both the DLA (data line active) and - * CDIHB (data inhibit) bits in the present state register. In theory - * just DLA should do the trick, but in practice it takes both. If the - * DAT0 line is still being held and we're not yet beyond the timeout - * point, just schedule another callout to check again later. - */ - inhibit = RD4(sc, SDHC_PRES_STATE) & (SDHC_PRES_DLA | SDHC_PRES_CDIHB); - - if (inhibit && getsbinuptime() < sc->r1bfix_timeout_at) { - callout_reset_sbt(&sc->r1bfix_callout, SBT_1MS, 0, - imx_sdhci_r1bfix_func, sc, 0); - return (false); - } - - /* - * If we reach this point with the inhibit bits still set, we've got a - * timeout, synthesize a DATA_TIMEOUT interrupt. Otherwise the DAT0 - * line has been released, and we synthesize a DATA_END, and if the type - * of fix needed was on a command-without-data we also now add in the - * original INT_RESPONSE that we suppressed earlier. - */ - if (inhibit) - sc->r1bfix_intmask |= SDHCI_INT_DATA_TIMEOUT; - else { - sc->r1bfix_intmask |= SDHCI_INT_DATA_END; - if (sc->r1bfix_type == R1BFIX_NODATA) - sc->r1bfix_intmask |= SDHCI_INT_RESPONSE; - } - - sc->r1bfix_type = R1BFIX_NONE; - return (true); -} - -static void -imx_sdhci_r1bfix_func(void * arg) -{ - struct imx_sdhci_softc *sc = arg; - boolean_t r1bwait_done; - - mtx_lock(&sc->slot.mtx); - r1bwait_done = imx_sdhci_r1bfix_is_wait_done(sc); - mtx_unlock(&sc->slot.mtx); - if (r1bwait_done) - sdhci_generic_intr(&sc->slot); -} - -static void -imx_sdhci_intr(void *arg) -{ - struct imx_sdhci_softc *sc = arg; - uint32_t intmask; - - mtx_lock(&sc->slot.mtx); - - /* - * Manually check the DAT0 line for R1B response types that the - * controller fails to handle properly. The controller asserts the done - * interrupt while the card is still asserting busy with the DAT0 line. - * - * We check DAT0 immediately because most of the time, especially on a - * read, the card will actually be done by time we get here. If it's - * not, then the wait_done routine will schedule a callout to re-check - * periodically until it is done. In that case we clear the interrupt - * out of the hardware now so that we can present it later when the DAT0 - * line is released. - * - * If we need to wait for the DAT0 line to be released, we set up a - * timeout point 250ms in the future. This number comes from the SD - * spec, which allows a command to take that long. In the real world, - * cards tend to take 10-20ms for a long-running command such as a write - * or erase that spans two pages. - */ - switch (sc->r1bfix_type) { - case R1BFIX_NODATA: - intmask = RD4(sc, SDHC_INT_STATUS) & SDHCI_INT_RESPONSE; - break; - case R1BFIX_AC12: - intmask = RD4(sc, SDHC_INT_STATUS) & SDHCI_INT_DATA_END; - break; - default: - intmask = 0; - break; - } - if (intmask) { - sc->r1bfix_timeout_at = getsbinuptime() + 250 * SBT_1MS; - if (!imx_sdhci_r1bfix_is_wait_done(sc)) { - WR4(sc, SDHC_INT_STATUS, intmask); - bus_barrier(sc->mem_res, SDHC_INT_STATUS, 4, - BUS_SPACE_BARRIER_WRITE); - } - } - - mtx_unlock(&sc->slot.mtx); - sdhci_generic_intr(&sc->slot); -} - -static int -imx_sdhci_get_ro(device_t bus, device_t child) -{ - - return (false); -} - -static int -imx_sdhci_detach(device_t dev) -{ - - return (EBUSY); -} - -static int -imx_sdhci_attach(device_t dev) -{ - struct imx_sdhci_softc *sc = device_get_softc(dev); - int rid, err; - phandle_t node; - - sc->dev = dev; - - sc->hwtype = ofw_bus_search_compatible(dev, compat_data)->ocd_data; - if (sc->hwtype == HWTYPE_NONE) - panic("Impossible: not compatible in imx_sdhci_attach()"); - - rid = 0; - sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, - RF_ACTIVE); - if (!sc->mem_res) { - device_printf(dev, "cannot allocate memory window\n"); - err = ENXIO; - goto fail; - } - - rid = 0; - sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, - RF_ACTIVE); - if (!sc->irq_res) { - device_printf(dev, "cannot allocate interrupt\n"); - err = ENXIO; - goto fail; - } - - if (bus_setup_intr(dev, sc->irq_res, INTR_TYPE_BIO | INTR_MPSAFE, - NULL, imx_sdhci_intr, sc, &sc->intr_cookie)) { - device_printf(dev, "cannot setup interrupt handler\n"); - err = ENXIO; - goto fail; - } - - sc->slot.quirks |= SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK; - - /* - * DMA is not really broken, I just haven't implemented it yet. - */ - sc->slot.quirks |= SDHCI_QUIRK_BROKEN_DMA; - - /* - * Set the buffer watermark level to 128 words (512 bytes) for both read - * and write. The hardware has a restriction that when the read or - * write ready status is asserted, that means you can read exactly the - * number of words set in the watermark register before you have to - * re-check the status and potentially wait for more data. The main - * sdhci driver provides no hook for doing status checking on less than - * a full block boundary, so we set the watermark level to be a full - * block. Reads and writes where the block size is less than the - * watermark size will work correctly too, no need to change the - * watermark for different size blocks. However, 128 is the maximum - * allowed for the watermark, so PIO is limitted to 512 byte blocks - * (which works fine for SD cards, may be a problem for SDIO some day). - * - * XXX need named constants for this stuff. - */ - WR4(sc, SDHC_WTMK_LVL, 0x08800880); - - sc->baseclk_hz = imx_ccm_sdhci_hz(); - sc->slot.max_clk = sc->baseclk_hz; - - /* - * If the slot is flagged with the non-removable property, set our flag - * to always force the SDHCI_CARD_PRESENT bit on. - * - * XXX Workaround for gpio-based card detect... - * - * We don't have gpio support yet. If there's a cd-gpios property just - * force the SDHCI_CARD_PRESENT bit on for now. If there isn't really a - * card there it will fail to probe at the mmc layer and nothing bad - * happens except instantiating an mmcN device for an empty slot. - */ - node = ofw_bus_get_node(dev); - if (OF_hasprop(node, "non-removable")) - sc->force_card_present = true; - else if (OF_hasprop(node, "cd-gpios")) { - /* XXX put real gpio hookup here. */ - sc->force_card_present = true; - } - - callout_init(&sc->r1bfix_callout, 1); - sdhci_init_slot(dev, &sc->slot, 0); - - bus_generic_probe(dev); - bus_generic_attach(dev); - - sdhci_start_slot(&sc->slot); - - return (0); - -fail: - if (sc->intr_cookie) - bus_teardown_intr(dev, sc->irq_res, sc->intr_cookie); - if (sc->irq_res) - bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq_res); - if (sc->mem_res) - bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res); - - return (err); -} - -static int -imx_sdhci_probe(device_t dev) -{ - - if (!ofw_bus_status_okay(dev)) - return (ENXIO); - - switch (ofw_bus_search_compatible(dev, compat_data)->ocd_data) { - case HWTYPE_ESDHC: - device_set_desc(dev, "Freescale eSDHC controller"); - return (BUS_PROBE_DEFAULT); - case HWTYPE_USDHC: - device_set_desc(dev, "Freescale uSDHC controller"); - return (BUS_PROBE_DEFAULT); - default: - break; - } - return (ENXIO); -} - -static device_method_t imx_sdhci_methods[] = { - /* Device interface */ - DEVMETHOD(device_probe, imx_sdhci_probe), - DEVMETHOD(device_attach, imx_sdhci_attach), - DEVMETHOD(device_detach, imx_sdhci_detach), - - /* Bus interface */ - DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar), - DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar), - DEVMETHOD(bus_print_child, bus_generic_print_child), - - /* MMC bridge interface */ - DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios), - DEVMETHOD(mmcbr_request, sdhci_generic_request), - DEVMETHOD(mmcbr_get_ro, imx_sdhci_get_ro), - DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host), - DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host), - - /* SDHCI registers accessors */ - DEVMETHOD(sdhci_read_1, imx_sdhci_read_1), - DEVMETHOD(sdhci_read_2, imx_sdhci_read_2), - DEVMETHOD(sdhci_read_4, imx_sdhci_read_4), - DEVMETHOD(sdhci_read_multi_4, imx_sdhci_read_multi_4), - DEVMETHOD(sdhci_write_1, imx_sdhci_write_1), - DEVMETHOD(sdhci_write_2, imx_sdhci_write_2), - DEVMETHOD(sdhci_write_4, imx_sdhci_write_4), - DEVMETHOD(sdhci_write_multi_4, imx_sdhci_write_multi_4), - - { 0, 0 } -}; - -static devclass_t imx_sdhci_devclass; - -static driver_t imx_sdhci_driver = { - "sdhci_imx", - imx_sdhci_methods, - sizeof(struct imx_sdhci_softc), -}; - -DRIVER_MODULE(sdhci_imx, simplebus, imx_sdhci_driver, imx_sdhci_devclass, 0, 0); -MODULE_DEPEND(sdhci_imx, sdhci, 1, 1, 1); -DRIVER_MODULE(mmc, sdhci_imx, mmc_driver, mmc_devclass, NULL, NULL); -MODULE_DEPEND(sdhci_imx, mmc, 1, 1, 1); diff --git a/sys/arm/freescale/vybrid/vf_common.c b/sys/arm/freescale/vybrid/vf_common.c index 494f5d6..2f17b97 100644 --- a/sys/arm/freescale/vybrid/vf_common.c +++ b/sys/arm/freescale/vybrid/vf_common.c @@ -32,7 +32,6 @@ __FBSDID("$FreeBSD$"); #include <sys/bus.h> #include <sys/kernel.h> -#include <dev/fdt/fdt_common.h> #include <dev/ofw/openfirm.h> #include <machine/bus.h> @@ -44,16 +43,15 @@ void cpu_reset(void) { phandle_t src; - uint32_t addr, paddr; + uint32_t paddr; bus_addr_t vaddr; if (src_swreset() == 0) goto end; src = OF_finddevice("src"); - if ((src != 0) && (OF_getprop(src, "reg", &paddr, sizeof(paddr))) > 0) { - addr = fdt32_to_cpu(paddr); - if (bus_space_map(fdtbus_bs_tag, addr, 0x10, 0, &vaddr) == 0) { + if ((src != 0) && (OF_getencprop(src, "reg", &paddr, sizeof(paddr))) > 0) { + if (bus_space_map(fdtbus_bs_tag, paddr, 0x10, 0, &vaddr) == 0) { bus_space_write_4(fdtbus_bs_tag, vaddr, 0x00, SW_RST); } } @@ -62,10 +60,6 @@ end: while (1); } -struct fdt_fixup_entry fdt_fixup_table[] = { - { NULL, NULL } -}; - #ifndef INTRNG static int fdt_pic_decode_ic(phandle_t node, pcell_t *intr, int *interrupt, int *trig, diff --git a/sys/arm/freescale/vybrid/vf_dcu4.c b/sys/arm/freescale/vybrid/vf_dcu4.c index 34dea46..7fbf4a3 100644 --- a/sys/arm/freescale/vybrid/vf_dcu4.c +++ b/sys/arm/freescale/vybrid/vf_dcu4.c @@ -50,7 +50,6 @@ __FBSDID("$FreeBSD$"); #include <vm/vm.h> #include <vm/pmap.h> -#include <dev/fdt/fdt_common.h> #include <dev/ofw/openfirm.h> #include <dev/ofw/ofw_bus.h> #include <dev/ofw/ofw_bus_subr.h> @@ -246,37 +245,37 @@ get_panel_info(struct dcu_softc *sc, struct panel_info *panel) /* panel size */ if ((len = OF_getproplen(node, "panel-size")) <= 0) return (ENXIO); - OF_getprop(node, "panel-size", &dts_value, len); - panel->width = fdt32_to_cpu(dts_value[0]); - panel->height = fdt32_to_cpu(dts_value[1]); + OF_getencprop(node, "panel-size", dts_value, len); + panel->width = dts_value[0]; + panel->height = dts_value[1]; /* hsync */ if ((len = OF_getproplen(node, "panel-hsync")) <= 0) return (ENXIO); - OF_getprop(node, "panel-hsync", &dts_value, len); - panel->h_back_porch = fdt32_to_cpu(dts_value[0]); - panel->h_pulse_width = fdt32_to_cpu(dts_value[1]); - panel->h_front_porch = fdt32_to_cpu(dts_value[2]); + OF_getencprop(node, "panel-hsync", dts_value, len); + panel->h_back_porch = dts_value[0]; + panel->h_pulse_width = dts_value[1]; + panel->h_front_porch = dts_value[2]; /* vsync */ if ((len = OF_getproplen(node, "panel-vsync")) <= 0) return (ENXIO); - OF_getprop(node, "panel-vsync", &dts_value, len); - panel->v_back_porch = fdt32_to_cpu(dts_value[0]); - panel->v_pulse_width = fdt32_to_cpu(dts_value[1]); - panel->v_front_porch = fdt32_to_cpu(dts_value[2]); + OF_getencprop(node, "panel-vsync", dts_value, len); + panel->v_back_porch = dts_value[0]; + panel->v_pulse_width = dts_value[1]; + panel->v_front_porch = dts_value[2]; /* clk divider */ if ((len = OF_getproplen(node, "panel-clk-div")) <= 0) return (ENXIO); - OF_getprop(node, "panel-clk-div", &dts_value, len); - panel->clk_div = fdt32_to_cpu(dts_value[0]); + OF_getencprop(node, "panel-clk-div", dts_value, len); + panel->clk_div = dts_value[0]; /* backlight pin */ if ((len = OF_getproplen(node, "panel-backlight-pin")) <= 0) return (ENXIO); - OF_getprop(node, "panel-backlight-pin", &dts_value, len); - panel->backlight_pin = fdt32_to_cpu(dts_value[0]); + OF_getencprop(node, "panel-backlight-pin", dts_value, len); + panel->backlight_pin = dts_value[0]; return (0); } diff --git a/sys/arm/freescale/vybrid/vf_edma.c b/sys/arm/freescale/vybrid/vf_edma.c index 9317921..eb6e514 100644 --- a/sys/arm/freescale/vybrid/vf_edma.c +++ b/sys/arm/freescale/vybrid/vf_edma.c @@ -43,7 +43,6 @@ __FBSDID("$FreeBSD$"); #include <sys/timetc.h> #include <sys/watchdog.h> -#include <dev/fdt/fdt_common.h> #include <dev/ofw/openfirm.h> #include <dev/ofw/ofw_bus.h> #include <dev/ofw/ofw_bus_subr.h> @@ -284,8 +283,8 @@ edma_attach(device_t dev) if ((len = OF_getproplen(node, "device-id")) <= 0) return (ENXIO); - OF_getprop(node, "device-id", &dts_value, len); - sc->device_id = fdt32_to_cpu(dts_value); + OF_getencprop(node, "device-id", &dts_value, len); + sc->device_id = dts_value; sc->dma_stop = dma_stop; sc->dma_setup = dma_setup; diff --git a/sys/arm/freescale/vybrid/vf_iomuxc.c b/sys/arm/freescale/vybrid/vf_iomuxc.c index 95711d6..c4e29fe 100644 --- a/sys/arm/freescale/vybrid/vf_iomuxc.c +++ b/sys/arm/freescale/vybrid/vf_iomuxc.c @@ -148,12 +148,12 @@ pinmux_set(struct iomuxc_softc *sc) continue; if ((len = OF_getproplen(child, "iomux_config")) > 0) { - OF_getprop(child, "iomux_config", &iomux_config, len); + OF_getencprop(child, "iomux_config", iomux_config, len); values = len / (sizeof(uint32_t)); for (i = 0; i < values; i += 2) { - pin = fdt32_to_cpu(iomux_config[i]); - pin_cfg = fdt32_to_cpu(iomux_config[i+1]); + pin = iomux_config[i]; + pin_cfg = iomux_config[i+1]; #if 0 device_printf(sc->dev, "Set pin %d to 0x%08x\n", pin, pin_cfg); diff --git a/sys/arm/freescale/vybrid/vf_machdep.c b/sys/arm/freescale/vybrid/vf_machdep.c index d32ba0d..15566a4 100644 --- a/sys/arm/freescale/vybrid/vf_machdep.c +++ b/sys/arm/freescale/vybrid/vf_machdep.c @@ -30,7 +30,6 @@ #include <sys/cdefs.h> __FBSDID("$FreeBSD$"); -#define _ARM32_BUS_DMA_PRIVATE #include <sys/param.h> #include <sys/systm.h> #include <sys/bus.h> @@ -78,17 +77,3 @@ platform_devmap_init(void) return (0); } - -struct arm32_dma_range * -bus_dma_get_range(void) -{ - - return (NULL); -} - -int -bus_dma_get_range_nb(void) -{ - - return (0); -} diff --git a/sys/arm/freescale/vybrid/vf_sai.c b/sys/arm/freescale/vybrid/vf_sai.c index 83f689f..8ff802a 100644 --- a/sys/arm/freescale/vybrid/vf_sai.c +++ b/sys/arm/freescale/vybrid/vf_sai.c @@ -47,7 +47,6 @@ __FBSDID("$FreeBSD$"); #include <dev/sound/chip.h> #include <mixer_if.h> -#include <dev/fdt/fdt_common.h> #include <dev/ofw/openfirm.h> #include <dev/ofw/ofw_bus.h> #include <dev/ofw/ofw_bus_subr.h> @@ -424,19 +423,19 @@ find_edma_controller(struct sc_info *sc) if ((len = OF_getproplen(node, "edma-mux-group")) <= 0) return (ENXIO); - OF_getprop(node, "edma-src-transmit", &dts_value, len); - edma_src_transmit = fdt32_to_cpu(dts_value); - OF_getprop(node, "edma-mux-group", &dts_value, len); - edma_mux_group = fdt32_to_cpu(dts_value); - OF_getprop(node, "edma-controller", &dts_value, len); - edma_node = OF_node_from_xref(fdt32_to_cpu(dts_value)); + OF_getencprop(node, "edma-src-transmit", &dts_value, len); + edma_src_transmit = dts_value; + OF_getencprop(node, "edma-mux-group", &dts_value, len); + edma_mux_group = dts_value; + OF_getencprop(node, "edma-controller", &dts_value, len); + edma_node = OF_node_from_xref(dts_value); if ((len = OF_getproplen(edma_node, "device-id")) <= 0) { return (ENXIO); } - OF_getprop(edma_node, "device-id", &dts_value, len); - edma_device_id = fdt32_to_cpu(dts_value); + OF_getencprop(edma_node, "device-id", &dts_value, len); + edma_device_id = dts_value; edma_sc = NULL; diff --git a/sys/arm/include/atomic.h b/sys/arm/include/atomic.h index 0cf69c9..091e3c1 100644 --- a/sys/arm/include/atomic.h +++ b/sys/arm/include/atomic.h @@ -39,13 +39,10 @@ #ifndef _MACHINE_ATOMIC_H_ #define _MACHINE_ATOMIC_H_ -#include <sys/types.h> #include <machine/armreg.h> #ifndef _KERNEL #include <machine/sysarch.h> -#else -#include <machine/cpuconf.h> #endif #if __ARM_ARCH >= 6 diff --git a/sys/arm/include/bus_dma.h b/sys/arm/include/bus_dma.h index ddf5504..1295118 100644 --- a/sys/arm/include/bus_dma.h +++ b/sys/arm/include/bus_dma.h @@ -72,7 +72,7 @@ #define BUS_DMA_TAG_VALID(t) ((t) != (bus_dma_tag_t)0) -#ifdef _ARM32_BUS_DMA_PRIVATE +#if defined(_ARM32_BUS_DMA_PRIVATE) && __ARM_ARCH < 6 /* * arm32_dma_range * diff --git a/sys/arm/include/cpuconf.h b/sys/arm/include/cpuconf.h deleted file mode 100644 index 24a3b8f..0000000 --- a/sys/arm/include/cpuconf.h +++ /dev/null @@ -1,192 +0,0 @@ -/* $NetBSD: cpuconf.h,v 1.8 2003/09/06 08:55:42 rearnsha Exp $ */ - -/*- - * Copyright (c) 2002 Wasabi Systems, Inc. - * All rights reserved. - * - * Written by Jason R. Thorpe for Wasabi Systems, Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed for the NetBSD Project by - * Wasabi Systems, Inc. - * 4. The name of Wasabi Systems, Inc. may not be used to endorse - * or promote products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * $FreeBSD$ - * - */ - -#ifndef _MACHINE_CPUCONF_H_ -#define _MACHINE_CPUCONF_H_ - -/* - * IF YOU CHANGE THIS FILE, MAKE SURE TO UPDATE THE DEFINITION OF - * "PMAP_NEEDS_PTE_SYNC" IN <arm/arm32/pmap.h> FOR THE CPU TYPE - * YOU ARE ADDING SUPPORT FOR. - */ - -/* - * Step 1: Count the number of CPU types configured into the kernel. - */ -#define CPU_NTYPES (defined(CPU_ARM9) + \ - defined(CPU_ARM9E) + \ - defined(CPU_ARM1176) + \ - defined(CPU_XSCALE_PXA2X0) + \ - defined(CPU_FA526) + \ - defined(CPU_XSCALE_IXP425)) + \ - defined(CPU_CORTEXA) + \ - defined(CPU_KRAIT) + \ - defined(CPU_MV_PJ4B) - -/* - * Step 2: Determine which ARM architecture versions are configured. - */ -#if defined(CPU_ARM9) || defined(CPU_FA526) -#define ARM_ARCH_4 1 -#else -#define ARM_ARCH_4 0 -#endif - -#if (defined(CPU_ARM9E) || \ - defined(CPU_XSCALE_81342) || \ - defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425)) -#define ARM_ARCH_5 1 -#else -#define ARM_ARCH_5 0 -#endif - -#if !defined(ARM_ARCH_6) -#if defined(CPU_ARM1176) -#define ARM_ARCH_6 1 -#else -#define ARM_ARCH_6 0 -#endif -#endif - -#if defined(CPU_CORTEXA) || defined(CPU_KRAIT) || defined(CPU_MV_PJ4B) -#define ARM_ARCH_7A 1 -#else -#define ARM_ARCH_7A 0 -#endif - -#define ARM_NARCH (ARM_ARCH_4 + ARM_ARCH_5 + ARM_ARCH_6 | ARM_ARCH_7A) - -/* - * Compatibility for userland builds that have no CPUTYPE defined. Use the ARCH - * constants predefined by the compiler to define our old-school arch constants. - * This is a stopgap measure to tide us over until the conversion of all code - * to the newer ACLE constants defined by ARM (see acle-compat.h). - */ -#if ARM_NARCH == 0 -#if defined(__ARM_ARCH_4T__) -#undef ARM_ARCH_4 -#undef ARM_NARCH -#define ARM_ARCH_4 1 -#define ARM_NARCH 1 -#define CPU_ARM9 1 -#elif defined(__ARM_ARCH_6ZK__) -#undef ARM_ARCH_6 -#undef ARM_NARCH -#define ARM_ARCH_6 1 -#define ARM_NARCH 1 -#define CPU_ARM1176 1 -#endif -#endif - -#if ARM_NARCH == 0 && !defined(KLD_MODULE) && defined(_KERNEL) -#error ARM_NARCH is 0 -#endif - -#if ARM_ARCH_5 || ARM_ARCH_6 || ARM_ARCH_7A -/* - * We could support Thumb code on v4T, but the lack of clean interworking - * makes that hard. - */ -#define THUMB_CODE -#endif - -/* - * Step 3: Define which MMU classes are configured: - * - * ARM_MMU_MEMC Prehistoric, external memory controller - * and MMU for ARMv2 CPUs. - * - * ARM_MMU_GENERIC Generic ARM MMU, compatible with ARMv4 and v5. - * - * ARM_MMU_V6 ARMv6 MMU. - * - * ARM_MMU_V7 ARMv7 MMU. - * - * ARM_MMU_XSCALE XScale MMU. Compatible with generic ARM - * MMU, but also has several extensions which - * require different PTE layout to use. - */ -#if (defined(CPU_ARM9) || defined(CPU_ARM9E) || defined(CPU_FA526)) -#define ARM_MMU_GENERIC 1 -#else -#define ARM_MMU_GENERIC 0 -#endif - -#if defined(CPU_ARM1176) -#define ARM_MMU_V6 1 -#else -#define ARM_MMU_V6 0 -#endif - -#if defined(CPU_CORTEXA) || defined(CPU_KRAIT) || defined(CPU_MV_PJ4B) -#define ARM_MMU_V7 1 -#else -#define ARM_MMU_V7 0 -#endif - -#if (defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \ - defined(CPU_XSCALE_81342)) -#define ARM_MMU_XSCALE 1 -#else -#define ARM_MMU_XSCALE 0 -#endif - -#define ARM_NMMUS (ARM_MMU_GENERIC + ARM_MMU_V6 + \ - ARM_MMU_V7 + ARM_MMU_XSCALE) -#if ARM_NMMUS == 0 && !defined(KLD_MODULE) && defined(_KERNEL) -#error ARM_NMMUS is 0 -#endif - -/* - * Step 4: Define features that may be present on a subset of CPUs - * - * ARM_XSCALE_PMU Performance Monitoring Unit on 81342 - */ - -#if (defined(CPU_XSCALE_81342)) -#define ARM_XSCALE_PMU 1 -#else -#define ARM_XSCALE_PMU 0 -#endif - -#if defined(CPU_XSCALE_81342) -#define CPU_XSCALE_CORE3 -#endif -#endif /* _MACHINE_CPUCONF_H_ */ diff --git a/sys/arm/include/cpufunc.h b/sys/arm/include/cpufunc.h index 3102b0a..d983add 100644 --- a/sys/arm/include/cpufunc.h +++ b/sys/arm/include/cpufunc.h @@ -48,7 +48,6 @@ #include <sys/types.h> #include <machine/armreg.h> -#include <machine/cpuconf.h> static __inline void breakpoint(void) diff --git a/sys/arm/include/cpuinfo.h b/sys/arm/include/cpuinfo.h index f4db021..41b5e6d 100644 --- a/sys/arm/include/cpuinfo.h +++ b/sys/arm/include/cpuinfo.h @@ -48,13 +48,14 @@ #define CPU_ARCH_CORTEX_A53 0xD03 #define CPU_ARCH_CORTEX_A57 0xD07 #define CPU_ARCH_CORTEX_A72 0xD08 +#define CPU_ARCH_CORTEX_A73 0xD09 /* QCOM */ #define CPU_ARCH_KRAIT_300 0x06F /* MRVL */ -#define CPU_ARCH_SHEEVA_851 0x581 /* PJ4/PJ4B */ +#define CPU_ARCH_SHEEVA_581 0x581 /* PJ4/PJ4B */ #define CPU_ARCH_SHEEVA_584 0x584 /* PJ4B-MP/PJ4C */ struct cpuinfo { @@ -80,8 +81,10 @@ struct cpuinfo { uint32_t id_isar4; uint32_t id_isar5; uint32_t cbar; + uint32_t ccsidr; + uint32_t clidr; - /* Parsed bits of above registers... */ + /* Parsed bits of above registers... */ /* midr */ int implementer; diff --git a/sys/arm/include/pcpu.h b/sys/arm/include/pcpu.h index d3ae30b..33dfb1b 100644 --- a/sys/arm/include/pcpu.h +++ b/sys/arm/include/pcpu.h @@ -32,8 +32,6 @@ #ifdef _KERNEL -#include <machine/cpuconf.h> - #include <sys/_lock.h> #include <sys/_mutex.h> diff --git a/sys/arm/include/pmap-v4.h b/sys/arm/include/pmap-v4.h index cfb675e..9ecfc37 100644 --- a/sys/arm/include/pmap-v4.h +++ b/sys/arm/include/pmap-v4.h @@ -51,7 +51,30 @@ #define _MACHINE_PMAP_V4_H_ #include <machine/pte-v4.h> -#include <machine/cpuconf.h> + +/* + * Define the MMU types we support based on the cpu types. While the code has + * some theoretical support for multiple MMU types in a single kernel, there are + * no actual working configurations that use that feature. + */ +#if (defined(CPU_ARM9) || defined(CPU_ARM9E) || defined(CPU_FA526)) +#define ARM_MMU_GENERIC 1 +#else +#define ARM_MMU_GENERIC 0 +#endif + +#if (defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \ + defined(CPU_XSCALE_81342)) +#define ARM_MMU_XSCALE 1 +#else +#define ARM_MMU_XSCALE 0 +#endif + +#define ARM_NMMUS (ARM_MMU_GENERIC + ARM_MMU_XSCALE) +#if ARM_NMMUS == 0 && !defined(KLD_MODULE) && defined(_KERNEL) +#error ARM_NMMUS is 0 +#endif + /* * Pte related macros */ diff --git a/sys/arm/lpc/lpc_fb.c b/sys/arm/lpc/lpc_fb.c index b2eab8b..e496915 100644 --- a/sys/arm/lpc/lpc_fb.c +++ b/sys/arm/lpc/lpc_fb.c @@ -52,7 +52,6 @@ __FBSDID("$FreeBSD$"); #include <machine/resource.h> #include <machine/intr.h> -#include <dev/fdt/fdt_common.h> #include <dev/ofw/ofw_bus.h> #include <dev/ofw/ofw_bus_subr.h> @@ -280,10 +279,9 @@ lpc_fb_intr(void *arg) static int lpc_fb_fdt_read(phandle_t node, const char *name, uint32_t *ret) { - if (OF_getprop(node, name, ret, sizeof(uint32_t)) <= 0) + if (OF_getencprop(node, name, ret, sizeof(uint32_t)) <= 0) return (ENOENT); - *ret = fdt32_to_cpu(*ret); return (0); } diff --git a/sys/arm/lpc/lpc_gpio.c b/sys/arm/lpc/lpc_gpio.c index 798469d..b062792 100644 --- a/sys/arm/lpc/lpc_gpio.c +++ b/sys/arm/lpc/lpc_gpio.c @@ -518,7 +518,7 @@ lpc_gpio_get_state(device_t dev, int pin, int *state) } void -lpc_gpio_init() +lpc_gpio_init(void) { bus_space_tag_t bst; bus_space_handle_t bsh; diff --git a/sys/arm/lpc/lpc_intc.c b/sys/arm/lpc/lpc_intc.c index db7c300..d26ef90 100644 --- a/sys/arm/lpc/lpc_intc.c +++ b/sys/arm/lpc/lpc_intc.c @@ -227,10 +227,6 @@ lpc_intc_eoi(void *data) } -struct fdt_fixup_entry fdt_fixup_table[] = { - { NULL, NULL } -}; - #ifndef INTRNG static int fdt_pic_decode_ic(phandle_t node, pcell_t *intr, int *interrupt, int *trig, diff --git a/sys/arm/lpc/lpc_timer.c b/sys/arm/lpc/lpc_timer.c index ded53fa..f745cf0 100644 --- a/sys/arm/lpc/lpc_timer.c +++ b/sys/arm/lpc/lpc_timer.c @@ -40,7 +40,6 @@ __FBSDID("$FreeBSD$"); #include <machine/cpu.h> #include <machine/intr.h> -#include <dev/fdt/fdt_common.h> #include <dev/ofw/ofw_bus.h> #include <dev/ofw/ofw_bus_subr.h> @@ -158,7 +157,7 @@ lpc_timer_attach(device_t dev) /* Get PERIPH_CLK encoded in parent bus 'bus-frequency' property */ node = ofw_bus_get_node(dev); - if (OF_getprop(OF_parent(node), "bus-frequency", &freq, + if (OF_getencprop(OF_parent(node), "bus-frequency", &freq, sizeof(pcell_t)) <= 0) { bus_release_resources(dev, lpc_timer_spec, sc->lt_res); bus_teardown_intr(dev, sc->lt_res[2], intrcookie); @@ -166,8 +165,6 @@ lpc_timer_attach(device_t dev) return (ENXIO); } - freq = fdt32_to_cpu(freq); - /* Set desired frequency in event timer and timecounter */ sc->lt_et.et_frequency = (uint64_t)freq; lpc_timecounter.tc_frequency = (uint64_t)freq; diff --git a/sys/arm/mv/gpio.c b/sys/arm/mv/gpio.c index 79b7cc6..6708167 100644 --- a/sys/arm/mv/gpio.c +++ b/sys/arm/mv/gpio.c @@ -113,7 +113,7 @@ struct gpio_ctrl_entry { gpios_phandler_t handler; }; -int mv_handle_gpios_prop(phandle_t ctrl, pcell_t *gpios, int len); +static int mv_handle_gpios_prop(phandle_t ctrl, pcell_t *gpios, int len); int gpio_get_config_from_dt(void); struct gpio_ctrl_entry gpio_controllers[] = { @@ -540,7 +540,7 @@ mv_gpio_value_set(uint32_t pin, uint8_t val) mv_gpio_reg_clear(reg, pin); } -int +static int mv_handle_gpios_prop(phandle_t ctrl, pcell_t *gpios, int len) { pcell_t gpio_cells, pincnt; @@ -554,10 +554,8 @@ mv_handle_gpios_prop(phandle_t ctrl, pcell_t *gpios, int len) /* Node is not a GPIO controller. */ return (ENXIO); - if (OF_getprop(ctrl, "#gpio-cells", &gpio_cells, sizeof(pcell_t)) < 0) + if (OF_getencprop(ctrl, "#gpio-cells", &gpio_cells, sizeof(pcell_t)) < 0) return (ENXIO); - - gpio_cells = fdt32_to_cpu(gpio_cells); if (gpio_cells != 3) return (ENXIO); @@ -567,9 +565,9 @@ mv_handle_gpios_prop(phandle_t ctrl, pcell_t *gpios, int len) if (fdt_regsize(ctrl, &gpio_ctrl, &size)) return (ENXIO); - if (OF_getprop(ctrl, "pin-count", &pincnt, sizeof(pcell_t)) < 0) + if (OF_getencprop(ctrl, "pin-count", &pincnt, sizeof(pcell_t)) < 0) return (ENXIO); - sc.pin_num = fdt32_to_cpu(pincnt); + sc.pin_num = pincnt; /* * Skip controller reference, since controller's phandle is given @@ -579,9 +577,9 @@ mv_handle_gpios_prop(phandle_t ctrl, pcell_t *gpios, int len) gpios += inc; for (t = 0; t < tuples; t++) { - pin = fdt32_to_cpu(gpios[0]); - dir = fdt32_to_cpu(gpios[1]); - flags = fdt32_to_cpu(gpios[2]); + pin = gpios[0]; + dir = gpios[1]; + flags = gpios[2]; mv_gpio_configure(pin, flags); @@ -630,7 +628,7 @@ mv_gpio_init(void) return (ENXIO); /* Get 'gpios' property. */ - OF_getprop(child, "gpios", &gpios, len); + OF_getencprop(child, "gpios", gpios, len); e = (struct gpio_ctrl_entry *)&gpio_controllers; @@ -641,7 +639,7 @@ mv_gpio_init(void) * contain a ref. to a node defining GPIO * controller. */ - ctrl = OF_node_from_xref(fdt32_to_cpu(gpios[0])); + ctrl = OF_node_from_xref(gpios[0]); if (fdt_is_compatible(ctrl, e->compat)) /* Call a handler. */ diff --git a/sys/arm/mv/mv_machdep.c b/sys/arm/mv/mv_machdep.c index a1d7d49..782fcf0 100644 --- a/sys/arm/mv/mv_machdep.c +++ b/sys/arm/mv/mv_machdep.c @@ -146,21 +146,19 @@ moveon: /* * Process 'pin-count' and 'pin-map' props. */ - if (OF_getprop(node, "pin-count", &pin_count, sizeof(pin_count)) <= 0) + if (OF_getencprop(node, "pin-count", &pin_count, sizeof(pin_count)) <= 0) return (ENXIO); - pin_count = fdt32_to_cpu(pin_count); if (pin_count > MPP_PIN_MAX) return (ERANGE); - if (OF_getprop(node, "#pin-cells", &pin_cells, sizeof(pin_cells)) <= 0) + if (OF_getencprop(node, "#pin-cells", &pin_cells, sizeof(pin_cells)) <= 0) pin_cells = MPP_PIN_CELLS; - pin_cells = fdt32_to_cpu(pin_cells); if (pin_cells > MPP_PIN_CELLS) return (ERANGE); tuple_size = sizeof(pcell_t) * pin_cells; bzero(pinmap, sizeof(pinmap)); - len = OF_getprop(node, "pin-map", pinmap, sizeof(pinmap)); + len = OF_getencprop(node, "pin-map", pinmap, sizeof(pinmap)); if (len <= 0) return (ERANGE); if (len % tuple_size) @@ -175,8 +173,8 @@ moveon: bzero(mpp, sizeof(mpp)); pinmap_ptr = pinmap; for (i = 0; i < pins; i++) { - mpp_pin = fdt32_to_cpu(*pinmap_ptr); - mpp_function = fdt32_to_cpu(*(pinmap_ptr + 1)); + mpp_pin = *pinmap_ptr; + mpp_function = *(pinmap_ptr + 1); mpp[mpp_pin] = mpp_function; pinmap_ptr += pin_cells; } @@ -408,12 +406,10 @@ platform_devmap_init(void) if (fdt_is_compatible(child, "mrvl,lbc")) { /* Check available space */ - if (OF_getprop(child, "bank-count", (void *)&bank_count, + if (OF_getencprop(child, "bank-count", &bank_count, sizeof(bank_count)) <= 0) /* If no property, use default value */ bank_count = 1; - else - bank_count = fdt32_to_cpu(bank_count); if ((i + bank_count) >= FDT_DEVMAP_MAX) return (ENOMEM); @@ -432,6 +428,7 @@ platform_devmap_init(void) return (0); } +#if __ARM_ARCH < 6 struct arm32_dma_range * bus_dma_get_range(void) { @@ -445,6 +442,7 @@ bus_dma_get_range_nb(void) return (0); } +#endif #if defined(CPU_MV_PJ4B) #ifdef DDB diff --git a/sys/arm/nvidia/tegra124/tegra124_machdep.c b/sys/arm/nvidia/tegra124/tegra124_machdep.c index 1233a42..d1e3889 100644 --- a/sys/arm/nvidia/tegra124/tegra124_machdep.c +++ b/sys/arm/nvidia/tegra124/tegra124_machdep.c @@ -24,7 +24,6 @@ * SUCH DAMAGE. */ -#define _ARM32_BUS_DMA_PRIVATE #include "opt_platform.h" #include <sys/cdefs.h> @@ -62,24 +61,6 @@ __FBSDID("$FreeBSD$"); PMC_SCRATCH0_MODE_BOOTLOADER | \ PMC_SCRATCH0_MODE_RCM) -struct fdt_fixup_entry fdt_fixup_table[] = { - { NULL, NULL } -}; - -struct arm32_dma_range * -bus_dma_get_range(void) -{ - - return (NULL); -} - -int -bus_dma_get_range_nb(void) -{ - - return (0); -} - static vm_offset_t tegra124_lastaddr(platform_t plat) { diff --git a/sys/arm/nvidia/tegra_efuse.c b/sys/arm/nvidia/tegra_efuse.c index 34e0da0..889c06f 100644 --- a/sys/arm/nvidia/tegra_efuse.c +++ b/sys/arm/nvidia/tegra_efuse.c @@ -237,7 +237,7 @@ tegra_fuse_read_4(int addr) { static void -tegra_efuse_dump_sku() +tegra_efuse_dump_sku(void) { printf(" TEGRA SKU Info:\n"); printf(" chip_id: %u\n", tegra_sku_info.chip_id); diff --git a/sys/arm/qemu/virt_common.c b/sys/arm/qemu/virt_common.c index 03cba30..cda02e5 100644 --- a/sys/arm/qemu/virt_common.c +++ b/sys/arm/qemu/virt_common.c @@ -37,10 +37,6 @@ __FBSDID("$FreeBSD$"); #include <machine/intr.h> -struct fdt_fixup_entry fdt_fixup_table[] = { - { NULL, NULL } -}; - #ifndef INTRNG fdt_pic_decode_t fdt_pic_table[] = { &gic_decode_fdt, diff --git a/sys/arm/qemu/virt_machdep.c b/sys/arm/qemu/virt_machdep.c index d15b97c..8509ca6 100644 --- a/sys/arm/qemu/virt_machdep.c +++ b/sys/arm/qemu/virt_machdep.c @@ -30,7 +30,6 @@ #include <sys/cdefs.h> __FBSDID("$FreeBSD$"); -#define _ARM32_BUS_DMA_PRIVATE #include <sys/param.h> #include <sys/systm.h> #include <sys/devmap.h> @@ -45,20 +44,6 @@ __FBSDID("$FreeBSD$"); #include "platform_if.h" -struct arm32_dma_range * -bus_dma_get_range(void) -{ - - return (NULL); -} - -int -bus_dma_get_range_nb(void) -{ - - return (0); -} - void cpu_reset(void) { diff --git a/sys/arm/rockchip/rk30xx_common.c b/sys/arm/rockchip/rk30xx_common.c index aa66b72..826ebda 100644 --- a/sys/arm/rockchip/rk30xx_common.c +++ b/sys/arm/rockchip/rk30xx_common.c @@ -38,10 +38,6 @@ __FBSDID("$FreeBSD$"); #include <machine/bus.h> #include <machine/vmparam.h> -struct fdt_fixup_entry fdt_fixup_table[] = { - { NULL, NULL } -}; - #ifndef INTRNG static int fdt_aintc_decode_ic(phandle_t node, pcell_t *intr, int *interrupt, int *trig, diff --git a/sys/arm/rockchip/rk30xx_gpio.c b/sys/arm/rockchip/rk30xx_gpio.c index 609eb6a..60dd57b 100644 --- a/sys/arm/rockchip/rk30xx_gpio.c +++ b/sys/arm/rockchip/rk30xx_gpio.c @@ -526,10 +526,8 @@ rk30_gpios_prop_handle(phandle_t ctrl, pcell_t *gpios, int len) if (sc == NULL) return ENXIO; - if (OF_getprop(ctrl, "#gpio-cells", &gpio_cells, sizeof(pcell_t)) < 0) + if (OF_getencprop(ctrl, "#gpio-cells", &gpio_cells, sizeof(pcell_t)) < 0) return (ENXIO); - - gpio_cells = fdt32_to_cpu(gpio_cells); if (gpio_cells != 2) return (ENXIO); @@ -546,9 +544,9 @@ rk30_gpios_prop_handle(phandle_t ctrl, pcell_t *gpios, int len) inc = sizeof(ihandle_t) / sizeof(pcell_t); gpios += inc; for (t = 0; t < tuples; t++) { - pin = fdt32_to_cpu(gpios[0]); - dir = fdt32_to_cpu(gpios[1]); - flags = fdt32_to_cpu(gpios[2]); + pin = gpios[0]; + dir = gpios[1]; + flags = gpios[2]; for (i = 0; i < sc->sc_gpio_npins; i++) { if (sc->sc_gpio_pins[i].gp_pin == pin) @@ -601,7 +599,7 @@ rk30_gpio_init(void) return (ENXIO); /* Get 'gpios' property. */ - OF_getprop(child, "gpios", &gpios, len); + OF_getencprop(child, "gpios", gpios, len); e = (struct gpio_ctrl_entry *)&gpio_controllers; @@ -612,7 +610,7 @@ rk30_gpio_init(void) * contain a ref. to a node defining GPIO * controller. */ - ctrl = OF_node_from_xref(fdt32_to_cpu(gpios[0])); + ctrl = OF_node_from_xref(gpios[0]); if (fdt_is_compatible(ctrl, e->compat)) /* Call a handler. */ diff --git a/sys/arm/rockchip/rk30xx_machdep.c b/sys/arm/rockchip/rk30xx_machdep.c index db34d33..bb37315 100644 --- a/sys/arm/rockchip/rk30xx_machdep.c +++ b/sys/arm/rockchip/rk30xx_machdep.c @@ -34,7 +34,6 @@ #include <sys/cdefs.h> __FBSDID("$FreeBSD$"); -#define _ARM32_BUS_DMA_PRIVATE #include <sys/param.h> #include <sys/systm.h> #include <sys/bus.h> @@ -92,20 +91,6 @@ platform_devmap_init(void) return (0); } -struct arm32_dma_range * -bus_dma_get_range(void) -{ - - return (NULL); -} - -int -bus_dma_get_range_nb(void) -{ - - return (0); -} - void cpu_reset() { diff --git a/sys/arm/rockchip/rk30xx_wdog.c b/sys/arm/rockchip/rk30xx_wdog.c index 32ef5bd..47d2b1c 100644 --- a/sys/arm/rockchip/rk30xx_wdog.c +++ b/sys/arm/rockchip/rk30xx_wdog.c @@ -171,7 +171,7 @@ rk30_wd_watchdog_fn(void *private, u_int cmd, int *error) } void -rk30_wd_watchdog_reset() +rk30_wd_watchdog_reset(void) { bus_space_handle_t bsh; diff --git a/sys/arm/samsung/exynos/exynos5_common.c b/sys/arm/samsung/exynos/exynos5_common.c index b91e083..04021c1 100644 --- a/sys/arm/samsung/exynos/exynos5_common.c +++ b/sys/arm/samsung/exynos/exynos5_common.c @@ -49,10 +49,6 @@ cpu_reset(void) while (1); } -struct fdt_fixup_entry fdt_fixup_table[] = { - { NULL, NULL } -}; - #ifndef INTRNG static int fdt_pic_decode_ic(phandle_t node, pcell_t *intr, int *interrupt, int *trig, diff --git a/sys/arm/samsung/exynos/exynos5_machdep.c b/sys/arm/samsung/exynos/exynos5_machdep.c index 6483a7a..76a5af1 100644 --- a/sys/arm/samsung/exynos/exynos5_machdep.c +++ b/sys/arm/samsung/exynos/exynos5_machdep.c @@ -30,7 +30,6 @@ #include <sys/cdefs.h> __FBSDID("$FreeBSD$"); -#define _ARM32_BUS_DMA_PRIVATE #include <sys/param.h> #include <sys/systm.h> #include <sys/bus.h> @@ -83,17 +82,3 @@ platform_devmap_init(void) return (0); } - -struct arm32_dma_range * -bus_dma_get_range(void) -{ - - return (NULL); -} - -int -bus_dma_get_range_nb(void) -{ - - return (0); -} diff --git a/sys/arm/ti/am335x/am335x_dmtpps.c b/sys/arm/ti/am335x/am335x_dmtpps.c index 6ed9bd5..2c4e634 100644 --- a/sys/arm/ti/am335x/am335x_dmtpps.c +++ b/sys/arm/ti/am335x/am335x_dmtpps.c @@ -163,7 +163,7 @@ dmtpps_translate_nickname(const char *nick) * fails that IS an error, return -1. */ static int -dmtpps_find_tmr_num_by_tunable() +dmtpps_find_tmr_num_by_tunable(void) { struct padinfo *pi; char iname[20]; @@ -201,7 +201,7 @@ dmtpps_find_tmr_num_by_tunable() * input pin. If so, return the timer number, if not return 0. */ static int -dmtpps_find_tmr_num_by_padconf() +dmtpps_find_tmr_num_by_padconf(void) { int err; unsigned int padstate; @@ -225,7 +225,7 @@ dmtpps_find_tmr_num_by_padconf() * configuration. This is done just once, the first time probe() runs. */ static int -dmtpps_find_tmr_num() +dmtpps_find_tmr_num(void) { int tmr_num; @@ -463,6 +463,14 @@ dmtpps_attach(device_t dev) sc->tmr_num = ti_hwmods_get_unit(dev, "timer"); snprintf(sc->tmr_name, sizeof(sc->tmr_name), "DMTimer%d", sc->tmr_num); + /* + * Configure the timer pulse/capture pin to input/capture mode. This is + * required in addition to configuring the pin as input with the pinmux + * controller (which was done via fdt data or tunable at probe time). + */ + sc->tclr = DMT_TCLR_GPO_CFG; + DMTIMER_WRITE4(sc, DMT_TCLR, sc->tclr); + /* Set up timecounter hardware, start it. */ DMTIMER_WRITE4(sc, DMT_TSICR, DMT_TSICR_RESET); while (DMTIMER_READ4(sc, DMT_TIOCP_CFG) & DMT_TIOCP_RESET) diff --git a/sys/arm/ti/am335x/am335x_dmtreg.h b/sys/arm/ti/am335x/am335x_dmtreg.h index 8a9d637..f2ef54d 100644 --- a/sys/arm/ti/am335x/am335x_dmtreg.h +++ b/sys/arm/ti/am335x/am335x_dmtreg.h @@ -62,7 +62,7 @@ #define DMT_TCLR_TRGMODE_BOTH (2 << 10) /* Trigger on match + ovflow */ #define DMT_TCLR_PWM_PTOGGLE (1 << 12) /* PWM toggles */ #define DMT_TCLR_CAP_MODE_2ND (1 << 13) /* Capture second event mode */ -#define DMT_TCLR_GPO_CFG (1 << 14) /* (no descr in datasheet) */ +#define DMT_TCLR_GPO_CFG (1 << 14) /* Tmr pin conf, 0=out, 1=in */ #define DMT_TCRR 0x3C /* Counter Register */ #define DMT_TLDR 0x40 /* Load Reg */ #define DMT_TTGR 0x44 /* Trigger Reg */ diff --git a/sys/arm/ti/am335x/am335x_lcd.c b/sys/arm/ti/am335x/am335x_lcd.c index 8121ef5..c23aa24 100644 --- a/sys/arm/ti/am335x/am335x_lcd.c +++ b/sys/arm/ti/am335x/am335x_lcd.c @@ -359,13 +359,13 @@ am335x_read_property(device_t dev, phandle_t node, const char *name, uint32_t *v { pcell_t cell; - if ((OF_getprop(node, name, &cell, sizeof(cell))) <= 0) { + if ((OF_getencprop(node, name, &cell, sizeof(cell))) <= 0) { device_printf(dev, "missing '%s' attribute in LCD panel info\n", name); return (ENXIO); } - *val = fdt32_to_cpu(cell); + *val = cell; return (0); } diff --git a/sys/arm/ti/am335x/am335x_lcd_syscons.c b/sys/arm/ti/am335x/am335x_lcd_syscons.c index 2cbf2fc..e8ab873 100644 --- a/sys/arm/ti/am335x/am335x_lcd_syscons.c +++ b/sys/arm/ti/am335x/am335x_lcd_syscons.c @@ -383,13 +383,13 @@ am335x_syscons_configure(int flags) root = OF_finddevice("/"); if ((root != 0) && (display = am335x_syscons_find_panel_node(root))) { - if ((OF_getprop(display, "panel_width", - &cell, sizeof(cell))) > 0) - va_sc->width = (int)fdt32_to_cpu(cell); + if ((OF_getencprop(display, "panel_width", &cell, + sizeof(cell))) > 0) + va_sc->width = cell; - if ((OF_getprop(display, "panel_height", - &cell, sizeof(cell))) > 0) - va_sc->height = (int)fdt32_to_cpu(cell); + if ((OF_getencprop(display, "panel_height", &cell, + sizeof(cell))) > 0) + va_sc->height = cell; } if (va_sc->width == 0) diff --git a/sys/arm/ti/ti_adc.c b/sys/arm/ti/ti_adc.c index 154cd78..2b49789 100644 --- a/sys/arm/ti/ti_adc.c +++ b/sys/arm/ti/ti_adc.c @@ -49,7 +49,6 @@ __FBSDID("$FreeBSD$"); #include <machine/bus.h> -#include <dev/fdt/fdt_common.h> #include <dev/ofw/openfirm.h> #include <dev/ofw/ofw_bus.h> #include <dev/ofw/ofw_bus_subr.h> @@ -767,14 +766,17 @@ ti_adc_attach(device_t dev) /* Read "tsc" node properties */ child = ofw_bus_find_child(node, "tsc"); if (child != 0 && OF_hasprop(child, "ti,wires")) { - if ((OF_getprop(child, "ti,wires", &cell, sizeof(cell))) > 0) - sc->sc_tsc_wires = fdt32_to_cpu(cell); - if ((OF_getprop(child, "ti,coordinate-readouts", &cell, sizeof(cell))) > 0) - sc->sc_coord_readouts = fdt32_to_cpu(cell); - if ((OF_getprop(child, "ti,x-plate-resistance", &cell, sizeof(cell))) > 0) - sc->sc_x_plate_resistance = fdt32_to_cpu(cell); - if ((OF_getprop(child, "ti,charge-delay", &cell, sizeof(cell))) > 0) - sc->sc_charge_delay = fdt32_to_cpu(cell); + if ((OF_getencprop(child, "ti,wires", &cell, sizeof(cell))) > 0) + sc->sc_tsc_wires = cell; + if ((OF_getencprop(child, "ti,coordinate-readouts", &cell, + sizeof(cell))) > 0) + sc->sc_coord_readouts = cell; + if ((OF_getencprop(child, "ti,x-plate-resistance", &cell, + sizeof(cell))) > 0) + sc->sc_x_plate_resistance = cell; + if ((OF_getencprop(child, "ti,charge-delay", &cell, + sizeof(cell))) > 0) + sc->sc_charge_delay = cell; nwire_configs = OF_getencprop_alloc(child, "ti,wire-config", sizeof(*wire_configs), (void **)&wire_configs); if (nwire_configs != sc->sc_tsc_wires) { diff --git a/sys/arm/ti/ti_common.c b/sys/arm/ti/ti_common.c index 41c5a72..64a7830 100644 --- a/sys/arm/ti/ti_common.c +++ b/sys/arm/ti/ti_common.c @@ -49,10 +49,6 @@ __FBSDID("$FreeBSD$"); #include <machine/intr.h> #include <machine/vmparam.h> -struct fdt_fixup_entry fdt_fixup_table[] = { - { NULL, NULL } -}; - #ifndef INTRNG #ifdef SOC_TI_AM335X static int diff --git a/sys/arm/ti/ti_machdep.c b/sys/arm/ti/ti_machdep.c index f8d5395..907b18b 100644 --- a/sys/arm/ti/ti_machdep.c +++ b/sys/arm/ti/ti_machdep.c @@ -40,7 +40,6 @@ #include <sys/cdefs.h> __FBSDID("$FreeBSD$"); -#define _ARM32_BUS_DMA_PRIVATE #include <sys/param.h> #include <sys/systm.h> #include <sys/bus.h> @@ -96,20 +95,6 @@ ti_am335x_devmap_init(platform_t plat) } #endif -struct arm32_dma_range * -bus_dma_get_range(void) -{ - - return (NULL); -} - -int -bus_dma_get_range_nb(void) -{ - - return (0); -} - void cpu_reset() { diff --git a/sys/arm/ti/ti_sdhci.c b/sys/arm/ti/ti_sdhci.c index a24e693..16fa956 100644 --- a/sys/arm/ti/ti_sdhci.c +++ b/sys/arm/ti/ti_sdhci.c @@ -44,7 +44,6 @@ __FBSDID("$FreeBSD$"); #include <machine/resource.h> #include <machine/intr.h> -#include <dev/fdt/fdt_common.h> #include <dev/ofw/ofw_bus.h> #include <dev/ofw/ofw_bus_subr.h> @@ -53,6 +52,7 @@ __FBSDID("$FreeBSD$"); #include <dev/mmc/mmcbrvar.h> #include <dev/sdhci/sdhci.h> +#include <dev/sdhci/sdhci_fdt_gpio.h> #include "sdhci_if.h" #include <arm/ti/ti_cpuid.h> @@ -62,7 +62,7 @@ __FBSDID("$FreeBSD$"); struct ti_sdhci_softc { device_t dev; - device_t gpio_dev; + struct sdhci_fdt_gpio * gpio; struct resource * mem_res; struct resource * irq_res; void * intr_cookie; @@ -71,11 +71,11 @@ struct ti_sdhci_softc { uint32_t mmchs_reg_off; uint32_t sdhci_reg_off; uint32_t baseclk_hz; - uint32_t wp_gpio_pin; uint32_t cmd_and_mode; uint32_t sdhci_clkdiv; boolean_t disable_highspeed; boolean_t force_card_present; + boolean_t disable_readonly; }; /* @@ -363,20 +363,27 @@ static int ti_sdhci_get_ro(device_t brdev, device_t reqdev) { struct ti_sdhci_softc *sc = device_get_softc(brdev); - unsigned int readonly = 0; - /* If a gpio pin is configured, read it. */ - if (sc->gpio_dev != NULL) { - GPIO_PIN_GET(sc->gpio_dev, sc->wp_gpio_pin, &readonly); - } + if (sc->disable_readonly) + return (0); - return (readonly); + return (sdhci_fdt_gpio_get_readonly(sc->gpio)); +} + +static bool +ti_sdhci_get_card_present(device_t dev, struct sdhci_slot *slot) +{ + struct ti_sdhci_softc *sc = device_get_softc(dev); + + return (sdhci_fdt_gpio_get_present(sc->gpio)); } static int ti_sdhci_detach(device_t dev) { + /* sdhci_fdt_gpio_teardown(sc->gpio); */ + return (EBUSY); } @@ -503,25 +510,6 @@ ti_sdhci_attach(device_t dev) } /* - * See if we've got a GPIO-based write detect pin. This is not the - * standard documented property for this, we added it in freebsd. - */ - if ((OF_getprop(node, "mmchs-wp-gpio-pin", &prop, sizeof(prop))) <= 0) - sc->wp_gpio_pin = 0xffffffff; - else - sc->wp_gpio_pin = fdt32_to_cpu(prop); - - if (sc->wp_gpio_pin != 0xffffffff) { - sc->gpio_dev = devclass_get_device(devclass_find("gpio"), 0); - if (sc->gpio_dev == NULL) - device_printf(dev, "Error: No GPIO device, " - "Write Protect pin will not function\n"); - else - GPIO_PIN_SETFLAGS(sc->gpio_dev, sc->wp_gpio_pin, - GPIO_PIN_INPUT); - } - - /* * Set the offset from the device's memory start to the MMCHS registers. * Also for OMAP4 disable high speed mode due to erratum ID i626. */ @@ -573,6 +561,21 @@ ti_sdhci_attach(device_t dev) goto fail; } + /* + * Set up handling of card-detect and write-protect gpio lines. + * + * If there is no write protect info in the fdt data, fall back to the + * historical practice of assuming that the card is writable. This + * works around bad fdt data from the upstream source. The alternative + * would be to trust the sdhci controller's PRESENT_STATE register WP + * bit, but it may say write protect is in effect when it's not if the + * pinmux setup doesn't route the WP signal into the sdchi block. + */ + sc->gpio = sdhci_fdt_gpio_setup(sc->dev, &sc->slot); + + if (!OF_hasprop(node, "wp-gpios") && !OF_hasprop(node, "wp-disable")) + sc->disable_readonly = true; + /* Initialise the MMCHS hardware. */ ti_sdhci_hw_init(dev); @@ -707,6 +710,7 @@ static device_method_t ti_sdhci_methods[] = { DEVMETHOD(sdhci_write_2, ti_sdhci_write_2), DEVMETHOD(sdhci_write_4, ti_sdhci_write_4), DEVMETHOD(sdhci_write_multi_4, ti_sdhci_write_multi_4), + DEVMETHOD(sdhci_get_card_present, ti_sdhci_get_card_present), DEVMETHOD_END }; diff --git a/sys/arm/versatile/sp804.c b/sys/arm/versatile/sp804.c index de05700..894415b 100644 --- a/sys/arm/versatile/sp804.c +++ b/sys/arm/versatile/sp804.c @@ -42,7 +42,6 @@ __FBSDID("$FreeBSD$"); #include <machine/cpu.h> #include <machine/intr.h> -#include <dev/fdt/fdt_common.h> #include <dev/ofw/openfirm.h> #include <dev/ofw/ofw_bus.h> #include <dev/ofw/ofw_bus_subr.h> @@ -223,8 +222,8 @@ sp804_timer_attach(device_t dev) sc->sysclk_freq = DEFAULT_FREQUENCY; /* Get the base clock frequency */ node = ofw_bus_get_node(dev); - if ((OF_getprop(node, "clock-frequency", &clock, sizeof(clock))) > 0) { - sc->sysclk_freq = fdt32_to_cpu(clock); + if ((OF_getencprop(node, "clock-frequency", &clock, sizeof(clock))) > 0) { + sc->sysclk_freq = clock; } /* Setup and enable the timer */ diff --git a/sys/arm/versatile/versatile_common.c b/sys/arm/versatile/versatile_common.c index aca54b7..983b3ce 100644 --- a/sys/arm/versatile/versatile_common.c +++ b/sys/arm/versatile/versatile_common.c @@ -46,10 +46,6 @@ __FBSDID("$FreeBSD$"); #include <machine/bus.h> #include <machine/vmparam.h> -struct fdt_fixup_entry fdt_fixup_table[] = { - { NULL, NULL } -}; - #ifndef INTRNG static int fdt_intc_decode_ic(phandle_t node, pcell_t *intr, int *interrupt, int *trig, diff --git a/sys/arm/versatile/versatile_machdep.c b/sys/arm/versatile/versatile_machdep.c index adaff7a..ca0377a 100644 --- a/sys/arm/versatile/versatile_machdep.c +++ b/sys/arm/versatile/versatile_machdep.c @@ -39,7 +39,6 @@ #include <sys/cdefs.h> __FBSDID("$FreeBSD$"); -#define _ARM32_BUS_DMA_PRIVATE #include <sys/param.h> #include <sys/systm.h> #include <sys/bus.h> @@ -102,22 +101,8 @@ platform_devmap_init(void) return (0); } -struct arm32_dma_range * -bus_dma_get_range(void) -{ - - return (NULL); -} - -int -bus_dma_get_range_nb(void) -{ - - return (0); -} - void -cpu_reset() +cpu_reset(void) { printf("cpu_reset\n"); while (1); diff --git a/sys/arm/xilinx/zy7_machdep.c b/sys/arm/xilinx/zy7_machdep.c index 4776878..7eb4308 100644 --- a/sys/arm/xilinx/zy7_machdep.c +++ b/sys/arm/xilinx/zy7_machdep.c @@ -36,7 +36,6 @@ #include <sys/cdefs.h> __FBSDID("$FreeBSD$"); -#define _ARM32_BUS_DMA_PRIVATE #include <sys/param.h> #include <sys/systm.h> #include <sys/bus.h> @@ -94,10 +93,6 @@ platform_devmap_init(void) } -struct fdt_fixup_entry fdt_fixup_table[] = { - { NULL, NULL } -}; - #ifndef INTRNG static int fdt_gic_decode_ic(phandle_t node, pcell_t *intr, int *interrupt, int *trig, @@ -120,22 +115,8 @@ fdt_pic_decode_t fdt_pic_table[] = { }; #endif -struct arm32_dma_range * -bus_dma_get_range(void) -{ - - return (NULL); -} - -int -bus_dma_get_range_nb(void) -{ - - return (0); -} - void -cpu_reset() +cpu_reset(void) { if (zynq7_cpu_reset != NULL) (*zynq7_cpu_reset)(); diff --git a/sys/arm/xilinx/zy7_slcr.c b/sys/arm/xilinx/zy7_slcr.c index c99d5b0..c630fe6 100644 --- a/sys/arm/xilinx/zy7_slcr.c +++ b/sys/arm/xilinx/zy7_slcr.c @@ -52,7 +52,6 @@ __FBSDID("$FreeBSD$"); #include <machine/resource.h> #include <machine/stdarg.h> -#include <dev/fdt/fdt_common.h> #include <dev/ofw/ofw_bus.h> #include <dev/ofw/ofw_bus_subr.h> @@ -497,7 +496,7 @@ zy7_pl_fclk_enabled(int unit) } int -zy7_pl_level_shifters_enabled() +zy7_pl_level_shifters_enabled(void) { struct zy7_slcr_softc *sc = zy7_slcr_softc_p; @@ -514,7 +513,7 @@ zy7_pl_level_shifters_enabled() } void -zy7_pl_level_shifters_enable() +zy7_pl_level_shifters_enable(void) { struct zy7_slcr_softc *sc = zy7_slcr_softc_p; @@ -529,7 +528,7 @@ zy7_pl_level_shifters_enable() } void -zy7_pl_level_shifters_disable() +zy7_pl_level_shifters_disable(void) { struct zy7_slcr_softc *sc = zy7_slcr_softc_p; @@ -621,8 +620,8 @@ zy7_slcr_attach(device_t dev) /* Derive PLL frequencies from PS_CLK. */ node = ofw_bus_get_node(dev); - if (OF_getprop(node, "clock-frequency", &cell, sizeof(cell)) > 0) - ps_clk_frequency = fdt32_to_cpu(cell); + if (OF_getencprop(node, "clock-frequency", &cell, sizeof(cell)) > 0) + ps_clk_frequency = cell; else ps_clk_frequency = ZYNQ_DEFAULT_PS_CLK_FREQUENCY; diff --git a/sys/arm/xscale/pxa/pxa_gpio.c b/sys/arm/xscale/pxa/pxa_gpio.c index ecc220a..a3ad33d 100644 --- a/sys/arm/xscale/pxa/pxa_gpio.c +++ b/sys/arm/xscale/pxa/pxa_gpio.c @@ -331,7 +331,7 @@ pxa_gpio_unmask_irq(int irq) } int -pxa_gpio_get_next_irq() +pxa_gpio_get_next_irq(void) { struct pxa_gpio_softc *sc; int gpio; diff --git a/sys/arm/xscale/pxa/pxa_icu.c b/sys/arm/xscale/pxa/pxa_icu.c index 4194da3..c375ccb 100644 --- a/sys/arm/xscale/pxa/pxa_icu.c +++ b/sys/arm/xscale/pxa/pxa_icu.c @@ -171,7 +171,7 @@ arm_unmask_irq(uintptr_t nb) } uint32_t -pxa_icu_get_icip() +pxa_icu_get_icip(void) { return (bus_space_read_4(pxa_icu_softc->pi_bst, @@ -187,7 +187,7 @@ pxa_icu_clear_icip(int irq) } uint32_t -pxa_icu_get_icfp() +pxa_icu_get_icfp(void) { return (bus_space_read_4(pxa_icu_softc->pi_bst, @@ -203,7 +203,7 @@ pxa_icu_clear_icfp(int irq) } uint32_t -pxa_icu_get_icmr() +pxa_icu_get_icmr(void) { return (bus_space_read_4(pxa_icu_softc->pi_bst, @@ -219,7 +219,7 @@ pxa_icu_set_icmr(uint32_t val) } uint32_t -pxa_icu_get_iclr() +pxa_icu_get_iclr(void) { return (bus_space_read_4(pxa_icu_softc->pi_bst, @@ -235,7 +235,7 @@ pxa_icu_set_iclr(uint32_t val) } uint32_t -pxa_icu_get_icpr() +pxa_icu_get_icpr(void) { return (bus_space_read_4(pxa_icu_softc->pi_bst, @@ -243,7 +243,7 @@ pxa_icu_get_icpr() } void -pxa_icu_idle_enable() +pxa_icu_idle_enable(void) { bus_space_write_4(pxa_icu_softc->pi_bst, @@ -251,7 +251,7 @@ pxa_icu_idle_enable() } void -pxa_icu_idle_disable() +pxa_icu_idle_disable(void) { bus_space_write_4(pxa_icu_softc->pi_bst, diff --git a/sys/arm/xscale/pxa/pxa_space.c b/sys/arm/xscale/pxa/pxa_space.c index 35b6cd9..2378efe 100644 --- a/sys/arm/xscale/pxa/pxa_space.c +++ b/sys/arm/xscale/pxa/pxa_space.c @@ -176,7 +176,7 @@ bus_space_tag_t base_tag = &_base_tag; bus_space_tag_t obio_tag = NULL; void -pxa_obio_tag_init() +pxa_obio_tag_init(void) { bcopy(&_base_tag, &_obio_tag, sizeof(struct bus_space)); diff --git a/sys/arm/xscale/pxa/pxa_timer.c b/sys/arm/xscale/pxa/pxa_timer.c index d62c1e1..e13793d 100644 --- a/sys/arm/xscale/pxa/pxa_timer.c +++ b/sys/arm/xscale/pxa/pxa_timer.c @@ -235,7 +235,7 @@ pxa_timer_set_osmr(int which, uint32_t val) } uint32_t -pxa_timer_get_oscr() +pxa_timer_get_oscr(void) { return (bus_space_read_4(timer_softc->pt_bst, @@ -251,7 +251,7 @@ pxa_timer_set_oscr(uint32_t val) } uint32_t -pxa_timer_get_ossr() +pxa_timer_get_ossr(void) { return (bus_space_read_4(timer_softc->pt_bst, @@ -267,7 +267,7 @@ pxa_timer_clear_ossr(uint32_t val) } void -pxa_timer_watchdog_enable() +pxa_timer_watchdog_enable(void) { bus_space_write_4(timer_softc->pt_bst, @@ -275,7 +275,7 @@ pxa_timer_watchdog_enable() } void -pxa_timer_watchdog_disable() +pxa_timer_watchdog_disable(void) { bus_space_write_4(timer_softc->pt_bst, |
