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-rw-r--r--sys/arm/allwinner/files.a102
-rw-r--r--sys/arm/allwinner/timer.c35
-rw-r--r--sys/arm/arm/locore.S1
-rw-r--r--sys/arm/arm/mpcore_timer.c30
-rw-r--r--sys/arm/broadcom/bcm2835/bcm2835_dma.c727
-rw-r--r--sys/arm/broadcom/bcm2835/bcm2835_dma.h62
-rw-r--r--sys/arm/broadcom/bcm2835/bcm2835_sdhci.c304
-rw-r--r--sys/arm/broadcom/bcm2835/bcm2835_systimer.c19
-rw-r--r--sys/arm/broadcom/bcm2835/files.bcm28351
-rw-r--r--sys/arm/conf/CUBIEBOARD4
-rw-r--r--sys/arm/conf/RPI-B2
-rw-r--r--sys/arm/econa/econa_machdep.c1
-rw-r--r--sys/arm/include/vmparam.h48
-rw-r--r--sys/arm/lpc/lpc_timer.c32
-rw-r--r--sys/arm/mv/timer.c31
-rw-r--r--sys/arm/s3c2xx0/s3c24x0_machdep.c1
-rw-r--r--sys/arm/ti/am335x/am335x_dmtimer.c28
-rw-r--r--sys/arm/versatile/sp804.c19
-rw-r--r--sys/arm/xscale/i80321/ep80219_machdep.c1
-rw-r--r--sys/arm/xscale/i80321/iq31244_machdep.c1
-rw-r--r--sys/arm/xscale/i8134x/crb_machdep.c1
-rw-r--r--sys/arm/xscale/ixp425/avila_machdep.c1
-rw-r--r--sys/arm/xscale/pxa/pxa_machdep.c1
23 files changed, 1192 insertions, 160 deletions
diff --git a/sys/arm/allwinner/files.a10 b/sys/arm/allwinner/files.a10
index 9e947de..c25682a 100644
--- a/sys/arm/allwinner/files.a10
+++ b/sys/arm/allwinner/files.a10
@@ -17,5 +17,5 @@ arm/allwinner/timer.c standard
arm/allwinner/aintc.c standard
arm/allwinner/bus_space.c standard
arm/allwinner/common.c standard
-arm/allwinner/console.c standard
+#arm/allwinner/console.c standard
arm/allwinner/a10_machdep.c standard
diff --git a/sys/arm/allwinner/timer.c b/sys/arm/allwinner/timer.c
index 4da3517..49c5f18 100644
--- a/sys/arm/allwinner/timer.c
+++ b/sys/arm/allwinner/timer.c
@@ -95,7 +95,7 @@ int a10_timer_get_timerfreq(struct a10_timer_softc *);
static u_int a10_timer_get_timecount(struct timecounter *);
static int a10_timer_timer_start(struct eventtimer *,
- struct bintime *, struct bintime *);
+ sbintime_t first, sbintime_t period);
static int a10_timer_timer_stop(struct eventtimer *);
static uint64_t timer_read_counter64(void);
@@ -193,12 +193,8 @@ a10_timer_attach(device_t dev)
sc->et.et_name = "a10_timer Eventtimer";
sc->et.et_flags = ET_FLAGS_ONESHOT | ET_FLAGS_PERIODIC;
sc->et.et_quality = 1000;
- sc->et.et_min_period.sec = 0;
- sc->et.et_min_period.frac =
- ((0x00000005LLU << 32) / sc->et.et_frequency) << 32;
- sc->et.et_max_period.sec = 0xfffffff0U / sc->et.et_frequency;
- sc->et.et_max_period.frac =
- ((0xfffffffeLLU << 32) / sc->et.et_frequency) << 32;
+ sc->et.et_min_period = (0x00000005LLU << 32) / sc->et.et_frequency;
+ sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency;
sc->et.et_start = a10_timer_timer_start;
sc->et.et_stop = a10_timer_timer_stop;
sc->et.et_priv = sc;
@@ -225,8 +221,8 @@ a10_timer_attach(device_t dev)
}
static int
-a10_timer_timer_start(struct eventtimer *et, struct bintime *first,
- struct bintime *period)
+a10_timer_timer_start(struct eventtimer *et, sbintime_t first,
+ sbintime_t period)
{
struct a10_timer_softc *sc;
uint32_t count;
@@ -234,26 +230,21 @@ a10_timer_timer_start(struct eventtimer *et, struct bintime *first,
sc = (struct a10_timer_softc *)et->et_priv;
- sc->sc_period = 0;
-
- if (period != NULL) {
- sc->sc_period = (sc->et.et_frequency * (period->frac >> 32)) >> 32;
- sc->sc_period += sc->et.et_frequency * period->sec;
- }
- if (first == NULL)
+ if (period != 0)
+ sc->sc_period = ((uint32_t)et->et_frequency * period) >> 32;
+ else
+ sc->sc_period = 0;
+ if (first != 0)
+ count = ((uint32_t)et->et_frequency * first) >> 32;
+ else
count = sc->sc_period;
- else {
- count = (sc->et.et_frequency * (first->frac >> 32)) >> 32;
- if (first->sec != 0)
- count += sc->et.et_frequency * first->sec;
- }
/* Update timer values */
timer_write_4(sc, SW_TIMER0_INT_VALUE_REG, sc->sc_period);
timer_write_4(sc, SW_TIMER0_CUR_VALUE_REG, count);
val = timer_read_4(sc, SW_TIMER0_CTRL_REG);
- if (first == NULL) {
+ if (period != 0) {
/* periodic */
val |= TIMER_AUTORELOAD;
} else {
diff --git a/sys/arm/arm/locore.S b/sys/arm/arm/locore.S
index 00a61e7..37e88fe 100644
--- a/sys/arm/arm/locore.S
+++ b/sys/arm/arm/locore.S
@@ -204,6 +204,7 @@ mmu_done:
virt_done:
mov r1, #20 /* loader info size is 20 bytes also second arg */
subs sp, sp, r1 /* allocate arm_boot_params struct on stack */
+ bic sp, sp, #7 /* align stack to 8 bytes */
mov r0, sp /* loader info pointer is first arg */
str r1, [r0] /* Store length of loader info */
str r9, [r0, #4] /* Store r0 from boot loader */
diff --git a/sys/arm/arm/mpcore_timer.c b/sys/arm/arm/mpcore_timer.c
index 41a0b27..8445d3d 100644
--- a/sys/arm/arm/mpcore_timer.c
+++ b/sys/arm/arm/mpcore_timer.c
@@ -167,31 +167,23 @@ arm_tmr_get_timecount(struct timecounter *tc)
* Always returns 0
*/
static int
-arm_tmr_start(struct eventtimer *et, struct bintime *first,
- struct bintime *period)
+arm_tmr_start(struct eventtimer *et, sbintime_t first, sbintime_t period)
{
- struct arm_tmr_softc *sc = (struct arm_tmr_softc *)et->et_priv;
uint32_t load, count;
uint32_t ctrl;
ctrl = PRV_TIMER_CTRL_IRQ_ENABLE | PRV_TIMER_CTRL_TIMER_ENABLE;
- if (period != NULL) {
- load = (et->et_frequency * (period->frac >> 32)) >> 32;
- if (period->sec > 0)
- load += et->et_frequency * period->sec;
+ if (period != 0) {
+ load = ((uint32_t)et->et_frequency * period) >> 32;
ctrl |= PRV_TIMER_CTRL_AUTO_RELOAD;
- } else {
+ } else
load = 0;
- }
- if (first != NULL) {
- count = (sc->et.et_frequency * (first->frac >> 32)) >> 32;
- if (first->sec != 0)
- count += sc->et.et_frequency * first->sec;
- } else {
+ if (first != 0)
+ count = ((uint32_t)et->et_frequency * first) >> 32;
+ else
count = load;
- }
tmr_prv_write_4(PRV_TIMER_LOAD, load);
tmr_prv_write_4(PRV_TIMER_COUNT, count);
@@ -330,12 +322,8 @@ arm_tmr_attach(device_t dev)
sc->et.et_quality = 1000;
sc->et.et_frequency = sc->clkfreq;
- sc->et.et_min_period.sec = 0;
- sc->et.et_min_period.frac =
- ((0x00000002LLU << 32) / sc->et.et_frequency) << 32;
- sc->et.et_max_period.sec = 0xfffffff0U / sc->et.et_frequency;
- sc->et.et_max_period.frac =
- ((0xfffffffeLLU << 32) / sc->et.et_frequency) << 32;
+ sc->et.et_min_period = (0x00000002LLU << 32) / sc->et.et_frequency;
+ sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency;
sc->et.et_start = arm_tmr_start;
sc->et.et_stop = arm_tmr_stop;
sc->et.et_priv = sc;
diff --git a/sys/arm/broadcom/bcm2835/bcm2835_dma.c b/sys/arm/broadcom/bcm2835/bcm2835_dma.c
new file mode 100644
index 0000000..5e1c9dc
--- /dev/null
+++ b/sys/arm/broadcom/bcm2835/bcm2835_dma.c
@@ -0,0 +1,727 @@
+/*
+ * Copyright (c) 2013 Daisuke Aoyama <aoyama@peach.ne.jp>
+ * Copyright (c) 2013 Oleksandr Tymoshenko <gonzo@bluezbox.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/kernel.h>
+#include <sys/lock.h>
+#include <sys/malloc.h>
+#include <sys/module.h>
+#include <sys/mutex.h>
+#include <sys/queue.h>
+#include <sys/resource.h>
+#include <sys/rman.h>
+
+#include <dev/fdt/fdt_common.h>
+#include <dev/ofw/openfirm.h>
+#include <dev/ofw/ofw_bus.h>
+#include <dev/ofw/ofw_bus_subr.h>
+
+#include <vm/vm.h>
+#include <vm/pmap.h>
+#include <machine/bus.h>
+#include <machine/cpu.h>
+#include <machine/cpufunc.h>
+#include <machine/pmap.h>
+
+#include "bcm2835_dma.h"
+#include "bcm2835_vcbus.h"
+
+#define MAX_REG 9
+
+/* private flags */
+#define BCM_DMA_CH_USED 0x00000001
+#define BCM_DMA_CH_FREE 0x40000000
+#define BCM_DMA_CH_UNMAP 0x80000000
+
+/* Register Map (4.2.1.2) */
+#define BCM_DMA_CS(n) (0x100*(n) + 0x00)
+#define CS_ACTIVE (1 << 0)
+#define CS_END (1 << 1)
+#define CS_INT (1 << 2)
+#define CS_DREQ (1 << 3)
+#define CS_ISPAUSED (1 << 4)
+#define CS_ISHELD (1 << 5)
+#define CS_ISWAIT (1 << 6)
+#define CS_ERR (1 << 8)
+#define CS_WAITWRT (1 << 28)
+#define CS_DISDBG (1 << 29)
+#define CS_ABORT (1 << 30)
+#define CS_RESET (1 << 31)
+#define BCM_DMA_CBADDR(n) (0x100*(n) + 0x04)
+#define BCM_DMA_INFO(n) (0x100*(n) + 0x08)
+#define INFO_INT_EN (1 << 0)
+#define INFO_TDMODE (1 << 1)
+#define INFO_WAIT_RESP (1 << 3)
+#define INFO_D_INC (1 << 4)
+#define INFO_D_WIDTH (1 << 5)
+#define INFO_D_DREQ (1 << 6)
+#define INFO_S_INC (1 << 8)
+#define INFO_S_WIDTH (1 << 9)
+#define INFO_S_DREQ (1 << 10)
+#define INFO_WAITS_SHIFT (21)
+#define INFO_PERMAP_SHIFT (16)
+#define INFO_PERMAP_MASK (0x1f << INFO_PERMAP_SHIFT)
+
+#define BCM_DMA_SRC(n) (0x100*(n) + 0x0C)
+#define BCM_DMA_DST(n) (0x100*(n) + 0x10)
+#define BCM_DMA_LEN(n) (0x100*(n) + 0x14)
+#define BCM_DMA_STRIDE(n) (0x100*(n) + 0x18)
+#define BCM_DMA_CBNEXT(n) (0x100*(n) + 0x1C)
+#define BCM_DMA_DEBUG(n) (0x100*(n) + 0x20)
+#define DEBUG_ERROR_MASK (7)
+
+#define BCM_DMA_INT_STATUS 0xfe0
+#define BCM_DMA_ENABLE 0xff0
+
+/* relative offset from BCM_VC_DMA0_BASE (p.39) */
+#define BCM_DMA_CH(n) (0x100*(n))
+
+/* DMA Control Block - 256bit aligned (p.40) */
+struct bcm_dma_cb {
+ uint32_t info; /* Transfer Information */
+ uint32_t src; /* Source Address */
+ uint32_t dst; /* Destination Address */
+ uint32_t len; /* Transfer Length */
+ uint32_t stride; /* 2D Mode Stride */
+ uint32_t next; /* Next Control Block Address */
+ uint32_t rsvd1; /* Reserved */
+ uint32_t rsvd2; /* Reserved */
+};
+
+#ifdef DEBUG
+static void bcm_dma_cb_dump(struct bcm_dma_cb *cb);
+static void bcm_dma_reg_dump(int ch);
+#endif
+
+/* DMA channel private info */
+struct bcm_dma_ch {
+ int ch;
+ uint32_t flags;
+ struct bcm_dma_cb * cb;
+ uint32_t vc_cb;
+ bus_dmamap_t dma_map;
+ void (*intr_func)(int, void *);
+ void * intr_arg;
+};
+
+struct bcm_dma_softc {
+ device_t sc_dev;
+ struct mtx sc_mtx;
+ struct resource * sc_mem;
+ struct resource * sc_irq[BCM_DMA_CH_MAX];
+ void * sc_intrhand[BCM_DMA_CH_MAX];
+ struct bcm_dma_ch sc_dma_ch[BCM_DMA_CH_MAX];
+ bus_dma_tag_t sc_dma_tag;
+};
+
+static struct bcm_dma_softc *bcm_dma_sc = NULL;
+
+static void
+bcm_dmamap_cb(void *arg, bus_dma_segment_t *segs,
+ int nseg, int err)
+{
+ bus_addr_t *addr;
+
+ if (err)
+ return;
+
+ addr = (bus_addr_t*)arg;
+ *addr = PHYS_TO_VCBUS(segs[0].ds_addr);
+}
+
+static void
+bcm_dma_reset(device_t dev, int ch)
+{
+ struct bcm_dma_softc *sc = device_get_softc(dev);
+ struct bcm_dma_cb *cb;
+ uint32_t cs;
+ int count;
+
+ if (ch < 0 || ch >= BCM_DMA_CH_MAX)
+ return;
+
+ cs = bus_read_4(sc->sc_mem, BCM_DMA_CS(ch));
+
+ if (cs & CS_ACTIVE) {
+ /* pause current task */
+ bus_write_4(sc->sc_mem, BCM_DMA_CS(ch), 0);
+
+ count = 1000;
+ do {
+ cs = bus_read_4(sc->sc_mem, BCM_DMA_CS(ch));
+ } while (!(cs & CS_ISPAUSED) && (count-- > 0));
+
+ if (!(cs & CS_ISPAUSED)) {
+ device_printf(dev,
+ "Can't abort DMA transfer at channel %d\n", ch);
+ }
+
+ bus_write_4(sc->sc_mem, BCM_DMA_CBNEXT(ch), 0);
+
+ /* Complete everything, clear interrupt */
+ bus_write_4(sc->sc_mem, BCM_DMA_CS(ch),
+ CS_ABORT | CS_INT | CS_END| CS_ACTIVE);
+ }
+
+ /* clear control blocks */
+ bus_write_4(sc->sc_mem, BCM_DMA_CBADDR(ch), 0);
+ bus_write_4(sc->sc_mem, BCM_DMA_CBNEXT(ch), 0);
+
+ /* Reset control block */
+ cb = sc->sc_dma_ch[ch].cb;
+ bzero(cb, sizeof(cb));
+}
+
+static int
+bcm_dma_init(device_t dev)
+{
+ struct bcm_dma_softc *sc = device_get_softc(dev);
+ uint32_t mask;
+ struct bcm_dma_ch *ch;
+ void *cb_virt;
+ vm_paddr_t cb_phys;
+ int err;
+ int i;
+
+ /* disable and clear interrupt status */
+ bus_write_4(sc->sc_mem, BCM_DMA_ENABLE, 0);
+ bus_write_4(sc->sc_mem, BCM_DMA_INT_STATUS, 0);
+
+ /* Allocate DMA chunks control blocks */
+ /* p.40 of spec - control block should be 32-bit aligned */
+ err = bus_dma_tag_create(bus_get_dma_tag(dev),
+ 1, 0, BUS_SPACE_MAXADDR_32BIT,
+ BUS_SPACE_MAXADDR, NULL, NULL,
+ sizeof(struct bcm_dma_cb), 1,
+ sizeof(struct bcm_dma_cb),
+ BUS_DMA_ALLOCNOW, NULL, NULL,
+ &sc->sc_dma_tag);
+
+ if (err) {
+ device_printf(dev, "failed allocate DMA tag");
+ return (err);
+ }
+
+ /* setup initial settings */
+ for (i = 0; i < BCM_DMA_CH_MAX; i++) {
+ ch = &sc->sc_dma_ch[i];
+
+ err = bus_dmamem_alloc(sc->sc_dma_tag, &cb_virt,
+ BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO,
+ &ch->dma_map);
+ if (err) {
+ device_printf(dev, "cannot allocate DMA memory\n");
+ break;
+ }
+
+ /*
+ * Least alignment for busdma-allocated stuff is cache
+ * line size, so just make sure nothing stupid happend
+ * and we got properly aligned address
+ */
+ if ((uintptr_t)cb_virt & 0x1f) {
+ device_printf(dev,
+ "DMA address is not 32-bytes aligned: %p\n",
+ (void*)cb_virt);
+ break;
+ }
+
+ err = bus_dmamap_load(sc->sc_dma_tag, ch->dma_map, cb_virt,
+ sizeof(struct bcm_dma_cb), bcm_dmamap_cb, &cb_phys,
+ BUS_DMA_WAITOK);
+ if (err) {
+ device_printf(dev, "cannot load DMA memory\n");
+ break;
+ }
+
+ bzero(ch, sizeof(struct bcm_dma_ch));
+ ch->ch = i;
+ ch->cb = cb_virt;
+ ch->vc_cb = cb_phys;
+ ch->intr_func = NULL;
+ ch->intr_arg = NULL;
+ ch->flags = BCM_DMA_CH_UNMAP;
+
+ ch->cb->info = INFO_WAIT_RESP;
+
+ /* reset DMA engine */
+ bcm_dma_reset(dev, i);
+ }
+
+ /* now use DMA2/DMA3 only */
+ sc->sc_dma_ch[2].flags = BCM_DMA_CH_FREE;
+ sc->sc_dma_ch[3].flags = BCM_DMA_CH_FREE;
+
+ /* enable DMAs */
+ mask = 0;
+
+ for (i = 0; i < BCM_DMA_CH_MAX; i++)
+ if (sc->sc_dma_ch[i].flags & BCM_DMA_CH_FREE)
+ mask |= (1 << i);
+
+ bus_write_4(sc->sc_mem, BCM_DMA_ENABLE, mask);
+
+ return (0);
+}
+
+/*
+ * Allocate DMA channel for further use, returns channel # or
+ * BCM_DMA_CH_INVALID
+ */
+int
+bcm_dma_allocate(int req_ch)
+{
+ struct bcm_dma_softc *sc = bcm_dma_sc;
+ int ch = BCM_DMA_CH_INVALID;
+ int i;
+
+ if (req_ch >= BCM_DMA_CH_MAX)
+ return (BCM_DMA_CH_INVALID);
+
+ /* Auto(req_ch < 0) or CH specified */
+ mtx_lock(&sc->sc_mtx);
+
+ if (req_ch < 0) {
+ for (i = 0; i < BCM_DMA_CH_MAX; i++) {
+ if (sc->sc_dma_ch[i].flags & BCM_DMA_CH_FREE) {
+ ch = i;
+ sc->sc_dma_ch[ch].flags &= ~BCM_DMA_CH_FREE;
+ sc->sc_dma_ch[ch].flags |= BCM_DMA_CH_USED;
+ break;
+ }
+ }
+ }
+ else {
+ if (sc->sc_dma_ch[req_ch].flags & BCM_DMA_CH_FREE) {
+ ch = req_ch;
+ sc->sc_dma_ch[ch].flags &= ~BCM_DMA_CH_FREE;
+ sc->sc_dma_ch[ch].flags |= BCM_DMA_CH_USED;
+ }
+ }
+
+ mtx_unlock(&sc->sc_mtx);
+ return (ch);
+}
+
+/*
+ * Frees allocated channel. Returns 0 on success, -1 otherwise
+ */
+int
+bcm_dma_free(int ch)
+{
+ struct bcm_dma_softc *sc = bcm_dma_sc;
+
+ if (ch < 0 || ch >= BCM_DMA_CH_MAX)
+ return (-1);
+
+ mtx_lock(&sc->sc_mtx);
+ if (sc->sc_dma_ch[ch].flags & BCM_DMA_CH_USED) {
+ sc->sc_dma_ch[ch].flags |= BCM_DMA_CH_FREE;
+ sc->sc_dma_ch[ch].flags &= ~BCM_DMA_CH_USED;
+ sc->sc_dma_ch[ch].intr_func = NULL;
+ sc->sc_dma_ch[ch].intr_arg = NULL;
+
+ /* reset DMA engine */
+ bcm_dma_reset(sc->sc_dev, ch);
+ }
+
+ mtx_unlock(&sc->sc_mtx);
+ return (0);
+}
+
+/*
+ * Assign handler function for channel interrupt
+ * Returns 0 on success, -1 otherwise
+ */
+int
+bcm_dma_setup_intr(int ch, void (*func)(int, void *), void *arg)
+{
+ struct bcm_dma_softc *sc = bcm_dma_sc;
+ struct bcm_dma_cb *cb;
+
+ if (ch < 0 || ch >= BCM_DMA_CH_MAX)
+ return (-1);
+
+ if (!(sc->sc_dma_ch[ch].flags & BCM_DMA_CH_USED))
+ return (-1);
+
+ sc->sc_dma_ch[ch].intr_func = func;
+ sc->sc_dma_ch[ch].intr_arg = arg;
+ cb = sc->sc_dma_ch[ch].cb;
+ cb->info |= INFO_INT_EN;
+
+ return (0);
+}
+
+/*
+ * Setup DMA source parameters
+ * ch - channel number
+ * dreq - hardware DREQ # or BCM_DMA_DREQ_NONE if
+ * source is physical memory
+ * inc_addr - BCM_DMA_INC_ADDR if source address
+ * should be increased after each access or
+ * BCM_DMA_SAME_ADDR if address should remain
+ * the same
+ * width - size of read operation, BCM_DMA_32BIT
+ * for 32bit bursts, BCM_DMA_128BIT for 128 bits
+ *
+ * Returns 0 on success, -1 otherwise
+ */
+int
+bcm_dma_setup_src(int ch, int dreq, int inc_addr, int width)
+{
+ struct bcm_dma_softc *sc = bcm_dma_sc;
+ uint32_t info;
+
+ if (ch < 0 || ch >= BCM_DMA_CH_MAX)
+ return (-1);
+
+ if (!(sc->sc_dma_ch[ch].flags & BCM_DMA_CH_USED))
+ return (-1);
+
+ info = sc->sc_dma_ch[ch].cb->info;
+ info &= ~INFO_PERMAP_MASK;
+ info |= (dreq << INFO_PERMAP_SHIFT) & INFO_PERMAP_MASK;
+
+ if (dreq)
+ info |= INFO_S_DREQ;
+ else
+ info &= ~INFO_S_DREQ;
+
+ if (width == BCM_DMA_128BIT)
+ info |= INFO_S_WIDTH;
+ else
+ info &= ~INFO_S_WIDTH;
+
+ if (inc_addr == BCM_DMA_INC_ADDR)
+ info |= INFO_S_INC;
+ else
+ info &= ~INFO_S_INC;
+
+ sc->sc_dma_ch[ch].cb->info = info;
+
+ return (0);
+}
+
+/*
+ * Setup DMA destination parameters
+ * ch - channel number
+ * dreq - hardware DREQ # or BCM_DMA_DREQ_NONE if
+ * destination is physical memory
+ * inc_addr - BCM_DMA_INC_ADDR if source address
+ * should be increased after each access or
+ * BCM_DMA_SAME_ADDR if address should remain
+ * the same
+ * width - size of write operation, BCM_DMA_32BIT
+ * for 32bit bursts, BCM_DMA_128BIT for 128 bits
+ *
+ * Returns 0 on success, -1 otherwise
+ */
+int
+bcm_dma_setup_dst(int ch, int dreq, int inc_addr, int width)
+{
+ struct bcm_dma_softc *sc = bcm_dma_sc;
+ uint32_t info;
+
+ if (ch < 0 || ch >= BCM_DMA_CH_MAX)
+ return (-1);
+
+ if (!(sc->sc_dma_ch[ch].flags & BCM_DMA_CH_USED))
+ return (-1);
+
+ info = sc->sc_dma_ch[ch].cb->info;
+ info &= ~INFO_PERMAP_MASK;
+ info |= (dreq << INFO_PERMAP_SHIFT) & INFO_PERMAP_MASK;
+
+ if (dreq)
+ info |= INFO_D_DREQ;
+ else
+ info &= ~INFO_D_DREQ;
+
+ if (width == BCM_DMA_128BIT)
+ info |= INFO_D_WIDTH;
+ else
+ info &= ~INFO_D_WIDTH;
+
+ if (inc_addr == BCM_DMA_INC_ADDR)
+ info |= INFO_D_INC;
+ else
+ info &= ~INFO_D_INC;
+
+ sc->sc_dma_ch[ch].cb->info = info;
+
+ return (0);
+}
+
+#ifdef DEBUG
+void
+bcm_dma_cb_dump(struct bcm_dma_cb *cb)
+{
+
+ printf("DMA CB ");
+ printf("INFO: %8.8x ", cb->info);
+ printf("SRC: %8.8x ", cb->src);
+ printf("DST: %8.8x ", cb->dst);
+ printf("LEN: %8.8x ", cb->len);
+ printf("\n");
+ printf("STRIDE: %8.8x ", cb->stride);
+ printf("NEXT: %8.8x ", cb->next);
+ printf("RSVD1: %8.8x ", cb->rsvd1);
+ printf("RSVD2: %8.8x ", cb->rsvd2);
+ printf("\n");
+}
+
+void
+bcm_dma_reg_dump(int ch)
+{
+ struct bcm_dma_softc *sc = bcm_dma_sc;
+ int i;
+ uint32_t reg;
+
+ if (ch < 0 || ch >= BCM_DMA_CH_MAX)
+ return;
+
+ printf("DMA%d: ", ch);
+ for (i = 0; i < MAX_REG; i++) {
+ reg = bus_read_4(sc->sc_mem, BCM_DMA_CH(ch) + i*4);
+ printf("%8.8x ", reg);
+ }
+ printf("\n");
+}
+#endif
+
+/*
+ * Start DMA transaction
+ * ch - channel number
+ * src, dst - source and destination address in
+ * ARM physical memory address space.
+ * len - amount of bytes to be transfered
+ *
+ * Returns 0 on success, -1 otherwise
+ */
+int
+bcm_dma_start(int ch, vm_paddr_t src, vm_paddr_t dst, int len)
+{
+ struct bcm_dma_softc *sc = bcm_dma_sc;
+ struct bcm_dma_cb *cb;
+
+ if (ch < 0 || ch >= BCM_DMA_CH_MAX)
+ return (-1);
+
+ if (!(sc->sc_dma_ch[ch].flags & BCM_DMA_CH_USED))
+ return (-1);
+
+ cb = sc->sc_dma_ch[ch].cb;
+ if (BCM2835_ARM_IS_IO(src))
+ cb->src = IO_TO_VCBUS(src);
+ else
+ cb->src = PHYS_TO_VCBUS(src);
+ if (BCM2835_ARM_IS_IO(dst))
+ cb->dst = IO_TO_VCBUS(dst);
+ else
+ cb->dst = PHYS_TO_VCBUS(dst);
+ cb->len = len;
+
+ bus_dmamap_sync(sc->sc_dma_tag,
+ sc->sc_dma_ch[ch].dma_map, BUS_DMASYNC_PREWRITE);
+
+ bus_write_4(sc->sc_mem, BCM_DMA_CBADDR(ch),
+ sc->sc_dma_ch[ch].vc_cb);
+ bus_write_4(sc->sc_mem, BCM_DMA_CS(ch), CS_ACTIVE);
+
+#ifdef DEBUG
+ bcm_dma_cb_dump(sc->sc_dma_ch[ch].cb);
+ bcm_dma_reg_dump(ch);
+#endif
+
+ return (0);
+}
+
+/*
+ * Get length requested for DMA transaction
+ * ch - channel number
+ *
+ * Returns size of transaction, 0 if channel is invalid
+ */
+uint32_t
+bcm_dma_length(int ch)
+{
+ struct bcm_dma_softc *sc = bcm_dma_sc;
+ struct bcm_dma_cb *cb;
+
+ if (ch < 0 || ch >= BCM_DMA_CH_MAX)
+ return (0);
+
+ if (!(sc->sc_dma_ch[ch].flags & BCM_DMA_CH_USED))
+ return (0);
+
+ cb = sc->sc_dma_ch[ch].cb;
+
+ return (cb->len);
+}
+
+static void
+bcm_dma_intr(void *arg)
+{
+ struct bcm_dma_softc *sc = bcm_dma_sc;
+ struct bcm_dma_ch *ch = (struct bcm_dma_ch *)arg;
+ uint32_t cs, debug;
+
+ /* my interrupt? */
+ cs = bus_read_4(sc->sc_mem, BCM_DMA_CS(ch->ch));
+
+ if (!(cs & (CS_INT | CS_ERR)))
+ return;
+
+ /* running? */
+ if (!(ch->flags & BCM_DMA_CH_USED)) {
+ device_printf(sc->sc_dev,
+ "unused DMA intr CH=%d, CS=%x\n", ch->ch, cs);
+ return;
+ }
+
+ if (cs & CS_ERR) {
+ debug = bus_read_4(sc->sc_mem, BCM_DMA_DEBUG(ch->ch));
+ device_printf(sc->sc_dev, "DMA error %d on CH%d\n",
+ debug & DEBUG_ERROR_MASK, ch->ch);
+ bus_write_4(sc->sc_mem, BCM_DMA_DEBUG(ch->ch),
+ debug & DEBUG_ERROR_MASK);
+ }
+
+ if (cs & CS_INT) {
+ /* acknowledge interrupt */
+ bus_write_4(sc->sc_mem, BCM_DMA_CS(ch->ch),
+ CS_INT | CS_END);
+
+ /* Prepare for possible access to len field */
+ bus_dmamap_sync(sc->sc_dma_tag, ch->dma_map,
+ BUS_DMASYNC_POSTWRITE);
+
+ /* save callback function and argument */
+ if (ch->intr_func)
+ ch->intr_func(ch->ch, ch->intr_arg);
+ }
+}
+
+static int
+bcm_dma_probe(device_t dev)
+{
+
+ if (!ofw_bus_is_compatible(dev, "broadcom,bcm2835-dma"))
+ return (ENXIO);
+
+ device_set_desc(dev, "BCM2835 DMA Controller");
+ return (BUS_PROBE_DEFAULT);
+}
+
+static int
+bcm_dma_attach(device_t dev)
+{
+ struct bcm_dma_softc *sc = device_get_softc(dev);
+ int rid, err = 0;
+ int i;
+
+ sc->sc_dev = dev;
+
+ if (bcm_dma_sc)
+ return (ENXIO);
+
+ for (i = 0; i < BCM_DMA_CH_MAX; i++) {
+ sc->sc_irq[i] = NULL;
+ sc->sc_intrhand[i] = NULL;
+ }
+
+ /* DMA0 - DMA14 */
+ rid = 0;
+ sc->sc_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE);
+ if (sc->sc_mem == NULL) {
+ device_printf(dev, "could not allocate memory resource\n");
+ return (ENXIO);
+ }
+
+ /* IRQ DMA0 - DMA11 XXX NOT USE DMA12(spurious?) */
+ for (rid = 0; rid < BCM_DMA_CH_MAX; rid++) {
+ sc->sc_irq[rid] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
+ RF_ACTIVE);
+ if (sc->sc_irq[rid] == NULL) {
+ device_printf(dev, "cannot allocate interrupt\n");
+ err = ENXIO;
+ goto fail;
+ }
+ if (bus_setup_intr(dev, sc->sc_irq[rid], INTR_TYPE_MISC | INTR_MPSAFE,
+ NULL, bcm_dma_intr, &sc->sc_dma_ch[rid],
+ &sc->sc_intrhand[rid])) {
+ device_printf(dev, "cannot setup interrupt handler\n");
+ err = ENXIO;
+ goto fail;
+ }
+ }
+
+ mtx_init(&sc->sc_mtx, "bcmdma", "bcmdma", MTX_DEF);
+ bcm_dma_sc = sc;
+
+ err = bcm_dma_init(dev);
+ if (err)
+ goto fail;
+
+ return (err);
+
+fail:
+ if (sc->sc_mem)
+ bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem);
+
+ for (i = 0; i < BCM_DMA_CH_MAX; i++) {
+ if (sc->sc_intrhand[i])
+ bus_teardown_intr(dev, sc->sc_irq[i], sc->sc_intrhand[i]);
+ if (sc->sc_irq[i])
+ bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq[i]);
+ }
+
+ return (err);
+}
+
+static device_method_t bcm_dma_methods[] = {
+ DEVMETHOD(device_probe, bcm_dma_probe),
+ DEVMETHOD(device_attach, bcm_dma_attach),
+ { 0, 0 }
+};
+
+static driver_t bcm_dma_driver = {
+ "bcm_dma",
+ bcm_dma_methods,
+ sizeof(struct bcm_dma_softc),
+};
+
+static devclass_t bcm_dma_devclass;
+
+DRIVER_MODULE(bcm_dma, simplebus, bcm_dma_driver, bcm_dma_devclass, 0, 0);
+MODULE_VERSION(bcm_dma, 1);
diff --git a/sys/arm/broadcom/bcm2835/bcm2835_dma.h b/sys/arm/broadcom/bcm2835/bcm2835_dma.h
new file mode 100644
index 0000000..785cf2c
--- /dev/null
+++ b/sys/arm/broadcom/bcm2835/bcm2835_dma.h
@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2013 Daisuke Aoyama <aoyama@peach.ne.jp>
+ * Copyright (c) 2013 Oleksandr Tymoshenko <gonzo@bluezbox.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#ifndef _BCM2835_DMA_H_
+#define _BCM2835_DMA_H_
+
+#define BCM_DMA_BLOCK_SIZE 512
+
+/* DMA0-DMA15 but DMA15 is special */
+#define BCM_DMA_CH_MAX 12
+
+/* request CH for any nubmer */
+#define BCM_DMA_CH_INVALID (-1)
+#define BCM_DMA_CH_ANY (-1)
+#define BCM_DMA_CH_FAST1 (2)
+#define BCM_DMA_CH_FAST2 (3)
+
+/* Peripheral DREQ Signals (4.2.1.3) */
+#define BCM_DMA_DREQ_NONE 0
+#define BCM_DMA_DREQ_EMMC 11
+#define BCM_DMA_DREQ_SDHOST 13
+
+#define BCM_DMA_SAME_ADDR 0
+#define BCM_DMA_INC_ADDR 1
+
+#define BCM_DMA_32BIT 0
+#define BCM_DMA_128BIT 1
+
+int bcm_dma_allocate(int req_ch);
+int bcm_dma_free(int ch);
+int bcm_dma_setup_intr(int ch, void (*func)(int, void *), void *arg);
+int bcm_dma_setup_src(int ch, int dreq, int inc_addr, int width);
+int bcm_dma_setup_dst(int ch, int dreq, int inc_addr, int width);
+int bcm_dma_start(int ch, vm_paddr_t src, vm_paddr_t dst, int len);
+uint32_t bcm_dma_length(int ch);
+
+#endif /* _BCM2835_DMA_H_ */
diff --git a/sys/arm/broadcom/bcm2835/bcm2835_sdhci.c b/sys/arm/broadcom/bcm2835/bcm2835_sdhci.c
index cfba2cd..3512954 100644
--- a/sys/arm/broadcom/bcm2835/bcm2835_sdhci.c
+++ b/sys/arm/broadcom/bcm2835/bcm2835_sdhci.c
@@ -67,8 +67,13 @@ __FBSDID("$FreeBSD$");
#include <dev/sdhci/sdhci.h>
#include "sdhci_if.h"
+#include "bcm2835_dma.h"
+#include "bcm2835_vcbus.h"
+
#define BCM2835_DEFAULT_SDHCI_FREQ 50
+#define BCM_SDHCI_BUFFER_SIZE 512
+
#define DEBUG
#ifdef DEBUG
@@ -85,9 +90,11 @@ __FBSDID("$FreeBSD$");
*/
static int bcm2835_sdhci_min_freq = 400000;
static int bcm2835_sdhci_hs = 1;
+static int bcm2835_sdhci_pio_mode = 0;
TUNABLE_INT("hw.bcm2835.sdhci.min_freq", &bcm2835_sdhci_min_freq);
TUNABLE_INT("hw.bcm2835.sdhci.hs", &bcm2835_sdhci_hs);
+TUNABLE_INT("hw.bcm2835.sdhci.pio_mode", &bcm2835_sdhci_pio_mode);
struct bcm_sdhci_dmamap_arg {
bus_addr_t sc_dma_busaddr;
@@ -111,23 +118,41 @@ struct bcm_sdhci_softc {
int sc_xfer_done;
int sc_bus_busy;
struct sdhci_slot sc_slot;
+ int sc_dma_inuse;
+ int sc_dma_ch;
+ bus_dma_tag_t sc_dma_tag;
+ bus_dmamap_t sc_dma_map;
+ void *sc_dma_buffer;
+ vm_paddr_t sc_dma_buffer_phys;
+ vm_paddr_t sc_sdhci_buffer_phys;;
};
-#define SD_MAX_BLOCKSIZE 1024
-/* XXX */
-
static int bcm_sdhci_probe(device_t);
static int bcm_sdhci_attach(device_t);
static int bcm_sdhci_detach(device_t);
static void bcm_sdhci_intr(void *);
static int bcm_sdhci_get_ro(device_t, device_t);
+static void bcm_sdhci_dma_intr(int ch, void *arg);
#define bcm_sdhci_lock(_sc) \
mtx_lock(&_sc->sc_mtx);
#define bcm_sdhci_unlock(_sc) \
mtx_unlock(&_sc->sc_mtx);
+static void
+bcm_dmamap_cb(void *arg, bus_dma_segment_t *segs,
+ int nseg, int err)
+{
+ bus_addr_t *addr;
+
+ if (err)
+ return;
+
+ addr = (bus_addr_t*)arg;
+ *addr = segs[0].ds_addr;
+}
+
static int
bcm_sdhci_probe(device_t dev)
{
@@ -146,9 +171,13 @@ bcm_sdhci_attach(device_t dev)
phandle_t node;
pcell_t cell;
int default_freq;
+ void *buffer;
+ vm_paddr_t buffer_phys;
+ void *va;
sc->sc_dev = dev;
sc->sc_req = NULL;
+ err = 0;
default_freq = BCM2835_DEFAULT_SDHCI_FREQ;
node = ofw_bus_get_node(sc->sc_dev);
@@ -191,6 +220,9 @@ bcm_sdhci_attach(device_t dev)
goto fail;
}
+ if (!bcm2835_sdhci_pio_mode)
+ sc->sc_slot.opt = SDHCI_PLATFORM_TRANSFER;
+
sc->sc_slot.caps = SDHCI_CAN_VDD_330 | SDHCI_CAN_VDD_180;
if (bcm2835_sdhci_hs)
sc->sc_slot.caps |= SDHCI_CAN_DO_HISPD;
@@ -201,6 +233,61 @@ bcm_sdhci_attach(device_t dev)
sdhci_init_slot(dev, &sc->sc_slot, 0);
+ sc->sc_dma_ch = bcm_dma_allocate(BCM_DMA_CH_FAST1);
+ if (sc->sc_dma_ch == BCM_DMA_CH_INVALID)
+ sc->sc_dma_ch = bcm_dma_allocate(BCM_DMA_CH_FAST2);
+ if (sc->sc_dma_ch == BCM_DMA_CH_INVALID)
+ sc->sc_dma_ch = bcm_dma_allocate(BCM_DMA_CH_ANY);
+ if (sc->sc_dma_ch == BCM_DMA_CH_INVALID)
+ goto fail;
+
+ bcm_dma_setup_intr(sc->sc_dma_ch, bcm_sdhci_dma_intr, sc);
+
+ /* Allocate DMA buffers */
+ err = bus_dma_tag_create(bus_get_dma_tag(dev),
+ 1, 0, BUS_SPACE_MAXADDR_32BIT,
+ BUS_SPACE_MAXADDR, NULL, NULL,
+ BCM_SDHCI_BUFFER_SIZE, 1, BCM_SDHCI_BUFFER_SIZE,
+ BUS_DMA_ALLOCNOW, NULL, NULL,
+ &sc->sc_dma_tag);
+
+ if (err) {
+ device_printf(dev, "failed allocate DMA tag");
+ goto fail;
+ }
+
+ err = bus_dmamem_alloc(sc->sc_dma_tag, &buffer,
+ BUS_DMA_WAITOK | BUS_DMA_COHERENT| BUS_DMA_ZERO,
+ &sc->sc_dma_map);
+
+ if (err) {
+ device_printf(dev, "cannot allocate DMA memory\n");
+ goto fail;
+ }
+
+ err = bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map, buffer,
+ BCM_SDHCI_BUFFER_SIZE, bcm_dmamap_cb, &buffer_phys,
+ BUS_DMA_WAITOK);
+ if (err) {
+ device_printf(dev, "cannot load DMA memory\n");
+ goto fail;
+ }
+
+ /*
+ * Sanity check: two least bits of address should be zero
+ */
+ if ((uintptr_t)buffer & 3) {
+ device_printf(dev,
+ "DMA address is not word-aligned\n");
+ goto fail;
+ }
+
+ sc->sc_dma_buffer = buffer;
+ sc->sc_dma_buffer_phys = buffer_phys;
+ va = (void*)rman_get_start(sc->sc_mem_res);
+ sc->sc_sdhci_buffer_phys =
+ pmap_kextract((vm_offset_t)va) + SDHCI_BUFFER;
+
bus_generic_probe(dev);
bus_generic_attach(dev);
@@ -354,6 +441,211 @@ bcm_sdhci_min_freq(device_t dev, struct sdhci_slot *slot)
return bcm2835_sdhci_min_freq;
}
+static void
+bcm_sdhci_dma_intr(int ch, void *arg)
+{
+ struct bcm_sdhci_softc *sc = (struct bcm_sdhci_softc *)arg;
+ struct sdhci_slot *slot = &sc->sc_slot;
+ uint32_t reg, mask;
+ void *buffer;
+ size_t len;
+ int left;
+
+ mtx_lock(&slot->mtx);
+
+ /* copy DMA buffer to VA if READ */
+ len = bcm_dma_length(sc->sc_dma_ch);
+ if (slot->curcmd->data->flags & MMC_DATA_READ) {
+ bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map,
+ BUS_DMASYNC_POSTREAD);
+
+ mask = SDHCI_INT_DATA_AVAIL;
+ /* all dma data in single or contiguous page */
+ buffer = (uint8_t*)(slot->curcmd->data->data) + slot->offset;
+ memcpy(buffer, sc->sc_dma_buffer, len);
+ } else {
+ bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map,
+ BUS_DMASYNC_POSTWRITE);
+ mask = SDHCI_INT_SPACE_AVAIL;
+ }
+
+ slot->offset += len;
+ sc->sc_dma_inuse = 0;
+
+ left = min(BCM_SDHCI_BUFFER_SIZE,
+ slot->curcmd->data->len - slot->offset);
+
+ /* DATA END? */
+ reg = bcm_sdhci_read_4(slot->bus, slot, SDHCI_INT_STATUS);
+
+ if (reg & SDHCI_INT_DATA_END) {
+ /* ACK for all outstanding interrupts */
+ bcm_sdhci_write_4(slot->bus, slot, SDHCI_INT_STATUS, reg);
+
+ /* enable INT */
+ slot->intmask |= SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL
+ | SDHCI_INT_DATA_END;
+ bcm_sdhci_write_4(slot->bus, slot, SDHCI_SIGNAL_ENABLE,
+ slot->intmask);
+
+ /* finish this data */
+ sdhci_finish_data(slot);
+ }
+ else {
+ /* already available? */
+ if (reg & mask) {
+ sc->sc_dma_inuse = 1;
+
+ /* ACK for DATA_AVAIL or SPACE_AVAIL */
+ bcm_sdhci_write_4(slot->bus, slot,
+ SDHCI_INT_STATUS, mask);
+
+ /* continue next DMA transfer */
+ if (slot->curcmd->data->flags & MMC_DATA_READ) {
+ bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map,
+ BUS_DMASYNC_PREREAD);
+
+ /* DMA start */
+ if (bcm_dma_start(sc->sc_dma_ch,
+ sc->sc_sdhci_buffer_phys,
+ sc->sc_dma_buffer_phys, left) != 0)
+ device_printf(sc->sc_dev, "failed DMA start\n");
+ } else {
+ buffer = (char*)slot->curcmd->data->data + slot->offset;
+ memcpy(sc->sc_dma_buffer, buffer, left);
+
+ bus_dmamap_sync(sc->sc_dma_tag,
+ sc->sc_dma_map, BUS_DMASYNC_PREWRITE);
+
+ /* DMA start */
+ if (bcm_dma_start(sc->sc_dma_ch,
+ sc->sc_dma_buffer_phys,
+ sc->sc_sdhci_buffer_phys, left) != 0)
+ device_printf(sc->sc_dev, "failed DMA start\n");
+ }
+ } else {
+ /* wait for next data by INT */
+
+ /* enable INT */
+ slot->intmask |= SDHCI_INT_DATA_AVAIL |
+ SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_END;
+ bcm_sdhci_write_4(slot->bus, slot, SDHCI_SIGNAL_ENABLE,
+ slot->intmask);
+ }
+ }
+
+ mtx_unlock(&slot->mtx);
+}
+
+static void
+bcm_sdhci_read_dma(struct sdhci_slot *slot)
+{
+ struct bcm_sdhci_softc *sc = device_get_softc(slot->bus);
+ size_t left;
+
+ if (sc->sc_dma_inuse) {
+ device_printf(sc->sc_dev, "DMA in use\n");
+ return;
+ }
+
+ sc->sc_dma_inuse = 1;
+
+ left = min(BCM_SDHCI_BUFFER_SIZE,
+ slot->curcmd->data->len - slot->offset);
+
+ KASSERT((left & 3) == 0,
+ ("%s: len = %d, not word-aligned", __func__, left));
+
+ bcm_dma_setup_src(sc->sc_dma_ch, BCM_DMA_DREQ_EMMC,
+ BCM_DMA_SAME_ADDR, BCM_DMA_32BIT);
+ bcm_dma_setup_dst(sc->sc_dma_ch, BCM_DMA_DREQ_NONE,
+ BCM_DMA_INC_ADDR,
+ (left & 0xf) ? BCM_DMA_32BIT : BCM_DMA_128BIT);
+
+ bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map,
+ BUS_DMASYNC_PREREAD);
+
+ /* DMA start */
+ if (bcm_dma_start(sc->sc_dma_ch, sc->sc_sdhci_buffer_phys,
+ sc->sc_dma_buffer_phys, left) != 0)
+ device_printf(sc->sc_dev, "failed DMA start\n");
+}
+
+static void
+bcm_sdhci_write_dma(struct sdhci_slot *slot)
+{
+ struct bcm_sdhci_softc *sc = device_get_softc(slot->bus);
+ char *buffer;
+ size_t left;
+
+ if (sc->sc_dma_inuse) {
+ device_printf(sc->sc_dev, "DMA in use\n");
+ return;
+ }
+
+ sc->sc_dma_inuse = 1;
+
+ left = min(BCM_SDHCI_BUFFER_SIZE,
+ slot->curcmd->data->len - slot->offset);
+
+ KASSERT((left & 3) == 0,
+ ("%s: len = %d, not word-aligned", __func__, left));
+
+ buffer = (char*)slot->curcmd->data->data + slot->offset;
+ memcpy(sc->sc_dma_buffer, buffer, left);
+
+ bcm_dma_setup_src(sc->sc_dma_ch, BCM_DMA_DREQ_NONE,
+ BCM_DMA_INC_ADDR,
+ (left & 0xf) ? BCM_DMA_32BIT : BCM_DMA_128BIT);
+ bcm_dma_setup_dst(sc->sc_dma_ch, BCM_DMA_DREQ_EMMC,
+ BCM_DMA_SAME_ADDR, BCM_DMA_32BIT);
+
+ bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map,
+ BUS_DMASYNC_PREWRITE);
+
+ /* DMA start */
+ if (bcm_dma_start(sc->sc_dma_ch, sc->sc_dma_buffer_phys,
+ sc->sc_sdhci_buffer_phys, left) != 0)
+ device_printf(sc->sc_dev, "failed DMA start\n");
+}
+
+static int
+bcm_sdhci_will_handle_transfer(device_t dev, struct sdhci_slot *slot)
+{
+ size_t left;
+
+ /* Do not use DMA for transfers less then block size */
+ left = min(BCM_DMA_BLOCK_SIZE,
+ slot->curcmd->data->len - slot->offset);
+ if (left < BCM_DMA_BLOCK_SIZE)
+ return (0);
+
+ return (1);
+}
+
+static void
+bcm_sdhci_start_transfer(device_t dev, struct sdhci_slot *slot,
+ uint32_t *intmask)
+{
+
+ /* Disable INT */
+ slot->intmask &= ~(SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_END);
+ bcm_sdhci_write_4(dev, slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
+
+ /* DMA transfer FIFO 1KB */
+ if (slot->curcmd->data->flags & MMC_DATA_READ)
+ bcm_sdhci_read_dma(slot);
+ else
+ bcm_sdhci_write_dma(slot);
+}
+
+static void
+bcm_sdhci_finish_transfer(device_t dev, struct sdhci_slot *slot)
+{
+
+ sdhci_finish_data(slot);
+}
+
static device_method_t bcm_sdhci_methods[] = {
/* Device interface */
DEVMETHOD(device_probe, bcm_sdhci_probe),
@@ -372,8 +664,12 @@ static device_method_t bcm_sdhci_methods[] = {
DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host),
DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host),
- /* SDHCI registers accessors */
DEVMETHOD(sdhci_min_freq, bcm_sdhci_min_freq),
+ /* Platform transfer methods */
+ DEVMETHOD(sdhci_platform_will_handle, bcm_sdhci_will_handle_transfer),
+ DEVMETHOD(sdhci_platform_start_transfer, bcm_sdhci_start_transfer),
+ DEVMETHOD(sdhci_platform_finish_transfer, bcm_sdhci_finish_transfer),
+ /* SDHCI registers accessors */
DEVMETHOD(sdhci_read_1, bcm_sdhci_read_1),
DEVMETHOD(sdhci_read_2, bcm_sdhci_read_2),
DEVMETHOD(sdhci_read_4, bcm_sdhci_read_4),
diff --git a/sys/arm/broadcom/bcm2835/bcm2835_systimer.c b/sys/arm/broadcom/bcm2835/bcm2835_systimer.c
index 97ec43a..1d7fdda 100644
--- a/sys/arm/broadcom/bcm2835/bcm2835_systimer.c
+++ b/sys/arm/broadcom/bcm2835/bcm2835_systimer.c
@@ -118,19 +118,16 @@ bcm_systimer_tc_get_timecount(struct timecounter *tc)
}
static int
-bcm_systimer_start(struct eventtimer *et, struct bintime *first,
- struct bintime *period)
+bcm_systimer_start(struct eventtimer *et, sbintime_t first, sbintime_t period)
{
struct systimer *st = et->et_priv;
uint32_t clo;
uint32_t count;
register_t s;
- if (first != NULL) {
+ if (first != 0) {
- count = (st->et.et_frequency * (first->frac >> 32)) >> 32;
- if (first->sec != 0)
- count += st->et.et_frequency * first->sec;
+ count = ((uint32_t)et->et_frequency * first) >> 32;
s = intr_disable();
clo = bcm_systimer_tc_read_4(SYSTIMER_CLO);
@@ -238,12 +235,10 @@ bcm_systimer_attach(device_t dev)
sc->st[DEFAULT_TIMER].et.et_flags = ET_FLAGS_ONESHOT;
sc->st[DEFAULT_TIMER].et.et_quality = 1000;
sc->st[DEFAULT_TIMER].et.et_frequency = sc->sysclk_freq;
- sc->st[DEFAULT_TIMER].et.et_min_period.sec = 0;
- sc->st[DEFAULT_TIMER].et.et_min_period.frac =
- ((MIN_PERIOD << 32) / sc->st[DEFAULT_TIMER].et.et_frequency) << 32;
- sc->st[DEFAULT_TIMER].et.et_max_period.sec = 0xfffffff0U / sc->st[DEFAULT_TIMER].et.et_frequency;
- sc->st[DEFAULT_TIMER].et.et_max_period.frac =
- ((0xfffffffeLLU << 32) / sc->st[DEFAULT_TIMER].et.et_frequency) << 32;
+ sc->st[DEFAULT_TIMER].et.et_min_period =
+ (MIN_PERIOD << 32) / sc->st[DEFAULT_TIMER].et.et_frequency;
+ sc->st[DEFAULT_TIMER].et.et_max_period =
+ (0xfffffffeLLU << 32) / sc->st[DEFAULT_TIMER].et.et_frequency;
sc->st[DEFAULT_TIMER].et.et_start = bcm_systimer_start;
sc->st[DEFAULT_TIMER].et.et_stop = bcm_systimer_stop;
sc->st[DEFAULT_TIMER].et.et_priv = &sc->st[DEFAULT_TIMER];
diff --git a/sys/arm/broadcom/bcm2835/files.bcm2835 b/sys/arm/broadcom/bcm2835/files.bcm2835
index 9885155..aa1af40 100644
--- a/sys/arm/broadcom/bcm2835/files.bcm2835
+++ b/sys/arm/broadcom/bcm2835/files.bcm2835
@@ -1,5 +1,6 @@
# $FreeBSD$
+arm/broadcom/bcm2835/bcm2835_dma.c standard
arm/broadcom/bcm2835/bcm2835_fb.c optional sc
arm/broadcom/bcm2835/bcm2835_gpio.c optional gpio
arm/broadcom/bcm2835/bcm2835_intr.c standard
diff --git a/sys/arm/conf/CUBIEBOARD b/sys/arm/conf/CUBIEBOARD
index fa5bfc8..1c0407b 100644
--- a/sys/arm/conf/CUBIEBOARD
+++ b/sys/arm/conf/CUBIEBOARD
@@ -87,8 +87,8 @@ options ROOTDEVNAME=\"ufs:/dev/da0s2\"
#options ATA_STATIC_ID # Static device numbering
# Console and misc
-#device uart
-#device uart_ns8250
+device uart
+device uart_ns8250
device pty
device snp
device md
diff --git a/sys/arm/conf/RPI-B b/sys/arm/conf/RPI-B
index d9e8d38..4d840cb 100644
--- a/sys/arm/conf/RPI-B
+++ b/sys/arm/conf/RPI-B
@@ -117,4 +117,4 @@ options FDT
# Note: DTB is normally loaded and modified by RPi boot loader, then
# handed to kernel via U-Boot and ubldr.
#options FDT_DTB_STATIC
-#makeoptions FDT_DTS_FILE=bcm2835-rpi-b.dts
+makeoptions FDT_DTS_FILE=bcm2835-rpi-b.dts
diff --git a/sys/arm/econa/econa_machdep.c b/sys/arm/econa/econa_machdep.c
index d622860..d64e826 100644
--- a/sys/arm/econa/econa_machdep.c
+++ b/sys/arm/econa/econa_machdep.c
@@ -68,7 +68,6 @@ __FBSDID("$FreeBSD$");
#include <vm/vm_object.h>
#include <vm/vm_page.h>
#include <vm/vm_map.h>
-#include <machine/pmap.h>
#include <machine/vmparam.h>
#include <machine/pcb.h>
#include <machine/undefined.h>
diff --git a/sys/arm/include/vmparam.h b/sys/arm/include/vmparam.h
index 09bf62c..9765b34 100644
--- a/sys/arm/include/vmparam.h
+++ b/sys/arm/include/vmparam.h
@@ -34,9 +34,32 @@
#ifndef _MACHINE_VMPARAM_H_
#define _MACHINE_VMPARAM_H_
+/*
+ * Machine dependent constants for ARM.
+ */
+
+/*
+ * Virtual memory related constants, all in bytes
+ */
+#ifndef MAXTSIZ
+#define MAXTSIZ (64UL*1024*1024) /* max text size */
+#endif
+#ifndef DFLDSIZ
+#define DFLDSIZ (128UL*1024*1024) /* initial data size limit */
+#endif
+#ifndef MAXDSIZ
+#define MAXDSIZ (512UL*1024*1024) /* max data size */
+#endif
+#ifndef DFLSSIZ
+#define DFLSSIZ (2UL*1024*1024) /* initial stack size limit */
+#endif
+#ifndef MAXSSIZ
+#define MAXSSIZ (8UL*1024*1024) /* max stack size */
+#endif
+#ifndef SGROWSIZ
+#define SGROWSIZ (128UL*1024) /* amount to grow stack */
+#endif
-/*#include <arm/arm32/vmparam.h>
-*/
/*
* Address space constants
*/
@@ -153,23 +176,6 @@
VM_MIN_KERNEL_ADDRESS + 1) * 2 / 5)
#endif
-#define MAXTSIZ (16*1024*1024)
-#ifndef DFLDSIZ
-#define DFLDSIZ (128*1024*1024)
-#endif
-#ifndef MAXDSIZ
-#define MAXDSIZ (512*1024*1024)
-#endif
-#ifndef DFLSSIZ
-#define DFLSSIZ (2*1024*1024)
-#endif
-#ifndef MAXSSIZ
-#define MAXSSIZ (8*1024*1024)
-#endif
-#ifndef SGROWSIZ
-#define SGROWSIZ (128*1024)
-#endif
-
#ifdef ARM_USE_SMALL_ALLOC
#define UMA_MD_SMALL_ALLOC
#endif /* ARM_USE_SMALL_ALLOC */
@@ -178,4 +184,8 @@ extern vm_offset_t vm_max_kernel_address;
#define ZERO_REGION_SIZE (64 * 1024) /* 64KB */
+#ifndef VM_MAX_AUTOTUNE_MAXUSERS
+#define VM_MAX_AUTOTUNE_MAXUSERS 384
+#endif
+
#endif /* _MACHINE_VMPARAM_H_ */
diff --git a/sys/arm/lpc/lpc_timer.c b/sys/arm/lpc/lpc_timer.c
index 87ed104..8572e1a 100644
--- a/sys/arm/lpc/lpc_timer.c
+++ b/sys/arm/lpc/lpc_timer.c
@@ -72,8 +72,8 @@ static struct lpc_timer_softc *timer_softc = NULL;
static int lpc_timer_initialized = 0;
static int lpc_timer_probe(device_t);
static int lpc_timer_attach(device_t);
-static int lpc_timer_start(struct eventtimer *, struct bintime *first,
- struct bintime *);
+static int lpc_timer_start(struct eventtimer *,
+ sbintime_t first, sbintime_t period);
static int lpc_timer_stop(struct eventtimer *et);
static unsigned lpc_get_timecount(struct timecounter *);
static int lpc_hardclock(void *);
@@ -173,12 +173,8 @@ lpc_timer_attach(device_t dev)
sc->lt_et.et_name = "LPC32x0 Timer0";
sc->lt_et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT;
sc->lt_et.et_quality = 1000;
- sc->lt_et.et_min_period.sec = 0;
- sc->lt_et.et_min_period.frac =
- ((0x00000002LLU << 32) / sc->lt_et.et_frequency) << 32;
- sc->lt_et.et_max_period.sec = 0xfffffff0U / sc->lt_et.et_frequency;
- sc->lt_et.et_max_period.frac =
- ((0xfffffffeLLU << 32) / sc->lt_et.et_frequency) << 32;
+ sc->lt_et.et_min_period = (0x00000002LLU << 32) / sc->lt_et.et_frequency;
+ sc->lt_et.et_max_period = (0xfffffffeLLU << 32) / sc->lt_et.et_frequency;
sc->lt_et.et_start = lpc_timer_start;
sc->lt_et.et_stop = lpc_timer_stop;
sc->lt_et.et_priv = sc;
@@ -199,27 +195,23 @@ lpc_timer_attach(device_t dev)
}
static int
-lpc_timer_start(struct eventtimer *et, struct bintime *first,
- struct bintime *period)
+lpc_timer_start(struct eventtimer *et, sbintime_t first, sbintime_t period)
{
struct lpc_timer_softc *sc = (struct lpc_timer_softc *)et->et_priv;
uint32_t ticks;
- if (period == NULL)
+ if (period == 0) {
sc->lt_oneshot = 1;
- else {
+ sc->lt_period = 0;
+ } else {
sc->lt_oneshot = 0;
- sc->lt_period = (sc->lt_et.et_frequency * (first->frac >> 32)) >> 32;
- sc->lt_period += sc->lt_et.et_frequency * first->sec;
+ sc->lt_period = ((uint32_t)et->et_frequency * period) >> 32;
}
- if (first == NULL)
+ if (first == 0)
ticks = sc->lt_period;
- else {
- ticks = (sc->lt_et.et_frequency * (first->frac >> 32)) >> 32;
- if (first->sec != 0)
- ticks += sc->lt_et.et_frequency * first->sec;
- }
+ else
+ ticks = ((uint32_t)et->et_frequency * first) >> 32;
/* Reset timer */
timer0_write_4(sc, LPC_TIMER_TCR, LPC_TIMER_TCR_RESET);
diff --git a/sys/arm/mv/timer.c b/sys/arm/mv/timer.c
index db6e404..51a6c17 100644
--- a/sys/arm/mv/timer.c
+++ b/sys/arm/mv/timer.c
@@ -93,7 +93,7 @@ static void mv_watchdog_enable(void);
static void mv_watchdog_disable(void);
static void mv_watchdog_event(void *, unsigned int, int *);
static int mv_timer_start(struct eventtimer *et,
- struct bintime *first, struct bintime *period);
+ sbintime_t first, sbintime_t period);
static int mv_timer_stop(struct eventtimer *et);
static void mv_setup_timers(void);
@@ -168,12 +168,8 @@ mv_timer_attach(device_t dev)
sc->et.et_quality = 1000;
sc->et.et_frequency = MV_CLOCK_SRC;
- sc->et.et_min_period.sec = 0;
- sc->et.et_min_period.frac =
- ((0x00000002LLU << 32) / sc->et.et_frequency) << 32;
- sc->et.et_max_period.sec = 0xfffffff0U / sc->et.et_frequency;
- sc->et.et_max_period.frac =
- ((0xfffffffeLLU << 32) / sc->et.et_frequency) << 32;
+ sc->et.et_min_period = (0x00000002LLU << 32) / sc->et.et_frequency;
+ sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency;
sc->et.et_start = mv_timer_start;
sc->et.et_stop = mv_timer_stop;
sc->et.et_priv = sc;
@@ -394,25 +390,20 @@ mv_watchdog_event(void *arg, unsigned int cmd, int *error)
}
static int
-mv_timer_start(struct eventtimer *et,
- struct bintime *first, struct bintime *period)
+mv_timer_start(struct eventtimer *et, sbintime_t first, sbintime_t period)
{
struct mv_timer_softc *sc;
uint32_t val, val1;
/* Calculate dividers. */
sc = (struct mv_timer_softc *)et->et_priv;
- if (period != NULL) {
- val = (sc->et.et_frequency * (period->frac >> 32)) >> 32;
- if (period->sec != 0)
- val += sc->et.et_frequency * period->sec;
- } else
+ if (period != 0)
+ val = ((uint32_t)sc->et.et_frequency * period) >> 32;
+ else
val = 0;
- if (first != NULL) {
- val1 = (sc->et.et_frequency * (first->frac >> 32)) >> 32;
- if (first->sec != 0)
- val1 += sc->et.et_frequency * first->sec;
- } else
+ if (first != 0)
+ val1 = ((uint32_t)sc->et.et_frequency * first) >> 32;
+ else
val1 = val;
/* Apply configuration. */
@@ -420,7 +411,7 @@ mv_timer_start(struct eventtimer *et,
mv_set_timer(0, val1);
val = mv_get_timer_control();
val |= CPU_TIMER0_EN;
- if (period != NULL)
+ if (period != 0)
val |= CPU_TIMER0_AUTO;
else
val &= ~CPU_TIMER0_AUTO;
diff --git a/sys/arm/s3c2xx0/s3c24x0_machdep.c b/sys/arm/s3c2xx0/s3c24x0_machdep.c
index e497bc4..1811b52 100644
--- a/sys/arm/s3c2xx0/s3c24x0_machdep.c
+++ b/sys/arm/s3c2xx0/s3c24x0_machdep.c
@@ -78,7 +78,6 @@ __FBSDID("$FreeBSD$");
#include <vm/vm_object.h>
#include <vm/vm_page.h>
#include <vm/vm_map.h>
-#include <machine/pmap.h>
#include <machine/vmparam.h>
#include <machine/pcb.h>
#include <machine/undefined.h>
diff --git a/sys/arm/ti/am335x/am335x_dmtimer.c b/sys/arm/ti/am335x/am335x_dmtimer.c
index be9832c..93911f2 100644
--- a/sys/arm/ti/am335x/am335x_dmtimer.c
+++ b/sys/arm/ti/am335x/am335x_dmtimer.c
@@ -143,30 +143,24 @@ am335x_dmtimer_tc_get_timecount(struct timecounter *tc)
}
static int
-am335x_dmtimer_start(struct eventtimer *et, struct bintime *first,
- struct bintime *period)
+am335x_dmtimer_start(struct eventtimer *et, sbintime_t first, sbintime_t period)
{
struct am335x_dmtimer *tmr = (struct am335x_dmtimer *)et->et_priv;
uint32_t load, count;
uint32_t tclr = 0;
- if (period != NULL) {
- load = (et->et_frequency * (period->frac >> 32)) >> 32;
- if (period->sec > 0)
- load += et->et_frequency * period->sec;
+ if (period != 0) {
+ load = ((uint32_t)et->et_frequency * period) >> 32;
tclr |= 2; /* autoreload bit */
panic("periodic timer not implemented\n");
} else {
load = 0;
}
- if (first != NULL) {
- count = (tmr->et.et_frequency * (first->frac >> 32)) >> 32;
- if (first->sec != 0)
- count += tmr->et.et_frequency * first->sec;
- } else {
+ if (first != 0)
+ count = ((uint32_t)et->et_frequency * first) >> 32;
+ else
count = load;
- }
/* Reset Timer */
am335x_dmtimer_et_write_4(DMTIMER_TSICR, 2);
@@ -316,12 +310,10 @@ am335x_dmtimer_attach(device_t dev)
sc->t[3].et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT;
sc->t[3].et.et_quality = 1000;
sc->t[3].et.et_frequency = sc->sysclk_freq;
- sc->t[3].et.et_min_period.sec = 0;
- sc->t[3].et.et_min_period.frac =
- ((0x00000002LLU << 32) / sc->t[3].et.et_frequency) << 32;
- sc->t[3].et.et_max_period.sec = 0xfffffff0U / sc->t[3].et.et_frequency;
- sc->t[3].et.et_max_period.frac =
- ((0xfffffffeLLU << 32) / sc->t[3].et.et_frequency) << 32;
+ sc->t[3].et.et_min_period =
+ (0x00000002LLU << 32) / sc->t[3].et.et_frequency;
+ sc->t[3].et.et_max_period =
+ (0xfffffffeLLU << 32) / sc->t[3].et.et_frequency;
sc->t[3].et.et_start = am335x_dmtimer_start;
sc->t[3].et.et_stop = am335x_dmtimer_stop;
sc->t[3].et.et_priv = &sc->t[3];
diff --git a/sys/arm/versatile/sp804.c b/sys/arm/versatile/sp804.c
index 82a1889..000ccb6 100644
--- a/sys/arm/versatile/sp804.c
+++ b/sys/arm/versatile/sp804.c
@@ -120,18 +120,15 @@ sp804_timer_tc_get_timecount(struct timecounter *tc)
}
static int
-sp804_timer_start(struct eventtimer *et, struct bintime *first,
- struct bintime *period)
+sp804_timer_start(struct eventtimer *et, sbintime_t first, sbintime_t period)
{
struct sp804_timer_softc *sc = et->et_priv;
uint32_t count, reg;
- if (first != NULL) {
+ if (first != 0) {
sc->et_enabled = 1;
- count = (sc->et.et_frequency * (first->frac >> 32)) >> 32;
- if (first->sec != 0)
- count += sc->et.et_frequency * first->sec;
+ count = ((uint32_t)et->et_frequency * first) >> 32;
sp804_timer_tc_write_4(SP804_TIMER2_LOAD, count);
reg = TIMER_CONTROL_32BIT | TIMER_CONTROL_INTREN |
@@ -142,7 +139,7 @@ sp804_timer_start(struct eventtimer *et, struct bintime *first,
return (0);
}
- if (period != NULL) {
+ if (period != 0) {
panic("period");
}
@@ -264,12 +261,8 @@ sp804_timer_attach(device_t dev)
sc->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT;
sc->et.et_quality = 1000;
sc->et.et_frequency = sc->sysclk_freq / DEFAULT_DIVISOR;
- sc->et.et_min_period.sec = 0;
- sc->et.et_min_period.frac =
- ((0x00000002LLU << 32) / sc->et.et_frequency) << 32;
- sc->et.et_max_period.sec = 0xfffffff0U / sc->et.et_frequency;
- sc->et.et_max_period.frac =
- ((0xfffffffeLLU << 32) / sc->et.et_frequency) << 32;
+ sc->et.et_min_period = (0x00000002LLU << 32) / sc->et.et_frequency;
+ sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency;
sc->et.et_start = sp804_timer_start;
sc->et.et_stop = sp804_timer_stop;
sc->et.et_priv = sc;
diff --git a/sys/arm/xscale/i80321/ep80219_machdep.c b/sys/arm/xscale/i80321/ep80219_machdep.c
index cb3d161..ff2f1c3 100644
--- a/sys/arm/xscale/i80321/ep80219_machdep.c
+++ b/sys/arm/xscale/i80321/ep80219_machdep.c
@@ -78,7 +78,6 @@ __FBSDID("$FreeBSD$");
#include <vm/vm_object.h>
#include <vm/vm_page.h>
#include <vm/vm_map.h>
-#include <machine/pmap.h>
#include <machine/vmparam.h>
#include <machine/pcb.h>
#include <machine/undefined.h>
diff --git a/sys/arm/xscale/i80321/iq31244_machdep.c b/sys/arm/xscale/i80321/iq31244_machdep.c
index 2375b6b..1412635 100644
--- a/sys/arm/xscale/i80321/iq31244_machdep.c
+++ b/sys/arm/xscale/i80321/iq31244_machdep.c
@@ -78,7 +78,6 @@ __FBSDID("$FreeBSD$");
#include <vm/vm_object.h>
#include <vm/vm_page.h>
#include <vm/vm_map.h>
-#include <machine/pmap.h>
#include <machine/vmparam.h>
#include <machine/pcb.h>
#include <machine/undefined.h>
diff --git a/sys/arm/xscale/i8134x/crb_machdep.c b/sys/arm/xscale/i8134x/crb_machdep.c
index a1344af..4ae836b 100644
--- a/sys/arm/xscale/i8134x/crb_machdep.c
+++ b/sys/arm/xscale/i8134x/crb_machdep.c
@@ -78,7 +78,6 @@ __FBSDID("$FreeBSD$");
#include <vm/vm_object.h>
#include <vm/vm_page.h>
#include <vm/vm_map.h>
-#include <machine/pmap.h>
#include <machine/vmparam.h>
#include <machine/pcb.h>
#include <machine/undefined.h>
diff --git a/sys/arm/xscale/ixp425/avila_machdep.c b/sys/arm/xscale/ixp425/avila_machdep.c
index 07026da..82e1aab0 100644
--- a/sys/arm/xscale/ixp425/avila_machdep.c
+++ b/sys/arm/xscale/ixp425/avila_machdep.c
@@ -78,7 +78,6 @@ __FBSDID("$FreeBSD$");
#include <vm/vm_object.h>
#include <vm/vm_page.h>
#include <vm/vm_map.h>
-#include <machine/pmap.h>
#include <machine/vmparam.h>
#include <machine/pcb.h>
#include <machine/undefined.h>
diff --git a/sys/arm/xscale/pxa/pxa_machdep.c b/sys/arm/xscale/pxa/pxa_machdep.c
index 706fb58..5640622 100644
--- a/sys/arm/xscale/pxa/pxa_machdep.c
+++ b/sys/arm/xscale/pxa/pxa_machdep.c
@@ -80,7 +80,6 @@ __FBSDID("$FreeBSD$");
#include <vm/vm_object.h>
#include <vm/vm_page.h>
#include <vm/vm_map.h>
-#include <machine/pmap.h>
#include <machine/vmparam.h>
#include <machine/pcb.h>
#include <machine/undefined.h>
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