diff options
Diffstat (limited to 'sys/arm')
| -rw-r--r-- | sys/arm/arm/cpufunc.c | 114 | ||||
| -rw-r--r-- | sys/arm/arm/cpufunc_asm_pj4b.S | 132 | ||||
| -rw-r--r-- | sys/arm/arm/identcpu.c | 8 | ||||
| -rw-r--r-- | sys/arm/arm/locore.S | 4 | ||||
| -rw-r--r-- | sys/arm/arm/mp_machdep.c | 8 | ||||
| -rw-r--r-- | sys/arm/conf/ARMADAXP | 3 | ||||
| -rw-r--r-- | sys/arm/include/armreg.h | 4 | ||||
| -rw-r--r-- | sys/arm/include/cpufunc.h | 11 | ||||
| -rw-r--r-- | sys/arm/mv/armadaxp/std.armadaxp | 12 | ||||
| -rw-r--r-- | sys/arm/mv/common.c | 70 | ||||
| -rw-r--r-- | sys/arm/mv/mv_machdep.c | 13 | ||||
| -rw-r--r-- | sys/arm/mv/mv_sata.c | 1 |
12 files changed, 100 insertions, 280 deletions
diff --git a/sys/arm/arm/cpufunc.c b/sys/arm/arm/cpufunc.c index 11c3e5e..d69f2f1 100644 --- a/sys/arm/arm/cpufunc.c +++ b/sys/arm/arm/cpufunc.c @@ -541,65 +541,6 @@ struct cpu_functions pj4bv7_cpufuncs = { pj4bv7_setup /* cpu setup */ }; - -struct cpu_functions pj4bv6_cpufuncs = { - /* CPU functions */ - - cpufunc_id, /* id */ - arm11_drain_writebuf, /* cpwait */ - - /* MMU functions */ - - cpufunc_control, /* control */ - cpufunc_domains, /* Domain */ - pj4b_setttb, /* Setttb */ - cpufunc_faultstatus, /* Faultstatus */ - cpufunc_faultaddress, /* Faultaddress */ - - /* TLB functions */ - - arm11_tlb_flushID, /* tlb_flushID */ - arm11_tlb_flushID_SE, /* tlb_flushID_SE */ - arm11_tlb_flushI, /* tlb_flushI */ - arm11_tlb_flushI_SE, /* tlb_flushI_SE */ - arm11_tlb_flushD, /* tlb_flushD */ - arm11_tlb_flushD_SE, /* tlb_flushD_SE */ - - /* Cache operations */ - armv6_icache_sync_all, /* icache_sync_all */ - pj4b_icache_sync_range, /* icache_sync_range */ - - armv6_dcache_wbinv_all, /* dcache_wbinv_all */ - pj4b_dcache_wbinv_range, /* dcache_wbinv_range */ - pj4b_dcache_inv_range, /* dcache_inv_range */ - pj4b_dcache_wb_range, /* dcache_wb_range */ - - armv6_idcache_wbinv_all, /* idcache_wbinv_all */ - pj4b_idcache_wbinv_range, /* idcache_wbinv_all */ - - (void *)cpufunc_nullop, /* l2cache_wbinv_all */ - (void *)cpufunc_nullop, /* l2cache_wbinv_range */ - (void *)cpufunc_nullop, /* l2cache_inv_range */ - (void *)cpufunc_nullop, /* l2cache_wb_range */ - - /* Other functions */ - - pj4b_drain_readbuf, /* flush_prefetchbuf */ - arm11_drain_writebuf, /* drain_writebuf */ - pj4b_flush_brnchtgt_all, /* flush_brnchtgt_C */ - pj4b_flush_brnchtgt_va, /* flush_brnchtgt_E */ - - (void *)cpufunc_nullop, /* sleep */ - - /* Soft functions */ - - cpufunc_null_fixup, /* dataabt_fixup */ - cpufunc_null_fixup, /* prefetchabt_fixup */ - - arm11_context_switch, /* context_switch */ - - pj4bv6_setup /* cpu setup */ -}; #endif /* CPU_MV_PJ4B */ #ifdef CPU_SA110 @@ -1496,27 +1437,14 @@ set_cpufuncs() #endif /* CPU_CORTEXA */ #if defined(CPU_MV_PJ4B) - if (cputype == CPU_ID_MV88SV581X_V6 || - cputype == CPU_ID_MV88SV581X_V7 || + if (cputype == CPU_ID_MV88SV581X_V7 || cputype == CPU_ID_MV88SV584X_V7 || - cputype == CPU_ID_ARM_88SV581X_V6 || cputype == CPU_ID_ARM_88SV581X_V7) { - if (cpu_pfr(0) & ARM_PFR0_THUMBEE_MASK) - cpufuncs = pj4bv7_cpufuncs; - else - cpufuncs = pj4bv6_cpufuncs; - - get_cachetype_cp15(); - pmap_pte_init_mmu_v6(); - goto out; - } else if (cputype == CPU_ID_ARM_88SV584X_V6 || - cputype == CPU_ID_MV88SV584X_V6) { - cpufuncs = pj4bv6_cpufuncs; + cpufuncs = pj4bv7_cpufuncs; get_cachetype_cp15(); pmap_pte_init_mmu_v6(); goto out; } - #endif /* CPU_MV_PJ4B */ #ifdef CPU_SA110 if (cputype == CPU_ID_SA110) { @@ -2446,44 +2374,6 @@ arm11x6_setup(char *args) #ifdef CPU_MV_PJ4B void -pj4bv6_setup(char *args) -{ - int cpuctrl; - - pj4b_config(); - - cpuctrl = CPU_CONTROL_MMU_ENABLE; -#ifndef ARM32_DISABLE_ALIGNMENT_FAULTS - cpuctrl |= CPU_CONTROL_AFLT_ENABLE; -#endif - cpuctrl |= CPU_CONTROL_DC_ENABLE; - cpuctrl |= (0xf << 3); -#ifdef __ARMEB__ - cpuctrl |= CPU_CONTROL_BEND_ENABLE; -#endif - cpuctrl |= CPU_CONTROL_SYST_ENABLE; - cpuctrl |= CPU_CONTROL_BPRD_ENABLE; - cpuctrl |= CPU_CONTROL_IC_ENABLE; - if (vector_page == ARM_VECTORS_HIGH) - cpuctrl |= CPU_CONTROL_VECRELOC; - cpuctrl |= (0x5 << 16); - cpuctrl |= CPU_CONTROL_V6_EXTPAGE; - /* XXX not yet */ - /* cpuctrl |= CPU_CONTROL_L2_ENABLE; */ - - /* Make sure caches are clean. */ - cpu_idcache_wbinv_all(); - cpu_l2cache_wbinv_all(); - - /* Set the control register */ - ctrl = cpuctrl; - cpu_control(0xffffffff, cpuctrl); - - cpu_idcache_wbinv_all(); - cpu_l2cache_wbinv_all(); -} - -void pj4bv7_setup(args) char *args; { diff --git a/sys/arm/arm/cpufunc_asm_pj4b.S b/sys/arm/arm/cpufunc_asm_pj4b.S index e6182fb..d8d400c 100644 --- a/sys/arm/arm/cpufunc_asm_pj4b.S +++ b/sys/arm/arm/cpufunc_asm_pj4b.S @@ -34,9 +34,6 @@ __FBSDID("$FreeBSD$"); #include <machine/param.h> -.Lpj4b_cache_line_size: - .word _C_LABEL(arm_pdcache_line_size) - .Lpj4b_sf_ctrl_reg: .word 0xf1021820 @@ -52,135 +49,6 @@ ENTRY(pj4b_setttb) RET END(pj4b_setttb) -ENTRY_NP(armv6_icache_sync_all) - /* - * We assume that the code here can never be out of sync with the - * dcache, so that we can safely flush the Icache and fall through - * into the Dcache cleaning code. - */ - mov r0, #0 - mcr p15, 0, r0, c7, c5, 0 /* Invalidate ICache */ - mcr p15, 0, r0, c7, c10, 0 /* Clean (don't invalidate) DCache */ - mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ - RET -END(armv6_icache_sync_all) - -ENTRY(pj4b_icache_sync_range) - sub r1, r1, #1 - add r1, r0, r1 - mcrr p15, 0, r1, r0, c5 /* invalidate IC range */ - mcrr p15, 0, r1, r0, c12 /* clean DC range */ - mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ - RET -END(pj4b_icache_sync_range) - -ENTRY(pj4b_dcache_inv_range) - ldr ip, .Lpj4b_cache_line_size - ldr ip, [ip] - sub r1, r1, #1 /* Don't overrun */ - sub r3, ip, #1 - and r2, r0, r3 - add r1, r1, r2 - bic r0, r0, r3 - - mcr p15, 0, r0, c7, c10, 5 /* Data Memory Barrier err:4413 */ -1: - mcr p15, 0, r0, c7, c6, 1 - add r0, r0, ip - subs r1, r1, ip - bpl 1b - mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ - RET -END(pj4b_dcache_inv_range) - -ENTRY(armv6_idcache_wbinv_all) - mov r0, #0 - mcr p15, 0, r0, c7, c5, 0 /* invalidate ICache */ - mcr p15, 0, r0, c7, c14, 0 /* clean and invalidate DCache */ - mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ - RET -END(armv6_idcache_wbinv_all) - -ENTRY(armv6_dcache_wbinv_all) - mov r0, #0 - mcr p15, 0, r0, c7, c14, 0 /* clean and invalidate DCache */ - mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ - RET -END(armv6_dcache_wbinv_all) - -ENTRY(pj4b_idcache_wbinv_range) - ldr ip, .Lpj4b_cache_line_size - ldr ip, [ip] - sub r1, r1, #1 /* Don't overrun */ - sub r3, ip, #1 - and r2, r0, r3 - add r1, r1, r2 - bic r0, r0, r3 - - mcr p15, 0, r0, c7, c10, 5 /* Data Memory Barrier err:4611 */ -1: -#ifdef SMP - /* Request for ownership */ - ldr r2, [r0] - str r2, [r0] -#endif - mcr p15, 0, r0, c7, c5, 1 - mcr p15, 0, r0, c7, c14, 1 /* L2C clean and invalidate entry */ - add r0, r0, ip - subs r1, r1, ip - bpl 1b - mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ - RET -END(pj4b_idcache_wbinv_range) - -ENTRY(pj4b_dcache_wbinv_range) - ldr ip, .Lpj4b_cache_line_size - ldr ip, [ip] - sub r1, r1, #1 /* Don't overrun */ - sub r3, ip, #1 - and r2, r0, r3 - add r1, r1, r2 - bic r0, r0, r3 - - mcr p15, 0, r0, c7, c10, 5 /* Data Memory Barrier err:4611 */ -1: -#ifdef SMP - /* Request for ownership */ - ldr r2, [r0] - str r2, [r0] -#endif - mcr p15, 0, r0, c7, c14, 1 - add r0, r0, ip - subs r1, r1, ip - bpl 1b - mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ - RET -END(pj4b_dcache_wbinv_range) - -ENTRY(pj4b_dcache_wb_range) - ldr ip, .Lpj4b_cache_line_size - ldr ip, [ip] - sub r1, r1, #1 /* Don't overrun */ - sub r3, ip, #1 - and r2, r0, r3 - add r1, r1, r2 - bic r0, r0, r3 - - mcr p15, 0, r0, c7, c10, 5 /* Data Memory Barrier err:4611 */ -1: -#ifdef SMP - /* Request for ownership */ - ldr r2, [r0] - str r2, [r0] -#endif - mcr p15, 0, r0, c7, c10, 1 /* L2C clean single entry by MVA */ - add r0, r0, ip - subs r1, r1, ip - bpl 1b - mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ - RET -END(pj4b_dcache_wb_range) - ENTRY(pj4b_drain_readbuf) mcr p15, 0, r0, c7, c5, 4 /* flush prefetch buffers */ RET diff --git a/sys/arm/arm/identcpu.c b/sys/arm/arm/identcpu.c index fd32666..f3870dd 100644 --- a/sys/arm/arm/identcpu.c +++ b/sys/arm/arm/identcpu.c @@ -321,18 +321,10 @@ const struct cpuidtab cpuids[] = { { CPU_ID_MV88FR571_VD, CPU_CLASS_MARVELL, "Feroceon 88FR571-VD", generic_steppings }, - { CPU_ID_MV88SV581X_V6, CPU_CLASS_MARVELL, "Sheeva 88SV581x", - generic_steppings }, - { CPU_ID_ARM_88SV581X_V6, CPU_CLASS_MARVELL, "Sheeva 88SV581x", - generic_steppings }, { CPU_ID_MV88SV581X_V7, CPU_CLASS_MARVELL, "Sheeva 88SV581x", generic_steppings }, { CPU_ID_ARM_88SV581X_V7, CPU_CLASS_MARVELL, "Sheeva 88SV581x", generic_steppings }, - { CPU_ID_MV88SV584X_V6, CPU_CLASS_MARVELL, "Sheeva 88SV584x", - generic_steppings }, - { CPU_ID_ARM_88SV584X_V6, CPU_CLASS_MARVELL, "Sheeva 88SV584x", - generic_steppings }, { CPU_ID_MV88SV584X_V7, CPU_CLASS_MARVELL, "Sheeva 88SV584x", generic_steppings }, diff --git a/sys/arm/arm/locore.S b/sys/arm/arm/locore.S index ecd7f53..678f3bf 100644 --- a/sys/arm/arm/locore.S +++ b/sys/arm/arm/locore.S @@ -266,10 +266,6 @@ mmu_init_table: /* map VA 0xc0000000..0xc3ffffff to PA */ MMU_INIT(KERNBASE, PHYSADDR, 64, L1_TYPE_S|L1_SHARED|L1_S_C|L1_S_AP(AP_KRW)) MMU_INIT(0x48000000, 0x48000000, 1, L1_TYPE_S|L1_SHARED|L1_S_C|L1_S_AP(AP_KRW)) -#if defined(CPU_MV_PJ4B) - /* map VA 0xf1000000..0xf1100000 to PA 0xd0000000 */ - MMU_INIT(0xf1000000, 0xd0000000, 1, L1_TYPE_S|L1_SHARED|L1_S_B|L1_S_AP(AP_KRW)) -#endif /* CPU_MV_PJ4B */ #endif /* SMP */ .word 0 /* end of table */ #endif diff --git a/sys/arm/arm/mp_machdep.c b/sys/arm/arm/mp_machdep.c index cebbd72..ff6b665 100644 --- a/sys/arm/arm/mp_machdep.c +++ b/sys/arm/arm/mp_machdep.c @@ -52,6 +52,10 @@ __FBSDID("$FreeBSD$"); #ifdef VFP #include <machine/vfp.h> #endif +#ifdef CPU_MV_PJ4B +#include <arm/mv/mvwin.h> +#include <dev/fdt/fdt_common.h> +#endif #include "opt_smp.h" @@ -131,8 +135,8 @@ cpu_mp_start(void) #if defined(CPU_MV_PJ4B) /* Add ARMADAXP registers required for snoop filter initialization */ - ((int *)(temp_pagetable_va))[0xf1000000 >> L1_S_SHIFT] = - L1_TYPE_S|L1_SHARED|L1_S_B|L1_S_AP(AP_KRW)|0xd0000000; + ((int *)(temp_pagetable_va))[MV_BASE >> L1_S_SHIFT] = + L1_TYPE_S|L1_SHARED|L1_S_B|L1_S_AP(AP_KRW)|fdt_immr_pa; #endif temp_pagetable = (void*)(vtophys(temp_pagetable_va)); diff --git a/sys/arm/conf/ARMADAXP b/sys/arm/conf/ARMADAXP index 50ed7ed..2b49459 100644 --- a/sys/arm/conf/ARMADAXP +++ b/sys/arm/conf/ARMADAXP @@ -76,8 +76,7 @@ device pass device da # SATA -device ata -#device mvs +device mvs # Serial ports device uart diff --git a/sys/arm/include/armreg.h b/sys/arm/include/armreg.h index d47f743..35d2e9f 100644 --- a/sys/arm/include/armreg.h +++ b/sys/arm/include/armreg.h @@ -172,14 +172,10 @@ #define CPU_ID_MV88FR571_41 0x41159260 /* Marvell Feroceon 88FR571-VD Core (actual ID from CPU reg) */ #endif -#define CPU_ID_MV88SV581X_V6 0x560F5810 /* Marvell Sheeva 88SV581x v6 Core */ #define CPU_ID_MV88SV581X_V7 0x561F5810 /* Marvell Sheeva 88SV581x v7 Core */ -#define CPU_ID_MV88SV584X_V6 0x561F5840 /* Marvell Sheeva 88SV584x v6 Core */ #define CPU_ID_MV88SV584X_V7 0x562F5840 /* Marvell Sheeva 88SV584x v7 Core */ /* Marvell's CPUIDs with ARM ID in implementor field */ -#define CPU_ID_ARM_88SV581X_V6 0x410fb760 /* Marvell Sheeva 88SV581x v6 Core */ #define CPU_ID_ARM_88SV581X_V7 0x413FC080 /* Marvell Sheeva 88SV581x v7 Core */ -#define CPU_ID_ARM_88SV584X_V6 0x410FB020 /* Marvell Sheeva 88SV584x v6 Core */ #define CPU_ID_FA526 0x66015260 #define CPU_ID_FA626TE 0x66056260 diff --git a/sys/arm/include/cpufunc.h b/sys/arm/include/cpufunc.h index 07c8258..d3e9ebe 100644 --- a/sys/arm/include/cpufunc.h +++ b/sys/arm/include/cpufunc.h @@ -188,7 +188,7 @@ extern u_int cputype; #else void tlb_broadcast(int); -#ifdef CPU_CORTEXA +#if defined(CPU_CORTEXA) || defined(CPU_MV_PJ4B) #define TLB_BROADCAST /* No need to explicitely send an IPI */ #else #define TLB_BROADCAST tlb_broadcast(7) @@ -482,14 +482,6 @@ void arm11_drain_writebuf (void); void pj4b_setttb (u_int); -void pj4b_icache_sync_range (vm_offset_t, vm_size_t); - -void pj4b_dcache_wbinv_range (vm_offset_t, vm_size_t); -void pj4b_dcache_inv_range (vm_offset_t, vm_size_t); -void pj4b_dcache_wb_range (vm_offset_t, vm_size_t); - -void pj4b_idcache_wbinv_range (vm_offset_t, vm_size_t); - void pj4b_drain_readbuf (void); void pj4b_flush_brnchtgt_all (void); void pj4b_flush_brnchtgt_va (u_int); @@ -523,7 +515,6 @@ void armv7_drain_writebuf (void); void armv7_sev (void); u_int armv7_auxctrl (u_int, u_int); void pj4bv7_setup (char *string); -void pj4bv6_setup (char *string); void pj4b_config (void); int get_core_id (void); diff --git a/sys/arm/mv/armadaxp/std.armadaxp b/sys/arm/mv/armadaxp/std.armadaxp index bf2a5f6..d731ad3 100644 --- a/sys/arm/mv/armadaxp/std.armadaxp +++ b/sys/arm/mv/armadaxp/std.armadaxp @@ -1,16 +1,16 @@ # $FreeBSD$ -# kernel gets loaded at 0x00f00000 by the loader, but runs at virtual address -# 0xc0f00000. RAM starts at 0. We put the pagetable at a reasonable place +# kernel gets loaded at 0x00200000 by the loader, but runs at virtual address +# 0xc0200000. RAM starts at 0. We put the pagetable at a reasonable place # in memory, but may need to bounce it higher if there's a problem with this. # We could paper over this by loading the kernel at 0xc0000000 virtual, but # that leads to other complications, so we'll just reclaim the lower region of # ram after we're loaded. Put the page tables for startup at 1MB. -makeoptions KERNPHYSADDR=0x00f00000 -makeoptions KERNVIRTADDR=0xc0f00000 +makeoptions KERNPHYSADDR=0x00200000 +makeoptions KERNVIRTADDR=0xc0200000 -options KERNPHYSADDR=0x00f00000 -options KERNVIRTADDR=0xc0f00000 +options KERNPHYSADDR=0x00200000 +options KERNVIRTADDR=0xc0200000 options PHYSADDR=0x00000000 options STARTUP_PAGETABLE_ADDR=0x00100000 diff --git a/sys/arm/mv/common.c b/sys/arm/mv/common.c index d4bee64..366fcf1 100644 --- a/sys/arm/mv/common.c +++ b/sys/arm/mv/common.c @@ -2078,9 +2078,79 @@ fdt_fixup_busfreq(phandle_t root) OF_setprop(sb, "bus-frequency", (void *)&freq, sizeof(freq)); } +static void +fdt_fixup_ranges(phandle_t root) +{ + phandle_t node; + pcell_t par_addr_cells, addr_cells, size_cells; + pcell_t ranges[3], reg[2], *rangesptr; + int len, tuple_size, tuples_count; + uint32_t base; + + /* Fix-up SoC ranges according to real fdt_immr_pa */ + if ((node = fdt_find_compatible(root, "simple-bus", 1)) != 0) { + if (fdt_addrsize_cells(node, &addr_cells, &size_cells) == 0 && + (par_addr_cells = fdt_parent_addr_cells(node) <= 2)) { + tuple_size = sizeof(pcell_t) * (par_addr_cells + + addr_cells + size_cells); + len = OF_getprop(node, "ranges", ranges, + sizeof(ranges)); + tuples_count = len / tuple_size; + /* Unexpected settings are not supported */ + if (tuples_count != 1) + goto fixup_failed; + + rangesptr = &ranges[0]; + rangesptr += par_addr_cells; + base = fdt_data_get((void *)rangesptr, addr_cells); + *rangesptr = cpu_to_fdt32(fdt_immr_pa); + if (OF_setprop(node, "ranges", (void *)&ranges[0], + sizeof(ranges)) < 0) + goto fixup_failed; + } + } + + /* Fix-up PCIe reg according to real PCIe registers' PA */ + if ((node = fdt_find_compatible(root, "mrvl,pcie", 1)) != 0) { + if (fdt_addrsize_cells(OF_parent(node), &par_addr_cells, + &size_cells) == 0) { + tuple_size = sizeof(pcell_t) * (par_addr_cells + + size_cells); + len = OF_getprop(node, "reg", reg, sizeof(reg)); + tuples_count = len / tuple_size; + /* Unexpected settings are not supported */ + if (tuples_count != 1) + goto fixup_failed; + + base = fdt_data_get((void *)®[0], par_addr_cells); + base &= ~0xFF000000; + base |= fdt_immr_pa; + reg[0] = cpu_to_fdt32(base); + if (OF_setprop(node, "reg", (void *)®[0], + sizeof(reg)) < 0) + goto fixup_failed; + } + } + /* Fix-up succeeded. May return and continue */ + return; + +fixup_failed: + while (1) { + /* + * In case of any error while fixing ranges just hang. + * 1. No message can be displayed yet since console + * is not initialized. + * 2. Going further will cause failure on bus_space_map() + * relying on the wrong ranges or data abort when + * accessing PCIe registers. + */ + } +} + struct fdt_fixup_entry fdt_fixup_table[] = { { "mrvl,DB-88F6281", &fdt_fixup_busfreq }, { "mrvl,DB-78460", &fdt_fixup_busfreq }, + { "mrvl,DB-78460", &fdt_fixup_ranges }, { NULL, NULL } }; diff --git a/sys/arm/mv/mv_machdep.c b/sys/arm/mv/mv_machdep.c index d31a512..9758cfb 100644 --- a/sys/arm/mv/mv_machdep.c +++ b/sys/arm/mv/mv_machdep.c @@ -329,6 +329,19 @@ initarm_devmap_init(void) i = 0; arm_devmap_register_table(&fdt_devmap[0]); +#ifdef SOC_MV_ARMADAXP + vm_paddr_t cur_immr_pa; + + /* + * Acquire SoC registers' base passed by u-boot and fill devmap + * accordingly. DTB is going to be modified basing on this data + * later. + */ + __asm __volatile("mrc p15, 4, %0, c15, c0, 0" : "=r" (cur_immr_pa)); + cur_immr_pa = (cur_immr_pa << 13) & 0xff000000; + if (cur_immr_pa != 0) + fdt_immr_pa = cur_immr_pa; +#endif /* * IMMR range. */ diff --git a/sys/arm/mv/mv_sata.c b/sys/arm/mv/mv_sata.c index 28c641f..87b3823 100644 --- a/sys/arm/mv/mv_sata.c +++ b/sys/arm/mv/mv_sata.c @@ -200,6 +200,7 @@ sata_probe(device_t dev) case MV_DEV_88F6282: case MV_DEV_MV78100: case MV_DEV_MV78100_Z0: + case MV_DEV_MV78460: sc->sc_version = 2; sc->sc_edma_qlen = 32; break; |
