diff options
Diffstat (limited to 'sys/arm/xilinx/zy7_reg.h')
| -rw-r--r-- | sys/arm/xilinx/zy7_reg.h | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/sys/arm/xilinx/zy7_reg.h b/sys/arm/xilinx/zy7_reg.h index c1aac94..2f55ffe 100644 --- a/sys/arm/xilinx/zy7_reg.h +++ b/sys/arm/xilinx/zy7_reg.h @@ -44,16 +44,13 @@ #define ZYNQ7_PLGP1_SIZE 0x40000000 /* I/O Peripheral registers. */ -#define ZYNQ7_PSIO_VBASE 0xE0000000 #define ZYNQ7_PSIO_HWBASE 0xE0000000 #define ZYNQ7_PSIO_SIZE 0x00300000 /* UART0 and UART1 */ -#define ZYNQ7_UART0_VBASE (ZYNQ7_PSIO_VBASE) #define ZYNQ7_UART0_HWBASE (ZYNQ7_PSIO_HWBASE) #define ZYNQ7_UART0_SIZE 0x1000 -#define ZYNQ7_UART1_VBASE (ZYNQ7_PSIO_VBASE+0x1000) #define ZYNQ7_UART1_HWBASE (ZYNQ7_PSIO_HWBASE+0x1000) #define ZYNQ7_UART1_SIZE 0x1000 @@ -63,15 +60,12 @@ #define ZYNQ7_SMC_SIZE 0x05000000 /* SLCR, PS system, and CPU private registers combined in this region. */ -#define ZYNQ7_PSCTL_VBASE 0xF8000000 #define ZYNQ7_PSCTL_HWBASE 0xF8000000 #define ZYNQ7_PSCTL_SIZE 0x01000000 -#define ZYNQ7_SLCR_VBASE (ZYNQ7_PSCTL_VBASE) #define ZYNQ7_SLCR_HWBASE (ZYNQ7_PSCTL_HWBASE) #define ZYNQ7_SLCR_SIZE 0x1000 -#define ZYNQ7_DEVCFG_VBASE (ZYNQ7_PSCTL_VBASE+0x7000) #define ZYNQ7_DEVCFG_HWBASE (ZYNQ7_PSCTL_HWBASE+0x7000) #define ZYNQ7_DEVCFG_SIZE 0x1000 |
