diff options
Diffstat (limited to 'sys/arm/freescale/imx/imx6_ccm.c')
| -rw-r--r-- | sys/arm/freescale/imx/imx6_ccm.c | 37 |
1 files changed, 37 insertions, 0 deletions
diff --git a/sys/arm/freescale/imx/imx6_ccm.c b/sys/arm/freescale/imx/imx6_ccm.c index cc86082..0439a5f 100644 --- a/sys/arm/freescale/imx/imx6_ccm.c +++ b/sys/arm/freescale/imx/imx6_ccm.c @@ -348,6 +348,43 @@ imx_ccm_ahb_hz(void) return (132000000); } +void +imx_ccm_ipu_enable(int ipu) +{ + struct ccm_softc *sc; + uint32_t reg; + + sc = ccm_sc; + reg = RD4(sc, CCM_CCGR3); + if (ipu == 1) + reg |= CCGR3_IPU1_IPU | CCGR3_IPU1_DI0; + else + reg |= CCGR3_IPU2_IPU | CCGR3_IPU2_DI0; + WR4(sc, CCM_CCGR3, reg); +} + +void +imx_ccm_hdmi_enable(void) +{ + struct ccm_softc *sc; + uint32_t reg; + + sc = ccm_sc; + reg = RD4(sc, CCM_CCGR2); + reg |= CCGR2_HDMI_TX | CCGR2_HDMI_TX_ISFR; + WR4(sc, CCM_CCGR2, reg); + + /* Set HDMI clock to 280MHz */ + reg = RD4(sc, CCM_CHSCCDR); + reg &= ~(CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK | + CHSCCDR_IPU1_DI0_PODF_MASK | CHSCCDR_IPU1_DI0_CLK_SEL_MASK); + reg |= (CHSCCDR_PODF_DIVIDE_BY_3 << CHSCCDR_IPU1_DI0_PODF_SHIFT); + reg |= (CHSCCDR_IPU_PRE_CLK_540M_PFD << CHSCCDR_IPU1_DI0_PRE_CLK_SEL_SHIFT); + WR4(sc, CCM_CHSCCDR, reg); + reg |= (CHSCCDR_CLK_SEL_LDB_DI0 << CHSCCDR_IPU1_DI0_CLK_SEL_SHIFT); + WR4(sc, CCM_CHSCCDR, reg); +} + uint32_t imx_ccm_get_cacrr(void) { |
