diff options
Diffstat (limited to 'sys/arm/at91')
35 files changed, 1495 insertions, 913 deletions
diff --git a/sys/arm/at91/at91.c b/sys/arm/at91/at91.c index da3aa72..deb3c38 100644 --- a/sys/arm/at91/at91.c +++ b/sys/arm/at91/at91.c @@ -242,15 +242,29 @@ at91_identify(driver_t *drv, device_t parent) BUS_ADD_CHILD(parent, 0, "atmelarm", 0); } +static void +at91_cpu_add_builtin_children(device_t dev, const struct cpu_devs *walker) +{ + int i; + + for (i = 1; walker->name; i++, walker++) { + at91_add_child(dev, i, walker->name, walker->unit, + walker->mem_base, walker->mem_len, walker->irq0, + walker->irq1, walker->irq2); + } +} + static int at91_attach(device_t dev) { struct at91_softc *sc = device_get_softc(dev); const struct pmap_devmap *pdevmap; + int i; at91_softc = sc; sc->sc_st = &at91_bs_tag; sc->sc_sh = AT91_BASE; + sc->sc_aic_sh = AT91_BASE + AT91_SYS_BASE; sc->dev = dev; sc->sc_irq_rman.rm_type = RMAN_ARRAY; @@ -269,13 +283,34 @@ at91_attach(device_t dev) panic("at91_attach: failed to set up memory rman"); } - /* - * Our device list will be added automatically by the cpu device - * e.g. at91rm9200.c when it is identified. To ensure that the - * CPU and PMC are attached first any other "identified" devices - * call BUS_ADD_CHILD(9) with an "order" of at least 2. + * Setup the interrupt table. + */ + if (soc_info.soc_data == NULL || soc_info.soc_data->soc_irq_prio == NULL) + panic("Interrupt priority table missing\n"); + for (i = 0; i < 32; i++) { + bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_SVR + + i * 4, i); + /* Priority. */ + bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_SMR + i * 4, + soc_info.soc_data->soc_irq_prio[i]); + if (i < 8) + bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_EOICR, + 1); + } + + bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_SPU, 32); + /* No debug. */ + bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_DCR, 0); + /* Disable and clear all interrupts. */ + bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_IDCR, 0xffffffff); + bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_ICCR, 0xffffffff); + + /* + * Add this device's children... */ + at91_cpu_add_builtin_children(dev, soc_info.soc_data->soc_children); + soc_info.soc_data->soc_clock_init(); bus_generic_probe(dev); bus_generic_attach(dev); @@ -362,7 +397,6 @@ at91_setup_intr(device_t dev, device_t child, struct resource *ires, int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg, void **cookiep) { - struct at91_softc *sc = device_get_softc(dev); int error; if (rman_get_start(ires) == AT91_IRQ_SYSTEM && filt == NULL) @@ -372,8 +406,6 @@ at91_setup_intr(device_t dev, device_t child, if (error) return (error); - bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_IECR, - 1 << rman_get_start(ires)); return (0); } diff --git a/sys/arm/at91/at91_machdep.c b/sys/arm/at91/at91_machdep.c index 0bb79bd..2dc95e3 100644 --- a/sys/arm/at91/at91_machdep.c +++ b/sys/arm/at91/at91_machdep.c @@ -94,6 +94,7 @@ __FBSDID("$FreeBSD$"); #include <arm/at91/at91_usartreg.h> #include <arm/at91/at91rm92reg.h> #include <arm/at91/at91sam9g20reg.h> +#include <arm/at91/at91sam9g45reg.h> /* Page table for mapping proc0 zero page */ #define KERNEL_PT_SYS 0 @@ -201,6 +202,17 @@ const struct pmap_devmap at91_devmap[] = { VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, + /* + * The next should be good for the 9G45. + */ + { + /* Internal Memory 1MB */ + AT91SAM9G45_OHCI_BASE, + AT91SAM9G45_OHCI_PA_BASE, + 0x00100000, + VM_PROT_READ|VM_PROT_WRITE, + PTE_NOCACHE, + }, { 0, 0, 0, 0, 0, } }; @@ -213,7 +225,7 @@ extern int memsize[]; long at91_ramsize(void) { - uint32_t cr, mr, *SDRAMC; + uint32_t cr, mdr, mr, *SDRAMC; int banks, rows, cols, bw; #ifdef LINUX_BOOT_ABI /* @@ -231,6 +243,24 @@ at91_ramsize(void) rows = ((cr & AT91RM92_SDRAMC_CR_NR_MASK) >> 2) + 11; cols = (cr & AT91RM92_SDRAMC_CR_NC_MASK) + 8; bw = (mr & AT91RM92_SDRAMC_MR_DBW_16) ? 1 : 2; + } else if (at91_cpu_is(AT91_T_SAM9G45)) { + SDRAMC = (uint32_t *)(AT91_BASE + AT91SAM9G45_DDRSDRC0_BASE); + cr = SDRAMC[AT91SAM9G45_DDRSDRC_CR / 4]; + mdr = SDRAMC[AT91SAM9G45_DDRSDRC_MDR / 4]; + banks = 0; + rows = ((cr & AT91SAM9G45_DDRSDRC_CR_NR_MASK) >> 2) + 11; + cols = (cr & AT91SAM9G45_DDRSDRC_CR_NC_MASK) + 8; + bw = (mdr & AT91SAM9G45_DDRSDRC_MDR_DBW_16) ? 1 : 2; + + /* Fix the calculation for DDR memory */ + mdr &= AT91SAM9G45_DDRSDRC_MDR_MASK; + if (mdr & AT91SAM9G45_DDRSDRC_MDR_LPDDR1 || + mdr & AT91SAM9G45_DDRSDRC_MDR_DDR2) { + /* The cols value is 1 higher for DDR */ + cols += 1; + /* DDR has 4 internal banks. */ + banks = 2; + } } else { /* * This should be good for the 9260, 9261, 9G20, 9G35 and 9X25 @@ -402,6 +432,7 @@ at91_try_id(uint32_t dbgu_base) * try to get the matching CPU support. */ soc_info.soc_data = at91_match_soc(soc_info.type, soc_info.subtype); + soc_info.dbgu_base = AT91_BASE + dbgu_base; return (1); } diff --git a/sys/arm/at91/at91_pio_rm9200.h b/sys/arm/at91/at91_pio_rm9200.h deleted file mode 100644 index 809262f..0000000 --- a/sys/arm/at91/at91_pio_rm9200.h +++ /dev/null @@ -1,208 +0,0 @@ -/* $FreeBSD$ */ - -#ifndef ARM_AT91_AT91_PIO_RM9200_H -#define ARM_AT91_AT91_PIO_RM9200_H - -#include <arm/at91/at91_pioreg.h> -/* - * These defines come from an atmel file that says specifically that it - * has no copyright. - */ - -//***************************************************************************** -// PIO DEFINITIONS FOR AT91RM9200 -//***************************************************************************** -#define AT91C_PA0_MISO (AT91C_PIO_PA0) // SPI Master In Slave -#define AT91C_PA0_PCK3 (AT91C_PIO_PA0) // PMC Programmable Clock Output 3 -#define AT91C_PA1_MOSI (AT91C_PIO_PA1) // SPI Master Out Slave -#define AT91C_PA1_PCK0 (AT91C_PIO_PA1) // PMC Programmable Clock Output 0 -#define AT91C_PA10_ETX1 (AT91C_PIO_PA10) // Ethernet MAC Transmit Data 1 -#define AT91C_PA10_MCDB1 (AT91C_PIO_PA10) // Multimedia Card B Data 1 -#define AT91C_PA11_ECRS_ECRSDV (AT91C_PIO_PA11) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid -#define AT91C_PA11_MCDB2 (AT91C_PIO_PA11) // Multimedia Card B Data 2 -#define AT91C_PA12_ERX0 (AT91C_PIO_PA12) // Ethernet MAC Receive Data 0 -#define AT91C_PA12_MCDB3 (AT91C_PIO_PA12) // Multimedia Card B Data 3 -#define AT91C_PA13_ERX1 (AT91C_PIO_PA13) // Ethernet MAC Receive Data 1 -#define AT91C_PA13_TCLK0 (AT91C_PIO_PA13) // Timer Counter 0 external clock input -#define AT91C_PA14_ERXER (AT91C_PIO_PA14) // Ethernet MAC Receive Error -#define AT91C_PA14_TCLK1 (AT91C_PIO_PA14) // Timer Counter 1 external clock input -#define AT91C_PA15_EMDC (AT91C_PIO_PA15) // Ethernet MAC Management Data Clock -#define AT91C_PA15_TCLK2 (AT91C_PIO_PA15) // Timer Counter 2 external clock input -#define AT91C_PA16_EMDIO (AT91C_PIO_PA16) // Ethernet MAC Management Data Input/Output -#define AT91C_PA16_IRQ6 (AT91C_PIO_PA16) // AIC Interrupt input 6 -#define AT91C_PA17_TXD0 (AT91C_PIO_PA17) // USART 0 Transmit Data -#define AT91C_PA17_TIOA0 (AT91C_PIO_PA17) // Timer Counter 0 Multipurpose Timer I/O Pin A -#define AT91C_PA18_RXD0 (AT91C_PIO_PA18) // USART 0 Receive Data -#define AT91C_PA18_TIOB0 (AT91C_PIO_PA18) // Timer Counter 0 Multipurpose Timer I/O Pin B -#define AT91C_PA19_SCK0 (AT91C_PIO_PA19) // USART 0 Serial Clock -#define AT91C_PA19_TIOA1 (AT91C_PIO_PA19) // Timer Counter 1 Multipurpose Timer I/O Pin A -#define AT91C_PA2_SPCK (AT91C_PIO_PA2) // SPI Serial Clock -#define AT91C_PA2_IRQ4 (AT91C_PIO_PA2) // AIC Interrupt Input 4 -#define AT91C_PA20_CTS0 (AT91C_PIO_PA20) // USART 0 Clear To Send -#define AT91C_PA20_TIOB1 (AT91C_PIO_PA20) // Timer Counter 1 Multipurpose Timer I/O Pin B -#define AT91C_PA21_RTS0 (AT91C_PIO_PA21) // Usart 0 Ready To Send -#define AT91C_PA21_TIOA2 (AT91C_PIO_PA21) // Timer Counter 2 Multipurpose Timer I/O Pin A -#define AT91C_PA22_RXD2 (AT91C_PIO_PA22) // USART 2 Receive Data -#define AT91C_PA22_TIOB2 (AT91C_PIO_PA22) // Timer Counter 2 Multipurpose Timer I/O Pin B -#define AT91C_PA23_TXD2 (AT91C_PIO_PA23) // USART 2 Transmit Data -#define AT91C_PA23_IRQ3 (AT91C_PIO_PA23) // Interrupt input 3 -#define AT91C_PA24_SCK2 (AT91C_PIO_PA24) // USART2 Serial Clock -#define AT91C_PA24_PCK1 (AT91C_PIO_PA24) // PMC Programmable Clock Output 1 -#define AT91C_PA25_TWD (AT91C_PIO_PA25) // TWI Two-wire Serial Data -#define AT91C_PA25_IRQ2 (AT91C_PIO_PA25) // Interrupt input 2 -#define AT91C_PA26_TWCK (AT91C_PIO_PA26) // TWI Two-wire Serial Clock -#define AT91C_PA26_IRQ1 (AT91C_PIO_PA26) // Interrupt input 1 -#define AT91C_PA27_MCCK (AT91C_PIO_PA27) // Multimedia Card Clock -#define AT91C_PA27_TCLK3 (AT91C_PIO_PA27) // Timer Counter 3 External Clock Input -#define AT91C_PA28_MCCDA (AT91C_PIO_PA28) // Multimedia Card A Command -#define AT91C_PA28_TCLK4 (AT91C_PIO_PA28) // Timer Counter 4 external Clock Input -#define AT91C_PA29_MCDA0 (AT91C_PIO_PA29) // Multimedia Card A Data 0 -#define AT91C_PA29_TCLK5 (AT91C_PIO_PA29) // Timer Counter 5 external clock input -#define AT91C_PA3_NPCS0 (AT91C_PIO_PA3) // SPI Peripheral Chip Select 0 -#define AT91C_PA3_IRQ5 (AT91C_PIO_PA3) // AIC Interrupt Input 5 -#define AT91C_PA30_DRXD (AT91C_PIO_PA30) // DBGU Debug Receive Data -#define AT91C_PA30_CTS2 (AT91C_PIO_PA30) // Usart 2 Clear To Send -#define AT91C_PA31_DTXD (AT91C_PIO_PA31) // DBGU Debug Transmit Data -#define AT91C_PA31_RTS2 (AT91C_PIO_PA31) // USART 2 Ready To Send -#define AT91C_PA4_NPCS1 (AT91C_PIO_PA4) // SPI Peripheral Chip Select 1 -#define AT91C_PA4_PCK1 (AT91C_PIO_PA4) // PMC Programmable Clock Output 1 -#define AT91C_PA5_NPCS2 (AT91C_PIO_PA5) // SPI Peripheral Chip Select 2 -#define AT91C_PA5_TXD3 (AT91C_PIO_PA5) // USART 3 Transmit Data -#define AT91C_PA6_NPCS3 (AT91C_PIO_PA6) // SPI Peripheral Chip Select 3 -#define AT91C_PA6_RXD3 (AT91C_PIO_PA6) // USART 3 Receive Data -#define AT91C_PA7_ETXCK_EREFCK (AT91C_PIO_PA7) // Ethernet MAC Transmit Clock/Reference Clock -#define AT91C_PA7_PCK2 (AT91C_PIO_PA7) // PMC Programmable Clock 2 -#define AT91C_PA8_ETXEN (AT91C_PIO_PA8) // Ethernet MAC Transmit Enable -#define AT91C_PA8_MCCDB (AT91C_PIO_PA8) // Multimedia Card B Command -#define AT91C_PA9_ETX0 (AT91C_PIO_PA9) // Ethernet MAC Transmit Data 0 -#define AT91C_PA9_MCDB0 (AT91C_PIO_PA9) // Multimedia Card B Data 0 -#define AT91C_PB0_TF0 (AT91C_PIO_PB0) // SSC Transmit Frame Sync 0 -#define AT91C_PB0_TIOB3 (AT91C_PIO_PB0) // Timer Counter 3 Multipurpose Timer I/O Pin B -#define AT91C_PB1_TK0 (AT91C_PIO_PB1) // SSC Transmit Clock 0 -#define AT91C_PB1_CTS3 (AT91C_PIO_PB1) // USART 3 Clear To Send -#define AT91C_PB10_RK1 (AT91C_PIO_PB10) // SSC Receive Clock 1 -#define AT91C_PB10_TIOA5 (AT91C_PIO_PB10) // Timer Counter 5 Multipurpose Timer I/O Pin A -#define AT91C_PB11_RF1 (AT91C_PIO_PB11) // SSC Receive Frame Sync 1 -#define AT91C_PB11_TIOB5 (AT91C_PIO_PB11) // Timer Counter 5 Multipurpose Timer I/O Pin B -#define AT91C_PB12_TF2 (AT91C_PIO_PB12) // SSC Transmit Frame Sync 2 -#define AT91C_PB12_ETX2 (AT91C_PIO_PB12) // Ethernet MAC Transmit Data 2 -#define AT91C_PB13_TK2 (AT91C_PIO_PB13) // SSC Transmit Clock 2 -#define AT91C_PB13_ETX3 (AT91C_PIO_PB13) // Ethernet MAC Transmit Data 3 -#define AT91C_PB14_TD2 (AT91C_PIO_PB14) // SSC Transmit Data 2 -#define AT91C_PB14_ETXER (AT91C_PIO_PB14) // Ethernet MAC Transmikt Coding Error -#define AT91C_PB15_RD2 (AT91C_PIO_PB15) // SSC Receive Data 2 -#define AT91C_PB15_ERX2 (AT91C_PIO_PB15) // Ethernet MAC Receive Data 2 -#define AT91C_PB16_RK2 (AT91C_PIO_PB16) // SSC Receive Clock 2 -#define AT91C_PB16_ERX3 (AT91C_PIO_PB16) // Ethernet MAC Receive Data 3 -#define AT91C_PB17_RF2 (AT91C_PIO_PB17) // SSC Receive Frame Sync 2 -#define AT91C_PB17_ERXDV (AT91C_PIO_PB17) // Ethernet MAC Receive Data Valid -#define AT91C_PB18_RI1 (AT91C_PIO_PB18) // USART 1 Ring Indicator -#define AT91C_PB18_ECOL (AT91C_PIO_PB18) // Ethernet MAC Collision Detected -#define AT91C_PB19_DTR1 (AT91C_PIO_PB19) // USART 1 Data Terminal ready -#define AT91C_PB19_ERXCK (AT91C_PIO_PB19) // Ethernet MAC Receive Clock -#define AT91C_PB2_TD0 (AT91C_PIO_PB2) // SSC Transmit data -#define AT91C_PB2_SCK3 (AT91C_PIO_PB2) // USART 3 Serial Clock -#define AT91C_PB20_TXD1 (AT91C_PIO_PB20) // USART 1 Transmit Data -#define AT91C_PB21_RXD1 (AT91C_PIO_PB21) // USART 1 Receive Data -#define AT91C_PB22_SCK1 (AT91C_PIO_PB22) // USART1 Serial Clock -#define AT91C_PB23_DCD1 (AT91C_PIO_PB23) // USART 1 Data Carrier Detect -#define AT91C_PB24_CTS1 (AT91C_PIO_PB24) // USART 1 Clear To Send -#define AT91C_PB25_DSR1 (AT91C_PIO_PB25) // USART 1 Data Set ready -#define AT91C_PB25_EF100 (AT91C_PIO_PB25) // Ethernet MAC Force 100 Mbits/sec -#define AT91C_PB26_RTS1 (AT91C_PIO_PB26) // Usart 0 Ready To Send -#define AT91C_PB27_PCK0 (AT91C_PIO_PB27) // PMC Programmable Clock Output 0 -#define AT91C_PB28_FIQ (AT91C_PIO_PB28) // AIC Fast Interrupt Input -#define AT91C_PB29_IRQ0 (AT91C_PIO_PB29) // Interrupt input 0 -#define AT91C_PB3_RD0 (AT91C_PIO_PB3) // SSC Receive Data -#define AT91C_PB3_MCDA1 (AT91C_PIO_PB3) // Multimedia Card A Data 1 -#define AT91C_PB4_RK0 (AT91C_PIO_PB4) // SSC Receive Clock -#define AT91C_PB4_MCDA2 (AT91C_PIO_PB4) // Multimedia Card A Data 2 -#define AT91C_PB5_RF0 (AT91C_PIO_PB5) // SSC Receive Frame Sync 0 -#define AT91C_PB5_MCDA3 (AT91C_PIO_PB5) // Multimedia Card A Data 3 -#define AT91C_PB6_TF1 (AT91C_PIO_PB6) // SSC Transmit Frame Sync 1 -#define AT91C_PB6_TIOA3 (AT91C_PIO_PB6) // Timer Counter 4 Multipurpose Timer I/O Pin A -#define AT91C_PB7_TK1 (AT91C_PIO_PB7) // SSC Transmit Clock 1 -#define AT91C_PB7_TIOB3 (AT91C_PIO_PB7) // Timer Counter 3 Multipurpose Timer I/O Pin B -#define AT91C_PB8_TD1 (AT91C_PIO_PB8) // SSC Transmit Data 1 -#define AT91C_PB8_TIOA4 (AT91C_PIO_PB8) // Timer Counter 4 Multipurpose Timer I/O Pin A -#define AT91C_PB9_RD1 (AT91C_PIO_PB9) // SSC Receive Data 1 -#define AT91C_PB9_TIOB4 (AT91C_PIO_PB9) // Timer Counter 4 Multipurpose Timer I/O Pin B -#define AT91C_PC0_BFCK (AT91C_PIO_PC0) // Burst Flash Clock -#define AT91C_PC1_BFRDY_SMOE (AT91C_PIO_PC1) // Burst Flash Ready -#define AT91C_PC10_NCS4_CFCS (AT91C_PIO_PC10) // Compact Flash Chip Select -#define AT91C_PC11_NCS5_CFCE1 (AT91C_PIO_PC11) // Chip Select 5 / Compact Flash Chip Enable 1 -#define AT91C_PC12_NCS6_CFCE2 (AT91C_PIO_PC12) // Chip Select 6 / Compact Flash Chip Enable 2 -#define AT91C_PC13_NCS7 (AT91C_PIO_PC13) // Chip Select 7 -#define AT91C_PC16_D16 (AT91C_PIO_PC16) // Data Bus [16] -#define AT91C_PC17_D17 (AT91C_PIO_PC17) // Data Bus [17] -#define AT91C_PC18_D18 (AT91C_PIO_PC18) // Data Bus [18] -#define AT91C_PC19_D19 (AT91C_PIO_PC19) // Data Bus [19] -#define AT91C_PC2_BFAVD (AT91C_PIO_PC2)u // Burst Flash Address Valid -#define AT91C_PC20_D20 (AT91C_PIO_PC20) // Data Bus [20] -#define AT91C_PC21_D21 (AT91C_PIO_PC21) // Data Bus [21] -#define AT91C_PC22_D22 (AT91C_PIO_PC22) // Data Bus [22] -#define AT91C_PC23_D23 (AT91C_PIO_PC23) // Data Bus [23] -#define AT91C_PC24_D24 (AT91C_PIO_PC24) // Data Bus [24] -#define AT91C_PC25_D25 (AT91C_PIO_PC25) // Data Bus [25] -#define AT91C_PC26_D26 (AT91C_PIO_PC26) // Data Bus [26] -#define AT91C_PC27_D27 (AT91C_PIO_PC27) // Data Bus [27] -#define AT91C_PC28_D28 (AT91C_PIO_PC28) // Data Bus [28] -#define AT91C_PC29_D29 (AT91C_PIO_PC29) // Data Bus [29] -#define AT91C_PC3_BFBAA_SMWE (AT91C_PIO_PC3) // Burst Flash Address Advance / SmartMedia Write Enable -#define AT91C_PC30_D30 (AT91C_PIO_PC30) // Data Bus [30] -#define AT91C_PC31_D31 (AT91C_PIO_PC31) // Data Bus [31] -#define AT91C_PC4_BFOE (AT91C_PIO_PC4) // Burst Flash Output Enable -#define AT91C_PC5_BFWE (AT91C_PIO_PC5) // Burst Flash Write Enable -#define AT91C_PC6_NWAIT (AT91C_PIO_PC6) // NWAIT -#define AT91C_PC7_A23 (AT91C_PIO_PC7) // Address Bus[23] -#define AT91C_PC8_A24 (AT91C_PIO_PC8) // Address Bus[24] -#define AT91C_PC9_A25_CFRNW (AT91C_PIO_PC9) // Address Bus[25] / Compact Flash Read Not Write -#define AT91C_PD0_ETX0 (AT91C_PIO_PD0) // Ethernet MAC Transmit Data 0 -#define AT91C_PD1_ETX1 (AT91C_PIO_PD1) // Ethernet MAC Transmit Data 1 -#define AT91C_PD10_PCK3 (AT91C_PIO_PD10) // PMC Programmable Clock Output 3 -#define AT91C_PD10_TPS1 (AT91C_PIO_PD10) // ETM ARM9 pipeline status 1 -#define AT91C_PD11_ (AT91C_PIO_PD11) // -#define AT91C_PD11_TPS2 (AT91C_PIO_PD11) // ETM ARM9 pipeline status 2 -#define AT91C_PD12_ (AT91C_PIO_PD12) // -#define AT91C_PD12_TPK0 (AT91C_PIO_PD12) // ETM Trace Packet 0 -#define AT91C_PD13_ (AT91C_PIO_PD13) // -#define AT91C_PD13_TPK1 (AT91C_PIO_PD13) // ETM Trace Packet 1 -#define AT91C_PD14_ (AT91C_PIO_PD14) // -#define AT91C_PD14_TPK2 (AT91C_PIO_PD14) // ETM Trace Packet 2 -#define AT91C_PD15_TD0 (AT91C_PIO_PD15) // SSC Transmit data -#define AT91C_PD15_TPK3 (AT91C_PIO_PD15) // ETM Trace Packet 3 -#define AT91C_PD16_TD1 (AT91C_PIO_PD16) // SSC Transmit Data 1 -#define AT91C_PD16_TPK4 (AT91C_PIO_PD16) // ETM Trace Packet 4 -#define AT91C_PD17_TD2 (AT91C_PIO_PD17) // SSC Transmit Data 2 -#define AT91C_PD17_TPK5 (AT91C_PIO_PD17) // ETM Trace Packet 5 -#define AT91C_PD18_NPCS1 (AT91C_PIO_PD18) // SPI Peripheral Chip Select 1 -#define AT91C_PD18_TPK6 (AT91C_PIO_PD18) // ETM Trace Packet 6 -#define AT91C_PD19_NPCS2 (AT91C_PIO_PD19) // SPI Peripheral Chip Select 2 -#define AT91C_PD19_TPK7 (AT91C_PIO_PD19) // ETM Trace Packet 7 -#define AT91C_PD2_ETX2 (AT91C_PIO_PD2) // Ethernet MAC Transmit Data 2 -#define AT91C_PD20_NPCS3 (AT91C_PIO_PD20) // SPI Peripheral Chip Select 3 -#define AT91C_PD20_TPK8 (AT91C_PIO_PD20) // ETM Trace Packet 8 -#define AT91C_PD21_RTS0 (AT91C_PIO_PD21) // Usart 0 Ready To Send -#define AT91C_PD21_TPK9 (AT91C_PIO_PD21) // ETM Trace Packet 9 -#define AT91C_PD22_RTS1 (AT91C_PIO_PD22) // Usart 0 Ready To Send -#define AT91C_PD22_TPK10 (AT91C_PIO_PD22) // ETM Trace Packet 10 -#define AT91C_PD23_RTS2 (AT91C_PIO_PD23) // USART 2 Ready To Send -#define AT91C_PD23_TPK11 (AT91C_PIO_PD23) // ETM Trace Packet 11 -#define AT91C_PD24_RTS3 (AT91C_PIO_PD24) // USART 3 Ready To Send -#define AT91C_PD24_TPK12 (AT91C_PIO_PD24) // ETM Trace Packet 12 -#define AT91C_PD25_DTR1 (AT91C_PIO_PD25) // USART 1 Data Terminal ready -#define AT91C_PD25_TPK13 (AT91C_PIO_PD25) // ETM Trace Packet 13 -#define AT91C_PD26_TPK14 (AT91C_PIO_PD26) // ETM Trace Packet 14 -#define AT91C_PD27_TPK15 (AT91C_PIO_PD27) // ETM Trace Packet 15 -#define AT91C_PD3_ETX3 (AT91C_PIO_PD3) // Ethernet MAC Transmit Data 3 -#define AT91C_PD4_ETXEN (AT91C_PIO_PD4) // Ethernet MAC Transmit Enable -#define AT91C_PD5_ETXER (AT91C_PIO_PD5) // Ethernet MAC Transmikt Coding Error -#define AT91C_PD6_DTXD (AT91C_PIO_PD6) // DBGU Debug Transmit Data -#define AT91C_PD7_PCK0 (AT91C_PIO_PD7) // PMC Programmable Clock Output 0 -#define AT91C_PD7_TSYNC (AT91C_PIO_PD7) // ETM Synchronization signal -#define AT91C_PD8_PCK1 (AT91C_PIO_PD8) // PMC Programmable Clock Output 1 -#define AT91C_PD8_TCLK (AT91C_PIO_PD8) // ETM Trace Clock signal -#define AT91C_PD9_PCK2 (AT91C_PIO_PD9) // PMC Programmable Clock 2 -#define AT91C_PD9_TPS0 (AT91C_PIO_PD9) // ETM ARM9 pipeline status 0 - -#endif /* ARM_AT91_AT91_PIO_RM9200_H */ diff --git a/sys/arm/at91/at91_pio_sam9g45.h b/sys/arm/at91/at91_pio_sam9g45.h new file mode 100644 index 0000000..6045536 --- /dev/null +++ b/sys/arm/at91/at91_pio_sam9g45.h @@ -0,0 +1,272 @@ +/*- + * ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support - ROUSSET - + * ---------------------------------------------------------------------------- + * Copyright (c) 2009, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + * + * From AT91LIB version 1.9 boards/at91sam9g45-ek/at91sam9g45/AT91SAM9G45.h + */ + +/* $FreeBSD$ */ + +#ifndef ARM_AT91_AT91_PIO_SAM9G45_H +#define ARM_AT91_AT91_PIO_SAM9G45_H + +#include <arm/at91/at91_pioreg.h> + +// ***************************************************************************** +// PIO DEFINITIONS FOR AT91SAM9G45 +// ***************************************************************************** +#define AT91C_PA0_MCI0_CK (AT91C_PIO_PA0) // +#define AT91C_PA0_TCLK3 (AT91C_PIO_PA0) // +#define AT91C_PA1_MCI0_CDA (AT91C_PIO_PA1) // +#define AT91C_PA1_TIOA3 (AT91C_PIO_PA1) // +#define AT91C_PA10_ETX0 (AT91C_PIO_PA10) // Ethernet MAC Transmit Data 0 +#define AT91C_PA11_ETX1 (AT91C_PIO_PA11) // Ethernet MAC Transmit Data 1 +#define AT91C_PA12_ERX0 (AT91C_PIO_PA12) // Ethernet MAC Receive Data 0 +#define AT91C_PA13_ERX1 (AT91C_PIO_PA13) // Ethernet MAC Receive Data 1 +#define AT91C_PA14_ETXEN (AT91C_PIO_PA14) // Ethernet MAC Transmit Enable +#define AT91C_PA15_ERXDV (AT91C_PIO_PA15) // Ethernet MAC Receive Data Valid +#define AT91C_PA16_ERXER (AT91C_PIO_PA16) // Ethernet MAC Receive Error +#define AT91C_PA17_ETXCK_EREFCK (AT91C_PIO_PA17) // Ethernet MAC Transmit Clock/Reference Clock +#define AT91C_PA18_EMDC (AT91C_PIO_PA18) // Ethernet MAC Management Data Clock +#define AT91C_PA19_EMDIO (AT91C_PIO_PA19) // Ethernet MAC Management Data Input/Output +#define AT91C_PA2_MCI0_DA0 (AT91C_PIO_PA2) // +#define AT91C_PA2_TIOB3 (AT91C_PIO_PA2) // +#define AT91C_PA20_TWD0 (AT91C_PIO_PA20) // TWI Two-wire Serial Data +#define AT91C_PA21_TWCK0 (AT91C_PIO_PA21) // TWI Two-wire Serial Clock +#define AT91C_PA22_MCI1_CDA (AT91C_PIO_PA22) // +#define AT91C_PA22_SCK3 (AT91C_PIO_PA22) // +#define AT91C_PA23_MCI1_DA0 (AT91C_PIO_PA23) // +#define AT91C_PA23_RTS3 (AT91C_PIO_PA23) // +#define AT91C_PA24_MCI1_DA1 (AT91C_PIO_PA24) // +#define AT91C_PA24_CTS3 (AT91C_PIO_PA24) // +#define AT91C_PA25_MCI1_DA2 (AT91C_PIO_PA25) // +#define AT91C_PA25_PWM3 (AT91C_PIO_PA25) // +#define AT91C_PA26_MCI1_DA3 (AT91C_PIO_PA26) // +#define AT91C_PA26_TIOB2 (AT91C_PIO_PA26) // +#define AT91C_PA27_MCI1_DA4 (AT91C_PIO_PA27) // +#define AT91C_PA27_ETXER (AT91C_PIO_PA27) // Ethernet MAC Transmikt Coding Error +#define AT91C_PA28_MCI1_DA5 (AT91C_PIO_PA28) // +#define AT91C_PA28_ERXCK (AT91C_PIO_PA28) // Ethernet MAC Receive Clock +#define AT91C_PA29_MCI1_DA6 (AT91C_PIO_PA29) // +#define AT91C_PA29_ECRS (AT91C_PIO_PA29) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid +#define AT91C_PA3_MCI0_DA1 (AT91C_PIO_PA3) // +#define AT91C_PA3_TCLK4 (AT91C_PIO_PA3) // +#define AT91C_PA30_MCI1_DA7 (AT91C_PIO_PA30) // +#define AT91C_PA30_ECOL (AT91C_PIO_PA30) // Ethernet MAC Collision Detected +#define AT91C_PA31_MCI1_CK (AT91C_PIO_PA31) // +#define AT91C_PA31_PCK0 (AT91C_PIO_PA31) // +#define AT91C_PA4_MCI0_DA2 (AT91C_PIO_PA4) // +#define AT91C_PA4_TIOA4 (AT91C_PIO_PA4) // +#define AT91C_PA5_MCI0_DA3 (AT91C_PIO_PA5) // +#define AT91C_PA5_TIOB4 (AT91C_PIO_PA5) // +#define AT91C_PA6_MCI0_DA4 (AT91C_PIO_PA6) // +#define AT91C_PA6_ETX2 (AT91C_PIO_PA6) // Ethernet MAC Transmit Data 2 +#define AT91C_PA7_MCI0_DA5 (AT91C_PIO_PA7) // +#define AT91C_PA7_ETX3 (AT91C_PIO_PA7) // Ethernet MAC Transmit Data 3 +#define AT91C_PA8_MCI0_DA6 (AT91C_PIO_PA8) // +#define AT91C_PA8_ERX2 (AT91C_PIO_PA8) // Ethernet MAC Receive Data 2 +#define AT91C_PA9_MCI0_DA7 (AT91C_PIO_PA9) // +#define AT91C_PA9_ERX3 (AT91C_PIO_PA9) // Ethernet MAC Receive Data 3 +#define AT91C_PB0_SPI0_MISO (AT91C_PIO_PB0) // SPI 0 Master In Slave +#define AT91C_PB1_SPI0_MOSI (AT91C_PIO_PB1) // SPI 0 Master Out Slave +#define AT91C_PB10_TWD1 (AT91C_PIO_PB10) // +#define AT91C_PB10_ISI_D10 (AT91C_PIO_PB10) // +#define AT91C_PB11_TWCK1 (AT91C_PIO_PB11) // +#define AT91C_PB11_ISI_D11 (AT91C_PIO_PB11) // +#define AT91C_PB12_DRXD (AT91C_PIO_PB12) // +#define AT91C_PB13_DTXD (AT91C_PIO_PB13) // +#define AT91C_PB14_SPI1_MISO (AT91C_PIO_PB14) // +#define AT91C_PB15_SPI1_MOSI (AT91C_PIO_PB15) // +#define AT91C_PB15_CTS0 (AT91C_PIO_PB15) // +#define AT91C_PB16_SPI1_SPCK (AT91C_PIO_PB16) // +#define AT91C_PB16_SCK0 (AT91C_PIO_PB16) // +#define AT91C_PB17_SPI1_NPCS0 (AT91C_PIO_PB17) // +#define AT91C_PB17_RTS0 (AT91C_PIO_PB17) // +#define AT91C_PB18_RXD0 (AT91C_PIO_PB18) // +#define AT91C_PB18_SPI0_NPCS1 (AT91C_PIO_PB18) // +#define AT91C_PB19_TXD0 (AT91C_PIO_PB19) // +#define AT91C_PB19_SPI0_NPCS2 (AT91C_PIO_PB19) // +#define AT91C_PB2_SPI0_SPCK (AT91C_PIO_PB2) // SPI 0 Serial Clock +#define AT91C_PB20_ISI_D0 (AT91C_PIO_PB20) // +#define AT91C_PB21_ISI_D1 (AT91C_PIO_PB21) // +#define AT91C_PB22_ISI_D2 (AT91C_PIO_PB22) // +#define AT91C_PB23_ISI_D3 (AT91C_PIO_PB23) // +#define AT91C_PB24_ISI_D4 (AT91C_PIO_PB24) // +#define AT91C_PB25_ISI_D5 (AT91C_PIO_PB25) // +#define AT91C_PB26_ISI_D6 (AT91C_PIO_PB26) // +#define AT91C_PB27_ISI_D7 (AT91C_PIO_PB27) // +#define AT91C_PB28_ISI_PCK (AT91C_PIO_PB28) // +#define AT91C_PB29_ISI_VSYNC (AT91C_PIO_PB29) // +#define AT91C_PB3_SPI0_NPCS0 (AT91C_PIO_PB3) // SPI 0 Peripheral Chip Select 0 +#define AT91C_PB30_ISI_HSYNC (AT91C_PIO_PB30) // +#define AT91C_PB31_ (AT91C_PIO_PB31) // +#define AT91C_PB31_PCK1 (AT91C_PIO_PB31) // +#define AT91C_PB4_TXD1 (AT91C_PIO_PB4) // USART 1 Transmit Data +#define AT91C_PB5_RXD1 (AT91C_PIO_PB5) // USART 1 Receive Data +#define AT91C_PB6_TXD2 (AT91C_PIO_PB6) // USART 2 Transmit Data +#define AT91C_PB7_RXD2 (AT91C_PIO_PB7) // USART 2 Receive Data +#define AT91C_PB8_TXD3 (AT91C_PIO_PB8) // USART 3 Transmit Data +#define AT91C_PB8_ISI_D8 (AT91C_PIO_PB8) // +#define AT91C_PB9_RXD3 (AT91C_PIO_PB9) // USART 3 Receive Data +#define AT91C_PB9_ISI_D9 (AT91C_PIO_PB9) // +#define AT91C_PC0_DQM2 (AT91C_PIO_PC0) // DQM2 +#define AT91C_PC1_DQM3 (AT91C_PIO_PC1) // DQM3 +#define AT91C_PC10_NCS4_CFCS0 (AT91C_PIO_PC10) // +#define AT91C_PC10_TCLK2 (AT91C_PIO_PC10) // +#define AT91C_PC11_NCS5_CFCS1 (AT91C_PIO_PC11) // +#define AT91C_PC11_CTS2 (AT91C_PIO_PC11) // +#define AT91C_PC12_A25_CFRNW (AT91C_PIO_PC12) // +#define AT91C_PC13_NCS2 (AT91C_PIO_PC13) // +#define AT91C_PC14_NCS3_NANDCS (AT91C_PIO_PC14) // +#define AT91C_PC15_NWAIT (AT91C_PIO_PC15) // +#define AT91C_PC16_D16 (AT91C_PIO_PC16) // +#define AT91C_PC17_D17 (AT91C_PIO_PC17) // +#define AT91C_PC18_D18 (AT91C_PIO_PC18) // +#define AT91C_PC19_D19 (AT91C_PIO_PC19) // +#define AT91C_PC2_A19 (AT91C_PIO_PC2) // +#define AT91C_PC20_D20 (AT91C_PIO_PC20) // +#define AT91C_PC21_D21 (AT91C_PIO_PC21) // +#define AT91C_PC22_D22 (AT91C_PIO_PC22) // +#define AT91C_PC23_D23 (AT91C_PIO_PC23) // +#define AT91C_PC24_D24 (AT91C_PIO_PC24) // +#define AT91C_PC25_D25 (AT91C_PIO_PC25) // +#define AT91C_PC26_D26 (AT91C_PIO_PC26) // +#define AT91C_PC27_D27 (AT91C_PIO_PC27) // +#define AT91C_PC28_D28 (AT91C_PIO_PC28) // +#define AT91C_PC29_D29 (AT91C_PIO_PC29) // +#define AT91C_PC3_A20 (AT91C_PIO_PC3) // +#define AT91C_PC30_D30 (AT91C_PIO_PC30) // +#define AT91C_PC31_D31 (AT91C_PIO_PC31) // +#define AT91C_PC4_A21_NANDALE (AT91C_PIO_PC4) // +#define AT91C_PC5_A22_NANDCLE (AT91C_PIO_PC5) // +#define AT91C_PC6_A23 (AT91C_PIO_PC6) // +#define AT91C_PC7_A24 (AT91C_PIO_PC7) // +#define AT91C_PC8_CFCE1 (AT91C_PIO_PC8) // +#define AT91C_PC9_CFCE2 (AT91C_PIO_PC9) // +#define AT91C_PC9_RTS2 (AT91C_PIO_PC9) // +#define AT91C_PD0_TK0 (AT91C_PIO_PD0) // +#define AT91C_PD0_PWM3 (AT91C_PIO_PD0) // +#define AT91C_PD1_TF0 (AT91C_PIO_PD1) // +#define AT91C_PD10_TD1 (AT91C_PIO_PD10) // +#define AT91C_PD11_RD1 (AT91C_PIO_PD11) // +#define AT91C_PD12_TK1 (AT91C_PIO_PD12) // +#define AT91C_PD12_PCK0 (AT91C_PIO_PD12) // +#define AT91C_PD13_RK1 (AT91C_PIO_PD13) // +#define AT91C_PD14_TF1 (AT91C_PIO_PD14) // +#define AT91C_PD15_RF1 (AT91C_PIO_PD15) // +#define AT91C_PD16_RTS1 (AT91C_PIO_PD16) // +#define AT91C_PD17_CTS1 (AT91C_PIO_PD17) // +#define AT91C_PD18_SPI1_NPCS2 (AT91C_PIO_PD18) // +#define AT91C_PD18_IRQ (AT91C_PIO_PD18) // +#define AT91C_PD19_SPI1_NPCS3 (AT91C_PIO_PD19) // +#define AT91C_PD19_FIQ (AT91C_PIO_PD19) // +#define AT91C_PD2_TD0 (AT91C_PIO_PD2) // +#define AT91C_PD20_TIOA0 (AT91C_PIO_PD20) // +#define AT91C_PD21_TIOA1 (AT91C_PIO_PD21) // +#define AT91C_PD22_TIOA2 (AT91C_PIO_PD22) // +#define AT91C_PD23_TCLK0 (AT91C_PIO_PD23) // +#define AT91C_PD24_SPI0_NPCS1 (AT91C_PIO_PD24) // +#define AT91C_PD24_PWM0 (AT91C_PIO_PD24) // +#define AT91C_PD25_SPI0_NPCS2 (AT91C_PIO_PD25) // +#define AT91C_PD25_PWM1 (AT91C_PIO_PD25) // +#define AT91C_PD26_PCK0 (AT91C_PIO_PD26) // +#define AT91C_PD26_PWM2 (AT91C_PIO_PD26) // +#define AT91C_PD27_PCK1 (AT91C_PIO_PD27) // +#define AT91C_PD27_SPI0_NPCS3 (AT91C_PIO_PD27) // +#define AT91C_PD28_TSADTRG (AT91C_PIO_PD28) // +#define AT91C_PD28_SPI1_NPCS1 (AT91C_PIO_PD28) // +#define AT91C_PD29_TCLK1 (AT91C_PIO_PD29) // +#define AT91C_PD29_SCK1 (AT91C_PIO_PD29) // +#define AT91C_PD3_RD0 (AT91C_PIO_PD3) // +#define AT91C_PD30_TIOB0 (AT91C_PIO_PD30) // +#define AT91C_PD30_SCK2 (AT91C_PIO_PD30) // +#define AT91C_PD31_TIOB1 (AT91C_PIO_PD31) // +#define AT91C_PD31_PWM1 (AT91C_PIO_PD31) // +#define AT91C_PD4_RK0 (AT91C_PIO_PD4) // +#define AT91C_PD5_RF0 (AT91C_PIO_PD5) // +#define AT91C_PD6_AC97RX (AT91C_PIO_PD6) // +#define AT91C_PD7_AC97TX (AT91C_PIO_PD7) // +#define AT91C_PD7_TIOA5 (AT91C_PIO_PD7) // +#define AT91C_PD8_AC97FS (AT91C_PIO_PD8) // +#define AT91C_PD8_TIOB5 (AT91C_PIO_PD8) // +#define AT91C_PD9_AC97CK (AT91C_PIO_PD9) // +#define AT91C_PD9_TCLK5 (AT91C_PIO_PD9) // +#define AT91C_PE0_LCDPWR (AT91C_PIO_PE0) // +#define AT91C_PE0_PCK0 (AT91C_PIO_PE0) // +#define AT91C_PE1_LCDMOD (AT91C_PIO_PE1) // +#define AT91C_PE10_LCDD3 (AT91C_PIO_PE10) // +#define AT91C_PE10_LCDD5 (AT91C_PIO_PE10) // +#define AT91C_PE11_LCDD4 (AT91C_PIO_PE11) // +#define AT91C_PE11_LCDD6 (AT91C_PIO_PE11) // +#define AT91C_PE12_LCDD5 (AT91C_PIO_PE12) // +#define AT91C_PE12_LCDD7 (AT91C_PIO_PE12) // +#define AT91C_PE13_LCDD6 (AT91C_PIO_PE13) // +#define AT91C_PE13_LCDD10 (AT91C_PIO_PE13) // +#define AT91C_PE14_LCDD7 (AT91C_PIO_PE14) // +#define AT91C_PE14_LCDD11 (AT91C_PIO_PE14) // +#define AT91C_PE15_LCDD8 (AT91C_PIO_PE15) // +#define AT91C_PE15_LCDD12 (AT91C_PIO_PE15) // +#define AT91C_PE16_LCDD9 (AT91C_PIO_PE16) // +#define AT91C_PE16_LCDD13 (AT91C_PIO_PE16) // +#define AT91C_PE17_LCDD10 (AT91C_PIO_PE17) // +#define AT91C_PE17_LCDD14 (AT91C_PIO_PE17) // +#define AT91C_PE18_LCDD11 (AT91C_PIO_PE18) // +#define AT91C_PE18_LCDD15 (AT91C_PIO_PE18) // +#define AT91C_PE19_LCDD12 (AT91C_PIO_PE19) // +#define AT91C_PE19_LCDD18 (AT91C_PIO_PE19) // +#define AT91C_PE2_LCDCC (AT91C_PIO_PE2) // +#define AT91C_PE20_LCDD13 (AT91C_PIO_PE20) // +#define AT91C_PE20_LCDD19 (AT91C_PIO_PE20) // +#define AT91C_PE21_LCDD14 (AT91C_PIO_PE21) // +#define AT91C_PE21_LCDD20 (AT91C_PIO_PE21) // +#define AT91C_PE22_LCDD15 (AT91C_PIO_PE22) // +#define AT91C_PE22_LCDD21 (AT91C_PIO_PE22) // +#define AT91C_PE23_LCDD16 (AT91C_PIO_PE23) // +#define AT91C_PE23_LCDD22 (AT91C_PIO_PE23) // +#define AT91C_PE24_LCDD17 (AT91C_PIO_PE24) // +#define AT91C_PE24_LCDD23 (AT91C_PIO_PE24) // +#define AT91C_PE25_LCDD18 (AT91C_PIO_PE25) // +#define AT91C_PE26_LCDD19 (AT91C_PIO_PE26) // +#define AT91C_PE27_LCDD20 (AT91C_PIO_PE27) // +#define AT91C_PE28_LCDD21 (AT91C_PIO_PE28) // +#define AT91C_PE29_LCDD22 (AT91C_PIO_PE29) // +#define AT91C_PE3_LCDVSYNC (AT91C_PIO_PE3) // +#define AT91C_PE30_LCDD23 (AT91C_PIO_PE30) // +#define AT91C_PE31_PWM2 (AT91C_PIO_PE31) // +#define AT91C_PE31_PCK1 (AT91C_PIO_PE31) // +#define AT91C_PE4_LCDHSYNC (AT91C_PIO_PE4) // +#define AT91C_PE5_LCDDOTCK (AT91C_PIO_PE5) // +#define AT91C_PE6_LCDDEN (AT91C_PIO_PE6) // +#define AT91C_PE7_LCDD0 (AT91C_PIO_PE7) // +#define AT91C_PE7_LCDD2 (AT91C_PIO_PE7) // +#define AT91C_PE8_LCDD1 (AT91C_PIO_PE8) // +#define AT91C_PE8_LCDD3 (AT91C_PIO_PE8) // +#define AT91C_PE9_LCDD2 (AT91C_PIO_PE9) // +#define AT91C_PE9_LCDD4 (AT91C_PIO_PE9) // + +#endif /* ARM_AT91_AT91_PIO_SAM9G45_H */ diff --git a/sys/arm/at91/at91_pmc.c b/sys/arm/at91/at91_pmc.c index 799a87b..8711d17 100644 --- a/sys/arm/at91/at91_pmc.c +++ b/sys/arm/at91/at91_pmc.c @@ -65,6 +65,7 @@ MALLOC_DEFINE(M_PMC, "at91_pmc_clocks", "AT91 PMC Clock descriptors"); #define AT91_PMC_BASE 0xffffc00 static void at91_pmc_set_pllb_mode(struct at91_pmc_clock *, int); +static void at91_pmc_set_upll_mode(struct at91_pmc_clock *, int); static void at91_pmc_set_sys_mode(struct at91_pmc_clock *, int); static void at91_pmc_set_periph_mode(struct at91_pmc_clock *, int); static void at91_pmc_clock_alias(const char *name, const char *alias); @@ -110,6 +111,18 @@ static struct at91_pmc_clock pllb = { .set_mode = &at91_pmc_set_pllb_mode, }; +/* Used by USB on at91sam9g45 */ +static struct at91_pmc_clock upll = { + .name = "upll", // UTMI PLL, used for USB functions on 9G45 + .parent = &main_ck, + .refcnt = 0, + .id = 0, + .primary = 1, + .pll = 1, + .pmc_mask = (1 << 6), + .set_mode = &at91_pmc_set_upll_mode, +}; + static struct at91_pmc_clock udpck = { .name = "udpck", .parent = &pllb, @@ -143,6 +156,7 @@ static struct at91_pmc_clock *clock_list[16+32] = { &main_ck, &plla, &pllb, + &upll, &udpck, &uhpck, &mck, @@ -199,6 +213,26 @@ at91_pmc_set_pllb_mode(struct at91_pmc_clock *clk, int on) } static void +at91_pmc_set_upll_mode(struct at91_pmc_clock *clk, int on) +{ + struct at91_pmc_softc *sc = pmc_softc; + uint32_t value; + + if (on) { + on = PMC_IER_LOCKU; + value = CKGR_UCKR_UPLLEN | CKGR_UCKR_BIASEN; + } else + value = 0; + + WR4(sc, CKGR_UCKR, RD4(sc, CKGR_UCKR) | value); + while ((RD4(sc, PMC_SR) & PMC_IER_LOCKU) != on) + continue; + + WR4(sc, PMC_USB, PMC_USB_USBDIV(9) | PMC_USB_USBS); + WR4(sc, PMC_SCER, PMC_SCER_UHP_SAM9); +} + +static void at91_pmc_set_sys_mode(struct at91_pmc_clock *clk, int on) { struct at91_pmc_softc *sc = pmc_softc; @@ -466,6 +500,12 @@ at91_pmc_init_clock(void) uhpck.pmc_mask = PMC_SCER_UHP_SAM9; udpck.pmc_mask = PMC_SCER_UDP_SAM9; } + /* There is no pllb on AT91SAM9G45 */ + if (at91_cpu_is(AT91_T_SAM9G45)) { + uhpck.parent = &upll; + uhpck.pmc_mask = PMC_SCER_UHP_SAM9; + } + mckr = RD4(sc, PMC_MCKR); main_ck.hz = main_clock; @@ -506,8 +546,14 @@ at91_pmc_init_clock(void) mdiv = (mckr & PMC_MCKR_MDIV_MASK) >> 8; if (at91_is_sam9() || at91_is_sam9xe()) { + /* + * On AT91SAM9G45 when mdiv == 3 we need to divide + * MCK by 3 but not, for example, on 9g20. + */ + if (!at91_cpu_is(AT91_T_SAM9G45) || mdiv <= 2) + mdiv *= 2; if (mdiv > 0) - mck.hz /= mdiv * 2; + mck.hz /= mdiv; } else mck.hz /= (1 + mdiv); diff --git a/sys/arm/at91/at91_pmcreg.h b/sys/arm/at91/at91_pmcreg.h index eaf08c6..ce6165d 100644 --- a/sys/arm/at91/at91_pmcreg.h +++ b/sys/arm/at91/at91_pmcreg.h @@ -36,14 +36,14 @@ #define PMC_PCER 0x10 /* Peripheral Clock Enable Register */ #define PMC_PCDR 0x14 /* Peripheral Clock Disable Register */ #define PMC_PCSR 0x18 /* Peripheral Clock Status Register */ - /* 0x1c reserved */ +#define CKGR_UCKR 0x1c /* UTMI Clock Configuration Register */ #define CKGR_MOR 0x20 /* Main Oscillator Register */ #define CKGR_MCFR 0x24 /* Main Clock Frequency Register */ #define CKGR_PLLAR 0x28 /* PLL A Register */ #define CKGR_PLLBR 0x2c /* PLL B Register */ #define PMC_MCKR 0x30 /* Master Clock Register */ /* 0x34 reserved */ - /* 0x38 reserved */ +#define PMC_USB 0x38 /* USB Clock Register */ /* 0x3c reserved */ #define PMC_PCK0 0x40 /* Programmable Clock 0 Register */ #define PMC_PCK1 0x44 /* Programmable Clock 1 Register */ @@ -77,6 +77,10 @@ /* PMC Peripheral Clock Status Register */ /* Each bit here is 1 << peripheral number to enable/disable/status */ +/* PMC UTMI Clock Configuration Register */ +#define CKGR_UCKR_BIASEN (1UL << 24) +#define CKGR_UCKR_UPLLEN (1UL << 16) + /* PMC Clock Generator Main Oscillator Register */ #define CKGR_MOR_MOSCEN (1UL << 0) /* MOSCEN: Main Oscillator Enable */ #define CKGR_MOR_OSCBYPASS (1UL << 1) /* Oscillator Bypass */ @@ -93,6 +97,10 @@ #define PMC_MCKR_MDIV_MASK (3 << 8) #define PMC_MCKR_PRES_MASK (7 << 2) +/* PMC USB Clock Register */ +#define PMC_USB_USBDIV(n) (((n) & 0x0F) << 8) +#define PMC_USB_USBS (1 << 0) + /* PMC Interrupt Enable Register */ /* PMC Interrupt Disable Register */ /* PMC Status Register */ @@ -101,6 +109,7 @@ #define PMC_IER_LOCKA (1UL << 1) /* PLL A Locked */ #define PMC_IER_LOCKB (1UL << 2) /* PLL B Locked */ #define PMC_IER_MCKRDY (1UL << 3) /* Master Clock Status */ +#define PMC_IER_LOCKU (1UL << 6) /* UPLL Locked */ #define PMC_IER_PCK0RDY (1UL << 8) /* Programmable Clock 0 Ready */ #define PMC_IER_PCK1RDY (1UL << 9) /* Programmable Clock 1 Ready */ #define PMC_IER_PCK2RDY (1UL << 10) /* Programmable Clock 2 Ready */ diff --git a/sys/arm/at91/at91_spi.c b/sys/arm/at91/at91_spi.c index a81e0be..f01e984 100644 --- a/sys/arm/at91/at91_spi.c +++ b/sys/arm/at91/at91_spi.c @@ -42,6 +42,7 @@ __FBSDID("$FreeBSD$"); #include <machine/bus.h> +#include <arm/at91/at91var.h> #include <arm/at91/at91_spireg.h> #include <arm/at91/at91_pdcreg.h> @@ -144,6 +145,7 @@ at91_spi_attach(device_t dev) * memory and APB bandwidth. * Also, currently we lack a way for lettting both the board and the * slave devices take their maximum supported SPI clocks into account. + * Also, we hard-wire SPI mode to 3. */ csr = SPI_CSR_CPOL | (4 << 16) | (0xff << 8); WR4(sc, SPI_CSR0, csr); @@ -285,7 +287,10 @@ at91_spi_transfer(device_t dev, device_t child, struct spi_command *cmd) */ WR4(sc, PDC_PTCR, PDC_PTCR_TXTDIS | PDC_PTCR_RXTDIS); -#ifdef SPI_CHIPSEL_SUPPORT + /* + * PSCDEC = 0 has a range of 0..3 for chip select. We + * don't support PSCDEC = 1 which has a range of 0..15. + */ if (cmd->cs < 0 || cmd->cs > 3) { device_printf(dev, "Invalid chip select %d requested by %s\n", cmd->cs, @@ -293,18 +298,23 @@ at91_spi_transfer(device_t dev, device_t child, struct spi_command *cmd) err = EINVAL; goto out; } + #ifdef SPI_CHIP_SELECT_HIGH_SUPPORT + /* + * The AT91RM9200 couldn't do CS high for CS 0. Other chips can, but we + * don't support that yet, or other spi modes. + */ if (at91_is_rm92() && cmd->cs == 0 && (cmd->flags & SPI_CHIP_SELECT_HIGH) != 0) { device_printf(dev, - "Invalid chip select high requested by %s\n", + "Invalid chip select high requested by %s for cs 0.\n", device_get_nameunit(child)); err = EINVAL; goto out; } #endif - WR4(sc, SPI_MR, (RD4(sc, SPI_MR) & ~0x000f0000) | CS_TO_MR(cmd->cs)); -#endif + err = (RD4(sc, SPI_MR) & ~0x000f0000) | CS_TO_MR(cmd->cs); + WR4(sc, SPI_MR, err); /* * Set up the TX side of the transfer. diff --git a/sys/arm/at91/at91rm9200.c b/sys/arm/at91/at91rm9200.c index 51627f0..a3201e3 100644 --- a/sys/arm/at91/at91rm9200.c +++ b/sys/arm/at91/at91rm9200.c @@ -46,14 +46,6 @@ __FBSDID("$FreeBSD$"); #include <arm/at91/at91_pmcvar.h> #include <arm/at91/at91soc.h> - -struct at91rm92_softc { - device_t dev; - bus_space_tag_t sc_st; - bus_space_handle_t sc_sh; - bus_space_handle_t sc_sys_sh; - bus_space_handle_t sc_aic_sh; -}; /* * Standard priority levels for the system. 0 is lowest and 7 is highest. * These values are the ones Atmel uses for its Linux port, which differ @@ -137,19 +129,6 @@ static const struct cpu_devs at91_devs[] = { 0, 0, 0, 0, 0 } }; -static void -at91_cpu_add_builtin_children(device_t dev) -{ - int i; - const struct cpu_devs *walker; - - for (i = 1, walker = at91_devs; walker->name; i++, walker++) { - at91_add_child(dev, i, walker->name, walker->unit, - walker->mem_base, walker->mem_len, walker->irq0, - walker->irq1, walker->irq2); - } -} - static uint32_t at91_pll_outb(int freq) { @@ -160,71 +139,19 @@ at91_pll_outb(int freq) return (0x8000); } -static void -at91_identify(driver_t *drv, device_t parent) -{ - - if (at91_cpu_is(AT91_T_RM9200)) { - at91_add_child(parent, 0, "at91rm920", 0, 0, 0, -1, 0, 0); - at91_cpu_add_builtin_children(parent); - } -} - -static int -at91_probe(device_t dev) -{ - - device_set_desc(dev, soc_info.name); - return (0); -} - -static int -at91_attach(device_t dev) -{ - struct at91_pmc_clock *clk; - struct at91rm92_softc *sc = device_get_softc(dev); - int i; - - struct at91_softc *at91sc = device_get_softc(device_get_parent(dev)); - - sc->sc_st = at91sc->sc_st; - sc->sc_sh = at91sc->sc_sh; - sc->dev = dev; - - if (bus_space_subregion(sc->sc_st, sc->sc_sh, AT91RM92_SYS_BASE, - AT91RM92_SYS_SIZE, &sc->sc_sys_sh) != 0) - panic("Enable to map system registers"); - - if (bus_space_subregion(sc->sc_st, sc->sc_sh, AT91RM92_AIC_BASE, - AT91RM92_AIC_SIZE, &sc->sc_aic_sh) != 0) - panic("Enable to map system registers"); - - /* XXX Hack to tell atmelarm about the AIC */ - at91sc->sc_aic_sh = sc->sc_aic_sh; - - for (i = 0; i < 32; i++) { - bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_SVR + - i * 4, i); - /* Priority. */ - bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_SMR + i * 4, - at91_irq_prio[i]); - if (i < 8) - bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_EOICR, - 1); - } - - bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_SPU, 32); - /* No debug. */ - bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_DCR, 0); - /* Disable and clear all interrupts. */ - bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_IDCR, 0xffffffff); - bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_ICCR, 0xffffffff); - +#if 0 +/* -- XXX are these needed? */ /* Disable all interrupts for RTC (0xe24 == RTC_IDR) */ bus_space_write_4(sc->sc_st, sc->sc_sys_sh, 0xe24, 0xffffffff); /* Disable all interrupts for the SDRAM controller */ bus_space_write_4(sc->sc_st, sc->sc_sys_sh, 0xfa8, 0xffffffff); +#endif + +static void +at91_clock_init(void) +{ + struct at91_pmc_clock *clk; /* Update USB device port clock info */ clk = at91_pmc_clock_ref("udpck"); @@ -260,30 +187,14 @@ at91_attach(device_t dev) clk->pll_div_mask = RM9200_PLL_B_DIV_MASK; clk->set_outb = at91_pll_outb; at91_pmc_clock_deref(clk); - - return (0); } -static device_method_t at91_methods[] = { - DEVMETHOD(device_probe, at91_probe), - DEVMETHOD(device_attach, at91_attach), - DEVMETHOD(device_identify, at91_identify), - {0, 0}, -}; - -static driver_t at91rm92_driver = { - "at91rm920", - at91_methods, - sizeof(struct at91rm92_softc), -}; - -static devclass_t at91rm92_devclass; - -DRIVER_MODULE(at91rm920, atmelarm, at91rm92_driver, at91rm92_devclass, 0, 0); - static struct at91_soc_data soc_data = { .soc_delay = at91_st_delay, - .soc_reset = at91_st_cpu_reset + .soc_reset = at91_st_cpu_reset, + .soc_clock_init = at91_clock_init, + .soc_irq_prio = at91_irq_prio, + .soc_children = at91_devs, }; AT91_SOC(AT91_T_RM9200, &soc_data); diff --git a/sys/arm/at91/at91rm9200_devices.c b/sys/arm/at91/at91rm9200_devices.c new file mode 100644 index 0000000..9f5efa4 --- /dev/null +++ b/sys/arm/at91/at91rm9200_devices.c @@ -0,0 +1,142 @@ +/*- + * Copyright (c) 2012 M. Warner Losh. All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <sys/cdefs.h> +__FBSDID("$FreeBSD$"); + +#include <sys/param.h> +#include <sys/systm.h> +#include <sys/bus.h> +#include <sys/kernel.h> +#include <sys/malloc.h> +#include <sys/module.h> + +#define _ARM32_BUS_DMA_PRIVATE +#include <machine/bus.h> + +#include <arm/at91/at91var.h> +#include <arm/at91/at91board.h> +#include <arm/at91/at91rm92reg.h> +#include <arm/at91/at91rm9200var.h> +#include <arm/at91/at91_pioreg.h> +#include <arm/at91/at91_piovar.h> + +/* + * The AT91RM9200 uses the same silicon for both the BGA and PQFP + * packages. There's no documented way to detect this at runtime, + * so we require the board code to register what type of SoC is on the + * board in question. The pinouts are not quite compatible, and we + * use this information to cope with the slight differences. + */ +void +at91rm9200_set_subtype(enum at91_soc_subtype st) +{ + + switch (st) { + case AT91_ST_RM9200_BGA: + case AT91_ST_RM9200_PQFP: + soc_info.subtype = st; + break; + default: + panic("Bad SoC subtype %d for at91rm9200_set_subtype.", st); + break; + } +} + +void +at91rm9200_config_uart(unsigned devid, unsigned unit, unsigned pinmask) +{ + + /* + * Since the USART supports RS-485 multidrop mode, it allows the + * TX pins to float. However, for RS-232 operations, we don't want + * these pins to float. Instead, they should be pulled up to avoid + * mismatches. Linux does something similar when it configures the + * TX lines. This implies that we also allow the RX lines to float + * rather than be in the state they are left in by the boot loader. + * Since they are input pins, I think that this is the right thing + * to do. + */ + + /* + * Current boards supported don't need the extras, but they should be + * implemented. But that should wait until the new pin api goes in. + */ + switch (devid) { + case AT91_ID_DBGU: + at91_pio_use_periph_a(AT91RM92_PIOA_BASE, AT91C_PIO_PA30, 0); /* DRXD */ + at91_pio_use_periph_a(AT91RM92_PIOA_BASE, AT91C_PIO_PA31, 1); /* DTXD */ + break; + + case AT91RM9200_ID_USART0: + at91_pio_use_periph_a(AT91RM92_PIOA_BASE, AT91C_PIO_PA17, 1); /* TXD0 */ + at91_pio_use_periph_a(AT91RM92_PIOA_BASE, AT91C_PIO_PA19, 0); /* RXD0 */ + /* CTS PA20 */ + /* RTS -- errata #39 PA21 */ + break; + + case AT91RM9200_ID_USART1: + at91_pio_use_periph_a(AT91RM92_PIOB_BASE, AT91C_PIO_PB20, 1); /* TXD1 */ + at91_pio_use_periph_a(AT91RM92_PIOB_BASE, AT91C_PIO_PB21, 0); /* RXD1 */ + /* RI - PB18 */ + /* DTR - PB19 */ + /* DCD - PB23 */ + /* CTS - PB24 */ + /* DSR - PB25 */ + /* RTS - PB26 */ + break; + + case AT91RM9200_ID_USART2: + at91_pio_use_periph_a(AT91RM92_PIOA_BASE, AT91C_PIO_PA22, 0); /* RXD2 */ + at91_pio_use_periph_a(AT91RM92_PIOA_BASE, AT91C_PIO_PA23, 1); /* TXD2 */ + /* CTS - PA30 B periph */ + /* RTS - PA31 B periph */ + break; + + case AT91RM9200_ID_USART3: + at91_pio_use_periph_b(AT91RM92_PIOA_BASE, AT91C_PIO_PA5, 1); /* TXD3 */ + at91_pio_use_periph_b(AT91RM92_PIOA_BASE, AT91C_PIO_PA6, 0); /* RXD3 */ + /* CTS - PB0 B periph */ + /* RTS - PB1 B periph */ + break; + + default: + break; + } +} + +void +at91rm9200_config_mci(int has_4wire) +{ + /* XXX TODO chip changed GPIO, other slots, etc */ + at91_pio_use_periph_a(AT91RM92_PIOA_BASE, AT91C_PIO_PA27, 0); /* MCCK */ + at91_pio_use_periph_a(AT91RM92_PIOA_BASE, AT91C_PIO_PA28, 1); /* MCCDA */ + at91_pio_use_periph_a(AT91RM92_PIOA_BASE, AT91C_PIO_PA29, 1); /* MCDA0 */ + if (has_4wire) { + at91_pio_use_periph_b(AT91RM92_PIOB_BASE, AT91C_PIO_PB3, 1); /* MCDA1 */ + at91_pio_use_periph_b(AT91RM92_PIOB_BASE, AT91C_PIO_PB4, 1); /* MCDA2 */ + at91_pio_use_periph_b(AT91RM92_PIOB_BASE, AT91C_PIO_PB5, 1); /* MCDA3 */ + } +} diff --git a/sys/arm/at91/at91rm9200var.h b/sys/arm/at91/at91rm9200var.h new file mode 100644 index 0000000..156320e --- /dev/null +++ b/sys/arm/at91/at91rm9200var.h @@ -0,0 +1,58 @@ +/*- + * Copyright (c) 2012 M. Warner Losh. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +/* $FreeBSD$ */ + +#ifndef ARM_AT91_AT91RM9200VAR_H +#define ARM_AT91_AT91RM9200VAR_H + +void at91rm9200_set_subtype(enum at91_soc_subtype st); + +#define AT91RM9200_ID_USART0 1 +#define AT91RM9200_ID_USART1 2 +#define AT91RM9200_ID_USART2 3 +#define AT91RM9200_ID_USART3 4 + +/* + * Serial port convenience routines + */ +/* uart pins that are wired... */ +#define AT91_UART_CTS 0x01 +#define AT91_UART_RTS 0x02 +#define AT91_UART_RI 0x04 +#define AT91_UART_DTR 0x08 +#define AT91_UART_DCD 0x10 +#define AT91_UART_DSR 0x20 + +#define AT91_ID_DBGU 0 + +void at91rm9200_config_uart(unsigned devid, unsigned unit, unsigned pinmask); + +/* + * MCI (sd/mmc card support) + */ +void at91rm9200_config_mci(int has_4wire); + +#endif /* ARM_AT91_AT91RM9200VAR_H */ diff --git a/sys/arm/at91/at91sam9260.c b/sys/arm/at91/at91sam9260.c index 9ea0335..23a5f57 100644 --- a/sys/arm/at91/at91sam9260.c +++ b/sys/arm/at91/at91sam9260.c @@ -47,15 +47,6 @@ __FBSDID("$FreeBSD$"); #include <arm/at91/at91_pmcvar.h> #include <arm/at91/at91_rstreg.h> -struct at91sam9_softc { - device_t dev; - bus_space_tag_t sc_st; - bus_space_handle_t sc_sh; - bus_space_handle_t sc_sys_sh; - bus_space_handle_t sc_aic_sh; - bus_space_handle_t sc_matrix_sh; -}; - /* * Standard priority levels for the system. 0 is lowest and 7 is highest. * These values are the ones Atmel uses for its Linux port @@ -131,19 +122,6 @@ static const struct cpu_devs at91_devs[] = { 0, 0, 0, 0, 0 } }; -static void -at91_cpu_add_builtin_children(device_t dev) -{ - int i; - const struct cpu_devs *walker; - - for (i = 1, walker = at91_devs; walker->name; i++, walker++) { - at91_add_child(dev, i, walker->name, walker->unit, - walker->mem_base, walker->mem_len, walker->irq0, - walker->irq1, walker->irq2); - } -} - static uint32_t at91_pll_outa(int freq) { @@ -162,76 +140,9 @@ at91_pll_outb(int freq) } static void -at91_identify(driver_t *drv, device_t parent) -{ - - if (soc_info.type == AT91_T_SAM9260) { - at91_add_child(parent, 0, "at91sam9260", 0, 0, 0, -1, 0, 0); - at91_cpu_add_builtin_children(parent); - } -} - -static int -at91_probe(device_t dev) -{ - - device_set_desc(dev, soc_info.name); - return (0); -} - -static int -at91_attach(device_t dev) +at91_clock_init(void) { struct at91_pmc_clock *clk; - struct at91sam9_softc *sc = device_get_softc(dev); - int i; - - struct at91_softc *at91sc = device_get_softc(device_get_parent(dev)); - - sc->sc_st = at91sc->sc_st; - sc->sc_sh = at91sc->sc_sh; - sc->dev = dev; - - if (bus_space_subregion(sc->sc_st, sc->sc_sh, AT91SAM9260_SYS_BASE, - AT91SAM9260_SYS_SIZE, &sc->sc_sys_sh) != 0) - panic("Enable to map system registers"); - - if (bus_space_subregion(sc->sc_st, sc->sc_sh, AT91SAM9260_AIC_BASE, - AT91SAM9260_AIC_SIZE, &sc->sc_aic_sh) != 0) - panic("Enable to map system registers"); - - /* XXX Hack to tell atmelarm about the AIC */ - at91sc->sc_aic_sh = sc->sc_aic_sh; - - for (i = 0; i < 32; i++) { - bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_SVR + - i * 4, i); - /* Priority. */ - bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_SMR + i * 4, - at91_irq_prio[i]); - if (i < 8) - bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_EOICR, - 1); - } - - bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_SPU, 32); - /* No debug. */ - bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_DCR, 0); - /* Disable and clear all interrupts. */ - bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_IDCR, 0xffffffff); - bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_ICCR, 0xffffffff); - - if (bus_space_subregion(sc->sc_st, sc->sc_sh, - AT91SAM9260_MATRIX_BASE, AT91SAM9260_MATRIX_SIZE, - &sc->sc_matrix_sh) != 0) - panic("Enable to map matrix registers"); - - /* activate NAND */ - i = bus_space_read_4(sc->sc_st, sc->sc_matrix_sh, - AT91SAM9260_EBICSA); - bus_space_write_4(sc->sc_st, sc->sc_matrix_sh, - AT91SAM9260_EBICSA, - i | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA); /* Update USB device port clock info */ clk = at91_pmc_clock_ref("udpck"); @@ -276,30 +187,14 @@ at91_attach(device_t dev) clk->pll_div_mask = SAM9260_PLL_B_DIV_MASK; clk->set_outb = at91_pll_outb; at91_pmc_clock_deref(clk); - return (0); } -static device_method_t at91sam9260_methods[] = { - DEVMETHOD(device_probe, at91_probe), - DEVMETHOD(device_attach, at91_attach), - DEVMETHOD(device_identify, at91_identify), - DEVMETHOD_END -}; - -static driver_t at91sam9260_driver = { - "at91sam9260", - at91sam9260_methods, - sizeof(struct at91sam9_softc), -}; - -static devclass_t at91sam9260_devclass; - -DRIVER_MODULE(at91sam9260, atmelarm, at91sam9260_driver, at91sam9260_devclass, - NULL, NULL); - static struct at91_soc_data soc_data = { .soc_delay = at91_pit_delay, - .soc_reset = at91_rst_cpu_reset + .soc_reset = at91_rst_cpu_reset, + .soc_clock_init = at91_clock_init, + .soc_irq_prio = at91_irq_prio, + .soc_children = at91_devs, }; AT91_SOC(AT91_T_SAM9260, &soc_data); diff --git a/sys/arm/at91/at91sam9g20.c b/sys/arm/at91/at91sam9g20.c index 4b87ad0..73876b0 100644 --- a/sys/arm/at91/at91sam9g20.c +++ b/sys/arm/at91/at91sam9g20.c @@ -47,15 +47,6 @@ __FBSDID("$FreeBSD$"); #include <arm/at91/at91_pmcvar.h> #include <arm/at91/at91_rstreg.h> -struct at91sam9_softc { - device_t dev; - bus_space_tag_t sc_st; - bus_space_handle_t sc_sh; - bus_space_handle_t sc_sys_sh; - bus_space_handle_t sc_aic_sh; - bus_space_handle_t sc_matrix_sh; -}; - /* * Standard priority levels for the system. 0 is lowest and 7 is highest. * These values are the ones Atmel uses for its Linux port @@ -131,19 +122,6 @@ static const struct cpu_devs at91_devs[] = { 0, 0, 0, 0, 0 } }; -static void -at91_cpu_add_builtin_children(device_t dev) -{ - int i; - const struct cpu_devs *walker; - - for (i = 1, walker = at91_devs; walker->name; i++, walker++) { - at91_add_child(dev, i, walker->name, walker->unit, - walker->mem_base, walker->mem_len, walker->irq0, - walker->irq1, walker->irq2); - } -} - static uint32_t at91_pll_outa(int freq) { @@ -169,81 +147,9 @@ at91_pll_outb(int freq) } static void -at91_identify(driver_t *drv, device_t parent) -{ - - if (at91_cpu_is(AT91_T_SAM9G20)) { - at91_add_child(parent, 0, "at91sam", 9, 0, 0, -1, 0, 0); - at91_cpu_add_builtin_children(parent); - } -} - -static int -at91_probe(device_t dev) -{ - - device_set_desc(dev, soc_info.name); - return (0); -} - -static int -at91_attach(device_t dev) +at91_clock_init(void) { struct at91_pmc_clock *clk; - struct at91sam9_softc *sc = device_get_softc(dev); - int i; - - struct at91_softc *at91sc = device_get_softc(device_get_parent(dev)); - - sc->sc_st = at91sc->sc_st; - sc->sc_sh = at91sc->sc_sh; - sc->dev = dev; - - /* - * XXX These values work for the RM9200, SAM926[01], and SAM9G20 - * will have to fix this when we want to support anything else. XXX - */ - if (bus_space_subregion(sc->sc_st, sc->sc_sh, AT91SAM9G20_SYS_BASE, - AT91SAM9G20_SYS_SIZE, &sc->sc_sys_sh) != 0) - panic("Enable to map system registers"); - - if (bus_space_subregion(sc->sc_st, sc->sc_sh, AT91SAM9G20_AIC_BASE, - AT91SAM9G20_AIC_SIZE, &sc->sc_aic_sh) != 0) - panic("Enable to map system registers"); - - /* XXX Hack to tell atmelarm about the AIC */ - at91sc->sc_aic_sh = sc->sc_aic_sh; - - for (i = 0; i < 32; i++) { - bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_SVR + - i * 4, i); - /* Priority. */ - bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_SMR + i * 4, - at91_irq_prio[i]); - if (i < 8) - bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_EOICR, - 1); - } - - bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_SPU, 32); - /* No debug. */ - bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_DCR, 0); - /* Disable and clear all interrupts. */ - bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_IDCR, 0xffffffff); - bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_ICCR, 0xffffffff); - - if (bus_space_subregion(sc->sc_st, sc->sc_sh, - AT91SAM9G20_MATRIX_BASE, AT91SAM9G20_MATRIX_SIZE, - &sc->sc_matrix_sh) != 0) - panic("Enable to map matrix registers"); - - /* activate NAND*/ - i = bus_space_read_4(sc->sc_st, sc->sc_matrix_sh, - AT91SAM9G20_EBICSA); - bus_space_write_4(sc->sc_st, sc->sc_matrix_sh, - AT91SAM9G20_EBICSA, - i | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA); - /* Update USB device port clock info */ clk = at91_pmc_clock_ref("udpck"); @@ -279,29 +185,14 @@ at91_attach(device_t dev) clk->pll_div_mask = SAM9G20_PLL_B_DIV_MASK; clk->set_outb = at91_pll_outb; at91_pmc_clock_deref(clk); - return (0); } -static device_method_t at91_methods[] = { - DEVMETHOD(device_probe, at91_probe), - DEVMETHOD(device_attach, at91_attach), - DEVMETHOD(device_identify, at91_identify), - {0, 0}, -}; - -static driver_t at91sam9_driver = { - "at91sam", - at91_methods, - sizeof(struct at91sam9_softc), -}; - -static devclass_t at91sam9_devclass; - -DRIVER_MODULE(at91sam, atmelarm, at91sam9_driver, at91sam9_devclass, 0, 0); - static struct at91_soc_data soc_data = { .soc_delay = at91_pit_delay, - .soc_reset = at91_rst_cpu_reset + .soc_reset = at91_rst_cpu_reset, + .soc_clock_init = at91_clock_init, + .soc_irq_prio = at91_irq_prio, + .soc_children = at91_devs, }; AT91_SOC(AT91_T_SAM9G20, &soc_data); diff --git a/sys/arm/at91/at91sam9g45.c b/sys/arm/at91/at91sam9g45.c new file mode 100644 index 0000000..638c3d9 --- /dev/null +++ b/sys/arm/at91/at91sam9g45.c @@ -0,0 +1,177 @@ +/*- + * Copyright (c) 2005 Olivier Houchard. All rights reserved. + * Copyright (c) 2010 Greg Ansley. All rights reserved. + * Copyright (c) 2012 Andrew Turner. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <sys/cdefs.h> +__FBSDID("$FreeBSD$"); + +#include <sys/param.h> +#include <sys/systm.h> +#include <sys/bus.h> +#include <sys/kernel.h> +#include <sys/malloc.h> +#include <sys/module.h> + +#define _ARM32_BUS_DMA_PRIVATE +#include <machine/bus.h> + +#include <arm/at91/at91var.h> +#include <arm/at91/at91reg.h> +#include <arm/at91/at91soc.h> +#include <arm/at91/at91_aicreg.h> +#include <arm/at91/at91sam9g45reg.h> +#include <arm/at91/at91_pitreg.h> +#include <arm/at91/at91_pmcreg.h> +#include <arm/at91/at91_pmcvar.h> +#include <arm/at91/at91_rstreg.h> + +/* + * Standard priority levels for the system. 0 is lowest and 7 is highest. + * These values are the ones Atmel uses for its Linux port + */ +static const int at91_irq_prio[32] = +{ + 7, /* Advanced Interrupt Controller */ + 7, /* System Peripherals */ + 1, /* Parallel IO Controller A */ + 1, /* Parallel IO Controller B */ + 1, /* Parallel IO Controller C */ + 1, /* Parallel IO Controller D and E */ + 0, + 5, /* USART 0 */ + 5, /* USART 1 */ + 5, /* USART 2 */ + 5, /* USART 3 */ + 0, /* Multimedia Card Interface 0 */ + 6, /* Two-Wire Interface 0 */ + 6, /* Two-Wire Interface 1 */ + 5, /* Serial Peripheral Interface 0 */ + 5, /* Serial Peripheral Interface 1 */ + 4, /* Serial Synchronous Controller 0 */ + 4, /* Serial Synchronous Controller 1 */ + 0, /* Timer Counter 0, 1, 2, 3, 4 and 5 */ + 0, /* Pulse Width Modulation Controller */ + 0, /* Touch Screen Controller */ + 0, /* DMA Controller */ + 2, /* USB Host High Speed port */ + 3, /* LCD Controller */ + 5, /* AC97 Controller */ + 3, /* Ethernet */ + 0, /* Image Sensor Interface */ + 2, /* USB Device High Speed port */ + 0, /* (reserved) */ + 0, /* Multimedia Card Interface 1 */ + 0, /* (reserved) */ + 0, /* Advanced Interrupt Controller IRQ0 */ +}; + +#define DEVICE(_name, _id, _unit) \ + { \ + _name, _unit, \ + AT91SAM9G45_ ## _id ##_BASE, \ + AT91SAM9G45_ ## _id ## _SIZE, \ + AT91SAM9G45_IRQ_ ## _id \ + } + +static const struct cpu_devs at91_devs[] = +{ + DEVICE("at91_pmc", PMC, 0), + DEVICE("at91_wdt", WDT, 0), + DEVICE("at91_rst", RSTC, 0), + DEVICE("at91_pit", PIT, 0), + DEVICE("at91_pio", PIOA, 0), + DEVICE("at91_pio", PIOB, 1), + DEVICE("at91_pio", PIOC, 2), + DEVICE("at91_pio", PIOD, 3), + DEVICE("at91_pio", PIOE, 4), + DEVICE("at91_twi", TWI0, 0), + DEVICE("at91_twi", TWI1, 1), + DEVICE("at91_mci", HSMCI0, 0), + DEVICE("at91_mci", HSMCI1, 1), + DEVICE("uart", DBGU, 0), + DEVICE("uart", USART0, 1), + DEVICE("uart", USART1, 2), + DEVICE("uart", USART2, 3), + DEVICE("uart", USART3, 4), + DEVICE("spi", SPI0, 0), + DEVICE("spi", SPI1, 1), + DEVICE("ate", EMAC, 0), + DEVICE("macb", EMAC, 0), + DEVICE("nand", NAND, 0), + DEVICE("ohci", OHCI, 0), + { 0, 0, 0, 0, 0 } +}; + +static uint32_t +at91_pll_outa(int freq) +{ + + switch (freq / 10000000) { + case 747 ... 801: return ((1 << 29) | (0 << 14)); + case 697 ... 746: return ((1 << 29) | (1 << 14)); + case 647 ... 696: return ((1 << 29) | (2 << 14)); + case 597 ... 646: return ((1 << 29) | (3 << 14)); + case 547 ... 596: return ((1 << 29) | (4 << 14)); + case 497 ... 546: return ((1 << 29) | (5 << 14)); + case 447 ... 496: return ((1 << 29) | (6 << 14)); + case 397 ... 446: return ((1 << 29) | (7 << 14)); + default: return (1 << 29); + } +} + +static void +at91_clock_init(void) +{ + struct at91_pmc_clock *clk; + + /* Update USB host port clock info */ + clk = at91_pmc_clock_ref("uhpck"); + clk->pmc_mask = PMC_SCER_UHP_SAM9; + at91_pmc_clock_deref(clk); + + /* Each SOC has different PLL contraints */ + clk = at91_pmc_clock_ref("plla"); + clk->pll_min_in = SAM9G45_PLL_A_MIN_IN_FREQ; /* 2 MHz */ + clk->pll_max_in = SAM9G45_PLL_A_MAX_IN_FREQ; /* 32 MHz */ + clk->pll_min_out = SAM9G45_PLL_A_MIN_OUT_FREQ; /* 400 MHz */ + clk->pll_max_out = SAM9G45_PLL_A_MAX_OUT_FREQ; /* 800 MHz */ + clk->pll_mul_shift = SAM9G45_PLL_A_MUL_SHIFT; + clk->pll_mul_mask = SAM9G45_PLL_A_MUL_MASK; + clk->pll_div_shift = SAM9G45_PLL_A_DIV_SHIFT; + clk->pll_div_mask = SAM9G45_PLL_A_DIV_MASK; + clk->set_outb = at91_pll_outa; + at91_pmc_clock_deref(clk); +} + +static struct at91_soc_data soc_data = { + .soc_delay = at91_pit_delay, + .soc_reset = at91_rst_cpu_reset, + .soc_clock_init = at91_clock_init, + .soc_irq_prio = at91_irq_prio, + .soc_children = at91_devs, +}; + +AT91_SOC(AT91_T_SAM9G45, &soc_data); diff --git a/sys/arm/at91/at91sam9g45reg.h b/sys/arm/at91/at91sam9g45reg.h new file mode 100644 index 0000000..86574b3 --- /dev/null +++ b/sys/arm/at91/at91sam9g45reg.h @@ -0,0 +1,294 @@ +/*- + * Copyright (c) 2009 Sylvestre Gallon. All rights reserved. + * Copyright (c) 2010 Greg Ansley. All rights reserved. + * Copyright (c) 2012 Andrew Turner. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +/* $FreeBSD$ */ + +#ifndef AT91SAM9G45REG_H_ +#define AT91SAM9G45REG_H_ + +/* Chip Specific limits */ +#define SAM9G45_PLL_A_MIN_IN_FREQ 2000000 /* 2 Mhz */ +#define SAM9G45_PLL_A_MAX_IN_FREQ 32000000 /* 32 Mhz */ +#define SAM9G45_PLL_A_MIN_OUT_FREQ 400000000 /* 400 Mhz */ +#define SAM9G45_PLL_A_MAX_OUT_FREQ 800000000 /* 800 Mhz */ +#define SAM9G45_PLL_A_MUL_SHIFT 16 +#define SAM9G45_PLL_A_MUL_MASK 0xFF +#define SAM9G45_PLL_A_DIV_SHIFT 0 +#define SAM9G45_PLL_A_DIV_MASK 0xFF + +/* + * Memory map, from datasheet : + * 0x00000000 - 0x0ffffffff : Internal Memories + * 0x10000000 - 0x1ffffffff : Chip Select 0 + * 0x20000000 - 0x2ffffffff : Chip Select 1 + * 0x30000000 - 0x3ffffffff : Chip Select 2 + * 0x40000000 - 0x4ffffffff : Chip Select 3 + * 0x50000000 - 0x5ffffffff : Chip Select 4 + * 0x60000000 - 0x6ffffffff : Chip Select 5 + * 0x70000000 - 0x7ffffffff : DDR SDRC 0 + * 0x80000000 - 0xeffffffff : Undefined (Abort) + * 0xf0000000 - 0xfffffffff : Peripherals + */ + +#define AT91_CHIPSELECT_0 0x10000000 +#define AT91_CHIPSELECT_1 0x20000000 +#define AT91_CHIPSELECT_2 0x30000000 +#define AT91_CHIPSELECT_3 0x40000000 +#define AT91_CHIPSELECT_4 0x50000000 +#define AT91_CHIPSELECT_5 0x60000000 + + +#define AT91SAM9G45_EMAC_BASE 0xffbc000 +#define AT91SAM9G45_EMAC_SIZE 0x4000 + +#define AT91SAM9G45_RSTC_BASE 0xffffd00 +#define AT91SAM9G45_RSTC_SIZE 0x10 + +/* USART*/ + +#define AT91SAM9G45_USART_SIZE 0x4000 +#define AT91SAM9G45_USART0_BASE 0xff8c000 +#define AT91SAM9G45_USART0_SIZE AT91SAM9G45_USART_SIZE +#define AT91SAM9G45_USART1_BASE 0xff90000 +#define AT91SAM9G45_USART1_SIZE AT91SAM9G45_USART_SIZE +#define AT91SAM9G45_USART2_BASE 0xff94000 +#define AT91SAM9G45_USART2_SIZE AT91SAM9G45_USART_SIZE +#define AT91SAM9G45_USART3_BASE 0xff98000 +#define AT91SAM9G45_USART3_SIZE AT91SAM9G45_USART_SIZE + +/*TC*/ +#define AT91SAM9G45_TC0_BASE 0xff7c000 +#define AT91SAM9G45_TC0_SIZE 0x4000 +#define AT91SAM9G45_TC0C0_BASE 0xff7c000 +#define AT91SAM9G45_TC0C1_BASE 0xff7c040 +#define AT91SAM9G45_TC0C2_BASE 0xff7c080 + +#define AT91SAM9G45_TC1_BASE 0xffd4000 +#define AT91SAM9G45_TC1_SIZE 0x4000 +#define AT91SAM9G45_TC1C0_BASE 0xffd4000 +#define AT91SAM9G45_TC1C1_BASE 0xffd4040 +#define AT91SAM9G45_TC1C2_BASE 0xffd4080 + +/*SPI*/ + +#define AT91SAM9G45_SPI0_BASE 0xffa48000 +#define AT91SAM9G45_SPI0_SIZE 0x4000 + +#define AT91SAM9G45_SPI1_BASE 0xffa8000 +#define AT91SAM9G45_SPI1_SIZE 0x4000 + +/* System Registers */ +#define AT91SAM9G45_SYS_BASE 0xffff000 +#define AT91SAM9G45_SYS_SIZE 0x1000 + +#define AT91SAM9G45_MATRIX_BASE 0xfffea00 +#define AT91SAM9G45_MATRIX_SIZE 0x200 + +#define AT91SAM9G45_DBGU_BASE 0xfffee00 +#define AT91SAM9G45_DBGU_SIZE 0x200 + +/* + * PIO + */ +#define AT91SAM9G45_PIOA_BASE 0xffff200 +#define AT91SAM9G45_PIOA_SIZE 0x200 +#define AT91SAM9G45_PIOB_BASE 0xffff400 +#define AT91SAM9G45_PIOB_SIZE 0x200 +#define AT91SAM9G45_PIOC_BASE 0xffff600 +#define AT91SAM9G45_PIOC_SIZE 0x200 +#define AT91SAM9G45_PIOD_BASE 0xffff800 +#define AT91SAM9G45_PIOD_SIZE 0x200 +#define AT91SAM9G45_PIOE_BASE 0xffffa00 +#define AT91SAM9G45_PIOE_SIZE 0x200 + +#define AT91SAM9G45_PMC_BASE 0xffffc00 +#define AT91SAM9G45_PMC_SIZE 0x100 + +/* IRQs : */ +/* + * 0: AIC + * 1: System peripheral (System timer, RTC, DBGU) + * 2: PIO Controller A + * 3: PIO Controller B + * 4: PIO Controller C + * 5: PIO Controller D/E + * 6: TRNG + * 7: USART 0 + * 8: USART 1 + * 9: USART 2 + * 10: USART 3 + * 11: Multimedia Card interface 0 + * 12: Two-wirte interface 0 + * 13: Two-wirte interface 1 + * 14: SPI 0 + * 15: SPI 1 + * 16: SSC 0 + * 17: SSC 0 + * 18: Timer Counter 0, 2, 3, 4, 5 + * 19: PWM + * 20: Touch Screen ADC + * 21: DMA + * 22: USB Host port + * 23: LCD + * 24: AC97 + * 25: EMAC + * 26: Image Sensor Interface + * 27: USB Device High Speed + * 28: - + * 29: Multimedia Card interface 1 + * 30: Reserved + * 31: AIC + */ + +#define AT91SAM9G45_IRQ_SYSTEM 1 +#define AT91SAM9G45_IRQ_PIOA 2 +#define AT91SAM9G45_IRQ_PIOB 3 +#define AT91SAM9G45_IRQ_PIOC 4 +#define AT91SAM9G45_IRQ_PIOD 5 +#define AT91SAM9G45_IRQ_PIOE 6 +#define AT91SAM9G45_IRQ_USART0 7 +#define AT91SAM9G45_IRQ_USART1 8 +#define AT91SAM9G45_IRQ_USART2 9 +#define AT91SAM9G45_IRQ_USART3 10 +#define AT91SAM9G45_IRQ_HSMCI0 11 +#define AT91SAM9G45_IRQ_TWI0 12 +#define AT91SAM9G45_IRQ_TWI1 13 +#define AT91SAM9G45_IRQ_SPI0 14 +#define AT91SAM9G45_IRQ_SPI1 15 +#define AT91SAM9G45_IRQ_SSC0 16 +#define AT91SAM9G45_IRQ_SSC1 17 +#define AT91SAM9G45_IRQ_TC0_TC5 18 +#define AT91SAM9G45_IRQ_PWM 19 +#define AT91SAM9G45_IRQ_TSADCC 20 +#define AT91SAM9G45_IRQ_DMA 21 +#define AT91SAM9G45_IRQ_UHP 22 +#define AT91SAM9G45_IRQ_LCDC 23 +#define AT91SAM9G45_IRQ_AC97C 24 +#define AT91SAM9G45_IRQ_EMAC 25 +#define AT91SAM9G45_IRQ_ISI 26 +#define AT91SAM9G45_IRQ_UDPHS 27 +/* Reserved 28 */ +#define AT91SAM9G45_IRQ_HSMCI1 29 +/* Reserved 30 */ +#define AT91SAM9G45_IRQ_AICBASE 31 + +/* Alias */ +#define AT91SAM9G45_IRQ_DBGU AT91SAM9G45_IRQ_SYSTEM +#define AT91SAM9G45_IRQ_PMC AT91SAM9G45_IRQ_SYSTEM +#define AT91SAM9G45_IRQ_WDT AT91SAM9G45_IRQ_SYSTEM +#define AT91SAM9G45_IRQ_PIT AT91SAM9G45_IRQ_SYSTEM +#define AT91SAM9G45_IRQ_RSTC AT91SAM9G45_IRQ_SYSTEM +#define AT91SAM9G45_IRQ_OHCI AT91SAM9G45_IRQ_UHP +#define AT91SAM9G45_IRQ_TC0 AT91SAM9G45_IRQ_TC0_TC5 +#define AT91SAM9G45_IRQ_TC1 AT91SAM9G45_IRQ_TC0_TC5 +#define AT91SAM9G45_IRQ_TC2 AT91SAM9G45_IRQ_TC0_TC5 +#define AT91SAM9G45_IRQ_TC3 AT91SAM9G45_IRQ_TC0_TC5 +#define AT91SAM9G45_IRQ_TC4 AT91SAM9G45_IRQ_TC0_TC5 +#define AT91SAM9G45_IRQ_TC5 AT91SAM9G45_IRQ_TC0_TC5 +#define AT91SAM9G45_IRQ_NAND (-1) + +#define AT91SAM9G45_AIC_BASE 0xffff000 +#define AT91SAM9G45_AIC_SIZE 0x200 + +/* Timer */ + +#define AT91SAM9G45_WDT_BASE 0xffffd40 +#define AT91SAM9G45_WDT_SIZE 0x10 + +#define AT91SAM9G45_PIT_BASE 0xffffd30 +#define AT91SAM9G45_PIT_SIZE 0x10 + +#define AT91SAM9G45_SMC_BASE 0xfffe800 +#define AT91SAM9G45_SMC_SIZE 0x200 + +#define AT91SAM9G45_PMC_BASE 0xffffc00 +#define AT91SAM9G45_PMC_SIZE 0x100 + +#define AT91SAM9G45_HSMCI0_BASE 0xff80000 +#define AT91SAM9G45_HSMCI0_SIZE 0x4000 + +#define AT91SAM9G45_HSMCI1_BASE 0xffd0000 +#define AT91SAM9G45_HSMCI1_SIZE 0x4000 + +#define AT91SAM9G45_TWI0_BASE 0xff84000 +#define AT91SAM9G45_TWI0_SIZE 0x4000 +#define AT91SAM9G45_TWI1_BASE 0xff88000 +#define AT91SAM9G45_TWI1_SIZE 0x4000 + +/* XXX Needs to be carfully coordinated with + * other * soc's so phyical and vm address + * mapping are unique. XXX + */ +#define AT91SAM9G45_OHCI_BASE 0xdfb00000 +#define AT91SAM9G45_OHCI_PA_BASE 0x00700000 +#define AT91SAM9G45_OHCI_SIZE 0x00100000 + +#define AT91SAM9G45_NAND_BASE 0xe0000000 +#define AT91SAM9G45_NAND_PA_BASE 0x40000000 +#define AT91SAM9G45_NAND_SIZE 0x10000000 + + +/* DDRSDRC */ +#define AT91SAM9G45_DDRSDRC1_BASE 0xfffea00 +#define AT91SAM9G45_DDRSDRC0_BASE 0xfffe600 +#define AT91SAM9G45_DDRSDRC_MR 0x00 +#define AT91SAM9G45_DDRSDRC_TR 0x04 +#define AT91SAM9G45_DDRSDRC_CR 0x08 +#define AT91SAM9G45_DDRSDRC_CR_NC_8 0x0 +#define AT91SAM9G45_DDRSDRC_CR_NC_9 0x1 +#define AT91SAM9G45_DDRSDRC_CR_NC_10 0x2 +#define AT91SAM9G45_DDRSDRC_CR_NC_11 0x3 +#define AT91SAM9G45_DDRSDRC_CR_NC_MASK 0x00000003 +#define AT91SAM9G45_DDRSDRC_CR_NR_11 0x0 +#define AT91SAM9G45_DDRSDRC_CR_NR_12 0x4 +#define AT91SAM9G45_DDRSDRC_CR_NR_13 0x8 +#define AT91SAM9G45_DDRSDRC_CR_NR_14 0xc +#define AT91SAM9G45_DDRSDRC_CR_NR_MASK 0x0000000c +#define AT91SAM9G45_DDRSDRC_TPR0 0x0c +#define AT91SAM9G45_DDRSDRC_TPR1 0x10 +#define AT91SAM9G45_DDRSDRC_TPR2 0x14 +/* Reserved 0x18 */ +#define AT91SAM9G45_DDRSDRC_LPR 0x1c +#define AT91SAM9G45_DDRSDRC_MDR 0x20 +#define AT91SAM9G45_DDRSDRC_MDR_SDR 0x0 +#define AT91SAM9G45_DDRSDRC_MDR_LPSDR 0x1 +#define AT91SAM9G45_DDRSDRC_MDR_LPDDR1 0x3 +#define AT91SAM9G45_DDRSDRC_MDR_DDR2 0x6 +#define AT91SAM9G45_DDRSDRC_MDR_MASK 0x00000007 +#define AT91SAM9G45_DDRSDRC_MDR_DBW_16 0x10 +#define AT91SAM9G45_DDRSDRC_DLL 0x24 +#define AT91SAM9G45_DDRSDRC_HSR 0x2c +#define AT91SAM9G45_DDRSDRC_DELAY1R 0x40 +#define AT91SAM9G45_DDRSDRC_DELAY2R 0x44 +#define AT91SAM9G45_DDRSDRC_DELAY3R 0x48 +#define AT91SAM9G45_DDRSDRC_DELAY4R 0x4c +/* Reserved 0x50 - 0xe0 */ +#define AT91SAM9G45_DDRSDRC_WPMR 0xe4 +#define AT91SAM9G45_DDRSDRC_WPSR 0xe8 + +#endif /* AT91SAM9G45REG_H_*/ + diff --git a/sys/arm/at91/at91sam9x25.c b/sys/arm/at91/at91sam9x5.c index b84d30c..3de9ebd 100644 --- a/sys/arm/at91/at91sam9x25.c +++ b/sys/arm/at91/at91sam9x5.c @@ -41,20 +41,12 @@ __FBSDID("$FreeBSD$"); #include <arm/at91/at91reg.h> #include <arm/at91/at91soc.h> #include <arm/at91/at91_aicreg.h> -#include <arm/at91/at91sam9x25reg.h> +#include <arm/at91/at91sam9x5reg.h> #include <arm/at91/at91_pitreg.h> #include <arm/at91/at91_pmcreg.h> #include <arm/at91/at91_pmcvar.h> #include <arm/at91/at91_rstreg.h> -struct at91sam9x25_softc { - device_t dev; - bus_space_tag_t sc_st; - bus_space_handle_t sc_sh; - bus_space_handle_t sc_sys_sh; - bus_space_handle_t sc_aic_sh; -}; - /* * Standard priority levels for the system. 0 is lowest and 7 is highest. * These values are the ones Atmel uses for its Linux port @@ -133,19 +125,6 @@ static const struct cpu_devs at91_devs[] = { 0, 0, 0, 0, 0 } }; -static void -at91_cpu_add_builtin_children(device_t dev) -{ - int i; - const struct cpu_devs *walker; - - for (i = 1, walker = at91_devs; walker->name; i++, walker++) { - at91_add_child(dev, i, walker->name, walker->unit, - walker->mem_base, walker->mem_len, walker->irq0, - walker->irq1, walker->irq2); - } -} - static uint32_t at91_pll_outa(int freq) { @@ -171,68 +150,9 @@ at91_pll_outb(int freq) } static void -at91_identify(driver_t *drv, device_t parent) -{ - - if (soc_info.type == AT91_T_SAM9X5 && soc_info.subtype == AT91_ST_SAM9X25) { - at91_add_child(parent, 0, "at91sam9x25", 0, 0, 0, -1, 0, 0); - at91_cpu_add_builtin_children(parent); - } -} - -static int -at91_probe(device_t dev) -{ - - device_set_desc(dev, "AT91SAM9X25"); - return (0); -} - -static int -at91_attach(device_t dev) +at91_clock_init(void) { struct at91_pmc_clock *clk; - struct at91sam9x25_softc *sc = device_get_softc(dev); - int i; - - struct at91_softc *at91sc = device_get_softc(device_get_parent(dev)); - - sc->sc_st = at91sc->sc_st; - sc->sc_sh = at91sc->sc_sh; - sc->dev = dev; - - /* - * XXX These values work for the RM9200, SAM926[01], and SAM9X25 - * will have to fix this when we want to support anything else. XXX - */ - if (bus_space_subregion(sc->sc_st, sc->sc_sh, AT91SAM9X25_SYS_BASE, - AT91SAM9X25_SYS_SIZE, &sc->sc_sys_sh) != 0) - panic("Enable to map system registers"); - - if (bus_space_subregion(sc->sc_st, sc->sc_sh, AT91SAM9X25_AIC_BASE, - AT91SAM9X25_AIC_SIZE, &sc->sc_aic_sh) != 0) - panic("Enable to map system registers"); - - /* XXX Hack to tell atmelarm about the AIC */ - at91sc->sc_aic_sh = sc->sc_aic_sh; - - for (i = 0; i < 32; i++) { - bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_SVR + - i * 4, i); - /* Priority. */ - bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_SMR + i * 4, - at91_irq_prio[i]); - if (i < 8) - bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_EOICR, - 1); - } - - bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_SPU, 32); - /* No debug. */ - bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_DCR, 0); - /* Disable and clear all interrupts. */ - bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_IDCR, 0xffffffff); - bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_ICCR, 0xffffffff); /* Update USB device port clock info */ clk = at91_pmc_clock_ref("udpck"); @@ -268,29 +188,14 @@ at91_attach(device_t dev) clk->pll_div_mask = SAM9X25_PLL_B_DIV_MASK; clk->set_outb = at91_pll_outb; at91_pmc_clock_deref(clk); - return (0); } -static device_method_t at91sam9x25_methods[] = { - DEVMETHOD(device_probe, at91_probe), - DEVMETHOD(device_attach, at91_attach), - DEVMETHOD(device_identify, at91_identify), - {0, 0}, -}; - -static driver_t at91sam9x25_driver = { - "at91sam9x25", - at91sam9x25_methods, - sizeof(struct at91sam9x25_softc), -}; - -static devclass_t at91sam9x25_devclass; - -DRIVER_MODULE(at91sam9x25, atmelarm, at91sam9x25_driver, at91sam9x25_devclass, 0, 0); - static struct at91_soc_data soc_data = { .soc_delay = at91_pit_delay, - .soc_reset = at91_rst_cpu_reset + .soc_reset = at91_rst_cpu_reset, + .soc_clock_init = at91_clock_init, + .soc_irq_prio = at91_irq_prio, + .soc_children = at91_devs, }; AT91_SOC_SUB(AT91_T_SAM9X5, AT91_ST_SAM9X25, &soc_data); diff --git a/sys/arm/at91/at91sam9x25reg.h b/sys/arm/at91/at91sam9x5reg.h index d497e2b..17c43ff 100644 --- a/sys/arm/at91/at91sam9x25reg.h +++ b/sys/arm/at91/at91sam9x5reg.h @@ -27,8 +27,8 @@ /* $FreeBSD$ */ -#ifndef AT91SAM9X25REG_H_ -#define AT91SAM9X25REG_H_ +#ifndef AT91SAM9X5REG_H_ +#define AT91SAM9X5REG_H_ #ifndef AT91SAM9X25_MASTER_CLOCK #define AT91SAM9X25_MASTER_CLOCK ((18432000 * 43)/6) @@ -312,5 +312,4 @@ #define AT91SAM9X25_SDRAMC_ISR 0x20 #define AT91SAM9X25_SDRAMC_MDR 0x24 -#endif /* AT91SAM9X25REG_H_*/ - +#endif /* AT91SAM9X5REG_H_*/ diff --git a/sys/arm/at91/at91var.h b/sys/arm/at91/at91var.h index 183b723..b149465 100644 --- a/sys/arm/at91/at91var.h +++ b/sys/arm/at91/at91var.h @@ -104,10 +104,14 @@ enum at91_soc_family { typedef void (*DELAY_t)(int); typedef void (*cpu_reset_t)(void); +typedef void (*clk_init_t)(void); struct at91_soc_data { DELAY_t soc_delay; cpu_reset_t soc_reset; + clk_init_t soc_clock_init; + const int *soc_irq_prio; + const struct cpu_devs *soc_children; }; struct at91_soc_info { @@ -117,6 +121,7 @@ struct at91_soc_info { uint32_t cidr; uint32_t exid; char name[AT91_SOC_NAME_MAX]; + uint32_t dbgu_base; struct at91_soc_data *soc_data; }; diff --git a/sys/arm/at91/board_bwct.c b/sys/arm/at91/board_bwct.c index 63f3910..0515b21 100644 --- a/sys/arm/at91/board_bwct.c +++ b/sys/arm/at91/board_bwct.c @@ -1,6 +1,6 @@ /*- * Copyright (c) 2005-2008 Olivier Houchard. All rights reserved. - * Copyright (c) 2005-2008 Warner Losh. All rights reserved. + * Copyright (c) 2005-2012 Warner Losh. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -31,37 +31,22 @@ __FBSDID("$FreeBSD$"); #include <machine/board.h> #include <arm/at91/at91board.h> -#include <arm/at91/at91rm92reg.h> -#include <arm/at91/at91_piovar.h> -#include <arm/at91/at91_pio_rm9200.h> +#include <arm/at91/at91var.h> +#include <arm/at91/at91rm9200var.h> BOARD_INIT long board_init(void) { + + at91rm9200_set_subtype(AT91_ST_RM9200_BGA); + /* - * Since the USART supports RS-485 multidrop mode, it allows the - * TX pins to float. However, for RS-232 operations, we don't want - * these pins to float. Instead, they should be pulled up to avoid - * mismatches. Linux does something similar when it configures the - * TX lines. This implies that we also allow the RX lines to float - * rather than be in the state they are left in by the boot loader. - * Since they are input pins, I think that this is the right thing - * to do. + * I don't know anything at all about this board. */ + at91rm9200_config_uart(AT91_ID_DBGU, 0, 0); /* DBGU just Tx and Rx */ - /* PIOA's A periph: Turn USART 0 and 2's TX/RX pins */ - at91_pio_use_periph_a(AT91RM92_PIOA_BASE, - AT91C_PA18_RXD0 | AT91C_PA22_RXD2, 0); - at91_pio_use_periph_a(AT91RM92_PIOA_BASE, - AT91C_PA17_TXD0 | AT91C_PA23_TXD2, 1); - /* PIOA's B periph: Turn USART 3's TX/RX pins */ - at91_pio_use_periph_b(AT91RM92_PIOA_BASE, AT91C_PA6_RXD3, 0); - at91_pio_use_periph_b(AT91RM92_PIOA_BASE, AT91C_PA5_TXD3, 1); - /* PIOB's A periph: Turn USART 1's TX/RX pins */ - at91_pio_use_periph_a(AT91RM92_PIOB_BASE, AT91C_PB21_RXD1, 0); - at91_pio_use_periph_a(AT91RM92_PIOB_BASE, AT91C_PB20_TXD1, 1); - - /* Pin assignment */ + at91rm9200_config_mci(0); + /* Configure ethernet */ return (at91_ramsize()); } diff --git a/sys/arm/at91/board_ethernut5.c b/sys/arm/at91/board_ethernut5.c index a09c335..96beeba 100644 --- a/sys/arm/at91/board_ethernut5.c +++ b/sys/arm/at91/board_ethernut5.c @@ -146,4 +146,4 @@ board_init(void) return (at91_ramsize()); } -ARM_BOARD(NONE, "Ethernut 5") +ARM_BOARD(ETHERNUT5, "Ethernut 5") diff --git a/sys/arm/at91/board_hl200.c b/sys/arm/at91/board_hl200.c index 07db749..d3ac4fe 100644 --- a/sys/arm/at91/board_hl200.c +++ b/sys/arm/at91/board_hl200.c @@ -1,6 +1,6 @@ /*- * Copyright (c) 2005-2008 Olivier Houchard. All rights reserved. - * Copyright (c) 2005-2008 Warner Losh. All rights reserved. + * Copyright (c) 2005-2012 Warner Losh. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -31,34 +31,33 @@ __FBSDID("$FreeBSD$"); #include <machine/board.h> #include <arm/at91/at91board.h> +#include <arm/at91/at91var.h> #include <arm/at91/at91rm92reg.h> -#include <arm/at91/at91_piovar.h> -#include <arm/at91/at91_pio_rm9200.h> +#include <arm/at91/at91rm9200var.h> BOARD_INIT long board_init(void) { + + at91rm9200_set_subtype(AT91_ST_RM9200_BGA); + /* - * Since the USART supports RS-485 multidrop mode, it allows the - * TX pins to float. However, for RS-232 operations, we don't want - * these pins to float. Instead, they should be pulled up to avoid - * mismatches. Linux does something similar when it configures the - * TX lines. This implies that we also allow the RX lines to float - * rather than be in the state they are left in by the boot loader. - * Since they are input pins, I think that this is the right thing - * to do. + * Unsure what all is in the HOTe HL200, but I do know there's + * one serial port that isn't DBGU. There's many other peripherals + * that need to be configured here. */ - /* PIOA's A periph: Turn USART 0 and 2's TX/RX pins */ - at91_pio_use_periph_a(AT91RM92_PIOA_BASE, - AT91C_PA18_RXD0 | AT91C_PA22_RXD2, 0); - at91_pio_use_periph_a(AT91RM92_PIOA_BASE, - AT91C_PA17_TXD0 | AT91C_PA23_TXD2, 1); - /* PIOA's B periph: Turn USART 3's TX/RX pins */ - at91_pio_use_periph_b(AT91RM92_PIOA_BASE, AT91C_PA6_RXD3, 0); - at91_pio_use_periph_b(AT91RM92_PIOA_BASE, AT91C_PA5_TXD3, 1); - /* PIOB's A periph: Turn USART 1's TX/RX pins */ - at91_pio_use_periph_a(AT91RM92_PIOB_BASE, AT91C_PB21_RXD1, 0); - at91_pio_use_periph_a(AT91RM92_PIOB_BASE, AT91C_PB20_TXD1, 1); + at91rm9200_config_uart(AT91_ID_DBGU, 0, 0); /* DBGU just Tx and Rx */ + at91rm9200_config_uart(AT91RM9200_ID_USART0, 1, 0); /* Tx and Rx */ + + at91rm9200_config_mci(0); /* HOTe HL200 unknown 1 vs 4 wire */ + + /* Enable CF card slot */ + /* Enable sound thing */ + /* Enable VGA chip */ + /* Enable ethernet */ + /* Enable TWI + RTC */ + /* Enable USB Host */ + /* Enable USB Device (gadget) */ return (at91_ramsize()); } diff --git a/sys/arm/at91/board_kb920x.c b/sys/arm/at91/board_kb920x.c index a577f87..1f35705 100644 --- a/sys/arm/at91/board_kb920x.c +++ b/sys/arm/at91/board_kb920x.c @@ -1,6 +1,6 @@ /*- * Copyright (c) 2005-2008 Olivier Houchard. All rights reserved. - * Copyright (c) 2005-2008 Warner Losh. All rights reserved. + * Copyright (c) 2005-2012 Warner Losh. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -30,44 +30,35 @@ __FBSDID("$FreeBSD$"); #include <sys/systm.h> #include <machine/board.h> -#include <arm/at91/at91var.h> #include <arm/at91/at91board.h> -#include <arm/at91/at91rm92reg.h> -#include <arm/at91/at91_piovar.h> -#include <arm/at91/at91_pio_rm9200.h> +#include <arm/at91/at91var.h> +#include <arm/at91/at91rm9200var.h> BOARD_INIT long board_init(void) { + + at91rm9200_set_subtype(AT91_ST_RM9200_PQFP); + /* - * Since the USART supports RS-485 multidrop mode, it allows the - * TX pins to float. However, for RS-232 operations, we don't want - * these pins to float. Instead, they should be pulled up to avoid - * mismatches. Linux does something similar when it configures the - * TX lines. This implies that we also allow the RX lines to float - * rather than be in the state they are left in by the boot loader. - * Since they are input pins, I think that this is the right thing - * to do. + * Setup the serial ports. + * DBGU is the main one, although jumpers can make USART0 default. + * USART1 is IrDA, and USART3 is optional RS485. */ - /* PIOA's A periph: Turn USART 0 and 2's TX/RX pins */ - at91_pio_use_periph_a(AT91RM92_PIOA_BASE, - AT91C_PA18_RXD0 | AT91C_PA22_RXD2, 0); - at91_pio_use_periph_a(AT91RM92_PIOA_BASE, - AT91C_PA17_TXD0 | AT91C_PA23_TXD2, 1); - /* PIOA's B periph: Turn USART 3's TX/RX pins */ - at91_pio_use_periph_b(AT91RM92_PIOA_BASE, AT91C_PA6_RXD3, 0); - at91_pio_use_periph_b(AT91RM92_PIOA_BASE, AT91C_PA5_TXD3, 1); - /* PIOB's A periph: Turn USART 1's TX/RX pins */ - at91_pio_use_periph_a(AT91RM92_PIOB_BASE, AT91C_PB21_RXD1, 0); - at91_pio_use_periph_a(AT91RM92_PIOB_BASE, AT91C_PB20_TXD1, 1); + at91rm9200_config_uart(AT91_ID_DBGU, 0, 0); /* DBGU just Tx and Rx */ + at91rm9200_config_uart(AT91RM9200_ID_USART0, 1, 0); /* Tx and Rx */ + at91rm9200_config_uart(AT91RM9200_ID_USART1, 2, 0); /* Tx and Rx - IRDA */ + at91rm9200_config_uart(AT91RM9200_ID_USART3, 3, /* Tx, Rx, CTS, RTS - RS485 */ + AT91_UART_CTS | AT91_UART_RTS); + + at91rm9200_config_mci(1); - /* MMC/SD Interface */ - at91_pio_use_periph_a(AT91RM92_PIOA_BASE,AT91C_PA27_MCCK, 0); - at91_pio_use_periph_a(AT91RM92_PIOA_BASE,AT91C_PA28_MCCDA, 1); - at91_pio_use_periph_a(AT91RM92_PIOA_BASE,AT91C_PA29_MCDA0, 1); - at91_pio_use_periph_b(AT91RM92_PIOB_BASE,AT91C_PB3_MCDA1, 1); - at91_pio_use_periph_b(AT91RM92_PIOB_BASE,AT91C_PB4_MCDA2, 1); - at91_pio_use_periph_b(AT91RM92_PIOB_BASE,AT91C_PB5_MCDA3, 1); + /* CFE interface */ + /* ethernet interface */ + /* lcd interface */ + /* USB host */ + /* USB device (gadget) */ + /* TWI */ return (at91_ramsize()); } diff --git a/sys/arm/at91/board_sam9260ek.c b/sys/arm/at91/board_sam9260ek.c new file mode 100644 index 0000000..61b9cbd --- /dev/null +++ b/sys/arm/at91/board_sam9260ek.c @@ -0,0 +1,169 @@ +/*- + * Copyright (c) 2012 Marius Strobl <marius@FreeBSD.org> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +/* + * Ethernut 5 board support + */ + +#include <sys/cdefs.h> +__FBSDID("$FreeBSD$"); + +#include <sys/param.h> +#include <sys/systm.h> +#include <machine/board.h> +#include <arm/at91/at91_pioreg.h> +#include <arm/at91/at91_piovar.h> +#include <arm/at91/at91board.h> +#include <arm/at91/at91sam9260reg.h> + +BOARD_INIT long +board_init(void) +{ + + /* + * DBGU + */ + /* DRXD */ + at91_pio_use_periph_a(AT91SAM9260_PIOB_BASE, AT91C_PIO_PB14, 0); + /* DTXD */ + at91_pio_use_periph_a(AT91SAM9260_PIOB_BASE, AT91C_PIO_PB15, 1); + + /* + * EMAC + */ + /* ETX0 */ + at91_pio_use_periph_a(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA12, 0); + /* ETX1 */ + at91_pio_use_periph_a(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA13, 0); + /* ERX0 */ + at91_pio_use_periph_a(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA14, 0); + /* ERX1 */ + at91_pio_use_periph_a(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA15, 0); + /* ETXEN */ + at91_pio_use_periph_a(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA16, 0); + /* ERXDV */ + at91_pio_use_periph_a(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA17, 0); + /* ERXER */ + at91_pio_use_periph_a(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA18, 0); + /* ETXCK */ + at91_pio_use_periph_a(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA19, 0); + /* EMDC */ + at91_pio_use_periph_a(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA20, 0); + /* EMDIO */ + at91_pio_use_periph_a(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA21, 0); + /* Not RMII */ + /* ETX2 */ + at91_pio_use_periph_b(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA10, 0); + /* ETX3 */ + at91_pio_use_periph_b(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA11, 0); + /* ETXER */ + at91_pio_use_periph_b(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA22, 0); + /* ERX2 */ + at91_pio_use_periph_b(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA25, 0); + /* ERX3 */ + at91_pio_use_periph_b(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA26, 0); + /* ERXCK */ + at91_pio_use_periph_b(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA27, 0); + /* ECRS */ + at91_pio_use_periph_b(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA28, 0); + /* ECOL */ + at91_pio_use_periph_b(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA29, 0); + + + /* + * MMC, wired to socket B. + */ + /* MCDB0 */ + at91_pio_use_periph_b(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA0, 1); + /* MCCDB */ + at91_pio_use_periph_b(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA1, 1); + /* MCDB3 */ + at91_pio_use_periph_b(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA3, 1); + /* MCDB2 */ + at91_pio_use_periph_b(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA4, 1); + /* MCDB1 */ + at91_pio_use_periph_b(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA5, 1); + /* MCCK */ + at91_pio_use_periph_a(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA8, 1); + + /* + * SPI0 and MMC are wired together, since we don't support sharing + * don't support the dataflash. But if you did, you'd have to + * use CS0 and CS1. + */ + + /* + * SPI1 is wired to a audio CODEC that we don't support, so + * give it a pass. + */ + + /* + * TWI. Only one child on the iic bus, which we take care of + * via hints. + */ + /* TWD */ + at91_pio_use_periph_a(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA23, 1); + /* TWCK */ + at91_pio_use_periph_a(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA24, 1); + + /* + * USART0 + */ + /* TXD0 */ + at91_pio_use_periph_a(AT91SAM9260_PIOB_BASE, AT91C_PIO_PB4, 1); + /* RXD0 */ + at91_pio_use_periph_a(AT91SAM9260_PIOB_BASE, AT91C_PIO_PB5, 0); + /* DSR0 */ + at91_pio_use_periph_a(AT91SAM9260_PIOB_BASE, AT91C_PIO_PB22, 0); + /* DCD0 */ + at91_pio_use_periph_a(AT91SAM9260_PIOB_BASE, AT91C_PIO_PB23, 0); + /* DTR0 */ + at91_pio_use_periph_a(AT91SAM9260_PIOB_BASE, AT91C_PIO_PB24, 1); + /* RI0 */ + at91_pio_use_periph_a(AT91SAM9260_PIOB_BASE, AT91C_PIO_PB25, 0); + /* RTS0 */ + at91_pio_use_periph_a(AT91SAM9260_PIOB_BASE, AT91C_PIO_PB26, 1); + /* CTS0 */ + at91_pio_use_periph_a(AT91SAM9260_PIOB_BASE, AT91C_PIO_PB27, 0); + + /* + * USART1 + */ + /* RTS1 */ + at91_pio_use_periph_a(AT91SAM9260_PIOB_BASE, AT91C_PIO_PB28, 1); + /* CTS1 */ + at91_pio_use_periph_a(AT91SAM9260_PIOB_BASE, AT91C_PIO_PB29, 0); + /* TXD1 */ + at91_pio_use_periph_a(AT91SAM9260_PIOB_BASE, AT91C_PIO_PB6, 1); + /* RXD1 */ + at91_pio_use_periph_a(AT91SAM9260_PIOB_BASE, AT91C_PIO_PB7, 0); + + /* USART2 - USART5 aren't wired up, except via PIO pins, ignore them. */ + + return (at91_ramsize()); +} + +ARM_BOARD(AT91SAM9260EK, "Atmel SMA9260-EK") diff --git a/sys/arm/at91/board_sn9g45.c b/sys/arm/at91/board_sn9g45.c new file mode 100644 index 0000000..eb1980e --- /dev/null +++ b/sys/arm/at91/board_sn9g45.c @@ -0,0 +1,55 @@ +/*- + * Copyright (c) 2009 Greg Ansley. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +/* + * DesignA Electronics Snapper9g45 + * http://www.designa-electronics.com/ + */ + +#include <sys/cdefs.h> +__FBSDID("$FreeBSD$"); +#include <sys/param.h> +#include <sys/systm.h> + +#include <machine/board.h> +#include <arm/at91/at91board.h> +#include <arm/at91/at91reg.h> +#include <arm/at91/at91var.h> +#include <arm/at91/at91sam9g45reg.h> +#include <arm/at91/at91_piovar.h> +#include <arm/at91/at91_pio_sam9g45.h> + +BOARD_INIT long +board_init(void) +{ + + /* PIOB's A periph: Turn the debug USART's TX/RX pins */ + at91_pio_use_periph_a(AT91SAM9G45_PIOB_BASE, AT91C_PB12_DRXD, 0); + at91_pio_use_periph_a(AT91SAM9G45_PIOB_BASE, AT91C_PB13_DTXD, 1); + + return (at91_ramsize()); +} + +ARM_BOARD(SNAPPER9G45, "DesignA Electronics Snapper9G45"); diff --git a/sys/arm/at91/board_tsc4370.c b/sys/arm/at91/board_tsc4370.c index 8139a4a..7b1086b 100644 --- a/sys/arm/at91/board_tsc4370.c +++ b/sys/arm/at91/board_tsc4370.c @@ -1,6 +1,6 @@ /*- * Copyright (c) 2005-2008 Olivier Houchard. All rights reserved. - * Copyright (c) 2005-2008 Warner Losh. All rights reserved. + * Copyright (c) 2005-2012 Warner Losh. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -31,38 +31,32 @@ __FBSDID("$FreeBSD$"); #include <machine/board.h> #include <arm/at91/at91board.h> +#include <arm/at91/at91var.h> #include <arm/at91/at91rm92reg.h> +#include <arm/at91/at91rm9200var.h> #include <arm/at91/at91_piovar.h> -#include <arm/at91/at91_pio_rm9200.h> +#include <arm/at91/at91_pioreg.h> BOARD_INIT long board_init(void) { - /* - * Since the USART supports RS-485 multidrop mode, it allows the - * TX pins to float. However, for RS-232 operations, we don't want - * these pins to float. Instead, they should be pulled up to avoid - * mismatches. Linux does something similar when it configures the - * TX lines. This implies that we also allow the RX lines to float - * rather than be in the state they are left in by the boot loader. - * Since they are input pins, I think that this is the right thing - * to do. - */ - /* PIOA's A periph: Turn USART 0 and 2's TX/RX pins */ - at91_pio_use_periph_a(AT91RM92_PIOA_BASE, - AT91C_PA18_RXD0 | AT91C_PA22_RXD2, 0); - at91_pio_use_periph_a(AT91RM92_PIOA_BASE, - AT91C_PA17_TXD0 | AT91C_PA23_TXD2, 1); - /* PIOA's B periph: Turn USART 3's TX/RX pins */ - at91_pio_use_periph_b(AT91RM92_PIOA_BASE, AT91C_PA6_RXD3, 0); - at91_pio_use_periph_b(AT91RM92_PIOA_BASE, AT91C_PA5_TXD3, 1); - /* We're using TC0's A1 and A2 input */ - at91_pio_use_periph_b(AT91RM92_PIOA_BASE, - AT91C_PA19_TIOA1 | AT91C_PA21_TIOA2, 0); - /* PIOB's A periph: Turn USART 1's TX/RX pins */ - at91_pio_use_periph_a(AT91RM92_PIOB_BASE, AT91C_PB21_RXD1, 0); - at91_pio_use_periph_a(AT91RM92_PIOB_BASE, AT91C_PB20_TXD1, 1); + at91rm9200_set_subtype(AT91_ST_RM9200_PQFP); + + at91rm9200_config_uart(AT91_ID_DBGU, 0, 0); /* DBGU just Tx and Rx */ + at91rm9200_config_uart(AT91RM9200_ID_USART0, 1, 0); /* Tx and Rx */ + at91rm9200_config_uart(AT91RM9200_ID_USART1, 2, 0); /* Tx and Rx */ + at91rm9200_config_uart(AT91RM9200_ID_USART2, 3, 0); /* Tx and Rx */ + at91rm9200_config_uart(AT91RM9200_ID_USART3, 4, 0); /* Tx and Rx */ + + at91rm9200_config_mci(0); /* tsc4370 board has only 1 wire */ + /* Newer boards may have 4 wires */ + + /* Configure TWI */ + /* Configure SPI + dataflash */ + /* Configure SSC */ + /* Configure USB Host */ + /* Configure FPGA attached to chip selects */ /* Pin assignment */ /* Assert PA24 low -- talk to rubidium */ diff --git a/sys/arm/at91/files.at91 b/sys/arm/at91/files.at91 index 8e3a75d..04dfd16 100644 --- a/sys/arm/at91/files.at91 +++ b/sys/arm/at91/files.at91 @@ -22,16 +22,18 @@ arm/at91/at91_wdt.c optional at91_wdt arm/at91/if_ate.c optional ate arm/at91/if_macb.c optional macb arm/at91/uart_bus_at91usart.c optional uart -arm/at91/uart_cpu_at91rm9200usart.c optional uart +arm/at91/uart_cpu_at91usart.c optional uart arm/at91/uart_dev_at91usart.c optional uart # # All the "systems on a chip" we support # arm/at91/at91soc.c standard arm/at91/at91rm9200.c optional at91rm9200 +arm/at91/at91rm9200_devices.c optional at91rm9200 arm/at91/at91sam9260.c optional at91sam9260 arm/at91/at91sam9g20.c optional at91sam9g20 -arm/at91/at91sam9x25.c optional at91sam9x25 +arm/at91/at91sam9g45.c optional at91sam9g45 +arm/at91/at91sam9x5.c optional at91sam9x5 # # All the boards we support # @@ -41,6 +43,15 @@ arm/at91/board_hl200.c optional at91_board_hl200 arm/at91/board_hl201.c optional at91_board_hl201 arm/at91/board_kb920x.c optional at91_board_kb920x arm/at91/board_qila9g20.c optional at91_board_qila9g20 +arm/at91/board_sam9260ek.c optional at91_board_sam9260ek arm/at91/board_sam9g20ek.c optional at91_board_sam9g20ek arm/at91/board_sam9x25ek.c optional at91_board_sam9x25ek +arm/at91/board_sn9g45.c optional at91_board_sn9g45 arm/at91/board_tsc4370.c optional at91_board_tsc4370 +# +# usb +# +dev/usb/controller/at91dci.c optional at91_dci +dev/usb/controller/at91dci_atmelarm.c optional at91_dci +dev/usb/controller/ohci_atmelarm.c optional ohci +dev/usb/controller/ehci_atmelarm.c optional ehci diff --git a/sys/arm/at91/hints.at91rm9200 b/sys/arm/at91/hints.at91rm9200 deleted file mode 100644 index 4fb861f..0000000 --- a/sys/arm/at91/hints.at91rm9200 +++ /dev/null @@ -1,68 +0,0 @@ -# $FreeBSD$ -# - -# These are the wiring for the at91rm9200. These are the built-in devices -# for that cpu. - -# DBGU is unit 0 -hint.uart.0.at="apb" -hint.uart.0.maddr="0xfffff200" -hint.uart.0.flags=0x10 -# USART0 is unit 1 -hint.uart.1.at="apb" -hint.uart.1.maddr="0xfffc0000" -# USART1 is unit 2 -hint.uart.2.at="apb" -hint.uart.2.maddr="0xfffc4000" -# USART2 is unit 3 -hint.uart.3.at="apb" -hint.uart.3.maddr="0xfffc8000" -# USART3 is unit 4 -hint.uart.4.at="apb" -hint.uart.4.maddr="0xfffcc000" - -# SSC0 -hint.ssc.0.at="apb" -hint.ssc.0.maddr="0xfffd0000" -# SSC1 -hint.ssc.1.at="apb" -hint.ssc.1.maddr="0xfffd4000" -# SSC2 -hint.ssc.1.at="apb" -hint.ssc.1.maddr="0xfffd8000" - -# TC0, TC1, TC2 -hint.tc.0.at="apb" -hint.tc.0.maddr="0xfffa0000" -# TC3, TC4, TC5 -hint.tc.1.at="apb" -hint.tc.1.maddr="0xfffa4000" - -# USB Device -hint.udp.0.at="apb" -hint.udp.0.maddr="0xfffb0000" - -# MCI -hint.mci.0.at="apb" -hint.mci.0.maddr="0xfffb4000" - -# TWI -hint.twi.0.at="apb" -hint.twi.0.maddr="0xfffb8000" - -# EMAC -hint.emac.0.at="apb" -hint.emac.0.maddr="0xfffbc000" - -# SPI -hint.spi.0.at="apb" -hint.spi.0.maddr="0xfffe0000" - -# PMC -hint.pmc.0.at="apb" -hint.pmc.0.maddr="0xfffffc00" - -# USB host (ohci) -#??? maybe this needs to be on asb instead of apb -hint.ohci.at="apb" -hint.ohci.maddr="0x00300000" diff --git a/sys/arm/at91/hints.at91sam9261 b/sys/arm/at91/hints.at91sam9261 deleted file mode 100644 index b60c60e..0000000 --- a/sys/arm/at91/hints.at91sam9261 +++ /dev/null @@ -1,67 +0,0 @@ -# $FreeBSD$ -# - -# These are the wiring for the at91sam9261. These are the built-in devices -# for that cpu. - -# DBGU is unit 0 -hint.uart.0.at="apb" -hint.uart.0.maddr="0xfffff200" -hint.uart.0.flags=0x10 -# USART0 is unit 1 -hint.uart.1.at="apb" -hint.uart.1.maddr="0xfffb0000" -# USART1 is unit 2 -hint.uart.2.at="apb" -hint.uart.2.maddr="0xfffb4000" -# USART2 is unit 3 -hint.uart.3.at="apb" -hint.uart.3.maddr="0xfffb8000" -# USART3 is unit 4 -hint.uart.4.at="apb" -hint.uart.4.maddr="0xfffbc000" - -# TC0, TC1, TC2 -hint.tc.0.at="apb" -hint.tc.0.maddr="0xfffa0000" - -# USB Device -hint.udp.0.at="apb" -hint.udp.0.maddr="0xfffa4000" - -# MCI -hint.mci.0.at="apb" -hint.mci.0.maddr="0xfffa8000" - -# TWI -hint.twi.0.at="apb" -hint.twi.0.maddr="0xfffac000" - -# SSC0 -hint.ssc.0.at="apb" -hint.ssc.0.maddr="0xfffbc000" -# SSC1 -hint.ssc.1.at="apb" -hint.ssc.1.maddr="0xfffc0000" -# SSC2 -hint.ssc.1.at="apb" -hint.ssc.1.maddr="0xfffc4000" - -# SPI0 -hint.spi.0.at="apb" -hint.spi.0.maddr="0xfffc8000" -# SSC1 -hint.spi.1.at="apb" -hint.spi.1.maddr="0xfffcc000" - -# PMC -hint.pmc.0.at="apb" -hint.pmc.0.maddr="0xfffffc00" - -# USB host (ohci) -#??? maybe this needs to be on asb instead of apb -hint.ohci.at="apb" -hint.ohci.maddr="0x00500000" -# LCD controller -hint.atlcd.at="apb" -hint.atlcd.maddr="0x00600000" diff --git a/sys/arm/at91/if_ate.c b/sys/arm/at91/if_ate.c index 3d80435..58062e7 100644 --- a/sys/arm/at91/if_ate.c +++ b/sys/arm/at91/if_ate.c @@ -569,8 +569,6 @@ ate_activate(device_t dev) /* * DMA tag and map for the TX descriptors. - * XXX Old EMAC (not EMACB) doesn't really need DMA'able - * memory. We could just malloc it. gja XXX */ if (bus_dma_tag_create(bus_get_dma_tag(dev), sizeof(eth_tx_desc_t), 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, @@ -606,11 +604,10 @@ ate_activate(device_t dev) if (sc->is_emacb) { /* Write the descriptor queue address. */ WR4(sc, ETHB_TBQP, sc->tx_desc_phys); - } - /* EMACB: Enable transceiver input clock */ - if (sc->is_emacb) + /* EMACB: Enable transceiver input clock */ WR4(sc, ETHB_UIO, RD4(sc, ETHB_UIO) | ETHB_UIO_CLKE); + } return (0); @@ -676,7 +673,7 @@ ate_deactivate(struct ate_softc *sc) } if (sc->is_emacb) - WR4(sc, ETHB_UIO, RD4(sc, ETHB_UIO) & ~ETHB_UIO_CLKE); + WR4(sc, ETHB_UIO, RD4(sc, ETHB_UIO) & ~ETHB_UIO_CLKE); } /* @@ -849,12 +846,11 @@ ate_intr(void *xsc) return; if (status & ETH_ISR_RCOM) { - - bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, + bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, BUS_DMASYNC_POSTREAD); - rxdhead = &sc->rx_descs[sc->rxhead]; - while (rxdhead->addr & ETH_CPU_OWNER) { + rxdhead = &sc->rx_descs[sc->rxhead]; + while (rxdhead->addr & ETH_CPU_OWNER) { if (!sc->is_emacb) { /* * Simulate SAM9 FIRST/LAST bits for RM9200. @@ -933,7 +929,8 @@ ate_intr(void *xsc) /* XXX Performance robbing copy. Could * recieve directly to mbufs if not an - * RM9200. XXX */ + * RM9200. And even then we could likely + * copy just the protocol headers. XXX */ m_append(mb, count, sc->rx_buf[sc->rxhead]); remain -= count; } @@ -1014,6 +1011,9 @@ ate_intr(void *xsc) BARRIER(sc, ETH_CTL, 4, BUS_SPACE_BARRIER_WRITE); WR4(sc, ETH_CTL, reg | ETH_CTL_RE); } + + /* XXX need to work around SAM9260 errata 43.2.4.1: + * disable the mac, reset tx buffer, enable mac on TUND */ } /* @@ -1269,7 +1269,7 @@ atestop(struct ate_softc *sc) /* Turn off transeiver input clock */ if (sc->is_emacb) - WR4(sc, ETHB_UIO, RD4(sc, ETHB_UIO) & ~ETHB_UIO_CLKE); + WR4(sc, ETHB_UIO, RD4(sc, ETHB_UIO) & ~ETHB_UIO_CLKE); /* * XXX we should power down the EMAC if it isn't in use, after diff --git a/sys/arm/at91/std.at91sam9g45 b/sys/arm/at91/std.at91sam9g45 new file mode 100644 index 0000000..7e7c1a3 --- /dev/null +++ b/sys/arm/at91/std.at91sam9g45 @@ -0,0 +1,14 @@ +# $FreeBSD$ +# +# Unlike other Atmel SoCs, which have their SDRAM at CS1, the +# at91sam9g45 family has it on CS6, so PHYSADDR must be adjusted +# accordingly. The at91sam9g45, at91sam9g46, at91sam9m10 and at91sam9m11 +# SoCs are members of this family. + +files "../at91/files.at91" +cpu CPU_ARM9 +makeoptions CONF_CFLAGS=-mcpu=arm9 +options PHYSADDR=0x70000000 + +# bring in the sam specific timers and such +device at91sam9 diff --git a/sys/arm/at91/std.atmel b/sys/arm/at91/std.atmel index c278cf0..e707da5 100644 --- a/sys/arm/at91/std.atmel +++ b/sys/arm/at91/std.atmel @@ -9,7 +9,8 @@ options PHYSADDR=0x20000000 device at91rm9200 device at91sam9260 device at91sam9g20 -device at91sam9x25 +device at91sam9g45 +device at91sam9x5 # bring in the sam specific timers and such device at91sam9 diff --git a/sys/arm/at91/std.sam9260ek b/sys/arm/at91/std.sam9260ek new file mode 100644 index 0000000..e7d1884 --- /dev/null +++ b/sys/arm/at91/std.sam9260ek @@ -0,0 +1,11 @@ +# $FreeBSD$ +include "../at91/std.at91sam9" + +options STARTUP_PAGETABLE_ADDR=0x20800000 +makeoptions KERNPHYSADDR=0x20000000 +makeoptions KERNVIRTADDR=0xc0000000 +options KERNPHYSADDR=0x20000000 +options KERNVIRTADDR=0xc0000000 + +device at91_board_sam9260ek +device at91sam9260 diff --git a/sys/arm/at91/std.sam9x25ek b/sys/arm/at91/std.sam9x25ek index 32b1f3b..661213b 100644 --- a/sys/arm/at91/std.sam9x25ek +++ b/sys/arm/at91/std.sam9x25ek @@ -8,4 +8,4 @@ options KERNPHYSADDR=0x20000000 options KERNVIRTADDR=0xc0000000 device at91_board_sam9x25ek -device at91sam9x25 +device at91sam9x5 diff --git a/sys/arm/at91/std.sn9g45 b/sys/arm/at91/std.sn9g45 new file mode 100644 index 0000000..e0d7c98 --- /dev/null +++ b/sys/arm/at91/std.sn9g45 @@ -0,0 +1,12 @@ +#$FreeBSD$ +include "../at91/std.at91sam9g45" + +options STARTUP_PAGETABLE_ADDR=0x70800000 +makeoptions KERNPHYSADDR=0x70008000 +options KERNPHYSADDR=0x70008000 +makeoptions KERNVIRTADDR=0xc0008000 +options KERNVIRTADDR=0xc0008000 + +device at91sam9g45 +device at91_board_sn9g45 + diff --git a/sys/arm/at91/uart_bus_at91usart.c b/sys/arm/at91/uart_bus_at91usart.c index b042537..98cde1d 100644 --- a/sys/arm/at91/uart_bus_at91usart.c +++ b/sys/arm/at91/uart_bus_at91usart.c @@ -95,6 +95,12 @@ usart_at91_probe(device_t dev) case 4: device_set_desc(dev, "USART3"); break; + case 5: + device_set_desc(dev, "USART4"); + break; + case 6: + device_set_desc(dev, "USART5"); + break; } sc->sc_class = &at91_usart_class; if (sc->sc_class->uc_rclk == 0) diff --git a/sys/arm/at91/uart_cpu_at91rm9200usart.c b/sys/arm/at91/uart_cpu_at91usart.c index cb39bf9..33b5621 100644 --- a/sys/arm/at91/uart_cpu_at91rm9200usart.c +++ b/sys/arm/at91/uart_cpu_at91usart.c @@ -43,7 +43,6 @@ __FBSDID("$FreeBSD$"); #include <dev/uart/uart_bus.h> #include <dev/uart/uart_cpu.h> -#include <arm/at91/at91rm92reg.h> #include <arm/at91/at91var.h> bus_space_tag_t uart_bus_space_io; @@ -71,9 +70,10 @@ uart_cpu_getdev(int devtype, struct uart_devinfo *di) di->bas.bst = &at91_bs_tag; /* * XXX: Not pretty, but will work because we map the needed addresses - * early. + * early. At least we probed this so that the console will work on + * all flavors of Atmel we can detect. */ - di->bas.bsh = AT91_BASE + AT91RM92_DBGU_BASE; + di->bas.bsh = soc_info.dbgu_base; di->baudrate = 115200; di->bas.regshft = 0; di->bas.rclk = 0; |
