diff options
Diffstat (limited to 'sys/arm/at91/at91sam9g20reg.h')
| -rw-r--r-- | sys/arm/at91/at91sam9g20reg.h | 131 |
1 files changed, 94 insertions, 37 deletions
diff --git a/sys/arm/at91/at91sam9g20reg.h b/sys/arm/at91/at91sam9g20reg.h index 9194b11..71683e9 100644 --- a/sys/arm/at91/at91sam9g20reg.h +++ b/sys/arm/at91/at91sam9g20reg.h @@ -1,5 +1,6 @@ /*- * Copyright (c) 2009 Sylvestre Gallon. All rights reserved. + * Copyright (c) 2010 Greg Ansley. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -28,6 +29,29 @@ #ifndef AT91SAM9G20REG_H_ #define AT91SAM9G20REG_H_ +#ifndef AT91SAM9G20_MASTER_CLOCK +#define AT91SAM9G20_MASTER_CLOCK ((18432000 * 43)/6) +#endif + +/* Chip Specific limits */ +#define SAM9G20_PLL_A_MIN_IN_FREQ 2000000 /* 2 Mhz */ +#define SAM9G20_PLL_A_MAX_IN_FREQ 32000000 /* 32 Mhz */ +#define SAM9G20_PLL_A_MIN_OUT_FREQ 400000000 /* 400 Mhz */ +#define SAM9G20_PLL_A_MAX_OUT_FREQ 800000000 /* 800 Mhz */ +#define SAM9G20_PLL_A_MUL_SHIFT 16 +#define SAM9G20_PLL_A_MUL_MASK 0xFF +#define SAM9G20_PLL_A_DIV_SHIFT 0 +#define SAM9G20_PLL_A_DIV_MASK 0xFF + +#define SAM9G20_PLL_B_MIN_IN_FREQ 2000000 /* 2 Mhz */ +#define SAM9G20_PLL_B_MAX_IN_FREQ 32000000 /* 32 Mhz */ +#define SAM9G20_PLL_B_MIN_OUT_FREQ 30000000 /* 30 Mhz */ +#define SAM9G20_PLL_B_MAX_OUT_FREQ 100000000 /* 100 Mhz */ +#define SAM9G20_PLL_B_MUL_SHIFT 16 +#define SAM9G20_PLL_B_MUL_MASK 0x3F +#define SAM9G20_PLL_B_DIV_SHIFT 0 +#define SAM9G20_PLL_B_DIV_MASK 0xFF + /* * Memory map, from datasheet : * 0x00000000 - 0x0ffffffff : Internal Memories @@ -56,11 +80,11 @@ #define AT91SAM9G20_BASE 0xd0000000 -#define AT91SAM9G20_IRQ_EMAC 21 #define AT91SAM9G20_EMAC_BASE 0xffc4000 #define AT91SAM9G20_EMAC_SIZE 0x4000 #define AT91SAM9G20_RSTC_BASE 0xffffd00 +#define AT91SAM9G20_RSTC_SIZE 0x10 #define RSTC_CR 0 #define RSTC_PROCRST (1 << 0) @@ -69,13 +93,25 @@ /* USART*/ +#define AT91SAM9G20_USART_SIZE 0x4000 #define AT91SAM9G20_USART0_BASE 0xffb0000 #define AT91SAM9G20_USART0_PDC 0xffb0100 +#define AT91SAM9G20_USART0_SIZE AT91SAM9G20_USART_SIZE #define AT91SAM9G20_USART1_BASE 0xffb4000 #define AT91SAM9G20_USART1_PDC 0xffb4100 +#define AT91SAM9G20_USART1_SIZE AT91SAM9G20_USART_SIZE #define AT91SAM9G20_USART2_BASE 0xffb8000 #define AT91SAM9G20_USART2_PDC 0xffb8100 -#define AT91SAM9G20_USART_SIZE 0x4000 +#define AT91SAM9G20_USART2_SIZE AT91SAM9G20_USART_SIZE +#define AT91SAM9G20_USART3_BASE 0xffd0000 +#define AT91SAM9G20_USART3_PDC 0xffd0100 +#define AT91SAM9G20_USART3_SIZE AT91SAM9G20_USART_SIZE +#define AT91SAM9G20_USART4_BASE 0xffd4000 +#define AT91SAM9G20_USART4_PDC 0xffd4100 +#define AT91SAM9G20_USART4_SIZE AT91SAM9G20_USART_SIZE +#define AT91SAM9G20_USART5_BASE 0xffd8000 +#define AT91SAM9G20_USART5_PDC 0xffd8100 +#define AT91SAM9G20_USART5_SIZE AT91SAM9G20_USART_SIZE /*TC*/ #define AT91SAM9G20_TC0_BASE 0xffa0000 @@ -99,28 +135,27 @@ #define AT91SAM9G20_IRQ_SPI1 13 /* System Registers */ -#define AT91SAM9G20_SYS_BASE 0xfffe000 -#define AT91SAM9G20_SYS_SIZE 0x2000 - -#define AT91SAM9G20_MATRIX (0xe00) +#define AT91SAM9G20_SYS_BASE 0xffff000 +#define AT91SAM9G20_SYS_SIZE 0x1000 -#define AT91SAM9G20_EBICSA (AT91SAM9G20_MATRIX + 0x011C) +#define AT91SAM9G20_MATRIX_BASE 0xfffee00 +#define AT91SAM9G20_MATRIX_SIZE 0x1000 +#define AT91SAM9G20_EBICSA 0x011C #define AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA (1 << 3) -#define DBGU 0x200 -#define DBGU_SIZE 0x200 -#define DBGU_C1R (0x200 + 64) /* Chip ID1 Register */ -#define DBGU_C2R (0x200 + 68) /* Chip ID2 Register */ -#define DBGU_FNTR (0x200 + 72) /* Force NTRST Register */ +#define AT91SAM9G20_DBGU_BASE 0xffff200 +#define AT91SAM9G20_DBGU_SIZE 0x200 /* * PIO */ #define AT91SAM9G20_PIOA_BASE 0xffff400 -#define AT91SAM9G20_PIO_SIZE 0x200 +#define AT91SAM9G20_PIOA_SIZE 0x200 #define AT91SAM9G20_PIOB_BASE 0xffff600 +#define AT91SAM9G20_PIOB_SIZE 0x200 #define AT91SAM9G20_PIOC_BASE 0xffff800 +#define AT91SAM9G20_PIOC_SIZE 0x200 #define AT91RM92_PMC_BASE 0xffffc00 #define AT91RM92_PMC_SIZE 0x100 @@ -131,27 +166,33 @@ * 2: PIO Controller A * 3: PIO Controller B * 4: PIO Controller C - * 5: - + * 5: ADC * 6: USART 0 * 7: USART 1 * 8: USART 2 * 9: MMC Interface * 10: USB device port * 11: Two-wirte interface - * 12: SPI - * 13: SPI + * 12: SPI 0 + * 13: SPI 1 * 14: SSC - * 15: SSC - * 16: SSC + * 15: - (reserved) + * 16: - (reserved) * 17: Timer Counter 0 * 18: Timer Counter 1 * 19: Timer Counter 2 * 20: USB Host port * 21: EMAC - * 22-28: - - * 29: AIC - * 30: AIC - * 31: AIC + * 22: ISI + * 23: USART 3 + * 24: USART 4 + * 25: USART 2 + * 26: Timer Counter 3 + * 27: Timer Counter 4 + * 28: Timer Counter 5 + * 29: AIC IRQ0 + * 30: AIC IRQ1 + * 31: AIC IRQ2 */ #define AT91SAM9G20_IRQ_SYSTEM 1 @@ -173,12 +214,25 @@ #define AT91SAM9G20_IRQ_TC1 18 #define AT91SAM9G20_IRQ_TC2 19 #define AT91SAM9G20_IRQ_UHP 20 +#define AT91SAM9G20_IRQ_EMAC 21 +#define AT91SAM9G20_IRQ_USART3 23 +#define AT91SAM9G20_IRQ_USART4 24 +#define AT91SAM9G20_IRQ_USART5 25 #define AT91SAM9G20_IRQ_AICBASE 29 -/* Timer */ +/* Alias */ +#define AT91SAM9G20_IRQ_DBGU AT91SAM9G20_IRQ_SYSTEM +#define AT91SAM9G20_IRQ_PMC AT91SAM9G20_IRQ_SYSTEM +#define AT91SAM9G20_IRQ_WDT AT91SAM9G20_IRQ_SYSTEM +#define AT91SAM9G20_IRQ_PIT AT91SAM9G20_IRQ_SYSTEM +#define AT91SAM9G20_IRQ_RSTC AT91SAM9G20_IRQ_SYSTEM +#define AT91SAM9G20_IRQ_OHCI AT91SAM9G20_IRQ_UHP +#define AT91SAM9G20_IRQ_NAND (-1) -#define AT91SAM9G20_DBGU_BASE 0xffff200 -#define AT91SAM9G20_DBGU_SIZE 0x200 +#define AT91SAM9G20_AIC_BASE 0xffff000 +#define AT91SAM9G20_AIC_SIZE 0x200 + +/* Timer */ #define AT91SAM9G20_WDT_BASE 0xffffd40 #define AT91SAM9G20_WDT_SIZE 0x10 @@ -195,22 +249,24 @@ #define AT91SAM9G20_UDP_BASE 0xffa4000 #define AT91SAM9G20_UDP_SIZE 0x4000 -#define AT91SAM9G20_OHCI_BASE 0xdfe00000 -#define AT91SAM9G20_OHCI_PA_BASE 0x00500000 -#define AT91SAM9G20_OHCI_SIZE 0x00100000 +#define AT91SAM9G20_MCI_BASE 0xffa8000 +#define AT91SAM9G20_MCI_SIZE 0x4000 +#define AT91SAM9G20_TWI_BASE 0xffaC000 +#define AT91SAM9G20_TWI_SIZE 0x4000 -//#define AT91SAM9G20_NAND_BASE 0xdf100000 - -//#define AT91SAM9G20_NAND_BASE 0x40000000 - -#define AT91SAM9G20_NAND_BASE 0xe0000000 +/* XXX Needs to be carfully coordinated with + * other * soc's so phyical and vm address + * mapping are unique. XXX + */ +#define AT91SAM9G20_OHCI_BASE 0xdfc00000 +#define AT91SAM9G20_OHCI_PA_BASE 0x00500000 +#define AT91SAM9G20_OHCI_SIZE 0x00100000 -#define AT91SAM9G20_NAND_PA_BASE 0x40000000 -#define AT91SAM9G20_NAND_SIZE 0x10000000 -//#define AT91SAM9G20_NAND_SIZE 0x00900000 +#define AT91SAM9G20_NAND_BASE 0xe0000000 +#define AT91SAM9G20_NAND_PA_BASE 0x40000000 +#define AT91SAM9G20_NAND_SIZE 0x10000000 -//#define AT91SAM9G20_OHCI_SIZE 0x0004000 /* SDRAMC */ #define AT91SAM9G20_SDRAMC_BASE 0xfffea00 @@ -234,6 +290,7 @@ #define AT91SAM9G20_SDRAMC_CR_NR_MASK 0x0000000c #define AT91SAM9G20_SDRAMC_CR_NB_2 0x00 #define AT91SAM9G20_SDRAMC_CR_NB_4 0x10 +#define AT91SAM9G20_SDRAMC_CR_DBW_16 0x80 #define AT91SAM9G20_SDRAMC_CR_NB_MASK 0x00000010 #define AT91SAM9G20_SDRAMC_CR_NCAS_MASK 0x00000060 #define AT91SAM9G20_SDRAMC_CR_TWR_MASK 0x00000780 |
