diff options
Diffstat (limited to 'sys/arm/arm')
| -rw-r--r-- | sys/arm/arm/cpufunc.c | 114 | ||||
| -rw-r--r-- | sys/arm/arm/cpufunc_asm_pj4b.S | 132 | ||||
| -rw-r--r-- | sys/arm/arm/identcpu.c | 8 | ||||
| -rw-r--r-- | sys/arm/arm/locore.S | 4 | ||||
| -rw-r--r-- | sys/arm/arm/mp_machdep.c | 8 |
5 files changed, 8 insertions, 258 deletions
diff --git a/sys/arm/arm/cpufunc.c b/sys/arm/arm/cpufunc.c index 11c3e5e..d69f2f1 100644 --- a/sys/arm/arm/cpufunc.c +++ b/sys/arm/arm/cpufunc.c @@ -541,65 +541,6 @@ struct cpu_functions pj4bv7_cpufuncs = { pj4bv7_setup /* cpu setup */ }; - -struct cpu_functions pj4bv6_cpufuncs = { - /* CPU functions */ - - cpufunc_id, /* id */ - arm11_drain_writebuf, /* cpwait */ - - /* MMU functions */ - - cpufunc_control, /* control */ - cpufunc_domains, /* Domain */ - pj4b_setttb, /* Setttb */ - cpufunc_faultstatus, /* Faultstatus */ - cpufunc_faultaddress, /* Faultaddress */ - - /* TLB functions */ - - arm11_tlb_flushID, /* tlb_flushID */ - arm11_tlb_flushID_SE, /* tlb_flushID_SE */ - arm11_tlb_flushI, /* tlb_flushI */ - arm11_tlb_flushI_SE, /* tlb_flushI_SE */ - arm11_tlb_flushD, /* tlb_flushD */ - arm11_tlb_flushD_SE, /* tlb_flushD_SE */ - - /* Cache operations */ - armv6_icache_sync_all, /* icache_sync_all */ - pj4b_icache_sync_range, /* icache_sync_range */ - - armv6_dcache_wbinv_all, /* dcache_wbinv_all */ - pj4b_dcache_wbinv_range, /* dcache_wbinv_range */ - pj4b_dcache_inv_range, /* dcache_inv_range */ - pj4b_dcache_wb_range, /* dcache_wb_range */ - - armv6_idcache_wbinv_all, /* idcache_wbinv_all */ - pj4b_idcache_wbinv_range, /* idcache_wbinv_all */ - - (void *)cpufunc_nullop, /* l2cache_wbinv_all */ - (void *)cpufunc_nullop, /* l2cache_wbinv_range */ - (void *)cpufunc_nullop, /* l2cache_inv_range */ - (void *)cpufunc_nullop, /* l2cache_wb_range */ - - /* Other functions */ - - pj4b_drain_readbuf, /* flush_prefetchbuf */ - arm11_drain_writebuf, /* drain_writebuf */ - pj4b_flush_brnchtgt_all, /* flush_brnchtgt_C */ - pj4b_flush_brnchtgt_va, /* flush_brnchtgt_E */ - - (void *)cpufunc_nullop, /* sleep */ - - /* Soft functions */ - - cpufunc_null_fixup, /* dataabt_fixup */ - cpufunc_null_fixup, /* prefetchabt_fixup */ - - arm11_context_switch, /* context_switch */ - - pj4bv6_setup /* cpu setup */ -}; #endif /* CPU_MV_PJ4B */ #ifdef CPU_SA110 @@ -1496,27 +1437,14 @@ set_cpufuncs() #endif /* CPU_CORTEXA */ #if defined(CPU_MV_PJ4B) - if (cputype == CPU_ID_MV88SV581X_V6 || - cputype == CPU_ID_MV88SV581X_V7 || + if (cputype == CPU_ID_MV88SV581X_V7 || cputype == CPU_ID_MV88SV584X_V7 || - cputype == CPU_ID_ARM_88SV581X_V6 || cputype == CPU_ID_ARM_88SV581X_V7) { - if (cpu_pfr(0) & ARM_PFR0_THUMBEE_MASK) - cpufuncs = pj4bv7_cpufuncs; - else - cpufuncs = pj4bv6_cpufuncs; - - get_cachetype_cp15(); - pmap_pte_init_mmu_v6(); - goto out; - } else if (cputype == CPU_ID_ARM_88SV584X_V6 || - cputype == CPU_ID_MV88SV584X_V6) { - cpufuncs = pj4bv6_cpufuncs; + cpufuncs = pj4bv7_cpufuncs; get_cachetype_cp15(); pmap_pte_init_mmu_v6(); goto out; } - #endif /* CPU_MV_PJ4B */ #ifdef CPU_SA110 if (cputype == CPU_ID_SA110) { @@ -2446,44 +2374,6 @@ arm11x6_setup(char *args) #ifdef CPU_MV_PJ4B void -pj4bv6_setup(char *args) -{ - int cpuctrl; - - pj4b_config(); - - cpuctrl = CPU_CONTROL_MMU_ENABLE; -#ifndef ARM32_DISABLE_ALIGNMENT_FAULTS - cpuctrl |= CPU_CONTROL_AFLT_ENABLE; -#endif - cpuctrl |= CPU_CONTROL_DC_ENABLE; - cpuctrl |= (0xf << 3); -#ifdef __ARMEB__ - cpuctrl |= CPU_CONTROL_BEND_ENABLE; -#endif - cpuctrl |= CPU_CONTROL_SYST_ENABLE; - cpuctrl |= CPU_CONTROL_BPRD_ENABLE; - cpuctrl |= CPU_CONTROL_IC_ENABLE; - if (vector_page == ARM_VECTORS_HIGH) - cpuctrl |= CPU_CONTROL_VECRELOC; - cpuctrl |= (0x5 << 16); - cpuctrl |= CPU_CONTROL_V6_EXTPAGE; - /* XXX not yet */ - /* cpuctrl |= CPU_CONTROL_L2_ENABLE; */ - - /* Make sure caches are clean. */ - cpu_idcache_wbinv_all(); - cpu_l2cache_wbinv_all(); - - /* Set the control register */ - ctrl = cpuctrl; - cpu_control(0xffffffff, cpuctrl); - - cpu_idcache_wbinv_all(); - cpu_l2cache_wbinv_all(); -} - -void pj4bv7_setup(args) char *args; { diff --git a/sys/arm/arm/cpufunc_asm_pj4b.S b/sys/arm/arm/cpufunc_asm_pj4b.S index e6182fb..d8d400c 100644 --- a/sys/arm/arm/cpufunc_asm_pj4b.S +++ b/sys/arm/arm/cpufunc_asm_pj4b.S @@ -34,9 +34,6 @@ __FBSDID("$FreeBSD$"); #include <machine/param.h> -.Lpj4b_cache_line_size: - .word _C_LABEL(arm_pdcache_line_size) - .Lpj4b_sf_ctrl_reg: .word 0xf1021820 @@ -52,135 +49,6 @@ ENTRY(pj4b_setttb) RET END(pj4b_setttb) -ENTRY_NP(armv6_icache_sync_all) - /* - * We assume that the code here can never be out of sync with the - * dcache, so that we can safely flush the Icache and fall through - * into the Dcache cleaning code. - */ - mov r0, #0 - mcr p15, 0, r0, c7, c5, 0 /* Invalidate ICache */ - mcr p15, 0, r0, c7, c10, 0 /* Clean (don't invalidate) DCache */ - mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ - RET -END(armv6_icache_sync_all) - -ENTRY(pj4b_icache_sync_range) - sub r1, r1, #1 - add r1, r0, r1 - mcrr p15, 0, r1, r0, c5 /* invalidate IC range */ - mcrr p15, 0, r1, r0, c12 /* clean DC range */ - mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ - RET -END(pj4b_icache_sync_range) - -ENTRY(pj4b_dcache_inv_range) - ldr ip, .Lpj4b_cache_line_size - ldr ip, [ip] - sub r1, r1, #1 /* Don't overrun */ - sub r3, ip, #1 - and r2, r0, r3 - add r1, r1, r2 - bic r0, r0, r3 - - mcr p15, 0, r0, c7, c10, 5 /* Data Memory Barrier err:4413 */ -1: - mcr p15, 0, r0, c7, c6, 1 - add r0, r0, ip - subs r1, r1, ip - bpl 1b - mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ - RET -END(pj4b_dcache_inv_range) - -ENTRY(armv6_idcache_wbinv_all) - mov r0, #0 - mcr p15, 0, r0, c7, c5, 0 /* invalidate ICache */ - mcr p15, 0, r0, c7, c14, 0 /* clean and invalidate DCache */ - mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ - RET -END(armv6_idcache_wbinv_all) - -ENTRY(armv6_dcache_wbinv_all) - mov r0, #0 - mcr p15, 0, r0, c7, c14, 0 /* clean and invalidate DCache */ - mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ - RET -END(armv6_dcache_wbinv_all) - -ENTRY(pj4b_idcache_wbinv_range) - ldr ip, .Lpj4b_cache_line_size - ldr ip, [ip] - sub r1, r1, #1 /* Don't overrun */ - sub r3, ip, #1 - and r2, r0, r3 - add r1, r1, r2 - bic r0, r0, r3 - - mcr p15, 0, r0, c7, c10, 5 /* Data Memory Barrier err:4611 */ -1: -#ifdef SMP - /* Request for ownership */ - ldr r2, [r0] - str r2, [r0] -#endif - mcr p15, 0, r0, c7, c5, 1 - mcr p15, 0, r0, c7, c14, 1 /* L2C clean and invalidate entry */ - add r0, r0, ip - subs r1, r1, ip - bpl 1b - mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ - RET -END(pj4b_idcache_wbinv_range) - -ENTRY(pj4b_dcache_wbinv_range) - ldr ip, .Lpj4b_cache_line_size - ldr ip, [ip] - sub r1, r1, #1 /* Don't overrun */ - sub r3, ip, #1 - and r2, r0, r3 - add r1, r1, r2 - bic r0, r0, r3 - - mcr p15, 0, r0, c7, c10, 5 /* Data Memory Barrier err:4611 */ -1: -#ifdef SMP - /* Request for ownership */ - ldr r2, [r0] - str r2, [r0] -#endif - mcr p15, 0, r0, c7, c14, 1 - add r0, r0, ip - subs r1, r1, ip - bpl 1b - mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ - RET -END(pj4b_dcache_wbinv_range) - -ENTRY(pj4b_dcache_wb_range) - ldr ip, .Lpj4b_cache_line_size - ldr ip, [ip] - sub r1, r1, #1 /* Don't overrun */ - sub r3, ip, #1 - and r2, r0, r3 - add r1, r1, r2 - bic r0, r0, r3 - - mcr p15, 0, r0, c7, c10, 5 /* Data Memory Barrier err:4611 */ -1: -#ifdef SMP - /* Request for ownership */ - ldr r2, [r0] - str r2, [r0] -#endif - mcr p15, 0, r0, c7, c10, 1 /* L2C clean single entry by MVA */ - add r0, r0, ip - subs r1, r1, ip - bpl 1b - mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ - RET -END(pj4b_dcache_wb_range) - ENTRY(pj4b_drain_readbuf) mcr p15, 0, r0, c7, c5, 4 /* flush prefetch buffers */ RET diff --git a/sys/arm/arm/identcpu.c b/sys/arm/arm/identcpu.c index fd32666..f3870dd 100644 --- a/sys/arm/arm/identcpu.c +++ b/sys/arm/arm/identcpu.c @@ -321,18 +321,10 @@ const struct cpuidtab cpuids[] = { { CPU_ID_MV88FR571_VD, CPU_CLASS_MARVELL, "Feroceon 88FR571-VD", generic_steppings }, - { CPU_ID_MV88SV581X_V6, CPU_CLASS_MARVELL, "Sheeva 88SV581x", - generic_steppings }, - { CPU_ID_ARM_88SV581X_V6, CPU_CLASS_MARVELL, "Sheeva 88SV581x", - generic_steppings }, { CPU_ID_MV88SV581X_V7, CPU_CLASS_MARVELL, "Sheeva 88SV581x", generic_steppings }, { CPU_ID_ARM_88SV581X_V7, CPU_CLASS_MARVELL, "Sheeva 88SV581x", generic_steppings }, - { CPU_ID_MV88SV584X_V6, CPU_CLASS_MARVELL, "Sheeva 88SV584x", - generic_steppings }, - { CPU_ID_ARM_88SV584X_V6, CPU_CLASS_MARVELL, "Sheeva 88SV584x", - generic_steppings }, { CPU_ID_MV88SV584X_V7, CPU_CLASS_MARVELL, "Sheeva 88SV584x", generic_steppings }, diff --git a/sys/arm/arm/locore.S b/sys/arm/arm/locore.S index ecd7f53..678f3bf 100644 --- a/sys/arm/arm/locore.S +++ b/sys/arm/arm/locore.S @@ -266,10 +266,6 @@ mmu_init_table: /* map VA 0xc0000000..0xc3ffffff to PA */ MMU_INIT(KERNBASE, PHYSADDR, 64, L1_TYPE_S|L1_SHARED|L1_S_C|L1_S_AP(AP_KRW)) MMU_INIT(0x48000000, 0x48000000, 1, L1_TYPE_S|L1_SHARED|L1_S_C|L1_S_AP(AP_KRW)) -#if defined(CPU_MV_PJ4B) - /* map VA 0xf1000000..0xf1100000 to PA 0xd0000000 */ - MMU_INIT(0xf1000000, 0xd0000000, 1, L1_TYPE_S|L1_SHARED|L1_S_B|L1_S_AP(AP_KRW)) -#endif /* CPU_MV_PJ4B */ #endif /* SMP */ .word 0 /* end of table */ #endif diff --git a/sys/arm/arm/mp_machdep.c b/sys/arm/arm/mp_machdep.c index cebbd72..ff6b665 100644 --- a/sys/arm/arm/mp_machdep.c +++ b/sys/arm/arm/mp_machdep.c @@ -52,6 +52,10 @@ __FBSDID("$FreeBSD$"); #ifdef VFP #include <machine/vfp.h> #endif +#ifdef CPU_MV_PJ4B +#include <arm/mv/mvwin.h> +#include <dev/fdt/fdt_common.h> +#endif #include "opt_smp.h" @@ -131,8 +135,8 @@ cpu_mp_start(void) #if defined(CPU_MV_PJ4B) /* Add ARMADAXP registers required for snoop filter initialization */ - ((int *)(temp_pagetable_va))[0xf1000000 >> L1_S_SHIFT] = - L1_TYPE_S|L1_SHARED|L1_S_B|L1_S_AP(AP_KRW)|0xd0000000; + ((int *)(temp_pagetable_va))[MV_BASE >> L1_S_SHIFT] = + L1_TYPE_S|L1_SHARED|L1_S_B|L1_S_AP(AP_KRW)|fdt_immr_pa; #endif temp_pagetable = (void*)(vtophys(temp_pagetable_va)); |
