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-rw-r--r--sys/arm/arm/cpufunc_asm_armv7.S8
1 files changed, 4 insertions, 4 deletions
diff --git a/sys/arm/arm/cpufunc_asm_armv7.S b/sys/arm/arm/cpufunc_asm_armv7.S
index dee9a9a..25f052f 100644
--- a/sys/arm/arm/cpufunc_asm_armv7.S
+++ b/sys/arm/arm/cpufunc_asm_armv7.S
@@ -247,8 +247,8 @@ ENTRY(armv7_idcache_wbinv_range)
add r0, r0, ip
subs r1, r1, ip
bhi .Larmv7_id_wbinv_next
- isb /* instruction synchronization barrier */
dsb /* data synchronization barrier */
+ isb /* instruction synchronization barrier */
RET
END(armv7_idcache_wbinv_range)
@@ -258,8 +258,8 @@ ENTRY_NP(armv7_icache_sync_all)
#else
mcr CP15_ICIALLU
#endif
- isb /* instruction synchronization barrier */
dsb /* data synchronization barrier */
+ isb /* instruction synchronization barrier */
RET
END(armv7_icache_sync_all)
@@ -267,13 +267,13 @@ ENTRY_NP(armv7_icache_sync_range)
ldr ip, .Larmv7_icache_line_size
ldr ip, [ip]
.Larmv7_sync_next:
- mcr CP15_ICIMVAU(r0)
mcr CP15_DCCMVAC(r0)
+ mcr CP15_ICIMVAU(r0)
add r0, r0, ip
subs r1, r1, ip
bhi .Larmv7_sync_next
- isb /* instruction synchronization barrier */
dsb /* data synchronization barrier */
+ isb /* instruction synchronization barrier */
RET
END(armv7_icache_sync_range)
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