diff options
Diffstat (limited to 'lib/libpmc/pmc.core.3')
| -rw-r--r-- | lib/libpmc/pmc.core.3 | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/lib/libpmc/pmc.core.3 b/lib/libpmc/pmc.core.3 index ce085ca..3c97e09 100644 --- a/lib/libpmc/pmc.core.3 +++ b/lib/libpmc/pmc.core.3 @@ -85,13 +85,13 @@ Configure the PMC to increment only if the number of configured events measured in a cycle is greater than or equal to .Ar value . .It Li edge -Configure the PMC to count the number of deasserted to asserted +Configure the PMC to count the number of de-asserted to asserted transitions of the conditions expressed by the other qualifiers. If specified, the counter will increment only once whenever a condition becomes true, irrespective of the number of clocks during which the condition remains true. .It Li inv -Invert the sense of comparision when the +Invert the sense of comparison when the .Dq Li cmask qualifier is present, making the counter increment when the number of events per cycle is less than the value specified by the @@ -159,7 +159,7 @@ The default is .Dq Li both . .Pp Events that require a cache coherence qualifier to be specified use an -additional qualifer +additional qualifier .Dq Li cachestate= Ns Ar value , where argument .Ar value @@ -348,8 +348,8 @@ The number of completed partial write transactions. The number of completed read-for-ownership transactions. .It Li Bus_Trans_WB Op ,agent= Ns Ar agent .Pq Event 67H -The number of completed writeback transactions from the data cache -unit, excluding L2 writebacks. +The number of completed write-back transactions from the data cache +unit, excluding L2 write-backs. .It Li Cycles_Div_Busy .Pq Event 14H , Umask 00H The number of cycles the divider is busy. @@ -393,13 +393,13 @@ The number of cacheable read and write operations to L1 data cache. .It Li Data_Mem_Ref .Pq Event 43H , Umask 01H The number of L1 data reads and writes, both cacheable and -uncacheable. +un-cacheable. .It Li Dbus_Busy Op ,core= Ns Ar core .Pq Event 22H The number of core cycles during which the data bus was busy. .It Li Dbus_Busy_Rd Op ,core= Ns Ar core .Pq Event 23H -The nunber of cycles during which the data bus was busy transferring +The number of cycles during which the data bus was busy transferring data to a core. .It Li Div .Pq Event 13H , Umask 00H @@ -460,7 +460,7 @@ streaming buffers. .It Li ICache_Reads .Pq Event 80H , Umask 00H The number of instruction fetches from the the instruction cache and -streaming buffers counting both cacheable and uncacheable fetches. +streaming buffers counting both cacheable and un-cacheable fetches. .It Li IFU_Mem_Stall .Pq Event 86H , Umask 00H The number of cycles the instruction fetch unit was stalled while @@ -754,7 +754,7 @@ Performance monitoring events for retired floating point operations .It AE29 DR3 address match on MOVD/MOVQ/MOVNTQ memory store instruction may incorrectly increment performance monitoring count -for saturating simd instructions retired (Event CFH). +for saturating SIMD instructions retired (Event CFH). .It AE33 Hardware prefetch performance monitoring events may be counted inaccurately. |
