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-rw-r--r--lib/libpmc/libpmc.c96
1 files changed, 88 insertions, 8 deletions
diff --git a/lib/libpmc/libpmc.c b/lib/libpmc/libpmc.c
index 3b7dc37..85c460d 100644
--- a/lib/libpmc/libpmc.c
+++ b/lib/libpmc/libpmc.c
@@ -183,11 +183,21 @@ static const struct pmc_event_descr corei7_event_table[] =
__PMC_EV_ALIAS_COREI7()
};
+static const struct pmc_event_descr ivybridge_event_table[] =
+{
+ __PMC_EV_ALIAS_IVYBRIDGE()
+};
+
static const struct pmc_event_descr sandybridge_event_table[] =
{
__PMC_EV_ALIAS_SANDYBRIDGE()
};
+static const struct pmc_event_descr sandybridge_xeon_event_table[] =
+{
+ __PMC_EV_ALIAS_SANDYBRIDGE_XEON()
+};
+
static const struct pmc_event_descr westmere_event_table[] =
{
__PMC_EV_ALIAS_WESTMERE()
@@ -222,7 +232,9 @@ PMC_MDEP_TABLE(atom, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC);
PMC_MDEP_TABLE(core, IAP, PMC_CLASS_SOFT, PMC_CLASS_TSC);
PMC_MDEP_TABLE(core2, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC);
PMC_MDEP_TABLE(corei7, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP);
+PMC_MDEP_TABLE(ivybridge, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC);
PMC_MDEP_TABLE(sandybridge, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP);
+PMC_MDEP_TABLE(sandybridge_xeon, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC);
PMC_MDEP_TABLE(westmere, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP);
PMC_MDEP_TABLE(k7, K7, PMC_CLASS_SOFT, PMC_CLASS_TSC);
PMC_MDEP_TABLE(k8, K8, PMC_CLASS_SOFT, PMC_CLASS_TSC);
@@ -259,7 +271,9 @@ PMC_CLASS_TABLE_DESC(atom, IAP, atom, iap);
PMC_CLASS_TABLE_DESC(core, IAP, core, iap);
PMC_CLASS_TABLE_DESC(core2, IAP, core2, iap);
PMC_CLASS_TABLE_DESC(corei7, IAP, corei7, iap);
+PMC_CLASS_TABLE_DESC(ivybridge, IAP, ivybridge, iap);
PMC_CLASS_TABLE_DESC(sandybridge, IAP, sandybridge, iap);
+PMC_CLASS_TABLE_DESC(sandybridge_xeon, IAP, sandybridge_xeon, iap);
PMC_CLASS_TABLE_DESC(westmere, IAP, westmere, iap);
PMC_CLASS_TABLE_DESC(ucf, UCF, ucf, ucf);
PMC_CLASS_TABLE_DESC(corei7uc, UCP, corei7uc, ucp);
@@ -365,14 +379,14 @@ static struct pmc_op_getdyneventinfo soft_event_info;
/* Event masks for events */
struct pmc_masks {
const char *pm_name;
- const uint32_t pm_value;
+ const uint64_t pm_value;
};
#define PMCMASK(N,V) { .pm_name = #N, .pm_value = (V) }
#define NULLMASK { .pm_name = NULL }
#if defined(__amd64__) || defined(__i386__)
static int
-pmc_parse_mask(const struct pmc_masks *pmask, char *p, uint32_t *evmask)
+pmc_parse_mask(const struct pmc_masks *pmask, char *p, uint64_t *evmask)
{
const struct pmc_masks *pm;
char *q, *r;
@@ -561,8 +575,12 @@ static struct pmc_event_alias core2_aliases_without_iaf[] = {
#define atom_aliases_without_iaf core2_aliases_without_iaf
#define corei7_aliases core2_aliases
#define corei7_aliases_without_iaf core2_aliases_without_iaf
+#define ivybridge_aliases core2_aliases
+#define ivybridge_aliases_without_iaf core2_aliases_without_iaf
#define sandybridge_aliases core2_aliases
#define sandybridge_aliases_without_iaf core2_aliases_without_iaf
+#define sandybridge_xeon_aliases core2_aliases
+#define sandybridge_xeon_aliases_without_iaf core2_aliases_without_iaf
#define westmere_aliases core2_aliases
#define westmere_aliases_without_iaf core2_aliases_without_iaf
@@ -663,7 +681,7 @@ static struct pmc_masks iap_transition_mask[] = {
NULLMASK
};
-static struct pmc_masks iap_rsp_mask[] = {
+static struct pmc_masks iap_rsp_mask_i7_wm[] = {
PMCMASK(DMND_DATA_RD, (1 << 0)),
PMCMASK(DMND_RFO, (1 << 1)),
PMCMASK(DMND_IFETCH, (1 << 2)),
@@ -682,12 +700,43 @@ static struct pmc_masks iap_rsp_mask[] = {
NULLMASK
};
+static struct pmc_masks iap_rsp_mask_sb_sbx_ib[] = {
+ PMCMASK(REQ_DMND_DATA_RD, (1ULL << 0)),
+ PMCMASK(REQ_DMND_RFO, (1ULL << 1)),
+ PMCMASK(REQ_DMND_IFETCH, (1ULL << 2)),
+ PMCMASK(REQ_WB, (1ULL << 3)),
+ PMCMASK(REQ_PF_DATA_RD, (1ULL << 4)),
+ PMCMASK(REQ_PF_RFO, (1ULL << 5)),
+ PMCMASK(REQ_PF_IFETCH, (1ULL << 6)),
+ PMCMASK(REQ_PF_LLC_DATA_RD, (1ULL << 7)),
+ PMCMASK(REQ_PF_LLC_RFO, (1ULL << 8)),
+ PMCMASK(REQ_PF_LLC_IFETCH, (1ULL << 9)),
+ PMCMASK(REQ_BUS_LOCKS, (1ULL << 10)),
+ PMCMASK(REQ_STRM_ST, (1ULL << 11)),
+ PMCMASK(REQ_OTHER, (1ULL << 15)),
+ PMCMASK(RES_ANY, (1ULL << 16)),
+ PMCMASK(RES_SUPPLIER_SUPP, (1ULL << 17)),
+ PMCMASK(RES_SUPPLIER_LLC_HITM, (1ULL << 18)),
+ PMCMASK(RES_SUPPLIER_LLC_HITE, (1ULL << 19)),
+ PMCMASK(RES_SUPPLIER_LLC_HITS, (1ULL << 20)),
+ PMCMASK(RES_SUPPLIER_LLC_HITF, (1ULL << 21)),
+ PMCMASK(RES_SUPPLIER_LOCAL, (1ULL << 22)),
+ PMCMASK(RES_SNOOP_SNP_NONE, (1ULL << 31)),
+ PMCMASK(RES_SNOOP_SNP_NO_NEEDED,(1ULL << 32)),
+ PMCMASK(RES_SNOOP_SNP_MISS, (1ULL << 33)),
+ PMCMASK(RES_SNOOP_HIT_NO_FWD, (1ULL << 34)),
+ PMCMASK(RES_SNOOP_HIT_FWD, (1ULL << 35)),
+ PMCMASK(RES_SNOOP_HITM, (1ULL << 36)),
+ PMCMASK(RES_NON_DRAM, (1ULL << 37)),
+ NULLMASK
+};
+
static int
iap_allocate_pmc(enum pmc_event pe, char *ctrspec,
struct pmc_op_pmcallocate *pmc_config)
{
char *e, *p, *q;
- uint32_t cachestate, evmask, rsp;
+ uint64_t cachestate, evmask, rsp;
int count, n;
pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE |
@@ -753,7 +802,14 @@ iap_allocate_pmc(enum pmc_event pe, char *ctrspec,
} else if (cpu_info.pm_cputype == PMC_CPU_INTEL_COREI7 ||
cpu_info.pm_cputype == PMC_CPU_INTEL_WESTMERE) {
if (KWPREFIXMATCH(p, IAP_KW_RSP "=")) {
- n = pmc_parse_mask(iap_rsp_mask, p, &rsp);
+ n = pmc_parse_mask(iap_rsp_mask_i7_wm, p, &rsp);
+ } else
+ return (-1);
+ } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_SANDYBRIDGE ||
+ cpu_info.pm_cputype == PMC_CPU_INTEL_SANDYBRIDGE_XEON ||
+ cpu_info.pm_cputype == PMC_CPU_INTEL_IVYBRIDGE) {
+ if (KWPREFIXMATCH(p, IAP_KW_RSP "=")) {
+ n = pmc_parse_mask(iap_rsp_mask_sb_sbx_ib, p, &rsp);
} else
return (-1);
} else
@@ -1072,7 +1128,8 @@ k8_allocate_pmc(enum pmc_event pe, char *ctrspec,
{
char *e, *p, *q;
int n;
- uint32_t count, evmask;
+ uint32_t count;
+ uint64_t evmask;
const struct pmc_masks *pm, *pmask;
pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
@@ -1554,7 +1611,8 @@ p4_allocate_pmc(enum pmc_event pe, char *ctrspec,
char *e, *p, *q;
int count, has_tag, has_busreqtype, n;
- uint32_t evmask, cccractivemask;
+ uint32_t cccractivemask;
+ uint64_t evmask;
const struct pmc_masks *pm, *pmask;
pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
@@ -1982,7 +2040,7 @@ p6_allocate_pmc(enum pmc_event pe, char *ctrspec,
struct pmc_op_pmcallocate *pmc_config)
{
char *e, *p, *q;
- uint32_t evmask;
+ uint64_t evmask;
int count, n;
const struct pmc_masks *pm, *pmask;
@@ -2622,10 +2680,18 @@ pmc_event_names_of_class(enum pmc_class cl, const char ***eventnames,
ev = corei7_event_table;
count = PMC_EVENT_TABLE_SIZE(corei7);
break;
+ case PMC_CPU_INTEL_IVYBRIDGE:
+ ev = ivybridge_event_table;
+ count = PMC_EVENT_TABLE_SIZE(ivybridge);
+ break;
case PMC_CPU_INTEL_SANDYBRIDGE:
ev = sandybridge_event_table;
count = PMC_EVENT_TABLE_SIZE(sandybridge);
break;
+ case PMC_CPU_INTEL_SANDYBRIDGE_XEON:
+ ev = sandybridge_xeon_event_table;
+ count = PMC_EVENT_TABLE_SIZE(sandybridge_xeon);
+ break;
case PMC_CPU_INTEL_WESTMERE:
ev = westmere_event_table;
count = PMC_EVENT_TABLE_SIZE(westmere);
@@ -2914,11 +2980,17 @@ pmc_init(void)
pmc_class_table[n++] = &corei7uc_class_table_descr;
PMC_MDEP_INIT_INTEL_V2(corei7);
break;
+ case PMC_CPU_INTEL_IVYBRIDGE:
+ PMC_MDEP_INIT_INTEL_V2(ivybridge);
+ break;
case PMC_CPU_INTEL_SANDYBRIDGE:
pmc_class_table[n++] = &ucf_class_table_descr;
pmc_class_table[n++] = &sandybridgeuc_class_table_descr;
PMC_MDEP_INIT_INTEL_V2(sandybridge);
break;
+ case PMC_CPU_INTEL_SANDYBRIDGE_XEON:
+ PMC_MDEP_INIT_INTEL_V2(sandybridge_xeon);
+ break;
case PMC_CPU_INTEL_WESTMERE:
pmc_class_table[n++] = &ucf_class_table_descr;
pmc_class_table[n++] = &westmereuc_class_table_descr;
@@ -3049,10 +3121,18 @@ _pmc_name_of_event(enum pmc_event pe, enum pmc_cputype cpu)
ev = corei7_event_table;
evfence = corei7_event_table + PMC_EVENT_TABLE_SIZE(corei7);
break;
+ case PMC_CPU_INTEL_IVYBRIDGE:
+ ev = ivybridge_event_table;
+ evfence = ivybridge_event_table + PMC_EVENT_TABLE_SIZE(ivybridge);
+ break;
case PMC_CPU_INTEL_SANDYBRIDGE:
ev = sandybridge_event_table;
evfence = sandybridge_event_table + PMC_EVENT_TABLE_SIZE(sandybridge);
break;
+ case PMC_CPU_INTEL_SANDYBRIDGE_XEON:
+ ev = sandybridge_xeon_event_table;
+ evfence = sandybridge_xeon_event_table + PMC_EVENT_TABLE_SIZE(sandybridge_xeon);
+ break;
case PMC_CPU_INTEL_WESTMERE:
ev = westmere_event_table;
evfence = westmere_event_table + PMC_EVENT_TABLE_SIZE(westmere);
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