diff options
Diffstat (limited to 'lib/libc/ia64/gen')
| -rw-r--r-- | lib/libc/ia64/gen/Makefile.inc | 7 | ||||
| -rw-r--r-- | lib/libc/ia64/gen/__divdf3.S | 143 | ||||
| -rw-r--r-- | lib/libc/ia64/gen/__divdi3.S | 141 | ||||
| -rw-r--r-- | lib/libc/ia64/gen/__divsf3.S | 117 | ||||
| -rw-r--r-- | lib/libc/ia64/gen/__divsi3.S | 123 | ||||
| -rw-r--r-- | lib/libc/ia64/gen/__moddi3.S | 158 | ||||
| -rw-r--r-- | lib/libc/ia64/gen/__modsi3.S | 130 | ||||
| -rw-r--r-- | lib/libc/ia64/gen/__udivdi3.S | 142 | ||||
| -rw-r--r-- | lib/libc/ia64/gen/__udivsi3.S | 123 | ||||
| -rw-r--r-- | lib/libc/ia64/gen/__umoddi3.S | 154 | ||||
| -rw-r--r-- | lib/libc/ia64/gen/__umodsi3.S | 130 | ||||
| -rw-r--r-- | lib/libc/ia64/gen/_setjmp.S | 350 | ||||
| -rw-r--r-- | lib/libc/ia64/gen/fabs.S | 34 | ||||
| -rw-r--r-- | lib/libc/ia64/gen/fpgetmask.c | 40 | ||||
| -rw-r--r-- | lib/libc/ia64/gen/fpsetmask.c | 44 | ||||
| -rw-r--r-- | lib/libc/ia64/gen/frexp.c | 56 | ||||
| -rw-r--r-- | lib/libc/ia64/gen/infinity.c | 36 | ||||
| -rw-r--r-- | lib/libc/ia64/gen/isinf.c | 55 | ||||
| -rw-r--r-- | lib/libc/ia64/gen/ldexp.c | 137 | ||||
| -rw-r--r-- | lib/libc/ia64/gen/modf.c | 106 | ||||
| -rw-r--r-- | lib/libc/ia64/gen/setjmp.S | 89 | ||||
| -rw-r--r-- | lib/libc/ia64/gen/sigsetjmp.S | 75 |
22 files changed, 2390 insertions, 0 deletions
diff --git a/lib/libc/ia64/gen/Makefile.inc b/lib/libc/ia64/gen/Makefile.inc new file mode 100644 index 0000000..4f5dd40 --- /dev/null +++ b/lib/libc/ia64/gen/Makefile.inc @@ -0,0 +1,7 @@ +# $FreeBSD$ + +SRCS+= _setjmp.S fabs.S frexp.c infinity.c isinf.c ldexp.c modf.c setjmp.S +SRCS+= sigsetjmp.S fpsetmask.c fpgetmask.c +SRCS+= __divdi3.S __divsi3.S __moddi3.S __modsi3.S +SRCS+= __udivdi3.S __udivsi3.S __umoddi3.S __umodsi3.S +SRCS+= __divdf3.S __divsf3.S diff --git a/lib/libc/ia64/gen/__divdf3.S b/lib/libc/ia64/gen/__divdf3.S new file mode 100644 index 0000000..f27d3e0 --- /dev/null +++ b/lib/libc/ia64/gen/__divdf3.S @@ -0,0 +1,143 @@ +// $FreeBSD$ + +// +// Copyright (c) 2000, Intel Corporation +// All rights reserved. +// +// Contributed 2/15/2000 by Marius Cornea, John Harrison, Cristina Iordache, +// Ted Kubaska, Bob Norin, and Shane Story of the Computational Software Lab, +// Intel Corporation. +// +// WARRANTY DISCLAIMER +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL INTEL OR ITS +// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY +// OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT (INCLUDING +// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// Intel Corporation is the author of this code, and requests that all +// problem reports or change requests be submitted to it directly at +// http://developer.intel.com/opensource. +// + +#include <machine/asm.h> + + .section .text + +ENTRY(__divdf3, 0) +{ .mfi + // a is in f8 + // b is in f9 + + // predicate registers used: p6 + // floating-point registers used: f6, f7, f8, f9, f10, f11 + + // load a, the first argument, in f6 + nop.m 0 + mov f6=f8 + nop.i 0 +} { .mfi + // load b, the second argument, in f7 + nop.m 0 + mov f7=f9 + nop.i 0;; +} { .mfi + + // BEGIN DOUBLE PRECISION LATENCY-OPTIMIZED DIVIDE ALGORITHM + + nop.m 0 + // Step (1) + // y0 = 1 / b in f8 + frcpa.s0 f8,p6=f6,f7 + nop.i 0;; +} { .mfi + nop.m 0 + // Step (2) + // q0 = a * y0 in f9 + (p6) fma.s1 f9=f6,f8,f0 + nop.i 0 +} { .mfi + nop.m 0 + // Step (3) + // e0 = 1 - b * y0 in f10 + (p6) fnma.s1 f10=f7,f8,f1 + nop.i 0;; +} { .mfi + nop.m 0 + // Step (4) + // q1 = q0 + e0 * q0 in f9 + (p6) fma.s1 f9=f10,f9,f9 + nop.i 0 +} { .mfi + nop.m 0 + // Step (5) + // e1 = e0 * e0 in f11 + (p6) fma.s1 f11=f10,f10,f0 + nop.i 0 +} { .mfi + nop.m 0 + // Step (6) + // y1 = y0 + e0 * y0 in f8 + (p6) fma.s1 f8=f10,f8,f8 + nop.i 0;; +} { .mfi + nop.m 0 + // Step (7) + // q2 = q1 + e1 * q1 in f9 + (p6) fma.s1 f9=f11,f9,f9 + nop.i 0 +} { .mfi + nop.m 0 + // Step (8) + // e2 = e1 * e1 in f10 + (p6) fma.s1 f10=f11,f11,f0 + nop.i 0 +} { .mfi + nop.m 0 + // Step (9) + // y2 = y1 + e1 * y1 in f8 + (p6) fma.s1 f8=f11,f8,f8 + nop.i 0;; +} { .mfi + nop.m 0 + // Step (10) + // q3 = q2 + e2 * q2 in f9 + (p6) fma.d.s1 f9=f10,f9,f9 + nop.i 0;; +} { .mfi + nop.m 0 + // Step (11) + // y3 = y2 + e2 * y2 in f8 + (p6) fma.s1 f8=f10,f8,f8 + nop.i 0;; +} { .mfi + nop.m 0 + // Step (12) + // r0 = a - b * q3 in f6 + (p6) fnma.d.s1 f6=f7,f9,f6 + nop.i 0;; +} { .mfi + nop.m 0 + // Step (13) + // q4 = q3 + r0 * y3 in f8 + (p6) fma.d.s0 f8=f6,f8,f9 + nop.i 0;; + + // END DOUBLE PRECISION LATENCY-OPTIMIZED DIVIDE ALGORITHM + +} { .mib + nop.m 0 + nop.i 0 + // return + br.ret.sptk b0;; +} + +END(__divdf3) + diff --git a/lib/libc/ia64/gen/__divdi3.S b/lib/libc/ia64/gen/__divdi3.S new file mode 100644 index 0000000..7b06bf46 --- /dev/null +++ b/lib/libc/ia64/gen/__divdi3.S @@ -0,0 +1,141 @@ +/* $FreeBSD$ */ +.file "__divdi3.s" + +// +// Copyright (c) 2000, Intel Corporation +// All rights reserved. +// +// Contributed 2/15/2000 by Marius Cornea, John Harrison, Cristina Iordache, +// Ted Kubaska, Bob Norin, and Shane Story of the Computational Software Lab, +// Intel Corporation. +// +// WARRANTY DISCLAIMER +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL INTEL OR ITS +// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY +// OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT (INCLUDING +// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// Intel Corporation is the author of this code, and requests that all +// problem reports or change requests be submitted to it directly at +// http://developer.intel.com/opensource. +// + +.section .text +.proc __divdi3# +.align 32 +.global __divdi3# +.align 32 + +// 64-bit signed integer divide + +__divdi3: + +{ .mii + alloc r31=ar.pfs,2,0,0,0 + nop.i 0 + nop.i 0;; +} { .mmi + + // 64-BIT SIGNED INTEGER DIVIDE BEGINS HERE + + setf.sig f8=r32 + setf.sig f9=r33 + nop.i 0;; +} { .mfb + nop.m 0 + fcvt.xf f6=f8 + nop.b 0 +} { .mfb + nop.m 0 + fcvt.xf f7=f9 + nop.b 0;; +} { .mfi + nop.m 0 + // Step (1) + // y0 = 1 / b in f8 + frcpa.s1 f8,p6=f6,f7 + nop.i 0;; +} { .mfi + nop.m 0 + // Step (2) + // e0 = 1 - b * y0 in f9 + (p6) fnma.s1 f9=f7,f8,f1 + nop.i 0 +} { .mfi + nop.m 0 + // Step (3) + // q0 = a * y0 in f10 + (p6) fma.s1 f10=f6,f8,f0 + nop.i 0;; +} { .mfi + nop.m 0 + // Step (4) + // e1 = e0 * e0 in f11 + (p6) fma.s1 f11=f9,f9,f0 + nop.i 0 +} { .mfi + nop.m 0 + // Step (5) + // q1 = q0 + e0 * q0 in f10 + (p6) fma.s1 f10=f9,f10,f10 + nop.i 0;; +} { .mfi + nop.m 0 + // Step (6) + // y1 = y0 + e0 * y0 in f8 + (p6) fma.s1 f8=f9,f8,f8 + nop.i 0;; +} { .mfi + nop.m 0 + // Step (7) + // q2 = q1 + e1 * q1 in f9 + (p6) fma.s1 f9=f11,f10,f10 + nop.i 0;; +} { .mfi + nop.m 0 + // Step (8) + // y2 = y1 + e1 * y1 in f8 + (p6) fma.s1 f8=f11,f8,f8 + nop.i 0;; +} { .mfi + nop.m 0 + // Step (9) + // r2 = a - b * q2 in f10 + (p6) fnma.s1 f10=f7,f9,f6 + nop.i 0;; +} { .mfi + nop.m 0 + // Step (10) + // q3 = q2 + r2 * y2 in f8 + (p6) fma.s1 f8=f10,f8,f9 + nop.i 0;; +} { .mfb + nop.m 0 + // Step (11) + // q = trunc (q3) + fcvt.fx.trunc.s1 f8=f8 + nop.b 0;; +} { .mmi + // quotient will be in r8 (if b != 0) + getf.sig r8=f8 + nop.m 0 + nop.i 0;; +} + + // 64-BIT SIGNED INTEGER DIVIDE ENDS HERE + +{ .mmb + nop.m 0 + nop.m 0 + br.ret.sptk b0;; +} + +.endp __divdi3 diff --git a/lib/libc/ia64/gen/__divsf3.S b/lib/libc/ia64/gen/__divsf3.S new file mode 100644 index 0000000..e962415 --- /dev/null +++ b/lib/libc/ia64/gen/__divsf3.S @@ -0,0 +1,117 @@ +// $FreeBSD$ + +// +// Copyright (c) 2000, Intel Corporation +// All rights reserved. +// +// Contributed 2/15/2000 by Marius Cornea, John Harrison, Cristina Iordache, +// Ted Kubaska, Bob Norin, and Shane Story of the Computational Software Lab, +// Intel Corporation. +// +// WARRANTY DISCLAIMER +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL INTEL OR ITS +// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY +// OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT (INCLUDING +// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// Intel Corporation is the author of this code, and requests that all +// problem reports or change requests be submitted to it directly at +// http://developer.intel.com/opensource. +// + +#include <machine/asm.h> + +ENTRY(__divsf3, 0) +{ .mfi + // a is in f8 + // b is in f9 + + // general registers used: r31, r32, r33, r34 + // predicate registers used: p6 + // floating-point registers used: f6, f7, f8 + + nop.m 0 + // load a, the first argument, in f6 + mov f6=f8 + nop.i 0;; +} { .mfi + nop.m 0 + // load b, the second argument, in f7 + mov f7=f9 + nop.i 0;; +} { .mfi + + // BEGIN SINGLE PRECISION LATENCY-OPTIMIZED DIVIDE ALGORITHM + + nop.m 0 + // Step (1) + // y0 = 1 / b in f8 + frcpa.s0 f8,p6=f6,f7 + nop.i 0;; +} { .mfi + nop.m 0 + // Step (2) + // q0 = a * y0 in f6 + (p6) fma.s1 f6=f6,f8,f0 + nop.i 0 +} { .mfi + nop.m 0 + // Step (3) + // e0 = 1 - b * y0 in f7 + (p6) fnma.s1 f7=f7,f8,f1 + nop.i 0;; +} { .mfi + nop.m 0 + // Step (4) + // q1 = q0 + e0 * q0 in f6 + (p6) fma.s1 f6=f7,f6,f6 + nop.i 0 +} { .mfi + nop.m 0 + // Step (5) + // e1 = e0 * e0 in f7 + (p6) fma.s1 f7=f7,f7,f0 + nop.i 0;; +} { .mfi + nop.m 0 + // Step (6) + // q2 = q1 + e1 * q1 in f6 + (p6) fma.s1 f6=f7,f6,f6 + nop.i 0 +} { .mfi + nop.m 0 + // Step (7) + // e2 = e1 * e1 in f7 + (p6) fma.s1 f7=f7,f7,f0 + nop.i 0;; +} { .mfi + nop.m 0 + // Step (8) + // q3 = q2 + e2 * q2 in f6 + (p6) fma.d.s1 f6=f7,f6,f6 + nop.i 0;; +} { .mfi + nop.m 0 + // Step (9) + // q3' = q3 in f8 + (p6) fma.s.s0 f8=f6,f1,f0 + nop.i 0;; + + // END SINGLE PRECISION LATENCY-OPTIMIZED DIVIDE ALGORITHM + +} { .mmb + nop.m 0 + nop.m 0 + // return + br.ret.sptk b0;; +} + +END(__divsf3) diff --git a/lib/libc/ia64/gen/__divsi3.S b/lib/libc/ia64/gen/__divsi3.S new file mode 100644 index 0000000..7c088e9 --- /dev/null +++ b/lib/libc/ia64/gen/__divsi3.S @@ -0,0 +1,123 @@ +/* $FreeBSD$ */ +.file "__divsi3.s" + +// +// Copyright (c) 2000, Intel Corporation +// All rights reserved. +// +// Contributed 2/15/2000 by Marius Cornea, John Harrison, Cristina Iordache, +// Ted Kubaska, Bob Norin, and Shane Story of the Computational Software Lab, +// Intel Corporation. +// +// WARRANTY DISCLAIMER +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL INTEL OR ITS +// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY +// OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT (INCLUDING +// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// Intel Corporation is the author of this code, and requests that all +// problem reports or change requests be submitted to it directly at +// http://developer.intel.com/opensource. +// + +.section .text + +// 32-bit signed integer divide + +.proc __divsi3# +.align 32 +.global __divsi3# +.align 32 + +__divsi3: + +{ .mii + alloc r31=ar.pfs,2,0,0,0 + nop.i 0 + nop.i 0;; +} { .mii + nop.m 0 + + // 32-BIT SIGNED INTEGER DIVIDE BEGINS HERE + + // general register used: + // r32 - 32-bit signed integer dividend + // r33 - 32-bit signed integer divisor + // r8 - 32-bit signed integer result + // r2 - scratch register + // floating-point registers used: f6, f7, f8, f9 + // predicate registers used: p6 + + sxt4 r32=r32 + sxt4 r33=r33;; +} { .mmb + setf.sig f6=r32 + setf.sig f7=r33 + nop.b 0;; +} { .mfi + nop.m 0 + fcvt.xf f6=f6 + nop.i 0 +} { .mfi + nop.m 0 + fcvt.xf f7=f7 + mov r2 = 0x0ffdd;; +} { .mfi + setf.exp f9 = r2 + // (1) y0 + frcpa.s1 f8,p6=f6,f7 + nop.i 0;; +} { .mfi + nop.m 0 + // (2) q0 = a * y0 + (p6) fma.s1 f6=f6,f8,f0 + nop.i 0 +} { .mfi + nop.m 0 + // (3) e0 = 1 - b * y0 + (p6) fnma.s1 f7=f7,f8,f1 + nop.i 0;; +} { .mfi + nop.m 0 + // (4) q1 = q0 + e0 * q0 + (p6) fma.s1 f6=f7,f6,f6 + nop.i 0 +} { .mfi + nop.m 0 + // (5) e1 = e0 * e0 + 2^-34 + (p6) fma.s1 f7=f7,f7,f9 + nop.i 0;; +} { .mfi + nop.m 0 + // (6) q2 = q1 + e1 * q1 + (p6) fma.s1 f8=f7,f6,f6 + nop.i 0;; +} { .mfi + nop.m 0 + // (7) q = trunc(q2) + fcvt.fx.trunc.s1 f8=f8 + nop.i 0;; +} { .mmi + // quotient will be in the least significant 32 bits of r8 (if b != 0) + getf.sig r8=f8 + nop.m 0 + nop.i 0;; +} + + // 32-BIT SIGNED INTEGER DIVIDE ENDS HERE + +{ .mmb + nop.m 0 + nop.m 0 + br.ret.sptk b0;; +} + +.endp __divsi3 diff --git a/lib/libc/ia64/gen/__moddi3.S b/lib/libc/ia64/gen/__moddi3.S new file mode 100644 index 0000000..bc2cc61 --- /dev/null +++ b/lib/libc/ia64/gen/__moddi3.S @@ -0,0 +1,158 @@ +/* $FreeBSD$ */ +.file "__moddi3.s" + +// +// Copyright (c) 2000, Intel Corporation +// All rights reserved. +// +// Contributed 2/15/2000 by Marius Cornea, John Harrison, Cristina Iordache, +// Ted Kubaska, Bob Norin, and Shane Story of the Computational Software Lab, +// Intel Corporation. +// +// WARRANTY DISCLAIMER +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL INTEL OR ITS +// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY +// OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT (INCLUDING +// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// Intel Corporation is the author of this code, and requests that all +// problem reports or change requests be submitted to it directly at +// http://developer.intel.com/opensource. +// + +.section .text + +// 64-bit signed integer remainder + +.proc __moddi3# +.align 32 +.global __moddi3# +.align 32 + +__moddi3: + +{ .mii + alloc r31=ar.pfs,3,0,0,0 + nop.i 0 + nop.i 0 +} { .mmb + + // 64-BIT SIGNED INTEGER REMAINDER BEGINS HERE + + // general register used: + // r32 - 64-bit signed integer dividend + // r33 - 64-bit signed integer divisor + // r8 - 64-bit signed integer result + // r2 - scratch register + // floating-point registers used: f6, f7, f8, f9, f10, f11, f12 + // predicate registers used: p6 + + setf.sig f12=r32 // holds a in integer form + setf.sig f7=r33 + nop.b 0 +} { .mlx + nop.m 0 + //movl r2=0x8000000000000000;; + movl r2=0xffffffffffffffff;; +} { .mfi + // get the 2's complement of b + sub r33=r0,r33 + fcvt.xf f6=f12 + nop.i 0 +} { .mfi + nop.m 0 + fcvt.xf f7=f7 + nop.i 0;; +} { .mfi + nop.m 0 + // Step (1) + // y0 = 1 / b in f8 + frcpa.s1 f8,p6=f6,f7 + nop.i 0;; +} { .mfi + nop.m 0 + // Step (2) + // q0 = a * y0 in f10 + (p6) fma.s1 f10=f6,f8,f0 + nop.i 0 +} { .mfi + nop.m 0 + // Step (3) + // e0 = 1 - b * y0 in f9 + (p6) fnma.s1 f9=f7,f8,f1 + nop.i 0;; +} { .mfi + nop.m 0 + // Step (4) + // q1 = q0 + e0 * q0 in f10 + (p6) fma.s1 f10=f9,f10,f10 + nop.i 0 +} { .mfi + nop.m 0 + // Step (5) + // e1 = e0 * e0 in f11 + (p6) fma.s1 f11=f9,f9,f0 + nop.i 0;; +} { .mfi + nop.m 0 + // Step (6) + // y1 = y0 + e0 * y0 in f8 + (p6) fma.s1 f8=f9,f8,f8 + nop.i 0;; +} { .mfi + nop.m 0 + // Step (7) + // q2 = q1 + e1 * q1 in f9 + (p6) fma.s1 f9=f11,f10,f10 + nop.i 0;; +} { .mfi + nop.m 0 + // Step (8) + // y2 = y1 + e1 * y1 in f8 + (p6) fma.s1 f8=f11,f8,f8 + nop.i 0;; +} { .mfi + nop.m 0 + // Step (9) + // r2 = a - b * q2 in f10 + (p6) fnma.s1 f10=f7,f9,f6 + nop.i 0;; +} { .mfi + setf.sig f7=r33 + // Step (10) + // q3 = q2 + r2 * y2 in f8 + (p6) fma.s1 f8=f10,f8,f9 + nop.i 0;; +} { .mfi + nop.m 0 + // (11) q = trunc(q3) + fcvt.fx.trunc.s1 f8=f8 + nop.i 0;; +} { .mfi + nop.m 0 + // (12) r = a + (-b) * q + xma.l f8=f8,f7,f12 + nop.i 0;; +} { .mib + getf.sig r8=f8 + nop.i 0 + nop.b 0 +} + + // 64-BIT SIGNED INTEGER REMAINDER ENDS HERE + +{ .mib + nop.m 0 + nop.i 0 + br.ret.sptk b0;; +} + +.endp __moddi3 diff --git a/lib/libc/ia64/gen/__modsi3.S b/lib/libc/ia64/gen/__modsi3.S new file mode 100644 index 0000000..f91cf75 --- /dev/null +++ b/lib/libc/ia64/gen/__modsi3.S @@ -0,0 +1,130 @@ +/* $FreeBSD$ */ +.file "__modsi3.s" + +// +// Copyright (c) 2000, Intel Corporation +// All rights reserved. +// +// Contributed 2/15/2000 by Marius Cornea, John Harrison, Cristina Iordache, +// Ted Kubaska, Bob Norin, and Shane Story of the Computational Software Lab, +// Intel Corporation. +// +// WARRANTY DISCLAIMER +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL INTEL OR ITS +// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY +// OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT (INCLUDING +// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// Intel Corporation is the author of this code, and requests that all +// problem reports or change requests be submitted to it directly at +// http://developer.intel.com/opensource. +// + +.section .text + +// 32-bit signed integer remainder + +.proc __modsi3# +.align 32 +.global __modsi3# +.align 32 + +__modsi3: + +{ .mii + alloc r31=ar.pfs,2,0,0,0 + nop.i 0 + nop.i 0;; +} { .mii + nop.m 0 + + // 32-BIT SIGNED INTEGER REMAINDER BEGINS HERE + + // general register used: + // r32 - 32-bit signed integer dividend + // r33 - 32-bit signed integer divisor + // r8 - 32-bit signed integer result + // r2 - scratch register + // floating-point registers used: f6, f7, f8, f9, f10, f11 + // predicate registers used: p6 + + sxt4 r32=r32 + sxt4 r33=r33;; +} { .mmb + setf.sig f11=r32 + setf.sig f7=r33 + nop.b 0;; +} { .mfi + // get 2's complement of b + sub r33=r0,r33 + fcvt.xf f6=f11 + nop.i 0 +} { .mfi + nop.m 0 + fcvt.xf f7=f7 + mov r2 = 0x0ffdd;; +} { .mfi + setf.exp f9 = r2 + // (1) y0 + frcpa.s1 f8,p6=f6,f7 + nop.i 0;; +} { .mfi + nop.m 0 + // (2) q0 = a * y0 + (p6) fma.s1 f10=f6,f8,f0 + nop.i 0 +} { .mfi + nop.m 0 + // (3) e0 = 1 - b * y0 + (p6) fnma.s1 f8=f7,f8,f1 + nop.i 0;; +} { .mfi + // 2's complement of b + setf.sig f7=r33 + // (4) q1 = q0 + e0 * q0 + (p6) fma.s1 f10=f8,f10,f10 + nop.i 0 +} { .mfi + nop.m 0 + // (5) e1 = e0 * e0 + 2^-34 + (p6) fma.s1 f8=f8,f8,f9 + nop.i 0;; +} { .mfi + nop.m 0 + // (6) q2 = q1 + e1 * q1 + (p6) fma.s1 f8=f8,f10,f10 + nop.i 0;; +} { .mfi + nop.m 0 + // (7) q = trunc(q2) + fcvt.fx.trunc.s1 f8=f8 + nop.i 0;; +} { .mfi + nop.m 0 + // (8) r = a + (-b) * q + xma.l f8=f8,f7,f11 + nop.i 0;; +} { .mmi + // remainder will be in the least significant 32 bits of r8 (if b != 0) + getf.sig r8=f8 + nop.m 0 + nop.i 0;; +} + + // 32-BIT SIGNED INTEGER REMAINDER ENDS HERE + +{ .mmb + nop.m 0 + nop.m 0 + br.ret.sptk b0;; +} + +.endp __modsi3 diff --git a/lib/libc/ia64/gen/__udivdi3.S b/lib/libc/ia64/gen/__udivdi3.S new file mode 100644 index 0000000..6a9fad4c --- /dev/null +++ b/lib/libc/ia64/gen/__udivdi3.S @@ -0,0 +1,142 @@ +/* $FreeBSD$ */ +.file "__udivdi3.s" + +// +// Copyright (c) 2000, Intel Corporation +// All rights reserved. +// +// Contributed 2/15/2000 by Marius Cornea, John Harrison, Cristina Iordache, +// Ted Kubaska, Bob Norin, and Shane Story of the Computational Software Lab, +// Intel Corporation. +// +// WARRANTY DISCLAIMER +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL INTEL OR ITS +// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY +// OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT (INCLUDING +// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// Intel Corporation is the author of this code, and requests that all +// problem reports or change requests be submitted to it directly at +// http://developer.intel.com/opensource. +// + +.section .text +.proc __udivdi3# +.align 32 +.global __udivdi3# +.align 32 + +// 64-bit unsigned integer divide + +__udivdi3: + +{ .mii + alloc r31=ar.pfs,2,0,0,0 + nop.i 0 + nop.i 0;; +} + +{ .mmi + + // 64-BIT UNSIGNED INTEGER DIVIDE BEGINS HERE + + setf.sig f8=r32 + setf.sig f9=r33 + nop.i 0;; +} { .mfb + nop.m 0 + fma.s1 f6=f8,f1,f0 + nop.b 0 +} { .mfb + nop.m 0 + fma.s1 f7=f9,f1,f0 + nop.b 0;; +} { .mfi + nop.m 0 + // Step (1) + // y0 = 1 / b in f8 + frcpa.s1 f8,p6=f6,f7 + nop.i 0;; +} { .mfi + nop.m 0 + // Step (2) + // e0 = 1 - b * y0 in f9 + (p6) fnma.s1 f9=f7,f8,f1 + nop.i 0 +} { .mfi + nop.m 0 + // Step (3) + // q0 = a * y0 in f10 + (p6) fma.s1 f10=f6,f8,f0 + nop.i 0;; +} { .mfi + nop.m 0 + // Step (4) + // e1 = e0 * e0 in f11 + (p6) fma.s1 f11=f9,f9,f0 + nop.i 0 +} { .mfi + nop.m 0 + // Step (5) + // q1 = q0 + e0 * q0 in f10 + (p6) fma.s1 f10=f9,f10,f10 + nop.i 0;; +} { .mfi + nop.m 0 + // Step (6) + // y1 = y0 + e0 * y0 in f8 + (p6) fma.s1 f8=f9,f8,f8 + nop.i 0;; +} { .mfi + nop.m 0 + // Step (7) + // q2 = q1 + e1 * q1 in f9 + (p6) fma.s1 f9=f11,f10,f10 + nop.i 0;; +} { .mfi + nop.m 0 + // Step (8) + // y2 = y1 + e1 * y1 in f8 + (p6) fma.s1 f8=f11,f8,f8 + nop.i 0;; +} { .mfi + nop.m 0 + // Step (9) + // r2 = a - b * q2 in f10 + (p6) fnma.s1 f10=f7,f9,f6 + nop.i 0;; +} { .mfi + nop.m 0 + // Step (10) + // q3 = q2 + r2 * y2 in f8 + (p6) fma.s1 f8=f10,f8,f9 + nop.i 0;; +} { .mfb + nop.m 0 + // (11) q = trunc(q3) + fcvt.fxu.trunc.s1 f8=f8 + nop.b 0;; +} { .mmi + // quotient will be in r8 (if b != 0) + getf.sig r8=f8 + nop.m 0 + nop.i 0;; +} + + // 64-BIT UNSIGNED INTEGER DIVIDE ENDS HERE + +{ .mmb + nop.m 0 + nop.m 0 + br.ret.sptk b0;; +} + +.endp __udivdi3 diff --git a/lib/libc/ia64/gen/__udivsi3.S b/lib/libc/ia64/gen/__udivsi3.S new file mode 100644 index 0000000..0ac0369 --- /dev/null +++ b/lib/libc/ia64/gen/__udivsi3.S @@ -0,0 +1,123 @@ +/* $FreeBSD$ */ +.file "__udivsi3.s" + +// +// Copyright (c) 2000, Intel Corporation +// All rights reserved. +// +// Contributed 2/15/2000 by Marius Cornea, John Harrison, Cristina Iordache, +// Ted Kubaska, Bob Norin, and Shane Story of the Computational Software Lab, +// Intel Corporation. +// +// WARRANTY DISCLAIMER +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL INTEL OR ITS +// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY +// OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT (INCLUDING +// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// Intel Corporation is the author of this code, and requests that all +// problem reports or change requests be submitted to it directly at +// http://developer.intel.com/opensource. +// + +.section .text + +// 32-bit unsigned integer divide + +.proc __udivsi3# +.align 32 +.global __udivsi3# +.align 32 + +__udivsi3: + +{ .mii + alloc r31=ar.pfs,2,0,0,0 + nop.i 0 + nop.i 0;; +} { .mii + nop.m 0 + + // 32-BIT UNSIGNED INTEGER DIVIDE BEGINS HERE + + // general register used: + // r32 - 32-bit unsigned integer dividend + // r33 - 32-bit unsigned integer divisor + // r8 - 32-bit unsigned integer result + // r2 - scratch register + // floating-point registers used: f6, f7, f8, f9 + // predicate registers used: p6 + + zxt4 r32=r32 + zxt4 r33=r33;; +} { .mmb + setf.sig f6=r32 + setf.sig f7=r33 + nop.b 0;; +} { .mfi + nop.m 0 + fcvt.xf f6=f6 + nop.i 0 +} { .mfi + nop.m 0 + fcvt.xf f7=f7 + mov r2 = 0x0ffdd;; +} { .mfi + setf.exp f9 = r2 + // (1) y0 + frcpa.s1 f8,p6=f6,f7 + nop.i 0;; +} { .mfi + nop.m 0 + // (2) q0 = a * y0 + (p6) fma.s1 f6=f6,f8,f0 + nop.i 0 +} { .mfi + nop.m 0 + // (3) e0 = 1 - b * y0 + (p6) fnma.s1 f7=f7,f8,f1 + nop.i 0;; +} { .mfi + nop.m 0 + // (4) q1 = q0 + e0 * q0 + (p6) fma.s1 f6=f7,f6,f6 + nop.i 0 +} { .mfi + nop.m 0 + // (5) e1 = e0 * e0 + 2^-34 + (p6) fma.s1 f7=f7,f7,f9 + nop.i 0;; +} { .mfi + nop.m 0 + // (6) q2 = q1 + e1 * q1 + (p6) fma.s1 f8=f7,f6,f6 + nop.i 0;; +} { .mfi + nop.m 0 + // (7) q = trunc(q2) + fcvt.fxu.trunc.s1 f8=f8 + nop.i 0;; +} { .mmi + // quotient will be in the least significant 32 bits of r8 (if b != 0) + getf.sig r8=f8 + nop.m 0 + nop.i 0;; +} + + // 32-BIT UNSIGNED INTEGER DIVIDE ENDS HERE + +{ .mmb + nop.m 0 + nop.m 0 + br.ret.sptk b0;; +} + +.endp __udivsi3 diff --git a/lib/libc/ia64/gen/__umoddi3.S b/lib/libc/ia64/gen/__umoddi3.S new file mode 100644 index 0000000..84991b0 --- /dev/null +++ b/lib/libc/ia64/gen/__umoddi3.S @@ -0,0 +1,154 @@ +/* $FreeBSD$ */ +.file "__umoddi3.s" + +// +// Copyright (c) 2000, Intel Corporation +// All rights reserved. +// +// Contributed 2/15/2000 by Marius Cornea, John Harrison, Cristina Iordache, +// Ted Kubaska, Bob Norin, and Shane Story of the Computational Software Lab, +// Intel Corporation. +// +// WARRANTY DISCLAIMER +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL INTEL OR ITS +// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY +// OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT (INCLUDING +// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// Intel Corporation is the author of this code, and requests that all +// problem reports or change requests be submitted to it directly at +// http://developer.intel.com/opensource. +// + +.section .text + + // 64-bit unsigned integer remainder + +.proc __umoddi3# +.align 32 +.global __umoddi3# +.align 32 + +__umoddi3: + +{ .mii + alloc r31=ar.pfs,3,0,0,0 + nop.i 0 + nop.i 0 +} { .mmb + + // 64-BIT UNSIGNED INTEGER REMAINDER BEGINS HERE + + // general register used: + // r32 - 64-bit unsigned integer dividend + // r33 - 64-bit unsigned integer divisor + // r8 - 64-bit unsigned integer result + // floating-point registers used: f6, f7, f8, f9, f10, f11, f12 + // predicate registers used: p6 + + setf.sig f12=r32 // holds a in integer form + setf.sig f7=r33 + nop.b 0;; +} { .mfi + // get 2's complement of b + sub r33=r0,r33 + fcvt.xuf.s1 f6=f12 + nop.i 0 +} { .mfi + nop.m 0 + fcvt.xuf.s1 f7=f7 + nop.i 0;; +} { .mfi + nop.m 0 + // Step (1) + // y0 = 1 / b in f8 + frcpa.s1 f8,p6=f6,f7 + nop.i 0;; +} { .mfi + nop.m 0 + // Step (2) + // q0 = a * y0 in f10 + (p6) fma.s1 f10=f6,f8,f0 + nop.i 0 +} { .mfi + nop.m 0 + // Step (3) + // e0 = 1 - b * y0 in f9 + (p6) fnma.s1 f9=f7,f8,f1 + nop.i 0;; +} { .mfi + nop.m 0 + // Step (4) + // q1 = q0 + e0 * q0 in f10 + (p6) fma.s1 f10=f9,f10,f10 + nop.i 0 +} { .mfi + nop.m 0 + // Step (5) + // e1 = e0 * e0 in f11 + (p6) fma.s1 f11=f9,f9,f0 + nop.i 0;; +} { .mfi + nop.m 0 + // Step (6) + // y1 = y0 + e0 * y0 in f8 + (p6) fma.s1 f8=f9,f8,f8 + nop.i 0;; +} { .mfi + nop.m 0 + // Step (7) + // q2 = q1 + e1 * q1 in f9 + (p6) fma.s1 f9=f11,f10,f10 + nop.i 0;; +} { .mfi + nop.m 0 + // Step (8) + // y2 = y1 + e1 * y1 in f8 + (p6) fma.s1 f8=f11,f8,f8 + nop.i 0;; +} { .mfi + nop.m 0 + // Step (9) + // r2 = a - b * q2 in f10 + (p6) fnma.s1 f10=f7,f9,f6 + nop.i 0;; +} { .mfi + // f7=-b + setf.sig f7=r33 + // Step (10) + // q3 = q2 + r2 * y2 in f8 + (p6) fma.s1 f8=f10,f8,f9 + nop.i 0;; +} { .mfi + nop.m 0 + // (11) q = trunc(q3) + fcvt.fxu.trunc.s1 f8=f8 + nop.i 0;; +} { .mfi + nop.m 0 + // (12) r = a + (-b) * q + xma.l f8=f8,f7,f12 + nop.i 0;; +} { .mib + getf.sig r8=f8 + nop.i 0 + nop.b 0 +} + + // 64-BIT UNSIGNED INTEGER REMAINDER ENDS HERE + +{ .mib + nop.m 0 + nop.i 0 + br.ret.sptk b0;; +} + +.endp __umoddi3 diff --git a/lib/libc/ia64/gen/__umodsi3.S b/lib/libc/ia64/gen/__umodsi3.S new file mode 100644 index 0000000..5076e76 --- /dev/null +++ b/lib/libc/ia64/gen/__umodsi3.S @@ -0,0 +1,130 @@ +/* $FreeBSD$ */ +.file "__umodsi3.s" + +// +// Copyright (c) 2000, Intel Corporation +// All rights reserved. +// +// Contributed 2/15/2000 by Marius Cornea, John Harrison, Cristina Iordache, +// Ted Kubaska, Bob Norin, and Shane Story of the Computational Software Lab, +// Intel Corporation. +// +// WARRANTY DISCLAIMER +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL INTEL OR ITS +// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY +// OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT (INCLUDING +// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// Intel Corporation is the author of this code, and requests that all +// problem reports or change requests be submitted to it directly at +// http://developer.intel.com/opensource. +// + +.section .text + +// 32-bit unsigned integer remainder + +.proc __umodsi3# +.align 32 +.global __umodsi3# +.align 32 + +__umodsi3: + +{ .mii + alloc r31=ar.pfs,2,0,0,0 + nop.i 0 + nop.i 0;; +} { .mii + nop.m 0 + + // 32-BIT UNSIGNED INTEGER REMAINDER BEGINS HERE + + // general register used: + // r32 - 32-bit unsigned integer dividend + // r33 - 32-bit unsigned integer divisor + // r8 - 32-bit unsigned integer result + // r2 - scratch register + // floating-point registers used: f6, f7, f8, f9, f10, f11 + // predicate registers used: p6 + + zxt4 r32=r32 + zxt4 r33=r33;; +} { .mmb + setf.sig f11=r32 + setf.sig f7=r33 + nop.b 0;; +} { .mfi + nop.m 0 + fcvt.xf f6=f11 + nop.i 0 +} { .mfi + // get 2's complement of b + sub r33=r0,r33 + fcvt.xf f7=f7 + mov r2 = 0x0ffdd;; +} { .mfi + setf.exp f9 = r2 + // (1) y0 + frcpa.s1 f8,p6=f6,f7 + nop.i 0;; +} { .mfi + nop.m 0 + // (2) q0 = a * y0 + (p6) fma.s1 f10=f6,f8,f0 + nop.i 0 +} { .mfi + nop.m 0 + // (3) e0 = 1 - b * y0 + (p6) fnma.s1 f8=f7,f8,f1 + nop.i 0;; +} { .mfi + nop.m 0 + // (4) q1 = q0 + e0 * q0 + (p6) fma.s1 f10=f8,f10,f10 + nop.i 0 +} { .mfi + // get 2's complement of b + setf.sig f7=r33 + // (5) e1 = e0 * e0 + 2^-34 + (p6) fma.s1 f8=f8,f8,f9 + nop.i 0;; +} { .mfi + nop.m 0 + // (6) q2 = q1 + e1 * q1 + (p6) fma.s1 f8=f8,f10,f10 + nop.i 0;; +} { .mfi + nop.m 0 + // (7) q = trunc(q2) + fcvt.fxu.trunc.s1 f8=f8 + nop.i 0;; +} { .mfi + nop.m 0 + // (8) r = a + (-b) * q + xma.l f8=f8,f7,f11 + nop.i 0;; +} { .mmi + // remainder will be in the least significant 32 bits of r8 (if b != 0) + getf.sig r8=f8 + nop.m 0 + nop.i 0;; +} + + // 32-BIT UNSIGNED INTEGER REMAINDER ENDS HERE + +{ .mmb + nop.m 0 + nop.m 0 + br.ret.sptk b0;; +} + +.endp __umodsi3 diff --git a/lib/libc/ia64/gen/_setjmp.S b/lib/libc/ia64/gen/_setjmp.S new file mode 100644 index 0000000..e4e90b2 --- /dev/null +++ b/lib/libc/ia64/gen/_setjmp.S @@ -0,0 +1,350 @@ +// $FreeBSD$ +// +// Copyright (c) 1999, 2000 +// Intel Corporation. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// 1. Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. All advertising materials mentioning features or use of this software +// must display the following acknowledgement: +// +// This product includes software developed by Intel Corporation and +// its contributors. +// +// 4. Neither the name of Intel Corporation or its contributors may be +// used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY INTEL CORPORATION AND CONTRIBUTORS ``AS IS'' +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL INTEL CORPORATION OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF +// THE POSSIBILITY OF SUCH DAMAGE. +// +// + +// +// Module Name: +// +// setjmp.s +// +// Abstract: +// +// Contains an implementation of setjmp and longjmp for the +// IA-64 architecture. + + .file "setjmp.s" + +#define LOCORE +#include <machine/asm.h> +#include <machine/setjmp.h> + +// int _setjmp(struct jmp_buffer *) +// +// Setup a non-local goto. +// +// Description: +// +// SetJump stores the current register set in the area pointed to +// by "save". It returns zero. Subsequent calls to "LongJump" will +// restore the registers and return non-zero to the same location. +// +// On entry, r32 contains the pointer to the jmp_buffer +// + +ENTRY(_setjmp, 1) + // + // Make sure buffer is aligned at 16byte boundary + // + add r10 = -0x10,r0 ;; // mask the lower 4 bits + and r32 = r32, r10;; + add r32 = 0x10, r32;; // move to next 16 byte boundary + + add r10 = J_PREDS, r32 // skip Unats & pfs save area + add r11 = J_BSP, r32 + // + // save immediate context + // + mov r2 = ar.bsp // save backing store pointer + mov r3 = pr // save predicates + flushrs + ;; + // + // save user Unat register + // + mov r16 = ar.lc // save loop count register + mov r14 = ar.unat // save user Unat register + + st8 [r10] = r3, J_LC-J_PREDS + st8 [r11] = r2, J_R4-J_BSP + ;; + st8 [r10] = r16, J_R5-J_LC + st8 [r32] = r14, J_NATS // Note: Unat at the + // beginning of the save area + mov r15 = ar.pfs + ;; + // + // save preserved general registers & NaT's + // + st8.spill [r11] = r4, J_R6-J_R4 + ;; + st8.spill [r10] = r5, J_R7-J_R5 + ;; + st8.spill [r11] = r6, J_SP-J_R6 + ;; + st8.spill [r10] = r7, J_F3-J_R7 + ;; + st8.spill [r11] = sp, J_F2-J_SP + ;; + // + // save spilled Unat and pfs registers + // + mov r2 = ar.unat // save Unat register after spill + ;; + st8 [r32] = r2, J_PFS-J_NATS // save unat for spilled regs + ;; + st8 [r32] = r15 // save pfs + // + // save floating registers + // + stf.spill [r11] = f2, J_F4-J_F2 + stf.spill [r10] = f3, J_F5-J_F3 + ;; + stf.spill [r11] = f4, J_F16-J_F4 + stf.spill [r10] = f5, J_F17-J_F5 + ;; + stf.spill [r11] = f16, J_F18-J_F16 + stf.spill [r10] = f17, J_F19-J_F17 + ;; + stf.spill [r11] = f18, J_F20-J_F18 + stf.spill [r10] = f19, J_F21-J_F19 + ;; + stf.spill [r11] = f20, J_F22-J_F20 + stf.spill [r10] = f21, J_F23-J_F21 + ;; + stf.spill [r11] = f22, J_F24-J_F22 + stf.spill [r10] = f23, J_F25-J_F23 + ;; + stf.spill [r11] = f24, J_F26-J_F24 + stf.spill [r10] = f25, J_F27-J_F25 + ;; + stf.spill [r11] = f26, J_F28-J_F26 + stf.spill [r10] = f27, J_F29-J_F27 + ;; + stf.spill [r11] = f28, J_F30-J_F28 + stf.spill [r10] = f29, J_F31-J_F29 + ;; + stf.spill [r11] = f30, J_FPSR-J_F30 + stf.spill [r10] = f31, J_B0-J_F31 // size of f31 + fpsr + // + // save FPSR register & branch registers + // + mov r2 = ar.fpsr // save fpsr register + mov r3 = b0 + ;; + st8 [r11] = r2, J_B1-J_FPSR + st8 [r10] = r3, J_B2-J_B0 + mov r2 = b1 + mov r3 = b2 + ;; + st8 [r11] = r2, J_B3-J_B1 + st8 [r10] = r3, J_B4-J_B2 + mov r2 = b3 + mov r3 = b4 + ;; + st8 [r11] = r2, J_B5-J_B3 + st8 [r10] = r3 + mov r2 = b5 + ;; + st8 [r11] = r2 + ;; + // + // return + // + mov r8 = r0 // return 0 from setjmp + mov ar.unat = r14 // restore unat + br.ret.sptk b0 + +END(_setjmp) + + +// +// void _longjmp(struct jmp_buffer *, int val) +// +// Perform a non-local goto. +// +// Description: +// +// LongJump initializes the register set to the values saved by a +// previous 'SetJump' and jumps to the return location saved by that +// 'SetJump'. This has the effect of unwinding the stack and returning +// for a second time to the 'SetJump'. +// + + WEAK_ALIAS(_longjmp,___longjmp) +ENTRY(___longjmp, 2) + // + // Make sure buffer is aligned at 16byte boundary + // + add r10 = -0x10,r0 ;; // mask the lower 4 bits + and r32 = r32, r10;; + add r32 = 0x10, r32;; // move to next 16 byte boundary + + // + // caching the return value as we do invala in the end + // + mov r8 = r33 // return value + + // + // get immediate context + // + mov r14 = ar.rsc // get user RSC conf + add r10 = J_PFS, r32 // get address of pfs + add r11 = J_NATS, r32 + ;; + ld8 r15 = [r10], J_BSP-J_PFS // get pfs + ld8 r2 = [r11], J_LC-J_NATS // get unat for spilled regs + ;; + mov ar.unat = r2 + ;; + ld8 r16 = [r10], J_PREDS-J_BSP // get backing store pointer + mov ar.rsc = r0 // put RSE in enforced lazy + mov ar.pfs = r15 + ;; + + // + // while returning from longjmp the BSPSTORE and BSP needs to be + // same and discard all the registers allocated after we did + // setjmp. Also, we need to generate the RNAT register since we + // did not flushed the RSE on setjmp. + // + mov r17 = ar.bspstore // get current BSPSTORE + ;; + cmp.ltu p6,p7 = r17, r16 // is it less than BSP of +(p6) br.spnt.few .flush_rse + mov r19 = ar.rnat // get current RNAT + ;; + loadrs // invalidate dirty regs + br.sptk.many .restore_rnat // restore RNAT + +.flush_rse: + flushrs + ;; + mov r19 = ar.rnat // get current RNAT + mov r17 = r16 // current BSPSTORE + ;; +.restore_rnat: + // + // check if RNAT is saved between saved BSP and curr BSPSTORE + // + mov r18 = 0x3f + ;; + dep r18 = r18,r16,3,6 // get RNAT address + ;; + cmp.ltu p8,p9 = r18, r17 // RNAT saved on RSE + ;; +(p8) ld8 r19 = [r18] // get RNAT from RSE + ;; + mov ar.bspstore = r16 // set new BSPSTORE + ;; + mov ar.rnat = r19 // restore RNAT + mov ar.rsc = r14 // restore RSC conf + + + ld8 r3 = [r11], J_R4-J_LC // get lc register + ld8 r2 = [r10], J_R5-J_PREDS // get predicates + ;; + mov pr = r2, -1 + mov ar.lc = r3 + // + // restore preserved general registers & NaT's + // + ld8.fill r4 = [r11], J_R6-J_R4 + ;; + ld8.fill r5 = [r10], J_R7-J_R5 + ld8.fill r6 = [r11], J_SP-J_R6 + ;; + ld8.fill r7 = [r10], J_F2-J_R7 + ld8.fill sp = [r11], J_F3-J_SP + ;; + // + // restore floating registers + // + ldf.fill f2 = [r10], J_F4-J_F2 + ldf.fill f3 = [r11], J_F5-J_F3 + ;; + ldf.fill f4 = [r10], J_F16-J_F4 + ldf.fill f5 = [r11], J_F17-J_F5 + ;; + ldf.fill f16 = [r10], J_F18-J_F16 + ldf.fill f17 = [r11], J_F19-J_F17 + ;; + ldf.fill f18 = [r10], J_F20-J_F18 + ldf.fill f19 = [r11], J_F21-J_F19 + ;; + ldf.fill f20 = [r10], J_F22-J_F20 + ldf.fill f21 = [r11], J_F23-J_F21 + ;; + ldf.fill f22 = [r10], J_F24-J_F22 + ldf.fill f23 = [r11], J_F25-J_F23 + ;; + ldf.fill f24 = [r10], J_F26-J_F24 + ldf.fill f25 = [r11], J_F27-J_F25 + ;; + ldf.fill f26 = [r10], J_F28-J_F26 + ldf.fill f27 = [r11], J_F29-J_F27 + ;; + ldf.fill f28 = [r10], J_F30-J_F28 + ldf.fill f29 = [r11], J_F31-J_F29 + ;; + ldf.fill f30 = [r10], J_FPSR-J_F30 + ldf.fill f31 = [r11], J_B0-J_F31 ;; + + // + // restore branch registers and fpsr + // + ld8 r16 = [r10], J_B1-J_FPSR // get fpsr + ld8 r17 = [r11], J_B2-J_B0 // get return pointer + ;; + mov ar.fpsr = r16 + mov b0 = r17 + ld8 r2 = [r10], J_B3-J_B1 + ld8 r3 = [r11], J_B4-J_B2 + ;; + mov b1 = r2 + mov b2 = r3 + ld8 r2 = [r10], J_B5-J_B3 + ld8 r3 = [r11] + ;; + mov b3 = r2 + mov b4 = r3 + ld8 r2 = [r10] + ld8 r21 = [r32] // get user unat + ;; + mov b5 = r2 + mov ar.unat = r21 + + // + // invalidate ALAT + // + invala ;; + + br.ret.sptk b0 + +END(___longjmp) diff --git a/lib/libc/ia64/gen/fabs.S b/lib/libc/ia64/gen/fabs.S new file mode 100644 index 0000000..786606b --- /dev/null +++ b/lib/libc/ia64/gen/fabs.S @@ -0,0 +1,34 @@ +/*- + * Copyright (c) 2000 Doug Rabson + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#include <machine/asm.h> + +ENTRY(fabs, 1) + fabs fret0=farg0 + br.ret.sptk.few rp +END(fabs) diff --git a/lib/libc/ia64/gen/fpgetmask.c b/lib/libc/ia64/gen/fpgetmask.c new file mode 100644 index 0000000..f3beea8 --- /dev/null +++ b/lib/libc/ia64/gen/fpgetmask.c @@ -0,0 +1,40 @@ +/*- + * Copyright (c) 2001 Doug Rabson + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <sys/cdefs.h> +__FBSDID("$FreeBSD$"); + +#include <sys/types.h> +#include <ieeefp.h> + +fp_except_t +fpgetmask(void) +{ + u_int64_t fpsr; + + __asm __volatile("mov %0=ar.fpsr" : "=r" (fpsr)); + return (fpsr & 0x1f) ^ 0x1f; +} diff --git a/lib/libc/ia64/gen/fpsetmask.c b/lib/libc/ia64/gen/fpsetmask.c new file mode 100644 index 0000000..c69dccb --- /dev/null +++ b/lib/libc/ia64/gen/fpsetmask.c @@ -0,0 +1,44 @@ +/*- + * Copyright (c) 2001 Doug Rabson + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <sys/cdefs.h> +__FBSDID("$FreeBSD$"); + +#include <sys/types.h> +#include <ieeefp.h> + +fp_except_t +fpsetmask(fp_except_t mask) +{ + u_int64_t fpsr; + u_int64_t oldmask; + + __asm __volatile("mov %0=ar.fpsr" : "=r" (fpsr)); + oldmask = (fpsr & 0x1f) ^ 0x1f; + fpsr = (fpsr & ~0x1f) | (mask ^ 0x1f); + __asm __volatile("mov ar.fpsr=%0" :: "r" (fpsr)); + return oldmask; +} diff --git a/lib/libc/ia64/gen/frexp.c b/lib/libc/ia64/gen/frexp.c new file mode 100644 index 0000000..d4f5139 --- /dev/null +++ b/lib/libc/ia64/gen/frexp.c @@ -0,0 +1,56 @@ +/* $NetBSD: frexp.c,v 1.1 1995/02/10 17:50:22 cgd Exp $ */ + +/* + * Copyright (c) 1994, 1995 Carnegie-Mellon University. + * All rights reserved. + * + * Author: Chris G. Demetriou + * + * Permission to use, copy, modify and distribute this software and + * its documentation is hereby granted, provided that both the copyright + * notice and this permission notice appear in all copies of the + * software, derivative works or modified versions, and any portions + * thereof, and that both notices appear in supporting documentation. + * + * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" + * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND + * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. + * + * Carnegie Mellon requests users of this software to return to + * + * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU + * School of Computer Science + * Carnegie Mellon University + * Pittsburgh PA 15213-3890 + * + * any improvements or extensions that they make and grant Carnegie the + * rights to redistribute these changes. + */ + +#include <sys/cdefs.h> +__FBSDID("$FreeBSD$"); + +#include <sys/types.h> +#include <machine/ieee.h> +#include <math.h> + +double +frexp(value, eptr) + double value; + int *eptr; +{ + union doub { + double v; + struct ieee_double s; + } u; + + if (value) { + u.v = value; + *eptr = u.s.dbl_exp - (DBL_EXP_BIAS - 1); + u.s.dbl_exp = DBL_EXP_BIAS - 1; + return(u.v); + } else { + *eptr = 0; + return((double)0); + } +} diff --git a/lib/libc/ia64/gen/infinity.c b/lib/libc/ia64/gen/infinity.c new file mode 100644 index 0000000..a24cea8 --- /dev/null +++ b/lib/libc/ia64/gen/infinity.c @@ -0,0 +1,36 @@ +/* $NetBSD: infinity.c,v 1.1 1995/02/10 17:50:23 cgd Exp $ */ + +/* + * Copyright (c) 1994, 1995 Carnegie-Mellon University. + * All rights reserved. + * + * Author: Chris G. Demetriou + * + * Permission to use, copy, modify and distribute this software and + * its documentation is hereby granted, provided that both the copyright + * notice and this permission notice appear in all copies of the + * software, derivative works or modified versions, and any portions + * thereof, and that both notices appear in supporting documentation. + * + * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" + * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND + * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. + * + * Carnegie Mellon requests users of this software to return to + * + * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU + * School of Computer Science + * Carnegie Mellon University + * Pittsburgh PA 15213-3890 + * + * any improvements or extensions that they make and grant Carnegie the + * rights to redistribute these changes. + */ + +#include <sys/cdefs.h> +__FBSDID("$FreeBSD$"); + +#include <math.h> + +/* bytes for +Infinity on an ia64 (IEEE double format) */ +char __infinity[] = { 0, 0, 0, 0, 0, 0, 0xf0, 0x7f }; diff --git a/lib/libc/ia64/gen/isinf.c b/lib/libc/ia64/gen/isinf.c new file mode 100644 index 0000000..d878905 --- /dev/null +++ b/lib/libc/ia64/gen/isinf.c @@ -0,0 +1,55 @@ +/* $NetBSD: isinf.c,v 1.1 1995/02/10 17:50:23 cgd Exp $ */ + +/* + * Copyright (c) 1994, 1995 Carnegie-Mellon University. + * All rights reserved. + * + * Author: Chris G. Demetriou + * + * Permission to use, copy, modify and distribute this software and + * its documentation is hereby granted, provided that both the copyright + * notice and this permission notice appear in all copies of the + * software, derivative works or modified versions, and any portions + * thereof, and that both notices appear in supporting documentation. + * + * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" + * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND + * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. + * + * Carnegie Mellon requests users of this software to return to + * + * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU + * School of Computer Science + * Carnegie Mellon University + * Pittsburgh PA 15213-3890 + * + * any improvements or extensions that they make and grant Carnegie the + * rights to redistribute these changes. + */ + +#include <sys/cdefs.h> +__FBSDID("$FreeBSD$"); + +#include <sys/types.h> +#include <machine/ieee.h> +#include <math.h> + +int +isnan(d) + double d; +{ + struct ieee_double *p = (struct ieee_double *)&d; + + return (p->dbl_exp == DBL_EXP_INFNAN && + (p->dbl_frach || p->dbl_fracl)); +} + +int +isinf(d) + double d; +{ + struct ieee_double *p = (struct ieee_double *)&d; + + return (p->dbl_exp == DBL_EXP_INFNAN && + !p->dbl_frach && !p->dbl_fracl); +} diff --git a/lib/libc/ia64/gen/ldexp.c b/lib/libc/ia64/gen/ldexp.c new file mode 100644 index 0000000..c431417 --- /dev/null +++ b/lib/libc/ia64/gen/ldexp.c @@ -0,0 +1,137 @@ +/* $NetBSD: ldexp.c,v 1.1 1995/02/10 17:50:24 cgd Exp $ */ + +/* + * Copyright (c) 1994, 1995 Carnegie-Mellon University. + * All rights reserved. + * + * Author: Chris G. Demetriou + * + * Permission to use, copy, modify and distribute this software and + * its documentation is hereby granted, provided that both the copyright + * notice and this permission notice appear in all copies of the + * software, derivative works or modified versions, and any portions + * thereof, and that both notices appear in supporting documentation. + * + * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" + * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND + * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. + * + * Carnegie Mellon requests users of this software to return to + * + * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU + * School of Computer Science + * Carnegie Mellon University + * Pittsburgh PA 15213-3890 + * + * any improvements or extensions that they make and grant Carnegie the + * rights to redistribute these changes. + */ + +#include <sys/cdefs.h> +__FBSDID("$FreeBSD$"); + +#include <sys/types.h> +#include <machine/ieee.h> +#include <errno.h> +#include <math.h> + +/* + * double ldexp(double val, int exp) + * returns: val * (2**exp) + */ +double +ldexp(val, exp) + double val; + int exp; +{ + int oldexp, newexp, mulexp; + union doub { + double v; + struct ieee_double s; + } u, mul; + + /* + * If input is zero, or no change, just return input. + * Likewise, if input is Inf or NaN, just return it. + */ + u.v = val; + oldexp = u.s.dbl_exp; + if (val == 0 || exp == 0 || oldexp == DBL_EXP_INFNAN) + return (val); + + /* + * Compute new exponent and check for over/under flow. + * Underflow, unfortunately, could mean switching to denormal. + * If result out of range, set ERANGE and return 0 if too small + * or Inf if too big, with the same sign as the input value. + */ + newexp = oldexp + exp; + if (newexp >= DBL_EXP_INFNAN) { + /* u.s.dbl_sign = val < 0; -- already set */ + u.s.dbl_exp = DBL_EXP_INFNAN; + u.s.dbl_frach = u.s.dbl_fracl = 0; + errno = ERANGE; + return (u.v); /* Inf */ + } + if (newexp <= 0) { + /* + * The output number is either a denormal or underflows + * (see comments in machine/ieee.h). + */ + if (newexp <= -DBL_FRACBITS) { + /* u.s.dbl_sign = val < 0; -- already set */ + u.s.dbl_exp = 0; + u.s.dbl_frach = u.s.dbl_fracl = 0; + errno = ERANGE; + return (u.v); /* zero */ + } + /* + * We are going to produce a denorm. Our `exp' argument + * might be as small as -2097, and we cannot compute + * 2^-2097, so we may have to do this as many as three + * steps (not just two, as for positive `exp's below). + */ + mul.v = 0; + while (exp <= -DBL_EXP_BIAS) { + mul.s.dbl_exp = 1; + val *= mul.v; + exp += DBL_EXP_BIAS - 1; + } + mul.s.dbl_exp = exp + DBL_EXP_BIAS; + val *= mul.v; + return (val); + } + + /* + * Newexp is positive. + * + * If oldexp is zero, we are starting with a denorm, and simply + * adjusting the exponent will produce bogus answers. We need + * to fix that first. + */ + if (oldexp == 0) { + /* + * Multiply by 2^mulexp to make the number normalizable. + * We cannot multiply by more than 2^1023, but `exp' + * argument might be as large as 2046. A single + * adjustment, however, will normalize the number even + * for huge `exp's, and then we can use exponent + * arithmetic just as for normal `double's. + */ + mulexp = exp <= DBL_EXP_BIAS ? exp : DBL_EXP_BIAS; + mul.v = 0; + mul.s.dbl_exp = mulexp + DBL_EXP_BIAS; + val *= mul.v; + if (mulexp == exp) + return (val); + u.v = val; + newexp -= mulexp; + } + + /* + * Both oldexp and newexp are positive; just replace the + * old exponent with the new one. + */ + u.s.dbl_exp = newexp; + return (u.v); +} diff --git a/lib/libc/ia64/gen/modf.c b/lib/libc/ia64/gen/modf.c new file mode 100644 index 0000000..def3aad --- /dev/null +++ b/lib/libc/ia64/gen/modf.c @@ -0,0 +1,106 @@ +/* $NetBSD: modf.c,v 1.1 1995/02/10 17:50:25 cgd Exp $ */ + +/* + * Copyright (c) 1994, 1995 Carnegie-Mellon University. + * All rights reserved. + * + * Author: Chris G. Demetriou + * + * Permission to use, copy, modify and distribute this software and + * its documentation is hereby granted, provided that both the copyright + * notice and this permission notice appear in all copies of the + * software, derivative works or modified versions, and any portions + * thereof, and that both notices appear in supporting documentation. + * + * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" + * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND + * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. + * + * Carnegie Mellon requests users of this software to return to + * + * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU + * School of Computer Science + * Carnegie Mellon University + * Pittsburgh PA 15213-3890 + * + * any improvements or extensions that they make and grant Carnegie the + * rights to redistribute these changes. + */ + +#include <sys/cdefs.h> +__FBSDID("$FreeBSD$"); + +#include <sys/types.h> +#include <machine/ieee.h> +#include <math.h> + +/* + * double modf(double val, double *iptr) + * returns: f and i such that |f| < 1.0, (f + i) = val, and + * sign(f) == sign(i) == sign(val). + * + * Beware signedness when doing subtraction, and also operand size! + */ +double +modf(val, iptr) + double val, *iptr; +{ + union doub { + double v; + struct ieee_double s; + } u, v; + u_int64_t frac; + + /* + * If input is Inf or NaN, return it and leave i alone. + */ + u.v = val; + if (u.s.dbl_exp == DBL_EXP_INFNAN) + return (u.v); + + /* + * If input can't have a fractional part, return + * (appropriately signed) zero, and make i be the input. + */ + if ((int)u.s.dbl_exp - DBL_EXP_BIAS > DBL_FRACBITS - 1) { + *iptr = u.v; + v.v = 0.0; + v.s.dbl_sign = u.s.dbl_sign; + return (v.v); + } + + /* + * If |input| < 1.0, return it, and set i to the appropriately + * signed zero. + */ + if (u.s.dbl_exp < DBL_EXP_BIAS) { + v.v = 0.0; + v.s.dbl_sign = u.s.dbl_sign; + *iptr = v.v; + return (u.v); + } + + /* + * There can be a fractional part of the input. + * If you look at the math involved for a few seconds, it's + * plain to see that the integral part is the input, with the + * low (DBL_FRACBITS - (exponent - DBL_EXP_BIAS)) bits zeroed, + * the the fractional part is the part with the rest of the + * bits zeroed. Just zeroing the high bits to get the + * fractional part would yield a fraction in need of + * normalization. Therefore, we take the easy way out, and + * just use subtraction to get the fractional part. + */ + v.v = u.v; + /* Zero the low bits of the fraction, the sleazy way. */ + frac = ((u_int64_t)v.s.dbl_frach << 32) + v.s.dbl_fracl; + frac >>= DBL_FRACBITS - (u.s.dbl_exp - DBL_EXP_BIAS); + frac <<= DBL_FRACBITS - (u.s.dbl_exp - DBL_EXP_BIAS); + v.s.dbl_fracl = frac & 0xffffffff; + v.s.dbl_frach = frac >> 32; + *iptr = v.v; + + u.v -= v.v; + u.s.dbl_sign = v.s.dbl_sign; + return (u.v); +} diff --git a/lib/libc/ia64/gen/setjmp.S b/lib/libc/ia64/gen/setjmp.S new file mode 100644 index 0000000..0ba630b --- /dev/null +++ b/lib/libc/ia64/gen/setjmp.S @@ -0,0 +1,89 @@ +/* $NetBSD: setjmp.S,v 1.3 1997/12/05 02:06:27 thorpej Exp $ */ +/* $FreeBSD$ */ + +/* + * Copyright (c) 1994, 1995 Carnegie-Mellon University. + * All rights reserved. + * + * Author: Chris G. Demetriou + * + * Permission to use, copy, modify and distribute this software and + * its documentation is hereby granted, provided that both the copyright + * notice and this permission notice appear in all copies of the + * software, derivative works or modified versions, and any portions + * thereof, and that both notices appear in supporting documentation. + * + * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" + * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND + * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. + * + * Carnegie Mellon requests users of this software to return to + * + * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU + * School of Computer Science + * Carnegie Mellon University + * Pittsburgh PA 15213-3890 + * + * any improvements or extensions that they make and grant Carnegie the + * rights to redistribute these changes. + */ + +#define LOCORE +#include <machine/asm.h> +#include <machine/setjmp.h> + +/* + * C library -- setjmp, longjmp + * + * longjmp(a,v) + * will generate a "return(v)" from + * the last call to + * setjmp(a) + * by restoring registers from the stack, + * and the previous signal state. + */ + +ENTRY(setjmp, 1) + alloc loc0=ar.pfs,1,2,3,0 + mov loc1=rp + // + // Compensate for the pointer twiddling that setjmp does. + // + dep r14=r0,r32,0,4 + ;; + mov out0=1 // how = SIG_BLOCK + mov out1=0 // set = NULL + add out2=J_SIG0+0x10,r14 // oset = &jb[J_SIG0] + br.call.sptk.few rp=__sys_sigprocmask + ;; + mov rp=loc1 + mov r14=loc0 + ;; + alloc r15=ar.pfs,1,0,0,0 // drop register frame + ;; + mov ar.pfs=r14 // restore ar.pfs + br.sptk.many _setjmp // finish saving state +END(setjmp) + + WEAK_ALIAS(longjmp,__longjmp) +ENTRY(__longjmp, 2) + alloc loc0=ar.pfs,2,2,3,0 + mov loc1=rp + // + // Compensate for the pointer twiddling that setjmp does. + // + dep r14=r0,r32,0,4 + ;; + mov out0=3 // how = SIG_SETMASK + add out1=J_SIG0+0x10,r14 // set = &jb[J_SIG0] + mov out2=0 // oset = NULL + br.call.sptk.few rp=__sys_sigprocmask + ;; + mov rp=loc1 + mov r14=loc0 + ;; + alloc r15=ar.pfs,2,0,0,0 // drop register frame + ;; + mov ar.pfs=r14 // restore ar.pfs + br.sptk.many _longjmp // finish restoring state +END(__longjmp) diff --git a/lib/libc/ia64/gen/sigsetjmp.S b/lib/libc/ia64/gen/sigsetjmp.S new file mode 100644 index 0000000..e3a9768 --- /dev/null +++ b/lib/libc/ia64/gen/sigsetjmp.S @@ -0,0 +1,75 @@ +/* $NetBSD: sigsetjmp.S,v 1.2 1996/10/17 03:08:07 cgd Exp $ */ +/* $FreeBSD$ */ + +/* + * Copyright (c) 1994, 1995 Carnegie-Mellon University. + * All rights reserved. + * + * Author: Chris G. Demetriou + * + * Permission to use, copy, modify and distribute this software and + * its documentation is hereby granted, provided that both the copyright + * notice and this permission notice appear in all copies of the + * software, derivative works or modified versions, and any portions + * thereof, and that both notices appear in supporting documentation. + * + * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" + * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND + * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. + * + * Carnegie Mellon requests users of this software to return to + * + * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU + * School of Computer Science + * Carnegie Mellon University + * Pittsburgh PA 15213-3890 + * + * any improvements or extensions that they make and grant Carnegie the + * rights to redistribute these changes. + */ + +#define LOCORE +#include <machine/asm.h> +#include <machine/setjmp.h> + +/* + * C library -- sigsetjmp, siglongjmp + * + * siglongjmp(a,v) + * will generate a "return(v)" from + * the last call to + * sigsetjmp(a, mask) + * by restoring registers from the stack. + * If `mask' is non-zero, the previous signal + * state will be restored. + */ + +ENTRY(sigsetjmp, 2) + // + // Compensate for the pointer twiddling that setjmp does. + // + dep r14=r0,r32,0,4 + ;; + add r14=J_SIGMASK+0x10,r14 // place to save mask + ;; + st8 [r14]=in1 // save mask value + cmp.ne p6,p7=0,in1 // save signal state? +(p6) br.cond.dptk.many setjmp +(p7) br.cond.dpnt.many _setjmp +END(sigsetjmp) + + WEAK_ALIAS(siglongjmp,__siglongjmp) +ENTRY(__siglongjmp, 2) + // + // Compensate for the pointer twiddling that setjmp does. + // + dep r14=r0,r32,0,4 + ;; + add r14=J_SIGMASK+0x10,r14 // address of mask value + ;; + ld8 r14=[r14] + ;; + cmp.ne p6,p7=0,r14 // did we save signals? +(p6) br.cond.dptk.many longjmp +(p7) br.cond.dpnt.many _longjmp +END(__siglongjmp) |
