summaryrefslogtreecommitdiffstats
path: root/lib/clang/libllvmcodegen/Makefile
diff options
context:
space:
mode:
Diffstat (limited to 'lib/clang/libllvmcodegen/Makefile')
-rw-r--r--lib/clang/libllvmcodegen/Makefile108
1 files changed, 78 insertions, 30 deletions
diff --git a/lib/clang/libllvmcodegen/Makefile b/lib/clang/libllvmcodegen/Makefile
index e233226..caed836 100644
--- a/lib/clang/libllvmcodegen/Makefile
+++ b/lib/clang/libllvmcodegen/Makefile
@@ -3,36 +3,84 @@
LIB= llvmcodegen
SRCDIR= lib/CodeGen
-SRCS= AggressiveAntiDepBreaker.cpp Analysis.cpp BranchFolding.cpp \
- CalcSpillWeights.cpp CodePlacementOpt.cpp \
- CriticalAntiDepBreaker.cpp DeadMachineInstructionElim.cpp \
- DwarfEHPrepare.cpp ELFCodeEmitter.cpp ELFWriter.cpp \
- ExactHazardRecognizer.cpp GCMetadata.cpp GCStrategy.cpp \
- IfConversion.cpp IntrinsicLowering.cpp LLVMTargetMachine.cpp \
- LatencyPriorityQueue.cpp LiveInterval.cpp \
- LiveIntervalAnalysis.cpp LiveStackAnalysis.cpp \
- LiveVariables.cpp LowerSubregs.cpp MachineBasicBlock.cpp \
- MachineCSE.cpp MachineDominators.cpp MachineFunction.cpp \
- MachineFunctionAnalysis.cpp MachineFunctionPass.cpp \
- MachineFunctionPrinterPass.cpp MachineInstr.cpp \
- MachineLICM.cpp MachineLoopInfo.cpp MachineModuleInfo.cpp \
- MachineModuleInfoImpls.cpp MachinePassRegistry.cpp \
- MachineRegisterInfo.cpp MachineSSAUpdater.cpp MachineSink.cpp \
- MachineVerifier.cpp ObjectCodeEmitter.cpp OcamlGC.cpp \
- OptimizeExts.cpp OptimizePHIs.cpp PHIElimination.cpp \
- Passes.cpp PostRASchedulerList.cpp PreAllocSplitting.cpp \
- ProcessImplicitDefs.cpp PrologEpilogInserter.cpp \
- PseudoSourceValue.cpp RegAllocFast.cpp RegAllocLinearScan.cpp \
- RegAllocLocal.cpp RegAllocPBQP.cpp RegisterCoalescer.cpp \
- RegisterScavenging.cpp ScheduleDAG.cpp ScheduleDAGEmit.cpp \
- ScheduleDAGInstrs.cpp ScheduleDAGPrinter.cpp ShadowStackGC.cpp \
- ShrinkWrapping.cpp SimpleRegisterCoalescing.cpp \
- SjLjEHPrepare.cpp SlotIndexes.cpp Spiller.cpp \
- StackProtector.cpp StackSlotColoring.cpp \
- StrongPHIElimination.cpp TailDuplication.cpp \
- TargetInstrInfoImpl.cpp TargetLoweringObjectFileImpl.cpp \
- TwoAddressInstructionPass.cpp UnreachableBlockElim.cpp \
- VirtRegMap.cpp VirtRegRewriter.cpp
+SRCS= AggressiveAntiDepBreaker.cpp \
+ Analysis.cpp \
+ BranchFolding.cpp \
+ CalcSpillWeights.cpp \
+ CallingConvLower.cpp \
+ CodePlacementOpt.cpp \
+ CriticalAntiDepBreaker.cpp \
+ DeadMachineInstructionElim.cpp \
+ DwarfEHPrepare.cpp \
+ ELFCodeEmitter.cpp \
+ ELFWriter.cpp \
+ GCMetadata.cpp \
+ GCMetadataPrinter.cpp \
+ GCStrategy.cpp \
+ IfConversion.cpp \
+ InlineSpiller.cpp \
+ IntrinsicLowering.cpp \
+ LLVMTargetMachine.cpp \
+ LatencyPriorityQueue.cpp \
+ LiveInterval.cpp \
+ LiveIntervalAnalysis.cpp \
+ LiveStackAnalysis.cpp \
+ LiveVariables.cpp \
+ LowerSubregs.cpp \
+ MachineBasicBlock.cpp \
+ MachineCSE.cpp \
+ MachineDominators.cpp \
+ MachineFunction.cpp \
+ MachineFunctionAnalysis.cpp \
+ MachineFunctionPass.cpp \
+ MachineFunctionPrinterPass.cpp \
+ MachineInstr.cpp \
+ MachineLICM.cpp \
+ MachineLoopInfo.cpp \
+ MachineModuleInfo.cpp \
+ MachineModuleInfoImpls.cpp \
+ MachinePassRegistry.cpp \
+ MachineRegisterInfo.cpp \
+ MachineSSAUpdater.cpp \
+ MachineSink.cpp \
+ MachineVerifier.cpp \
+ ObjectCodeEmitter.cpp \
+ OcamlGC.cpp \
+ OptimizeExts.cpp \
+ OptimizePHIs.cpp \
+ PHIElimination.cpp \
+ Passes.cpp \
+ PostRAHazardRecognizer.cpp \
+ PostRASchedulerList.cpp \
+ PreAllocSplitting.cpp \
+ ProcessImplicitDefs.cpp \
+ PrologEpilogInserter.cpp \
+ PseudoSourceValue.cpp \
+ RegAllocFast.cpp \
+ RegAllocLinearScan.cpp \
+ RegAllocPBQP.cpp \
+ RegisterCoalescer.cpp \
+ RegisterScavenging.cpp \
+ ScheduleDAG.cpp \
+ ScheduleDAGEmit.cpp \
+ ScheduleDAGInstrs.cpp \
+ ScheduleDAGPrinter.cpp \
+ ShadowStackGC.cpp \
+ ShrinkWrapping.cpp \
+ SimpleRegisterCoalescing.cpp \
+ SjLjEHPrepare.cpp \
+ SlotIndexes.cpp \
+ Spiller.cpp \
+ StackProtector.cpp \
+ StackSlotColoring.cpp \
+ StrongPHIElimination.cpp \
+ TailDuplication.cpp \
+ TargetInstrInfoImpl.cpp \
+ TargetLoweringObjectFileImpl.cpp \
+ TwoAddressInstructionPass.cpp \
+ UnreachableBlockElim.cpp \
+ VirtRegMap.cpp \
+ VirtRegRewriter.cpp
TGHDRS= Intrinsics
OpenPOWER on IntegriCloud