diff options
Diffstat (limited to 'lib/Target/SystemZ')
20 files changed, 564 insertions, 491 deletions
diff --git a/lib/Target/SystemZ/AsmPrinter/CMakeLists.txt b/lib/Target/SystemZ/AsmPrinter/CMakeLists.txt deleted file mode 100644 index c6be83a..0000000 --- a/lib/Target/SystemZ/AsmPrinter/CMakeLists.txt +++ /dev/null @@ -1,6 +0,0 @@ -include_directories( ${CMAKE_CURRENT_BINARY_DIR}/.. ${CMAKE_CURRENT_SOURCE_DIR}/.. ) - -add_llvm_library(LLVMSystemZAsmPrinter - SystemZAsmPrinter.cpp - ) -add_dependencies(LLVMSystemZAsmPrinter SystemZCodeGenTable_gen) diff --git a/lib/Target/SystemZ/AsmPrinter/Makefile b/lib/Target/SystemZ/AsmPrinter/Makefile deleted file mode 100644 index 0f90ed3..0000000 --- a/lib/Target/SystemZ/AsmPrinter/Makefile +++ /dev/null @@ -1,15 +0,0 @@ -##===- lib/Target/SystemZ/AsmPrinter/Makefile --------------*- Makefile -*-===## -# -# The LLVM Compiler Infrastructure -# -# This file is distributed under the University of Illinois Open Source -# License. See LICENSE.TXT for details. -# -##===----------------------------------------------------------------------===## -LEVEL = ../../../.. -LIBRARYNAME = LLVMSystemZAsmPrinter - -# Hack: we need to include 'main' SystemZ target directory to grab private headers -CPP.Flags += -I$(PROJ_OBJ_DIR)/.. -I$(PROJ_SRC_DIR)/.. - -include $(LEVEL)/Makefile.common diff --git a/lib/Target/SystemZ/CMakeLists.txt b/lib/Target/SystemZ/CMakeLists.txt index 880e56f..1f5d355 100644 --- a/lib/Target/SystemZ/CMakeLists.txt +++ b/lib/Target/SystemZ/CMakeLists.txt @@ -11,9 +11,11 @@ tablegen(SystemZGenCallingConv.inc -gen-callingconv) tablegen(SystemZGenSubtarget.inc -gen-subtarget) add_llvm_target(SystemZCodeGen + SystemZAsmPrinter.cpp SystemZISelDAGToDAG.cpp SystemZISelLowering.cpp SystemZInstrInfo.cpp + SystemZFrameLowering.cpp SystemZMCAsmInfo.cpp SystemZRegisterInfo.cpp SystemZSubtarget.cpp @@ -21,4 +23,4 @@ add_llvm_target(SystemZCodeGen SystemZSelectionDAGInfo.cpp ) -target_link_libraries (LLVMSystemZCodeGen LLVMSelectionDAG) +add_subdirectory(TargetInfo) diff --git a/lib/Target/SystemZ/Makefile b/lib/Target/SystemZ/Makefile index 5b44090..6930e14 100644 --- a/lib/Target/SystemZ/Makefile +++ b/lib/Target/SystemZ/Makefile @@ -17,7 +17,7 @@ BUILT_SOURCES = SystemZGenRegisterInfo.h.inc SystemZGenRegisterNames.inc \ SystemZGenInstrInfo.inc SystemZGenAsmWriter.inc \ SystemZGenDAGISel.inc SystemZGenSubtarget.inc SystemZGenCallingConv.inc -DIRS = AsmPrinter TargetInfo +DIRS = TargetInfo include $(LEVEL)/Makefile.common diff --git a/lib/Target/SystemZ/AsmPrinter/SystemZAsmPrinter.cpp b/lib/Target/SystemZ/SystemZAsmPrinter.cpp index d7ac8f5..fd4d8b7 100644 --- a/lib/Target/SystemZ/AsmPrinter/SystemZAsmPrinter.cpp +++ b/lib/Target/SystemZ/SystemZAsmPrinter.cpp @@ -55,9 +55,15 @@ namespace { void printS16ImmOperand(const MachineInstr *MI, int OpNum, raw_ostream &O) { O << (int16_t)MI->getOperand(OpNum).getImm(); } + void printU16ImmOperand(const MachineInstr *MI, int OpNum, raw_ostream &O) { + O << (uint16_t)MI->getOperand(OpNum).getImm(); + } void printS32ImmOperand(const MachineInstr *MI, int OpNum, raw_ostream &O) { O << (int32_t)MI->getOperand(OpNum).getImm(); } + void printU32ImmOperand(const MachineInstr *MI, int OpNum, raw_ostream &O) { + O << (uint32_t)MI->getOperand(OpNum).getImm(); + } void printInstruction(const MachineInstr *MI, raw_ostream &O); static const char *getRegisterName(unsigned RegNo); diff --git a/lib/Target/SystemZ/SystemZFrameLowering.cpp b/lib/Target/SystemZ/SystemZFrameLowering.cpp new file mode 100644 index 0000000..2ad84a2 --- /dev/null +++ b/lib/Target/SystemZ/SystemZFrameLowering.cpp @@ -0,0 +1,386 @@ +//=====- SystemZFrameLowering.cpp - SystemZ Frame Information ------*- C++ -*-====// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file contains the SystemZ implementation of TargetFrameLowering class. +// +//===----------------------------------------------------------------------===// + +#include "SystemZFrameLowering.h" +#include "SystemZInstrBuilder.h" +#include "SystemZInstrInfo.h" +#include "SystemZMachineFunctionInfo.h" +#include "llvm/Function.h" +#include "llvm/CodeGen/MachineFrameInfo.h" +#include "llvm/CodeGen/MachineFunction.h" +#include "llvm/CodeGen/MachineInstrBuilder.h" +#include "llvm/CodeGen/MachineModuleInfo.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/Target/TargetData.h" +#include "llvm/Target/TargetOptions.h" +#include "llvm/Support/CommandLine.h" + +using namespace llvm; + +SystemZFrameLowering::SystemZFrameLowering(const SystemZSubtarget &sti) + : TargetFrameLowering(TargetFrameLowering::StackGrowsDown, 8, -160), STI(sti) { + // Fill the spill offsets map + static const unsigned SpillOffsTab[][2] = { + { SystemZ::R2D, 0x10 }, + { SystemZ::R3D, 0x18 }, + { SystemZ::R4D, 0x20 }, + { SystemZ::R5D, 0x28 }, + { SystemZ::R6D, 0x30 }, + { SystemZ::R7D, 0x38 }, + { SystemZ::R8D, 0x40 }, + { SystemZ::R9D, 0x48 }, + { SystemZ::R10D, 0x50 }, + { SystemZ::R11D, 0x58 }, + { SystemZ::R12D, 0x60 }, + { SystemZ::R13D, 0x68 }, + { SystemZ::R14D, 0x70 }, + { SystemZ::R15D, 0x78 } + }; + + RegSpillOffsets.grow(SystemZ::NUM_TARGET_REGS); + + for (unsigned i = 0, e = array_lengthof(SpillOffsTab); i != e; ++i) + RegSpillOffsets[SpillOffsTab[i][0]] = SpillOffsTab[i][1]; +} + +/// needsFP - Return true if the specified function should have a dedicated +/// frame pointer register. This is true if the function has variable sized +/// allocas or if frame pointer elimination is disabled. +bool SystemZFrameLowering::hasFP(const MachineFunction &MF) const { + const MachineFrameInfo *MFI = MF.getFrameInfo(); + return DisableFramePointerElim(MF) || MFI->hasVarSizedObjects(); +} + +/// emitSPUpdate - Emit a series of instructions to increment / decrement the +/// stack pointer by a constant value. +static +void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, + int64_t NumBytes, const TargetInstrInfo &TII) { + unsigned Opc; uint64_t Chunk; + bool isSub = NumBytes < 0; + uint64_t Offset = isSub ? -NumBytes : NumBytes; + + if (Offset >= (1LL << 15) - 1) { + Opc = SystemZ::ADD64ri32; + Chunk = (1LL << 31) - 1; + } else { + Opc = SystemZ::ADD64ri16; + Chunk = (1LL << 15) - 1; + } + + DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); + + while (Offset) { + uint64_t ThisVal = (Offset > Chunk) ? Chunk : Offset; + MachineInstr *MI = + BuildMI(MBB, MBBI, DL, TII.get(Opc), SystemZ::R15D) + .addReg(SystemZ::R15D).addImm(isSub ? -ThisVal : ThisVal); + // The PSW implicit def is dead. + MI->getOperand(3).setIsDead(); + Offset -= ThisVal; + } +} + +void SystemZFrameLowering::emitPrologue(MachineFunction &MF) const { + MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB + MachineFrameInfo *MFI = MF.getFrameInfo(); + const SystemZInstrInfo &TII = + *static_cast<const SystemZInstrInfo*>(MF.getTarget().getInstrInfo()); + SystemZMachineFunctionInfo *SystemZMFI = + MF.getInfo<SystemZMachineFunctionInfo>(); + MachineBasicBlock::iterator MBBI = MBB.begin(); + DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); + + // Get the number of bytes to allocate from the FrameInfo. + // Note that area for callee-saved stuff is already allocated, thus we need to + // 'undo' the stack movement. + uint64_t StackSize = MFI->getStackSize(); + StackSize -= SystemZMFI->getCalleeSavedFrameSize(); + + uint64_t NumBytes = StackSize - getOffsetOfLocalArea(); + + // Skip the callee-saved push instructions. + while (MBBI != MBB.end() && + (MBBI->getOpcode() == SystemZ::MOV64mr || + MBBI->getOpcode() == SystemZ::MOV64mrm)) + ++MBBI; + + if (MBBI != MBB.end()) + DL = MBBI->getDebugLoc(); + + // adjust stack pointer: R15 -= numbytes + if (StackSize || MFI->hasCalls()) { + assert(MF.getRegInfo().isPhysRegUsed(SystemZ::R15D) && + "Invalid stack frame calculation!"); + emitSPUpdate(MBB, MBBI, -(int64_t)NumBytes, TII); + } + + if (hasFP(MF)) { + // Update R11 with the new base value... + BuildMI(MBB, MBBI, DL, TII.get(SystemZ::MOV64rr), SystemZ::R11D) + .addReg(SystemZ::R15D); + + // Mark the FramePtr as live-in in every block except the entry. + for (MachineFunction::iterator I = llvm::next(MF.begin()), E = MF.end(); + I != E; ++I) + I->addLiveIn(SystemZ::R11D); + + } +} + +void SystemZFrameLowering::emitEpilogue(MachineFunction &MF, + MachineBasicBlock &MBB) const { + const MachineFrameInfo *MFI = MF.getFrameInfo(); + MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr(); + const SystemZInstrInfo &TII = + *static_cast<const SystemZInstrInfo*>(MF.getTarget().getInstrInfo()); + SystemZMachineFunctionInfo *SystemZMFI = + MF.getInfo<SystemZMachineFunctionInfo>(); + unsigned RetOpcode = MBBI->getOpcode(); + + switch (RetOpcode) { + case SystemZ::RET: break; // These are ok + default: + assert(0 && "Can only insert epilog into returning blocks"); + } + + // Get the number of bytes to allocate from the FrameInfo + // Note that area for callee-saved stuff is already allocated, thus we need to + // 'undo' the stack movement. + uint64_t StackSize = + MFI->getStackSize() - SystemZMFI->getCalleeSavedFrameSize(); + uint64_t NumBytes = StackSize - getOffsetOfLocalArea(); + + // Skip the final terminator instruction. + while (MBBI != MBB.begin()) { + MachineBasicBlock::iterator PI = prior(MBBI); + --MBBI; + if (!PI->getDesc().isTerminator()) + break; + } + + // During callee-saved restores emission stack frame was not yet finialized + // (and thus - the stack size was unknown). Tune the offset having full stack + // size in hands. + if (StackSize || MFI->hasCalls()) { + assert((MBBI->getOpcode() == SystemZ::MOV64rmm || + MBBI->getOpcode() == SystemZ::MOV64rm) && + "Expected to see callee-save register restore code"); + assert(MF.getRegInfo().isPhysRegUsed(SystemZ::R15D) && + "Invalid stack frame calculation!"); + + unsigned i = 0; + MachineInstr &MI = *MBBI; + while (!MI.getOperand(i).isImm()) { + ++i; + assert(i < MI.getNumOperands() && "Unexpected restore code!"); + } + + uint64_t Offset = NumBytes + MI.getOperand(i).getImm(); + // If Offset does not fit into 20-bit signed displacement field we need to + // emit some additional code... + if (Offset > 524287) { + // Fold the displacement into load instruction as much as possible. + NumBytes = Offset - 524287; + Offset = 524287; + emitSPUpdate(MBB, MBBI, NumBytes, TII); + } + + MI.getOperand(i).ChangeToImmediate(Offset); + } +} + +int SystemZFrameLowering::getFrameIndexOffset(const MachineFunction &MF, + int FI) const { + const MachineFrameInfo *MFI = MF.getFrameInfo(); + const SystemZMachineFunctionInfo *SystemZMFI = + MF.getInfo<SystemZMachineFunctionInfo>(); + int Offset = MFI->getObjectOffset(FI) + MFI->getOffsetAdjustment(); + uint64_t StackSize = MFI->getStackSize(); + + // Fixed objects are really located in the "previous" frame. + if (FI < 0) + StackSize -= SystemZMFI->getCalleeSavedFrameSize(); + + Offset += StackSize - getOffsetOfLocalArea(); + + // Skip the register save area if we generated the stack frame. + if (StackSize || MFI->hasCalls()) + Offset -= getOffsetOfLocalArea(); + + return Offset; +} + +bool +SystemZFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MI, + const std::vector<CalleeSavedInfo> &CSI, + const TargetRegisterInfo *TRI) const { + if (CSI.empty()) + return false; + + DebugLoc DL; + if (MI != MBB.end()) DL = MI->getDebugLoc(); + + MachineFunction &MF = *MBB.getParent(); + const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); + SystemZMachineFunctionInfo *MFI = MF.getInfo<SystemZMachineFunctionInfo>(); + unsigned CalleeFrameSize = 0; + + // Scan the callee-saved and find the bounds of register spill area. + unsigned LowReg = 0, HighReg = 0, StartOffset = -1U, EndOffset = 0; + for (unsigned i = 0, e = CSI.size(); i != e; ++i) { + unsigned Reg = CSI[i].getReg(); + if (!SystemZ::FP64RegClass.contains(Reg)) { + unsigned Offset = RegSpillOffsets[Reg]; + CalleeFrameSize += 8; + if (StartOffset > Offset) { + LowReg = Reg; StartOffset = Offset; + } + if (EndOffset < Offset) { + HighReg = Reg; EndOffset = RegSpillOffsets[Reg]; + } + } + } + + // Save information for epilogue inserter. + MFI->setCalleeSavedFrameSize(CalleeFrameSize); + MFI->setLowReg(LowReg); MFI->setHighReg(HighReg); + + // Save GPRs + if (StartOffset) { + // Build a store instruction. Use STORE MULTIPLE instruction if there are many + // registers to store, otherwise - just STORE. + MachineInstrBuilder MIB = + BuildMI(MBB, MI, DL, TII.get((LowReg == HighReg ? + SystemZ::MOV64mr : SystemZ::MOV64mrm))); + + // Add store operands. + MIB.addReg(SystemZ::R15D).addImm(StartOffset); + if (LowReg == HighReg) + MIB.addReg(0); + MIB.addReg(LowReg, RegState::Kill); + if (LowReg != HighReg) + MIB.addReg(HighReg, RegState::Kill); + + // Do a second scan adding regs as being killed by instruction + for (unsigned i = 0, e = CSI.size(); i != e; ++i) { + unsigned Reg = CSI[i].getReg(); + // Add the callee-saved register as live-in. It's killed at the spill. + MBB.addLiveIn(Reg); + if (Reg != LowReg && Reg != HighReg) + MIB.addReg(Reg, RegState::ImplicitKill); + } + } + + // Save FPRs + for (unsigned i = 0, e = CSI.size(); i != e; ++i) { + unsigned Reg = CSI[i].getReg(); + if (SystemZ::FP64RegClass.contains(Reg)) { + MBB.addLiveIn(Reg); + TII.storeRegToStackSlot(MBB, MI, Reg, true, CSI[i].getFrameIdx(), + &SystemZ::FP64RegClass, TRI); + } + } + + return true; +} + +bool +SystemZFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MI, + const std::vector<CalleeSavedInfo> &CSI, + const TargetRegisterInfo *TRI) const { + if (CSI.empty()) + return false; + + DebugLoc DL; + if (MI != MBB.end()) DL = MI->getDebugLoc(); + + MachineFunction &MF = *MBB.getParent(); + const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); + SystemZMachineFunctionInfo *MFI = MF.getInfo<SystemZMachineFunctionInfo>(); + + // Restore FP registers + for (unsigned i = 0, e = CSI.size(); i != e; ++i) { + unsigned Reg = CSI[i].getReg(); + if (SystemZ::FP64RegClass.contains(Reg)) + TII.loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(), + &SystemZ::FP64RegClass, TRI); + } + + // Restore GP registers + unsigned LowReg = MFI->getLowReg(), HighReg = MFI->getHighReg(); + unsigned StartOffset = RegSpillOffsets[LowReg]; + + if (StartOffset) { + // Build a load instruction. Use LOAD MULTIPLE instruction if there are many + // registers to load, otherwise - just LOAD. + MachineInstrBuilder MIB = + BuildMI(MBB, MI, DL, TII.get((LowReg == HighReg ? + SystemZ::MOV64rm : SystemZ::MOV64rmm))); + // Add store operands. + MIB.addReg(LowReg, RegState::Define); + if (LowReg != HighReg) + MIB.addReg(HighReg, RegState::Define); + + MIB.addReg(hasFP(MF) ? SystemZ::R11D : SystemZ::R15D); + MIB.addImm(StartOffset); + if (LowReg == HighReg) + MIB.addReg(0); + + // Do a second scan adding regs as being defined by instruction + for (unsigned i = 0, e = CSI.size(); i != e; ++i) { + unsigned Reg = CSI[i].getReg(); + if (Reg != LowReg && Reg != HighReg) + MIB.addReg(Reg, RegState::ImplicitDefine); + } + } + + return true; +} + +void +SystemZFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, + RegScavenger *RS) const { + // Determine whether R15/R14 will ever be clobbered inside the function. And + // if yes - mark it as 'callee' saved. + MachineFrameInfo *FFI = MF.getFrameInfo(); + MachineRegisterInfo &MRI = MF.getRegInfo(); + + // Check whether high FPRs are ever used, if yes - we need to save R15 as + // well. + static const unsigned HighFPRs[] = { + SystemZ::F8L, SystemZ::F9L, SystemZ::F10L, SystemZ::F11L, + SystemZ::F12L, SystemZ::F13L, SystemZ::F14L, SystemZ::F15L, + SystemZ::F8S, SystemZ::F9S, SystemZ::F10S, SystemZ::F11S, + SystemZ::F12S, SystemZ::F13S, SystemZ::F14S, SystemZ::F15S, + }; + + bool HighFPRsUsed = false; + for (unsigned i = 0, e = array_lengthof(HighFPRs); i != e; ++i) + HighFPRsUsed |= MRI.isPhysRegUsed(HighFPRs[i]); + + if (FFI->hasCalls()) + /* FIXME: function is varargs */ + /* FIXME: function grabs RA */ + /* FIXME: function calls eh_return */ + MRI.setPhysRegUsed(SystemZ::R14D); + + if (HighFPRsUsed || + FFI->hasCalls() || + FFI->getObjectIndexEnd() != 0 || // Contains automatic variables + FFI->hasVarSizedObjects() // Function calls dynamic alloca's + /* FIXME: function is varargs */) + MRI.setPhysRegUsed(SystemZ::R15D); +} diff --git a/lib/Target/SystemZ/SystemZFrameLowering.h b/lib/Target/SystemZ/SystemZFrameLowering.h new file mode 100644 index 0000000..1284b68 --- /dev/null +++ b/lib/Target/SystemZ/SystemZFrameLowering.h @@ -0,0 +1,57 @@ +//=- SystemZFrameLowering.h - Define frame lowering for z/System -*- C++ -*--=// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// +// +//===----------------------------------------------------------------------===// + +#ifndef SYSTEMZ_FRAMEINFO_H +#define SYSTEMZ_FRAMEINFO_H + +#include "SystemZ.h" +#include "SystemZSubtarget.h" +#include "llvm/Target/TargetFrameLowering.h" +#include "llvm/ADT/IndexedMap.h" + +namespace llvm { + class SystemZSubtarget; + +class SystemZFrameLowering : public TargetFrameLowering { + IndexedMap<unsigned> RegSpillOffsets; +protected: + const SystemZSubtarget &STI; + +public: + explicit SystemZFrameLowering(const SystemZSubtarget &sti); + + /// emitProlog/emitEpilog - These methods insert prolog and epilog code into + /// the function. + void emitPrologue(MachineFunction &MF) const; + void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const; + + bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MI, + const std::vector<CalleeSavedInfo> &CSI, + const TargetRegisterInfo *TRI) const; + bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MI, + const std::vector<CalleeSavedInfo> &CSI, + const TargetRegisterInfo *TRI) const; + + void processFunctionBeforeCalleeSavedScan(MachineFunction &MF, + RegScavenger *RS) const; + + bool hasReservedCallFrame(const MachineFunction &MF) const { return true; } + bool hasFP(const MachineFunction &MF) const; + int getFrameIndexOffset(const MachineFunction &MF, int FI) const; +}; + +} // End llvm namespace + +#endif diff --git a/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp b/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp index ed290ca..2186ff1 100644 --- a/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp +++ b/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp @@ -120,18 +120,17 @@ namespace { #include "SystemZGenDAGISel.inc" private: - bool SelectAddrRI12Only(SDNode *Op, SDValue& Addr, + bool SelectAddrRI12Only(SDValue& Addr, SDValue &Base, SDValue &Disp); - bool SelectAddrRI12(SDNode *Op, SDValue& Addr, + bool SelectAddrRI12(SDValue& Addr, SDValue &Base, SDValue &Disp, bool is12BitOnly = false); - bool SelectAddrRI(SDNode *Op, SDValue& Addr, - SDValue &Base, SDValue &Disp); - bool SelectAddrRRI12(SDNode *Op, SDValue Addr, + bool SelectAddrRI(SDValue& Addr, SDValue &Base, SDValue &Disp); + bool SelectAddrRRI12(SDValue Addr, SDValue &Base, SDValue &Disp, SDValue &Index); - bool SelectAddrRRI20(SDNode *Op, SDValue Addr, + bool SelectAddrRRI20(SDValue Addr, SDValue &Base, SDValue &Disp, SDValue &Index); - bool SelectLAAddr(SDNode *Op, SDValue Addr, + bool SelectLAAddr(SDValue Addr, SDValue &Base, SDValue &Disp, SDValue &Index); SDNode *Select(SDNode *Node); @@ -142,8 +141,6 @@ namespace { bool MatchAddress(SDValue N, SystemZRRIAddressMode &AM, bool is12Bit, unsigned Depth = 0); bool MatchAddressBase(SDValue N, SystemZRRIAddressMode &AM); - bool MatchAddressRI(SDValue N, SystemZRRIAddressMode &AM, - bool is12Bit); }; } // end anonymous namespace @@ -355,12 +352,12 @@ void SystemZDAGToDAGISel::getAddressOperands(const SystemZRRIAddressMode &AM, /// Returns true if the address can be represented by a base register plus /// an unsigned 12-bit displacement [r+imm]. -bool SystemZDAGToDAGISel::SelectAddrRI12Only(SDNode *Op, SDValue& Addr, +bool SystemZDAGToDAGISel::SelectAddrRI12Only(SDValue &Addr, SDValue &Base, SDValue &Disp) { - return SelectAddrRI12(Op, Addr, Base, Disp, /*is12BitOnly*/true); + return SelectAddrRI12(Addr, Base, Disp, /*is12BitOnly*/true); } -bool SystemZDAGToDAGISel::SelectAddrRI12(SDNode *Op, SDValue& Addr, +bool SystemZDAGToDAGISel::SelectAddrRI12(SDValue &Addr, SDValue &Base, SDValue &Disp, bool is12BitOnly) { SystemZRRIAddressMode AM20(/*isRI*/true), AM12(/*isRI*/true); @@ -410,7 +407,7 @@ bool SystemZDAGToDAGISel::SelectAddrRI12(SDNode *Op, SDValue& Addr, /// Returns true if the address can be represented by a base register plus /// a signed 20-bit displacement [r+imm]. -bool SystemZDAGToDAGISel::SelectAddrRI(SDNode *Op, SDValue& Addr, +bool SystemZDAGToDAGISel::SelectAddrRI(SDValue& Addr, SDValue &Base, SDValue &Disp) { SystemZRRIAddressMode AM(/*isRI*/true); bool Done = false; @@ -453,7 +450,7 @@ bool SystemZDAGToDAGISel::SelectAddrRI(SDNode *Op, SDValue& Addr, /// Returns true if the address can be represented by a base register plus /// index register plus an unsigned 12-bit displacement [base + idx + imm]. -bool SystemZDAGToDAGISel::SelectAddrRRI12(SDNode *Op, SDValue Addr, +bool SystemZDAGToDAGISel::SelectAddrRRI12(SDValue Addr, SDValue &Base, SDValue &Disp, SDValue &Index) { SystemZRRIAddressMode AM20, AM12; bool Done = false; @@ -502,7 +499,7 @@ bool SystemZDAGToDAGISel::SelectAddrRRI12(SDNode *Op, SDValue Addr, /// Returns true if the address can be represented by a base register plus /// index register plus a signed 20-bit displacement [base + idx + imm]. -bool SystemZDAGToDAGISel::SelectAddrRRI20(SDNode *Op, SDValue Addr, +bool SystemZDAGToDAGISel::SelectAddrRRI20(SDValue Addr, SDValue &Base, SDValue &Disp, SDValue &Index) { SystemZRRIAddressMode AM; bool Done = false; @@ -546,7 +543,7 @@ bool SystemZDAGToDAGISel::SelectAddrRRI20(SDNode *Op, SDValue Addr, /// SelectLAAddr - it calls SelectAddr and determines if the maximal addressing /// mode it matches can be cost effectively emitted as an LA/LAY instruction. -bool SystemZDAGToDAGISel::SelectLAAddr(SDNode *Op, SDValue Addr, +bool SystemZDAGToDAGISel::SelectLAAddr(SDValue Addr, SDValue &Base, SDValue &Disp, SDValue &Index) { SystemZRRIAddressMode AM; @@ -583,7 +580,7 @@ bool SystemZDAGToDAGISel::TryFoldLoad(SDNode *P, SDValue N, SDValue &Base, SDValue &Disp, SDValue &Index) { if (ISD::isNON_EXTLoad(N.getNode()) && IsLegalToFold(N, P, P, OptLevel)) - return SelectAddrRRI20(P, N.getOperand(1), Base, Disp, Index); + return SelectAddrRRI20(N.getOperand(1), Base, Disp, Index); return false; } diff --git a/lib/Target/SystemZ/SystemZISelLowering.cpp b/lib/Target/SystemZ/SystemZISelLowering.cpp index 67f739f..d694f2e 100644 --- a/lib/Target/SystemZ/SystemZISelLowering.cpp +++ b/lib/Target/SystemZ/SystemZISelLowering.cpp @@ -147,8 +147,8 @@ SystemZTargetLowering::SystemZTargetLowering(SystemZTargetMachine &tm) : setOperationAction(ISD::FREM, MVT::f64, Expand); // We have only 64-bit bitconverts - setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand); - setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand); + setOperationAction(ISD::BITCAST, MVT::f32, Expand); + setOperationAction(ISD::BITCAST, MVT::i32, Expand); setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); @@ -341,7 +341,7 @@ SystemZTargetLowering::LowerCCCArguments(SDValue Chain, // from this parameter SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); ArgValue = DAG.getLoad(LocVT, dl, Chain, FIN, - PseudoSourceValue::getFixedStack(FI), 0, + MachinePointerInfo::getFixedStack(FI), false, false, 0); } @@ -377,8 +377,8 @@ SystemZTargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const { - MachineFunction &MF = DAG.getMachineFunction(); + const TargetFrameLowering *TFI = TM.getFrameLowering(); // Offset to first argument stack slot. const unsigned FirstArgOffset = 160; @@ -431,7 +431,7 @@ SystemZTargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee, if (StackPtr.getNode() == 0) StackPtr = DAG.getCopyFromReg(Chain, dl, - (RegInfo->hasFP(MF) ? + (TFI->hasFP(MF) ? SystemZ::R11D : SystemZ::R15D), getPointerTy()); @@ -441,7 +441,7 @@ SystemZTargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee, DAG.getIntPtrConstant(Offset)); MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, - PseudoSourceValue::getStack(), Offset, + MachinePointerInfo(), false, false, 0)); } } @@ -471,7 +471,7 @@ SystemZTargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee, Callee = DAG.getTargetExternalSymbol(E->getSymbol(), getPointerTy()); // Returns a chain & a flag for retval copy to use. - SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); + SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); SmallVector<SDValue, 8> Ops; Ops.push_back(Chain); Ops.push_back(Callee); @@ -710,7 +710,7 @@ SDValue SystemZTargetLowering::LowerSELECT_CC(SDValue Op, SDValue SystemZCC; SDValue Flag = EmitCmp(LHS, RHS, CC, SystemZCC, DAG); - SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag); + SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue); SmallVector<SDValue, 4> Ops; Ops.push_back(TrueV); Ops.push_back(FalseV); @@ -747,7 +747,7 @@ SDValue SystemZTargetLowering::LowerGlobalAddress(SDValue Op, if (ExtraLoadRequired) Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result, - PseudoSourceValue::getGOT(), 0, false, false, 0); + MachinePointerInfo::getGOT(), false, false, 0); // If there was a non-zero offset that we didn't fold, create an explicit // addition for it. diff --git a/lib/Target/SystemZ/SystemZInstrBuilder.h b/lib/Target/SystemZ/SystemZInstrBuilder.h index fa87061..2f2ef08 100644 --- a/lib/Target/SystemZ/SystemZInstrBuilder.h +++ b/lib/Target/SystemZ/SystemZInstrBuilder.h @@ -115,9 +115,9 @@ addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset = 0) { if (TID.mayStore()) Flags |= MachineMemOperand::MOStore; MachineMemOperand *MMO = - MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI), - Flags, Offset, - MFI.getObjectSize(FI), + MF.getMachineMemOperand(MachinePointerInfo( + PseudoSourceValue::getFixedStack(FI), Offset), + Flags, MFI.getObjectSize(FI), MFI.getObjectAlignment(FI)); return addOffset(MIB.addFrameIndex(FI), Offset) .addMemOperand(MMO); diff --git a/lib/Target/SystemZ/SystemZInstrInfo.cpp b/lib/Target/SystemZ/SystemZInstrInfo.cpp index 367bed3..be52803 100644 --- a/lib/Target/SystemZ/SystemZInstrInfo.cpp +++ b/lib/Target/SystemZ/SystemZInstrInfo.cpp @@ -28,28 +28,6 @@ using namespace llvm; SystemZInstrInfo::SystemZInstrInfo(SystemZTargetMachine &tm) : TargetInstrInfoImpl(SystemZInsts, array_lengthof(SystemZInsts)), RI(tm, *this), TM(tm) { - // Fill the spill offsets map - static const unsigned SpillOffsTab[][2] = { - { SystemZ::R2D, 0x10 }, - { SystemZ::R3D, 0x18 }, - { SystemZ::R4D, 0x20 }, - { SystemZ::R5D, 0x28 }, - { SystemZ::R6D, 0x30 }, - { SystemZ::R7D, 0x38 }, - { SystemZ::R8D, 0x40 }, - { SystemZ::R9D, 0x48 }, - { SystemZ::R10D, 0x50 }, - { SystemZ::R11D, 0x58 }, - { SystemZ::R12D, 0x60 }, - { SystemZ::R13D, 0x68 }, - { SystemZ::R14D, 0x70 }, - { SystemZ::R15D, 0x78 } - }; - - RegSpillOffsets.grow(SystemZ::NUM_TARGET_REGS); - - for (unsigned i = 0, e = array_lengthof(SpillOffsTab); i != e; ++i) - RegSpillOffsets[SpillOffsTab[i][0]] = SpillOffsTab[i][1]; } /// isGVStub - Return true if the GV requires an extra load to get the @@ -211,134 +189,6 @@ unsigned SystemZInstrInfo::isStoreToStackSlot(const MachineInstr *MI, return 0; } -bool -SystemZInstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - const std::vector<CalleeSavedInfo> &CSI, - const TargetRegisterInfo *TRI) const { - if (CSI.empty()) - return false; - - DebugLoc DL; - if (MI != MBB.end()) DL = MI->getDebugLoc(); - - MachineFunction &MF = *MBB.getParent(); - SystemZMachineFunctionInfo *MFI = MF.getInfo<SystemZMachineFunctionInfo>(); - unsigned CalleeFrameSize = 0; - - // Scan the callee-saved and find the bounds of register spill area. - unsigned LowReg = 0, HighReg = 0, StartOffset = -1U, EndOffset = 0; - for (unsigned i = 0, e = CSI.size(); i != e; ++i) { - unsigned Reg = CSI[i].getReg(); - if (!SystemZ::FP64RegClass.contains(Reg)) { - unsigned Offset = RegSpillOffsets[Reg]; - CalleeFrameSize += 8; - if (StartOffset > Offset) { - LowReg = Reg; StartOffset = Offset; - } - if (EndOffset < Offset) { - HighReg = Reg; EndOffset = RegSpillOffsets[Reg]; - } - } - } - - // Save information for epilogue inserter. - MFI->setCalleeSavedFrameSize(CalleeFrameSize); - MFI->setLowReg(LowReg); MFI->setHighReg(HighReg); - - // Save GPRs - if (StartOffset) { - // Build a store instruction. Use STORE MULTIPLE instruction if there are many - // registers to store, otherwise - just STORE. - MachineInstrBuilder MIB = - BuildMI(MBB, MI, DL, get((LowReg == HighReg ? - SystemZ::MOV64mr : SystemZ::MOV64mrm))); - - // Add store operands. - MIB.addReg(SystemZ::R15D).addImm(StartOffset); - if (LowReg == HighReg) - MIB.addReg(0); - MIB.addReg(LowReg, RegState::Kill); - if (LowReg != HighReg) - MIB.addReg(HighReg, RegState::Kill); - - // Do a second scan adding regs as being killed by instruction - for (unsigned i = 0, e = CSI.size(); i != e; ++i) { - unsigned Reg = CSI[i].getReg(); - // Add the callee-saved register as live-in. It's killed at the spill. - MBB.addLiveIn(Reg); - if (Reg != LowReg && Reg != HighReg) - MIB.addReg(Reg, RegState::ImplicitKill); - } - } - - // Save FPRs - for (unsigned i = 0, e = CSI.size(); i != e; ++i) { - unsigned Reg = CSI[i].getReg(); - if (SystemZ::FP64RegClass.contains(Reg)) { - MBB.addLiveIn(Reg); - storeRegToStackSlot(MBB, MI, Reg, true, CSI[i].getFrameIdx(), - &SystemZ::FP64RegClass, &RI); - } - } - - return true; -} - -bool -SystemZInstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - const std::vector<CalleeSavedInfo> &CSI, - const TargetRegisterInfo *TRI) const { - if (CSI.empty()) - return false; - - DebugLoc DL; - if (MI != MBB.end()) DL = MI->getDebugLoc(); - - MachineFunction &MF = *MBB.getParent(); - const TargetRegisterInfo *RegInfo= MF.getTarget().getRegisterInfo(); - SystemZMachineFunctionInfo *MFI = MF.getInfo<SystemZMachineFunctionInfo>(); - - // Restore FP registers - for (unsigned i = 0, e = CSI.size(); i != e; ++i) { - unsigned Reg = CSI[i].getReg(); - if (SystemZ::FP64RegClass.contains(Reg)) - loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(), - &SystemZ::FP64RegClass, &RI); - } - - // Restore GP registers - unsigned LowReg = MFI->getLowReg(), HighReg = MFI->getHighReg(); - unsigned StartOffset = RegSpillOffsets[LowReg]; - - if (StartOffset) { - // Build a load instruction. Use LOAD MULTIPLE instruction if there are many - // registers to load, otherwise - just LOAD. - MachineInstrBuilder MIB = - BuildMI(MBB, MI, DL, get((LowReg == HighReg ? - SystemZ::MOV64rm : SystemZ::MOV64rmm))); - // Add store operands. - MIB.addReg(LowReg, RegState::Define); - if (LowReg != HighReg) - MIB.addReg(HighReg, RegState::Define); - - MIB.addReg((RegInfo->hasFP(MF) ? SystemZ::R11D : SystemZ::R15D)); - MIB.addImm(StartOffset); - if (LowReg == HighReg) - MIB.addReg(0); - - // Do a second scan adding regs as being defined by instruction - for (unsigned i = 0, e = CSI.size(); i != e; ++i) { - unsigned Reg = CSI[i].getReg(); - if (Reg != LowReg && Reg != HighReg) - MIB.addReg(Reg, RegState::ImplicitDefine); - } - } - - return true; -} - bool SystemZInstrInfo:: ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { assert(Cond.size() == 1 && "Invalid Xbranch condition!"); diff --git a/lib/Target/SystemZ/SystemZInstrInfo.h b/lib/Target/SystemZ/SystemZInstrInfo.h index c248f24..6cb7200 100644 --- a/lib/Target/SystemZ/SystemZInstrInfo.h +++ b/lib/Target/SystemZ/SystemZInstrInfo.h @@ -50,7 +50,6 @@ namespace SystemZII { class SystemZInstrInfo : public TargetInstrInfoImpl { const SystemZRegisterInfo RI; SystemZTargetMachine &TM; - IndexedMap<unsigned> RegSpillOffsets; public: explicit SystemZInstrInfo(SystemZTargetMachine &TM); @@ -80,15 +79,6 @@ public: const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const; - virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - const std::vector<CalleeSavedInfo> &CSI, - const TargetRegisterInfo *TRI) const; - virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - const std::vector<CalleeSavedInfo> &CSI, - const TargetRegisterInfo *TRI) const; - bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const; virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const; virtual bool AnalyzeBranch(MachineBasicBlock &MBB, diff --git a/lib/Target/SystemZ/SystemZInstrInfo.td b/lib/Target/SystemZ/SystemZInstrInfo.td index 8df07c0..11a39fc 100644 --- a/lib/Target/SystemZ/SystemZInstrInfo.td +++ b/lib/Target/SystemZ/SystemZInstrInfo.td @@ -46,15 +46,15 @@ def SDT_Address : SDTypeProfile<1, 1, // SystemZ Specific Node Definitions. //===----------------------------------------------------------------------===// def SystemZretflag : SDNode<"SystemZISD::RET_FLAG", SDTNone, - [SDNPHasChain, SDNPOptInFlag]>; + [SDNPHasChain, SDNPOptInGlue]>; def SystemZcall : SDNode<"SystemZISD::CALL", SDT_SystemZCall, - [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag, SDNPVariadic]>; + [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, SDNPVariadic]>; def SystemZcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SystemZCallSeqStart, - [SDNPHasChain, SDNPOutFlag]>; + [SDNPHasChain, SDNPOutGlue]>; def SystemZcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SystemZCallSeqEnd, - [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; + [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; def SystemZcmp : SDNode<"SystemZISD::CMP", SDT_CmpTest>; def SystemZucmp : SDNode<"SystemZISD::UCMP", SDT_CmpTest>; def SystemZbrcond : SDNode<"SystemZISD::BRCOND", SDT_BrCond, @@ -229,19 +229,19 @@ def MOV64ri16 : RII<0x9A7, [(set GR64:$dst, immSExt16:$src)]>; def MOV64rill16 : RII<0xFA5, - (outs GR64:$dst), (ins i64imm:$src), + (outs GR64:$dst), (ins u16imm:$src), "llill\t{$dst, $src}", [(set GR64:$dst, i64ll16:$src)]>; def MOV64rilh16 : RII<0xEA5, - (outs GR64:$dst), (ins i64imm:$src), + (outs GR64:$dst), (ins u16imm:$src), "llilh\t{$dst, $src}", [(set GR64:$dst, i64lh16:$src)]>; def MOV64rihl16 : RII<0xDA5, - (outs GR64:$dst), (ins i64imm:$src), + (outs GR64:$dst), (ins u16imm:$src), "llihl\t{$dst, $src}", [(set GR64:$dst, i64hl16:$src)]>; def MOV64rihh16 : RII<0xCA5, - (outs GR64:$dst), (ins i64imm:$src), + (outs GR64:$dst), (ins u16imm:$src), "llihh\t{$dst, $src}", [(set GR64:$dst, i64hh16:$src)]>; @@ -250,10 +250,10 @@ def MOV64ri32 : RILI<0x1C0, "lgfi\t{$dst, $src}", [(set GR64:$dst, immSExt32:$src)]>; def MOV64rilo32 : RILI<0xFC0, - (outs GR64:$dst), (ins i64imm:$src), + (outs GR64:$dst), (ins u32imm:$src), "llilf\t{$dst, $src}", [(set GR64:$dst, i64lo32:$src)]>; -def MOV64rihi32 : RILI<0xEC0, (outs GR64:$dst), (ins i64imm:$src), +def MOV64rihi32 : RILI<0xEC0, (outs GR64:$dst), (ins u32imm:$src), "llihf\t{$dst, $src}", [(set GR64:$dst, i64hi32:$src)]>; } @@ -642,42 +642,42 @@ def AND64rm : RXYI<0xE360, (outs GR64:$dst), (ins GR64:$src1, rriaddr:$src2), (implicit PSW)]>; def AND32rill16 : RII<0xA57, - (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2), + (outs GR32:$dst), (ins GR32:$src1, u16imm:$src2), "nill\t{$dst, $src2}", [(set GR32:$dst, (and GR32:$src1, i32ll16c:$src2))]>; def AND64rill16 : RII<0xA57, - (outs GR64:$dst), (ins GR64:$src1, i64imm:$src2), + (outs GR64:$dst), (ins GR64:$src1, u16imm:$src2), "nill\t{$dst, $src2}", [(set GR64:$dst, (and GR64:$src1, i64ll16c:$src2))]>; def AND32rilh16 : RII<0xA56, - (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2), + (outs GR32:$dst), (ins GR32:$src1, u16imm:$src2), "nilh\t{$dst, $src2}", [(set GR32:$dst, (and GR32:$src1, i32lh16c:$src2))]>; def AND64rilh16 : RII<0xA56, - (outs GR64:$dst), (ins GR64:$src1, i64imm:$src2), + (outs GR64:$dst), (ins GR64:$src1, u16imm:$src2), "nilh\t{$dst, $src2}", [(set GR64:$dst, (and GR64:$src1, i64lh16c:$src2))]>; def AND64rihl16 : RII<0xA55, - (outs GR64:$dst), (ins GR64:$src1, i64imm:$src2), + (outs GR64:$dst), (ins GR64:$src1, u16imm:$src2), "nihl\t{$dst, $src2}", [(set GR64:$dst, (and GR64:$src1, i64hl16c:$src2))]>; def AND64rihh16 : RII<0xA54, - (outs GR64:$dst), (ins GR64:$src1, i64imm:$src2), + (outs GR64:$dst), (ins GR64:$src1, u16imm:$src2), "nihh\t{$dst, $src2}", [(set GR64:$dst, (and GR64:$src1, i64hh16c:$src2))]>; def AND32ri : RILI<0xC0B, - (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2), + (outs GR32:$dst), (ins GR32:$src1, u32imm:$src2), "nilf\t{$dst, $src2}", [(set GR32:$dst, (and GR32:$src1, imm:$src2))]>; def AND64rilo32 : RILI<0xC0B, - (outs GR64:$dst), (ins GR64:$src1, i64imm:$src2), + (outs GR64:$dst), (ins GR64:$src1, u32imm:$src2), "nilf\t{$dst, $src2}", [(set GR64:$dst, (and GR64:$src1, i64lo32c:$src2))]>; def AND64rihi32 : RILI<0xC0A, - (outs GR64:$dst), (ins GR64:$src1, i64imm:$src2), + (outs GR64:$dst), (ins GR64:$src1, u32imm:$src2), "nihf\t{$dst, $src2}", [(set GR64:$dst, (and GR64:$src1, i64hi32c:$src2))]>; @@ -707,41 +707,41 @@ def OR64rm : RXYI<0xE381, (outs GR64:$dst), (ins GR64:$src1, rriaddr:$src2), // FIXME: Provide proper encoding! def OR32ri16 : RII<0xA5B, - (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2), + (outs GR32:$dst), (ins GR32:$src1, u32imm:$src2), "oill\t{$dst, $src2}", [(set GR32:$dst, (or GR32:$src1, i32ll16:$src2))]>; def OR32ri16h : RII<0xA5A, - (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2), + (outs GR32:$dst), (ins GR32:$src1, u32imm:$src2), "oilh\t{$dst, $src2}", [(set GR32:$dst, (or GR32:$src1, i32lh16:$src2))]>; def OR32ri : RILI<0xC0D, - (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2), + (outs GR32:$dst), (ins GR32:$src1, u32imm:$src2), "oilf\t{$dst, $src2}", [(set GR32:$dst, (or GR32:$src1, imm:$src2))]>; def OR64rill16 : RII<0xA5B, - (outs GR64:$dst), (ins GR64:$src1, i64imm:$src2), + (outs GR64:$dst), (ins GR64:$src1, u16imm:$src2), "oill\t{$dst, $src2}", [(set GR64:$dst, (or GR64:$src1, i64ll16:$src2))]>; def OR64rilh16 : RII<0xA5A, - (outs GR64:$dst), (ins GR64:$src1, i64imm:$src2), + (outs GR64:$dst), (ins GR64:$src1, u16imm:$src2), "oilh\t{$dst, $src2}", [(set GR64:$dst, (or GR64:$src1, i64lh16:$src2))]>; def OR64rihl16 : RII<0xA59, - (outs GR64:$dst), (ins GR64:$src1, i64imm:$src2), + (outs GR64:$dst), (ins GR64:$src1, u16imm:$src2), "oihl\t{$dst, $src2}", [(set GR64:$dst, (or GR64:$src1, i64hl16:$src2))]>; def OR64rihh16 : RII<0xA58, - (outs GR64:$dst), (ins GR64:$src1, i64imm:$src2), + (outs GR64:$dst), (ins GR64:$src1, u16imm:$src2), "oihh\t{$dst, $src2}", [(set GR64:$dst, (or GR64:$src1, i64hh16:$src2))]>; def OR64rilo32 : RILI<0xC0D, - (outs GR64:$dst), (ins GR64:$src1, i64imm:$src2), + (outs GR64:$dst), (ins GR64:$src1, u32imm:$src2), "oilf\t{$dst, $src2}", [(set GR64:$dst, (or GR64:$src1, i64lo32:$src2))]>; def OR64rihi32 : RILI<0xC0C, - (outs GR64:$dst), (ins GR64:$src1, i64imm:$src2), + (outs GR64:$dst), (ins GR64:$src1, u32imm:$src2), "oihf\t{$dst, $src2}", [(set GR64:$dst, (or GR64:$src1, i64hi32:$src2))]>; diff --git a/lib/Target/SystemZ/SystemZMCAsmInfo.cpp b/lib/Target/SystemZ/SystemZMCAsmInfo.cpp index 4f7f70b..2dc7e7b 100644 --- a/lib/Target/SystemZ/SystemZMCAsmInfo.cpp +++ b/lib/Target/SystemZ/SystemZMCAsmInfo.cpp @@ -14,6 +14,7 @@ #include "SystemZMCAsmInfo.h" #include "llvm/MC/MCContext.h" #include "llvm/MC/MCSectionELF.h" +#include "llvm/Support/ELF.h" using namespace llvm; SystemZMCAsmInfo::SystemZMCAsmInfo(const Target &T, StringRef TT) { @@ -24,6 +25,6 @@ SystemZMCAsmInfo::SystemZMCAsmInfo(const Target &T, StringRef TT) { const MCSection *SystemZMCAsmInfo:: getNonexecutableStackSection(MCContext &Ctx) const{ - return Ctx.getELFSection(".note.GNU-stack", MCSectionELF::SHT_PROGBITS, - 0, SectionKind::getMetadata(), false); + return Ctx.getELFSection(".note.GNU-stack", ELF::SHT_PROGBITS, + 0, SectionKind::getMetadata()); } diff --git a/lib/Target/SystemZ/SystemZOperands.td b/lib/Target/SystemZ/SystemZOperands.td index 0de50fd..8b835cc 100644 --- a/lib/Target/SystemZ/SystemZOperands.td +++ b/lib/Target/SystemZ/SystemZOperands.td @@ -246,6 +246,14 @@ def s16imm : Operand<i32> { def s16imm64 : Operand<i64> { let PrintMethod = "printS16ImmOperand"; } +// Unsigned i16 +def u16imm : Operand<i32> { + let PrintMethod = "printU16ImmOperand"; +} +def u16imm64 : Operand<i64> { + let PrintMethod = "printU16ImmOperand"; +} + // Signed i20 def s20imm : Operand<i32> { let PrintMethod = "printS20ImmOperand"; @@ -260,6 +268,13 @@ def s32imm : Operand<i32> { def s32imm64 : Operand<i64> { let PrintMethod = "printS32ImmOperand"; } +// Unsigned i32 +def u32imm : Operand<i32> { + let PrintMethod = "printU32ImmOperand"; +} +def u32imm64 : Operand<i64> { + let PrintMethod = "printU32ImmOperand"; +} def imm_pcrel : Operand<i64> { let PrintMethod = "printPCRelImmOperand"; diff --git a/lib/Target/SystemZ/SystemZRegisterInfo.cpp b/lib/Target/SystemZ/SystemZRegisterInfo.cpp index f8d3e6a..28f94f4 100644 --- a/lib/Target/SystemZ/SystemZRegisterInfo.cpp +++ b/lib/Target/SystemZ/SystemZRegisterInfo.cpp @@ -20,7 +20,7 @@ #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineRegisterInfo.h" -#include "llvm/Target/TargetFrameInfo.h" +#include "llvm/Target/TargetFrameLowering.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetOptions.h" @@ -49,49 +49,21 @@ SystemZRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { BitVector SystemZRegisterInfo::getReservedRegs(const MachineFunction &MF) const { BitVector Reserved(getNumRegs()); - if (hasFP(MF)) + const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); + + if (TFI->hasFP(MF)) Reserved.set(SystemZ::R11D); Reserved.set(SystemZ::R14D); Reserved.set(SystemZ::R15D); return Reserved; } -/// needsFP - Return true if the specified function should have a dedicated -/// frame pointer register. This is true if the function has variable sized -/// allocas or if frame pointer elimination is disabled. -bool SystemZRegisterInfo::hasFP(const MachineFunction &MF) const { - const MachineFrameInfo *MFI = MF.getFrameInfo(); - return DisableFramePointerElim(MF) || MFI->hasVarSizedObjects(); -} - void SystemZRegisterInfo:: eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const { MBB.erase(I); } -int SystemZRegisterInfo::getFrameIndexOffset(const MachineFunction &MF, - int FI) const { - const TargetFrameInfo &TFI = *MF.getTarget().getFrameInfo(); - const MachineFrameInfo *MFI = MF.getFrameInfo(); - const SystemZMachineFunctionInfo *SystemZMFI = - MF.getInfo<SystemZMachineFunctionInfo>(); - int Offset = MFI->getObjectOffset(FI) + MFI->getOffsetAdjustment(); - uint64_t StackSize = MFI->getStackSize(); - - // Fixed objects are really located in the "previous" frame. - if (FI < 0) - StackSize -= SystemZMFI->getCalleeSavedFrameSize(); - - Offset += StackSize - TFI.getOffsetOfLocalArea(); - - // Skip the register save area if we generated the stack frame. - if (StackSize || MFI->hasCalls()) - Offset -= TFI.getOffsetOfLocalArea(); - - return Offset; -} - void SystemZRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, RegScavenger *RS) const { @@ -100,6 +72,8 @@ SystemZRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, unsigned i = 0; MachineInstr &MI = *II; MachineFunction &MF = *MI.getParent()->getParent(); + const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); + while (!MI.getOperand(i).isFI()) { ++i; assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); @@ -107,7 +81,7 @@ SystemZRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, int FrameIndex = MI.getOperand(i).getIndex(); - unsigned BasePtr = (hasFP(MF) ? SystemZ::R11D : SystemZ::R15D); + unsigned BasePtr = (TFI->hasFP(MF) ? SystemZ::R11D : SystemZ::R15D); // This must be part of a rri or ri operand memory reference. Replace the // FrameIndex with base register with BasePtr. Add an offset to the @@ -117,7 +91,7 @@ SystemZRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, // Offset is a either 12-bit unsigned or 20-bit signed integer. // FIXME: handle "too long" displacements. int Offset = - getFrameIndexOffset(MF, FrameIndex) + MI.getOperand(i+1).getImm(); + TFI->getFrameIndexOffset(MF, FrameIndex) + MI.getOperand(i+1).getImm(); // Check whether displacement is too long to fit into 12 bit zext field. MI.setDesc(TII.getMemoryInstr(MI.getOpcode(), Offset)); @@ -125,178 +99,6 @@ SystemZRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, MI.getOperand(i+1).ChangeToImmediate(Offset); } -void -SystemZRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, - RegScavenger *RS) const { - // Determine whether R15/R14 will ever be clobbered inside the function. And - // if yes - mark it as 'callee' saved. - MachineFrameInfo *FFI = MF.getFrameInfo(); - MachineRegisterInfo &MRI = MF.getRegInfo(); - - // Check whether high FPRs are ever used, if yes - we need to save R15 as - // well. - static const unsigned HighFPRs[] = { - SystemZ::F8L, SystemZ::F9L, SystemZ::F10L, SystemZ::F11L, - SystemZ::F12L, SystemZ::F13L, SystemZ::F14L, SystemZ::F15L, - SystemZ::F8S, SystemZ::F9S, SystemZ::F10S, SystemZ::F11S, - SystemZ::F12S, SystemZ::F13S, SystemZ::F14S, SystemZ::F15S, - }; - - bool HighFPRsUsed = false; - for (unsigned i = 0, e = array_lengthof(HighFPRs); i != e; ++i) - HighFPRsUsed |= MRI.isPhysRegUsed(HighFPRs[i]); - - if (FFI->hasCalls()) - /* FIXME: function is varargs */ - /* FIXME: function grabs RA */ - /* FIXME: function calls eh_return */ - MRI.setPhysRegUsed(SystemZ::R14D); - - if (HighFPRsUsed || - FFI->hasCalls() || - FFI->getObjectIndexEnd() != 0 || // Contains automatic variables - FFI->hasVarSizedObjects() // Function calls dynamic alloca's - /* FIXME: function is varargs */) - MRI.setPhysRegUsed(SystemZ::R15D); -} - -/// emitSPUpdate - Emit a series of instructions to increment / decrement the -/// stack pointer by a constant value. -static -void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, - int64_t NumBytes, const TargetInstrInfo &TII) { - unsigned Opc; uint64_t Chunk; - bool isSub = NumBytes < 0; - uint64_t Offset = isSub ? -NumBytes : NumBytes; - - if (Offset >= (1LL << 15) - 1) { - Opc = SystemZ::ADD64ri32; - Chunk = (1LL << 31) - 1; - } else { - Opc = SystemZ::ADD64ri16; - Chunk = (1LL << 15) - 1; - } - - DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); - - while (Offset) { - uint64_t ThisVal = (Offset > Chunk) ? Chunk : Offset; - MachineInstr *MI = - BuildMI(MBB, MBBI, DL, TII.get(Opc), SystemZ::R15D) - .addReg(SystemZ::R15D).addImm(isSub ? -ThisVal : ThisVal); - // The PSW implicit def is dead. - MI->getOperand(3).setIsDead(); - Offset -= ThisVal; - } -} - -void SystemZRegisterInfo::emitPrologue(MachineFunction &MF) const { - MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB - const TargetFrameInfo &TFI = *MF.getTarget().getFrameInfo(); - MachineFrameInfo *MFI = MF.getFrameInfo(); - SystemZMachineFunctionInfo *SystemZMFI = - MF.getInfo<SystemZMachineFunctionInfo>(); - MachineBasicBlock::iterator MBBI = MBB.begin(); - DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); - - // Get the number of bytes to allocate from the FrameInfo. - // Note that area for callee-saved stuff is already allocated, thus we need to - // 'undo' the stack movement. - uint64_t StackSize = MFI->getStackSize(); - StackSize -= SystemZMFI->getCalleeSavedFrameSize(); - - uint64_t NumBytes = StackSize - TFI.getOffsetOfLocalArea(); - - // Skip the callee-saved push instructions. - while (MBBI != MBB.end() && - (MBBI->getOpcode() == SystemZ::MOV64mr || - MBBI->getOpcode() == SystemZ::MOV64mrm)) - ++MBBI; - - if (MBBI != MBB.end()) - DL = MBBI->getDebugLoc(); - - // adjust stack pointer: R15 -= numbytes - if (StackSize || MFI->hasCalls()) { - assert(MF.getRegInfo().isPhysRegUsed(SystemZ::R15D) && - "Invalid stack frame calculation!"); - emitSPUpdate(MBB, MBBI, -(int64_t)NumBytes, TII); - } - - if (hasFP(MF)) { - // Update R11 with the new base value... - BuildMI(MBB, MBBI, DL, TII.get(SystemZ::MOV64rr), SystemZ::R11D) - .addReg(SystemZ::R15D); - - // Mark the FramePtr as live-in in every block except the entry. - for (MachineFunction::iterator I = llvm::next(MF.begin()), E = MF.end(); - I != E; ++I) - I->addLiveIn(SystemZ::R11D); - - } -} - -void SystemZRegisterInfo::emitEpilogue(MachineFunction &MF, - MachineBasicBlock &MBB) const { - const MachineFrameInfo *MFI = MF.getFrameInfo(); - const TargetFrameInfo &TFI = *MF.getTarget().getFrameInfo(); - MachineBasicBlock::iterator MBBI = prior(MBB.end()); - SystemZMachineFunctionInfo *SystemZMFI = - MF.getInfo<SystemZMachineFunctionInfo>(); - unsigned RetOpcode = MBBI->getOpcode(); - - switch (RetOpcode) { - case SystemZ::RET: break; // These are ok - default: - assert(0 && "Can only insert epilog into returning blocks"); - } - - // Get the number of bytes to allocate from the FrameInfo - // Note that area for callee-saved stuff is already allocated, thus we need to - // 'undo' the stack movement. - uint64_t StackSize = - MFI->getStackSize() - SystemZMFI->getCalleeSavedFrameSize(); - uint64_t NumBytes = StackSize - TFI.getOffsetOfLocalArea(); - - // Skip the final terminator instruction. - while (MBBI != MBB.begin()) { - MachineBasicBlock::iterator PI = prior(MBBI); - --MBBI; - if (!PI->getDesc().isTerminator()) - break; - } - - // During callee-saved restores emission stack frame was not yet finialized - // (and thus - the stack size was unknown). Tune the offset having full stack - // size in hands. - if (StackSize || MFI->hasCalls()) { - assert((MBBI->getOpcode() == SystemZ::MOV64rmm || - MBBI->getOpcode() == SystemZ::MOV64rm) && - "Expected to see callee-save register restore code"); - assert(MF.getRegInfo().isPhysRegUsed(SystemZ::R15D) && - "Invalid stack frame calculation!"); - - unsigned i = 0; - MachineInstr &MI = *MBBI; - while (!MI.getOperand(i).isImm()) { - ++i; - assert(i < MI.getNumOperands() && "Unexpected restore code!"); - } - - uint64_t Offset = NumBytes + MI.getOperand(i).getImm(); - // If Offset does not fit into 20-bit signed displacement field we need to - // emit some additional code... - if (Offset > 524287) { - // Fold the displacement into load instruction as much as possible. - NumBytes = Offset - 524287; - Offset = 524287; - emitSPUpdate(MBB, MBBI, NumBytes, TII); - } - - MI.getOperand(i).ChangeToImmediate(Offset); - } -} - unsigned SystemZRegisterInfo::getRARegister() const { assert(0 && "What is the return address register"); return 0; diff --git a/lib/Target/SystemZ/SystemZRegisterInfo.h b/lib/Target/SystemZ/SystemZRegisterInfo.h index 5dae865..b450798 100644 --- a/lib/Target/SystemZ/SystemZRegisterInfo.h +++ b/lib/Target/SystemZ/SystemZRegisterInfo.h @@ -34,11 +34,6 @@ struct SystemZRegisterInfo : public SystemZGenRegisterInfo { BitVector getReservedRegs(const MachineFunction &MF) const; - bool hasReservedCallFrame(const MachineFunction &MF) const { return true; } - bool hasFP(const MachineFunction &MF) const; - - int getFrameIndexOffset(const MachineFunction &MF, int FI) const; - void eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const; @@ -46,13 +41,6 @@ struct SystemZRegisterInfo : public SystemZGenRegisterInfo { void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, RegScavenger *RS = NULL) const; - - void processFunctionBeforeCalleeSavedScan(MachineFunction &MF, - RegScavenger *RS) const; - - void emitPrologue(MachineFunction &MF) const; - void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const; - // Debug information queries. unsigned getRARegister() const; unsigned getFrameRegister(const MachineFunction &MF) const; diff --git a/lib/Target/SystemZ/SystemZRegisterInfo.td b/lib/Target/SystemZ/SystemZRegisterInfo.td index 33be8dd..0028c85 100644 --- a/lib/Target/SystemZ/SystemZRegisterInfo.td +++ b/lib/Target/SystemZ/SystemZRegisterInfo.td @@ -190,8 +190,8 @@ def GR32 : RegisterClass<"SystemZ", [i32], 32, GR32Class::iterator GR32Class::allocation_order_begin(const MachineFunction &MF) const { const TargetMachine &TM = MF.getTarget(); - const TargetRegisterInfo *RI = TM.getRegisterInfo(); - if (RI->hasFP(MF)) + const TargetFrameLowering *TFI = TM.getFrameLowering(); + if (TFI->hasFP(MF)) return SystemZ_REG32_nofp; else return SystemZ_REG32; @@ -199,8 +199,8 @@ def GR32 : RegisterClass<"SystemZ", [i32], 32, GR32Class::iterator GR32Class::allocation_order_end(const MachineFunction &MF) const { const TargetMachine &TM = MF.getTarget(); - const TargetRegisterInfo *RI = TM.getRegisterInfo(); - if (RI->hasFP(MF)) + const TargetFrameLowering *TFI = TM.getFrameLowering(); + if (TFI->hasFP(MF)) return SystemZ_REG32_nofp + (sizeof(SystemZ_REG32_nofp) / sizeof(unsigned)); else return SystemZ_REG32 + (sizeof(SystemZ_REG32) / sizeof(unsigned)); @@ -237,8 +237,8 @@ def ADDR32 : RegisterClass<"SystemZ", [i32], 32, ADDR32Class::iterator ADDR32Class::allocation_order_begin(const MachineFunction &MF) const { const TargetMachine &TM = MF.getTarget(); - const TargetRegisterInfo *RI = TM.getRegisterInfo(); - if (RI->hasFP(MF)) + const TargetFrameLowering *TFI = TM.getFrameLowering(); + if (TFI->hasFP(MF)) return SystemZ_ADDR32_nofp; else return SystemZ_ADDR32; @@ -246,8 +246,8 @@ def ADDR32 : RegisterClass<"SystemZ", [i32], 32, ADDR32Class::iterator ADDR32Class::allocation_order_end(const MachineFunction &MF) const { const TargetMachine &TM = MF.getTarget(); - const TargetRegisterInfo *RI = TM.getRegisterInfo(); - if (RI->hasFP(MF)) + const TargetFrameLowering *TFI = TM.getFrameLowering(); + if (TFI->hasFP(MF)) return SystemZ_ADDR32_nofp + (sizeof(SystemZ_ADDR32_nofp) / sizeof(unsigned)); else return SystemZ_ADDR32 + (sizeof(SystemZ_ADDR32) / sizeof(unsigned)); @@ -284,8 +284,8 @@ def GR64 : RegisterClass<"SystemZ", [i64], 64, GR64Class::iterator GR64Class::allocation_order_begin(const MachineFunction &MF) const { const TargetMachine &TM = MF.getTarget(); - const TargetRegisterInfo *RI = TM.getRegisterInfo(); - if (RI->hasFP(MF)) + const TargetFrameLowering *TFI = TM.getFrameLowering(); + if (TFI->hasFP(MF)) return SystemZ_REG64_nofp; else return SystemZ_REG64; @@ -293,8 +293,8 @@ def GR64 : RegisterClass<"SystemZ", [i64], 64, GR64Class::iterator GR64Class::allocation_order_end(const MachineFunction &MF) const { const TargetMachine &TM = MF.getTarget(); - const TargetRegisterInfo *RI = TM.getRegisterInfo(); - if (RI->hasFP(MF)) + const TargetFrameLowering *TFI = TM.getFrameLowering(); + if (TFI->hasFP(MF)) return SystemZ_REG64_nofp + (sizeof(SystemZ_REG64_nofp) / sizeof(unsigned)); else return SystemZ_REG64 + (sizeof(SystemZ_REG64) / sizeof(unsigned)); @@ -331,8 +331,8 @@ def ADDR64 : RegisterClass<"SystemZ", [i64], 64, ADDR64Class::iterator ADDR64Class::allocation_order_begin(const MachineFunction &MF) const { const TargetMachine &TM = MF.getTarget(); - const TargetRegisterInfo *RI = TM.getRegisterInfo(); - if (RI->hasFP(MF)) + const TargetFrameLowering *TFI = TM.getFrameLowering(); + if (TFI->hasFP(MF)) return SystemZ_ADDR64_nofp; else return SystemZ_ADDR64; @@ -340,8 +340,8 @@ def ADDR64 : RegisterClass<"SystemZ", [i64], 64, ADDR64Class::iterator ADDR64Class::allocation_order_end(const MachineFunction &MF) const { const TargetMachine &TM = MF.getTarget(); - const TargetRegisterInfo *RI = TM.getRegisterInfo(); - if (RI->hasFP(MF)) + const TargetFrameLowering *TFI = TM.getFrameLowering(); + if (TFI->hasFP(MF)) return SystemZ_ADDR64_nofp + (sizeof(SystemZ_ADDR64_nofp) / sizeof(unsigned)); else return SystemZ_ADDR64 + (sizeof(SystemZ_ADDR64) / sizeof(unsigned)); @@ -368,8 +368,8 @@ def GR64P : RegisterClass<"SystemZ", [v2i32], 64, GR64PClass::iterator GR64PClass::allocation_order_begin(const MachineFunction &MF) const { const TargetMachine &TM = MF.getTarget(); - const TargetRegisterInfo *RI = TM.getRegisterInfo(); - if (RI->hasFP(MF)) + const TargetFrameLowering *TFI = TM.getFrameLowering(); + if (TFI->hasFP(MF)) return SystemZ_REG64P_nofp; else return SystemZ_REG64P; @@ -377,8 +377,8 @@ def GR64P : RegisterClass<"SystemZ", [v2i32], 64, GR64PClass::iterator GR64PClass::allocation_order_end(const MachineFunction &MF) const { const TargetMachine &TM = MF.getTarget(); - const TargetRegisterInfo *RI = TM.getRegisterInfo(); - if (RI->hasFP(MF)) + const TargetFrameLowering *TFI = TM.getFrameLowering(); + if (TFI->hasFP(MF)) return SystemZ_REG64P_nofp + (sizeof(SystemZ_REG64P_nofp) / sizeof(unsigned)); else return SystemZ_REG64P + (sizeof(SystemZ_REG64P) / sizeof(unsigned)); @@ -405,8 +405,8 @@ def GR128 : RegisterClass<"SystemZ", [v2i64], 128, GR128Class::iterator GR128Class::allocation_order_begin(const MachineFunction &MF) const { const TargetMachine &TM = MF.getTarget(); - const TargetRegisterInfo *RI = TM.getRegisterInfo(); - if (RI->hasFP(MF)) + const TargetFrameLowering *TFI = TM.getFrameLowering(); + if (TFI->hasFP(MF)) return SystemZ_REG128_nofp; else return SystemZ_REG128; @@ -414,8 +414,8 @@ def GR128 : RegisterClass<"SystemZ", [v2i64], 128, GR128Class::iterator GR128Class::allocation_order_end(const MachineFunction &MF) const { const TargetMachine &TM = MF.getTarget(); - const TargetRegisterInfo *RI = TM.getRegisterInfo(); - if (RI->hasFP(MF)) + const TargetFrameLowering *TFI = TM.getFrameLowering(); + if (TFI->hasFP(MF)) return SystemZ_REG128_nofp + (sizeof(SystemZ_REG128_nofp) / sizeof(unsigned)); else return SystemZ_REG128 + (sizeof(SystemZ_REG128) / sizeof(unsigned)); diff --git a/lib/Target/SystemZ/SystemZTargetMachine.cpp b/lib/Target/SystemZ/SystemZTargetMachine.cpp index f45827b..1603899 100644 --- a/lib/Target/SystemZ/SystemZTargetMachine.cpp +++ b/lib/Target/SystemZ/SystemZTargetMachine.cpp @@ -30,7 +30,7 @@ SystemZTargetMachine::SystemZTargetMachine(const Target &T, DataLayout("E-p:64:64:64-i8:8:16-i16:16:16-i32:32:32-i64:64:64-f32:32:32" "-f64:64:64-f128:128:128-a0:16:16-n32:64"), InstrInfo(*this), TLInfo(*this), TSInfo(*this), - FrameInfo(TargetFrameInfo::StackGrowsDown, 8, -160) { + FrameLowering(Subtarget) { if (getRelocationModel() == Reloc::Default) setRelocationModel(Reloc::Static); diff --git a/lib/Target/SystemZ/SystemZTargetMachine.h b/lib/Target/SystemZ/SystemZTargetMachine.h index 6af829b..524f83d 100644 --- a/lib/Target/SystemZ/SystemZTargetMachine.h +++ b/lib/Target/SystemZ/SystemZTargetMachine.h @@ -17,11 +17,12 @@ #include "SystemZInstrInfo.h" #include "SystemZISelLowering.h" +#include "SystemZFrameLowering.h" #include "SystemZSelectionDAGInfo.h" #include "SystemZRegisterInfo.h" #include "SystemZSubtarget.h" #include "llvm/Target/TargetData.h" -#include "llvm/Target/TargetFrameInfo.h" +#include "llvm/Target/TargetFrameLowering.h" #include "llvm/Target/TargetMachine.h" namespace llvm { @@ -34,15 +35,14 @@ class SystemZTargetMachine : public LLVMTargetMachine { SystemZInstrInfo InstrInfo; SystemZTargetLowering TLInfo; SystemZSelectionDAGInfo TSInfo; - - // SystemZ does not have any call stack frame, therefore not having - // any SystemZ specific FrameInfo class. - TargetFrameInfo FrameInfo; + SystemZFrameLowering FrameLowering; public: SystemZTargetMachine(const Target &T, const std::string &TT, const std::string &FS); - virtual const TargetFrameInfo *getFrameInfo() const { return &FrameInfo; } + virtual const TargetFrameLowering *getFrameLowering() const { + return &FrameLowering; + } virtual const SystemZInstrInfo *getInstrInfo() const { return &InstrInfo; } virtual const TargetData *getTargetData() const { return &DataLayout;} virtual const SystemZSubtarget *getSubtargetImpl() const { return &Subtarget; } |
