diff options
Diffstat (limited to 'lib/Target/PowerPC')
| -rw-r--r-- | lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp | 8 | ||||
| -rw-r--r-- | lib/Target/PowerPC/PPCISelLowering.cpp | 10 | ||||
| -rw-r--r-- | lib/Target/PowerPC/PPCInstrAltivec.td | 14 | ||||
| -rw-r--r-- | lib/Target/PowerPC/PPCRegisterInfo.cpp | 2 | ||||
| -rw-r--r-- | lib/Target/PowerPC/PPCRegisterInfo.h | 2 |
5 files changed, 23 insertions, 13 deletions
diff --git a/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp b/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp index ac901d0..3c7dfaf 100644 --- a/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp +++ b/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp @@ -309,8 +309,8 @@ namespace { const MCSymbol *&TOCEntry = TOC[Sym]; if (TOCEntry == 0) TOCEntry = OutContext. - GetOrCreateSymbol(StringRef(MAI->getPrivateGlobalPrefix()) + "C" + - Twine(LabelID++)); + GetOrCreateTemporarySymbol(StringRef(MAI->getPrivateGlobalPrefix()) + + "C" + Twine(LabelID++)); O << *TOCEntry << "@toc"; } @@ -672,14 +672,14 @@ static const MCSymbol *GetLazyPtr(const MCSymbol *Sym, MCContext &Ctx) { // Remove $stub suffix, add $lazy_ptr. SmallString<128> TmpStr(Sym->getName().begin(), Sym->getName().end()-5); TmpStr += "$lazy_ptr"; - return Ctx.GetOrCreateSymbol(TmpStr.str()); + return Ctx.GetOrCreateTemporarySymbol(TmpStr.str()); } static const MCSymbol *GetAnonSym(const MCSymbol *Sym, MCContext &Ctx) { // Add $tmp suffix to $stub, yielding $stub$tmp. SmallString<128> TmpStr(Sym->getName().begin(), Sym->getName().end()); TmpStr += "$tmp"; - return Ctx.GetOrCreateSymbol(TmpStr.str()); + return Ctx.GetOrCreateTemporarySymbol(TmpStr.str()); } void PPCDarwinAsmPrinter:: diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp index 3d81afa..aeaa7c6 100644 --- a/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/lib/Target/PowerPC/PPCISelLowering.cpp @@ -3258,6 +3258,16 @@ PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee, false, false, 0); } + // On Darwin, R12 must contain the address of an indirect callee. This does + // not mean the MTCTR instruction must use R12; it's easier to model this as + // an extra parameter, so do that. + if (!isTailCall && + !dyn_cast<GlobalAddressSDNode>(Callee) && + !dyn_cast<ExternalSymbolSDNode>(Callee) && + !isBLACompatibleAddress(Callee, DAG)) + RegsToPass.push_back(std::make_pair((unsigned)(isPPC64 ? PPC::X12 : + PPC::R12), Callee)); + // Build a sequence of copy-to-reg nodes chained together with token chain // and flag operands which copy the outgoing args into the appropriate regs. SDValue InFlag; diff --git a/lib/Target/PowerPC/PPCInstrAltivec.td b/lib/Target/PowerPC/PPCInstrAltivec.td index 3f4d329..3ff8f27 100644 --- a/lib/Target/PowerPC/PPCInstrAltivec.td +++ b/lib/Target/PowerPC/PPCInstrAltivec.td @@ -35,33 +35,33 @@ def vpkuwum_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), def vmrglb_shuffle : PatFrag<(ops node:$lhs, node:$rhs), - (vector_shuffle node:$lhs, node:$rhs), [{ + (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, false); }]>; def vmrglh_shuffle : PatFrag<(ops node:$lhs, node:$rhs), - (vector_shuffle node:$lhs, node:$rhs), [{ + (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, false); }]>; def vmrglw_shuffle : PatFrag<(ops node:$lhs, node:$rhs), - (vector_shuffle node:$lhs, node:$rhs), [{ + (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, false); }]>; def vmrghb_shuffle : PatFrag<(ops node:$lhs, node:$rhs), - (vector_shuffle node:$lhs, node:$rhs), [{ + (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, false); }]>; def vmrghh_shuffle : PatFrag<(ops node:$lhs, node:$rhs), - (vector_shuffle node:$lhs, node:$rhs), [{ + (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, false); }]>; def vmrghw_shuffle : PatFrag<(ops node:$lhs, node:$rhs), - (vector_shuffle node:$lhs, node:$rhs), [{ + (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, false); }]>; def vmrglb_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), - (vector_shuffle node:$lhs, node:$rhs), [{ + (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, true); }]>; def vmrglh_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), diff --git a/lib/Target/PowerPC/PPCRegisterInfo.cpp b/lib/Target/PowerPC/PPCRegisterInfo.cpp index 0b509ac..31bca16 100644 --- a/lib/Target/PowerPC/PPCRegisterInfo.cpp +++ b/lib/Target/PowerPC/PPCRegisterInfo.cpp @@ -713,7 +713,7 @@ void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II, unsigned PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, - int SPAdj, int *Value, + int SPAdj, FrameIndexValue *Value, RegScavenger *RS) const { assert(SPAdj == 0 && "Unexpected"); diff --git a/lib/Target/PowerPC/PPCRegisterInfo.h b/lib/Target/PowerPC/PPCRegisterInfo.h index 3aeed80..43cf535 100644 --- a/lib/Target/PowerPC/PPCRegisterInfo.h +++ b/lib/Target/PowerPC/PPCRegisterInfo.h @@ -67,7 +67,7 @@ public: void lowerCRSpilling(MachineBasicBlock::iterator II, unsigned FrameIndex, int SPAdj, RegScavenger *RS) const; unsigned eliminateFrameIndex(MachineBasicBlock::iterator II, - int SPAdj, int *Value = NULL, + int SPAdj, FrameIndexValue *Value = NULL, RegScavenger *RS = NULL) const; /// determineFrameLayout - Determine the size of the frame and maximum call |
