1 files changed, 26 insertions, 2 deletions
diff --git a/lib/Target/Mips/MipsRegisterInfo.td b/lib/Target/Mips/MipsRegisterInfo.td
index bbb275c..00e7723 100644
--- a/lib/Target/Mips/MipsRegisterInfo.td
+++ b/lib/Target/Mips/MipsRegisterInfo.td
@@ -17,6 +17,12 @@ class MipsReg<string n> : Register<n> {
   let Namespace = "Mips";
 }
 
+class MipsRegWithSubRegs<string n, list<Register> subregs> 
+  : RegisterWithSubRegs<n, subregs> {
+  field bits<5> Num;
+  let Namespace = "Mips";
+}
+
 // Mips CPU Registers
 class MipsGPRReg<bits<5> num, string n> : MipsReg<n> {
   let Num = num;
@@ -28,9 +34,9 @@ class FPR<bits<5> num, string n> : MipsReg<n> {
 }
 
 // Mips 64-bit (aliased) FPU Registers
-class AFPR<bits<5> num, string n, list<Register> aliases> : MipsReg<n> {
+class AFPR<bits<5> num, string n, list<Register> subregs> 
+  : MipsRegWithSubRegs<n, subregs> {
   let Num = num;
-  let Aliases = aliases;
 }
 
 //===----------------------------------------------------------------------===//
@@ -135,6 +141,23 @@ let Namespace = "Mips" in {
 }
 
 //===----------------------------------------------------------------------===//
+// Subregister Set Definitions
+//===----------------------------------------------------------------------===//
+
+def mips_subreg_fpeven : PatLeaf<(i32 1)>;
+def mips_subreg_fpodd  : PatLeaf<(i32 2)>;
+
+def : SubRegSet<1, [D0, D1, D2, D3, D4, D5, D6, D7, 
+                    D8, D9, D10, D11, D12, D13, D14, D15],
+                   [F0, F2, F4, F6, F8, F10, F12, F14,
+                    F16, F18, F20, F22, F24, F26, F28, F30]>;
+
+def : SubRegSet<2, [D0, D1, D2, D3, D4, D5, D6, D7, 
+                    D8, D9, D10, D11, D12, D13, D14, D15],
+                   [F1, F3, F5, F7, F9, F11, F13, F15,
+                    F17, F19, F21, F23, F25, F27, F29, F31]>;
+
+//===----------------------------------------------------------------------===//
 // Register Classes
 //===----------------------------------------------------------------------===//
 
@@ -232,6 +255,7 @@ def AFGR64 : RegisterClass<"Mips", [f64], 64,
   // Reserved
   D15]>
 {
+  let SubRegClassList = [FGR32, FGR32];
   let MethodProtos = [{
     iterator allocation_order_end(const MachineFunction &MF) const;
   }];